Branch data Line data Source code
1 : : /* SPDX-License-Identifier: BSD-3-Clause
2 : : * Copyright 2018 Mellanox Technologies, Ltd
3 : : */
4 : :
5 : : #include <unistd.h>
6 : :
7 : : #include <eal_export.h>
8 : : #include <rte_errno.h>
9 : : #include <rte_malloc.h>
10 : : #include <rte_eal_paging.h>
11 : :
12 : : #include "mlx5_prm.h"
13 : : #include "mlx5_devx_cmds.h"
14 : : #include "mlx5_common_log.h"
15 : : #include "mlx5_malloc.h"
16 : :
17 : : /* FW writes status value to the OUT buffer at offset 00H */
18 : : #define MLX5_FW_STATUS(o) MLX5_GET(general_obj_out_cmd_hdr, (o), status)
19 : : /* FW writes syndrome value to the OUT buffer at offset 04H */
20 : : #define MLX5_FW_SYNDROME(o) MLX5_GET(general_obj_out_cmd_hdr, (o), syndrome)
21 : :
22 : : #define MLX5_DEVX_ERR_RC(x) ((x) > 0 ? -(x) : ((x) < 0 ? (x) : -1))
23 : :
24 : : #define DEVX_DRV_LOG(level, out, reason, param, value) \
25 : : do { \
26 : : /* \
27 : : * Some (old) GCC compilers like 7.5.0 and aarch64 GCC 7.1-2017.08 \
28 : : * do not expand correctly when the macro invoked when the `param` \
29 : : * is `NULL`. \
30 : : * Use `local_param` to avoid direct `NULL` expansion. \
31 : : */ \
32 : : const char *local_param = (const char *)param; \
33 : : \
34 : : rte_errno = errno; \
35 : : if (!local_param) { \
36 : : DRV_LOG(level, \
37 : : "DevX %s failed errno=%d status=%#x syndrome=%#x", \
38 : : (reason), errno, MLX5_FW_STATUS((out)), \
39 : : MLX5_FW_SYNDROME((out))); \
40 : : } else { \
41 : : DRV_LOG(level, \
42 : : "DevX %s %s=%#X failed errno=%d status=%#x syndrome=%#x",\
43 : : (reason), local_param, (value), errno, \
44 : : MLX5_FW_STATUS((out)), MLX5_FW_SYNDROME((out))); \
45 : : } \
46 : : } while (0)
47 : :
48 : : static void *
49 [ # # ]: 0 : mlx5_devx_get_hca_cap(void *ctx, uint32_t *in, uint32_t *out,
50 : : int *err, uint32_t flags)
51 : : {
52 : : const size_t size_in = MLX5_ST_SZ_DW(query_hca_cap_in) * sizeof(int);
53 : : const size_t size_out = MLX5_ST_SZ_DW(query_hca_cap_out) * sizeof(int);
54 : : int rc;
55 : :
56 : : memset(in, 0, size_in);
57 : : memset(out, 0, size_out);
58 [ # # ]: 0 : MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
59 [ # # ]: 0 : MLX5_SET(query_hca_cap_in, in, op_mod, flags);
60 : 0 : rc = mlx5_glue->devx_general_cmd(ctx, in, size_in, out, size_out);
61 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
62 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "HCA capabilities", "func", flags >> 1);
63 [ # # ]: 0 : if (err)
64 [ # # ]: 0 : *err = MLX5_DEVX_ERR_RC(rc);
65 : 0 : return NULL;
66 : : }
67 [ # # ]: 0 : if (err)
68 : 0 : *err = 0;
69 : 0 : return MLX5_ADDR_OF(query_hca_cap_out, out, capability);
70 : : }
71 : :
72 : : /**
73 : : * Perform read access to the registers. Reads data from register
74 : : * and writes ones to the specified buffer.
75 : : *
76 : : * @param[in] ctx
77 : : * Context returned from mlx5 open_device() glue function.
78 : : * @param[in] reg_id
79 : : * Register identifier according to the PRM.
80 : : * @param[in] arg
81 : : * Register access auxiliary parameter according to the PRM.
82 : : * @param[out] data
83 : : * Pointer to the buffer to store read data.
84 : : * @param[in] dw_cnt
85 : : * Buffer size in double words.
86 : : *
87 : : * @return
88 : : * 0 on success, a negative value otherwise.
89 : : */
90 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_register_read)
91 : : int
92 : 0 : mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg,
93 : : uint32_t *data, uint32_t dw_cnt)
94 : : {
95 : 0 : uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0};
96 : 0 : uint32_t out[MLX5_ST_SZ_DW(access_register_out) +
97 : : MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0};
98 : : int rc;
99 : :
100 : : MLX5_ASSERT(data && dw_cnt);
101 : : MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX);
102 [ # # ]: 0 : if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) {
103 : 0 : DRV_LOG(ERR, "Not enough buffer for register read data");
104 : 0 : return -1;
105 : : }
106 : 0 : MLX5_SET(access_register_in, in, opcode,
107 : : MLX5_CMD_OP_ACCESS_REGISTER_USER);
108 : 0 : MLX5_SET(access_register_in, in, op_mod,
109 : : MLX5_ACCESS_REGISTER_IN_OP_MOD_READ);
110 : 0 : MLX5_SET(access_register_in, in, register_id, reg_id);
111 : 0 : MLX5_SET(access_register_in, in, argument, arg);
112 : 0 : rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,
113 : 0 : MLX5_ST_SZ_BYTES(access_register_out) +
114 : : sizeof(uint32_t) * dw_cnt);
115 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
116 [ # # # # ]: 0 : DEVX_DRV_LOG(DEBUG, out, "read access", "NIC register", reg_id);
117 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
118 : : }
119 : 0 : memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)],
120 : : dw_cnt * sizeof(uint32_t));
121 : 0 : return 0;
122 : : }
123 : :
124 : : /**
125 : : * Perform write access to the registers.
126 : : *
127 : : * @param[in] ctx
128 : : * Context returned from mlx5 open_device() glue function.
129 : : * @param[in] reg_id
130 : : * Register identifier according to the PRM.
131 : : * @param[in] arg
132 : : * Register access auxiliary parameter according to the PRM.
133 : : * @param[out] data
134 : : * Pointer to the buffer containing data to write.
135 : : * @param[in] dw_cnt
136 : : * Buffer size in double words (32bit units).
137 : : *
138 : : * @return
139 : : * 0 on success, a negative value otherwise.
140 : : */
141 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_register_write)
142 : : int
143 : 0 : mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, uint32_t arg,
144 : : uint32_t *data, uint32_t dw_cnt)
145 : : {
146 : 0 : uint32_t in[MLX5_ST_SZ_DW(access_register_in) +
147 : : MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0};
148 : 0 : uint32_t out[MLX5_ST_SZ_DW(access_register_out)] = {0};
149 : : int rc;
150 : : void *ptr;
151 : :
152 : : MLX5_ASSERT(data && dw_cnt);
153 : : MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX);
154 [ # # ]: 0 : if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) {
155 : 0 : DRV_LOG(ERR, "Data to write exceeds max size");
156 : 0 : return -1;
157 : : }
158 : 0 : MLX5_SET(access_register_in, in, opcode,
159 : : MLX5_CMD_OP_ACCESS_REGISTER_USER);
160 : 0 : MLX5_SET(access_register_in, in, op_mod,
161 : : MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE);
162 : 0 : MLX5_SET(access_register_in, in, register_id, reg_id);
163 : 0 : MLX5_SET(access_register_in, in, argument, arg);
164 : : ptr = MLX5_ADDR_OF(access_register_in, in, register_data);
165 : 0 : memcpy(ptr, data, dw_cnt * sizeof(uint32_t));
166 : 0 : rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
167 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
168 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "write access", "NIC register", reg_id);
169 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
170 : : }
171 : 0 : rc = mlx5_glue->devx_general_cmd(ctx, in,
172 : 0 : MLX5_ST_SZ_BYTES(access_register_in) +
173 : : dw_cnt * sizeof(uint32_t),
174 : : out, sizeof(out));
175 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
176 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "write access", "NIC register", reg_id);
177 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
178 : : }
179 : : return 0;
180 : : }
181 : :
182 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_flow_counter_alloc_general)
183 : : struct mlx5_devx_obj *
184 : 0 : mlx5_devx_cmd_flow_counter_alloc_general(void *ctx,
185 : : struct mlx5_devx_counter_attr *attr)
186 : : {
187 : 0 : struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs),
188 : : 0, SOCKET_ID_ANY);
189 : 0 : uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0};
190 : 0 : uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0};
191 : :
192 [ # # ]: 0 : if (!dcs) {
193 : 0 : rte_errno = ENOMEM;
194 : 0 : return NULL;
195 : : }
196 : 0 : MLX5_SET(alloc_flow_counter_in, in, opcode,
197 : : MLX5_CMD_OP_ALLOC_FLOW_COUNTER);
198 [ # # ]: 0 : if (attr->bulk_log_max_alloc)
199 : 0 : MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk_log_size,
200 : : attr->flow_counter_bulk_log_size);
201 : : else
202 : 0 : MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk,
203 : : attr->bulk_n_128);
204 [ # # ]: 0 : if (attr->pd_valid)
205 : 0 : MLX5_SET(alloc_flow_counter_in, in, pd, attr->pd);
206 : 0 : dcs->obj = mlx5_glue->devx_obj_create(ctx, in,
207 : : sizeof(in), out, sizeof(out));
208 [ # # ]: 0 : if (!dcs->obj) {
209 : 0 : DRV_LOG(ERR, "Can't allocate counters - error %d", errno);
210 : 0 : rte_errno = errno;
211 : 0 : mlx5_free(dcs);
212 : 0 : return NULL;
213 : : }
214 [ # # ]: 0 : dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id);
215 : 0 : return dcs;
216 : : }
217 : :
218 : : /**
219 : : * Allocate flow counters via devx interface.
220 : : *
221 : : * @param[in] ctx
222 : : * Context returned from mlx5 open_device() glue function.
223 : : * @param dcs
224 : : * Pointer to counters properties structure to be filled by the routine.
225 : : * @param bulk_n_128
226 : : * Bulk counter numbers in 128 counters units.
227 : : *
228 : : * @return
229 : : * Pointer to counter object on success, a negative value otherwise and
230 : : * rte_errno is set.
231 : : */
232 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_flow_counter_alloc)
233 : : struct mlx5_devx_obj *
234 : 0 : mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128)
235 : : {
236 : 0 : struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs),
237 : : 0, SOCKET_ID_ANY);
238 : 0 : uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0};
239 : 0 : uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0};
240 : :
241 [ # # ]: 0 : if (!dcs) {
242 : 0 : rte_errno = ENOMEM;
243 : 0 : return NULL;
244 : : }
245 : 0 : MLX5_SET(alloc_flow_counter_in, in, opcode,
246 : : MLX5_CMD_OP_ALLOC_FLOW_COUNTER);
247 : 0 : MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128);
248 : 0 : dcs->obj = mlx5_glue->devx_obj_create(ctx, in,
249 : : sizeof(in), out, sizeof(out));
250 [ # # ]: 0 : if (!dcs->obj) {
251 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "allocate counters", NULL, 0);
252 : 0 : mlx5_free(dcs);
253 : 0 : return NULL;
254 : : }
255 [ # # ]: 0 : dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id);
256 : 0 : return dcs;
257 : : }
258 : :
259 : : /**
260 : : * Query flow counters values.
261 : : *
262 : : * @param[in] dcs
263 : : * devx object that was obtained from mlx5_devx_cmd_fc_alloc.
264 : : * @param[in] clear
265 : : * Whether hardware should clear the counters after the query or not.
266 : : * @param[in] n_counters
267 : : * 0 in case of 1 counter to read, otherwise the counter number to read.
268 : : * @param pkts
269 : : * The number of packets that matched the flow.
270 : : * @param bytes
271 : : * The number of bytes that matched the flow.
272 : : * @param mkey
273 : : * The mkey key for batch query.
274 : : * @param addr
275 : : * The address in the mkey range for batch query.
276 : : * @param cmd_comp
277 : : * The completion object for asynchronous batch query.
278 : : * @param async_id
279 : : * The ID to be returned in the asynchronous batch query response.
280 : : *
281 : : * @return
282 : : * 0 on success, a negative value otherwise.
283 : : */
284 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_flow_counter_query)
285 : : int
286 : 0 : mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
287 : : int clear, uint32_t n_counters,
288 : : uint64_t *pkts, uint64_t *bytes,
289 : : uint32_t mkey, void *addr,
290 : : void *cmd_comp,
291 : : uint64_t async_id)
292 : : {
293 : : uint32_t out[MLX5_ST_SZ_BYTES(query_flow_counter_out) + MLX5_ST_SZ_BYTES(traffic_counter)];
294 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0};
295 : : const int out_len = RTE_DIM(out);
296 : : void *stats;
297 : : int rc;
298 : :
299 : 0 : MLX5_SET(query_flow_counter_in, in, opcode,
300 : : MLX5_CMD_OP_QUERY_FLOW_COUNTER);
301 : 0 : MLX5_SET(query_flow_counter_in, in, op_mod, 0);
302 : 0 : MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id);
303 : 0 : MLX5_SET(query_flow_counter_in, in, clear, !!clear);
304 : :
305 [ # # ]: 0 : if (n_counters) {
306 [ # # ]: 0 : MLX5_SET(query_flow_counter_in, in, num_of_counters,
307 : : n_counters);
308 [ # # ]: 0 : MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1);
309 : 0 : MLX5_SET(query_flow_counter_in, in, mkey, mkey);
310 : 0 : MLX5_SET64(query_flow_counter_in, in, address,
311 : : (uint64_t)(uintptr_t)addr);
312 : : }
313 [ # # ]: 0 : if (!cmd_comp)
314 : 0 : rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
315 : : out_len);
316 : : else
317 : 0 : rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in),
318 : : out_len, async_id,
319 : : cmd_comp);
320 [ # # ]: 0 : if (rc) {
321 : 0 : DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc);
322 : 0 : rte_errno = rc;
323 : 0 : return -rc;
324 : : }
325 [ # # ]: 0 : if (!n_counters) {
326 : : stats = MLX5_ADDR_OF(query_flow_counter_out,
327 : : out, flow_statistics);
328 [ # # ]: 0 : *pkts = MLX5_GET64(traffic_counter, stats, packets);
329 [ # # ]: 0 : *bytes = MLX5_GET64(traffic_counter, stats, octets);
330 : : }
331 : : return 0;
332 : : }
333 : :
334 : : /**
335 : : * Apply PCI relaxed-ordering and read-after-write ordering to mkey attributes.
336 : : *
337 : : * @param[in, out] mkey_attr
338 : : * Mkey attributes to update.
339 : : * @param[in] hca_attr
340 : : * HCA capabilities from mlx5_devx_cmd_query_hca_attr().
341 : : */
342 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_mkey_attr_set_ordering)
343 : : void
344 : 0 : mlx5_devx_mkey_attr_set_ordering(struct mlx5_devx_mkey_attr *mkey_attr,
345 : : const struct mlx5_hca_attr *hca_attr)
346 : : {
347 [ # # ]: 0 : if (!mkey_attr || !hca_attr)
348 : : return;
349 : :
350 : 0 : mkey_attr->relaxed_ordering_write = hca_attr->relaxed_ordering_write;
351 : 0 : mkey_attr->relaxed_ordering_read =
352 : 0 : hca_attr->relaxed_ordering_read || hca_attr->pci_relaxed_ordered_read;
353 [ # # ]: 0 : if (hca_attr->mkc_order_read_after_write)
354 : 0 : mkey_attr->read_after_write_ordering = MLX5_MKC_RAW_ORDERING_RO;
355 : : }
356 : :
357 : : /**
358 : : * Create a new mkey.
359 : : *
360 : : * @param[in] ctx
361 : : * Context returned from mlx5 open_device() glue function.
362 : : * @param[in] attr
363 : : * Attributes of the requested mkey.
364 : : *
365 : : * @return
366 : : * Pointer to Devx mkey on success, a negative value otherwise and rte_errno
367 : : * is set.
368 : : */
369 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_mkey_create)
370 : : struct mlx5_devx_obj *
371 : 0 : mlx5_devx_cmd_mkey_create(void *ctx,
372 : : struct mlx5_devx_mkey_attr *attr)
373 : : {
374 : 0 : struct mlx5_klm *klm_array = attr->klm_array;
375 : 0 : int klm_num = attr->klm_num;
376 [ # # ]: 0 : int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) +
377 : 0 : (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm);
378 : 0 : uint32_t *in = alloca(sizeof(uint32_t) * in_size_dw);
379 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0};
380 : : void *mkc;
381 : 0 : struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey),
382 : : 0, SOCKET_ID_ANY);
383 : : size_t pgsize;
384 : : uint32_t translation_size;
385 : :
386 [ # # ]: 0 : if (!mkey) {
387 : 0 : rte_errno = ENOMEM;
388 : 0 : return NULL;
389 : : }
390 : : memset(in, 0, in_size_dw * 4);
391 : 0 : pgsize = rte_mem_page_size();
392 [ # # ]: 0 : if (pgsize == (size_t)-1) {
393 : 0 : mlx5_free(mkey);
394 : 0 : DRV_LOG(ERR, "Failed to get page size");
395 : 0 : rte_errno = ENOMEM;
396 : 0 : return NULL;
397 : : }
398 [ # # ]: 0 : MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY);
399 : : mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
400 [ # # ]: 0 : if (klm_num > 0) {
401 : : int i;
402 : 0 : uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in,
403 : : klm_pas_mtt);
404 : 0 : translation_size = RTE_ALIGN(klm_num, 4);
405 [ # # ]: 0 : for (i = 0; i < klm_num; i++) {
406 [ # # ]: 0 : MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count);
407 [ # # ]: 0 : MLX5_SET(klm, klm, mkey, klm_array[i].mkey);
408 [ # # ]: 0 : MLX5_SET64(klm, klm, address, klm_array[i].address);
409 : 0 : klm += MLX5_ST_SZ_BYTES(klm);
410 : : }
411 [ # # ]: 0 : for (; i < (int)translation_size; i++) {
412 [ # # ]: 0 : MLX5_SET(klm, klm, mkey, 0x0);
413 : 0 : MLX5_SET64(klm, klm, address, 0x0);
414 : 0 : klm += MLX5_ST_SZ_BYTES(klm);
415 : : }
416 [ # # # # ]: 0 : MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ?
417 : : MLX5_MKC_ACCESS_MODE_KLM_FBS :
418 : : MLX5_MKC_ACCESS_MODE_KLM);
419 [ # # ]: 0 : MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size);
420 : : } else {
421 : 0 : translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16;
422 [ # # ]: 0 : MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
423 [ # # # # ]: 0 : MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize));
424 : : }
425 [ # # ]: 0 : MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
426 : : translation_size);
427 [ # # ]: 0 : MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id);
428 [ # # ]: 0 : MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access);
429 [ # # ]: 0 : MLX5_SET(mkc, mkc, lw, 0x1);
430 [ # # ]: 0 : MLX5_SET(mkc, mkc, lr, 0x1);
431 [ # # ]: 0 : if (attr->set_remote_rw) {
432 [ # # ]: 0 : MLX5_SET(mkc, mkc, rw, 0x1);
433 [ # # ]: 0 : MLX5_SET(mkc, mkc, rr, 0x1);
434 : : }
435 [ # # ]: 0 : MLX5_SET(mkc, mkc, qpn, 0xffffff);
436 [ # # ]: 0 : MLX5_SET(mkc, mkc, pd, attr->pd);
437 [ # # ]: 0 : MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF);
438 [ # # ]: 0 : MLX5_SET(mkc, mkc, umr_en, attr->umr_en);
439 [ # # ]: 0 : MLX5_SET(mkc, mkc, translations_octword_size, translation_size);
440 [ # # ]: 0 : MLX5_SET(mkc, mkc, relaxed_ordering_write,
441 : : attr->relaxed_ordering_write);
442 [ # # ]: 0 : MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read);
443 [ # # ]: 0 : MLX5_SET(mkc, mkc, order_read_after_write,
444 : : attr->read_after_write_ordering);
445 [ # # ]: 0 : MLX5_SET64(mkc, mkc, start_addr, attr->addr);
446 [ # # ]: 0 : MLX5_SET64(mkc, mkc, len, attr->size);
447 [ # # ]: 0 : MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en);
448 [ # # ]: 0 : if (attr->crypto_en) {
449 [ # # ]: 0 : MLX5_SET(mkc, mkc, bsf_en, attr->crypto_en);
450 [ # # ]: 0 : MLX5_SET(mkc, mkc, bsf_octword_size, 4);
451 : : }
452 : 0 : mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out,
453 : : sizeof(out));
454 [ # # ]: 0 : if (!mkey->obj) {
455 [ # # # # : 0 : DEVX_DRV_LOG(ERR, out, klm_num ? "create indirect mkey"
# # ]
456 : : : "create direct key", NULL, 0);
457 : 0 : mlx5_free(mkey);
458 : 0 : return NULL;
459 : : }
460 [ # # ]: 0 : mkey->id = MLX5_GET(create_mkey_out, out, mkey_index);
461 : 0 : mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF);
462 : 0 : return mkey;
463 : : }
464 : :
465 : : /**
466 : : * Get status of devx command response.
467 : : * Mainly used for asynchronous commands.
468 : : *
469 : : * @param[in] out
470 : : * The out response buffer.
471 : : *
472 : : * @return
473 : : * 0 on success, non-zero value otherwise.
474 : : */
475 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_get_out_command_status)
476 : : int
477 : 0 : mlx5_devx_get_out_command_status(void *out)
478 : : {
479 : : int status;
480 : :
481 [ # # ]: 0 : if (!out)
482 : : return -EINVAL;
483 [ # # ]: 0 : status = MLX5_GET(query_flow_counter_out, out, status);
484 [ # # ]: 0 : if (status) {
485 [ # # ]: 0 : int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome);
486 : :
487 : 0 : DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status,
488 : : syndrome);
489 : : }
490 : : return status;
491 : : }
492 : :
493 : : /**
494 : : * Destroy any object allocated by a Devx API.
495 : : *
496 : : * @param[in] obj
497 : : * Pointer to a general object.
498 : : *
499 : : * @return
500 : : * 0 on success, a negative value otherwise.
501 : : */
502 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_destroy)
503 : : int
504 : 0 : mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj)
505 : : {
506 : : int ret;
507 : :
508 [ # # ]: 0 : if (!obj)
509 : : return 0;
510 : 0 : ret = mlx5_glue->devx_obj_destroy(obj->obj);
511 : 0 : mlx5_free(obj);
512 : 0 : return ret;
513 : : }
514 : :
515 : : static int
516 : 0 : mlx5_devx_cmd_query_esw_vport_context(void *ctx,
517 : : struct mlx5_hca_attr *attr)
518 : : {
519 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_esw_vport_context_in)] = {0};
520 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_esw_vport_context_out)] = {0};
521 : : void *vctx;
522 : : int rc;
523 : :
524 : 0 : MLX5_SET(query_esw_vport_context_in, in, opcode, MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT);
525 : 0 : rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
526 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
527 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "query ESW vport context", NULL, 0);
528 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
529 : : }
530 : : vctx = MLX5_ADDR_OF(query_esw_vport_context_out, out, esw_vport_context);
531 [ # # ]: 0 : attr->fdb_to_vport_reg_c = MLX5_GET(esw_vport_context, vctx, fdb_to_vport_reg_c);
532 [ # # ]: 0 : if (attr->fdb_to_vport_reg_c != 0) {
533 : 0 : attr->vport_to_fdb_metadata =
534 [ # # ]: 0 : MLX5_GET(esw_vport_context, vctx, vport_to_fdb_metadata);
535 : 0 : attr->fdb_to_vport_metadata =
536 [ # # ]: 0 : MLX5_GET(esw_vport_context, vctx, fdb_to_vport_metadata);
537 [ # # ]: 0 : attr->fdb_to_vport_reg_c_id =
538 : 0 : MLX5_GET(esw_vport_context, vctx, fdb_to_vport_reg_c_id);
539 : : }
540 : : return 0;
541 : : }
542 : :
543 : : /**
544 : : * Query NIC vport context.
545 : : * Fills minimal inline attribute.
546 : : *
547 : : * @param[in] ctx
548 : : * ibv contexts returned from mlx5dv_open_device.
549 : : * @param[in] vport
550 : : * vport index
551 : : * @param[out] attr
552 : : * Attributes device values.
553 : : *
554 : : * @return
555 : : * 0 on success, a negative value otherwise.
556 : : */
557 : : static int
558 : 0 : mlx5_devx_cmd_query_nic_vport_context(void *ctx,
559 : : unsigned int vport,
560 : : struct mlx5_hca_attr *attr)
561 : : {
562 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0};
563 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0};
564 : : void *vctx;
565 : : int rc;
566 : :
567 : : /* Query NIC vport context to determine inline mode. */
568 : 0 : MLX5_SET(query_nic_vport_context_in, in, opcode,
569 : : MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT);
570 : 0 : MLX5_SET(query_nic_vport_context_in, in, vport_number, vport);
571 [ # # ]: 0 : if (vport)
572 [ # # ]: 0 : MLX5_SET(query_nic_vport_context_in, in, other_vport, 1);
573 : 0 : rc = mlx5_glue->devx_general_cmd(ctx,
574 : : in, sizeof(in),
575 : : out, sizeof(out));
576 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
577 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "query NIC vport context", NULL, 0);
578 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
579 : : }
580 : : vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out,
581 : : nic_vport_context);
582 [ # # ]: 0 : if (attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
583 [ # # ]: 0 : attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx,
584 : : min_wqe_inline_mode);
585 [ # # ]: 0 : attr->system_image_guid = MLX5_GET64(nic_vport_context, vctx,
586 : : system_image_guid);
587 [ # # ]: 0 : attr->vport_to_fdb_metadata = MLX5_GET(nic_vport_context, vctx, vport_to_fdb_metadata);
588 [ # # ]: 0 : attr->fdb_to_vport_metadata = MLX5_GET(nic_vport_context, vctx, fdb_to_vport_metadata);
589 : 0 : return 0;
590 : : }
591 : :
592 : : /**
593 : : * Query NIC vDPA attributes.
594 : : *
595 : : * @param[in] ctx
596 : : * Context returned from mlx5 open_device() glue function.
597 : : * @param[out] vdpa_attr
598 : : * vDPA Attributes structure to fill.
599 : : */
600 : : static void
601 : 0 : mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx,
602 : : struct mlx5_hca_vdpa_attr *vdpa_attr)
603 : : {
604 : : uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)];
605 : : uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)];
606 : : void *hcattr;
607 : :
608 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, NULL,
609 : : MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION |
610 : : (uint32_t)MLX5_HCA_CAP_OPMOD_GET_CUR);
611 [ # # ]: 0 : if (!hcattr) {
612 : 0 : DRV_LOG(DEBUG, "Failed to query devx VDPA capabilities");
613 : 0 : vdpa_attr->valid = 0;
614 : : } else {
615 : 0 : vdpa_attr->valid = 1;
616 : 0 : vdpa_attr->desc_tunnel_offload_type =
617 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
618 : : desc_tunnel_offload_type);
619 : 0 : vdpa_attr->eth_frame_offload_type =
620 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
621 : : eth_frame_offload_type);
622 : 0 : vdpa_attr->virtio_version_1_0 =
623 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
624 : : virtio_version_1_0);
625 [ # # ]: 0 : vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr,
626 : : tso_ipv4);
627 [ # # ]: 0 : vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr,
628 : : tso_ipv6);
629 [ # # ]: 0 : vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
630 : : tx_csum);
631 [ # # ]: 0 : vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
632 : : rx_csum);
633 [ # # ]: 0 : vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr,
634 : : event_mode);
635 : 0 : vdpa_attr->virtio_queue_type =
636 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
637 : : virtio_queue_type);
638 : 0 : vdpa_attr->log_doorbell_stride =
639 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
640 : : log_doorbell_stride);
641 : 0 : vdpa_attr->vnet_modify_ext =
642 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
643 : : vnet_modify_ext);
644 : 0 : vdpa_attr->virtio_net_q_addr_modify =
645 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
646 : : virtio_net_q_addr_modify);
647 : 0 : vdpa_attr->virtio_q_index_modify =
648 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
649 : : virtio_q_index_modify);
650 : 0 : vdpa_attr->log_doorbell_bar_size =
651 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
652 : : log_doorbell_bar_size);
653 : 0 : vdpa_attr->doorbell_bar_offset =
654 [ # # ]: 0 : MLX5_GET64(virtio_emulation_cap, hcattr,
655 : : doorbell_bar_offset);
656 : 0 : vdpa_attr->max_num_virtio_queues =
657 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
658 : : max_num_virtio_queues);
659 [ # # ]: 0 : vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr,
660 : : umem_1_buffer_param_a);
661 [ # # ]: 0 : vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr,
662 : : umem_1_buffer_param_b);
663 [ # # ]: 0 : vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr,
664 : : umem_2_buffer_param_a);
665 [ # # ]: 0 : vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr,
666 : : umem_2_buffer_param_b);
667 [ # # ]: 0 : vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr,
668 : : umem_3_buffer_param_a);
669 [ # # ]: 0 : vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr,
670 : : umem_3_buffer_param_b);
671 : : }
672 : 0 : }
673 : :
674 : : /**
675 : : * Query match sample handle parameters.
676 : : *
677 : : * This command allows translating a field sample handle returned by either
678 : : * PARSE_GRAPH_FLOW_MATCH_SAMPLE or by GENEVE TLV OPTION object into values
679 : : * used for header modification or header matching/hashing.
680 : : *
681 : : * @param[in] ctx
682 : : * Context used to create either GENEVE TLV option or FLEX PARSE GRAPH object.
683 : : * @param[in] sample_field_id
684 : : * Field sample handle returned by either PARSE_GRAPH_FLOW_MATCH_SAMPLE
685 : : * or by GENEVE TLV OPTION object.
686 : : * @param[out] attr
687 : : * Pointer to match sample info attributes structure.
688 : : *
689 : : * @return
690 : : * 0 on success, a negative errno otherwise and rte_errno is set.
691 : : */
692 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_match_sample_info_query)
693 : : int
694 : 0 : mlx5_devx_cmd_match_sample_info_query(void *ctx, uint32_t sample_field_id,
695 : : struct mlx5_devx_match_sample_info_query_attr *attr)
696 : : {
697 : : #ifdef HAVE_IBV_FLOW_DV_SUPPORT
698 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_match_sample_info_out)] = {0};
699 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_match_sample_info_in)] = {0};
700 : : int rc;
701 : :
702 : 0 : MLX5_SET(query_match_sample_info_in, in, opcode,
703 : : MLX5_CMD_OP_QUERY_MATCH_SAMPLE_INFO);
704 : 0 : MLX5_SET(query_match_sample_info_in, in, op_mod, 0);
705 : 0 : MLX5_SET(query_match_sample_info_in, in, sample_field_id,
706 : : sample_field_id);
707 : 0 : rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
708 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
709 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "query match sample info",
710 : : "sample_field_id", sample_field_id);
711 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
712 : : }
713 [ # # ]: 0 : attr->modify_field_id = MLX5_GET(query_match_sample_info_out, out,
714 : : modify_field_id);
715 [ # # ]: 0 : attr->sample_dw_data = MLX5_GET(query_match_sample_info_out, out,
716 : : field_format_select_dw);
717 [ # # ]: 0 : attr->sample_dw_ok_bit = MLX5_GET(query_match_sample_info_out, out,
718 : : ok_bit_format_select_dw);
719 [ # # ]: 0 : attr->sample_dw_ok_bit_offset = MLX5_GET(query_match_sample_info_out,
720 : : out, ok_bit_offset);
721 : 0 : return 0;
722 : : #else
723 : : (void)ctx;
724 : : (void)sample_field_id;
725 : : (void)attr;
726 : : return -ENOTSUP;
727 : : #endif
728 : : }
729 : :
730 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_query_parse_samples)
731 : : int
732 : 0 : mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,
733 : : uint32_t *ids,
734 : : uint32_t num, uint8_t *anchor)
735 : : {
736 : 0 : uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
737 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0};
738 : : void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr);
739 : : void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex);
740 : : void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
741 : : int ret;
742 : : uint32_t idx = 0;
743 : : uint32_t i;
744 : :
745 [ # # ]: 0 : if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) {
746 : 0 : rte_errno = EINVAL;
747 : 0 : DRV_LOG(ERR, "Too many sample IDs to be fetched.");
748 : 0 : return -rte_errno;
749 : : }
750 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
751 : : MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
752 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
753 : : MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
754 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id);
755 : 0 : ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in),
756 : : out, sizeof(out));
757 [ # # ]: 0 : if (ret) {
758 : 0 : rte_errno = ret;
759 : 0 : DRV_LOG(ERR, "Failed to query sample IDs with object %p.",
760 : : (void *)flex_obj);
761 : 0 : return -rte_errno;
762 : : }
763 [ # # ]: 0 : if (anchor)
764 [ # # ]: 0 : *anchor = MLX5_GET(parse_graph_flex, flex, head_anchor_id);
765 [ # # ]: 0 : for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM && idx < num; i++) {
766 : 0 : void *s_off = (void *)((char *)sample + i *
767 : : MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
768 : : uint32_t en;
769 : :
770 [ # # ]: 0 : en = MLX5_GET(parse_graph_flow_match_sample, s_off,
771 : : flow_match_sample_en);
772 [ # # ]: 0 : if (!en)
773 : 0 : continue;
774 [ # # ]: 0 : ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off,
775 : : flow_match_sample_field_id);
776 : : }
777 [ # # ]: 0 : if (num != idx) {
778 : 0 : rte_errno = EINVAL;
779 : 0 : DRV_LOG(ERR, "Number of sample IDs are not as expected.");
780 : 0 : return -rte_errno;
781 : : }
782 : : return ret;
783 : : }
784 : :
785 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_flex_parser)
786 : : struct mlx5_devx_obj *
787 : 0 : mlx5_devx_cmd_create_flex_parser(void *ctx,
788 : : struct mlx5_devx_graph_node_attr *data)
789 : : {
790 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0};
791 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
792 : : void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr);
793 : : void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex);
794 : : void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
795 : : void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc);
796 : : void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc);
797 : 0 : struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc
798 : : (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY);
799 : : uint32_t i;
800 : :
801 [ # # ]: 0 : if (!parse_flex_obj) {
802 : 0 : DRV_LOG(ERR, "Failed to allocate flex parser data.");
803 : 0 : rte_errno = ENOMEM;
804 : 0 : return NULL;
805 : : }
806 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
807 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
808 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
809 : : MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
810 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, header_length_mode,
811 : : data->header_length_mode);
812 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, header_length_field_offset_mode,
813 : : data->header_length_field_offset_mode);
814 [ # # ]: 0 : MLX5_SET64(parse_graph_flex, flex, modify_field_select,
815 : : data->modify_field_select);
816 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, header_length_base_value,
817 : : data->header_length_base_value);
818 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, header_length_field_offset,
819 : : data->header_length_field_offset);
820 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, header_length_field_shift,
821 : : data->header_length_field_shift);
822 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, next_header_field_offset,
823 : : data->next_header_field_offset);
824 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, next_header_field_size,
825 : : data->next_header_field_size);
826 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, header_length_field_mask,
827 : : data->header_length_field_mask);
828 [ # # ]: 0 : for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {
829 : : struct mlx5_devx_match_sample_attr *s = &data->sample[i];
830 : 0 : void *s_off = (void *)((char *)sample + i *
831 : : MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
832 : :
833 [ # # ]: 0 : if (!s->flow_match_sample_en)
834 : 0 : continue;
835 [ # # ]: 0 : MLX5_SET(parse_graph_flow_match_sample, s_off,
836 : : flow_match_sample_en, !!s->flow_match_sample_en);
837 [ # # ]: 0 : MLX5_SET(parse_graph_flow_match_sample, s_off,
838 : : flow_match_sample_field_offset,
839 : : s->flow_match_sample_field_offset);
840 [ # # ]: 0 : MLX5_SET(parse_graph_flow_match_sample, s_off,
841 : : flow_match_sample_offset_mode,
842 : : s->flow_match_sample_offset_mode);
843 [ # # ]: 0 : MLX5_SET(parse_graph_flow_match_sample, s_off,
844 : : flow_match_sample_field_offset_mask,
845 : : s->flow_match_sample_field_offset_mask);
846 [ # # ]: 0 : MLX5_SET(parse_graph_flow_match_sample, s_off,
847 : : flow_match_sample_field_offset_shift,
848 : : s->flow_match_sample_field_offset_shift);
849 [ # # ]: 0 : MLX5_SET(parse_graph_flow_match_sample, s_off,
850 : : flow_match_sample_field_base_offset,
851 : : s->flow_match_sample_field_base_offset);
852 [ # # ]: 0 : MLX5_SET(parse_graph_flow_match_sample, s_off,
853 : : flow_match_sample_tunnel_mode,
854 : : s->flow_match_sample_tunnel_mode);
855 : : }
856 [ # # ]: 0 : for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) {
857 : : struct mlx5_devx_graph_arc_attr *ia = &data->in[i];
858 : : struct mlx5_devx_graph_arc_attr *oa = &data->out[i];
859 : 0 : void *in_off = (void *)((char *)in_arc + i *
860 : : MLX5_ST_SZ_BYTES(parse_graph_arc));
861 : 0 : void *out_off = (void *)((char *)out_arc + i *
862 : : MLX5_ST_SZ_BYTES(parse_graph_arc));
863 : :
864 [ # # ]: 0 : if (ia->arc_parse_graph_node != 0) {
865 [ # # ]: 0 : MLX5_SET(parse_graph_arc, in_off,
866 : : compare_condition_value,
867 : : ia->compare_condition_value);
868 [ # # ]: 0 : MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel,
869 : : ia->start_inner_tunnel);
870 [ # # ]: 0 : MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node,
871 : : ia->arc_parse_graph_node);
872 [ # # ]: 0 : MLX5_SET(parse_graph_arc, in_off,
873 : : parse_graph_node_handle,
874 : : ia->parse_graph_node_handle);
875 : : }
876 [ # # ]: 0 : if (oa->arc_parse_graph_node != 0) {
877 [ # # ]: 0 : MLX5_SET(parse_graph_arc, out_off,
878 : : compare_condition_value,
879 : : oa->compare_condition_value);
880 [ # # ]: 0 : MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel,
881 : : oa->start_inner_tunnel);
882 [ # # ]: 0 : MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node,
883 : : oa->arc_parse_graph_node);
884 [ # # ]: 0 : MLX5_SET(parse_graph_arc, out_off,
885 : : parse_graph_node_handle,
886 : : oa->parse_graph_node_handle);
887 : : }
888 : : }
889 : 0 : parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
890 : : out, sizeof(out));
891 [ # # ]: 0 : if (!parse_flex_obj->obj) {
892 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create FLEX PARSE GRAPH", NULL, 0);
893 : 0 : mlx5_free(parse_flex_obj);
894 : 0 : return NULL;
895 : : }
896 [ # # ]: 0 : parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
897 : 0 : return parse_flex_obj;
898 : : }
899 : :
900 : : static int
901 : 0 : mlx5_devx_cmd_query_hca_parse_graph_node_cap
902 : : (void *ctx, struct mlx5_hca_flex_attr *attr)
903 : : {
904 : : uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)];
905 : : uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)];
906 : : void *hcattr;
907 : : int rc;
908 : :
909 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
910 : : MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP |
911 : : (uint32_t)MLX5_HCA_CAP_OPMOD_GET_CUR);
912 [ # # ]: 0 : if (!hcattr)
913 : 0 : return rc;
914 [ # # ]: 0 : attr->node_in = MLX5_GET(parse_graph_node_cap, hcattr, node_in);
915 [ # # ]: 0 : attr->node_out = MLX5_GET(parse_graph_node_cap, hcattr, node_out);
916 [ # # ]: 0 : attr->header_length_mode = MLX5_GET(parse_graph_node_cap, hcattr,
917 : : header_length_mode);
918 [ # # ]: 0 : attr->sample_offset_mode = MLX5_GET(parse_graph_node_cap, hcattr,
919 : : sample_offset_mode);
920 [ # # ]: 0 : attr->max_num_arc_in = MLX5_GET(parse_graph_node_cap, hcattr,
921 : : max_num_arc_in);
922 [ # # ]: 0 : attr->max_num_arc_out = MLX5_GET(parse_graph_node_cap, hcattr,
923 : : max_num_arc_out);
924 [ # # ]: 0 : attr->max_num_sample = MLX5_GET(parse_graph_node_cap, hcattr,
925 : : max_num_sample);
926 [ # # ]: 0 : attr->parse_graph_anchor = MLX5_GET(parse_graph_node_cap, hcattr, parse_graph_anchor);
927 [ # # ]: 0 : attr->sample_tunnel_inner2 = MLX5_GET(parse_graph_node_cap, hcattr,
928 : : sample_tunnel_inner2);
929 [ # # ]: 0 : attr->zero_size_supported = MLX5_GET(parse_graph_node_cap, hcattr,
930 : : zero_size_supported);
931 [ # # ]: 0 : attr->sample_id_in_out = MLX5_GET(parse_graph_node_cap, hcattr,
932 : : sample_id_in_out);
933 [ # # ]: 0 : attr->max_base_header_length = MLX5_GET(parse_graph_node_cap, hcattr,
934 : : max_base_header_length);
935 [ # # ]: 0 : attr->max_sample_base_offset = MLX5_GET(parse_graph_node_cap, hcattr,
936 : : max_sample_base_offset);
937 [ # # ]: 0 : attr->max_next_header_offset = MLX5_GET(parse_graph_node_cap, hcattr,
938 : : max_next_header_offset);
939 [ # # ]: 0 : attr->header_length_mask_width = MLX5_GET(parse_graph_node_cap, hcattr,
940 : : header_length_mask_width);
941 [ # # ]: 0 : attr->header_length_field_mode_wa = !MLX5_GET(parse_graph_node_cap, hcattr,
942 : : header_length_field_offset_mode);
943 : : /* Get the max supported samples from HCA CAP 2 */
944 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
945 : : MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 |
946 : : (uint32_t)MLX5_HCA_CAP_OPMOD_GET_CUR);
947 [ # # ]: 0 : if (!hcattr)
948 : 0 : return rc;
949 : 0 : attr->max_num_prog_sample =
950 [ # # ]: 0 : MLX5_GET(cmd_hca_cap_2, hcattr, max_num_prog_sample_field);
951 : 0 : return 0;
952 : : }
953 : :
954 : : static int
955 : 0 : mlx5_devx_query_pkt_integrity_match(void *hcattr)
956 : : {
957 [ # # ]: 0 : return MLX5_GET(flow_table_nic_cap, hcattr,
958 [ # # # # ]: 0 : ft_field_support_2_nic_receive.inner_l3_ok) &&
959 : : MLX5_GET(flow_table_nic_cap, hcattr,
960 [ # # # # ]: 0 : ft_field_support_2_nic_receive.inner_l4_ok) &&
961 : : MLX5_GET(flow_table_nic_cap, hcattr,
962 [ # # # # ]: 0 : ft_field_support_2_nic_receive.outer_l3_ok) &&
963 : : MLX5_GET(flow_table_nic_cap, hcattr,
964 [ # # # # ]: 0 : ft_field_support_2_nic_receive.outer_l4_ok) &&
965 : : MLX5_GET(flow_table_nic_cap, hcattr,
966 : : ft_field_support_2_nic_receive
967 [ # # # # ]: 0 : .inner_ipv4_checksum_ok) &&
968 : : MLX5_GET(flow_table_nic_cap, hcattr,
969 [ # # # # ]: 0 : ft_field_support_2_nic_receive.inner_l4_checksum_ok) &&
970 : : MLX5_GET(flow_table_nic_cap, hcattr,
971 : : ft_field_support_2_nic_receive
972 [ # # # # : 0 : .outer_ipv4_checksum_ok) &&
# # # # #
# # # # #
# # # # ]
973 [ # # # # ]: 0 : MLX5_GET(flow_table_nic_cap, hcattr,
974 : : ft_field_support_2_nic_receive.outer_l4_checksum_ok);
975 : : }
976 : :
977 : : /**
978 : : * Query HCA attributes.
979 : : * Using those attributes we can check on run time if the device
980 : : * is having the required capabilities.
981 : : *
982 : : * @param[in] ctx
983 : : * Context returned from mlx5 open_device() glue function.
984 : : * @param[out] attr
985 : : * Attributes device values.
986 : : *
987 : : * @return
988 : : * 0 on success, a negative value otherwise.
989 : : */
990 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_query_hca_attr)
991 : : int
992 : 0 : mlx5_devx_cmd_query_hca_attr(void *ctx,
993 : : struct mlx5_hca_attr *attr)
994 : : {
995 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
996 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
997 : : bool hca_cap_2_sup;
998 : : uint64_t general_obj_types_supported = 0;
999 : : uint64_t stc_action_type_127_64;
1000 : : void *hcattr;
1001 : : int rc, i;
1002 : :
1003 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1004 : : MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE |
1005 : : (uint32_t)MLX5_HCA_CAP_OPMOD_GET_CUR);
1006 [ # # ]: 0 : if (!hcattr)
1007 : 0 : return rc;
1008 [ # # ]: 0 : hca_cap_2_sup = MLX5_GET(cmd_hca_cap, hcattr, hca_cap_2);
1009 [ # # ]: 0 : attr->max_wqe_sz_sq = MLX5_GET(cmd_hca_cap, hcattr, max_wqe_sz_sq);
1010 : 0 : attr->flow_counter_bulk_alloc_bitmap =
1011 [ # # ]: 0 : MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc);
1012 [ # # ]: 0 : attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr,
1013 : : flow_counters_dump);
1014 [ # # ]: 0 : attr->log_max_rmp = MLX5_GET(cmd_hca_cap, hcattr, log_max_rmp);
1015 [ # # ]: 0 : attr->mem_rq_rmp = MLX5_GET(cmd_hca_cap, hcattr, mem_rq_rmp);
1016 [ # # ]: 0 : attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr,
1017 : : log_max_rqt_size);
1018 [ # # ]: 0 : attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager);
1019 [ # # ]: 0 : attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin);
1020 [ # # ]: 0 : attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr,
1021 : : log_max_hairpin_queues);
1022 [ # # ]: 0 : attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr,
1023 : : log_max_hairpin_wq_data_sz);
1024 [ # # ]: 0 : attr->log_max_hairpin_num_packets = MLX5_GET
1025 : : (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz);
1026 [ # # ]: 0 : attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id);
1027 [ # # ]: 0 : attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr,
1028 : : relaxed_ordering_write);
1029 [ # # ]: 0 : attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr,
1030 : : relaxed_ordering_read);
1031 [ # # ]: 0 : attr->pci_relaxed_ordered_read = MLX5_GET(cmd_hca_cap, hcattr,
1032 : : pci_relaxed_ordered_read);
1033 [ # # ]: 0 : attr->mkc_order_read_after_write = MLX5_GET(cmd_hca_cap, hcattr,
1034 : : mkc_order_read_after_write);
1035 [ # # ]: 0 : attr->mkc_order_write_after_write_ro_only = MLX5_GET(cmd_hca_cap, hcattr,
1036 : : mkc_order_write_after_write_ro_only);
1037 [ # # ]: 0 : attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr,
1038 : : access_register_user);
1039 [ # # ]: 0 : attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr,
1040 : : eth_net_offloads);
1041 [ # # ]: 0 : attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);
1042 [ # # ]: 0 : attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr,
1043 : : flex_parser_protocols);
1044 [ # # ]: 0 : attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr,
1045 : : max_geneve_tlv_options);
1046 [ # # ]: 0 : attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr,
1047 : : max_geneve_tlv_option_data_len);
1048 [ # # ]: 0 : attr->geneve_tlv_option_offset = MLX5_GET(cmd_hca_cap, hcattr,
1049 : : geneve_tlv_option_offset);
1050 [ # # ]: 0 : attr->geneve_tlv_sample = MLX5_GET(cmd_hca_cap, hcattr,
1051 : : geneve_tlv_sample);
1052 [ # # ]: 0 : attr->query_match_sample_info = MLX5_GET(cmd_hca_cap, hcattr,
1053 : : query_match_sample_info);
1054 [ # # ]: 0 : attr->geneve_tlv_option_sample_id = MLX5_GET(cmd_hca_cap, hcattr,
1055 : : flex_parser_id_geneve_opt_0);
1056 [ # # ]: 0 : attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos);
1057 [ # # ]: 0 : attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr,
1058 : : wqe_index_ignore_cap);
1059 [ # # ]: 0 : attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd);
1060 [ # # ]: 0 : attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq);
1061 [ # # ]: 0 : attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr,
1062 : : log_max_static_sq_wq);
1063 [ # # ]: 0 : attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports);
1064 [ # # ]: 0 : attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr,
1065 : : device_frequency_khz);
1066 : 0 : attr->scatter_fcs_w_decap_disable =
1067 [ # # ]: 0 : MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable);
1068 [ # # ]: 0 : attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce);
1069 [ # # ]: 0 : attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format);
1070 [ # # ]: 0 : attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format);
1071 : 0 : attr->steering_format_version =
1072 [ # # ]: 0 : MLX5_GET(cmd_hca_cap, hcattr, steering_format_version);
1073 [ # # ]: 0 : attr->regexp_params = MLX5_GET(cmd_hca_cap, hcattr, regexp_params);
1074 [ # # ]: 0 : attr->regexp_version = MLX5_GET(cmd_hca_cap, hcattr, regexp_version);
1075 [ # # ]: 0 : attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr,
1076 : : regexp_num_of_engines);
1077 : : /* Read the general_obj_types bitmap and extract the relevant bits. */
1078 [ # # ]: 0 : general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr,
1079 : : general_obj_types);
1080 : 0 : attr->qos.flow_meter_aso_sup =
1081 : 0 : !!(general_obj_types_supported &
1082 : : MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO);
1083 : 0 : attr->vdpa.valid = !!(general_obj_types_supported &
1084 : : MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q);
1085 : 0 : attr->vdpa.queue_counters_valid =
1086 : 0 : !!(general_obj_types_supported &
1087 : : MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS);
1088 : 0 : attr->parse_graph_flex_node =
1089 : 0 : !!(general_obj_types_supported &
1090 : : MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE);
1091 : 0 : attr->flow_hit_aso = !!(general_obj_types_supported &
1092 : : MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO);
1093 : 0 : attr->geneve_tlv_opt = !!(general_obj_types_supported &
1094 : : MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT);
1095 : 0 : attr->dek = !!(general_obj_types_supported &
1096 : : MLX5_GENERAL_OBJ_TYPES_CAP_DEK);
1097 : 0 : attr->import_kek = !!(general_obj_types_supported &
1098 : : MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK);
1099 : 0 : attr->credential = !!(general_obj_types_supported &
1100 : : MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL);
1101 : 0 : attr->crypto_login = !!(general_obj_types_supported &
1102 : : MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN);
1103 : : /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */
1104 [ # # ]: 0 : attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq);
1105 [ # # ]: 0 : attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp);
1106 [ # # ]: 0 : attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz);
1107 [ # # ]: 0 : attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz);
1108 [ # # ]: 0 : attr->log_max_wq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_wq_sz);
1109 [ # # ]: 0 : attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz);
1110 [ # # ]: 0 : attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd);
1111 [ # # ]: 0 : attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq);
1112 [ # # ]: 0 : attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz);
1113 : 0 : attr->reg_c_preserve =
1114 [ # # ]: 0 : MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve);
1115 [ # # ]: 0 : attr->mmo_regex_qp_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_qp);
1116 [ # # ]: 0 : attr->mmo_regex_sq_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_sq);
1117 [ # # ]: 0 : attr->mmo_dma_sq_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_sq);
1118 [ # # ]: 0 : attr->mmo_compress_sq_en = MLX5_GET(cmd_hca_cap, hcattr,
1119 : : compress_mmo_sq);
1120 [ # # ]: 0 : attr->mmo_decompress_sq_en = MLX5_GET(cmd_hca_cap, hcattr,
1121 : : decompress_mmo_sq);
1122 [ # # ]: 0 : attr->mmo_dma_qp_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_qp);
1123 [ # # ]: 0 : attr->mmo_compress_qp_en = MLX5_GET(cmd_hca_cap, hcattr,
1124 : : compress_mmo_qp);
1125 [ # # ]: 0 : attr->decomp_deflate_v1_en = MLX5_GET(cmd_hca_cap, hcattr,
1126 : : decompress_deflate_v1);
1127 [ # # ]: 0 : attr->decomp_deflate_v2_en = MLX5_GET(cmd_hca_cap, hcattr,
1128 : : decompress_deflate_v2);
1129 [ # # ]: 0 : attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr,
1130 : : compress_min_block_size);
1131 [ # # ]: 0 : attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size);
1132 [ # # ]: 0 : attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr,
1133 : : log_compress_mmo_size);
1134 [ # # ]: 0 : attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr,
1135 : : log_decompress_mmo_size);
1136 [ # # ]: 0 : attr->decomp_lz4_data_only_en = MLX5_GET(cmd_hca_cap, hcattr,
1137 : : decompress_lz4_data_only_v2);
1138 [ # # ]: 0 : attr->decomp_lz4_no_checksum_en = MLX5_GET(cmd_hca_cap, hcattr,
1139 : : decompress_lz4_no_checksum_v2);
1140 [ # # ]: 0 : attr->decomp_lz4_checksum_en = MLX5_GET(cmd_hca_cap, hcattr,
1141 : : decompress_lz4_checksum_v2);
1142 [ # # ]: 0 : attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression);
1143 [ # # ]: 0 : attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr,
1144 : : mini_cqe_resp_flow_tag);
1145 [ # # ]: 0 : attr->cqe_compression_128 = MLX5_GET(cmd_hca_cap, hcattr,
1146 : : cqe_compression_128);
1147 [ # # ]: 0 : attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr,
1148 : : mini_cqe_resp_l3_l4_tag);
1149 [ # # ]: 0 : attr->enhanced_cqe_compression = MLX5_GET(cmd_hca_cap, hcattr,
1150 : : enhanced_cqe_compression);
1151 : 0 : attr->umr_indirect_mkey_disabled =
1152 [ # # ]: 0 : MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled);
1153 : 0 : attr->umr_modify_entity_size_disabled =
1154 [ # # ]: 0 : MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled);
1155 [ # # ]: 0 : attr->wait_on_time = MLX5_GET(cmd_hca_cap, hcattr, wait_on_time);
1156 [ # # ]: 0 : attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto);
1157 : 0 : attr->ct_offload = !!(general_obj_types_supported &
1158 : : MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD);
1159 [ # # ]: 0 : attr->rq_delay_drop = MLX5_GET(cmd_hca_cap, hcattr, rq_delay_drop);
1160 [ # # ]: 0 : attr->nic_flow_table = MLX5_GET(cmd_hca_cap, hcattr, nic_flow_table);
1161 [ # # ]: 0 : attr->striding_rq = MLX5_GET(cmd_hca_cap, hcattr, striding_rq);
1162 : 0 : attr->ext_stride_num_range =
1163 [ # # ]: 0 : MLX5_GET(cmd_hca_cap, hcattr, ext_stride_num_range);
1164 [ # # ]: 0 : attr->nic_flow_table = MLX5_GET(cmd_hca_cap, hcattr, nic_flow_table);
1165 [ # # ]: 0 : attr->max_flow_counter_15_0 = MLX5_GET(cmd_hca_cap, hcattr,
1166 : : max_flow_counter_15_0);
1167 [ # # ]: 0 : attr->max_flow_counter_31_16 = MLX5_GET(cmd_hca_cap, hcattr,
1168 : : max_flow_counter_31_16);
1169 [ # # ]: 0 : attr->alloc_flow_counter_pd = MLX5_GET(cmd_hca_cap, hcattr,
1170 : : alloc_flow_counter_pd);
1171 [ # # ]: 0 : attr->flow_counter_access_aso = MLX5_GET(cmd_hca_cap, hcattr,
1172 : : flow_counter_access_aso);
1173 [ # # ]: 0 : attr->flow_access_aso_opc_mod = MLX5_GET(cmd_hca_cap, hcattr,
1174 : : flow_access_aso_opc_mod);
1175 [ # # ]: 0 : attr->wqe_based_flow_table_sup = MLX5_GET(cmd_hca_cap, hcattr,
1176 : : wqe_based_flow_table_update_cap);
1177 : : /*
1178 : : * Flex item support needs max_num_prog_sample_field
1179 : : * from the Capabilities 2 table for PARSE_GRAPH_NODE
1180 : : */
1181 [ # # ]: 0 : if (attr->parse_graph_flex_node) {
1182 : 0 : rc = mlx5_devx_cmd_query_hca_parse_graph_node_cap
1183 : : (ctx, &attr->flex);
1184 [ # # ]: 0 : if (rc)
1185 : : return -1;
1186 : 0 : attr->flex.query_match_sample_info =
1187 : 0 : attr->query_match_sample_info;
1188 : : }
1189 [ # # ]: 0 : if (attr->crypto) {
1190 [ # # # # : 0 : attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts) ||
# # ]
1191 [ # # # # : 0 : MLX5_GET(cmd_hca_cap, hcattr, aes_xts_multi_block_be_tweak) ||
# # # # #
# # # ]
1192 : : MLX5_GET(cmd_hca_cap, hcattr, aes_xts_single_block_le_tweak);
1193 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1194 : : MLX5_GET_HCA_CAP_OP_MOD_CRYPTO |
1195 : : (uint32_t)MLX5_HCA_CAP_OPMOD_GET_CUR);
1196 [ # # ]: 0 : if (!hcattr)
1197 : : return -1;
1198 [ # # ]: 0 : attr->crypto_wrapped_import_method = !!(MLX5_GET(crypto_caps,
1199 : : hcattr, wrapped_import_method)
1200 : 0 : & 1 << 2);
1201 [ # # ]: 0 : attr->crypto_mmo.crypto_mmo_qp = MLX5_GET(crypto_caps, hcattr, crypto_mmo_qp);
1202 : 0 : attr->crypto_mmo.gcm_256_encrypt =
1203 [ # # ]: 0 : MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_256_encrypt);
1204 : 0 : attr->crypto_mmo.gcm_128_encrypt =
1205 [ # # ]: 0 : MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_128_encrypt);
1206 : 0 : attr->crypto_mmo.gcm_256_decrypt =
1207 [ # # ]: 0 : MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_256_decrypt);
1208 : 0 : attr->crypto_mmo.gcm_128_decrypt =
1209 [ # # ]: 0 : MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_128_decrypt);
1210 : 0 : attr->crypto_mmo.gcm_auth_tag_128 =
1211 [ # # ]: 0 : MLX5_GET(crypto_caps, hcattr, gcm_auth_tag_128);
1212 : 0 : attr->crypto_mmo.gcm_auth_tag_96 =
1213 [ # # ]: 0 : MLX5_GET(crypto_caps, hcattr, gcm_auth_tag_96);
1214 : 0 : attr->crypto_mmo.log_crypto_mmo_max_size =
1215 [ # # ]: 0 : MLX5_GET(crypto_caps, hcattr, log_crypto_mmo_max_size);
1216 : : }
1217 [ # # ]: 0 : if (hca_cap_2_sup) {
1218 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1219 : : MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 |
1220 : : (uint32_t)MLX5_HCA_CAP_OPMOD_GET_CUR);
1221 [ # # ]: 0 : if (!hcattr) {
1222 : 0 : DRV_LOG(DEBUG,
1223 : : "Failed to query DevX HCA capabilities 2.");
1224 : 0 : return rc;
1225 : : }
1226 [ # # ]: 0 : attr->log_min_stride_wqe_sz = MLX5_GET(cmd_hca_cap_2, hcattr,
1227 : : log_min_stride_wqe_sz);
1228 [ # # ]: 0 : attr->hairpin_sq_wqe_bb_size = MLX5_GET(cmd_hca_cap_2, hcattr,
1229 : : hairpin_sq_wqe_bb_size);
1230 [ # # ]: 0 : attr->hairpin_sq_wq_in_host_mem = MLX5_GET(cmd_hca_cap_2, hcattr,
1231 : : hairpin_sq_wq_in_host_mem);
1232 [ # # ]: 0 : attr->hairpin_data_buffer_locked = MLX5_GET(cmd_hca_cap_2, hcattr,
1233 : : hairpin_data_buffer_locked);
1234 [ # # ]: 0 : attr->flow_counter_bulk_log_max_alloc = MLX5_GET(cmd_hca_cap_2,
1235 : : hcattr, flow_counter_bulk_log_max_alloc);
1236 : 0 : attr->flow_counter_bulk_log_granularity =
1237 [ # # ]: 0 : MLX5_GET(cmd_hca_cap_2, hcattr,
1238 : : flow_counter_bulk_log_granularity);
1239 [ # # ]: 0 : rc = MLX5_GET(cmd_hca_cap_2, hcattr,
1240 : : cross_vhca_object_to_object_supported);
1241 : 0 : attr->cross_vhca =
1242 : : (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_STC_TO_TIR) &&
1243 : : (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_STC_TO_FT) &&
1244 : 0 : (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_FT_TO_FT) &&
1245 : : (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_FT_TO_RTC);
1246 [ # # ]: 0 : rc = MLX5_GET(cmd_hca_cap_2, hcattr,
1247 : : allowed_object_for_other_vhca_access);
1248 : 0 : attr->cross_vhca = attr->cross_vhca &&
1249 : : (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_TIR) &&
1250 [ # # # # ]: 0 : (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_FT) &&
1251 : : (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_RTC);
1252 [ # # ]: 0 : if (attr->ct_offload)
1253 [ # # ]: 0 : attr->log_max_conn_track_offload = MLX5_GET(cmd_hca_cap_2, hcattr,
1254 : : log_max_conn_track_offload);
1255 : : }
1256 [ # # ]: 0 : if (attr->log_min_stride_wqe_sz == 0)
1257 : 0 : attr->log_min_stride_wqe_sz = MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE;
1258 [ # # ]: 0 : if (attr->qos.sup) {
1259 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1260 : : MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |
1261 : : (uint32_t)MLX5_HCA_CAP_OPMOD_GET_CUR);
1262 [ # # ]: 0 : if (!hcattr) {
1263 : 0 : DRV_LOG(DEBUG, "Failed to query devx QOS capabilities");
1264 : 0 : return rc;
1265 : : }
1266 : 0 : attr->qos.flow_meter_old =
1267 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr, flow_meter_old);
1268 : 0 : attr->qos.log_max_flow_meter =
1269 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr, log_max_flow_meter);
1270 [ # # ]: 0 : attr->qos.flow_meter_reg_c_ids =
1271 : : MLX5_GET(qos_cap, hcattr, flow_meter_reg_id);
1272 : 0 : attr->qos.flow_meter =
1273 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr, flow_meter);
1274 : 0 : attr->qos.packet_pacing =
1275 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr, packet_pacing);
1276 : 0 : attr->qos.wqe_rate_pp =
1277 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr, wqe_rate_pp);
1278 : 0 : attr->qos.packet_pacing_burst_bound =
1279 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr,
1280 : : packet_pacing_burst_bound);
1281 : 0 : attr->qos.packet_pacing_typical_size =
1282 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr,
1283 : : packet_pacing_typical_size);
1284 : 0 : attr->qos.packet_pacing_max_rate =
1285 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr,
1286 : : packet_pacing_max_rate);
1287 : 0 : attr->qos.packet_pacing_min_rate =
1288 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr,
1289 : : packet_pacing_min_rate);
1290 : 0 : attr->qos.packet_pacing_rate_table_size =
1291 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr,
1292 : : packet_pacing_rate_table_size);
1293 [ # # ]: 0 : if (attr->qos.flow_meter_aso_sup) {
1294 : 0 : attr->qos.log_meter_aso_granularity =
1295 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr,
1296 : : log_meter_aso_granularity);
1297 : 0 : attr->qos.log_meter_aso_max_alloc =
1298 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr,
1299 : : log_meter_aso_max_alloc);
1300 : 0 : attr->qos.log_max_num_meter_aso =
1301 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr,
1302 : : log_max_num_meter_aso);
1303 : : }
1304 : : }
1305 [ # # ]: 0 : if (attr->vdpa.valid)
1306 : 0 : mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa);
1307 [ # # ]: 0 : if (!attr->eth_net_offloads)
1308 : : return 0;
1309 : : /* Query Flow Sampler Capability From FLow Table Properties Layout. */
1310 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1311 : : MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE |
1312 : : (uint32_t)MLX5_HCA_CAP_OPMOD_GET_CUR);
1313 [ # # ]: 0 : if (!hcattr) {
1314 : 0 : attr->log_max_ft_sampler_num = 0;
1315 : 0 : return rc;
1316 : : }
1317 [ # # ]: 0 : attr->log_max_ft_sampler_num = MLX5_GET
1318 : : (flow_table_nic_cap, hcattr,
1319 : : flow_table_properties_nic_receive.log_max_ft_sampler_num);
1320 [ # # ]: 0 : attr->flow.tunnel_header_0_1 = MLX5_GET
1321 : : (flow_table_nic_cap, hcattr,
1322 : : ft_field_support_2_nic_receive.tunnel_header_0_1);
1323 [ # # ]: 0 : attr->flow.tunnel_header_2_3 = MLX5_GET
1324 : : (flow_table_nic_cap, hcattr,
1325 : : ft_field_support_2_nic_receive.tunnel_header_2_3);
1326 [ # # ]: 0 : attr->modify_outer_ip_ecn = MLX5_GET
1327 : : (flow_table_nic_cap, hcattr,
1328 : : ft_header_modify_nic_receive.outer_ip_ecn);
1329 [ # # ]: 0 : attr->modify_outer_ipv6_traffic_class = MLX5_GET
1330 : : (flow_table_nic_cap, hcattr,
1331 : : ft_header_modify_nic_receive.outer_ipv6_traffic_class);
1332 : 0 : attr->set_reg_c = 0xffff;
1333 [ # # ]: 0 : if (attr->nic_flow_table) {
1334 : : #define GET_RX_REG_X_BITS \
1335 : : MLX5_GET(flow_table_nic_cap, hcattr, \
1336 : : ft_header_modify_nic_receive.metadata_reg_c_x)
1337 : : #define GET_TX_REG_X_BITS \
1338 : : MLX5_GET(flow_table_nic_cap, hcattr, \
1339 : : ft_header_modify_nic_transmit.metadata_reg_c_x)
1340 : :
1341 : : uint32_t tx_reg, rx_reg, reg_c_8_15;
1342 : :
1343 [ # # ]: 0 : tx_reg = GET_TX_REG_X_BITS;
1344 [ # # ]: 0 : reg_c_8_15 = MLX5_GET(flow_table_nic_cap, hcattr,
1345 : : ft_field_support_2_nic_transmit.metadata_reg_c_8_15);
1346 : 0 : tx_reg |= ((0xff & reg_c_8_15) << 8);
1347 [ # # ]: 0 : rx_reg = GET_RX_REG_X_BITS;
1348 [ # # ]: 0 : reg_c_8_15 = MLX5_GET(flow_table_nic_cap, hcattr,
1349 : : ft_field_support_2_nic_receive.metadata_reg_c_8_15);
1350 : 0 : rx_reg |= ((0xff & reg_c_8_15) << 8);
1351 : 0 : attr->set_reg_c &= (rx_reg & tx_reg);
1352 : :
1353 [ # # ]: 0 : attr->rx_sw_owner_v2 = MLX5_GET(flow_table_nic_cap, hcattr,
1354 : : flow_table_properties_nic_receive.sw_owner_v2);
1355 [ # # ]: 0 : if (!attr->rx_sw_owner_v2)
1356 [ # # ]: 0 : attr->rx_sw_owner = MLX5_GET(flow_table_nic_cap, hcattr,
1357 : : flow_table_properties_nic_receive.sw_owner);
1358 : :
1359 [ # # ]: 0 : attr->tx_sw_owner_v2 = MLX5_GET(flow_table_nic_cap, hcattr,
1360 : : flow_table_properties_nic_transmit.sw_owner_v2);
1361 [ # # ]: 0 : if (!attr->tx_sw_owner_v2)
1362 [ # # ]: 0 : attr->tx_sw_owner = MLX5_GET(flow_table_nic_cap, hcattr,
1363 : : flow_table_properties_nic_transmit.sw_owner);
1364 : :
1365 : : #undef GET_RX_REG_X_BITS
1366 : : #undef GET_TX_REG_X_BITS
1367 : : }
1368 : 0 : attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr);
1369 [ # # ]: 0 : attr->inner_ipv4_ihl = MLX5_GET
1370 : : (flow_table_nic_cap, hcattr,
1371 : : ft_field_support_2_nic_receive.inner_ipv4_ihl);
1372 [ # # ]: 0 : attr->outer_ipv4_ihl = MLX5_GET
1373 : : (flow_table_nic_cap, hcattr,
1374 : : ft_field_support_2_nic_receive.outer_ipv4_ihl);
1375 [ # # ]: 0 : attr->lag_rx_port_affinity = MLX5_GET
1376 : : (flow_table_nic_cap, hcattr,
1377 : : ft_field_support_2_nic_receive.lag_rx_port_affinity);
1378 : : /* Query HCA offloads for Ethernet protocol. */
1379 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1380 : : MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS |
1381 : : (uint32_t)MLX5_HCA_CAP_OPMOD_GET_CUR);
1382 [ # # ]: 0 : if (!hcattr) {
1383 : 0 : attr->eth_net_offloads = 0;
1384 : 0 : return rc;
1385 : : }
1386 [ # # ]: 0 : attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps,
1387 : : hcattr, wqe_vlan_insert);
1388 [ # # ]: 0 : attr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps,
1389 : : hcattr, csum_cap);
1390 [ # # ]: 0 : attr->vlan_cap = MLX5_GET(per_protocol_networking_offload_caps,
1391 : : hcattr, vlan_cap);
1392 [ # # ]: 0 : attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr,
1393 : : lro_cap);
1394 [ # # ]: 0 : attr->max_lso_cap = MLX5_GET(per_protocol_networking_offload_caps,
1395 : : hcattr, max_lso_cap);
1396 [ # # ]: 0 : attr->scatter_fcs = MLX5_GET(per_protocol_networking_offload_caps,
1397 : : hcattr, scatter_fcs);
1398 [ # # ]: 0 : attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps,
1399 : : hcattr, tunnel_lro_gre);
1400 [ # # ]: 0 : attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps,
1401 : : hcattr, tunnel_lro_vxlan);
1402 [ # # ]: 0 : attr->swp = MLX5_GET(per_protocol_networking_offload_caps,
1403 : : hcattr, swp);
1404 : 0 : attr->tunnel_stateless_gre =
1405 [ # # ]: 0 : MLX5_GET(per_protocol_networking_offload_caps,
1406 : : hcattr, tunnel_stateless_gre);
1407 : 0 : attr->tunnel_stateless_vxlan =
1408 [ # # ]: 0 : MLX5_GET(per_protocol_networking_offload_caps,
1409 : : hcattr, tunnel_stateless_vxlan);
1410 [ # # ]: 0 : attr->swp_csum = MLX5_GET(per_protocol_networking_offload_caps,
1411 : : hcattr, swp_csum);
1412 [ # # ]: 0 : attr->swp_lso = MLX5_GET(per_protocol_networking_offload_caps,
1413 : : hcattr, swp_lso);
1414 [ # # ]: 0 : attr->lro_max_msg_sz_mode = MLX5_GET
1415 : : (per_protocol_networking_offload_caps,
1416 : : hcattr, lro_max_msg_sz_mode);
1417 [ # # ]: 0 : for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) {
1418 : 0 : attr->lro_timer_supported_periods[i] =
1419 [ # # ]: 0 : MLX5_GET(per_protocol_networking_offload_caps, hcattr,
1420 : : lro_timer_supported_periods[i]);
1421 : : }
1422 [ # # ]: 0 : attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps,
1423 : : hcattr, lro_min_mss_size);
1424 : 0 : attr->tunnel_stateless_geneve_rx =
1425 [ # # ]: 0 : MLX5_GET(per_protocol_networking_offload_caps,
1426 : : hcattr, tunnel_stateless_geneve_rx);
1427 : 0 : attr->geneve_max_opt_len =
1428 [ # # ]: 0 : MLX5_GET(per_protocol_networking_offload_caps,
1429 : : hcattr, max_geneve_opt_len);
1430 [ # # ]: 0 : attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps,
1431 : : hcattr, wqe_inline_mode);
1432 [ # # ]: 0 : attr->tunnel_stateless_gtp = MLX5_GET
1433 : : (per_protocol_networking_offload_caps,
1434 : : hcattr, tunnel_stateless_gtp);
1435 [ # # ]: 0 : attr->tunnel_stateless_vxlan_gpe_nsh = MLX5_GET
1436 : : (per_protocol_networking_offload_caps,
1437 : : hcattr, tunnel_stateless_vxlan_gpe_nsh);
1438 [ # # ]: 0 : attr->rss_ind_tbl_cap = MLX5_GET
1439 : : (per_protocol_networking_offload_caps,
1440 : : hcattr, rss_ind_tbl_cap);
1441 [ # # ]: 0 : attr->multi_pkt_send_wqe = MLX5_GET
1442 : : (per_protocol_networking_offload_caps,
1443 : : hcattr, multi_pkt_send_wqe);
1444 [ # # ]: 0 : attr->enhanced_multi_pkt_send_wqe = MLX5_GET
1445 : : (per_protocol_networking_offload_caps,
1446 : : hcattr, enhanced_multi_pkt_send_wqe);
1447 [ # # ]: 0 : if (attr->wqe_based_flow_table_sup) {
1448 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1449 : : MLX5_GET_HCA_CAP_OP_MOD_WQE_BASED_FLOW_TABLE |
1450 : : (uint32_t)MLX5_HCA_CAP_OPMOD_GET_CUR);
1451 [ # # ]: 0 : if (!hcattr) {
1452 : 0 : DRV_LOG(DEBUG, "Failed to query WQE Based Flow table capabilities");
1453 : 0 : return rc;
1454 : : }
1455 [ # # ]: 0 : attr->max_header_modify_pattern_length = MLX5_GET(wqe_based_flow_table_cap,
1456 : : hcattr,
1457 : : max_header_modify_pattern_length);
1458 [ # # ]: 0 : attr->fdb_unified_en = MLX5_GET(wqe_based_flow_table_cap,
1459 : : hcattr,
1460 : : fdb_unified_en);
1461 [ # # ]: 0 : attr->fdb_rx_set_flow_tag_stc = MLX5_GET(wqe_based_flow_table_cap,
1462 : : hcattr,
1463 : : fdb_rx_set_flow_tag_stc);
1464 [ # # ]: 0 : stc_action_type_127_64 = MLX5_GET64(wqe_based_flow_table_cap,
1465 : : hcattr,
1466 : : stc_action_type_127_64);
1467 [ # # ]: 0 : if (stc_action_type_127_64 &
1468 : : (1 << (MLX5_IFC_STC_ACTION_TYPE_JUMP_FLOW_TABLE_FDB_RX_BIT_INDEX -
1469 : : MLX5_IFC_STC_ACTION_TYPE_BIT_64_INDEX)))
1470 : 0 : attr->jump_fdb_rx_en = 1;
1471 : : }
1472 : : /* Query HCA attribute for ROCE. */
1473 [ # # ]: 0 : if (attr->roce) {
1474 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1475 : : MLX5_GET_HCA_CAP_OP_MOD_ROCE |
1476 : : (uint32_t)MLX5_HCA_CAP_OPMOD_GET_CUR);
1477 [ # # ]: 0 : if (!hcattr) {
1478 : 0 : DRV_LOG(DEBUG,
1479 : : "Failed to query devx HCA ROCE capabilities");
1480 : 0 : return rc;
1481 : : }
1482 [ # # ]: 0 : attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format);
1483 : : }
1484 [ # # ]: 0 : if (attr->eth_virt) {
1485 : 0 : rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr);
1486 [ # # ]: 0 : if (rc) {
1487 : 0 : attr->eth_virt = 0;
1488 : 0 : goto error;
1489 : : }
1490 : : }
1491 [ # # ]: 0 : if (attr->eswitch_manager) {
1492 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1493 : : MLX5_SET_HCA_CAP_OP_MOD_ESW |
1494 : : (uint32_t)MLX5_HCA_CAP_OPMOD_GET_CUR);
1495 [ # # ]: 0 : if (!hcattr)
1496 : 0 : return rc;
1497 : 0 : attr->esw_mgr_vport_id_valid =
1498 [ # # ]: 0 : MLX5_GET(esw_cap, hcattr,
1499 : : esw_manager_vport_number_valid);
1500 : 0 : attr->esw_mgr_vport_id =
1501 [ # # ]: 0 : MLX5_GET(esw_cap, hcattr, esw_manager_vport_number);
1502 : 0 : mlx5_devx_cmd_query_esw_vport_context(ctx, attr);
1503 : : }
1504 [ # # ]: 0 : if (attr->eswitch_manager) {
1505 : : uint32_t esw_reg, reg_c_8_15;
1506 : :
1507 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1508 : : MLX5_GET_HCA_CAP_OP_MOD_ESW_FLOW_TABLE |
1509 : : (uint32_t)MLX5_HCA_CAP_OPMOD_GET_CUR);
1510 [ # # ]: 0 : if (!hcattr)
1511 : 0 : return rc;
1512 [ # # ]: 0 : esw_reg = MLX5_GET(flow_table_esw_cap, hcattr,
1513 : : ft_header_modify_esw_fdb.metadata_reg_c_x);
1514 [ # # ]: 0 : reg_c_8_15 = MLX5_GET(flow_table_esw_cap, hcattr,
1515 : : ft_field_support_2_esw_fdb.metadata_reg_c_8_15);
1516 : 0 : attr->set_reg_c &= ((0xff & reg_c_8_15) << 8) | esw_reg;
1517 : :
1518 [ # # ]: 0 : attr->esw_sw_owner_v2 = MLX5_GET(flow_table_esw_cap, hcattr,
1519 : : flow_table_properties_nic_esw_fdb.sw_owner_v2);
1520 [ # # ]: 0 : if (!attr->esw_sw_owner_v2)
1521 [ # # ]: 0 : attr->esw_sw_owner = MLX5_GET(flow_table_esw_cap, hcattr,
1522 : : flow_table_properties_nic_esw_fdb.sw_owner);
1523 : : }
1524 : : return 0;
1525 : : error:
1526 : 0 : rc = (rc > 0) ? -rc : rc;
1527 : 0 : return rc;
1528 : : }
1529 : :
1530 : : /**
1531 : : * Query TIS transport domain from QP verbs object using DevX API.
1532 : : *
1533 : : * @param[in] qp
1534 : : * Pointer to verbs QP returned by ibv_create_qp .
1535 : : * @param[in] tis_num
1536 : : * TIS number of TIS to query.
1537 : : * @param[out] tis_td
1538 : : * Pointer to TIS transport domain variable, to be set by the routine.
1539 : : *
1540 : : * @return
1541 : : * 0 on success, a negative value otherwise.
1542 : : */
1543 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_qp_query_tis_td)
1544 : : int
1545 : 0 : mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num,
1546 : : uint32_t *tis_td)
1547 : : {
1548 : : #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1549 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0};
1550 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0};
1551 : : int rc;
1552 : : void *tis_ctx;
1553 : :
1554 : 0 : MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS);
1555 : 0 : MLX5_SET(query_tis_in, in, tisn, tis_num);
1556 : 0 : rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out));
1557 [ # # ]: 0 : if (rc) {
1558 : 0 : DRV_LOG(ERR, "Failed to query QP using DevX");
1559 : 0 : return -rc;
1560 : : };
1561 : : tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context);
1562 [ # # ]: 0 : *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain);
1563 : 0 : return 0;
1564 : : #else
1565 : : (void)qp;
1566 : : (void)tis_num;
1567 : : (void)tis_td;
1568 : : return -ENOTSUP;
1569 : : #endif
1570 : : }
1571 : :
1572 : : /**
1573 : : * Fill WQ data for DevX API command.
1574 : : * Utility function for use when creating DevX objects containing a WQ.
1575 : : *
1576 : : * @param[in] wq_ctx
1577 : : * Pointer to WQ context to fill with data.
1578 : : * @param [in] wq_attr
1579 : : * Pointer to WQ attributes structure to fill in WQ context.
1580 : : */
1581 : : static void
1582 : 0 : devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr)
1583 : : {
1584 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type);
1585 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature);
1586 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode);
1587 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave);
1588 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge);
1589 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size);
1590 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset);
1591 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm);
1592 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, pd, wq_attr->pd);
1593 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page);
1594 [ # # ]: 0 : MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr);
1595 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter);
1596 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter);
1597 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride);
1598 [ # # ]: 0 : if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT)
1599 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, log_wq_pg_sz,
1600 : : wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT);
1601 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz);
1602 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid);
1603 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid);
1604 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, log_hairpin_num_packets,
1605 : : wq_attr->log_hairpin_num_packets);
1606 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz);
1607 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides,
1608 : : wq_attr->single_wqe_log_num_of_strides);
1609 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en);
1610 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes,
1611 : : wq_attr->single_stride_log_num_of_bytes);
1612 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id);
1613 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id);
1614 [ # # ]: 0 : MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset);
1615 : 0 : }
1616 : :
1617 : : /**
1618 : : * Create RQ using DevX API.
1619 : : *
1620 : : * @param[in] ctx
1621 : : * Context returned from mlx5 open_device() glue function.
1622 : : * @param [in] rq_attr
1623 : : * Pointer to create RQ attributes structure.
1624 : : * @param [in] socket
1625 : : * CPU socket ID for allocations.
1626 : : *
1627 : : * @return
1628 : : * The DevX object created, NULL otherwise and rte_errno is set.
1629 : : */
1630 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_rq)
1631 : : struct mlx5_devx_obj *
1632 : 0 : mlx5_devx_cmd_create_rq(void *ctx,
1633 : : struct mlx5_devx_create_rq_attr *rq_attr,
1634 : : int socket)
1635 : : {
1636 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0};
1637 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0};
1638 : : void *rq_ctx, *wq_ctx;
1639 : : struct mlx5_devx_wq_attr *wq_attr;
1640 : : struct mlx5_devx_obj *rq = NULL;
1641 : :
1642 [ # # # # ]: 0 : rq = mlx5_malloc_numa_tolerant(MLX5_MEM_ZERO, sizeof(*rq), 0, socket);
1643 [ # # ]: 0 : if (!rq) {
1644 : 0 : DRV_LOG(ERR, "Failed to allocate RQ data");
1645 : 0 : rte_errno = ENOMEM;
1646 : 0 : return NULL;
1647 : : }
1648 [ # # ]: 0 : MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ);
1649 : : rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx);
1650 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky);
1651 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en);
1652 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
1653 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
1654 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type);
1655 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
1656 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en);
1657 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin);
1658 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, hairpin_data_buffer_type, rq_attr->hairpin_data_buffer_type);
1659 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index);
1660 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn);
1661 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
1662 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn);
1663 [ # # ]: 0 : MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format);
1664 : : wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
1665 : 0 : wq_attr = &rq_attr->wq_attr;
1666 : 0 : devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1667 : 0 : rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1668 : : out, sizeof(out));
1669 [ # # ]: 0 : if (!rq->obj) {
1670 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create RQ", NULL, 0);
1671 : 0 : mlx5_free(rq);
1672 : 0 : return NULL;
1673 : : }
1674 [ # # ]: 0 : rq->id = MLX5_GET(create_rq_out, out, rqn);
1675 : 0 : return rq;
1676 : : }
1677 : :
1678 : : /**
1679 : : * Modify RQ using DevX API.
1680 : : *
1681 : : * @param[in] rq
1682 : : * Pointer to RQ object structure.
1683 : : * @param [in] rq_attr
1684 : : * Pointer to modify RQ attributes structure.
1685 : : *
1686 : : * @return
1687 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
1688 : : */
1689 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_modify_rq)
1690 : : int
1691 : 0 : mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
1692 : : struct mlx5_devx_modify_rq_attr *rq_attr)
1693 : : {
1694 : 0 : uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0};
1695 : 0 : uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0};
1696 : : void *rq_ctx, *wq_ctx;
1697 : : int ret;
1698 : :
1699 : 0 : MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ);
1700 : 0 : MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state);
1701 [ # # ]: 0 : MLX5_SET(modify_rq_in, in, rqn, rq->id);
1702 [ # # ]: 0 : MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask);
1703 : : rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1704 : 0 : MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
1705 [ # # ]: 0 : if (rq_attr->modify_bitmask &
1706 : : MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS)
1707 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
1708 [ # # ]: 0 : if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD)
1709 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
1710 [ # # ]: 0 : if (rq_attr->modify_bitmask &
1711 : : MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID)
1712 : 0 : MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
1713 : 0 : MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq);
1714 : 0 : MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca);
1715 [ # # ]: 0 : if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) {
1716 : : wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
1717 : 0 : MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm);
1718 : : }
1719 : 0 : ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in),
1720 : : out, sizeof(out));
1721 [ # # # # : 0 : if (ret || MLX5_FW_STATUS(out)) {
# # # # ]
1722 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "RQ modify", "rq_id", rq->id);
1723 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(ret);
1724 : : }
1725 : : return 0;
1726 : : }
1727 : :
1728 : : /*
1729 : : * Query RQ using DevX API.
1730 : : *
1731 : : * @param[in] rq_obj
1732 : : * RQ Devx Object
1733 : : * @param[out] out
1734 : : * RQ Query Output
1735 : : * @param[in] outlen
1736 : : * RQ Query Output Length
1737 : : *
1738 : : * @return
1739 : : * 0 if Query successful, else non-zero return value from devx_obj_query API
1740 : : */
1741 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_query_rq)
1742 : : int
1743 : 0 : mlx5_devx_cmd_query_rq(struct mlx5_devx_obj *rq_obj, void *out, size_t outlen)
1744 : : {
1745 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0};
1746 : : int rc;
1747 : :
1748 : 0 : MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ);
1749 : 0 : MLX5_SET(query_rq_in, in, rqn, rq_obj->id);
1750 : 0 : rc = mlx5_glue->devx_obj_query(rq_obj->obj, in, sizeof(in), out, outlen);
1751 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
1752 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "RQ query", "rq_id", rq_obj->id);
1753 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
1754 : : }
1755 : : return 0;
1756 : : }
1757 : :
1758 : : /**
1759 : : * Create RMP using DevX API.
1760 : : *
1761 : : * @param[in] ctx
1762 : : * Context returned from mlx5 open_device() glue function.
1763 : : * @param [in] rmp_attr
1764 : : * Pointer to create RMP attributes structure.
1765 : : * @param [in] socket
1766 : : * CPU socket ID for allocations.
1767 : : *
1768 : : * @return
1769 : : * The DevX object created, NULL otherwise and rte_errno is set.
1770 : : */
1771 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_rmp)
1772 : : struct mlx5_devx_obj *
1773 : 0 : mlx5_devx_cmd_create_rmp(void *ctx,
1774 : : struct mlx5_devx_create_rmp_attr *rmp_attr,
1775 : : int socket)
1776 : : {
1777 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_rmp_in)] = {0};
1778 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_rmp_out)] = {0};
1779 : : void *rmp_ctx, *wq_ctx;
1780 : : struct mlx5_devx_wq_attr *wq_attr;
1781 : : struct mlx5_devx_obj *rmp = NULL;
1782 : :
1783 [ # # # # ]: 0 : rmp = mlx5_malloc_numa_tolerant(MLX5_MEM_ZERO, sizeof(*rmp), 0, socket);
1784 [ # # ]: 0 : if (!rmp) {
1785 : 0 : DRV_LOG(ERR, "Failed to allocate RMP data");
1786 : 0 : rte_errno = ENOMEM;
1787 : 0 : return NULL;
1788 : : }
1789 [ # # ]: 0 : MLX5_SET(create_rmp_in, in, opcode, MLX5_CMD_OP_CREATE_RMP);
1790 : : rmp_ctx = MLX5_ADDR_OF(create_rmp_in, in, ctx);
1791 [ # # ]: 0 : MLX5_SET(rmpc, rmp_ctx, state, rmp_attr->state);
1792 [ # # ]: 0 : MLX5_SET(rmpc, rmp_ctx, basic_cyclic_rcv_wqe,
1793 : : rmp_attr->basic_cyclic_rcv_wqe);
1794 : : wq_ctx = MLX5_ADDR_OF(rmpc, rmp_ctx, wq);
1795 : 0 : wq_attr = &rmp_attr->wq_attr;
1796 : 0 : devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1797 : 0 : rmp->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1798 : : sizeof(out));
1799 [ # # ]: 0 : if (!rmp->obj) {
1800 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create RMP", NULL, 0);
1801 : 0 : mlx5_free(rmp);
1802 : 0 : return NULL;
1803 : : }
1804 [ # # ]: 0 : rmp->id = MLX5_GET(create_rmp_out, out, rmpn);
1805 : 0 : return rmp;
1806 : : }
1807 : :
1808 : : /*
1809 : : * Create TIR using DevX API.
1810 : : *
1811 : : * @param[in] ctx
1812 : : * Context returned from mlx5 open_device() glue function.
1813 : : * @param [in] tir_attr
1814 : : * Pointer to TIR attributes structure.
1815 : : *
1816 : : * @return
1817 : : * The DevX object created, NULL otherwise and rte_errno is set.
1818 : : */
1819 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_tir)
1820 : : struct mlx5_devx_obj *
1821 : 0 : mlx5_devx_cmd_create_tir(void *ctx,
1822 : : struct mlx5_devx_tir_attr *tir_attr)
1823 : : {
1824 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
1825 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0};
1826 : : void *tir_ctx, *outer, *inner, *rss_key;
1827 : : struct mlx5_devx_obj *tir = NULL;
1828 : :
1829 : 0 : tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY);
1830 [ # # ]: 0 : if (!tir) {
1831 : 0 : DRV_LOG(ERR, "Failed to allocate TIR data");
1832 : 0 : rte_errno = ENOMEM;
1833 : 0 : return NULL;
1834 : : }
1835 [ # # ]: 0 : MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1836 : : tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx);
1837 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type);
1838 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1839 : : tir_attr->lro_timeout_period_usecs);
1840 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask);
1841 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz);
1842 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn);
1843 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric);
1844 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, tunneled_offload_en,
1845 : : tir_attr->tunneled_offload_en);
1846 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table);
1847 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1848 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1849 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain);
1850 : : rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key);
1851 [ # # ]: 0 : memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN);
1852 : : outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer);
1853 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1854 : : tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1855 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1856 : : tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1857 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, outer, selected_fields,
1858 : : tir_attr->rx_hash_field_selector_outer.selected_fields);
1859 : : inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner);
1860 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1861 : : tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1862 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1863 : : tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1864 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, inner, selected_fields,
1865 : : tir_attr->rx_hash_field_selector_inner.selected_fields);
1866 : 0 : tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1867 : : out, sizeof(out));
1868 [ # # ]: 0 : if (!tir->obj) {
1869 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create TIR", NULL, 0);
1870 : 0 : mlx5_free(tir);
1871 : 0 : return NULL;
1872 : : }
1873 [ # # ]: 0 : tir->id = MLX5_GET(create_tir_out, out, tirn);
1874 : 0 : return tir;
1875 : : }
1876 : :
1877 : : /**
1878 : : * Modify TIR using DevX API.
1879 : : *
1880 : : * @param[in] tir
1881 : : * Pointer to TIR DevX object structure.
1882 : : * @param [in] modify_tir_attr
1883 : : * Pointer to TIR modification attributes structure.
1884 : : *
1885 : : * @return
1886 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
1887 : : */
1888 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_modify_tir)
1889 : : int
1890 : 0 : mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir,
1891 : : struct mlx5_devx_modify_tir_attr *modify_tir_attr)
1892 : : {
1893 : : struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir;
1894 : 0 : uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0};
1895 : 0 : uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0};
1896 : : void *tir_ctx;
1897 : : int ret;
1898 : :
1899 : 0 : MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR);
1900 : 0 : MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn);
1901 [ # # ]: 0 : MLX5_SET64(modify_tir_in, in, modify_bitmask,
1902 : : modify_tir_attr->modify_bitmask);
1903 : : tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1904 [ # # ]: 0 : if (modify_tir_attr->modify_bitmask &
1905 : : MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) {
1906 : 0 : MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1907 : : tir_attr->lro_timeout_period_usecs);
1908 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, lro_enable_mask,
1909 : : tir_attr->lro_enable_mask);
1910 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, lro_max_msg_sz,
1911 : : tir_attr->lro_max_msg_sz);
1912 : : }
1913 [ # # ]: 0 : if (modify_tir_attr->modify_bitmask &
1914 : : MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE)
1915 : 0 : MLX5_SET(tirc, tir_ctx, indirect_table,
1916 : : tir_attr->indirect_table);
1917 [ # # ]: 0 : if (modify_tir_attr->modify_bitmask &
1918 : : MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) {
1919 : : int i;
1920 : : void *outer, *inner;
1921 : :
1922 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, rx_hash_symmetric,
1923 : : tir_attr->rx_hash_symmetric);
1924 : 0 : MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1925 [ # # ]: 0 : for (i = 0; i < 10; i++) {
1926 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i],
1927 : : tir_attr->rx_hash_toeplitz_key[i]);
1928 : : }
1929 : : outer = MLX5_ADDR_OF(tirc, tir_ctx,
1930 : : rx_hash_field_selector_outer);
1931 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1932 : : tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1933 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1934 : : tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1935 [ # # ]: 0 : MLX5_SET
1936 : : (rx_hash_field_select, outer, selected_fields,
1937 : : tir_attr->rx_hash_field_selector_outer.selected_fields);
1938 : : inner = MLX5_ADDR_OF(tirc, tir_ctx,
1939 : : rx_hash_field_selector_inner);
1940 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1941 : : tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1942 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1943 : : tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1944 [ # # ]: 0 : MLX5_SET
1945 : : (rx_hash_field_select, inner, selected_fields,
1946 : : tir_attr->rx_hash_field_selector_inner.selected_fields);
1947 : : }
1948 [ # # ]: 0 : if (modify_tir_attr->modify_bitmask &
1949 : : MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) {
1950 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1951 : : }
1952 : 0 : ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in),
1953 : : out, sizeof(out));
1954 [ # # ]: 0 : if (ret) {
1955 : 0 : DRV_LOG(ERR, "Failed to modify TIR using DevX");
1956 : 0 : rte_errno = errno;
1957 : 0 : return -errno;
1958 : : }
1959 : : return ret;
1960 : : }
1961 : :
1962 : : /**
1963 : : * Create RQT using DevX API.
1964 : : *
1965 : : * @param[in] ctx
1966 : : * Context returned from mlx5 open_device() glue function.
1967 : : * @param [in] rqt_attr
1968 : : * Pointer to RQT attributes structure.
1969 : : *
1970 : : * @return
1971 : : * The DevX object created, NULL otherwise and rte_errno is set.
1972 : : */
1973 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_rqt)
1974 : : struct mlx5_devx_obj *
1975 : 0 : mlx5_devx_cmd_create_rqt(void *ctx,
1976 : : struct mlx5_devx_rqt_attr *rqt_attr)
1977 : : {
1978 : : uint32_t *in = NULL;
1979 : 0 : uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) +
1980 : 0 : rqt_attr->rqt_actual_size * sizeof(uint32_t);
1981 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
1982 : : void *rqt_ctx;
1983 : : struct mlx5_devx_obj *rqt = NULL;
1984 : : unsigned int i;
1985 : :
1986 : 0 : in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1987 [ # # ]: 0 : if (!in) {
1988 : 0 : DRV_LOG(ERR, "Failed to allocate RQT IN data");
1989 : 0 : rte_errno = ENOMEM;
1990 : 0 : return NULL;
1991 : : }
1992 : 0 : rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY);
1993 [ # # ]: 0 : if (!rqt) {
1994 : 0 : DRV_LOG(ERR, "Failed to allocate RQT data");
1995 : 0 : rte_errno = ENOMEM;
1996 : 0 : mlx5_free(in);
1997 : 0 : return NULL;
1998 : : }
1999 [ # # ]: 0 : MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
2000 : 0 : rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2001 [ # # ]: 0 : MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
2002 [ # # ]: 0 : MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
2003 [ # # ]: 0 : MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
2004 [ # # ]: 0 : for (i = 0; i < rqt_attr->rqt_actual_size; i++)
2005 [ # # ]: 0 : MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
2006 : 0 : rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out));
2007 : 0 : mlx5_free(in);
2008 [ # # ]: 0 : if (!rqt->obj) {
2009 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create RQT", NULL, 0);
2010 : 0 : mlx5_free(rqt);
2011 : 0 : return NULL;
2012 : : }
2013 [ # # ]: 0 : rqt->id = MLX5_GET(create_rqt_out, out, rqtn);
2014 : 0 : return rqt;
2015 : : }
2016 : :
2017 : : /**
2018 : : * Modify RQT using DevX API.
2019 : : *
2020 : : * @param[in] rqt
2021 : : * Pointer to RQT DevX object structure.
2022 : : * @param [in] rqt_attr
2023 : : * Pointer to RQT attributes structure.
2024 : : *
2025 : : * @return
2026 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
2027 : : */
2028 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_modify_rqt)
2029 : : int
2030 : 0 : mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
2031 : : struct mlx5_devx_rqt_attr *rqt_attr)
2032 : : {
2033 : 0 : uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) +
2034 : 0 : rqt_attr->rqt_actual_size * sizeof(uint32_t);
2035 : 0 : uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0};
2036 : 0 : uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
2037 : : void *rqt_ctx;
2038 : : unsigned int i;
2039 : : int ret;
2040 : :
2041 [ # # ]: 0 : if (!in) {
2042 : 0 : DRV_LOG(ERR, "Failed to allocate RQT modify IN data.");
2043 : 0 : rte_errno = ENOMEM;
2044 : 0 : return -ENOMEM;
2045 : : }
2046 [ # # ]: 0 : MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT);
2047 [ # # ]: 0 : MLX5_SET(modify_rqt_in, in, rqtn, rqt->id);
2048 : 0 : MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1);
2049 : 0 : rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context);
2050 [ # # ]: 0 : MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
2051 [ # # ]: 0 : MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
2052 [ # # ]: 0 : for (i = 0; i < rqt_attr->rqt_actual_size; i++)
2053 [ # # ]: 0 : MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
2054 : 0 : ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out));
2055 : 0 : mlx5_free(in);
2056 [ # # ]: 0 : if (ret) {
2057 : 0 : DRV_LOG(ERR, "Failed to modify RQT using DevX.");
2058 : 0 : rte_errno = errno;
2059 : 0 : return -rte_errno;
2060 : : }
2061 : : return ret;
2062 : : }
2063 : :
2064 : : /**
2065 : : * Create SQ using DevX API.
2066 : : *
2067 : : * @param[in] ctx
2068 : : * Context returned from mlx5 open_device() glue function.
2069 : : * @param [in] sq_attr
2070 : : * Pointer to SQ attributes structure.
2071 : : * @param [in] socket
2072 : : * CPU socket ID for allocations.
2073 : : *
2074 : : * @return
2075 : : * The DevX object created, NULL otherwise and rte_errno is set.
2076 : : **/
2077 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_sq)
2078 : : struct mlx5_devx_obj *
2079 : 0 : mlx5_devx_cmd_create_sq(void *ctx,
2080 : : struct mlx5_devx_create_sq_attr *sq_attr)
2081 : : {
2082 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0};
2083 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0};
2084 : : void *sq_ctx;
2085 : : void *wq_ctx;
2086 : : struct mlx5_devx_wq_attr *wq_attr;
2087 : : struct mlx5_devx_obj *sq = NULL;
2088 : :
2089 : 0 : sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY);
2090 [ # # ]: 0 : if (!sq) {
2091 : 0 : DRV_LOG(ERR, "Failed to allocate SQ data");
2092 : 0 : rte_errno = ENOMEM;
2093 : 0 : return NULL;
2094 : : }
2095 [ # # ]: 0 : MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ);
2096 : : sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx);
2097 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky);
2098 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master);
2099 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre);
2100 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en);
2101 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe,
2102 : : sq_attr->allow_multi_pkt_send_wqe);
2103 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode,
2104 : : sq_attr->min_wqe_inline_mode);
2105 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
2106 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr);
2107 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp);
2108 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin);
2109 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire);
2110 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq);
2111 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, hairpin_wq_buffer_type, sq_attr->hairpin_wq_buffer_type);
2112 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index);
2113 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn);
2114 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index,
2115 : : sq_attr->packet_pacing_rate_limit_index);
2116 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz);
2117 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num);
2118 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format);
2119 : : wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq);
2120 : 0 : wq_attr = &sq_attr->wq_attr;
2121 : 0 : devx_cmd_fill_wq_data(wq_ctx, wq_attr);
2122 : 0 : sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2123 : : out, sizeof(out));
2124 [ # # ]: 0 : if (!sq->obj) {
2125 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create SQ", NULL, 0);
2126 : 0 : mlx5_free(sq);
2127 : 0 : return NULL;
2128 : : }
2129 [ # # ]: 0 : sq->id = MLX5_GET(create_sq_out, out, sqn);
2130 : 0 : return sq;
2131 : : }
2132 : :
2133 : : /**
2134 : : * Modify SQ using DevX API.
2135 : : *
2136 : : * @param[in] sq
2137 : : * Pointer to SQ object structure.
2138 : : * @param [in] sq_attr
2139 : : * Pointer to SQ attributes structure.
2140 : : *
2141 : : * @return
2142 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
2143 : : */
2144 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_modify_sq)
2145 : : int
2146 : 0 : mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
2147 : : struct mlx5_devx_modify_sq_attr *sq_attr)
2148 : : {
2149 : 0 : uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0};
2150 : 0 : uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0};
2151 : : void *sq_ctx;
2152 : : int ret;
2153 : :
2154 : 0 : MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ);
2155 : 0 : MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state);
2156 [ # # ]: 0 : MLX5_SET(modify_sq_in, in, sqn, sq->id);
2157 : : sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2158 : 0 : MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
2159 : 0 : MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq);
2160 : 0 : MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca);
2161 [ # # ]: 0 : if (sq_attr->rl_update) {
2162 : 0 : uint64_t msk = MLX5_GET64(modify_sq_in, in, modify_bitmask);
2163 : :
2164 : 0 : msk |= MLX5_MODIFY_SQ_IN_MODIFY_BITMASK_PACKET_PACING_RATE_LIMIT_INDEX;
2165 [ # # ]: 0 : MLX5_SET64(modify_sq_in, in, modify_bitmask, msk);
2166 : 0 : MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index,
2167 : : sq_attr->packet_pacing_rate_limit_index);
2168 : : }
2169 : 0 : ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in),
2170 : : out, sizeof(out));
2171 [ # # # # : 0 : if (ret || MLX5_FW_STATUS(out)) {
# # # # ]
2172 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "SQ modify", "sq_id", sq->id);
2173 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(ret);
2174 : : }
2175 : : return 0;
2176 : : }
2177 : :
2178 : : /*
2179 : : * Query SQ using DevX API.
2180 : : *
2181 : : * @param[in] sq_obj
2182 : : * SQ Devx Object
2183 : : * @param[out] out
2184 : : * SQ Query Output
2185 : : * @param[in] outlen
2186 : : * SQ Query Output Length
2187 : : *
2188 : : * @return
2189 : : * 0 if Query successful, else non-zero return value from devx_obj_query API
2190 : : */
2191 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_query_sq)
2192 : : int
2193 : 0 : mlx5_devx_cmd_query_sq(struct mlx5_devx_obj *sq_obj, void *out, size_t outlen)
2194 : : {
2195 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_sq_in)] = {0};
2196 : : int rc;
2197 : :
2198 : 0 : MLX5_SET(query_sq_in, in, opcode, MLX5_CMD_OP_QUERY_SQ);
2199 : 0 : MLX5_SET(query_sq_in, in, sqn, sq_obj->id);
2200 : 0 : rc = mlx5_glue->devx_obj_query(sq_obj->obj, in, sizeof(in), out, outlen);
2201 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
2202 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "SQ query", "sq_id", sq_obj->id);
2203 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
2204 : : }
2205 : : return 0;
2206 : : }
2207 : :
2208 : : /**
2209 : : * Create TIS using DevX API.
2210 : : *
2211 : : * @param[in] ctx
2212 : : * Context returned from mlx5 open_device() glue function.
2213 : : * @param [in] tis_attr
2214 : : * Pointer to TIS attributes structure.
2215 : : *
2216 : : * @return
2217 : : * The DevX object created, NULL otherwise and rte_errno is set.
2218 : : */
2219 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_tis)
2220 : : struct mlx5_devx_obj *
2221 : 0 : mlx5_devx_cmd_create_tis(void *ctx,
2222 : : struct mlx5_devx_tis_attr *tis_attr)
2223 : : {
2224 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2225 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0};
2226 : : struct mlx5_devx_obj *tis = NULL;
2227 : : void *tis_ctx;
2228 : :
2229 : 0 : tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY);
2230 [ # # ]: 0 : if (!tis) {
2231 : 0 : DRV_LOG(ERR, "Failed to allocate TIS object");
2232 : 0 : rte_errno = ENOMEM;
2233 : 0 : return NULL;
2234 : : }
2235 [ # # ]: 0 : MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS);
2236 : : tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx);
2237 [ # # ]: 0 : MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,
2238 : : tis_attr->strict_lag_tx_port_affinity);
2239 [ # # ]: 0 : MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity,
2240 : : tis_attr->lag_tx_port_affinity);
2241 [ # # ]: 0 : MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio);
2242 [ # # ]: 0 : MLX5_SET(tisc, tis_ctx, transport_domain,
2243 : : tis_attr->transport_domain);
2244 : 0 : tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2245 : : out, sizeof(out));
2246 [ # # ]: 0 : if (!tis->obj) {
2247 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create TIS", NULL, 0);
2248 : 0 : mlx5_free(tis);
2249 : 0 : return NULL;
2250 : : }
2251 [ # # ]: 0 : tis->id = MLX5_GET(create_tis_out, out, tisn);
2252 : 0 : return tis;
2253 : : }
2254 : :
2255 : : /**
2256 : : * Create transport domain using DevX API.
2257 : : *
2258 : : * @param[in] ctx
2259 : : * Context returned from mlx5 open_device() glue function.
2260 : : * @return
2261 : : * The DevX object created, NULL otherwise and rte_errno is set.
2262 : : */
2263 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_td)
2264 : : struct mlx5_devx_obj *
2265 : 0 : mlx5_devx_cmd_create_td(void *ctx)
2266 : : {
2267 : 0 : uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0};
2268 : 0 : uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0};
2269 : : struct mlx5_devx_obj *td = NULL;
2270 : :
2271 : 0 : td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY);
2272 [ # # ]: 0 : if (!td) {
2273 : 0 : DRV_LOG(ERR, "Failed to allocate TD object");
2274 : 0 : rte_errno = ENOMEM;
2275 : 0 : return NULL;
2276 : : }
2277 [ # # ]: 0 : MLX5_SET(alloc_transport_domain_in, in, opcode,
2278 : : MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN);
2279 : 0 : td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2280 : : out, sizeof(out));
2281 [ # # ]: 0 : if (!td->obj) {
2282 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create TIS", NULL, 0);
2283 : 0 : mlx5_free(td);
2284 : 0 : return NULL;
2285 : : }
2286 [ # # ]: 0 : td->id = MLX5_GET(alloc_transport_domain_out, out,
2287 : : transport_domain);
2288 : 0 : return td;
2289 : : }
2290 : :
2291 : : /**
2292 : : * Dump all flows to file.
2293 : : *
2294 : : * @param[in] fdb_domain
2295 : : * FDB domain.
2296 : : * @param[in] rx_domain
2297 : : * RX domain.
2298 : : * @param[in] tx_domain
2299 : : * TX domain.
2300 : : * @param[out] file
2301 : : * Pointer to file stream.
2302 : : *
2303 : : * @return
2304 : : * 0 on success, a negative value otherwise.
2305 : : */
2306 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_flow_dump)
2307 : : int
2308 : 0 : mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused,
2309 : : void *rx_domain __rte_unused,
2310 : : void *tx_domain __rte_unused, FILE *file __rte_unused)
2311 : : {
2312 : : int ret = 0;
2313 : :
2314 : : #ifdef HAVE_MLX5_DR_FLOW_DUMP
2315 [ # # ]: 0 : if (fdb_domain) {
2316 : 0 : ret = mlx5_glue->dr_dump_domain(file, fdb_domain);
2317 [ # # ]: 0 : if (ret)
2318 : : return ret;
2319 : : }
2320 : : MLX5_ASSERT(rx_domain);
2321 : 0 : ret = mlx5_glue->dr_dump_domain(file, rx_domain);
2322 [ # # ]: 0 : if (ret)
2323 : : return ret;
2324 : : MLX5_ASSERT(tx_domain);
2325 : 0 : ret = mlx5_glue->dr_dump_domain(file, tx_domain);
2326 : : #else
2327 : : ret = ENOTSUP;
2328 : : #endif
2329 : 0 : return -ret;
2330 : : }
2331 : :
2332 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_flow_single_dump)
2333 : : int
2334 : 0 : mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused,
2335 : : FILE *file __rte_unused)
2336 : : {
2337 : : int ret = 0;
2338 : : #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE
2339 [ # # ]: 0 : if (rule_info)
2340 : 0 : ret = mlx5_glue->dr_dump_rule(file, rule_info);
2341 : : #else
2342 : : ret = ENOTSUP;
2343 : : #endif
2344 : 0 : return -ret;
2345 : : }
2346 : :
2347 : : /*
2348 : : * Create CQ using DevX API.
2349 : : *
2350 : : * @param[in] ctx
2351 : : * Context returned from mlx5 open_device() glue function.
2352 : : * @param [in] attr
2353 : : * Pointer to CQ attributes structure.
2354 : : *
2355 : : * @return
2356 : : * The DevX object created, NULL otherwise and rte_errno is set.
2357 : : */
2358 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_cq)
2359 : : struct mlx5_devx_obj *
2360 : 0 : mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr)
2361 : : {
2362 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0};
2363 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0};
2364 : 0 : struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO,
2365 : : sizeof(*cq_obj),
2366 : : 0, SOCKET_ID_ANY);
2367 : : void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context);
2368 : :
2369 [ # # ]: 0 : if (!cq_obj) {
2370 : 0 : DRV_LOG(ERR, "Failed to allocate CQ object memory.");
2371 : 0 : rte_errno = ENOMEM;
2372 : 0 : return NULL;
2373 : : }
2374 [ # # ]: 0 : MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ);
2375 [ # # ]: 0 : if (attr->db_umem_valid) {
2376 [ # # ]: 0 : MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid);
2377 [ # # ]: 0 : MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id);
2378 [ # # ]: 0 : MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset);
2379 : : } else {
2380 [ # # ]: 0 : MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr);
2381 : : }
2382 [ # # ]: 0 : MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ?
2383 : : MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B);
2384 [ # # ]: 0 : MLX5_SET(cqc, cqctx, cc, attr->use_first_only);
2385 [ # # ]: 0 : MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore);
2386 [ # # ]: 0 : MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size);
2387 [ # # ]: 0 : if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)
2388 [ # # ]: 0 : MLX5_SET(cqc, cqctx, log_page_size,
2389 : : attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT);
2390 [ # # ]: 0 : MLX5_SET(cqc, cqctx, c_eqn, attr->eqn);
2391 [ # # ]: 0 : MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id);
2392 [ # # ]: 0 : MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en);
2393 [ # # ]: 0 : MLX5_SET(cqc, cqctx, cqe_comp_layout, !!attr->cqe_comp_layout);
2394 [ # # ]: 0 : MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format);
2395 [ # # ]: 0 : MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext,
2396 : : attr->mini_cqe_res_format_ext);
2397 [ # # ]: 0 : if (attr->q_umem_valid) {
2398 [ # # ]: 0 : MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid);
2399 [ # # ]: 0 : MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id);
2400 [ # # ]: 0 : MLX5_SET64(create_cq_in, in, cq_umem_offset,
2401 : : attr->q_umem_offset);
2402 : : }
2403 : 0 : cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2404 : : sizeof(out));
2405 [ # # ]: 0 : if (!cq_obj->obj) {
2406 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create CQ", NULL, 0);
2407 : 0 : mlx5_free(cq_obj);
2408 : 0 : return NULL;
2409 : : }
2410 [ # # ]: 0 : cq_obj->id = MLX5_GET(create_cq_out, out, cqn);
2411 : 0 : return cq_obj;
2412 : : }
2413 : :
2414 : : /*
2415 : : * Query CQ using DevX API.
2416 : : *
2417 : : * @param[in] cq_obj
2418 : : * CQ Devx Object
2419 : : * @param[out] out
2420 : : * CQ Query Output
2421 : : * @param[in] outlen
2422 : : * CQ Query Output Length
2423 : : *
2424 : : * @return
2425 : : * 0 if Query successful, else non-zero return value from devx_obj_query API
2426 : : */
2427 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_query_cq)
2428 : : int
2429 : 0 : mlx5_devx_cmd_query_cq(struct mlx5_devx_obj *cq_obj, void *out, size_t outlen)
2430 : : {
2431 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_cq_in)] = {0};
2432 : : int rc;
2433 : :
2434 : 0 : MLX5_SET(query_cq_in, in, opcode, MLX5_CMD_OP_QUERY_CQ);
2435 : 0 : MLX5_SET(query_cq_in, in, cqn, cq_obj->id);
2436 : 0 : rc = mlx5_glue->devx_obj_query(cq_obj->obj, in, sizeof(in), out, outlen);
2437 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
2438 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "CQ query", "cq_id", cq_obj->id);
2439 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
2440 : : }
2441 : : return 0;
2442 : : }
2443 : :
2444 : : /**
2445 : : * Create VIRTQ using DevX API.
2446 : : *
2447 : : * @param[in] ctx
2448 : : * Context returned from mlx5 open_device() glue function.
2449 : : * @param [in] attr
2450 : : * Pointer to VIRTQ attributes structure.
2451 : : *
2452 : : * @return
2453 : : * The DevX object created, NULL otherwise and rte_errno is set.
2454 : : */
2455 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_virtq)
2456 : : struct mlx5_devx_obj *
2457 : 0 : mlx5_devx_cmd_create_virtq(void *ctx,
2458 : : struct mlx5_devx_virtq_attr *attr)
2459 : : {
2460 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
2461 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2462 : 0 : struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO,
2463 : : sizeof(*virtq_obj),
2464 : : 0, SOCKET_ID_ANY);
2465 : : void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
2466 : : void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
2467 : : void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
2468 : :
2469 [ # # ]: 0 : if (!virtq_obj) {
2470 : 0 : DRV_LOG(ERR, "Failed to allocate virtq data.");
2471 : 0 : rte_errno = ENOMEM;
2472 : 0 : return NULL;
2473 : : }
2474 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2475 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2476 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2477 : : MLX5_GENERAL_OBJ_TYPE_VIRTQ);
2478 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, hw_available_index,
2479 : : attr->hw_available_index);
2480 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index);
2481 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4);
2482 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6);
2483 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum);
2484 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum);
2485 [ # # ]: 0 : MLX5_SET16(virtio_q, virtctx, virtio_version_1_0,
2486 : : attr->virtio_version_1_0);
2487 [ # # ]: 0 : MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode);
2488 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id);
2489 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr);
2490 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr);
2491 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr);
2492 [ # # ]: 0 : MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
2493 [ # # ]: 0 : MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size);
2494 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey);
2495 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id);
2496 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size);
2497 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset);
2498 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id);
2499 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size);
2500 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset);
2501 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id);
2502 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size);
2503 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset);
2504 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id);
2505 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, pd, attr->pd);
2506 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode);
2507 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us);
2508 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp);
2509 [ # # ]: 0 : MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id);
2510 : 0 : virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2511 : : sizeof(out));
2512 [ # # ]: 0 : if (!virtq_obj->obj) {
2513 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create VIRTQ", NULL, 0);
2514 : 0 : mlx5_free(virtq_obj);
2515 : 0 : return NULL;
2516 : : }
2517 [ # # ]: 0 : virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2518 : 0 : return virtq_obj;
2519 : : }
2520 : :
2521 : : /**
2522 : : * Modify VIRTQ using DevX API.
2523 : : *
2524 : : * @param[in] virtq_obj
2525 : : * Pointer to virtq object structure.
2526 : : * @param [in] attr
2527 : : * Pointer to modify virtq attributes structure.
2528 : : *
2529 : : * @return
2530 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
2531 : : */
2532 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_modify_virtq)
2533 : : int
2534 : 0 : mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,
2535 : : struct mlx5_devx_virtq_attr *attr)
2536 : : {
2537 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
2538 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2539 : : void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
2540 : : void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
2541 : : void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
2542 : : int ret;
2543 : :
2544 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2545 : : MLX5_CMD_OP_MODIFY_GENERAL_OBJECT);
2546 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2547 : : MLX5_GENERAL_OBJ_TYPE_VIRTQ);
2548 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
2549 [ # # ]: 0 : MLX5_SET64(virtio_net_q, virtq, modify_field_select,
2550 : : attr->mod_fields_bitmap);
2551 : 0 : MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
2552 [ # # ]: 0 : if (!attr->mod_fields_bitmap) {
2553 : 0 : DRV_LOG(ERR, "Failed to modify VIRTQ for no type set.");
2554 : 0 : rte_errno = EINVAL;
2555 : 0 : return -rte_errno;
2556 : : }
2557 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_STATE)
2558 : 0 : MLX5_SET16(virtio_net_q, virtq, state, attr->state);
2559 [ # # ]: 0 : if (attr->mod_fields_bitmap &
2560 : : MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS) {
2561 : 0 : MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey,
2562 : : attr->dirty_bitmap_mkey);
2563 [ # # ]: 0 : MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr,
2564 : : attr->dirty_bitmap_addr);
2565 : 0 : MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size,
2566 : : attr->dirty_bitmap_size);
2567 : : }
2568 [ # # ]: 0 : if (attr->mod_fields_bitmap &
2569 : : MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE)
2570 [ # # ]: 0 : MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable,
2571 : : attr->dirty_bitmap_dump_enable);
2572 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_QUEUE_PERIOD) {
2573 : 0 : MLX5_SET(virtio_q, virtctx, queue_period_mode,
2574 : : attr->hw_latency_mode);
2575 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, queue_period_us,
2576 : : attr->hw_max_latency_us);
2577 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, queue_max_count,
2578 : : attr->hw_max_pending_comp);
2579 : : }
2580 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_ADDR) {
2581 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr);
2582 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr);
2583 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, available_addr,
2584 : : attr->available_addr);
2585 : : }
2586 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_AVAILABLE_INDEX)
2587 : 0 : MLX5_SET16(virtio_net_q, virtq, hw_available_index,
2588 : : attr->hw_available_index);
2589 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_USED_INDEX)
2590 : 0 : MLX5_SET16(virtio_net_q, virtq, hw_used_index,
2591 : : attr->hw_used_index);
2592 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_TYPE)
2593 : 0 : MLX5_SET16(virtio_q, virtctx, virtio_q_type, attr->q_type);
2594 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_VERSION_1_0)
2595 : 0 : MLX5_SET16(virtio_q, virtctx, virtio_version_1_0,
2596 : : attr->virtio_version_1_0);
2597 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_MKEY)
2598 : 0 : MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey);
2599 [ # # ]: 0 : if (attr->mod_fields_bitmap &
2600 : : MLX5_VIRTQ_MODIFY_TYPE_QUEUE_FEATURE_BIT_MASK) {
2601 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4);
2602 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6);
2603 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum);
2604 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum);
2605 : : }
2606 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_EVENT_MODE) {
2607 [ # # ]: 0 : MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode);
2608 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id);
2609 : : }
2610 : 0 : ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in),
2611 : : out, sizeof(out));
2612 [ # # ]: 0 : if (ret) {
2613 : 0 : DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
2614 : 0 : rte_errno = errno;
2615 : 0 : return -rte_errno;
2616 : : }
2617 : : return ret;
2618 : : }
2619 : :
2620 : : /**
2621 : : * Query VIRTQ using DevX API.
2622 : : *
2623 : : * @param[in] virtq_obj
2624 : : * Pointer to virtq object structure.
2625 : : * @param [in/out] attr
2626 : : * Pointer to virtq attributes structure.
2627 : : *
2628 : : * @return
2629 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
2630 : : */
2631 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_query_virtq)
2632 : : int
2633 : 0 : mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,
2634 : : struct mlx5_devx_virtq_attr *attr)
2635 : : {
2636 : 0 : uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
2637 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0};
2638 : : void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr);
2639 : : void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq);
2640 : : int ret;
2641 : :
2642 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2643 : : MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
2644 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2645 : : MLX5_GENERAL_OBJ_TYPE_VIRTQ);
2646 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
2647 : 0 : ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in),
2648 : : out, sizeof(out));
2649 [ # # ]: 0 : if (ret) {
2650 : 0 : DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
2651 : 0 : rte_errno = errno;
2652 : 0 : return -errno;
2653 : : }
2654 [ # # ]: 0 : attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq,
2655 : : hw_available_index);
2656 [ # # ]: 0 : attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index);
2657 [ # # ]: 0 : attr->state = MLX5_GET16(virtio_net_q, virtq, state);
2658 [ # # ]: 0 : attr->error_type = MLX5_GET16(virtio_net_q, virtq,
2659 : : virtio_q_context.error_type);
2660 : 0 : return ret;
2661 : : }
2662 : :
2663 : : /**
2664 : : * Create QP using DevX API.
2665 : : *
2666 : : * @param[in] ctx
2667 : : * Context returned from mlx5 open_device() glue function.
2668 : : * @param [in] attr
2669 : : * Pointer to QP attributes structure.
2670 : : *
2671 : : * @return
2672 : : * The DevX object created, NULL otherwise and rte_errno is set.
2673 : : */
2674 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_qp)
2675 : : struct mlx5_devx_obj *
2676 : 0 : mlx5_devx_cmd_create_qp(void *ctx,
2677 : : struct mlx5_devx_qp_attr *attr)
2678 : : {
2679 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0};
2680 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0};
2681 : 0 : struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO,
2682 : : sizeof(*qp_obj),
2683 : : 0, SOCKET_ID_ANY);
2684 : : void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
2685 : :
2686 [ # # ]: 0 : if (!qp_obj) {
2687 : 0 : DRV_LOG(ERR, "Failed to allocate QP data.");
2688 : 0 : rte_errno = ENOMEM;
2689 : 0 : return NULL;
2690 : : }
2691 [ # # ]: 0 : MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP);
2692 [ # # ]: 0 : MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC);
2693 [ # # ]: 0 : MLX5_SET(qpc, qpc, pd, attr->pd);
2694 [ # # ]: 0 : MLX5_SET(qpc, qpc, ts_format, attr->ts_format);
2695 [ # # ]: 0 : MLX5_SET(qpc, qpc, user_index, attr->user_index);
2696 [ # # ]: 0 : if (attr->uar_index) {
2697 [ # # ]: 0 : if (attr->mmo) {
2698 : : void *qpc_ext_and_pas_list = MLX5_ADDR_OF(create_qp_in,
2699 : : in, qpc_extension_and_pas_list);
2700 : : void *qpc_ext = MLX5_ADDR_OF(qpc_extension_and_pas_list,
2701 : : qpc_ext_and_pas_list, qpc_data_extension);
2702 : :
2703 [ # # ]: 0 : MLX5_SET(create_qp_in, in, qpc_ext, 1);
2704 [ # # ]: 0 : MLX5_SET(qpc_extension, qpc_ext, mmo, 1);
2705 : : }
2706 [ # # ]: 0 : MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2707 [ # # ]: 0 : MLX5_SET(qpc, qpc, uar_page, attr->uar_index);
2708 [ # # ]: 0 : if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)
2709 [ # # ]: 0 : MLX5_SET(qpc, qpc, log_page_size,
2710 : : attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT);
2711 [ # # ]: 0 : if (attr->num_of_send_wqbbs) {
2712 : : MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->num_of_send_wqbbs));
2713 [ # # ]: 0 : MLX5_SET(qpc, qpc, cqn_snd, attr->cqn);
2714 [ # # ]: 0 : MLX5_SET(qpc, qpc, log_sq_size,
2715 : : rte_log2_u32(attr->num_of_send_wqbbs));
2716 : : } else {
2717 [ # # ]: 0 : MLX5_SET(qpc, qpc, no_sq, 1);
2718 : : }
2719 [ # # ]: 0 : if (attr->num_of_receive_wqes) {
2720 : : MLX5_ASSERT(RTE_IS_POWER_OF_2(
2721 : : attr->num_of_receive_wqes));
2722 [ # # ]: 0 : MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn);
2723 [ # # ]: 0 : MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride -
2724 : : MLX5_LOG_RQ_STRIDE_SHIFT);
2725 [ # # # # ]: 0 : MLX5_SET(qpc, qpc, log_rq_size,
2726 : : rte_log2_u32(attr->num_of_receive_wqes));
2727 [ # # ]: 0 : MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ);
2728 : : } else {
2729 [ # # ]: 0 : MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
2730 : : }
2731 [ # # ]: 0 : if (attr->dbr_umem_valid) {
2732 [ # # ]: 0 : MLX5_SET(qpc, qpc, dbr_umem_valid,
2733 : : attr->dbr_umem_valid);
2734 [ # # ]: 0 : MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id);
2735 : : }
2736 [ # # ]: 0 : if (attr->cd_master)
2737 [ # # ]: 0 : MLX5_SET(qpc, qpc, cd_master, attr->cd_master);
2738 [ # # ]: 0 : if (attr->cd_slave_send)
2739 [ # # ]: 0 : MLX5_SET(qpc, qpc, cd_slave_send, attr->cd_slave_send);
2740 [ # # ]: 0 : if (attr->cd_slave_recv)
2741 [ # # ]: 0 : MLX5_SET(qpc, qpc, cd_slave_receive, attr->cd_slave_recv);
2742 [ # # ]: 0 : MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address);
2743 [ # # ]: 0 : MLX5_SET64(create_qp_in, in, wq_umem_offset,
2744 : : attr->wq_umem_offset);
2745 [ # # ]: 0 : MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id);
2746 [ # # ]: 0 : MLX5_SET(create_qp_in, in, wq_umem_valid, 1);
2747 : : } else {
2748 : : /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */
2749 [ # # ]: 0 : MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
2750 [ # # ]: 0 : MLX5_SET(qpc, qpc, no_sq, 1);
2751 : : }
2752 : 0 : qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2753 : : sizeof(out));
2754 [ # # ]: 0 : if (!qp_obj->obj) {
2755 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create QP", NULL, 0);
2756 : 0 : mlx5_free(qp_obj);
2757 : 0 : return NULL;
2758 : : }
2759 [ # # ]: 0 : qp_obj->id = MLX5_GET(create_qp_out, out, qpn);
2760 : 0 : return qp_obj;
2761 : : }
2762 : :
2763 : : /**
2764 : : * Modify QP using DevX API.
2765 : : * Currently supports only force loop-back QP.
2766 : : *
2767 : : * @param[in] qp
2768 : : * Pointer to QP object structure.
2769 : : * @param [in] qp_st_mod_op
2770 : : * The QP state modification operation.
2771 : : * @param [in] remote_qp_id
2772 : : * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation.
2773 : : *
2774 : : * @return
2775 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
2776 : : */
2777 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_modify_qp_state)
2778 : : int
2779 : 0 : mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op,
2780 : : uint32_t remote_qp_id)
2781 : : {
2782 : : union {
2783 : : uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)];
2784 : : uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)];
2785 : : uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)];
2786 : : uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_in)];
2787 : : } in;
2788 : : union {
2789 : : uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)];
2790 : : uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)];
2791 : : uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)];
2792 : : uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_out)];
2793 : : } out;
2794 : : void *qpc;
2795 : : int ret;
2796 : : unsigned int inlen;
2797 : : unsigned int outlen;
2798 : :
2799 : : memset(&in, 0, sizeof(in));
2800 : : memset(&out, 0, sizeof(out));
2801 : 0 : MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op);
2802 [ # # # # : 0 : switch (qp_st_mod_op) {
# ]
2803 : 0 : case MLX5_CMD_OP_RST2INIT_QP:
2804 : 0 : MLX5_SET(rst2init_qp_in, &in, qpn, qp->id);
2805 : : qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc);
2806 : 0 : MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
2807 : : MLX5_SET(qpc, qpc, rre, 1);
2808 [ # # ]: 0 : MLX5_SET(qpc, qpc, rwe, 1);
2809 : 0 : MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2810 : : inlen = sizeof(in.rst2init);
2811 : : outlen = sizeof(out.rst2init);
2812 : 0 : break;
2813 : 0 : case MLX5_CMD_OP_INIT2RTR_QP:
2814 : 0 : MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id);
2815 : : qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc);
2816 : 0 : MLX5_SET(qpc, qpc, primary_address_path.fl, 1);
2817 : 0 : MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
2818 : : MLX5_SET(qpc, qpc, mtu, 1);
2819 [ # # ]: 0 : MLX5_SET(qpc, qpc, log_msg_max, 30);
2820 : 0 : MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id);
2821 : 0 : MLX5_SET(qpc, qpc, min_rnr_nak, 0);
2822 : : inlen = sizeof(in.init2rtr);
2823 : : outlen = sizeof(out.init2rtr);
2824 : 0 : break;
2825 : 0 : case MLX5_CMD_OP_RTR2RTS_QP:
2826 : : qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc);
2827 : 0 : MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id);
2828 : 0 : MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 16);
2829 : : MLX5_SET(qpc, qpc, log_ack_req_freq, 0);
2830 [ # # ]: 0 : MLX5_SET(qpc, qpc, retry_count, 7);
2831 [ # # ]: 0 : MLX5_SET(qpc, qpc, rnr_retry, 7);
2832 : : inlen = sizeof(in.rtr2rts);
2833 : : outlen = sizeof(out.rtr2rts);
2834 : 0 : break;
2835 : 0 : case MLX5_CMD_OP_QP_2RST:
2836 : 0 : MLX5_SET(2rst_qp_in, &in, qpn, qp->id);
2837 : : inlen = sizeof(in.qp2rst);
2838 : : outlen = sizeof(out.qp2rst);
2839 : 0 : break;
2840 : 0 : default:
2841 : 0 : DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.",
2842 : : qp_st_mod_op);
2843 : 0 : rte_errno = EINVAL;
2844 : 0 : return -rte_errno;
2845 : : }
2846 : 0 : ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen);
2847 [ # # ]: 0 : if (ret) {
2848 : 0 : DRV_LOG(ERR, "Failed to modify QP using DevX.");
2849 : 0 : rte_errno = errno;
2850 : 0 : return -rte_errno;
2851 : : }
2852 : : return ret;
2853 : : }
2854 : :
2855 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_virtio_q_counters)
2856 : : struct mlx5_devx_obj *
2857 : 0 : mlx5_devx_cmd_create_virtio_q_counters(void *ctx)
2858 : : {
2859 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0};
2860 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2861 : 0 : struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO,
2862 : : sizeof(*couners_obj), 0,
2863 : : SOCKET_ID_ANY);
2864 : : void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr);
2865 : :
2866 [ # # ]: 0 : if (!couners_obj) {
2867 : 0 : DRV_LOG(ERR, "Failed to allocate virtio queue counters data.");
2868 : 0 : rte_errno = ENOMEM;
2869 : 0 : return NULL;
2870 : : }
2871 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2872 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2873 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2874 : : MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
2875 : 0 : couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2876 : : sizeof(out));
2877 [ # # ]: 0 : if (!couners_obj->obj) {
2878 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create virtio queue counters Obj", NULL,
2879 : : 0);
2880 : 0 : mlx5_free(couners_obj);
2881 : 0 : return NULL;
2882 : : }
2883 [ # # ]: 0 : couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2884 : 0 : return couners_obj;
2885 : : }
2886 : :
2887 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_query_virtio_q_counters)
2888 : : int
2889 : 0 : mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,
2890 : : struct mlx5_devx_virtio_q_couners_attr *attr)
2891 : : {
2892 : 0 : uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
2893 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0};
2894 : : void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr);
2895 : : void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out,
2896 : : virtio_q_counters);
2897 : : int ret;
2898 : :
2899 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2900 : : MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
2901 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2902 : : MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
2903 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id);
2904 : 0 : ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out,
2905 : : sizeof(out));
2906 [ # # ]: 0 : if (ret) {
2907 : 0 : DRV_LOG(ERR, "Failed to query virtio q counters using DevX.");
2908 : 0 : rte_errno = errno;
2909 : 0 : return -errno;
2910 : : }
2911 [ # # ]: 0 : attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
2912 : : received_desc);
2913 [ # # ]: 0 : attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
2914 : : completed_desc);
2915 [ # # ]: 0 : attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters,
2916 : : error_cqes);
2917 [ # # ]: 0 : attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters,
2918 : : bad_desc_errors);
2919 [ # # ]: 0 : attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters,
2920 : : exceed_max_chain);
2921 [ # # ]: 0 : attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters,
2922 : : invalid_buffer);
2923 : 0 : return ret;
2924 : : }
2925 : :
2926 : : /**
2927 : : * Create general object of type FLOW_HIT_ASO using DevX API.
2928 : : *
2929 : : * @param[in] ctx
2930 : : * Context returned from mlx5 open_device() glue function.
2931 : : * @param [in] pd
2932 : : * PD value to associate the FLOW_HIT_ASO object with.
2933 : : *
2934 : : * @return
2935 : : * The DevX object created, NULL otherwise and rte_errno is set.
2936 : : */
2937 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_flow_hit_aso_obj)
2938 : : struct mlx5_devx_obj *
2939 : 0 : mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd)
2940 : : {
2941 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0};
2942 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2943 : : struct mlx5_devx_obj *flow_hit_aso_obj = NULL;
2944 : : void *ptr = NULL;
2945 : :
2946 : 0 : flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj),
2947 : : 0, SOCKET_ID_ANY);
2948 [ # # ]: 0 : if (!flow_hit_aso_obj) {
2949 : 0 : DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data");
2950 : 0 : rte_errno = ENOMEM;
2951 : 0 : return NULL;
2952 : : }
2953 : : ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr);
2954 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2955 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2956 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2957 : : MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO);
2958 : : ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso);
2959 [ # # ]: 0 : MLX5_SET(flow_hit_aso, ptr, access_pd, pd);
2960 : 0 : flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2961 : : out, sizeof(out));
2962 [ # # ]: 0 : if (!flow_hit_aso_obj->obj) {
2963 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create FLOW_HIT_ASO", NULL, 0);
2964 : 0 : mlx5_free(flow_hit_aso_obj);
2965 : 0 : return NULL;
2966 : : }
2967 [ # # ]: 0 : flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2968 : 0 : return flow_hit_aso_obj;
2969 : : }
2970 : :
2971 : : /*
2972 : : * Create PD using DevX API.
2973 : : *
2974 : : * @param[in] ctx
2975 : : * Context returned from mlx5 open_device() glue function.
2976 : : *
2977 : : * @return
2978 : : * The DevX object created, NULL otherwise and rte_errno is set.
2979 : : */
2980 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_alloc_pd)
2981 : : struct mlx5_devx_obj *
2982 : 0 : mlx5_devx_cmd_alloc_pd(void *ctx)
2983 : : {
2984 : : struct mlx5_devx_obj *ppd =
2985 : 0 : mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY);
2986 : 0 : u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0};
2987 : 0 : u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0};
2988 : :
2989 [ # # ]: 0 : if (!ppd) {
2990 : 0 : DRV_LOG(ERR, "Failed to allocate PD data.");
2991 : 0 : rte_errno = ENOMEM;
2992 : 0 : return NULL;
2993 : : }
2994 : 0 : MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2995 : 0 : ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2996 : : out, sizeof(out));
2997 [ # # ]: 0 : if (!ppd->obj) {
2998 : 0 : mlx5_free(ppd);
2999 : 0 : DRV_LOG(ERR, "Failed to allocate PD Obj using DevX.");
3000 : 0 : rte_errno = errno;
3001 : 0 : return NULL;
3002 : : }
3003 [ # # ]: 0 : ppd->id = MLX5_GET(alloc_pd_out, out, pd);
3004 : 0 : return ppd;
3005 : : }
3006 : :
3007 : : /**
3008 : : * Create general object of type FLOW_METER_ASO using DevX API.
3009 : : *
3010 : : * @param[in] ctx
3011 : : * Context returned from mlx5 open_device() glue function.
3012 : : * @param [in] pd
3013 : : * PD value to associate the FLOW_METER_ASO object with.
3014 : : * @param [in] log_obj_size
3015 : : * log_obj_size define to allocate number of 2 * meters
3016 : : * in one FLOW_METER_ASO object.
3017 : : *
3018 : : * @return
3019 : : * The DevX object created, NULL otherwise and rte_errno is set.
3020 : : */
3021 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_flow_meter_aso_obj)
3022 : : struct mlx5_devx_obj *
3023 : 0 : mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd,
3024 : : uint32_t log_obj_size)
3025 : : {
3026 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0};
3027 : : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
3028 : : struct mlx5_devx_obj *flow_meter_aso_obj;
3029 : : void *ptr;
3030 : :
3031 : 0 : flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO,
3032 : : sizeof(*flow_meter_aso_obj),
3033 : : 0, SOCKET_ID_ANY);
3034 [ # # ]: 0 : if (!flow_meter_aso_obj) {
3035 : 0 : DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data");
3036 : 0 : rte_errno = ENOMEM;
3037 : 0 : return NULL;
3038 : : }
3039 : : ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr);
3040 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
3041 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
3042 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
3043 : : MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO);
3044 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range,
3045 : : log_obj_size);
3046 : : ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso);
3047 [ # # ]: 0 : MLX5_SET(flow_meter_aso, ptr, access_pd, pd);
3048 : 0 : flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create(
3049 : : ctx, in, sizeof(in),
3050 : : out, sizeof(out));
3051 [ # # ]: 0 : if (!flow_meter_aso_obj->obj) {
3052 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create FLOW_METTER_ASO", NULL, 0);
3053 : 0 : mlx5_free(flow_meter_aso_obj);
3054 : 0 : return NULL;
3055 : : }
3056 [ # # ]: 0 : flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr,
3057 : : out, obj_id);
3058 : 0 : return flow_meter_aso_obj;
3059 : : }
3060 : :
3061 : : /*
3062 : : * Create general object of type CONN_TRACK_OFFLOAD using DevX API.
3063 : : *
3064 : : * @param[in] ctx
3065 : : * Context returned from mlx5 open_device() glue function.
3066 : : * @param [in] pd
3067 : : * PD value to associate the CONN_TRACK_OFFLOAD ASO object with.
3068 : : * @param [in] log_obj_size
3069 : : * log_obj_size to allocate its power of 2 * objects
3070 : : * in one CONN_TRACK_OFFLOAD bulk allocation.
3071 : : *
3072 : : * @return
3073 : : * The DevX object created, NULL otherwise and rte_errno is set.
3074 : : */
3075 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_conn_track_offload_obj)
3076 : : struct mlx5_devx_obj *
3077 : 0 : mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, uint32_t pd,
3078 : : uint32_t log_obj_size)
3079 : : {
3080 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_conn_track_aso_in)] = {0};
3081 : : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
3082 : : struct mlx5_devx_obj *ct_aso_obj;
3083 : : void *ptr;
3084 : :
3085 : 0 : ct_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ct_aso_obj),
3086 : : 0, SOCKET_ID_ANY);
3087 [ # # ]: 0 : if (!ct_aso_obj) {
3088 : 0 : DRV_LOG(ERR, "Failed to allocate CONN_TRACK_OFFLOAD object.");
3089 : 0 : rte_errno = ENOMEM;
3090 : 0 : return NULL;
3091 : : }
3092 : : ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, hdr);
3093 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
3094 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
3095 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
3096 : : MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD);
3097 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, log_obj_size);
3098 : : ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, conn_track_offload);
3099 [ # # ]: 0 : MLX5_SET(conn_track_offload, ptr, conn_track_aso_access_pd, pd);
3100 : 0 : ct_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
3101 : : out, sizeof(out));
3102 [ # # ]: 0 : if (!ct_aso_obj->obj) {
3103 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create CONN_TRACK_OFFLOAD", NULL, 0);
3104 : 0 : mlx5_free(ct_aso_obj);
3105 : 0 : return NULL;
3106 : : }
3107 [ # # ]: 0 : ct_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
3108 : 0 : return ct_aso_obj;
3109 : : }
3110 : :
3111 : : /**
3112 : : * Create general object of type GENEVE TLV option using DevX API.
3113 : : *
3114 : : * @param[in] ctx
3115 : : * Context returned from mlx5 open_device() glue function.
3116 : : * @param[in] attr
3117 : : * Pointer to GENEVE TLV option attributes structure.
3118 : : *
3119 : : * @return
3120 : : * The DevX object created, NULL otherwise and rte_errno is set.
3121 : : */
3122 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_geneve_tlv_option)
3123 : : struct mlx5_devx_obj *
3124 : 0 : mlx5_devx_cmd_create_geneve_tlv_option(void *ctx,
3125 : : struct mlx5_devx_geneve_tlv_option_attr *attr)
3126 : : {
3127 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0};
3128 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
3129 : 0 : struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO,
3130 : : sizeof(*geneve_tlv_opt_obj),
3131 : : 0, SOCKET_ID_ANY);
3132 : :
3133 [ # # ]: 0 : if (!geneve_tlv_opt_obj) {
3134 : 0 : DRV_LOG(ERR, "Failed to allocate GENEVE TLV option object.");
3135 : 0 : rte_errno = ENOMEM;
3136 : 0 : return NULL;
3137 : : }
3138 : : void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr);
3139 : : void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in,
3140 : : geneve_tlv_opt);
3141 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
3142 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
3143 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
3144 : : MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT);
3145 [ # # ]: 0 : MLX5_SET(geneve_tlv_option, opt, option_type, attr->option_type);
3146 [ # # ]: 0 : MLX5_SET(geneve_tlv_option, opt, option_data_length,
3147 : : attr->option_data_len);
3148 [ # # ]: 0 : if (attr->option_class_ignore)
3149 [ # # ]: 0 : MLX5_SET(geneve_tlv_option, opt, option_class_ignore,
3150 : : attr->option_class_ignore);
3151 : : else
3152 [ # # # # ]: 0 : MLX5_SET(geneve_tlv_option, opt, option_class,
3153 : : rte_be_to_cpu_16(attr->option_class));
3154 [ # # ]: 0 : if (attr->offset_valid) {
3155 [ # # ]: 0 : MLX5_SET(geneve_tlv_option, opt, sample_offset_valid,
3156 : : attr->offset_valid);
3157 [ # # ]: 0 : MLX5_SET(geneve_tlv_option, opt, sample_offset,
3158 : : attr->sample_offset);
3159 : : }
3160 : 0 : geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in,
3161 : : sizeof(in), out,
3162 : : sizeof(out));
3163 [ # # ]: 0 : if (!geneve_tlv_opt_obj->obj) {
3164 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create GENEVE TLV option", NULL, 0);
3165 : 0 : mlx5_free(geneve_tlv_opt_obj);
3166 : 0 : return NULL;
3167 : : }
3168 [ # # ]: 0 : geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
3169 : 0 : return geneve_tlv_opt_obj;
3170 : : }
3171 : :
3172 : : /**
3173 : : * Query GENEVE TLV option using DevX API.
3174 : : *
3175 : : * @param[in] ctx
3176 : : * Context used to create GENEVE TLV option object.
3177 : : * @param[in] geneve_tlv_opt_obj
3178 : : * DevX object of the GENEVE TLV option.
3179 : : * @param[out] attr
3180 : : * Pointer to match sample info attributes structure.
3181 : : *
3182 : : * @return
3183 : : * 0 on success, a negative errno otherwise and rte_errno is set.
3184 : : */
3185 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_query_geneve_tlv_option)
3186 : : int
3187 : 0 : mlx5_devx_cmd_query_geneve_tlv_option(void *ctx,
3188 : : struct mlx5_devx_obj *geneve_tlv_opt_obj,
3189 : : struct mlx5_devx_match_sample_info_query_attr *attr)
3190 : : {
3191 : 0 : uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
3192 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_geneve_tlv_option_out)] = {0};
3193 : : void *hdr = MLX5_ADDR_OF(query_geneve_tlv_option_out, in, hdr);
3194 : : void *opt = MLX5_ADDR_OF(query_geneve_tlv_option_out, out,
3195 : : geneve_tlv_opt);
3196 : : int ret;
3197 : :
3198 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
3199 : : MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
3200 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
3201 : : MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT);
3202 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, geneve_tlv_opt_obj->id);
3203 : : /* Call first query to get sample handle. */
3204 : 0 : ret = mlx5_glue->devx_obj_query(geneve_tlv_opt_obj->obj, in, sizeof(in),
3205 : : out, sizeof(out));
3206 [ # # ]: 0 : if (ret) {
3207 : 0 : DRV_LOG(ERR, "Failed to query GENEVE TLV option using DevX.");
3208 : 0 : rte_errno = errno;
3209 : 0 : return -errno;
3210 : : }
3211 : : /* Call second query to get sample information. */
3212 [ # # # # ]: 0 : if (MLX5_GET(geneve_tlv_option, opt, sample_id_valid)) {
3213 [ # # ]: 0 : uint32_t sample_id = MLX5_GET(geneve_tlv_option, opt,
3214 : : geneve_sample_field_id);
3215 : :
3216 : 0 : return mlx5_devx_cmd_match_sample_info_query(ctx, sample_id,
3217 : : attr);
3218 : : }
3219 : 0 : DRV_LOG(DEBUG, "GENEVE TLV option sample isn't valid.");
3220 : 0 : return 0;
3221 : : }
3222 : :
3223 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_wq_query)
3224 : : int
3225 : 0 : mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id)
3226 : : {
3227 : : #ifdef HAVE_IBV_FLOW_DV_SUPPORT
3228 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0};
3229 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0};
3230 : : int rc;
3231 : : void *rq_ctx;
3232 : :
3233 : 0 : MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ);
3234 : 0 : MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num);
3235 : 0 : rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out));
3236 [ # # ]: 0 : if (rc) {
3237 : 0 : rte_errno = errno;
3238 : 0 : DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - "
3239 : : "rc = %d, errno = %d.", rc, errno);
3240 : 0 : return -rc;
3241 : : };
3242 : : rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context);
3243 [ # # ]: 0 : *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id);
3244 : 0 : return 0;
3245 : : #else
3246 : : (void)wq;
3247 : : (void)counter_set_id;
3248 : : return -ENOTSUP;
3249 : : #endif
3250 : : }
3251 : :
3252 : : /*
3253 : : * Allocate queue counters via devx interface.
3254 : : *
3255 : : * @param[in] ctx
3256 : : * Context returned from mlx5 open_device() glue function.
3257 : : * @param[out] syndrome
3258 : : * Get syndrome of devx command response.
3259 : : *
3260 : : * @return
3261 : : * Pointer to counter object on success, a NULL value otherwise and
3262 : : * rte_errno is set.
3263 : : */
3264 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_queue_counter_alloc)
3265 : : struct mlx5_devx_obj *
3266 : 0 : mlx5_devx_cmd_queue_counter_alloc(void *ctx, int *syndrome)
3267 : : {
3268 : : int status;
3269 : 0 : struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0,
3270 : : SOCKET_ID_ANY);
3271 : 0 : uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {0};
3272 : 0 : uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0};
3273 : :
3274 [ # # ]: 0 : if (!dcs) {
3275 : 0 : rte_errno = ENOMEM;
3276 : 0 : return NULL;
3277 : : }
3278 : 0 : MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
3279 : 0 : dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
3280 : : sizeof(out));
3281 [ # # ]: 0 : if (!dcs->obj) {
3282 [ # # # # ]: 0 : DEVX_DRV_LOG(DEBUG, out, "create q counter set", NULL, 0);
3283 [ # # ]: 0 : status = MLX5_GET(alloc_q_counter_out, out, status);
3284 [ # # ]: 0 : if (status && syndrome)
3285 [ # # ]: 0 : *syndrome = MLX5_GET(alloc_q_counter_out, out, syndrome);
3286 : 0 : mlx5_free(dcs);
3287 : 0 : return NULL;
3288 : : }
3289 [ # # ]: 0 : dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id);
3290 : 0 : return dcs;
3291 : : }
3292 : :
3293 : : /**
3294 : : * Query queue counters values.
3295 : : *
3296 : : * @param[in] dcs
3297 : : * devx object of the queue counter set.
3298 : : * @param[in] clear
3299 : : * Whether hardware should clear the counters after the query or not.
3300 : : * @param[out] out_of_buffers
3301 : : * Number of dropped occurred due to lack of WQE for the associated QPs/RQs.
3302 : : *
3303 : : * @return
3304 : : * 0 on success, a negative value otherwise.
3305 : : */
3306 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_queue_counter_query)
3307 : : int
3308 : 0 : mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear,
3309 : : uint32_t *out_of_buffers)
3310 : : {
3311 : 0 : uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0};
3312 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0};
3313 : : int rc;
3314 : :
3315 : 0 : MLX5_SET(query_q_counter_in, in, opcode,
3316 : : MLX5_CMD_OP_QUERY_Q_COUNTER);
3317 : 0 : MLX5_SET(query_q_counter_in, in, op_mod, 0);
3318 : 0 : MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id);
3319 : 0 : MLX5_SET(query_q_counter_in, in, clear, !!clear);
3320 : 0 : rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
3321 : : sizeof(out));
3322 [ # # ]: 0 : if (rc) {
3323 : 0 : DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc);
3324 : 0 : rte_errno = rc;
3325 : 0 : return -rc;
3326 : : }
3327 [ # # ]: 0 : *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer);
3328 : 0 : return 0;
3329 : : }
3330 : :
3331 : : /**
3332 : : * Create general object of type DEK using DevX API.
3333 : : *
3334 : : * @param[in] ctx
3335 : : * Context returned from mlx5 open_device() glue function.
3336 : : * @param [in] attr
3337 : : * Pointer to DEK attributes structure.
3338 : : *
3339 : : * @return
3340 : : * The DevX object created, NULL otherwise and rte_errno is set.
3341 : : */
3342 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_dek_obj)
3343 : : struct mlx5_devx_obj *
3344 : 0 : mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr)
3345 : : {
3346 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0};
3347 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
3348 : : struct mlx5_devx_obj *dek_obj = NULL;
3349 : : void *ptr = NULL, *key_addr = NULL;
3350 : :
3351 : 0 : dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj),
3352 : : 0, SOCKET_ID_ANY);
3353 [ # # ]: 0 : if (dek_obj == NULL) {
3354 : 0 : DRV_LOG(ERR, "Failed to allocate DEK object data");
3355 : 0 : rte_errno = ENOMEM;
3356 : 0 : return NULL;
3357 : : }
3358 : : ptr = MLX5_ADDR_OF(create_dek_in, in, hdr);
3359 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
3360 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
3361 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
3362 : : MLX5_GENERAL_OBJ_TYPE_DEK);
3363 : : ptr = MLX5_ADDR_OF(create_dek_in, in, dek);
3364 [ # # ]: 0 : MLX5_SET(dek, ptr, key_size, attr->key_size);
3365 [ # # ]: 0 : MLX5_SET(dek, ptr, has_keytag, attr->has_keytag);
3366 [ # # ]: 0 : MLX5_SET(dek, ptr, key_purpose, attr->key_purpose);
3367 [ # # ]: 0 : MLX5_SET(dek, ptr, pd, attr->pd);
3368 [ # # ]: 0 : MLX5_SET64(dek, ptr, opaque, attr->opaque);
3369 : : key_addr = MLX5_ADDR_OF(dek, ptr, key);
3370 : 0 : memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE);
3371 : 0 : dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
3372 : : out, sizeof(out));
3373 [ # # ]: 0 : if (dek_obj->obj == NULL) {
3374 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create DEK", NULL, 0);
3375 : 0 : mlx5_free(dek_obj);
3376 : 0 : return NULL;
3377 : : }
3378 [ # # ]: 0 : dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
3379 : 0 : return dek_obj;
3380 : : }
3381 : :
3382 : : /**
3383 : : * Create general object of type IMPORT_KEK using DevX API.
3384 : : *
3385 : : * @param[in] ctx
3386 : : * Context returned from mlx5 open_device() glue function.
3387 : : * @param [in] attr
3388 : : * Pointer to IMPORT_KEK attributes structure.
3389 : : *
3390 : : * @return
3391 : : * The DevX object created, NULL otherwise and rte_errno is set.
3392 : : */
3393 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_import_kek_obj)
3394 : : struct mlx5_devx_obj *
3395 : 0 : mlx5_devx_cmd_create_import_kek_obj(void *ctx,
3396 : : struct mlx5_devx_import_kek_attr *attr)
3397 : : {
3398 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_import_kek_in)] = {0};
3399 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
3400 : : struct mlx5_devx_obj *import_kek_obj = NULL;
3401 : : void *ptr = NULL, *key_addr = NULL;
3402 : :
3403 : 0 : import_kek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*import_kek_obj),
3404 : : 0, SOCKET_ID_ANY);
3405 [ # # ]: 0 : if (import_kek_obj == NULL) {
3406 : 0 : DRV_LOG(ERR, "Failed to allocate IMPORT_KEK object data");
3407 : 0 : rte_errno = ENOMEM;
3408 : 0 : return NULL;
3409 : : }
3410 : : ptr = MLX5_ADDR_OF(create_import_kek_in, in, hdr);
3411 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
3412 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
3413 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
3414 : : MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK);
3415 : : ptr = MLX5_ADDR_OF(create_import_kek_in, in, import_kek);
3416 [ # # ]: 0 : MLX5_SET(import_kek, ptr, key_size, attr->key_size);
3417 : : key_addr = MLX5_ADDR_OF(import_kek, ptr, key);
3418 : 0 : memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE);
3419 : 0 : import_kek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
3420 : : out, sizeof(out));
3421 [ # # ]: 0 : if (import_kek_obj->obj == NULL) {
3422 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create IMPORT_KEK", NULL, 0);
3423 : 0 : mlx5_free(import_kek_obj);
3424 : 0 : return NULL;
3425 : : }
3426 [ # # ]: 0 : import_kek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
3427 : 0 : return import_kek_obj;
3428 : : }
3429 : :
3430 : : /**
3431 : : * Create general object of type CREDENTIAL using DevX API.
3432 : : *
3433 : : * @param[in] ctx
3434 : : * Context returned from mlx5 open_device() glue function.
3435 : : * @param [in] attr
3436 : : * Pointer to CREDENTIAL attributes structure.
3437 : : *
3438 : : * @return
3439 : : * The DevX object created, NULL otherwise and rte_errno is set.
3440 : : */
3441 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_credential_obj)
3442 : : struct mlx5_devx_obj *
3443 : 0 : mlx5_devx_cmd_create_credential_obj(void *ctx,
3444 : : struct mlx5_devx_credential_attr *attr)
3445 : : {
3446 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_credential_in)] = {0};
3447 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
3448 : : struct mlx5_devx_obj *credential_obj = NULL;
3449 : : void *ptr = NULL, *credential_addr = NULL;
3450 : :
3451 : 0 : credential_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*credential_obj),
3452 : : 0, SOCKET_ID_ANY);
3453 [ # # ]: 0 : if (credential_obj == NULL) {
3454 : 0 : DRV_LOG(ERR, "Failed to allocate CREDENTIAL object data");
3455 : 0 : rte_errno = ENOMEM;
3456 : 0 : return NULL;
3457 : : }
3458 : : ptr = MLX5_ADDR_OF(create_credential_in, in, hdr);
3459 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
3460 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
3461 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
3462 : : MLX5_GENERAL_OBJ_TYPE_CREDENTIAL);
3463 : : ptr = MLX5_ADDR_OF(create_credential_in, in, credential);
3464 [ # # ]: 0 : MLX5_SET(credential, ptr, credential_role, attr->credential_role);
3465 : : credential_addr = MLX5_ADDR_OF(credential, ptr, credential);
3466 : 0 : memcpy(credential_addr, (void *)(attr->credential),
3467 : : MLX5_CRYPTO_CREDENTIAL_SIZE);
3468 : 0 : credential_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
3469 : : out, sizeof(out));
3470 [ # # ]: 0 : if (credential_obj->obj == NULL) {
3471 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create CREDENTIAL", NULL, 0);
3472 : 0 : mlx5_free(credential_obj);
3473 : 0 : return NULL;
3474 : : }
3475 [ # # ]: 0 : credential_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
3476 : 0 : return credential_obj;
3477 : : }
3478 : :
3479 : : /**
3480 : : * Create general object of type CRYPTO_LOGIN using DevX API.
3481 : : *
3482 : : * @param[in] ctx
3483 : : * Context returned from mlx5 open_device() glue function.
3484 : : * @param [in] attr
3485 : : * Pointer to CRYPTO_LOGIN attributes structure.
3486 : : *
3487 : : * @return
3488 : : * The DevX object created, NULL otherwise and rte_errno is set.
3489 : : */
3490 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_crypto_login_obj)
3491 : : struct mlx5_devx_obj *
3492 : 0 : mlx5_devx_cmd_create_crypto_login_obj(void *ctx,
3493 : : struct mlx5_devx_crypto_login_attr *attr)
3494 : : {
3495 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_crypto_login_in)] = {0};
3496 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
3497 : : struct mlx5_devx_obj *crypto_login_obj = NULL;
3498 : : void *ptr = NULL, *credential_addr = NULL;
3499 : :
3500 : 0 : crypto_login_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*crypto_login_obj),
3501 : : 0, SOCKET_ID_ANY);
3502 [ # # ]: 0 : if (crypto_login_obj == NULL) {
3503 : 0 : DRV_LOG(ERR, "Failed to allocate CRYPTO_LOGIN object data");
3504 : 0 : rte_errno = ENOMEM;
3505 : 0 : return NULL;
3506 : : }
3507 : : ptr = MLX5_ADDR_OF(create_crypto_login_in, in, hdr);
3508 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
3509 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
3510 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
3511 : : MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN);
3512 : : ptr = MLX5_ADDR_OF(create_crypto_login_in, in, crypto_login);
3513 [ # # ]: 0 : MLX5_SET(crypto_login, ptr, credential_pointer,
3514 : : attr->credential_pointer);
3515 [ # # ]: 0 : MLX5_SET(crypto_login, ptr, session_import_kek_ptr,
3516 : : attr->session_import_kek_ptr);
3517 : : credential_addr = MLX5_ADDR_OF(crypto_login, ptr, credential);
3518 : 0 : memcpy(credential_addr, (void *)(attr->credential),
3519 : : MLX5_CRYPTO_CREDENTIAL_SIZE);
3520 : 0 : crypto_login_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
3521 : : out, sizeof(out));
3522 [ # # ]: 0 : if (crypto_login_obj->obj == NULL) {
3523 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create CRYPTO_LOGIN", NULL, 0);
3524 : 0 : mlx5_free(crypto_login_obj);
3525 : 0 : return NULL;
3526 : : }
3527 [ # # ]: 0 : crypto_login_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
3528 : 0 : return crypto_login_obj;
3529 : : }
3530 : :
3531 : : /**
3532 : : * Query LAG context.
3533 : : *
3534 : : * @param[in] ctx
3535 : : * Pointer to ibv_context, returned from mlx5dv_open_device.
3536 : : * @param[out] lag_ctx
3537 : : * Pointer to struct mlx5_devx_lag_context, to be set by the routine.
3538 : : *
3539 : : * @return
3540 : : * 0 on success, a negative value otherwise.
3541 : : */
3542 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_query_lag)
3543 : : int
3544 : 0 : mlx5_devx_cmd_query_lag(void *ctx,
3545 : : struct mlx5_devx_lag_context *lag_ctx)
3546 : : {
3547 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_lag_in)] = {0};
3548 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_lag_out)] = {0};
3549 : : void *lctx;
3550 : : int rc;
3551 : :
3552 : 0 : MLX5_SET(query_lag_in, in, opcode, MLX5_CMD_OP_QUERY_LAG);
3553 : 0 : rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
3554 [ # # ]: 0 : if (rc)
3555 : 0 : goto error;
3556 : : lctx = MLX5_ADDR_OF(query_lag_out, out, context);
3557 [ # # ]: 0 : lag_ctx->fdb_selection_mode = MLX5_GET(lag_context, lctx,
3558 : : fdb_selection_mode);
3559 [ # # ]: 0 : lag_ctx->port_select_mode = MLX5_GET(lag_context, lctx,
3560 : : port_select_mode);
3561 [ # # ]: 0 : lag_ctx->lag_state = MLX5_GET(lag_context, lctx, lag_state);
3562 [ # # ]: 0 : lag_ctx->tx_remap_affinity_2 = MLX5_GET(lag_context, lctx,
3563 : : tx_remap_affinity_2);
3564 [ # # ]: 0 : lag_ctx->tx_remap_affinity_1 = MLX5_GET(lag_context, lctx,
3565 : : tx_remap_affinity_1);
3566 : 0 : return 0;
3567 : : error:
3568 : 0 : rc = (rc > 0) ? -rc : rc;
3569 : 0 : return rc;
3570 : : }
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