Branch data Line data Source code
1 : : /* SPDX-License-Identifier: BSD-3-Clause
2 : : * Copyright(c) 2021 HiSilicon Limited
3 : : */
4 : :
5 : : #include <string.h>
6 : :
7 : : #include <rte_cycles.h>
8 : : #include <rte_malloc.h>
9 : : #include <rte_test.h>
10 : : #include <rte_dmadev.h>
11 : :
12 : : #include "test.h"
13 : : #include "test_dmadev_api.h"
14 : :
15 : : extern int test_dma_api(uint16_t dev_id);
16 : :
17 : : #define TEST_MEMCPY_SIZE 1024
18 : : #define TEST_WAIT_US_VAL 50000
19 : : #define TEST_SG_MAX 64
20 : :
21 : : static int16_t test_dev_id;
22 : : static int16_t invalid_dev_id;
23 : :
24 : : static char *src;
25 : : static char *dst;
26 : : static char *src_sg[TEST_SG_MAX];
27 : : static char *dst_sg[TEST_SG_MAX];
28 : :
29 : : static int
30 : 0 : testsuite_setup(void)
31 : : {
32 : 0 : invalid_dev_id = -1;
33 : : int i, rc = 0;
34 : :
35 [ # # ]: 0 : for (i = 0; i < TEST_SG_MAX; i++) {
36 : 0 : src_sg[i] = rte_malloc("dmadev_test_src", TEST_MEMCPY_SIZE, 0);
37 [ # # ]: 0 : if (src_sg[i] == NULL) {
38 : : rc = -ENOMEM;
39 : 0 : goto exit;
40 : : }
41 : :
42 : 0 : dst_sg[i] = rte_malloc("dmadev_test_dst", TEST_MEMCPY_SIZE, 0);
43 [ # # ]: 0 : if (dst_sg[i] == NULL) {
44 : 0 : rte_free(src_sg[i]);
45 : 0 : src_sg[i] = NULL;
46 : : rc = -ENOMEM;
47 : 0 : goto exit;
48 : : }
49 : : }
50 : :
51 : 0 : src = src_sg[0];
52 : 0 : dst = dst_sg[0];
53 : :
54 : : /* Set dmadev log level to critical to suppress unnecessary output
55 : : * during API tests.
56 : : */
57 : 0 : rte_log_set_level_pattern("lib.dmadev", RTE_LOG_CRIT);
58 : :
59 : 0 : return rc;
60 : : exit:
61 [ # # ]: 0 : while (--i >= 0) {
62 : 0 : rte_free(src_sg[i]);
63 : 0 : rte_free(dst_sg[i]);
64 : : }
65 : :
66 : : return rc;
67 : : }
68 : :
69 : : static void
70 : 0 : testsuite_teardown(void)
71 : : {
72 : : int i;
73 : :
74 [ # # ]: 0 : for (i = 0; i < TEST_SG_MAX; i++) {
75 : 0 : rte_free(src_sg[i]);
76 : 0 : src_sg[i] = NULL;
77 : 0 : rte_free(dst_sg[i]);
78 : 0 : dst_sg[i] = NULL;
79 : : }
80 : :
81 : 0 : src = NULL;
82 : 0 : dst = NULL;
83 : : /* Ensure the dmadev is stopped. */
84 : 0 : rte_dma_stop(test_dev_id);
85 : 0 : rte_dma_stats_reset(test_dev_id, RTE_DMA_ALL_VCHAN);
86 : :
87 : 0 : rte_log_set_level_pattern("lib.dmadev", RTE_LOG_INFO);
88 : 0 : }
89 : :
90 : : static int
91 : 0 : test_dma_get_dev_id_by_name(void)
92 : : {
93 : 0 : int ret = rte_dma_get_dev_id_by_name("invalid_dmadev_device");
94 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EINVAL, "Expected -EINVAL, %d", ret);
95 : : return TEST_SUCCESS;
96 : : }
97 : :
98 : : static int
99 : 0 : test_dma_is_valid_dev(void)
100 : : {
101 : : int ret;
102 : 0 : ret = rte_dma_is_valid(invalid_dev_id);
103 [ # # ]: 0 : RTE_TEST_ASSERT(ret == false, "Expected false for invalid dev id");
104 : 0 : ret = rte_dma_is_valid(test_dev_id);
105 [ # # ]: 0 : RTE_TEST_ASSERT(ret == true, "Expected true for valid dev id");
106 : : return TEST_SUCCESS;
107 : : }
108 : :
109 : : static int
110 : 0 : test_dma_count(void)
111 : : {
112 : 0 : uint16_t count = rte_dma_count_avail();
113 [ # # ]: 0 : RTE_TEST_ASSERT(count > 0, "Invalid dmadev count %u", count);
114 : : return TEST_SUCCESS;
115 : : }
116 : :
117 : : static int
118 : 0 : test_dma_info_get(void)
119 : : {
120 : 0 : struct rte_dma_info info = { 0 };
121 : : int ret;
122 : :
123 : 0 : ret = rte_dma_info_get(invalid_dev_id, &info);
124 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EINVAL, "Expected -EINVAL, %d", ret);
125 : 0 : ret = rte_dma_info_get(test_dev_id, NULL);
126 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EINVAL, "Expected -EINVAL, %d", ret);
127 : 0 : ret = rte_dma_info_get(test_dev_id, &info);
128 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to obtain device info");
129 : :
130 : : return TEST_SUCCESS;
131 : : }
132 : :
133 : : static int
134 : 0 : check_configure_extra(struct rte_dma_info *info)
135 : : {
136 : 0 : struct rte_dma_conf conf = { 0 };
137 : : int ret;
138 : :
139 : : /* Check undefined flags */
140 [ # # ]: 0 : for (int i = 2; i < 64; i++) {
141 : : memset(&conf, 0, sizeof(conf));
142 : 0 : conf.nb_vchans = info->max_vchans;
143 : 0 : conf.flags = RTE_BIT64(i);
144 : 0 : ret = rte_dma_configure(test_dev_id, &conf);
145 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EINVAL,
146 : : "Expected -EINVAL for undefined flag bit %d, %d", i, ret);
147 : : }
148 : :
149 : : /* Check enable silent mode without support */
150 [ # # ]: 0 : if (!(info->dev_capa & RTE_DMA_CAPA_SILENT)) {
151 : : memset(&conf, 0, sizeof(conf));
152 : 0 : conf.nb_vchans = info->max_vchans;
153 : 0 : conf.flags = RTE_DMA_CFG_FLAG_SILENT;
154 : 0 : ret = rte_dma_configure(test_dev_id, &conf);
155 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EINVAL,
156 : : "Expected -EINVAL for SILENT without capa, %d", ret);
157 : : }
158 : :
159 : : /* Check enable enqueue/dequeue mode without support */
160 [ # # ]: 0 : if (!(info->dev_capa & RTE_DMA_CAPA_OPS_ENQ_DEQ)) {
161 : : memset(&conf, 0, sizeof(conf));
162 : 0 : conf.nb_vchans = info->max_vchans;
163 : 0 : conf.flags = RTE_DMA_CFG_FLAG_ENQ_DEQ;
164 : 0 : ret = rte_dma_configure(test_dev_id, &conf);
165 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EINVAL,
166 : : "Expected -EINVAL for ENQ_DEQ without capa, %d", ret);
167 : : }
168 : :
169 : : /* Check non-zero priority without SP capability */
170 [ # # ]: 0 : if (!(info->dev_capa & RTE_DMA_CAPA_PRI_POLICY_SP)) {
171 : : memset(&conf, 0, sizeof(conf));
172 : 0 : conf.nb_vchans = info->max_vchans;
173 : 0 : conf.priority = 1;
174 : 0 : ret = rte_dma_configure(test_dev_id, &conf);
175 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EINVAL,
176 : : "Expected -EINVAL for non-zero priority without SP, %d", ret);
177 : : }
178 : :
179 : : return 0;
180 : : }
181 : :
182 : : static int
183 : 0 : test_dma_configure(void)
184 : : {
185 : 0 : struct rte_dma_conf conf = { 0 };
186 : 0 : struct rte_dma_info info = { 0 };
187 : : int ret;
188 : :
189 : : /* Check for invalid parameters */
190 : 0 : ret = rte_dma_configure(invalid_dev_id, &conf);
191 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EINVAL, "Expected -EINVAL, %d", ret);
192 : 0 : ret = rte_dma_configure(test_dev_id, NULL);
193 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EINVAL, "Expected -EINVAL, %d", ret);
194 : :
195 : : /* Check for nb_vchans == 0 */
196 : : memset(&conf, 0, sizeof(conf));
197 : 0 : ret = rte_dma_configure(test_dev_id, &conf);
198 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EINVAL, "Expected -EINVAL, %d", ret);
199 : :
200 : : /* Check for conf.nb_vchans > info.max_vchans */
201 : 0 : ret = rte_dma_info_get(test_dev_id, &info);
202 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to obtain device info");
203 : : memset(&conf, 0, sizeof(conf));
204 : 0 : conf.nb_vchans = info.max_vchans + 1;
205 : 0 : ret = rte_dma_configure(test_dev_id, &conf);
206 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EINVAL, "Expected -EINVAL, %d", ret);
207 : :
208 : : /* Check flags, priority extra validations */
209 : 0 : ret = check_configure_extra(&info);
210 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to check configure extra");
211 : :
212 : : /* Configure success */
213 : : memset(&conf, 0, sizeof(conf));
214 : 0 : conf.nb_vchans = info.max_vchans;
215 : 0 : ret = rte_dma_configure(test_dev_id, &conf);
216 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to configure dmadev, %d", ret);
217 : :
218 : : /* Check configure success */
219 : 0 : ret = rte_dma_info_get(test_dev_id, &info);
220 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to obtain device info");
221 [ # # ]: 0 : RTE_TEST_ASSERT_EQUAL(conf.nb_vchans, info.nb_vchans,
222 : : "Configure nb_vchans not match");
223 : :
224 : : return TEST_SUCCESS;
225 : : }
226 : :
227 : : static int
228 : 0 : check_direction(void)
229 : : {
230 : : struct rte_dma_vchan_conf vchan_conf;
231 : : int ret;
232 : :
233 : : /* Check for direction */
234 : : memset(&vchan_conf, 0, sizeof(vchan_conf));
235 : 0 : vchan_conf.direction = RTE_DMA_DIR_DEV_TO_DEV + 1;
236 : 0 : ret = rte_dma_vchan_setup(test_dev_id, 0, &vchan_conf);
237 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EINVAL, "Expected -EINVAL, %d", ret);
238 : 0 : vchan_conf.direction = RTE_DMA_DIR_MEM_TO_MEM - 1;
239 : 0 : ret = rte_dma_vchan_setup(test_dev_id, 0, &vchan_conf);
240 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EINVAL, "Expected -EINVAL, %d", ret);
241 : :
242 : : /* Check for direction and dev_capa combination */
243 : : memset(&vchan_conf, 0, sizeof(vchan_conf));
244 : 0 : vchan_conf.direction = RTE_DMA_DIR_MEM_TO_DEV;
245 : 0 : ret = rte_dma_vchan_setup(test_dev_id, 0, &vchan_conf);
246 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EINVAL, "Expected -EINVAL, %d", ret);
247 : 0 : vchan_conf.direction = RTE_DMA_DIR_DEV_TO_MEM;
248 : 0 : ret = rte_dma_vchan_setup(test_dev_id, 0, &vchan_conf);
249 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EINVAL, "Expected -EINVAL, %d", ret);
250 : 0 : vchan_conf.direction = RTE_DMA_DIR_DEV_TO_DEV;
251 : 0 : ret = rte_dma_vchan_setup(test_dev_id, 0, &vchan_conf);
252 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EINVAL, "Expected -EINVAL, %d", ret);
253 : :
254 : : return 0;
255 : : }
256 : :
257 : : static int
258 : 0 : check_vchan_port(struct rte_dma_info *dev_info)
259 : : {
260 : : struct rte_dma_vchan_conf vchan_conf;
261 : : int ret;
262 : :
263 : : /* Check invalid port_type enum values */
264 : : memset(&vchan_conf, 0, sizeof(vchan_conf));
265 : : vchan_conf.direction = RTE_DMA_DIR_MEM_TO_MEM;
266 : 0 : vchan_conf.nb_desc = dev_info->min_desc;
267 : 0 : vchan_conf.src_port.port_type = RTE_DMA_PORT_PCIE + 1;
268 : 0 : ret = rte_dma_vchan_setup(test_dev_id, 0, &vchan_conf);
269 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EINVAL,
270 : : "Expected -EINVAL for invalid port_type, %d", ret);
271 : :
272 : : /* Check src port type vs direction mismatch */
273 : : memset(&vchan_conf, 0, sizeof(vchan_conf));
274 : : vchan_conf.direction = RTE_DMA_DIR_MEM_TO_MEM;
275 : 0 : vchan_conf.nb_desc = dev_info->min_desc;
276 : 0 : vchan_conf.src_port.port_type = RTE_DMA_PORT_PCIE;
277 : 0 : ret = rte_dma_vchan_setup(test_dev_id, 0, &vchan_conf);
278 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EINVAL, "Expected -EINVAL, %d", ret);
279 : :
280 : : /* Check dst port type vs direction mismatch */
281 : : memset(&vchan_conf, 0, sizeof(vchan_conf));
282 : : vchan_conf.direction = RTE_DMA_DIR_MEM_TO_MEM;
283 : 0 : vchan_conf.nb_desc = dev_info->min_desc;
284 : 0 : vchan_conf.dst_port.port_type = RTE_DMA_PORT_PCIE;
285 : 0 : ret = rte_dma_vchan_setup(test_dev_id, 0, &vchan_conf);
286 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EINVAL, "Expected -EINVAL, %d", ret);
287 : :
288 : : /* Check non-zero reserved fields in src_port */
289 : : memset(&vchan_conf, 0, sizeof(vchan_conf));
290 : : vchan_conf.direction = RTE_DMA_DIR_MEM_TO_MEM;
291 : 0 : vchan_conf.nb_desc = dev_info->min_desc;
292 : 0 : vchan_conf.src_port.reserved[0] = 1;
293 : 0 : ret = rte_dma_vchan_setup(test_dev_id, 0, &vchan_conf);
294 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EINVAL,
295 : : "Expected -EINVAL for non-zero src_port.reserved, %d", ret);
296 : :
297 : : /* Check non-zero reserved fields in dst_port */
298 : : memset(&vchan_conf, 0, sizeof(vchan_conf));
299 : : vchan_conf.direction = RTE_DMA_DIR_MEM_TO_MEM;
300 : 0 : vchan_conf.nb_desc = dev_info->min_desc;
301 : 0 : vchan_conf.dst_port.reserved[0] = 1;
302 : 0 : ret = rte_dma_vchan_setup(test_dev_id, 0, &vchan_conf);
303 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EINVAL,
304 : : "Expected -EINVAL for non-zero dst_port.reserved, %d", ret);
305 : :
306 : : return 0;
307 : : }
308 : :
309 : : static int
310 : 0 : check_vchan_domain(struct rte_dma_info *dev_info)
311 : : {
312 : : struct rte_dma_vchan_conf vchan_conf;
313 : : int ret;
314 : :
315 : : /* Check invalid domain type enum */
316 : : memset(&vchan_conf, 0, sizeof(vchan_conf));
317 : : vchan_conf.direction = RTE_DMA_DIR_MEM_TO_MEM;
318 : 0 : vchan_conf.nb_desc = dev_info->min_desc;
319 : 0 : vchan_conf.domain.type = RTE_DMA_INTER_OS_DOMAIN + 1;
320 : 0 : ret = rte_dma_vchan_setup(test_dev_id, 0, &vchan_conf);
321 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EINVAL,
322 : : "Expected -EINVAL for invalid domain type, %d", ret);
323 : :
324 : : /* Check non-zero domain.reserved */
325 : : memset(&vchan_conf, 0, sizeof(vchan_conf));
326 : : vchan_conf.direction = RTE_DMA_DIR_MEM_TO_MEM;
327 : 0 : vchan_conf.nb_desc = dev_info->min_desc;
328 : 0 : vchan_conf.domain.reserved[0] = 1;
329 : 0 : ret = rte_dma_vchan_setup(test_dev_id, 0, &vchan_conf);
330 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EINVAL,
331 : : "Expected -EINVAL for non-zero domain.reserved, %d", ret);
332 : :
333 : : /* Check inter-domain type without MEM_TO_MEM direction */
334 : : memset(&vchan_conf, 0, sizeof(vchan_conf));
335 : 0 : vchan_conf.direction = RTE_DMA_DIR_MEM_TO_DEV;
336 : 0 : vchan_conf.nb_desc = dev_info->min_desc;
337 : 0 : vchan_conf.domain.type = RTE_DMA_INTER_PROCESS_DOMAIN;
338 : 0 : ret = rte_dma_vchan_setup(test_dev_id, 0, &vchan_conf);
339 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EINVAL,
340 : : "Expected -EINVAL for inter-domain non-MEM_TO_MEM, %d", ret);
341 : :
342 : : /* Check domain INTER_PROCESS without capability */
343 : : memset(&vchan_conf, 0, sizeof(vchan_conf));
344 : : vchan_conf.direction = RTE_DMA_DIR_MEM_TO_MEM;
345 : 0 : vchan_conf.nb_desc = dev_info->min_desc;
346 : 0 : vchan_conf.domain.type = RTE_DMA_INTER_PROCESS_DOMAIN;
347 : 0 : ret = rte_dma_vchan_setup(test_dev_id, 0, &vchan_conf);
348 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EINVAL,
349 : : "Expected -EINVAL for INTER_PROCESS without capa, %d", ret);
350 : :
351 : : /* Check domain INTER_OS without capability */
352 : : memset(&vchan_conf, 0, sizeof(vchan_conf));
353 : : vchan_conf.direction = RTE_DMA_DIR_MEM_TO_MEM;
354 : 0 : vchan_conf.nb_desc = dev_info->min_desc;
355 : 0 : vchan_conf.domain.type = RTE_DMA_INTER_OS_DOMAIN;
356 : 0 : ret = rte_dma_vchan_setup(test_dev_id, 0, &vchan_conf);
357 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EINVAL,
358 : : "Expected -EINVAL for INTER_OS without capa, %d", ret);
359 : :
360 : : return 0;
361 : : }
362 : :
363 : : static int
364 : 0 : check_auto_free_conf(struct rte_dma_info *dev_info)
365 : : {
366 : : struct rte_dma_vchan_conf vchan_conf;
367 : : int ret;
368 : :
369 : : /* Check non-zero reserved fields in auto_free */
370 : : memset(&vchan_conf, 0, sizeof(vchan_conf));
371 : : vchan_conf.direction = RTE_DMA_DIR_MEM_TO_MEM;
372 : 0 : vchan_conf.nb_desc = dev_info->min_desc;
373 : 0 : vchan_conf.auto_free.reserved[0] = 1;
374 : 0 : ret = rte_dma_vchan_setup(test_dev_id, 0, &vchan_conf);
375 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EINVAL,
376 : : "Expected -EINVAL for non-zero auto_free.reserved, %d", ret);
377 : :
378 : : /* Check auto_free.m2d.pool without M2D auto-free capability */
379 : : memset(&vchan_conf, 0, sizeof(vchan_conf));
380 : : vchan_conf.direction = RTE_DMA_DIR_MEM_TO_MEM;
381 : 0 : vchan_conf.nb_desc = dev_info->min_desc;
382 : 0 : vchan_conf.auto_free.m2d.pool = (struct rte_mempool *)(uintptr_t)0x1;
383 : 0 : ret = rte_dma_vchan_setup(test_dev_id, 0, &vchan_conf);
384 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EINVAL,
385 : : "Expected -EINVAL for auto_free without M2D capa, %d", ret);
386 : :
387 : : return 0;
388 : : }
389 : :
390 : : static int
391 : 0 : test_dma_vchan_setup(void)
392 : : {
393 : 0 : struct rte_dma_vchan_conf vchan_conf = { 0 };
394 : 0 : struct rte_dma_conf dev_conf = { 0 };
395 : 0 : struct rte_dma_info dev_info = { 0 };
396 : : int ret;
397 : :
398 : : /* Check for invalid parameters */
399 : 0 : ret = rte_dma_vchan_setup(invalid_dev_id, 0, &vchan_conf);
400 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EINVAL, "Expected -EINVAL, %d", ret);
401 : 0 : ret = rte_dma_vchan_setup(test_dev_id, 0, NULL);
402 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EINVAL, "Expected -EINVAL, %d", ret);
403 : 0 : ret = rte_dma_vchan_setup(test_dev_id, 0, &vchan_conf);
404 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EINVAL, "Expected -EINVAL, %d", ret);
405 : :
406 : : /* Make sure configure success */
407 : 0 : ret = rte_dma_info_get(test_dev_id, &dev_info);
408 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to obtain device info");
409 : 0 : dev_conf.nb_vchans = dev_info.max_vchans;
410 : 0 : ret = rte_dma_configure(test_dev_id, &dev_conf);
411 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to configure dmadev, %d", ret);
412 : :
413 : : /* Check for invalid vchan */
414 : 0 : ret = rte_dma_vchan_setup(test_dev_id, dev_conf.nb_vchans, &vchan_conf);
415 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EINVAL, "Expected -EINVAL, %d", ret);
416 : :
417 : : /* Check for direction */
418 : 0 : ret = check_direction();
419 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to check direction");
420 : :
421 : : /* Check for nb_desc validation */
422 : : memset(&vchan_conf, 0, sizeof(vchan_conf));
423 : : vchan_conf.direction = RTE_DMA_DIR_MEM_TO_MEM;
424 : 0 : vchan_conf.nb_desc = dev_info.min_desc - 1;
425 : 0 : ret = rte_dma_vchan_setup(test_dev_id, 0, &vchan_conf);
426 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EINVAL, "Expected -EINVAL, %d", ret);
427 : 0 : vchan_conf.nb_desc = dev_info.max_desc + 1;
428 : 0 : ret = rte_dma_vchan_setup(test_dev_id, 0, &vchan_conf);
429 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EINVAL, "Expected -EINVAL, %d", ret);
430 : :
431 : : /* Check port type and reserved fields */
432 : 0 : ret = check_vchan_port(&dev_info);
433 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to check vchan port");
434 : :
435 : : /* Check domain param validation */
436 : 0 : ret = check_vchan_domain(&dev_info);
437 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to check vchan domain");
438 : :
439 : : /* Check auto_free config validation */
440 : 0 : ret = check_auto_free_conf(&dev_info);
441 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to check auto_free conf");
442 : :
443 : : /* Check vchan setup success */
444 : : memset(&vchan_conf, 0, sizeof(vchan_conf));
445 : : vchan_conf.direction = RTE_DMA_DIR_MEM_TO_MEM;
446 : 0 : vchan_conf.nb_desc = dev_info.min_desc;
447 : 0 : ret = rte_dma_vchan_setup(test_dev_id, 0, &vchan_conf);
448 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to setup vchan, %d", ret);
449 : :
450 : : return TEST_SUCCESS;
451 : : }
452 : :
453 : : static int
454 : 0 : setup_vchan(int nb_vchans, bool ena_enq_deq)
455 : : {
456 : 0 : struct rte_dma_vchan_conf vchan_conf = { 0 };
457 : 0 : struct rte_dma_info dev_info = { 0 };
458 : 0 : struct rte_dma_conf dev_conf = { 0 };
459 : : int ret;
460 : :
461 : 0 : ret = rte_dma_info_get(test_dev_id, &dev_info);
462 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to obtain device info, %d", ret);
463 : 0 : dev_conf.nb_vchans = nb_vchans;
464 [ # # ]: 0 : dev_conf.flags = ena_enq_deq ? RTE_DMA_CFG_FLAG_ENQ_DEQ : 0;
465 : 0 : ret = rte_dma_configure(test_dev_id, &dev_conf);
466 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to configure, %d", ret);
467 : 0 : vchan_conf.direction = RTE_DMA_DIR_MEM_TO_MEM;
468 : 0 : vchan_conf.nb_desc = dev_info.min_desc;
469 [ # # ]: 0 : for (int i = 0; i < nb_vchans; i++) {
470 : 0 : ret = rte_dma_vchan_setup(test_dev_id, i, &vchan_conf);
471 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to setup vchan %d, %d", i, ret);
472 : : }
473 : :
474 : : return TEST_SUCCESS;
475 : : }
476 : :
477 : : static int
478 : 0 : test_dma_start_stop(void)
479 : : {
480 : 0 : struct rte_dma_vchan_conf vchan_conf = { 0 };
481 : 0 : struct rte_dma_conf dev_conf = { 0 };
482 : : int ret;
483 : :
484 : : /* Check for invalid parameters */
485 : 0 : ret = rte_dma_start(invalid_dev_id);
486 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EINVAL, "Expected -EINVAL, %d", ret);
487 : 0 : ret = rte_dma_stop(invalid_dev_id);
488 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EINVAL, "Expected -EINVAL, %d", ret);
489 : :
490 : : /* Setup one vchan for later test */
491 : 0 : ret = setup_vchan(1, 0);
492 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to setup one vchan, %d", ret);
493 : :
494 : 0 : ret = rte_dma_start(test_dev_id);
495 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to start, %d", ret);
496 : :
497 : : /* Check reconfigure and vchan setup when device started */
498 : 0 : ret = rte_dma_configure(test_dev_id, &dev_conf);
499 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EBUSY, "Failed to configure, %d", ret);
500 : 0 : ret = rte_dma_vchan_setup(test_dev_id, 0, &vchan_conf);
501 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EBUSY, "Failed to setup vchan, %d", ret);
502 : :
503 : 0 : ret = rte_dma_stop(test_dev_id);
504 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to stop, %d", ret);
505 : :
506 : : return TEST_SUCCESS;
507 : : }
508 : :
509 : : static int
510 : 0 : test_dma_reconfigure(void)
511 : : {
512 : : struct rte_dma_conf dev_conf = { 0 };
513 : 0 : struct rte_dma_info dev_info = { 0 };
514 : : uint16_t cfg_vchans;
515 : : int ret;
516 : :
517 : 0 : ret = rte_dma_info_get(test_dev_id, &dev_info);
518 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to obtain device info, %d", ret);
519 : :
520 : : /* At least two vchans required for the test */
521 [ # # ]: 0 : if (dev_info.max_vchans < 2)
522 : : return TEST_SKIPPED;
523 : :
524 : : /* Setup one vchan for later test */
525 : 0 : ret = setup_vchan(1, 0);
526 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to setup one vchan, %d", ret);
527 : :
528 : 0 : ret = rte_dma_start(test_dev_id);
529 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to start, %d", ret);
530 : :
531 : 0 : ret = rte_dma_stop(test_dev_id);
532 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to stop, %d", ret);
533 : :
534 : : /* Check reconfigure and vchan setup after device stopped */
535 : 0 : cfg_vchans = dev_conf.nb_vchans = (dev_info.max_vchans - 1);
536 : :
537 : 0 : ret = setup_vchan(cfg_vchans, 0);
538 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to setup one vchan, %d", ret);
539 : :
540 : 0 : ret = rte_dma_start(test_dev_id);
541 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to start, %d", ret);
542 : :
543 : 0 : ret = rte_dma_info_get(test_dev_id, &dev_info);
544 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to obtain device info, %d", ret);
545 [ # # ]: 0 : RTE_TEST_ASSERT_EQUAL(dev_info.nb_vchans, cfg_vchans, "incorrect reconfiguration");
546 : :
547 : 0 : ret = rte_dma_stop(test_dev_id);
548 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to stop, %d", ret);
549 : :
550 : : return TEST_SUCCESS;
551 : : }
552 : :
553 : : static int
554 : 0 : test_dma_stats(void)
555 : : {
556 : 0 : struct rte_dma_info dev_info = { 0 };
557 : 0 : struct rte_dma_stats stats = { 0 };
558 : : int ret;
559 : :
560 : : /* Check for invalid parameters */
561 : 0 : ret = rte_dma_stats_get(invalid_dev_id, 0, &stats);
562 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EINVAL, "Expected -EINVAL, %d", ret);
563 : 0 : ret = rte_dma_stats_get(invalid_dev_id, 0, NULL);
564 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EINVAL, "Expected -EINVAL, %d", ret);
565 : 0 : ret = rte_dma_stats_reset(invalid_dev_id, 0);
566 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EINVAL, "Expected -EINVAL, %d", ret);
567 : :
568 : : /* Setup one vchan for later test */
569 : 0 : ret = setup_vchan(1, 0);
570 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to setup one vchan, %d", ret);
571 : :
572 : : /* Check for invalid vchan */
573 : 0 : ret = rte_dma_info_get(test_dev_id, &dev_info);
574 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to obtain device info, %d", ret);
575 : 0 : ret = rte_dma_stats_get(test_dev_id, dev_info.max_vchans, &stats);
576 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EINVAL, "Expected -EINVAL, %d", ret);
577 : 0 : ret = rte_dma_stats_reset(test_dev_id, dev_info.max_vchans);
578 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EINVAL, "Expected -EINVAL, %d", ret);
579 : :
580 : : /* Check for valid vchan */
581 : 0 : ret = rte_dma_stats_get(test_dev_id, 0, &stats);
582 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to get stats, %d", ret);
583 : 0 : ret = rte_dma_stats_get(test_dev_id, RTE_DMA_ALL_VCHAN, &stats);
584 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to get all stats, %d", ret);
585 : 0 : ret = rte_dma_stats_reset(test_dev_id, 0);
586 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to reset stats, %d", ret);
587 : 0 : ret = rte_dma_stats_reset(test_dev_id, RTE_DMA_ALL_VCHAN);
588 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to reset all stats, %d", ret);
589 : :
590 : : return TEST_SUCCESS;
591 : : }
592 : :
593 : : static int
594 : 0 : test_dma_dump(void)
595 : : {
596 : : int ret;
597 : :
598 : : /* Check for invalid parameters */
599 : 0 : ret = rte_dma_dump(invalid_dev_id, stderr);
600 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EINVAL, "Excepted -EINVAL, %d", ret);
601 : 0 : ret = rte_dma_dump(test_dev_id, NULL);
602 [ # # ]: 0 : RTE_TEST_ASSERT(ret == -EINVAL, "Excepted -EINVAL, %d", ret);
603 : :
604 : : return TEST_SUCCESS;
605 : : }
606 : :
607 : : static void
608 : 0 : setup_memory(void)
609 : : {
610 : : int i;
611 : :
612 [ # # ]: 0 : for (i = 0; i < TEST_MEMCPY_SIZE; i++)
613 : 0 : src[i] = (char)i;
614 : 0 : memset(dst, 0, TEST_MEMCPY_SIZE);
615 : 0 : }
616 : :
617 : : static int
618 : 0 : verify_memory(void)
619 : : {
620 : : int i;
621 : :
622 [ # # ]: 0 : for (i = 0; i < TEST_MEMCPY_SIZE; i++) {
623 [ # # ]: 0 : if (src[i] == dst[i])
624 : : continue;
625 : 0 : RTE_TEST_ASSERT_EQUAL(src[i], dst[i],
626 : : "Failed to copy memory, %d %d", src[i], dst[i]);
627 : : }
628 : :
629 : : return 0;
630 : : }
631 : :
632 : : static void
633 : 0 : sg_memory_setup(int n)
634 : : {
635 : : int i, j;
636 : :
637 [ # # ]: 0 : for (i = 0; i < n; i++) {
638 [ # # ]: 0 : for (j = 0; j < TEST_MEMCPY_SIZE; j++)
639 : 0 : src_sg[i][j] = (char)j;
640 : :
641 : 0 : memset(dst_sg[i], 0, TEST_MEMCPY_SIZE);
642 : : }
643 : 0 : }
644 : :
645 : : static int
646 : 0 : sg_memory_verify(int n)
647 : : {
648 : : int i, j;
649 : :
650 [ # # ]: 0 : for (i = 0; i < n; i++) {
651 [ # # ]: 0 : for (j = 0; j < TEST_MEMCPY_SIZE; j++) {
652 [ # # ]: 0 : if (src_sg[i][j] == dst_sg[i][j])
653 : : continue;
654 : :
655 : 0 : RTE_TEST_ASSERT_EQUAL(src_sg[i][j], dst_sg[i][j], "Failed to copy memory, %d %d",
656 : : src_sg[i][j], dst_sg[i][j]);
657 : : }
658 : : }
659 : :
660 : : return 0;
661 : : }
662 : :
663 : : static int
664 : 0 : test_dma_completed(void)
665 : : {
666 : 0 : uint16_t last_idx = 1;
667 : 0 : bool has_error = true;
668 : : uint16_t cpl_ret;
669 : : int ret;
670 : :
671 : : /* Setup one vchan for later test */
672 : 0 : ret = setup_vchan(1, 0);
673 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to setup one vchan, %d", ret);
674 : :
675 : 0 : ret = rte_dma_start(test_dev_id);
676 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to start, %d", ret);
677 : :
678 : 0 : setup_memory();
679 : :
680 : : /* Check enqueue without submit */
681 : 0 : ret = rte_dma_copy(test_dev_id, 0,
682 : : rte_malloc_virt2iova(src),
683 : : rte_malloc_virt2iova(dst),
684 : : TEST_MEMCPY_SIZE, 0);
685 [ # # ]: 0 : RTE_TEST_ASSERT_EQUAL(ret, 0, "Failed to enqueue copy, %d", ret);
686 : 0 : rte_delay_us_sleep(TEST_WAIT_US_VAL);
687 : 0 : cpl_ret = rte_dma_completed(test_dev_id, 0, 1, &last_idx, &has_error);
688 [ # # ]: 0 : RTE_TEST_ASSERT_EQUAL(cpl_ret, 0, "Failed to get completed");
689 : :
690 : : /* Check add submit */
691 : 0 : ret = rte_dma_submit(test_dev_id, 0);
692 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to submit, %d", ret);
693 : 0 : rte_delay_us_sleep(TEST_WAIT_US_VAL);
694 : 0 : cpl_ret = rte_dma_completed(test_dev_id, 0, 1, &last_idx, &has_error);
695 [ # # ]: 0 : RTE_TEST_ASSERT_EQUAL(cpl_ret, 1, "Failed to get completed");
696 [ # # ]: 0 : RTE_TEST_ASSERT_EQUAL(last_idx, 0, "Last idx should be zero, %u",
697 : : last_idx);
698 [ # # ]: 0 : RTE_TEST_ASSERT_EQUAL(has_error, false, "Should have no error");
699 : 0 : ret = verify_memory();
700 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to verify memory");
701 : :
702 : 0 : setup_memory();
703 : :
704 : : /* Check for enqueue with submit */
705 : 0 : ret = rte_dma_copy(test_dev_id, 0,
706 : : rte_malloc_virt2iova(src),
707 : : rte_malloc_virt2iova(dst),
708 : : TEST_MEMCPY_SIZE, RTE_DMA_OP_FLAG_SUBMIT);
709 [ # # ]: 0 : RTE_TEST_ASSERT_EQUAL(ret, 1, "Failed to enqueue copy, %d", ret);
710 : 0 : rte_delay_us_sleep(TEST_WAIT_US_VAL);
711 : 0 : cpl_ret = rte_dma_completed(test_dev_id, 0, 1, &last_idx, &has_error);
712 [ # # ]: 0 : RTE_TEST_ASSERT_EQUAL(cpl_ret, 1, "Failed to get completed");
713 [ # # ]: 0 : RTE_TEST_ASSERT_EQUAL(last_idx, 1, "Last idx should be 1, %u",
714 : : last_idx);
715 [ # # ]: 0 : RTE_TEST_ASSERT_EQUAL(has_error, false, "Should have no error");
716 : 0 : ret = verify_memory();
717 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to verify memory");
718 : :
719 : : /* Stop dmadev to make sure dmadev to a known state */
720 : 0 : ret = rte_dma_stop(test_dev_id);
721 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to stop, %d", ret);
722 : :
723 : : return TEST_SUCCESS;
724 : : }
725 : :
726 : : static int
727 : 0 : test_dma_completed_status(void)
728 : : {
729 : 0 : enum rte_dma_status_code status[1] = { 1 };
730 : 0 : uint16_t last_idx = 1;
731 : : uint16_t cpl_ret, i;
732 : : int ret;
733 : :
734 : : /* Setup one vchan for later test */
735 : 0 : ret = setup_vchan(1, 0);
736 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to setup one vchan, %d", ret);
737 : :
738 : 0 : ret = rte_dma_start(test_dev_id);
739 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to start, %d", ret);
740 : :
741 : : /* Check for enqueue with submit */
742 : 0 : ret = rte_dma_copy(test_dev_id, 0,
743 : : rte_malloc_virt2iova(src),
744 : : rte_malloc_virt2iova(dst),
745 : : TEST_MEMCPY_SIZE, RTE_DMA_OP_FLAG_SUBMIT);
746 [ # # ]: 0 : RTE_TEST_ASSERT_EQUAL(ret, 0, "Failed to enqueue copy, %d", ret);
747 : 0 : rte_delay_us_sleep(TEST_WAIT_US_VAL);
748 : 0 : cpl_ret = rte_dma_completed_status(test_dev_id, 0, 1, &last_idx,
749 : : status);
750 [ # # ]: 0 : RTE_TEST_ASSERT_EQUAL(cpl_ret, 1, "Failed to completed status");
751 [ # # ]: 0 : RTE_TEST_ASSERT_EQUAL(last_idx, 0, "Last idx should be zero, %u",
752 : : last_idx);
753 [ # # ]: 0 : for (i = 0; i < RTE_DIM(status); i++)
754 [ # # ]: 0 : RTE_TEST_ASSERT_EQUAL(status[i], 0,
755 : : "Failed to completed status, %d", status[i]);
756 : :
757 : : /* Check do completed status again */
758 : 0 : cpl_ret = rte_dma_completed_status(test_dev_id, 0, 1, &last_idx,
759 : : status);
760 [ # # ]: 0 : RTE_TEST_ASSERT_EQUAL(cpl_ret, 0, "Failed to completed status");
761 : :
762 : : /* Check for enqueue with submit again */
763 : 0 : ret = rte_dma_copy(test_dev_id, 0,
764 : : rte_malloc_virt2iova(src),
765 : : rte_malloc_virt2iova(dst),
766 : : TEST_MEMCPY_SIZE, RTE_DMA_OP_FLAG_SUBMIT);
767 [ # # ]: 0 : RTE_TEST_ASSERT_EQUAL(ret, 1, "Failed to enqueue copy, %d", ret);
768 : 0 : rte_delay_us_sleep(TEST_WAIT_US_VAL);
769 : 0 : cpl_ret = rte_dma_completed_status(test_dev_id, 0, 1, &last_idx,
770 : : status);
771 [ # # ]: 0 : RTE_TEST_ASSERT_EQUAL(cpl_ret, 1, "Failed to completed status");
772 [ # # ]: 0 : RTE_TEST_ASSERT_EQUAL(last_idx, 1, "Last idx should be 1, %u",
773 : : last_idx);
774 [ # # ]: 0 : for (i = 0; i < RTE_DIM(status); i++)
775 [ # # ]: 0 : RTE_TEST_ASSERT_EQUAL(status[i], 0,
776 : : "Failed to completed status, %d", status[i]);
777 : :
778 : : /* Stop dmadev to make sure dmadev to a known state */
779 : 0 : ret = rte_dma_stop(test_dev_id);
780 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to stop, %d", ret);
781 : :
782 : : return TEST_SUCCESS;
783 : : }
784 : :
785 : : static int
786 : 0 : test_dma_sg(void)
787 : : {
788 : : struct rte_dma_sge src_sge[TEST_SG_MAX], dst_sge[TEST_SG_MAX];
789 : 0 : struct rte_dma_info dev_info = { 0 };
790 : 0 : uint16_t last_idx = -1;
791 : 0 : bool has_error = true;
792 : : int n_sge, i, ret;
793 : : uint16_t cpl_ret;
794 : :
795 : 0 : ret = rte_dma_info_get(test_dev_id, &dev_info);
796 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to obtain device info, %d", ret);
797 : :
798 [ # # ]: 0 : if ((dev_info.dev_capa & RTE_DMA_CAPA_OPS_COPY_SG) == 0)
799 : : return TEST_SKIPPED;
800 : :
801 : 0 : n_sge = RTE_MIN(dev_info.max_sges, TEST_SG_MAX);
802 : :
803 : 0 : ret = setup_vchan(1, 0);
804 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to setup one vchan, %d", ret);
805 : :
806 : 0 : ret = rte_dma_start(test_dev_id);
807 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to start, %d", ret);
808 : :
809 [ # # ]: 0 : for (i = 0; i < n_sge; i++) {
810 : 0 : src_sge[i].addr = rte_malloc_virt2iova(src_sg[i]);
811 : 0 : src_sge[i].length = TEST_MEMCPY_SIZE;
812 : 0 : dst_sge[i].addr = rte_malloc_virt2iova(dst_sg[i]);
813 : 0 : dst_sge[i].length = TEST_MEMCPY_SIZE;
814 : : }
815 : :
816 : 0 : sg_memory_setup(n_sge);
817 : :
818 : : /* Check enqueue without submit */
819 : 0 : ret = rte_dma_copy_sg(test_dev_id, 0, src_sge, dst_sge, n_sge, n_sge, 0);
820 [ # # ]: 0 : RTE_TEST_ASSERT_EQUAL(ret, 0, "Failed to enqueue copy, %d", ret);
821 : :
822 : 0 : rte_delay_us_sleep(TEST_WAIT_US_VAL);
823 : :
824 : 0 : cpl_ret = rte_dma_completed(test_dev_id, 0, 1, &last_idx, &has_error);
825 [ # # ]: 0 : RTE_TEST_ASSERT_EQUAL(cpl_ret, 0, "Failed to get completed");
826 : :
827 : : /* Check DMA submit */
828 : 0 : ret = rte_dma_submit(test_dev_id, 0);
829 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to submit, %d", ret);
830 : :
831 : 0 : rte_delay_us_sleep(TEST_WAIT_US_VAL);
832 : :
833 : 0 : cpl_ret = rte_dma_completed(test_dev_id, 0, 1, &last_idx, &has_error);
834 [ # # ]: 0 : RTE_TEST_ASSERT_EQUAL(cpl_ret, 1, "Failed to get completed");
835 [ # # ]: 0 : RTE_TEST_ASSERT_EQUAL(last_idx, 0, "Last idx should be zero, %u", last_idx);
836 [ # # ]: 0 : RTE_TEST_ASSERT_EQUAL(has_error, false, "Should have no error");
837 : :
838 : 0 : ret = sg_memory_verify(n_sge);
839 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to verify memory");
840 : :
841 : 0 : sg_memory_setup(n_sge);
842 : :
843 : : /* Check for enqueue with submit */
844 : 0 : ret = rte_dma_copy_sg(test_dev_id, 0, src_sge, dst_sge, n_sge, n_sge,
845 : : RTE_DMA_OP_FLAG_SUBMIT);
846 [ # # ]: 0 : RTE_TEST_ASSERT_EQUAL(ret, 1, "Failed to enqueue copy, %d", ret);
847 : :
848 : 0 : rte_delay_us_sleep(TEST_WAIT_US_VAL);
849 : :
850 : 0 : cpl_ret = rte_dma_completed(test_dev_id, 0, 1, &last_idx, &has_error);
851 [ # # ]: 0 : RTE_TEST_ASSERT_EQUAL(cpl_ret, 1, "Failed to get completed");
852 [ # # ]: 0 : RTE_TEST_ASSERT_EQUAL(last_idx, 1, "Last idx should be 1, %u", last_idx);
853 [ # # ]: 0 : RTE_TEST_ASSERT_EQUAL(has_error, false, "Should have no error");
854 : :
855 : 0 : ret = sg_memory_verify(n_sge);
856 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to verify memory");
857 : :
858 : : /* Stop dmadev to make sure dmadev to a known state */
859 : 0 : ret = rte_dma_stop(test_dev_id);
860 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to stop, %d", ret);
861 : :
862 : : return TEST_SUCCESS;
863 : : }
864 : :
865 : : static int
866 : 0 : test_dma_ops_enq_deq(void)
867 : : {
868 : 0 : struct rte_dma_info dev_info = {0};
869 : : struct rte_dma_op *ops;
870 : : int n_sge, i, ret;
871 : :
872 : 0 : ret = rte_dma_info_get(test_dev_id, &dev_info);
873 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to obtain device info, %d", ret);
874 [ # # ]: 0 : if ((dev_info.dev_capa & RTE_DMA_CAPA_OPS_ENQ_DEQ) == 0)
875 : : return TEST_SKIPPED;
876 : :
877 : 0 : n_sge = RTE_MIN(dev_info.max_sges, TEST_SG_MAX);
878 : :
879 : 0 : ret = setup_vchan(1, 1);
880 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to setup one vchan, %d", ret);
881 : :
882 : 0 : ret = rte_dma_start(test_dev_id);
883 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to start, %d", ret);
884 : :
885 : 0 : ops = rte_zmalloc(
886 : 0 : "ops", sizeof(struct rte_dma_op) + ((2 * n_sge) * sizeof(struct rte_dma_sge)), 0);
887 : :
888 [ # # ]: 0 : for (i = 0; i < n_sge; i++) {
889 : 0 : ops->src_dst_seg[i].addr = rte_malloc_virt2iova(src_sg[i]);
890 : 0 : ops->src_dst_seg[i].length = TEST_MEMCPY_SIZE;
891 : 0 : ops->src_dst_seg[n_sge + i].addr = rte_malloc_virt2iova(dst_sg[i]);
892 : 0 : ops->src_dst_seg[n_sge + i].length = TEST_MEMCPY_SIZE;
893 : : }
894 : :
895 : 0 : ops->nb_src = n_sge;
896 : 0 : ops->nb_dst = n_sge;
897 : 0 : sg_memory_setup(n_sge);
898 : :
899 : : /* Enqueue operations */
900 : 0 : ret = rte_dma_enqueue_ops(test_dev_id, 0, &ops, 1);
901 [ # # ]: 0 : RTE_TEST_ASSERT(ret == 1, "Failed to enqueue DMA operations, %d", ret);
902 : :
903 : 0 : rte_delay_us_sleep(TEST_WAIT_US_VAL);
904 : :
905 : 0 : ops = NULL;
906 : : /* Dequeue operations */
907 : 0 : ret = rte_dma_dequeue_ops(test_dev_id, 0, &ops, 1);
908 [ # # ]: 0 : RTE_TEST_ASSERT(ret == 1, "Failed to dequeue DMA operations, %d", ret);
909 [ # # ]: 0 : RTE_TEST_ASSERT(ops != NULL, "Failed to dequeue DMA operations %p", ops);
910 : : /* Free allocated memory for ops */
911 : 0 : rte_free(ops);
912 : :
913 : 0 : ret = sg_memory_verify(n_sge);
914 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to verify memory");
915 : :
916 : : /* Stop dmadev to make sure dmadev to a known state */
917 : 0 : ret = rte_dma_stop(test_dev_id);
918 [ # # ]: 0 : RTE_TEST_ASSERT_SUCCESS(ret, "Failed to stop, %d", ret);
919 : :
920 : : return TEST_SUCCESS;
921 : : }
922 : :
923 : : static struct unit_test_suite dma_api_testsuite = {
924 : : .suite_name = "DMA API Test Suite",
925 : : .setup = testsuite_setup,
926 : : .teardown = testsuite_teardown,
927 : : .unit_test_cases = {
928 : : TEST_CASE(test_dma_get_dev_id_by_name),
929 : : TEST_CASE(test_dma_is_valid_dev),
930 : : TEST_CASE(test_dma_count),
931 : : TEST_CASE(test_dma_info_get),
932 : : TEST_CASE(test_dma_configure),
933 : : TEST_CASE(test_dma_vchan_setup),
934 : : TEST_CASE(test_dma_start_stop),
935 : : TEST_CASE(test_dma_reconfigure),
936 : : TEST_CASE(test_dma_stats),
937 : : TEST_CASE(test_dma_dump),
938 : : TEST_CASE(test_dma_completed),
939 : : TEST_CASE(test_dma_completed_status),
940 : : TEST_CASE(test_dma_sg),
941 : : TEST_CASE(test_dma_ops_enq_deq),
942 : : TEST_CASES_END()
943 : : }
944 : : };
945 : :
946 : : int
947 : 0 : test_dma_api(uint16_t dev_id)
948 : : {
949 : : struct rte_dma_info dev_info;
950 : :
951 [ # # ]: 0 : if (rte_dma_info_get(dev_id, &dev_info) < 0)
952 : : return TEST_SKIPPED;
953 : :
954 : 0 : printf("\n### Test dmadev infrastructure using %u [%s]\n", dev_id, dev_info.dev_name);
955 : 0 : test_dev_id = dev_id;
956 : 0 : return unit_test_suite_runner(&dma_api_testsuite);
957 : : };
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