Branch data Line data Source code
1 : : /* SPDX-License-Identifier: BSD-3-Clause
2 : : * Copyright (c) 2022 NVIDIA Corporation & Affiliates
3 : : */
4 : :
5 : : #include <eal_export.h>
6 : : #include <rte_flow.h>
7 : : #include <rte_flow_driver.h>
8 : : #include <rte_stdatomic.h>
9 : :
10 : : #include <mlx5_malloc.h>
11 : :
12 : : #include "mlx5.h"
13 : : #include "mlx5_common.h"
14 : : #include "mlx5_defs.h"
15 : : #include "mlx5_flow.h"
16 : : #include "mlx5_flow_os.h"
17 : : #include "mlx5_rx.h"
18 : :
19 : : #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
20 : : #include "mlx5_hws_cnt.h"
21 : :
22 : : /** Fast path async flow API functions. */
23 : : static struct rte_flow_fp_ops mlx5_flow_hw_fp_ops;
24 : :
25 : : /*
26 : : * The default ipool threshold value indicates which per_core_cache
27 : : * value to set.
28 : : */
29 : : #define MLX5_HW_IPOOL_SIZE_THRESHOLD (1 << 19)
30 : : /* The default min local cache size. */
31 : : #define MLX5_HW_IPOOL_CACHE_MIN (1 << 9)
32 : :
33 : : /* Default push burst threshold. */
34 : : #define BURST_THR 32u
35 : :
36 : : /* Default queue to flush the flows. */
37 : : #define MLX5_DEFAULT_FLUSH_QUEUE 0
38 : :
39 : : /* Maximum number of rules in control flow tables. */
40 : : #define MLX5_HW_CTRL_FLOW_NB_RULES (4096)
41 : :
42 : : /* Lowest flow group usable by an application if group translation is done. */
43 : : #define MLX5_HW_LOWEST_USABLE_GROUP (1)
44 : :
45 : : /* Maximum group index usable by user applications for transfer flows. */
46 : : #define MLX5_HW_MAX_TRANSFER_GROUP (UINT32_MAX - 1)
47 : :
48 : : /* Maximum group index usable by user applications for egress flows. */
49 : : #define MLX5_HW_MAX_EGRESS_GROUP (UINT32_MAX - 1)
50 : :
51 : : /* Lowest priority for HW root table. */
52 : : #define MLX5_HW_LOWEST_PRIO_ROOT 15
53 : :
54 : : /* Lowest priority for HW non-root table. */
55 : : #define MLX5_HW_LOWEST_PRIO_NON_ROOT (UINT32_MAX)
56 : :
57 : : /* Priorities for Rx control flow rules. */
58 : : #define MLX5_HW_CTRL_RX_PRIO_L2 (MLX5_HW_LOWEST_PRIO_ROOT)
59 : : #define MLX5_HW_CTRL_RX_PRIO_L3 (MLX5_HW_LOWEST_PRIO_ROOT - 1)
60 : : #define MLX5_HW_CTRL_RX_PRIO_L4 (MLX5_HW_LOWEST_PRIO_ROOT - 2)
61 : :
62 : : #define MLX5_HW_VLAN_PUSH_TYPE_IDX 0
63 : : #define MLX5_HW_VLAN_PUSH_VID_IDX 1
64 : : #define MLX5_HW_VLAN_PUSH_PCP_IDX 2
65 : :
66 : : struct mlx5_indlst_legacy {
67 : : struct mlx5_indirect_list indirect;
68 : : struct rte_flow_action_handle *handle;
69 : : enum rte_flow_action_type legacy_type;
70 : : };
71 : :
72 : : #define MLX5_CONST_ENCAP_ITEM(encap_type, ptr) \
73 : : (((const struct encap_type *)(ptr))->definition)
74 : :
75 : : /**
76 : : * Returns the size of a struct with a following layout:
77 : : *
78 : : * @code{.c}
79 : : * struct rte_flow_hw {
80 : : * // rte_flow_hw fields
81 : : * uint8_t rule[mlx5dr_rule_get_handle_size()];
82 : : * };
83 : : * @endcode
84 : : *
85 : : * Such struct is used as a basic container for HW Steering flow rule.
86 : : */
87 : : static size_t
88 : : mlx5_flow_hw_entry_size(void)
89 : : {
90 : 0 : return sizeof(struct rte_flow_hw) + mlx5dr_rule_get_handle_size();
91 : : }
92 : :
93 : : /**
94 : : * Returns the size of "auxed" rte_flow_hw structure which is assumed to be laid out as follows:
95 : : *
96 : : * @code{.c}
97 : : * struct {
98 : : * struct rte_flow_hw {
99 : : * // rte_flow_hw fields
100 : : * uint8_t rule[mlx5dr_rule_get_handle_size()];
101 : : * } flow;
102 : : * struct rte_flow_hw_aux aux;
103 : : * };
104 : : * @endcode
105 : : *
106 : : * Such struct is used whenever rte_flow_hw_aux cannot be allocated separately from the rte_flow_hw
107 : : * e.g., when table is resizable.
108 : : */
109 : : static size_t
110 : : mlx5_flow_hw_auxed_entry_size(void)
111 : : {
112 : 0 : size_t rule_size = mlx5dr_rule_get_handle_size();
113 : :
114 : 0 : return sizeof(struct rte_flow_hw) + rule_size + sizeof(struct rte_flow_hw_aux);
115 : : }
116 : :
117 : : /**
118 : : * Returns a valid pointer to rte_flow_hw_aux associated with given rte_flow_hw
119 : : * depending on template table configuration.
120 : : */
121 : : static __rte_always_inline struct rte_flow_hw_aux *
122 : : mlx5_flow_hw_aux(uint16_t port_id, struct rte_flow_hw *flow)
123 : : {
124 : 0 : struct rte_flow_template_table *table = flow->table;
125 : :
126 : 0 : if (!flow->nt_rule) {
127 [ # # # # : 0 : if (rte_flow_template_table_resizable(port_id, &table->cfg.attr)) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # #
# ]
128 : 0 : size_t offset = sizeof(struct rte_flow_hw) + mlx5dr_rule_get_handle_size();
129 : :
130 : 0 : return RTE_PTR_ADD(flow, offset);
131 : : } else {
132 : 0 : return &table->flow_aux[flow->idx - 1];
133 : : }
134 : : } else {
135 : 0 : return flow->nt2hws->flow_aux;
136 : : }
137 : : }
138 : :
139 : : static __rte_always_inline void
140 : : mlx5_flow_hw_aux_set_age_idx(struct rte_flow_hw *flow,
141 : : struct rte_flow_hw_aux *aux,
142 : : uint32_t age_idx)
143 : : {
144 : : /*
145 : : * Only when creating a flow rule, the type will be set explicitly.
146 : : * Or else, it should be none in the rule update case.
147 : : */
148 [ # # # # : 0 : if (unlikely(flow->operation_type == MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE))
# # # # #
# # # # #
# # # # #
# ]
149 : 0 : aux->upd.age_idx = age_idx;
150 : : else
151 : 0 : aux->orig.age_idx = age_idx;
152 : : }
153 : :
154 : : static __rte_always_inline uint32_t
155 : : mlx5_flow_hw_aux_get_age_idx(struct rte_flow_hw *flow, struct rte_flow_hw_aux *aux)
156 : : {
157 [ # # # # : 0 : if (unlikely(flow->operation_type == MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE))
# # # # #
# # # ]
158 : 0 : return aux->upd.age_idx;
159 : : else
160 : 0 : return aux->orig.age_idx;
161 : : }
162 : :
163 : : static __rte_always_inline void
164 : : mlx5_flow_hw_aux_set_mtr_id(struct rte_flow_hw *flow,
165 : : struct rte_flow_hw_aux *aux,
166 : : uint32_t mtr_id)
167 : : {
168 [ # # # # : 0 : if (unlikely(flow->operation_type == MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE))
# # # # #
# ]
169 : 0 : aux->upd.mtr_id = mtr_id;
170 : : else
171 : 0 : aux->orig.mtr_id = mtr_id;
172 : : }
173 : :
174 : : static __rte_always_inline uint32_t
175 : : mlx5_flow_hw_aux_get_mtr_id(struct rte_flow_hw *flow, struct rte_flow_hw_aux *aux)
176 : : {
177 [ # # ]: 0 : if (unlikely(flow->operation_type == MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE))
178 : 0 : return aux->upd.mtr_id;
179 : : else
180 : 0 : return aux->orig.mtr_id;
181 : : }
182 : :
183 : : static __rte_always_inline struct mlx5_hw_q_job *
184 : : flow_hw_action_job_init(struct mlx5_priv *priv, uint32_t queue,
185 : : const struct rte_flow_action_handle *handle,
186 : : void *user_data, void *query_data,
187 : : enum mlx5_hw_job_type type,
188 : : enum mlx5_hw_indirect_type indirect_type,
189 : : struct rte_flow_error *error);
190 : : static void
191 : : flow_hw_age_count_release(struct mlx5_priv *priv, uint32_t queue, struct rte_flow_hw *flow,
192 : : struct rte_flow_error *error);
193 : :
194 : : static int
195 : : mlx5_tbl_multi_pattern_process(struct rte_eth_dev *dev,
196 : : struct rte_flow_template_table *tbl,
197 : : struct mlx5_multi_pattern_segment *segment,
198 : : uint32_t bulk_size,
199 : : struct rte_flow_error *error);
200 : : static void
201 : : mlx5_destroy_multi_pattern_segment(struct mlx5_multi_pattern_segment *segment);
202 : :
203 : : static __rte_always_inline enum mlx5_indirect_list_type
204 : : flow_hw_inlist_type_get(const struct rte_flow_action *actions);
205 : :
206 : : static int
207 : : flow_hw_allocate_actions(struct rte_eth_dev *dev,
208 : : uint64_t action_flags,
209 : : struct rte_flow_error *error);
210 : :
211 : : static int
212 : : flow_hw_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
213 : : const struct rte_flow_item items[],
214 : : const struct rte_flow_action actions[],
215 : : bool external __rte_unused, int hairpin __rte_unused,
216 : : struct rte_flow_error *error);
217 : :
218 : : bool
219 : 0 : mlx5_hw_ctx_validate(const struct rte_eth_dev *dev, struct rte_flow_error *error)
220 : : {
221 : 0 : const struct mlx5_priv *priv = dev->data->dev_private;
222 : :
223 [ # # ]: 0 : if (!priv->dr_ctx) {
224 : 0 : rte_flow_error_set(error, EINVAL,
225 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
226 : : "non-template flow engine was not configured");
227 : 0 : return false;
228 : : }
229 : : return true;
230 : : }
231 : :
232 : : static int
233 : : flow_hw_allocate_actions(struct rte_eth_dev *dev,
234 : : uint64_t action_flags,
235 : : struct rte_flow_error *error);
236 : :
237 : : static __rte_always_inline int
238 : : mlx5_multi_pattern_reformat_to_index(enum mlx5dr_action_type type)
239 : : {
240 : : switch (type) {
241 : : case MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2:
242 : : return 0;
243 : : case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2:
244 : : return 1;
245 : : case MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2:
246 : : return 2;
247 : : case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3:
248 : : return 3;
249 : : default:
250 : : break;
251 : : }
252 : : return -1;
253 : : }
254 : :
255 : : /* Include only supported reformat actions for BWC non template API. */
256 : : static __rte_always_inline int
257 : : mlx5_bwc_multi_pattern_reformat_to_index(enum mlx5dr_action_type type)
258 : : {
259 : 0 : switch (type) {
260 : : case MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2:
261 : : case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2:
262 : : case MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2:
263 : : case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3:
264 : : return mlx5_multi_pattern_reformat_to_index(type);
265 : : default:
266 : : break;
267 : : }
268 : : return -1;
269 : : }
270 : :
271 : : static __rte_always_inline enum mlx5dr_action_type
272 : : mlx5_multi_pattern_reformat_index_to_type(uint32_t ix)
273 : : {
274 : : switch (ix) {
275 : : case 0:
276 : : return MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2;
277 : : case 1:
278 : : return MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;
279 : : case 2:
280 : : return MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2;
281 : : case 3:
282 : : return MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3;
283 : : default:
284 : : break;
285 : : }
286 : : return MLX5DR_ACTION_TYP_MAX;
287 : : }
288 : :
289 : : static inline enum mlx5dr_table_type
290 : : get_mlx5dr_fdb_table_type(const struct rte_flow_attr *attr,
291 : : uint32_t specialize, bool fdb_unified_en)
292 : : {
293 [ # # # # ]: 0 : if (fdb_unified_en && !!attr->group) {
294 [ # # ]: 0 : if ((specialize & (RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_WIRE_ORIG |
295 : : RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_VPORT_ORIG)) == 0)
296 : : return MLX5DR_TABLE_TYPE_FDB_UNIFIED;
297 : : MLX5_ASSERT((specialize & (RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_WIRE_ORIG |
298 : : RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_VPORT_ORIG)) !=
299 : : (RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_WIRE_ORIG |
300 : : RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_VPORT_ORIG));
301 [ # # ]: 0 : if (specialize & RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_WIRE_ORIG)
302 : : return MLX5DR_TABLE_TYPE_FDB_RX;
303 [ # # ]: 0 : if (specialize & RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_VPORT_ORIG)
304 : 0 : return MLX5DR_TABLE_TYPE_FDB_TX;
305 : : }
306 : :
307 : : return MLX5DR_TABLE_TYPE_FDB;
308 : : }
309 : :
310 : : static inline enum mlx5dr_table_type
311 : 0 : get_mlx5dr_table_type(const struct rte_flow_attr *attr, uint32_t specialize,
312 : : bool fdb_unified_en)
313 : : {
314 : : enum mlx5dr_table_type type;
315 : :
316 [ # # ]: 0 : if (attr->transfer)
317 : : type = get_mlx5dr_fdb_table_type(attr, specialize, fdb_unified_en);
318 [ # # ]: 0 : else if (attr->egress)
319 : : type = MLX5DR_TABLE_TYPE_NIC_TX;
320 : : else
321 : : type = MLX5DR_TABLE_TYPE_NIC_RX;
322 : 0 : return type;
323 : : }
324 : :
325 : : /** Human-readable name for mlx5dr_table_type (for error messages). */
326 : : static inline const char *
327 : : mlx5dr_table_type_name(enum mlx5dr_table_type type)
328 : : {
329 [ # # # # : 0 : switch (type) {
# # # # #
# # # #
# ]
330 : : case MLX5DR_TABLE_TYPE_NIC_RX: return "NIC_RX";
331 : 0 : case MLX5DR_TABLE_TYPE_NIC_TX: return "NIC_TX";
332 : 0 : case MLX5DR_TABLE_TYPE_FDB: return "FDB";
333 : 0 : case MLX5DR_TABLE_TYPE_FDB_RX: return "FDB_RX(wire_orig)";
334 : 0 : case MLX5DR_TABLE_TYPE_FDB_TX: return "FDB_TX(vf_orig)";
335 : 0 : case MLX5DR_TABLE_TYPE_FDB_UNIFIED: return "FDB_UNIFIED";
336 : 0 : default: return "unknown";
337 : : }
338 : : }
339 : :
340 : : /* Non template default queue size used for inner ctrl queue. */
341 : : #define MLX5_NT_DEFAULT_QUEUE_SIZE 32
342 : :
343 : : static int flow_hw_flush_all_ctrl_flows(struct rte_eth_dev *dev);
344 : : static int flow_hw_translate_group(struct rte_eth_dev *dev,
345 : : const struct mlx5_flow_template_table_cfg *cfg,
346 : : uint32_t group,
347 : : uint32_t *table_group,
348 : : struct rte_flow_error *error);
349 : : static __rte_always_inline int
350 : : flow_hw_set_vlan_vid_construct(struct rte_eth_dev *dev,
351 : : struct mlx5_modification_cmd *mhdr_cmd,
352 : : struct mlx5_action_construct_data *act_data,
353 : : const struct mlx5_hw_actions *hw_acts,
354 : : const struct rte_flow_action *action);
355 : : static void
356 : : flow_hw_construct_quota(struct mlx5_priv *priv,
357 : : struct mlx5dr_rule_action *rule_act, uint32_t qid);
358 : :
359 : : static int
360 : : mlx5_flow_ct_init(struct rte_eth_dev *dev,
361 : : uint32_t nb_conn_tracks,
362 : : uint16_t nb_queue);
363 : :
364 : : static __rte_always_inline uint32_t flow_hw_tx_tag_regc_mask(struct rte_eth_dev *dev);
365 : : static __rte_always_inline uint32_t flow_hw_tx_tag_regc_value(struct rte_eth_dev *dev);
366 : :
367 : : static int
368 : : mlx5_hw_validate_action_rss(struct rte_eth_dev *dev,
369 : : const struct rte_flow_action *template_action,
370 : : const struct rte_flow_action *template_mask,
371 : : const struct rte_flow_actions_template_attr *template_attr,
372 : : uint64_t action_flags,
373 : : bool is_indirect,
374 : : struct rte_flow_error *error);
375 : :
376 : : static int
377 : : mlx5_hw_validate_action_conntrack(struct rte_eth_dev *dev,
378 : : const struct rte_flow_action *template_action,
379 : : const struct rte_flow_action *template_mask,
380 : : const struct rte_flow_actions_template_attr *template_attr,
381 : : uint64_t action_flags,
382 : : struct rte_flow_error *error);
383 : :
384 : : static int flow_hw_async_create_validate(struct rte_eth_dev *dev,
385 : : const uint32_t queue,
386 : : const struct rte_flow_template_table *table,
387 : : enum rte_flow_table_insertion_type insertion_type,
388 : : const uint32_t rule_index,
389 : : const struct rte_flow_item items[],
390 : : const uint8_t pattern_template_index,
391 : : const struct rte_flow_action actions[],
392 : : const uint8_t action_template_index,
393 : : struct rte_flow_error *error);
394 : : static int flow_hw_async_update_validate(struct rte_eth_dev *dev,
395 : : const uint32_t queue,
396 : : const struct rte_flow_hw *flow,
397 : : const struct rte_flow_action actions[],
398 : : const uint8_t action_template_index,
399 : : struct rte_flow_error *error);
400 : : static int flow_hw_async_destroy_validate(struct rte_eth_dev *dev,
401 : : const uint32_t queue,
402 : : const struct rte_flow_hw *flow,
403 : : struct rte_flow_error *error);
404 : : static bool flow_hw_should_create_nat64_actions(struct mlx5_priv *priv);
405 : :
406 : : const struct mlx5_flow_driver_ops mlx5_flow_hw_drv_ops;
407 : :
408 : : /* DR action flags with different table. */
409 : : static uint32_t mlx5_hw_act_flag[MLX5_HW_ACTION_FLAG_MAX]
410 : : [MLX5DR_TABLE_TYPE_MAX] = {
411 : : {
412 : : MLX5DR_ACTION_FLAG_ROOT_RX,
413 : : MLX5DR_ACTION_FLAG_ROOT_TX,
414 : : MLX5DR_ACTION_FLAG_ROOT_FDB,
415 : : MLX5DR_ACTION_FLAG_ROOT_FDB,
416 : : MLX5DR_ACTION_FLAG_ROOT_FDB,
417 : : MLX5DR_ACTION_FLAG_ROOT_FDB,
418 : : },
419 : : {
420 : : MLX5DR_ACTION_FLAG_HWS_RX,
421 : : MLX5DR_ACTION_FLAG_HWS_TX,
422 : : MLX5DR_ACTION_FLAG_HWS_FDB,
423 : : MLX5DR_ACTION_FLAG_HWS_FDB_RX,
424 : : MLX5DR_ACTION_FLAG_HWS_FDB_TX,
425 : : MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED,
426 : : },
427 : : };
428 : :
429 : : /**
430 : : * Jump table flags.
431 : : * Can jump to FDB_RX table from FDB_RX or UNIFIED tables.
432 : : * Can jump to FDB_TX table from FDB_TX or UNIFIED tables.
433 : : * Can jump to UNIFIED table from all tables.
434 : : */
435 : : static uint32_t mlx5_hw_act_dest_table_flag[MLX5DR_TABLE_TYPE_MAX] = {
436 : : MLX5DR_ACTION_FLAG_HWS_RX,
437 : : MLX5DR_ACTION_FLAG_HWS_TX,
438 : : MLX5DR_ACTION_FLAG_HWS_FDB,
439 : : (MLX5DR_ACTION_FLAG_HWS_FDB_RX | MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED),
440 : : (MLX5DR_ACTION_FLAG_HWS_FDB_TX | MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED),
441 : : (MLX5DR_ACTION_FLAG_HWS_FDB_RX | MLX5DR_ACTION_FLAG_HWS_FDB_TX |
442 : : MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED),
443 : : };
444 : :
445 : : /* Ethernet item spec for promiscuous mode. */
446 : : static const struct rte_flow_item_eth ctrl_rx_eth_promisc_spec = {
447 : : .hdr.dst_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
448 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
449 : : .hdr.ether_type = 0,
450 : : };
451 : : /* Ethernet item mask for promiscuous mode. */
452 : : static const struct rte_flow_item_eth ctrl_rx_eth_promisc_mask = {
453 : : .hdr.dst_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
454 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
455 : : .hdr.ether_type = 0,
456 : : };
457 : :
458 : : /* Ethernet item spec for all multicast mode. */
459 : : static const struct rte_flow_item_eth ctrl_rx_eth_mcast_spec = {
460 : : .hdr.dst_addr.addr_bytes = { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 },
461 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
462 : : .hdr.ether_type = 0,
463 : : };
464 : : /* Ethernet item mask for all multicast mode. */
465 : : static const struct rte_flow_item_eth ctrl_rx_eth_mcast_mask = {
466 : : .hdr.dst_addr.addr_bytes = { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 },
467 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
468 : : .hdr.ether_type = 0,
469 : : };
470 : :
471 : : /* Ethernet item spec for IPv4 multicast traffic. */
472 : : static const struct rte_flow_item_eth ctrl_rx_eth_ipv4_mcast_spec = {
473 : : .hdr.dst_addr.addr_bytes = { 0x01, 0x00, 0x5e, 0x00, 0x00, 0x00 },
474 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
475 : : .hdr.ether_type = 0,
476 : : };
477 : : /* Ethernet item mask for IPv4 multicast traffic. */
478 : : static const struct rte_flow_item_eth ctrl_rx_eth_ipv4_mcast_mask = {
479 : : .hdr.dst_addr.addr_bytes = { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 },
480 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
481 : : .hdr.ether_type = 0,
482 : : };
483 : :
484 : : /* Ethernet item spec for IPv6 multicast traffic. */
485 : : static const struct rte_flow_item_eth ctrl_rx_eth_ipv6_mcast_spec = {
486 : : .hdr.dst_addr.addr_bytes = { 0x33, 0x33, 0x00, 0x00, 0x00, 0x00 },
487 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
488 : : .hdr.ether_type = 0,
489 : : };
490 : : /* Ethernet item mask for IPv6 multicast traffic. */
491 : : static const struct rte_flow_item_eth ctrl_rx_eth_ipv6_mcast_mask = {
492 : : .hdr.dst_addr.addr_bytes = { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 },
493 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
494 : : .hdr.ether_type = 0,
495 : : };
496 : :
497 : : /* Ethernet item mask for unicast traffic. */
498 : : static const struct rte_flow_item_eth ctrl_rx_eth_dmac_mask = {
499 : : .hdr.dst_addr.addr_bytes = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
500 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
501 : : .hdr.ether_type = 0,
502 : : };
503 : :
504 : : /* Ethernet item spec for broadcast. */
505 : : static const struct rte_flow_item_eth ctrl_rx_eth_bcast_spec = {
506 : : .hdr.dst_addr.addr_bytes = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
507 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
508 : : .hdr.ether_type = 0,
509 : : };
510 : :
511 : : static inline uint32_t
512 : : flow_hw_q_pending(struct mlx5_priv *priv, uint32_t queue)
513 : : {
514 : 0 : struct mlx5_hw_q *q = &priv->hw_q[queue];
515 : :
516 : : MLX5_ASSERT(q->size >= q->job_idx);
517 : 0 : return (q->size - q->job_idx) + q->ongoing_flow_ops;
518 : : }
519 : :
520 : : static inline void
521 : 0 : flow_hw_q_inc_flow_ops(struct mlx5_priv *priv, uint32_t queue)
522 : : {
523 : 0 : struct mlx5_hw_q *q = &priv->hw_q[queue];
524 : :
525 : 0 : q->ongoing_flow_ops++;
526 : 0 : }
527 : :
528 : : static inline void
529 : : flow_hw_q_dec_flow_ops(struct mlx5_priv *priv, uint32_t queue)
530 : : {
531 : 0 : struct mlx5_hw_q *q = &priv->hw_q[queue];
532 : :
533 : 0 : q->ongoing_flow_ops--;
534 : : }
535 : :
536 : : static inline enum mlx5dr_matcher_insert_mode
537 : : flow_hw_matcher_insert_mode_get(enum rte_flow_table_insertion_type insert_type)
538 : : {
539 : 0 : if (insert_type == RTE_FLOW_TABLE_INSERTION_TYPE_PATTERN)
540 : : return MLX5DR_MATCHER_INSERT_BY_HASH;
541 : : else
542 : 0 : return MLX5DR_MATCHER_INSERT_BY_INDEX;
543 : : }
544 : :
545 : : static inline enum mlx5dr_matcher_distribute_mode
546 : : flow_hw_matcher_distribute_mode_get(enum rte_flow_table_hash_func hash_func)
547 : : {
548 [ # # ]: 0 : if (hash_func == RTE_FLOW_TABLE_HASH_FUNC_LINEAR)
549 : : return MLX5DR_MATCHER_DISTRIBUTE_BY_LINEAR;
550 : : else
551 : 0 : return MLX5DR_MATCHER_DISTRIBUTE_BY_HASH;
552 : : }
553 : :
554 : : /**
555 : : * Set the hash fields according to the @p rss_desc information.
556 : : *
557 : : * @param[in] rss_desc
558 : : * Pointer to the mlx5_flow_rss_desc.
559 : : * @param[out] hash_fields
560 : : * Pointer to the RSS hash fields.
561 : : */
562 : : static void
563 : 0 : flow_hw_hashfields_set(struct mlx5_flow_rss_desc *rss_desc,
564 : : uint64_t *hash_fields)
565 : : {
566 : : uint64_t fields = 0;
567 : : int rss_inner = 0;
568 [ # # ]: 0 : uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
569 : :
570 : : #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
571 [ # # ]: 0 : if (rss_desc->level >= 2)
572 : : rss_inner = 1;
573 : : #endif
574 [ # # ]: 0 : if (rss_types & MLX5_IPV4_LAYER_TYPES) {
575 [ # # ]: 0 : if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
576 : : fields |= IBV_RX_HASH_SRC_IPV4;
577 [ # # ]: 0 : else if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
578 : : fields |= IBV_RX_HASH_DST_IPV4;
579 : : else
580 : : fields |= MLX5_IPV4_IBV_RX_HASH;
581 [ # # ]: 0 : } else if (rss_types & MLX5_IPV6_LAYER_TYPES) {
582 [ # # ]: 0 : if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
583 : : fields |= IBV_RX_HASH_SRC_IPV6;
584 [ # # ]: 0 : else if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
585 : : fields |= IBV_RX_HASH_DST_IPV6;
586 : : else
587 : : fields |= MLX5_IPV6_IBV_RX_HASH;
588 : : }
589 [ # # ]: 0 : if (rss_types & RTE_ETH_RSS_UDP) {
590 [ # # ]: 0 : if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
591 : 0 : fields |= IBV_RX_HASH_SRC_PORT_UDP;
592 [ # # ]: 0 : else if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
593 : 0 : fields |= IBV_RX_HASH_DST_PORT_UDP;
594 : : else
595 : 0 : fields |= MLX5_UDP_IBV_RX_HASH;
596 [ # # ]: 0 : } else if (rss_types & RTE_ETH_RSS_TCP) {
597 [ # # ]: 0 : if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
598 : 0 : fields |= IBV_RX_HASH_SRC_PORT_TCP;
599 [ # # ]: 0 : else if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
600 : 0 : fields |= IBV_RX_HASH_DST_PORT_TCP;
601 : : else
602 : 0 : fields |= MLX5_TCP_IBV_RX_HASH;
603 : : }
604 [ # # ]: 0 : if (rss_types & RTE_ETH_RSS_ESP)
605 : 0 : fields |= IBV_RX_HASH_IPSEC_SPI;
606 [ # # ]: 0 : if (rss_inner)
607 : 0 : fields |= IBV_RX_HASH_INNER;
608 : 0 : *hash_fields |= fields;
609 : 0 : }
610 : :
611 : : RTE_EXPORT_EXPERIMENTAL_SYMBOL(rte_pmd_mlx5_rss_tir_register, 26.03)
612 : : int
613 : 0 : rte_pmd_mlx5_rss_tir_register(uint16_t port_id,
614 : : const struct rte_flow_action_rss *rss,
615 : : struct rte_pmd_mlx5_rss_devx *devx)
616 : : {
617 : : struct rte_eth_dev *dev;
618 : : struct mlx5_hrxq *hrxq;
619 : 0 : struct mlx5_flow_rss_desc rss_desc = {
620 : : .hws_flags = MLX5DR_ACTION_FLAG_ROOT_RX,
621 : : };
622 : :
623 [ # # ]: 0 : if (rte_eth_dev_is_valid_port(port_id) < 0) {
624 : 0 : DRV_LOG(ERR, "port %u: no Ethernet device", port_id);
625 : 0 : rte_errno = ENODEV;
626 : 0 : return -rte_errno;
627 : : }
628 [ # # # # ]: 0 : if (!rss->queue_num || !rss->queue) {
629 : 0 : DRV_LOG(ERR, "port %u: invalid RSS queues configuration", port_id);
630 : 0 : rte_errno = EINVAL;
631 : 0 : return -rte_errno;
632 : : }
633 [ # # # # ]: 0 : if (rss->key && rss->key_len != MLX5_RSS_HASH_KEY_LEN) {
634 : 0 : DRV_LOG(ERR, "port %u: RSS key length must be %d",
635 : : port_id, MLX5_RSS_HASH_KEY_LEN);
636 : 0 : rte_errno = EINVAL;
637 : 0 : return -rte_errno;
638 : : }
639 [ # # ]: 0 : dev = &rte_eth_devices[port_id];
640 [ # # ]: 0 : if (!mlx5_hws_active(dev)) {
641 : 0 : DRV_LOG(ERR, "port %u: HWS not active", port_id);
642 : 0 : rte_errno = EINVAL;
643 : 0 : return -rte_errno;
644 : : }
645 : 0 : rss_desc.queue_num = rss->queue_num;
646 : 0 : rss_desc.const_q = rss->queue;
647 [ # # ]: 0 : if (rss->queue_num > 1) {
648 [ # # ]: 0 : memcpy(rss_desc.key,
649 : : rss->key ? rss->key : mlx5_rss_hash_default_key,
650 : : MLX5_RSS_HASH_KEY_LEN);
651 : 0 : rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
652 [ # # ]: 0 : rss_desc.types = !rss->types ? RTE_ETH_RSS_IP : rss->types;
653 : 0 : rss_desc.symmetric_hash_function = MLX5_RSS_IS_SYMM(rss->func);
654 : 0 : flow_hw_hashfields_set(&rss_desc, &rss_desc.hash_fields);
655 : 0 : mlx5_flow_dv_action_rss_l34_hash_adjust(rss->types,
656 : : &rss_desc.hash_fields);
657 [ # # ]: 0 : if (rss->level > 1) {
658 : 0 : rss_desc.hash_fields |= IBV_RX_HASH_INNER;
659 : 0 : rss_desc.tunnel = 1;
660 : : }
661 : : }
662 : :
663 : 0 : hrxq = mlx5_hrxq_get(dev, &rss_desc);
664 [ # # ]: 0 : if (!hrxq) {
665 : 0 : DRV_LOG(ERR, "port %u: failed to allocate DevX", port_id);
666 : 0 : return -rte_errno;
667 : : }
668 : 0 : devx->destroy_handle = hrxq;
669 : 0 : devx->obj = hrxq->tir->obj;
670 : 0 : devx->id = hrxq->tir->id;
671 : :
672 : 0 : return 0;
673 : : }
674 : :
675 : : RTE_EXPORT_EXPERIMENTAL_SYMBOL(rte_pmd_mlx5_rss_tir_unregister, 26.03)
676 : : int
677 : 0 : rte_pmd_mlx5_rss_tir_unregister(uint16_t port_id, void *handle)
678 : : {
679 : : struct rte_eth_dev *dev;
680 : : struct mlx5_hrxq *hrxq = handle;
681 : :
682 [ # # ]: 0 : if (rte_eth_dev_is_valid_port(port_id) < 0) {
683 : 0 : DRV_LOG(ERR, "port %u: no Ethernet device", port_id);
684 : 0 : rte_errno = ENODEV;
685 : 0 : return -rte_errno;
686 : : }
687 : 0 : dev = &rte_eth_devices[port_id];
688 : 0 : mlx5_hrxq_obj_release(dev, hrxq);
689 : 0 : return 0;
690 : : }
691 : :
692 : : uint64_t
693 : 0 : mlx5_flow_hw_action_flags_get(const struct rte_flow_action actions[],
694 : : const struct rte_flow_action **qrss,
695 : : const struct rte_flow_action **mark,
696 : : int *encap_idx,
697 : : int *act_cnt,
698 : : struct rte_flow_error *error)
699 : : {
700 : : uint64_t action_flags = 0;
701 : : const struct rte_flow_action *action;
702 : : const struct rte_flow_action_raw_encap *raw_encap;
703 : : int raw_decap_idx = -1;
704 : : int action_idx;
705 : :
706 : 0 : *encap_idx = -1;
707 : : action_idx = 0;
708 [ # # ]: 0 : for (action = actions; action->type != RTE_FLOW_ACTION_TYPE_END; action++) {
709 : 0 : int type = (int)action->type;
710 [ # # # # : 0 : switch (type) {
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
711 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT:
712 [ # # # # : 0 : switch (MLX5_INDIRECT_ACTION_TYPE_GET(action->conf)) {
# # ]
713 : 0 : case MLX5_INDIRECT_ACTION_TYPE_RSS:
714 : 0 : goto rss;
715 : 0 : case MLX5_INDIRECT_ACTION_TYPE_AGE:
716 : 0 : goto age;
717 : 0 : case MLX5_INDIRECT_ACTION_TYPE_COUNT:
718 : 0 : goto count;
719 : 0 : case MLX5_INDIRECT_ACTION_TYPE_CT:
720 : 0 : goto ct;
721 : 0 : case MLX5_INDIRECT_ACTION_TYPE_METER_MARK:
722 : 0 : goto meter;
723 : 0 : default:
724 : 0 : goto error;
725 : : }
726 : : break;
727 : 0 : case RTE_FLOW_ACTION_TYPE_DROP:
728 : 0 : action_flags |= MLX5_FLOW_ACTION_DROP;
729 : 0 : break;
730 : 0 : case RTE_FLOW_ACTION_TYPE_FLAG:
731 : 0 : action_flags |= MLX5_FLOW_ACTION_FLAG;
732 : 0 : break;
733 : 0 : case RTE_FLOW_ACTION_TYPE_MARK:
734 : 0 : action_flags |= MLX5_FLOW_ACTION_MARK;
735 : 0 : *mark = action;
736 : 0 : break;
737 : 0 : case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
738 : 0 : action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
739 : 0 : break;
740 : 0 : case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
741 : 0 : action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
742 : 0 : break;
743 : 0 : case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
744 : 0 : action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
745 : 0 : break;
746 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP:
747 : 0 : action_flags |= MLX5_FLOW_ACTION_JUMP;
748 : 0 : break;
749 : 0 : case RTE_FLOW_ACTION_TYPE_QUEUE:
750 : 0 : action_flags |= MLX5_FLOW_ACTION_QUEUE;
751 : 0 : *qrss = action;
752 : 0 : break;
753 : : case RTE_FLOW_ACTION_TYPE_RSS:
754 : 0 : rss:
755 : 0 : action_flags |= MLX5_FLOW_ACTION_RSS;
756 : 0 : *qrss = action;
757 : 0 : break;
758 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
759 : : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
760 : 0 : action_flags |= MLX5_FLOW_ACTION_ENCAP;
761 : 0 : *encap_idx = action_idx;
762 : 0 : break;
763 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
764 : 0 : action_flags |= MLX5_FLOW_ACTION_ENCAP;
765 : 0 : raw_encap = action->conf;
766 [ # # ]: 0 : if (raw_encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
767 : 0 : *encap_idx = raw_decap_idx != -1 ?
768 [ # # ]: 0 : raw_decap_idx : action_idx;
769 : : break;
770 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
771 : : case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
772 : 0 : action_flags |= MLX5_FLOW_ACTION_DECAP;
773 : 0 : break;
774 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
775 : 0 : action_flags |= MLX5_FLOW_ACTION_DECAP;
776 : : raw_decap_idx = action_idx;
777 : 0 : break;
778 : 0 : case RTE_FLOW_ACTION_TYPE_SEND_TO_KERNEL:
779 : 0 : action_flags |= MLX5_FLOW_ACTION_SEND_TO_KERNEL;
780 : 0 : break;
781 : 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
782 : 0 : action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
783 : 0 : break;
784 : 0 : case RTE_FLOW_ACTION_TYPE_PORT_ID:
785 : : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
786 : 0 : action_flags |= MLX5_FLOW_ACTION_PORT_ID;
787 : 0 : break;
788 : : case RTE_FLOW_ACTION_TYPE_AGE:
789 : 0 : age:
790 : 0 : action_flags |= MLX5_FLOW_ACTION_AGE;
791 : 0 : break;
792 : : case RTE_FLOW_ACTION_TYPE_COUNT:
793 : 0 : count:
794 : 0 : action_flags |= MLX5_FLOW_ACTION_COUNT;
795 : 0 : break;
796 : : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
797 : 0 : ct:
798 : 0 : action_flags |= MLX5_FLOW_ACTION_CT;
799 : 0 : break;
800 : : case RTE_FLOW_ACTION_TYPE_METER_MARK:
801 : 0 : meter:
802 : 0 : action_flags |= MLX5_FLOW_ACTION_METER;
803 : 0 : break;
804 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
805 : 0 : action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
806 : 0 : break;
807 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
808 : 0 : action_flags |= MLX5_FLOW_ACTION_JUMP_TO_TABLE_INDEX;
809 : 0 : break;
810 : 0 : case RTE_FLOW_ACTION_TYPE_SAMPLE:
811 : 0 : action_flags |= MLX5_FLOW_ACTION_SAMPLE;
812 : 0 : break;
813 : : case RTE_FLOW_ACTION_TYPE_VOID:
814 : : case RTE_FLOW_ACTION_TYPE_END:
815 : : break;
816 : 0 : default:
817 : 0 : goto error;
818 : : }
819 : 0 : action_idx++;
820 : : }
821 [ # # ]: 0 : if (*encap_idx == -1)
822 : 0 : *encap_idx = action_idx;
823 : 0 : action_idx++; /* The END action. */
824 : 0 : *act_cnt = action_idx;
825 : 0 : return action_flags;
826 : 0 : error:
827 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
828 : : action, "invalid flow action");
829 : 0 : return 0;
830 : : }
831 : :
832 : : /**
833 : : * Register destination table DR jump action.
834 : : *
835 : : * @param[in] dev
836 : : * Pointer to the rte_eth_dev structure.
837 : : * @param[in] table_attr
838 : : * Pointer to the flow attributes.
839 : : * @param[in] dest_group
840 : : * The destination group ID.
841 : : * @param[out] error
842 : : * Pointer to error structure.
843 : : *
844 : : * @return
845 : : * Table on success, NULL otherwise and rte_errno is set.
846 : : */
847 : : static struct mlx5_hw_jump_action *
848 : 0 : flow_hw_jump_action_register(struct rte_eth_dev *dev,
849 : : const struct mlx5_flow_template_table_cfg *cfg,
850 : : uint32_t dest_group,
851 : : struct rte_flow_error *error)
852 : : {
853 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
854 : 0 : struct rte_flow_attr jattr = cfg->attr.flow_attr;
855 : 0 : uint32_t specialize = cfg->attr.specialize;
856 : : struct mlx5_flow_group *grp;
857 : 0 : struct mlx5_flow_cb_ctx ctx = {
858 : : .dev = dev,
859 : : .error = error,
860 : : .data = &jattr,
861 : : .data2 = &specialize,
862 : : };
863 : : struct mlx5_list_entry *ge;
864 : : uint32_t target_group;
865 : :
866 : 0 : target_group = dest_group;
867 [ # # ]: 0 : if (flow_hw_translate_group(dev, cfg, dest_group, &target_group, error))
868 : : return NULL;
869 : 0 : jattr.group = target_group;
870 : 0 : ge = mlx5_hlist_register(priv->sh->flow_tbls, target_group, &ctx);
871 [ # # ]: 0 : if (!ge)
872 : : return NULL;
873 : : grp = container_of(ge, struct mlx5_flow_group, entry);
874 : 0 : return &grp->jump;
875 : : }
876 : :
877 : : /**
878 : : * Release jump action.
879 : : *
880 : : * @param[in] dev
881 : : * Pointer to the rte_eth_dev structure.
882 : : * @param[in] jump
883 : : * Pointer to the jump action.
884 : : */
885 : :
886 : : static void
887 : : flow_hw_jump_release(struct rte_eth_dev *dev, struct mlx5_hw_jump_action *jump)
888 : : {
889 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
890 : : struct mlx5_flow_group *grp;
891 : :
892 : 0 : grp = container_of(jump, struct mlx5_flow_group, jump);
893 : 0 : mlx5_hlist_unregister(priv->sh->flow_tbls, &grp->entry);
894 : 0 : }
895 : :
896 : : /**
897 : : * Register queue/RSS action.
898 : : *
899 : : * @param[in] dev
900 : : * Pointer to the rte_eth_dev structure.
901 : : * @param[in] hws_flags
902 : : * DR action flags.
903 : : * @param[in] action
904 : : * rte flow action.
905 : : * @param[in] item_flags
906 : : * Item flags for non template rule.
907 : : * @param[in] is_template
908 : : * True if it is a template rule.
909 : : *
910 : : * @return
911 : : * Table on success, NULL otherwise and rte_errno is set.
912 : : */
913 : : static inline struct mlx5_hrxq*
914 : 0 : flow_hw_tir_action_register(struct rte_eth_dev *dev,
915 : : uint32_t hws_flags,
916 : : const struct rte_flow_action *action)
917 : : {
918 : 0 : struct mlx5_flow_rss_desc rss_desc = {
919 : : .hws_flags = hws_flags,
920 : : };
921 : : struct mlx5_hrxq *hrxq;
922 : :
923 [ # # ]: 0 : if (action->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
924 : 0 : const struct rte_flow_action_queue *queue = action->conf;
925 : :
926 : 0 : rss_desc.const_q = &queue->index;
927 : 0 : rss_desc.queue_num = 1;
928 : : } else {
929 : 0 : const struct rte_flow_action_rss *rss = action->conf;
930 : :
931 : 0 : rss_desc.queue_num = rss->queue_num;
932 : 0 : rss_desc.const_q = rss->queue;
933 : 0 : memcpy(rss_desc.key,
934 [ # # ]: 0 : !rss->key ? mlx5_rss_hash_default_key : rss->key,
935 : : MLX5_RSS_HASH_KEY_LEN);
936 : 0 : rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
937 [ # # ]: 0 : rss_desc.types = !rss->types ? RTE_ETH_RSS_IP : rss->types;
938 : 0 : rss_desc.symmetric_hash_function = MLX5_RSS_IS_SYMM(rss->func);
939 : 0 : flow_hw_hashfields_set(&rss_desc, &rss_desc.hash_fields);
940 : 0 : mlx5_flow_dv_action_rss_l34_hash_adjust(rss->types,
941 : : &rss_desc.hash_fields);
942 [ # # ]: 0 : if (rss->level > 1) {
943 : 0 : rss_desc.hash_fields |= IBV_RX_HASH_INNER;
944 : 0 : rss_desc.tunnel = 1;
945 : : }
946 : : }
947 : 0 : hrxq = mlx5_hrxq_get(dev, &rss_desc);
948 : 0 : return hrxq;
949 : : }
950 : :
951 : : static __rte_always_inline int
952 : : flow_hw_ct_compile(struct rte_eth_dev *dev,
953 : : uint32_t queue, uint32_t idx,
954 : : struct mlx5dr_rule_action *rule_act)
955 : : {
956 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
957 : : struct mlx5_aso_ct_action *ct;
958 : :
959 : 0 : ct = mlx5_ipool_get(priv->hws_ctpool->cts, idx);
960 [ # # # # : 0 : if (!ct || (!priv->shared_host && mlx5_aso_ct_available(priv->sh, queue, ct)))
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # ]
961 : : return -1;
962 : 0 : rule_act->action = priv->hws_ctpool->dr_action;
963 : 0 : rule_act->aso_ct.offset = ct->offset;
964 : 0 : rule_act->aso_ct.direction = ct->is_original ?
965 : 0 : MLX5DR_ACTION_ASO_CT_DIRECTION_INITIATOR :
966 : : MLX5DR_ACTION_ASO_CT_DIRECTION_RESPONDER;
967 : : return 0;
968 : : }
969 : :
970 : : static void
971 : : flow_hw_template_destroy_reformat_action(struct mlx5_hw_encap_decap_action *encap_decap)
972 : : {
973 [ # # # # ]: 0 : if (encap_decap->action && !encap_decap->multi_pattern)
974 : 0 : mlx5dr_action_destroy(encap_decap->action);
975 : : }
976 : :
977 : : static void
978 : : flow_hw_template_destroy_mhdr_action(struct mlx5_hw_modify_header_action *mhdr)
979 : : {
980 [ # # # # ]: 0 : if (mhdr->action && !mhdr->multi_pattern)
981 : 0 : mlx5dr_action_destroy(mhdr->action);
982 : : }
983 : :
984 : : /**
985 : : * Destroy DR actions created by action template.
986 : : *
987 : : * For DR actions created during table creation's action translate.
988 : : * Need to destroy the DR action when destroying the table.
989 : : *
990 : : * @param[in] dev
991 : : * Pointer to the rte_eth_dev structure.
992 : : * @param[in] acts
993 : : * Pointer to the template HW steering DR actions.
994 : : */
995 : : static void
996 : 0 : __flow_hw_actions_release(struct rte_eth_dev *dev, struct mlx5_hw_actions *acts)
997 : : {
998 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
999 : :
1000 [ # # ]: 0 : if (acts->mark)
1001 [ # # ]: 0 : if (!(rte_atomic_fetch_sub_explicit(&priv->hws_mark_refcnt, 1,
1002 : : rte_memory_order_relaxed) - 1))
1003 : 0 : mlx5_flow_hw_rxq_flag_set(dev, false);
1004 : :
1005 [ # # ]: 0 : if (acts->jump) {
1006 : : struct mlx5_flow_group *grp;
1007 : :
1008 : 0 : grp = container_of
1009 : : (acts->jump, struct mlx5_flow_group, jump);
1010 : 0 : mlx5_hlist_unregister(priv->sh->flow_tbls, &grp->entry);
1011 : 0 : acts->jump = NULL;
1012 : : }
1013 [ # # ]: 0 : if (acts->tir) {
1014 : 0 : mlx5_hrxq_release(dev, acts->tir->idx);
1015 : 0 : acts->tir = NULL;
1016 : : }
1017 [ # # ]: 0 : if (acts->encap_decap) {
1018 : : flow_hw_template_destroy_reformat_action(acts->encap_decap);
1019 : 0 : mlx5_free(acts->encap_decap);
1020 : 0 : acts->encap_decap = NULL;
1021 : : }
1022 [ # # ]: 0 : if (acts->push_remove) {
1023 [ # # ]: 0 : if (acts->push_remove->action)
1024 : 0 : mlx5dr_action_destroy(acts->push_remove->action);
1025 : 0 : mlx5_free(acts->push_remove);
1026 : 0 : acts->push_remove = NULL;
1027 : : }
1028 [ # # ]: 0 : if (acts->mhdr) {
1029 : : flow_hw_template_destroy_mhdr_action(acts->mhdr);
1030 : 0 : mlx5_free(acts->mhdr);
1031 : 0 : acts->mhdr = NULL;
1032 : : }
1033 [ # # ]: 0 : if (mlx5_hws_cnt_id_valid(acts->cnt_id)) {
1034 [ # # ]: 0 : mlx5_hws_cnt_shared_put(priv->hws_cpool, &acts->cnt_id);
1035 : 0 : acts->cnt_id = 0;
1036 : : }
1037 [ # # ]: 0 : if (acts->mtr_id) {
1038 : 0 : mlx5_ipool_free(priv->hws_mpool->idx_pool, acts->mtr_id);
1039 : 0 : acts->mtr_id = 0;
1040 : : }
1041 : 0 : }
1042 : :
1043 : : /**
1044 : : * Release the action data back into the pool without destroy any action.
1045 : : *
1046 : : * @param[in] dev
1047 : : * Pointer to the rte_eth_dev structure.
1048 : : * @param[in] acts
1049 : : * Pointer to the template HW steering DR actions.
1050 : : */
1051 : : static inline void
1052 : 0 : __flow_hw_act_data_flush(struct rte_eth_dev *dev, struct mlx5_hw_actions *acts)
1053 : : {
1054 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1055 : : struct mlx5_action_construct_data *data;
1056 : :
1057 [ # # ]: 0 : while (!LIST_EMPTY(&acts->act_list)) {
1058 : : data = LIST_FIRST(&acts->act_list);
1059 [ # # ]: 0 : LIST_REMOVE(data, next);
1060 : 0 : mlx5_ipool_free(priv->acts_ipool, data->idx);
1061 : : }
1062 : 0 : }
1063 : :
1064 : : /*
1065 : : * Destroy DR actions created by action template.
1066 : : *
1067 : : * For DR actions created during table creation's action translate.
1068 : : * Need to destroy the DR action when destroying the table.
1069 : : *
1070 : : * @param[in] dev
1071 : : * Pointer to the rte_eth_dev structure.
1072 : : * @param[in] acts
1073 : : * Pointer to the template HW steering DR actions.
1074 : : */
1075 : : static void
1076 : 0 : __flow_hw_action_template_destroy(struct rte_eth_dev *dev, struct mlx5_hw_actions *acts)
1077 : : {
1078 : 0 : __flow_hw_act_data_flush(dev, acts);
1079 : 0 : __flow_hw_actions_release(dev, acts);
1080 : 0 : }
1081 : :
1082 : : /**
1083 : : * Append dynamic action to the dynamic action list.
1084 : : *
1085 : : * @param[in] priv
1086 : : * Pointer to the port private data structure.
1087 : : * @param[in] acts
1088 : : * Pointer to the template HW steering DR actions.
1089 : : * @param[in] type
1090 : : * Action type.
1091 : : * @param[in] action_src
1092 : : * Offset of source rte flow action.
1093 : : * @param[in] action_dst
1094 : : * Offset of destination DR action.
1095 : : *
1096 : : * @return
1097 : : * 0 on success, negative value otherwise and rte_errno is set.
1098 : : */
1099 : : static __rte_always_inline struct mlx5_action_construct_data *
1100 : : __flow_hw_act_data_alloc(struct mlx5_priv *priv,
1101 : : enum rte_flow_action_type type,
1102 : : uint16_t action_src,
1103 : : uint16_t action_dst)
1104 : : {
1105 : : struct mlx5_action_construct_data *act_data;
1106 : 0 : uint32_t idx = 0;
1107 : :
1108 : 0 : act_data = mlx5_ipool_zmalloc(priv->acts_ipool, &idx);
1109 [ # # # # : 0 : if (!act_data)
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
1110 : : return NULL;
1111 : 0 : act_data->idx = idx;
1112 : 0 : act_data->type = type;
1113 : 0 : act_data->action_src = action_src;
1114 : 0 : act_data->action_dst = action_dst;
1115 : : return act_data;
1116 : : }
1117 : :
1118 : : /**
1119 : : * Append dynamic action to the dynamic action list.
1120 : : *
1121 : : * @param[in] priv
1122 : : * Pointer to the port private data structure.
1123 : : * @param[in] acts
1124 : : * Pointer to the template HW steering DR actions.
1125 : : * @param[in] type
1126 : : * Action type.
1127 : : * @param[in] action_src
1128 : : * Offset of source rte flow action.
1129 : : * @param[in] action_dst
1130 : : * Offset of destination DR action.
1131 : : *
1132 : : * @return
1133 : : * 0 on success, negative value otherwise and rte_errno is set.
1134 : : */
1135 : : static __rte_always_inline int
1136 : : __flow_hw_act_data_general_append(struct mlx5_priv *priv,
1137 : : struct mlx5_hw_actions *acts,
1138 : : enum rte_flow_action_type type,
1139 : : uint16_t action_src,
1140 : : uint16_t action_dst)
1141 : : {
1142 : : struct mlx5_action_construct_data *act_data;
1143 : :
1144 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1145 : : if (!act_data)
1146 : : return -1;
1147 [ # # # # : 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
1148 : : return 0;
1149 : : }
1150 : :
1151 : : static __rte_always_inline int
1152 : : __flow_hw_act_data_indirect_append(struct mlx5_priv *priv,
1153 : : struct mlx5_hw_actions *acts,
1154 : : enum rte_flow_action_type type,
1155 : : enum rte_flow_action_type mask_type,
1156 : : uint16_t action_src,
1157 : : uint16_t action_dst)
1158 : : {
1159 : : struct mlx5_action_construct_data *act_data;
1160 : :
1161 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1162 : : if (!act_data)
1163 : : return -1;
1164 : 0 : act_data->indirect.expected_type = mask_type;
1165 [ # # ]: 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
1166 : : return 0;
1167 : : }
1168 : :
1169 : : static __rte_always_inline int
1170 : : flow_hw_act_data_indirect_list_append(struct mlx5_priv *priv,
1171 : : struct mlx5_hw_actions *acts,
1172 : : enum rte_flow_action_type type,
1173 : : uint16_t action_src, uint16_t action_dst,
1174 : : indirect_list_callback_t cb)
1175 : : {
1176 : : struct mlx5_action_construct_data *act_data;
1177 : :
1178 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1179 : : if (!act_data)
1180 : 0 : return -1;
1181 : 0 : act_data->indirect_list_cb = cb;
1182 [ # # # # : 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
# # ]
1183 : 0 : return 0;
1184 : : }
1185 : : /**
1186 : : * Append dynamic encap action to the dynamic action list.
1187 : : *
1188 : : * @param[in] priv
1189 : : * Pointer to the port private data structure.
1190 : : * @param[in] acts
1191 : : * Pointer to the template HW steering DR actions.
1192 : : * @param[in] type
1193 : : * Action type.
1194 : : * @param[in] action_src
1195 : : * Offset of source rte flow action.
1196 : : * @param[in] action_dst
1197 : : * Offset of destination DR action.
1198 : : * @param[in] len
1199 : : * Length of the data to be updated.
1200 : : *
1201 : : * @return
1202 : : * 0 on success, negative value otherwise and rte_errno is set.
1203 : : */
1204 : : static __rte_always_inline int
1205 : : __flow_hw_act_data_encap_append(struct mlx5_priv *priv,
1206 : : struct mlx5_hw_actions *acts,
1207 : : enum rte_flow_action_type type,
1208 : : uint16_t action_src,
1209 : : uint16_t action_dst,
1210 : : uint16_t len)
1211 : : {
1212 : : struct mlx5_action_construct_data *act_data;
1213 : :
1214 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1215 : : if (!act_data)
1216 : : return -1;
1217 : 0 : act_data->encap.len = len;
1218 [ # # ]: 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
1219 : : return 0;
1220 : : }
1221 : :
1222 : : /**
1223 : : * Append dynamic push action to the dynamic action list.
1224 : : *
1225 : : * @param[in] dev
1226 : : * Pointer to the port.
1227 : : * @param[in] acts
1228 : : * Pointer to the template HW steering DR actions.
1229 : : * @param[in] type
1230 : : * Action type.
1231 : : * @param[in] action_src
1232 : : * Offset of source rte flow action.
1233 : : * @param[in] action_dst
1234 : : * Offset of destination DR action.
1235 : : * @param[in] len
1236 : : * Length of the data to be updated.
1237 : : *
1238 : : * @return
1239 : : * Data pointer on success, NULL otherwise and rte_errno is set.
1240 : : */
1241 : : static __rte_always_inline void *
1242 : : __flow_hw_act_data_push_append(struct rte_eth_dev *dev,
1243 : : struct mlx5_hw_actions *acts,
1244 : : enum rte_flow_action_type type,
1245 : : uint16_t action_src,
1246 : : uint16_t action_dst,
1247 : : uint16_t len)
1248 : : {
1249 : : struct mlx5_action_construct_data *act_data;
1250 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1251 : :
1252 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1253 : : if (!act_data)
1254 : : return NULL;
1255 : 0 : act_data->ipv6_ext.len = len;
1256 [ # # ]: 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
1257 : : return act_data;
1258 : : }
1259 : :
1260 : : static __rte_always_inline int
1261 : : __flow_hw_act_data_hdr_modify_append(struct mlx5_priv *priv,
1262 : : struct mlx5_hw_actions *acts,
1263 : : enum rte_flow_action_type type,
1264 : : uint16_t action_src,
1265 : : uint16_t action_dst,
1266 : : const struct rte_flow_action_modify_field *mf,
1267 : : uint16_t mhdr_cmds_off,
1268 : : uint16_t mhdr_cmds_end,
1269 : : bool shared,
1270 : : struct field_modify_info *field,
1271 : : struct field_modify_info *dcopy,
1272 : : uint32_t *mask)
1273 : : {
1274 : : struct mlx5_action_construct_data *act_data;
1275 : :
1276 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1277 : : if (!act_data)
1278 : : return -1;
1279 : 0 : act_data->modify_header.action = *mf;
1280 : 0 : act_data->modify_header.mhdr_cmds_off = mhdr_cmds_off;
1281 : 0 : act_data->modify_header.mhdr_cmds_end = mhdr_cmds_end;
1282 : 0 : act_data->modify_header.shared = shared;
1283 [ # # ]: 0 : rte_memcpy(act_data->modify_header.field, field,
1284 : : sizeof(*field) * MLX5_ACT_MAX_MOD_FIELDS);
1285 [ # # ]: 0 : rte_memcpy(act_data->modify_header.dcopy, dcopy,
1286 : : sizeof(*dcopy) * MLX5_ACT_MAX_MOD_FIELDS);
1287 : : rte_memcpy(act_data->modify_header.mask, mask,
1288 : : sizeof(*mask) * MLX5_ACT_MAX_MOD_FIELDS);
1289 [ # # ]: 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
1290 : : return 0;
1291 : : }
1292 : :
1293 : : /**
1294 : : * Append shared RSS action to the dynamic action list.
1295 : : *
1296 : : * @param[in] priv
1297 : : * Pointer to the port private data structure.
1298 : : * @param[in] acts
1299 : : * Pointer to the template HW steering DR actions.
1300 : : * @param[in] type
1301 : : * Action type.
1302 : : * @param[in] action_src
1303 : : * Offset of source rte flow action.
1304 : : * @param[in] action_dst
1305 : : * Offset of destination DR action.
1306 : : * @param[in] idx
1307 : : * Shared RSS index.
1308 : : * @param[in] rss
1309 : : * Pointer to the shared RSS info.
1310 : : *
1311 : : * @return
1312 : : * 0 on success, negative value otherwise and rte_errno is set.
1313 : : */
1314 : : static __rte_always_inline int
1315 : : __flow_hw_act_data_shared_rss_append(struct mlx5_priv *priv,
1316 : : struct mlx5_hw_actions *acts,
1317 : : enum rte_flow_action_type type,
1318 : : uint16_t action_src,
1319 : : uint16_t action_dst,
1320 : : uint32_t idx,
1321 : : struct mlx5_shared_action_rss *rss)
1322 : : {
1323 : : struct mlx5_action_construct_data *act_data;
1324 : :
1325 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1326 : : if (!act_data)
1327 : : return -1;
1328 : 0 : act_data->shared_rss.level = rss->origin.level;
1329 [ # # ]: 0 : act_data->shared_rss.types = !rss->origin.types ? RTE_ETH_RSS_IP :
1330 : : rss->origin.types;
1331 : 0 : act_data->shared_rss.idx = idx;
1332 : 0 : act_data->shared_rss.symmetric_hash_function =
1333 : 0 : MLX5_RSS_IS_SYMM(rss->origin.func);
1334 [ # # ]: 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
1335 : : return 0;
1336 : : }
1337 : :
1338 : : /**
1339 : : * Append shared counter action to the dynamic action list.
1340 : : *
1341 : : * @param[in] priv
1342 : : * Pointer to the port private data structure.
1343 : : * @param[in] acts
1344 : : * Pointer to the template HW steering DR actions.
1345 : : * @param[in] type
1346 : : * Action type.
1347 : : * @param[in] action_src
1348 : : * Offset of source rte flow action.
1349 : : * @param[in] action_dst
1350 : : * Offset of destination DR action.
1351 : : * @param[in] cnt_id
1352 : : * Shared counter id.
1353 : : *
1354 : : * @return
1355 : : * 0 on success, negative value otherwise and rte_errno is set.
1356 : : */
1357 : : static __rte_always_inline int
1358 : : __flow_hw_act_data_shared_cnt_append(struct mlx5_priv *priv,
1359 : : struct mlx5_hw_actions *acts,
1360 : : enum rte_flow_action_type type,
1361 : : uint16_t action_src,
1362 : : uint16_t action_dst,
1363 : : cnt_id_t cnt_id)
1364 : : {
1365 : : struct mlx5_action_construct_data *act_data;
1366 : :
1367 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1368 : : if (!act_data)
1369 : : return -1;
1370 : : act_data->type = type;
1371 : 0 : act_data->shared_counter.id = cnt_id;
1372 [ # # ]: 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
1373 : : return 0;
1374 : : }
1375 : :
1376 : : /**
1377 : : * Append shared meter_mark action to the dynamic action list.
1378 : : *
1379 : : * @param[in] priv
1380 : : * Pointer to the port private data structure.
1381 : : * @param[in] acts
1382 : : * Pointer to the template HW steering DR actions.
1383 : : * @param[in] type
1384 : : * Action type.
1385 : : * @param[in] action_src
1386 : : * Offset of source rte flow action.
1387 : : * @param[in] action_dst
1388 : : * Offset of destination DR action.
1389 : : * @param[in] mtr_id
1390 : : * Shared meter id.
1391 : : *
1392 : : * @return
1393 : : * 0 on success, negative value otherwise and rte_errno is set.
1394 : : */
1395 : : static __rte_always_inline int
1396 : : __flow_hw_act_data_shared_mtr_append(struct mlx5_priv *priv,
1397 : : struct mlx5_hw_actions *acts,
1398 : : enum rte_flow_action_type type,
1399 : : uint16_t action_src,
1400 : : uint16_t action_dst,
1401 : : cnt_id_t mtr_id)
1402 : : { struct mlx5_action_construct_data *act_data;
1403 : :
1404 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1405 : : if (!act_data)
1406 : : return -1;
1407 : : act_data->type = type;
1408 : 0 : act_data->shared_meter.id = mtr_id;
1409 [ # # ]: 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
1410 : : return 0;
1411 : : }
1412 : :
1413 : : /**
1414 : : * Translate shared indirect action.
1415 : : *
1416 : : * @param[in] dev
1417 : : * Pointer to the rte_eth_dev data structure.
1418 : : * @param[in] action
1419 : : * Pointer to the shared indirect rte_flow action.
1420 : : * @param[in] acts
1421 : : * Pointer to the template HW steering DR actions.
1422 : : * @param[in] action_src
1423 : : * Offset of source rte flow action.
1424 : : * @param[in] action_dst
1425 : : * Offset of destination DR action.
1426 : : *
1427 : : * @return
1428 : : * 0 on success, negative value otherwise and rte_errno is set.
1429 : : */
1430 : : static __rte_always_inline int
1431 : : flow_hw_shared_action_translate(struct rte_eth_dev *dev,
1432 : : const struct rte_flow_action *action,
1433 : : struct mlx5_hw_actions *acts,
1434 : : uint16_t action_src,
1435 : : uint16_t action_dst,
1436 : : struct rte_flow_error *error)
1437 : : {
1438 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1439 : : struct mlx5_shared_action_rss *shared_rss;
1440 : 0 : uint32_t act_idx = (uint32_t)(uintptr_t)action->conf;
1441 : 0 : uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
1442 : 0 : uint32_t idx = act_idx &
1443 : : ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
1444 : :
1445 : 0 : switch (type) {
1446 : 0 : case MLX5_INDIRECT_ACTION_TYPE_RSS:
1447 : 0 : shared_rss = mlx5_ipool_get
1448 : 0 : (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
1449 [ # # ]: 0 : if (!shared_rss || __flow_hw_act_data_shared_rss_append
1450 : : (priv, acts,
1451 : : (enum rte_flow_action_type)MLX5_RTE_FLOW_ACTION_TYPE_RSS,
1452 : : action_src, action_dst, idx, shared_rss)) {
1453 : 0 : DRV_LOG(ERR, "port %u Indirect RSS action (handle %p) translate failed",
1454 : : dev->data->port_id, action->conf);
1455 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
1456 : : action, "Indirect RSS action translate failed");
1457 : : }
1458 : : break;
1459 : 0 : case MLX5_INDIRECT_ACTION_TYPE_COUNT:
1460 : : if (__flow_hw_act_data_shared_cnt_append(priv, acts,
1461 : : (enum rte_flow_action_type)
1462 : : MLX5_RTE_FLOW_ACTION_TYPE_COUNT,
1463 : : action_src, action_dst, act_idx)) {
1464 : 0 : DRV_LOG(ERR,
1465 : : "port %u Indirect count action (handle %p) "
1466 : : "translate failed",
1467 : : dev->data->port_id, action->conf);
1468 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
1469 : : action,
1470 : : "Indirect count action translate failed");
1471 : : }
1472 : : break;
1473 : 0 : case MLX5_INDIRECT_ACTION_TYPE_CT:
1474 : : if (flow_hw_ct_compile(dev, MLX5_HW_INV_QUEUE,
1475 : : idx, &acts->rule_acts[action_dst])) {
1476 : 0 : DRV_LOG(ERR, "port %u Indirect CT action (handle %p) translate failed",
1477 : : dev->data->port_id, action->conf);
1478 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
1479 : : action, "Indirect CT action translate failed");
1480 : : }
1481 : : break;
1482 : 0 : case MLX5_INDIRECT_ACTION_TYPE_METER_MARK:
1483 : : if (__flow_hw_act_data_shared_mtr_append(priv, acts,
1484 : : (enum rte_flow_action_type)
1485 : : MLX5_RTE_FLOW_ACTION_TYPE_METER_MARK,
1486 : : action_src, action_dst, idx)) {
1487 : 0 : DRV_LOG(ERR,
1488 : : "port %u Indirect meter mark action (handle %p) "
1489 : : "translate failed",
1490 : : dev->data->port_id, action->conf);
1491 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
1492 : : action,
1493 : : "Indirect meter mark action translate failed");
1494 : : }
1495 : : break;
1496 : 0 : case MLX5_INDIRECT_ACTION_TYPE_QUOTA:
1497 : : flow_hw_construct_quota(priv, &acts->rule_acts[action_dst], idx);
1498 : : break;
1499 : 0 : default:
1500 : 0 : DRV_LOG(ERR, "Unsupported shared action type: %d", type);
1501 : 0 : return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, action,
1502 : : "Unsupported shared action type");
1503 : : }
1504 : : return 0;
1505 : : }
1506 : :
1507 : : static __rte_always_inline bool
1508 : : flow_hw_action_modify_field_is_shared(const struct rte_flow_action *action,
1509 : : const struct rte_flow_action *mask)
1510 : : {
1511 : : const struct rte_flow_action_modify_field *v = action->conf;
1512 : 0 : const struct rte_flow_action_modify_field *m = mask->conf;
1513 : :
1514 : 0 : if (v->src.field == RTE_FLOW_FIELD_VALUE) {
1515 : : uint32_t j;
1516 : :
1517 [ # # ]: 0 : for (j = 0; j < RTE_DIM(m->src.value); ++j) {
1518 : : /*
1519 : : * Immediate value is considered to be masked
1520 : : * (and thus shared by all flow rules), if mask
1521 : : * is non-zero. Partial mask over immediate value
1522 : : * is not allowed.
1523 : : */
1524 [ # # ]: 0 : if (m->src.value[j])
1525 : : return true;
1526 : : }
1527 : : return false;
1528 : : }
1529 [ # # ]: 0 : if (v->src.field == RTE_FLOW_FIELD_POINTER)
1530 : 0 : return m->src.pvalue != NULL;
1531 : : /*
1532 : : * Source field types other than VALUE and
1533 : : * POINTER are always shared.
1534 : : */
1535 : : return true;
1536 : : }
1537 : :
1538 : : static __rte_always_inline bool
1539 : : flow_hw_should_insert_nop(const struct mlx5_hw_modify_header_action *mhdr,
1540 : : const struct mlx5_modification_cmd *cmd,
1541 : : const struct rte_flow_attr *attr)
1542 : : {
1543 : : struct mlx5_modification_cmd last_cmd = { { 0 } };
1544 : : struct mlx5_modification_cmd new_cmd = { { 0 } };
1545 : 0 : const uint32_t cmds_num = mhdr->mhdr_cmds_num;
1546 : : unsigned int last_type;
1547 : : bool should_insert = false;
1548 : :
1549 : : /*
1550 : : * Modify header action list does not require NOPs in root table,
1551 : : * because different type of underlying object is used:
1552 : : * - in root table - MODIFY_HEADER_CONTEXT (does not require NOPs),
1553 : : * - in non-root - either inline modify action or based on Modify Header Pattern
1554 : : * (which requires NOPs).
1555 : : */
1556 [ # # # # ]: 0 : if (attr->group == 0)
1557 : : return false;
1558 [ # # # # ]: 0 : if (cmds_num == 0)
1559 : : return false;
1560 : 0 : last_cmd = *(&mhdr->mhdr_cmds[cmds_num - 1]);
1561 [ # # # # ]: 0 : last_cmd.data0 = rte_be_to_cpu_32(last_cmd.data0);
1562 [ # # # # ]: 0 : last_cmd.data1 = rte_be_to_cpu_32(last_cmd.data1);
1563 : 0 : last_type = last_cmd.action_type;
1564 : 0 : new_cmd = *cmd;
1565 [ # # # # ]: 0 : new_cmd.data0 = rte_be_to_cpu_32(new_cmd.data0);
1566 [ # # # # ]: 0 : new_cmd.data1 = rte_be_to_cpu_32(new_cmd.data1);
1567 [ # # # # : 0 : switch (new_cmd.action_type) {
# # ]
1568 : 0 : case MLX5_MODIFICATION_TYPE_SET:
1569 : : case MLX5_MODIFICATION_TYPE_ADD:
1570 [ # # # # ]: 0 : if (last_type == MLX5_MODIFICATION_TYPE_SET ||
1571 : : last_type == MLX5_MODIFICATION_TYPE_ADD)
1572 : 0 : should_insert = new_cmd.field == last_cmd.field;
1573 : 0 : else if (last_type == MLX5_MODIFICATION_TYPE_COPY ||
1574 [ # # # # ]: 0 : last_type == MLX5_MODIFICATION_TYPE_ADD_FIELD)
1575 : 0 : should_insert = new_cmd.field == last_cmd.dst_field;
1576 : : else if (last_type == MLX5_MODIFICATION_TYPE_NOP)
1577 : : should_insert = false;
1578 : : else
1579 : : MLX5_ASSERT(false); /* Other types are not supported. */
1580 : : break;
1581 : 0 : case MLX5_MODIFICATION_TYPE_COPY:
1582 : : case MLX5_MODIFICATION_TYPE_ADD_FIELD:
1583 [ # # # # ]: 0 : if (last_type == MLX5_MODIFICATION_TYPE_SET ||
1584 : : last_type == MLX5_MODIFICATION_TYPE_ADD)
1585 [ # # # # ]: 0 : should_insert = (new_cmd.field == last_cmd.field ||
1586 [ # # # # ]: 0 : new_cmd.dst_field == last_cmd.field);
1587 : 0 : else if (last_type == MLX5_MODIFICATION_TYPE_COPY ||
1588 [ # # # # ]: 0 : last_type == MLX5_MODIFICATION_TYPE_ADD_FIELD)
1589 [ # # # # ]: 0 : should_insert = (new_cmd.field == last_cmd.dst_field ||
1590 [ # # # # ]: 0 : new_cmd.dst_field == last_cmd.dst_field);
1591 : : else if (last_type == MLX5_MODIFICATION_TYPE_NOP)
1592 : : should_insert = false;
1593 : : else
1594 : : MLX5_ASSERT(false); /* Other types are not supported. */
1595 : : break;
1596 : : default:
1597 : : /* Other action types should be rejected on AT validation. */
1598 : : MLX5_ASSERT(false);
1599 : : break;
1600 : : }
1601 : : return should_insert;
1602 : : }
1603 : :
1604 : : static __rte_always_inline int
1605 : : flow_hw_mhdr_cmd_nop_append(struct mlx5_hw_modify_header_action *mhdr)
1606 : : {
1607 : : struct mlx5_modification_cmd *nop;
1608 : : uint32_t num = mhdr->mhdr_cmds_num;
1609 : :
1610 [ # # # # ]: 0 : if (num + 1 >= MLX5_MHDR_MAX_CMD)
1611 : : return -ENOMEM;
1612 : 0 : nop = mhdr->mhdr_cmds + num;
1613 : : nop->data0 = 0;
1614 : : nop->action_type = MLX5_MODIFICATION_TYPE_NOP;
1615 : 0 : nop->data0 = rte_cpu_to_be_32(nop->data0);
1616 : 0 : nop->data1 = 0;
1617 : 0 : mhdr->mhdr_cmds_num = num + 1;
1618 : : return 0;
1619 : : }
1620 : :
1621 : : static __rte_always_inline int
1622 : : flow_hw_mhdr_cmd_append(struct mlx5_hw_modify_header_action *mhdr,
1623 : : struct mlx5_modification_cmd *cmd)
1624 : : {
1625 : 0 : uint32_t num = mhdr->mhdr_cmds_num;
1626 : :
1627 [ # # ]: 0 : if (num + 1 >= MLX5_MHDR_MAX_CMD)
1628 : : return -ENOMEM;
1629 : 0 : mhdr->mhdr_cmds[num] = *cmd;
1630 : 0 : mhdr->mhdr_cmds_num = num + 1;
1631 : : return 0;
1632 : : }
1633 : :
1634 : : static __rte_always_inline int
1635 : : flow_hw_converted_mhdr_cmds_append(struct mlx5_hw_modify_header_action *mhdr,
1636 : : struct mlx5_flow_dv_modify_hdr_resource *resource,
1637 : : const struct rte_flow_attr *attr)
1638 : : {
1639 : : uint32_t idx;
1640 : : int ret;
1641 : :
1642 [ # # ]: 0 : for (idx = 0; idx < resource->actions_num; ++idx) {
1643 : : struct mlx5_modification_cmd *src = &resource->actions[idx];
1644 : :
1645 [ # # ]: 0 : if (flow_hw_should_insert_nop(mhdr, src, attr)) {
1646 : : ret = flow_hw_mhdr_cmd_nop_append(mhdr);
1647 : : if (ret)
1648 : : return ret;
1649 : : }
1650 : : ret = flow_hw_mhdr_cmd_append(mhdr, src);
1651 : : if (ret)
1652 : : return ret;
1653 : : }
1654 : : return 0;
1655 : : }
1656 : :
1657 : : static __rte_always_inline void
1658 : : flow_hw_modify_field_init(struct mlx5_hw_modify_header_action *mhdr,
1659 : : struct rte_flow_actions_template *at)
1660 : : {
1661 : : memset(mhdr, 0, sizeof(*mhdr));
1662 : : /* Modify header action without any commands is shared by default. */
1663 : 0 : mhdr->shared = true;
1664 : 0 : mhdr->pos = at->mhdr_off;
1665 : : }
1666 : :
1667 : : static __rte_always_inline int
1668 : : flow_hw_modify_field_compile(struct rte_eth_dev *dev,
1669 : : const struct rte_flow_attr *attr,
1670 : : const struct rte_flow_action *action, /* Current action from AT. */
1671 : : const struct rte_flow_action *action_mask, /* Current mask from AT. */
1672 : : struct mlx5_hw_actions *acts,
1673 : : struct mlx5_hw_modify_header_action *mhdr,
1674 : : uint16_t src_pos,
1675 : : struct rte_flow_error *error)
1676 : : {
1677 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1678 : 0 : const struct rte_flow_action_modify_field *conf = action->conf;
1679 : : union {
1680 : : struct mlx5_flow_dv_modify_hdr_resource resource;
1681 : : uint8_t data[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
1682 : : sizeof(struct mlx5_modification_cmd) * MLX5_MHDR_MAX_CMD];
1683 : : } dummy;
1684 : : struct mlx5_flow_dv_modify_hdr_resource *resource;
1685 : 0 : struct rte_flow_item item = {
1686 : : .spec = NULL,
1687 : : .mask = NULL
1688 : : };
1689 : 0 : struct field_modify_info field[MLX5_ACT_MAX_MOD_FIELDS] = {
1690 : : {0, 0, MLX5_MODI_OUT_NONE} };
1691 : 0 : struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {
1692 : : {0, 0, MLX5_MODI_OUT_NONE} };
1693 : 0 : uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = { 0 };
1694 : 0 : uint32_t type, value = 0;
1695 : : uint16_t cmds_start, cmds_end;
1696 : : bool shared;
1697 : : int ret;
1698 : :
1699 : : /*
1700 : : * Modify header action is shared if previous modify_field actions
1701 : : * are shared and currently compiled action is shared.
1702 : : */
1703 : : shared = flow_hw_action_modify_field_is_shared(action, action_mask);
1704 : 0 : mhdr->shared &= shared;
1705 [ # # ]: 0 : if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
1706 : : conf->src.field == RTE_FLOW_FIELD_VALUE) {
1707 [ # # ]: 0 : type = conf->operation == RTE_FLOW_MODIFY_SET ? MLX5_MODIFICATION_TYPE_SET :
1708 : : MLX5_MODIFICATION_TYPE_ADD;
1709 : : /* For SET/ADD fill the destination field (field) first. */
1710 : 0 : mlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,
1711 : 0 : conf->width, dev,
1712 : : attr, error);
1713 : 0 : item.spec = conf->src.field == RTE_FLOW_FIELD_POINTER ?
1714 [ # # ]: 0 : (void *)(uintptr_t)conf->src.pvalue :
1715 : : (void *)(uintptr_t)&conf->src.value;
1716 [ # # ]: 0 : if (conf->dst.field == RTE_FLOW_FIELD_META ||
1717 : : conf->dst.field == RTE_FLOW_FIELD_TAG ||
1718 : : conf->dst.field == RTE_FLOW_FIELD_METER_COLOR ||
1719 : 0 : conf->dst.field == (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG) {
1720 : : uint8_t tag_index = flow_tag_index_get(&conf->dst);
1721 : :
1722 : 0 : value = *(const unaligned_uint32_t *)item.spec;
1723 [ # # # # ]: 0 : if (conf->dst.field == RTE_FLOW_FIELD_TAG &&
1724 : : tag_index == RTE_PMD_MLX5_LINEAR_HASH_TAG_INDEX)
1725 [ # # ]: 0 : value = rte_cpu_to_be_32(value << 16);
1726 : : else
1727 [ # # ]: 0 : value = rte_cpu_to_be_32(value);
1728 : 0 : item.spec = &value;
1729 : : } else if (conf->dst.field == RTE_FLOW_FIELD_GTP_PSC_QFI ||
1730 : : conf->dst.field == RTE_FLOW_FIELD_GENEVE_OPT_TYPE) {
1731 : : /*
1732 : : * Both QFI and Geneve option type are passed as an uint8_t integer,
1733 : : * but it is accessed through a 2nd least significant byte of a 32-bit
1734 : : * field in modify header command.
1735 : : */
1736 : 0 : value = *(const uint8_t *)item.spec;
1737 [ # # ]: 0 : value = rte_cpu_to_be_32(value << 8);
1738 : 0 : item.spec = &value;
1739 : : } else if (conf->dst.field == RTE_FLOW_FIELD_VXLAN_LAST_RSVD) {
1740 : 0 : value = *(const uint8_t *)item.spec << 24;
1741 [ # # ]: 0 : value = rte_cpu_to_be_32(value);
1742 : 0 : item.spec = &value;
1743 : 0 : } else if (conf->dst.field == RTE_FLOW_FIELD_IPV6_DSCP &&
1744 [ # # # # ]: 0 : !(mask[0] & MLX5_IPV6_HDR_ECN_MASK) &&
1745 [ # # ]: 0 : mlx5_dv_modify_ipv6_traffic_class_supported(dev->data->dev_private)) {
1746 : 0 : value = *(const unaligned_uint32_t *)item.spec << MLX5_IPV6_HDR_DSCP_SHIFT;
1747 : 0 : item.spec = &value;
1748 : : }
1749 : : } else {
1750 : 0 : type = conf->operation == RTE_FLOW_MODIFY_SET ?
1751 [ # # ]: 0 : MLX5_MODIFICATION_TYPE_COPY : MLX5_MODIFICATION_TYPE_ADD_FIELD;
1752 : : /* For COPY fill the destination field (dcopy) without mask. */
1753 : 0 : mlx5_flow_field_id_to_modify_info(&conf->dst, dcopy, NULL,
1754 : 0 : conf->width, dev,
1755 : : attr, error);
1756 : : /* Then construct the source field (field) with mask. */
1757 : 0 : mlx5_flow_field_id_to_modify_info(&conf->src, field, mask,
1758 : 0 : conf->width, dev,
1759 : : attr, error);
1760 : : }
1761 : 0 : item.mask = &mask;
1762 : : memset(&dummy, 0, sizeof(dummy));
1763 : : resource = &dummy.resource;
1764 : 0 : ret = mlx5_flow_dv_convert_modify_action(&item, field, dcopy, resource, type, error);
1765 [ # # ]: 0 : if (ret)
1766 : : return ret;
1767 : : MLX5_ASSERT(resource->actions_num > 0);
1768 : : /*
1769 : : * If previous modify field action collide with this one, then insert NOP command.
1770 : : * This NOP command will not be a part of action's command range used to update commands
1771 : : * on rule creation.
1772 : : */
1773 [ # # ]: 0 : if (flow_hw_should_insert_nop(mhdr, &resource->actions[0], attr)) {
1774 : : ret = flow_hw_mhdr_cmd_nop_append(mhdr);
1775 : : if (ret)
1776 : 0 : return rte_flow_error_set(error, ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1777 : : NULL, "too many modify field operations specified");
1778 : : }
1779 : 0 : cmds_start = mhdr->mhdr_cmds_num;
1780 : : ret = flow_hw_converted_mhdr_cmds_append(mhdr, resource, attr);
1781 [ # # ]: 0 : if (ret)
1782 : 0 : return rte_flow_error_set(error, ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1783 : : NULL, "too many modify field operations specified");
1784 : :
1785 : 0 : cmds_end = mhdr->mhdr_cmds_num;
1786 [ # # ]: 0 : if (shared)
1787 : : return 0;
1788 : : ret = __flow_hw_act_data_hdr_modify_append(priv, acts, RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
1789 : 0 : src_pos, mhdr->pos, conf,
1790 : : cmds_start, cmds_end, shared,
1791 : : field, dcopy, mask);
1792 : : if (ret)
1793 : 0 : return rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1794 : : NULL, "not enough memory to store modify field metadata");
1795 : : return 0;
1796 : : }
1797 : :
1798 : : static uint32_t
1799 : 0 : flow_hw_count_nop_modify_field(struct mlx5_hw_modify_header_action *mhdr)
1800 : : {
1801 : : uint32_t i;
1802 : : uint32_t nops = 0;
1803 : :
1804 [ # # ]: 0 : for (i = 0; i < mhdr->mhdr_cmds_num; ++i) {
1805 : 0 : struct mlx5_modification_cmd cmd = mhdr->mhdr_cmds[i];
1806 : :
1807 [ # # ]: 0 : cmd.data0 = rte_be_to_cpu_32(cmd.data0);
1808 [ # # ]: 0 : if (cmd.action_type == MLX5_MODIFICATION_TYPE_NOP)
1809 : 0 : ++nops;
1810 : : }
1811 : 0 : return nops;
1812 : : }
1813 : :
1814 : : static int
1815 : 0 : flow_hw_validate_compiled_modify_field(struct rte_eth_dev *dev,
1816 : : const struct mlx5_flow_template_table_cfg *cfg,
1817 : : struct mlx5_hw_modify_header_action *mhdr,
1818 : : struct rte_flow_error *error)
1819 : : {
1820 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1821 : 0 : struct mlx5_hca_attr *hca_attr = &priv->sh->cdev->config.hca_attr;
1822 : :
1823 : : /*
1824 : : * Header modify pattern length limitation is only valid for HWS groups, i.e. groups > 0.
1825 : : * In group 0, MODIFY_FIELD actions are handled with header modify actions
1826 : : * managed by rdma-core.
1827 : : */
1828 [ # # ]: 0 : if (cfg->attr.flow_attr.group != 0 &&
1829 [ # # ]: 0 : mhdr->mhdr_cmds_num > hca_attr->max_header_modify_pattern_length) {
1830 : 0 : uint32_t nops = flow_hw_count_nop_modify_field(mhdr);
1831 : :
1832 : 0 : DRV_LOG(ERR, "Too many modify header commands generated from "
1833 : : "MODIFY_FIELD actions. "
1834 : : "Generated HW commands = %u (amount of NOP commands = %u). "
1835 : : "Maximum supported = %u.",
1836 : : mhdr->mhdr_cmds_num, nops,
1837 : : hca_attr->max_header_modify_pattern_length);
1838 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1839 : : "Number of MODIFY_FIELD actions exceeds maximum "
1840 : : "supported limit of actions");
1841 : : }
1842 : : return 0;
1843 : : }
1844 : :
1845 : : static int
1846 : 0 : flow_hw_represented_port_compile(struct rte_eth_dev *dev,
1847 : : const struct rte_flow_attr *attr,
1848 : : const struct rte_flow_action *action,
1849 : : const struct rte_flow_action *action_mask,
1850 : : struct mlx5_hw_actions *acts,
1851 : : uint16_t action_src, uint16_t action_dst,
1852 : : struct rte_flow_error *error)
1853 : : {
1854 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1855 : 0 : const struct rte_flow_action_ethdev *v = action->conf;
1856 : 0 : const struct rte_flow_action_ethdev *m = action_mask->conf;
1857 : : int ret;
1858 : :
1859 [ # # ]: 0 : if (!attr->group)
1860 : 0 : return rte_flow_error_set(error, EINVAL,
1861 : : RTE_FLOW_ERROR_TYPE_ATTR, NULL,
1862 : : "represented_port action cannot"
1863 : : " be used on group 0");
1864 [ # # ]: 0 : if (!attr->transfer)
1865 : 0 : return rte_flow_error_set(error, EINVAL,
1866 : : RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER,
1867 : : NULL,
1868 : : "represented_port action requires"
1869 : : " transfer attribute");
1870 [ # # ]: 0 : if (attr->ingress || attr->egress)
1871 : 0 : return rte_flow_error_set(error, EINVAL,
1872 : : RTE_FLOW_ERROR_TYPE_ATTR, NULL,
1873 : : "represented_port action cannot"
1874 : : " be used with direction attributes");
1875 [ # # ]: 0 : if (!priv->master)
1876 : 0 : return rte_flow_error_set(error, EINVAL,
1877 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1878 : : "represented_port action must"
1879 : : " be used on proxy port");
1880 [ # # # # ]: 0 : if (m && !!m->port_id) {
1881 : : struct mlx5_priv *port_priv;
1882 : :
1883 [ # # ]: 0 : if (!v)
1884 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
1885 : : action, "port index was not provided");
1886 : 0 : port_priv = mlx5_port_to_eswitch_info(v->port_id, false);
1887 [ # # ]: 0 : if (port_priv == NULL)
1888 : 0 : return rte_flow_error_set
1889 : : (error, EINVAL,
1890 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1891 : : "port does not exist or unable to"
1892 : : " obtain E-Switch info for port");
1893 : : MLX5_ASSERT(priv->hw_vport != NULL);
1894 [ # # ]: 0 : if (priv->hw_vport[v->port_id]) {
1895 : 0 : acts->rule_acts[action_dst].action =
1896 : : priv->hw_vport[v->port_id];
1897 : : } else {
1898 : 0 : return rte_flow_error_set
1899 : : (error, EINVAL,
1900 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1901 : : "cannot use represented_port action"
1902 : : " with this port");
1903 : : }
1904 : : } else {
1905 : : ret = __flow_hw_act_data_general_append
1906 : 0 : (priv, acts, action->type,
1907 : : action_src, action_dst);
1908 : : if (ret)
1909 : 0 : return rte_flow_error_set
1910 : : (error, ENOMEM,
1911 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1912 : : "not enough memory to store"
1913 : : " vport action");
1914 : : }
1915 : : return 0;
1916 : : }
1917 : :
1918 : : static __rte_always_inline int
1919 : : flow_hw_cnt_compile(struct rte_eth_dev *dev, uint32_t start_pos,
1920 : : struct mlx5_hw_actions *acts, bool is_root)
1921 : : {
1922 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1923 : : uint32_t pos = start_pos;
1924 : : cnt_id_t cnt_id;
1925 : : int ret;
1926 : :
1927 : 0 : ret = mlx5_hws_cnt_shared_get(priv->hws_cpool, &cnt_id, 0);
1928 : : if (ret != 0)
1929 : : return ret;
1930 : 0 : ret = mlx5_hws_cnt_pool_get_action_offset
1931 : : (priv->hws_cpool,
1932 : : cnt_id,
1933 : : &acts->rule_acts[pos].action,
1934 : : &acts->rule_acts[pos].counter.offset,
1935 : : is_root);
1936 : : if (ret != 0)
1937 : : return ret;
1938 : 0 : acts->cnt_id = cnt_id;
1939 : : return 0;
1940 : : }
1941 : :
1942 : : static __rte_always_inline bool
1943 : : is_of_vlan_pcp_present(const struct rte_flow_action *actions)
1944 : : {
1945 : : /*
1946 : : * Order of RTE VLAN push actions is
1947 : : * OF_PUSH_VLAN / OF_SET_VLAN_VID [ / OF_SET_VLAN_PCP ]
1948 : : */
1949 : 0 : return actions[MLX5_HW_VLAN_PUSH_PCP_IDX].type ==
1950 : : RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP;
1951 : : }
1952 : :
1953 : : static __rte_always_inline bool
1954 : : is_template_masked_push_vlan(const struct rte_flow_action_of_push_vlan *mask)
1955 : : {
1956 : : /*
1957 : : * In masked push VLAN template all RTE push actions are masked.
1958 : : */
1959 [ # # ]: 0 : return mask && mask->ethertype != 0;
1960 : : }
1961 : :
1962 : 0 : static rte_be32_t vlan_hdr_to_be32(const struct rte_flow_action *actions)
1963 : : {
1964 : : /*
1965 : : * OpenFlow Switch Specification defines 801.1q VID as 12+1 bits.
1966 : : */
1967 : : rte_be32_t type, vid, pcp;
1968 : : #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
1969 : : rte_be32_t vid_lo, vid_hi;
1970 : : #endif
1971 : :
1972 : 0 : type = ((const struct rte_flow_action_of_push_vlan *)
1973 : 0 : actions[MLX5_HW_VLAN_PUSH_TYPE_IDX].conf)->ethertype;
1974 : 0 : vid = ((const struct rte_flow_action_of_set_vlan_vid *)
1975 : 0 : actions[MLX5_HW_VLAN_PUSH_VID_IDX].conf)->vlan_vid;
1976 : : pcp = is_of_vlan_pcp_present(actions) ?
1977 : : ((const struct rte_flow_action_of_set_vlan_pcp *)
1978 [ # # ]: 0 : actions[MLX5_HW_VLAN_PUSH_PCP_IDX].conf)->vlan_pcp : 0;
1979 : : #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
1980 : 0 : vid_hi = vid & 0xff;
1981 : : vid_lo = vid >> 8;
1982 : 0 : return (((vid_lo << 8) | (pcp << 5) | vid_hi) << 16) | type;
1983 : : #else
1984 : : return (type << 16) | (pcp << 13) | vid;
1985 : : #endif
1986 : : }
1987 : :
1988 : : static __rte_always_inline int
1989 : : flow_hw_meter_mark_alloc(struct rte_eth_dev *dev, uint32_t queue,
1990 : : const struct rte_flow_action *action,
1991 : : struct mlx5_hw_q_job *job, bool push,
1992 : : struct mlx5_aso_mtr **aso_mtr,
1993 : : struct rte_flow_error *error)
1994 : : {
1995 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1996 : 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
1997 : 0 : const struct rte_flow_action_meter_mark *meter_mark = action->conf;
1998 : : struct mlx5_flow_meter_info *fm;
1999 : 0 : uint32_t mtr_id = 0;
2000 : : uintptr_t handle = (uintptr_t)MLX5_INDIRECT_ACTION_TYPE_METER_MARK <<
2001 : : MLX5_INDIRECT_ACTION_TYPE_OFFSET;
2002 : :
2003 : 0 : if (priv->shared_host)
2004 : 0 : return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2005 : : "Meter mark actions can only be created on the host port");
2006 : : MLX5_ASSERT(aso_mtr);
2007 [ # # # # : 0 : if (meter_mark->profile == NULL)
# # # # #
# # # #
# ]
2008 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2009 : : "No Meter mark profile");
2010 : :
2011 : 0 : *aso_mtr = mlx5_ipool_malloc(pool->idx_pool, &mtr_id);
2012 [ # # # # : 0 : if (!*aso_mtr) {
# # # # #
# # # #
# ]
2013 [ # # # # : 0 : if (mtr_id)
# # # # #
# # # #
# ]
2014 : 0 : mlx5_ipool_free(pool->idx_pool, mtr_id);
2015 : 0 : return rte_flow_error_set(error, ENOMEM,
2016 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2017 : : NULL,
2018 : : "failed to allocate aso meter entry");
2019 : : }
2020 : : /* Fill the flow meter parameters. */
2021 : 0 : (*aso_mtr)->type = ASO_METER_INDIRECT;
2022 : : fm = &(*aso_mtr)->fm;
2023 : 0 : fm->meter_id = mtr_id;
2024 : 0 : fm->profile = (struct mlx5_flow_meter_profile *)(meter_mark->profile);
2025 : 0 : fm->is_enable = meter_mark->state;
2026 : 0 : fm->color_aware = meter_mark->color_mode;
2027 : 0 : (*aso_mtr)->pool = pool;
2028 [ # # ]: 0 : (*aso_mtr)->state = (queue == MLX5_HW_INV_QUEUE) ?
2029 : : ASO_METER_WAIT : ASO_METER_WAIT_ASYNC;
2030 : 0 : (*aso_mtr)->offset = mtr_id - 1;
2031 [ # # # # : 0 : (*aso_mtr)->init_color = fm->color_aware ? RTE_COLORS : RTE_COLOR_GREEN;
# # # # #
# # # #
# ]
2032 : 0 : job->action = (void *)(handle | mtr_id);
2033 : : /* Update ASO flow meter by wqe. */
2034 [ # # # # : 0 : if (mlx5_aso_meter_update_by_wqe(priv, queue, *aso_mtr,
# # # # #
# # # #
# ]
2035 : : &priv->mtr_bulk, job, push)) {
2036 : 0 : mlx5_ipool_free(pool->idx_pool, mtr_id);
2037 : 0 : return rte_flow_error_set(error, EBUSY,
2038 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2039 : : NULL,
2040 : : "Failed to enqueue ASO meter update");
2041 : : }
2042 : : /* Wait for ASO object completion. */
2043 [ # # # # : 0 : if (queue == MLX5_HW_INV_QUEUE &&
# # # # #
# # # # #
# # ]
2044 : 0 : mlx5_aso_mtr_wait(priv, *aso_mtr, true)) {
2045 : 0 : mlx5_ipool_free(pool->idx_pool, mtr_id);
2046 : : return -EIO;
2047 : : }
2048 : : return 0;
2049 : : }
2050 : :
2051 : : static __rte_always_inline int
2052 : : flow_hw_meter_mark_compile(struct rte_eth_dev *dev,
2053 : : uint16_t aso_mtr_pos,
2054 : : const struct rte_flow_action *action,
2055 : : struct mlx5dr_rule_action *acts,
2056 : : uint32_t *index,
2057 : : uint32_t queue,
2058 : : struct rte_flow_error *error)
2059 : : {
2060 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
2061 : 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
2062 : : struct mlx5_aso_mtr *aso_mtr = NULL;
2063 : : struct mlx5_hw_q_job *job =
2064 : : flow_hw_action_job_init(priv, queue, NULL, NULL, NULL,
2065 : : MLX5_HW_Q_JOB_TYPE_CREATE,
2066 : : MLX5_HW_INDIRECT_TYPE_LEGACY, NULL);
2067 : : int ret;
2068 : :
2069 : : if (!job)
2070 : : return -1;
2071 : : ret = flow_hw_meter_mark_alloc(dev, queue, action, job, true, &aso_mtr, error);
2072 [ # # # # : 0 : if (ret) {
# # # # #
# # # ]
2073 [ # # # # : 0 : if (ret != -EIO) {
# # # # #
# # # ]
2074 : : if (queue == MLX5_HW_INV_QUEUE)
2075 : 0 : queue = CTRL_QUEUE_ID(priv);
2076 : : flow_hw_job_put(priv, job, queue);
2077 : : }
2078 : : return -1;
2079 : : }
2080 : :
2081 : : /* Compile METER_MARK action */
2082 : 0 : acts[aso_mtr_pos].action = pool->action;
2083 : 0 : acts[aso_mtr_pos].aso_meter.offset = aso_mtr->offset;
2084 : 0 : *index = aso_mtr->fm.meter_id;
2085 : : return 0;
2086 : : }
2087 : :
2088 : : static int
2089 : 0 : flow_hw_translate_indirect_mirror(__rte_unused struct rte_eth_dev *dev,
2090 : : __rte_unused const struct mlx5_action_construct_data *act_data,
2091 : : const struct rte_flow_action *action,
2092 : : struct mlx5dr_rule_action *dr_rule)
2093 : : {
2094 : 0 : const struct rte_flow_action_indirect_list *list_conf = action->conf;
2095 : 0 : const struct mlx5_mirror *mirror = (typeof(mirror))list_conf->handle;
2096 : :
2097 : 0 : dr_rule->action = mirror->mirror_action;
2098 : 0 : return 0;
2099 : : }
2100 : :
2101 : : /**
2102 : : * HWS mirror implemented as FW island.
2103 : : * The action does not support indirect list flow configuration.
2104 : : * If template handle was masked, use handle mirror action in flow rules.
2105 : : * Otherwise let flow rule specify mirror handle.
2106 : : */
2107 : : static int
2108 : 0 : hws_table_tmpl_translate_indirect_mirror(struct rte_eth_dev *dev,
2109 : : const struct rte_flow_action *action,
2110 : : const struct rte_flow_action *mask,
2111 : : struct mlx5_hw_actions *acts,
2112 : : uint16_t action_src, uint16_t action_dst)
2113 : : {
2114 : : int ret = 0;
2115 : 0 : const struct rte_flow_action_indirect_list *mask_conf = mask->conf;
2116 : :
2117 [ # # # # ]: 0 : if (mask_conf && mask_conf->handle) {
2118 : : /**
2119 : : * If mirror handle was masked, assign fixed DR5 mirror action.
2120 : : */
2121 : : flow_hw_translate_indirect_mirror(dev, NULL, action,
2122 : 0 : &acts->rule_acts[action_dst]);
2123 : : } else {
2124 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
2125 : : ret = flow_hw_act_data_indirect_list_append
2126 : : (priv, acts, RTE_FLOW_ACTION_TYPE_INDIRECT_LIST,
2127 : : action_src, action_dst,
2128 : : flow_hw_translate_indirect_mirror);
2129 : : }
2130 : :
2131 : 0 : return ret;
2132 : : }
2133 : :
2134 : : static int
2135 : 0 : flow_hw_reformat_action(__rte_unused struct rte_eth_dev *dev,
2136 : : __rte_unused const struct mlx5_action_construct_data *data,
2137 : : const struct rte_flow_action *action,
2138 : : struct mlx5dr_rule_action *dr_rule)
2139 : : {
2140 : 0 : const struct rte_flow_action_indirect_list *indlst_conf = action->conf;
2141 : :
2142 : 0 : dr_rule->action = ((struct mlx5_hw_encap_decap_action *)
2143 : 0 : (indlst_conf->handle))->action;
2144 [ # # ]: 0 : if (!dr_rule->action)
2145 : 0 : return -EINVAL;
2146 : : return 0;
2147 : : }
2148 : :
2149 : : /**
2150 : : * Template conf must not be masked. If handle is masked, use the one in template,
2151 : : * otherwise update per flow rule.
2152 : : */
2153 : : static int
2154 : 0 : hws_table_tmpl_translate_indirect_reformat(struct rte_eth_dev *dev,
2155 : : const struct rte_flow_action *action,
2156 : : const struct rte_flow_action *mask,
2157 : : struct mlx5_hw_actions *acts,
2158 : : uint16_t action_src, uint16_t action_dst)
2159 : : {
2160 : : int ret = -1;
2161 : 0 : const struct rte_flow_action_indirect_list *mask_conf = mask->conf;
2162 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
2163 : :
2164 [ # # # # : 0 : if (mask_conf && mask_conf->handle && !mask_conf->conf)
# # ]
2165 : : /**
2166 : : * If handle was masked, assign fixed DR action.
2167 : : */
2168 : : ret = flow_hw_reformat_action(dev, NULL, action,
2169 [ # # ]: 0 : &acts->rule_acts[action_dst]);
2170 [ # # # # : 0 : else if (mask_conf && !mask_conf->handle && !mask_conf->conf)
# # ]
2171 : : ret = flow_hw_act_data_indirect_list_append
2172 : : (priv, acts, RTE_FLOW_ACTION_TYPE_INDIRECT_LIST,
2173 : : action_src, action_dst, flow_hw_reformat_action);
2174 : 0 : return ret;
2175 : : }
2176 : :
2177 : : static int
2178 : 0 : flow_dr_set_meter(struct mlx5_priv *priv,
2179 : : struct mlx5dr_rule_action *dr_rule,
2180 : : const struct rte_flow_action_indirect_list *action_conf)
2181 : : {
2182 : 0 : const struct mlx5_indlst_legacy *legacy_obj =
2183 : : (typeof(legacy_obj))action_conf->handle;
2184 : 0 : struct mlx5_aso_mtr_pool *mtr_pool = priv->hws_mpool;
2185 : 0 : uint32_t act_idx = (uint32_t)(uintptr_t)legacy_obj->handle;
2186 : 0 : uint32_t mtr_id = act_idx & (RTE_BIT32(MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
2187 : 0 : struct mlx5_aso_mtr *aso_mtr = mlx5_ipool_get(mtr_pool->idx_pool, mtr_id);
2188 : :
2189 [ # # ]: 0 : if (!aso_mtr)
2190 : : return -EINVAL;
2191 : 0 : dr_rule->action = mtr_pool->action;
2192 : 0 : dr_rule->aso_meter.offset = aso_mtr->offset;
2193 : 0 : return 0;
2194 : : }
2195 : :
2196 : : __rte_always_inline static void
2197 : : flow_dr_mtr_flow_color(struct mlx5dr_rule_action *dr_rule, enum rte_color init_color)
2198 : : {
2199 : 0 : dr_rule->aso_meter.init_color =
2200 : 0 : (enum mlx5dr_action_aso_meter_color)rte_col_2_mlx5_col(init_color);
2201 : 0 : }
2202 : :
2203 : : static int
2204 : 0 : flow_hw_translate_indirect_meter(struct rte_eth_dev *dev,
2205 : : const struct mlx5_action_construct_data *act_data,
2206 : : const struct rte_flow_action *action,
2207 : : struct mlx5dr_rule_action *dr_rule)
2208 : : {
2209 : : int ret;
2210 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
2211 : 0 : const struct rte_flow_action_indirect_list *action_conf = action->conf;
2212 : 0 : const struct rte_flow_indirect_update_flow_meter_mark **flow_conf =
2213 : : (typeof(flow_conf))action_conf->conf;
2214 : :
2215 : 0 : ret = flow_dr_set_meter(priv, dr_rule, action_conf);
2216 [ # # ]: 0 : if (ret)
2217 : : return ret;
2218 [ # # ]: 0 : if (!act_data->shared_meter.conf_masked) {
2219 [ # # # # : 0 : if (flow_conf && flow_conf[0] && flow_conf[0]->init_color < RTE_COLORS)
# # ]
2220 : : flow_dr_mtr_flow_color(dr_rule, flow_conf[0]->init_color);
2221 : : }
2222 : : return 0;
2223 : : }
2224 : :
2225 : : static int
2226 : 0 : hws_table_tmpl_translate_indirect_meter(struct rte_eth_dev *dev,
2227 : : const struct rte_flow_action *action,
2228 : : const struct rte_flow_action *mask,
2229 : : struct mlx5_hw_actions *acts,
2230 : : uint16_t action_src, uint16_t action_dst)
2231 : : {
2232 : : int ret;
2233 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
2234 : 0 : const struct rte_flow_action_indirect_list *action_conf = action->conf;
2235 : 0 : const struct rte_flow_action_indirect_list *mask_conf = mask->conf;
2236 [ # # # # ]: 0 : bool is_handle_masked = mask_conf && mask_conf->handle;
2237 [ # # # # : 0 : bool is_conf_masked = mask_conf && mask_conf->conf && mask_conf->conf[0];
# # ]
2238 : 0 : struct mlx5dr_rule_action *dr_rule = &acts->rule_acts[action_dst];
2239 : :
2240 [ # # ]: 0 : if (is_handle_masked) {
2241 : 0 : ret = flow_dr_set_meter(priv, dr_rule, action->conf);
2242 [ # # ]: 0 : if (ret)
2243 : : return ret;
2244 : : }
2245 [ # # ]: 0 : if (is_conf_masked) {
2246 : : const struct
2247 : 0 : rte_flow_indirect_update_flow_meter_mark **flow_conf =
2248 : : (typeof(flow_conf))action_conf->conf;
2249 : : flow_dr_mtr_flow_color(dr_rule,
2250 [ # # ]: 0 : flow_conf[0]->init_color);
2251 : : }
2252 [ # # ]: 0 : if (!is_handle_masked || !is_conf_masked) {
2253 : : struct mlx5_action_construct_data *act_data;
2254 : :
2255 : : ret = flow_hw_act_data_indirect_list_append
2256 : : (priv, acts, RTE_FLOW_ACTION_TYPE_INDIRECT_LIST,
2257 : : action_src, action_dst, flow_hw_translate_indirect_meter);
2258 : : if (ret)
2259 : 0 : return ret;
2260 : : act_data = LIST_FIRST(&acts->act_list);
2261 : 0 : act_data->shared_meter.conf_masked = is_conf_masked;
2262 : : }
2263 : : return 0;
2264 : : }
2265 : :
2266 : : static int
2267 : : hws_table_tmpl_translate_indirect_legacy(struct rte_eth_dev *dev,
2268 : : const struct rte_flow_action *action,
2269 : : const struct rte_flow_action *mask,
2270 : : struct mlx5_hw_actions *acts,
2271 : : uint16_t action_src, uint16_t action_dst)
2272 : : {
2273 : : int ret;
2274 : : const struct rte_flow_action_indirect_list *indlst_conf = action->conf;
2275 : : struct mlx5_indlst_legacy *indlst_obj = (typeof(indlst_obj))indlst_conf->handle;
2276 : 0 : uint32_t act_idx = (uint32_t)(uintptr_t)indlst_obj->handle;
2277 : 0 : uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
2278 : :
2279 : 0 : switch (type) {
2280 : 0 : case MLX5_INDIRECT_ACTION_TYPE_METER_MARK:
2281 : 0 : ret = hws_table_tmpl_translate_indirect_meter(dev, action, mask,
2282 : : acts, action_src,
2283 : : action_dst);
2284 : 0 : break;
2285 : : default:
2286 : : ret = -EINVAL;
2287 : : break;
2288 : : }
2289 : : return ret;
2290 : : }
2291 : :
2292 : : /*
2293 : : * template .. indirect_list handle Ht conf Ct ..
2294 : : * mask .. indirect_list handle Hm conf Cm ..
2295 : : *
2296 : : * PMD requires Ht != 0 to resolve handle type.
2297 : : * If Ht was masked (Hm != 0) DR5 action will be set according to Ht and will
2298 : : * not change. Otherwise, DR5 action will be resolved during flow rule build.
2299 : : * If Ct was masked (Cm != 0), table template processing updates base
2300 : : * indirect action configuration with Ct parameters.
2301 : : */
2302 : : static int
2303 : 0 : table_template_translate_indirect_list(struct rte_eth_dev *dev,
2304 : : const struct rte_flow_action *action,
2305 : : const struct rte_flow_action *mask,
2306 : : struct mlx5_hw_actions *acts,
2307 : : uint16_t action_src, uint16_t action_dst)
2308 : : {
2309 : : int ret = 0;
2310 : : enum mlx5_indirect_list_type type;
2311 : 0 : const struct rte_flow_action_indirect_list *list_conf = action->conf;
2312 : :
2313 [ # # # # ]: 0 : if (!list_conf || !list_conf->handle)
2314 : : return -EINVAL;
2315 : : type = mlx5_get_indirect_list_type(list_conf->handle);
2316 [ # # # # ]: 0 : switch (type) {
2317 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY:
2318 [ # # ]: 0 : ret = hws_table_tmpl_translate_indirect_legacy(dev, action, mask,
2319 : : acts, action_src,
2320 : : action_dst);
2321 : : break;
2322 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR:
2323 : 0 : ret = hws_table_tmpl_translate_indirect_mirror(dev, action, mask,
2324 : : acts, action_src,
2325 : : action_dst);
2326 : 0 : break;
2327 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT:
2328 [ # # ]: 0 : if (list_conf->conf)
2329 : : return -EINVAL;
2330 : 0 : ret = hws_table_tmpl_translate_indirect_reformat(dev, action, mask,
2331 : : acts, action_src,
2332 : : action_dst);
2333 : 0 : break;
2334 : : default:
2335 : : return -EINVAL;
2336 : : }
2337 : : return ret;
2338 : : }
2339 : :
2340 : : /**
2341 : : * Translate given encap action and mask to raw tunnel header buffer.
2342 : : *
2343 : : * @param[in] action
2344 : : * Pointer to encap action.
2345 : : * @param[in] mask
2346 : : * Pointer to encap action's mask.
2347 : : * @param[out] conf_encap_data
2348 : : * Buffer where tunnel header will be written.
2349 : : * @param[out] data_size
2350 : : * Pointer to tunnel header size.
2351 : : * @param[out] error
2352 : : * Pointer to error structure.
2353 : : *
2354 : : * @return
2355 : : * 0 or greater if translation was successful.
2356 : : * Negative errno value otherwise.
2357 : : *
2358 : : * If returned value is 0, then action is not shared in the actions template
2359 : : * If bigger than 0, then it is shared.
2360 : : */
2361 : : static int
2362 : 0 : translate_l2_encap_action(const struct rte_flow_action *action,
2363 : : const struct rte_flow_action *mask,
2364 : : uint8_t conf_encap_data[MLX5_ENCAP_MAX_LEN],
2365 : : size_t *data_size,
2366 : : struct rte_flow_error *error)
2367 : : {
2368 : : struct rte_flow_item *conf_item;
2369 : : int ret;
2370 : :
2371 [ # # ]: 0 : if (action->conf == NULL)
2372 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL,
2373 : : "Missing VXLAN/NVGRE encap action configuration");
2374 : :
2375 : : /* Only these 2 action types receive encap data as flow item pattern. */
2376 : : MLX5_ASSERT(action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ||
2377 : : action->type == RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP);
2378 [ # # ]: 0 : if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
2379 : 0 : conf_item = MLX5_CONST_ENCAP_ITEM(rte_flow_action_vxlan_encap, action->conf);
2380 : : else
2381 : 0 : conf_item = MLX5_CONST_ENCAP_ITEM(rte_flow_action_nvgre_encap, action->conf);
2382 [ # # ]: 0 : if (conf_item == NULL)
2383 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL,
2384 : : "Missing VXLAN/NVGRE tunnel definition in action config");
2385 : :
2386 : 0 : ret = mlx5_flow_dv_convert_encap_data(conf_item, conf_encap_data, data_size, error);
2387 [ # # ]: 0 : if (ret < 0)
2388 : : return ret;
2389 : :
2390 : : /* If mask is provided, then action is shared */
2391 : 0 : return mask->conf != NULL;
2392 : : }
2393 : :
2394 : : static void
2395 : : mlx5_set_reformat_header(struct mlx5dr_action_reformat_header *hdr,
2396 : : uint8_t *encap_data,
2397 : : size_t data_size)
2398 : : {
2399 : 0 : hdr->sz = data_size;
2400 : 0 : hdr->data = encap_data;
2401 : : }
2402 : :
2403 : : static int
2404 [ # # ]: 0 : mlx5_tbl_translate_reformat(struct mlx5_priv *priv,
2405 : : struct mlx5_hw_actions *acts,
2406 : : struct rte_flow_actions_template *at,
2407 : : uint8_t *encap_data, uint8_t *encap_data_m,
2408 : : struct mlx5_tbl_multi_pattern_ctx *mp_ctx,
2409 : : size_t data_size, uint16_t reformat_src,
2410 : : enum mlx5dr_action_type refmt_type,
2411 : : struct rte_flow_error *error)
2412 : : {
2413 : : int mp_reformat_ix = mlx5_multi_pattern_reformat_to_index(refmt_type);
2414 : : struct mlx5dr_action_reformat_header hdr;
2415 : : bool shared_rfmt = false;
2416 : : int ret;
2417 : :
2418 : : MLX5_ASSERT(at->reformat_off != UINT16_MAX);
2419 [ # # ]: 0 : if (encap_data && encap_data_m)
2420 : : shared_rfmt = true;
2421 : 0 : acts->encap_decap = mlx5_malloc(MLX5_MEM_ZERO,
2422 : : sizeof(*acts->encap_decap) + data_size,
2423 : : 0, SOCKET_ID_ANY);
2424 [ # # ]: 0 : if (!acts->encap_decap)
2425 : 0 : return rte_flow_error_set(error, ENOMEM,
2426 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2427 : : NULL, "no memory for reformat context");
2428 : 0 : acts->encap_decap_pos = at->reformat_off;
2429 : 0 : acts->encap_decap->data_size = data_size;
2430 : 0 : acts->encap_decap->action_type = refmt_type;
2431 [ # # ]: 0 : if (shared_rfmt || mp_reformat_ix < 0) {
2432 : : uint16_t reformat_ix = at->reformat_off;
2433 : : /*
2434 : : * This copy is only needed in non template mode.
2435 : : * In order to create the action later.
2436 : : */
2437 : 0 : memcpy(acts->encap_decap->data, encap_data, data_size);
2438 : 0 : acts->rule_acts[reformat_ix].reformat.data = acts->encap_decap->data;
2439 : 0 : acts->rule_acts[reformat_ix].reformat.offset = 0;
2440 : 0 : acts->encap_decap->shared = true;
2441 : : } else {
2442 : : uint32_t ix;
2443 : 0 : typeof(mp_ctx->reformat[0]) *reformat = mp_ctx->reformat +
2444 : : mp_reformat_ix;
2445 : : mlx5_set_reformat_header(&hdr, encap_data, data_size);
2446 : 0 : ix = reformat->elements_num++;
2447 : 0 : reformat->reformat_hdr[ix] = hdr;
2448 : 0 : acts->rule_acts[at->reformat_off].reformat.hdr_idx = ix;
2449 : 0 : acts->encap_decap->multi_pattern = 1;
2450 : 0 : ret = __flow_hw_act_data_encap_append
2451 : 0 : (priv, acts, (at->actions + reformat_src)->type,
2452 : : reformat_src, at->reformat_off, data_size);
2453 : : if (ret)
2454 : 0 : return -rte_errno;
2455 : : mlx5_multi_pattern_activate(mp_ctx);
2456 : : }
2457 : : return 0;
2458 : : }
2459 : :
2460 : : static int
2461 : 0 : mlx5_tbl_create_reformat_action(struct mlx5_priv *priv,
2462 : : const struct rte_flow_template_table_attr *table_attr,
2463 : : struct mlx5_hw_actions *acts,
2464 : : struct rte_flow_actions_template *at,
2465 : : uint8_t *encap_data,
2466 : : size_t data_size,
2467 : : enum mlx5dr_action_type refmt_type)
2468 : : {
2469 : 0 : const struct rte_flow_attr *attr = &table_attr->flow_attr;
2470 : : bool unified_fdb = is_unified_fdb(priv);
2471 : 0 : enum mlx5dr_table_type tbl_type = get_mlx5dr_table_type(attr, table_attr->specialize,
2472 : : unified_fdb);
2473 : : struct mlx5dr_action_reformat_header hdr;
2474 : :
2475 : : mlx5_set_reformat_header(&hdr, encap_data, data_size);
2476 : 0 : uint16_t reformat_ix = at->reformat_off;
2477 : 0 : uint32_t flags = mlx5_hw_act_flag[!!attr->group][tbl_type] |
2478 : : MLX5DR_ACTION_FLAG_SHARED;
2479 : :
2480 : 0 : acts->encap_decap->action = mlx5dr_action_create_reformat(priv->dr_ctx, refmt_type,
2481 : : 1, &hdr, 0, flags);
2482 [ # # ]: 0 : if (!acts->encap_decap->action)
2483 : 0 : return -rte_errno;
2484 : 0 : acts->rule_acts[reformat_ix].action = acts->encap_decap->action;
2485 : 0 : return 0;
2486 : : }
2487 : :
2488 : : static int
2489 : 0 : mlx5_tbl_translate_modify_header(struct rte_eth_dev *dev,
2490 : : const struct mlx5_flow_template_table_cfg *cfg,
2491 : : struct mlx5_hw_actions *acts,
2492 : : struct mlx5_tbl_multi_pattern_ctx *mp_ctx,
2493 : : struct mlx5_hw_modify_header_action *mhdr,
2494 : : struct rte_flow_error *error)
2495 : : {
2496 : 0 : uint16_t mhdr_ix = mhdr->pos;
2497 : : struct mlx5dr_action_mh_pattern pattern = {
2498 : 0 : .sz = sizeof(struct mlx5_modification_cmd) * mhdr->mhdr_cmds_num
2499 : : };
2500 : :
2501 : 0 : int ret = flow_hw_validate_compiled_modify_field(dev, cfg, mhdr, error);
2502 [ # # ]: 0 : if (ret) {
2503 : : __flow_hw_action_template_destroy(dev, acts);
2504 : 0 : return ret;
2505 : : }
2506 : 0 : acts->mhdr = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*acts->mhdr),
2507 : : 0, SOCKET_ID_ANY);
2508 [ # # ]: 0 : if (!acts->mhdr)
2509 : 0 : return rte_flow_error_set(error, ENOMEM,
2510 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2511 : : NULL, "translate modify_header: no memory for modify header context");
2512 : : rte_memcpy(acts->mhdr, mhdr, sizeof(*mhdr));
2513 [ # # ]: 0 : if (!mhdr->shared) {
2514 : 0 : pattern.data = (rte_be64_t *)acts->mhdr->mhdr_cmds;
2515 : : typeof(mp_ctx->mh) *mh = &mp_ctx->mh;
2516 : 0 : uint32_t idx = mh->elements_num;
2517 : 0 : mh->pattern[mh->elements_num++] = pattern;
2518 : 0 : acts->mhdr->multi_pattern = 1;
2519 : 0 : acts->rule_acts[mhdr_ix].modify_header.pattern_idx = idx;
2520 : : mlx5_multi_pattern_activate(mp_ctx);
2521 : : }
2522 : : return 0;
2523 : : }
2524 : :
2525 : : static int
2526 : 0 : mlx5_tbl_ensure_shared_modify_header(struct rte_eth_dev *dev,
2527 : : const struct mlx5_flow_template_table_cfg *cfg,
2528 : : struct mlx5_hw_actions *acts,
2529 : : struct rte_flow_error *error)
2530 : : {
2531 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
2532 : : bool unified_fdb = is_unified_fdb(priv);
2533 : : const struct rte_flow_template_table_attr *table_attr = &cfg->attr;
2534 : 0 : const struct rte_flow_attr *attr = &table_attr->flow_attr;
2535 : 0 : enum mlx5dr_table_type tbl_type = get_mlx5dr_table_type(attr, table_attr->specialize,
2536 : : unified_fdb);
2537 : : struct mlx5dr_action_mh_pattern pattern;
2538 : :
2539 [ # # ]: 0 : if (!acts->mhdr)
2540 : 0 : return rte_flow_error_set(error, EINVAL,
2541 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2542 : : "translate modify_header: mhdr is NULL");
2543 : :
2544 : 0 : pattern.sz = sizeof(struct mlx5_modification_cmd) * acts->mhdr->mhdr_cmds_num;
2545 : 0 : uint16_t mhdr_ix = acts->mhdr->pos;
2546 : 0 : uint32_t flags = mlx5_hw_act_flag[!!attr->group][tbl_type] | MLX5DR_ACTION_FLAG_SHARED;
2547 : :
2548 : 0 : pattern.data = (rte_be64_t *)acts->mhdr->mhdr_cmds;
2549 : 0 : acts->mhdr->action = mlx5dr_action_create_modify_header(priv->dr_ctx, 1,
2550 : : &pattern, 0, flags);
2551 [ # # ]: 0 : if (!acts->mhdr->action)
2552 : 0 : return rte_flow_error_set(error, rte_errno,
2553 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2554 : : "translate modify_header: failed to create DR action");
2555 : 0 : acts->rule_acts[mhdr_ix].action = acts->mhdr->action;
2556 : 0 : return 0;
2557 : : }
2558 : :
2559 : : static int
2560 : 0 : mlx5_create_ipv6_ext_reformat(struct rte_eth_dev *dev,
2561 : : const struct mlx5_flow_template_table_cfg *cfg,
2562 : : struct mlx5_hw_actions *acts,
2563 : : struct rte_flow_actions_template *at,
2564 : : uint8_t *push_data, uint8_t *push_data_m,
2565 : : size_t push_size, uint16_t recom_src,
2566 : : enum mlx5dr_action_type recom_type)
2567 : : {
2568 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
2569 : : bool unified_fdb = is_unified_fdb(priv);
2570 : : const struct rte_flow_template_table_attr *table_attr = &cfg->attr;
2571 : 0 : const struct rte_flow_attr *attr = &table_attr->flow_attr;
2572 : : enum mlx5dr_table_type type =
2573 : 0 : get_mlx5dr_table_type(attr, table_attr->specialize, unified_fdb);
2574 : : struct mlx5_action_construct_data *act_data;
2575 : 0 : struct mlx5dr_action_reformat_header hdr = {0};
2576 : : uint32_t flag, bulk = 0;
2577 : :
2578 : 0 : flag = mlx5_hw_act_flag[!!attr->group][type];
2579 : 0 : acts->push_remove = mlx5_malloc(MLX5_MEM_ZERO,
2580 : : sizeof(*acts->push_remove) + push_size,
2581 : : 0, SOCKET_ID_ANY);
2582 [ # # ]: 0 : if (!acts->push_remove)
2583 : : return -ENOMEM;
2584 : :
2585 [ # # # ]: 0 : switch (recom_type) {
2586 : 0 : case MLX5DR_ACTION_TYP_PUSH_IPV6_ROUTE_EXT:
2587 [ # # ]: 0 : if (!push_data || !push_size)
2588 : 0 : goto err1;
2589 [ # # ]: 0 : if (!push_data_m) {
2590 [ # # ]: 0 : bulk = rte_log2_u32(table_attr->nb_flows);
2591 : : } else {
2592 : 0 : flag |= MLX5DR_ACTION_FLAG_SHARED;
2593 : 0 : acts->push_remove->shared = 1;
2594 : : }
2595 : 0 : acts->push_remove->data_size = push_size;
2596 : 0 : memcpy(acts->push_remove->data, push_data, push_size);
2597 : 0 : hdr.data = push_data;
2598 : 0 : hdr.sz = push_size;
2599 : 0 : break;
2600 : 0 : case MLX5DR_ACTION_TYP_POP_IPV6_ROUTE_EXT:
2601 : 0 : flag |= MLX5DR_ACTION_FLAG_SHARED;
2602 : 0 : acts->push_remove->shared = 1;
2603 : 0 : break;
2604 : : default:
2605 : : break;
2606 : : }
2607 : :
2608 : 0 : acts->push_remove->action =
2609 : 0 : mlx5dr_action_create_reformat_ipv6_ext(priv->dr_ctx,
2610 : : recom_type, &hdr, bulk, flag);
2611 [ # # ]: 0 : if (!acts->push_remove->action)
2612 : 0 : goto err1;
2613 : 0 : acts->rule_acts[at->recom_off].action = acts->push_remove->action;
2614 : 0 : acts->rule_acts[at->recom_off].ipv6_ext.header = acts->push_remove->data;
2615 : 0 : acts->rule_acts[at->recom_off].ipv6_ext.offset = 0;
2616 : 0 : acts->push_remove_pos = at->recom_off;
2617 [ # # ]: 0 : if (!acts->push_remove->shared) {
2618 : 0 : act_data = __flow_hw_act_data_push_append(dev, acts,
2619 : : RTE_FLOW_ACTION_TYPE_IPV6_EXT_PUSH,
2620 : : recom_src, at->recom_off, push_size);
2621 : : if (!act_data)
2622 : 0 : goto err;
2623 : : }
2624 : : return 0;
2625 : : err:
2626 [ # # ]: 0 : if (acts->push_remove->action)
2627 : 0 : mlx5dr_action_destroy(acts->push_remove->action);
2628 : 0 : err1:
2629 [ # # ]: 0 : if (acts->push_remove) {
2630 : 0 : mlx5_free(acts->push_remove);
2631 : 0 : acts->push_remove = NULL;
2632 : : }
2633 : : return -EINVAL;
2634 : : }
2635 : :
2636 : : static bool
2637 : : is_indirect_action_type_supported_root(const enum rte_flow_action_type type)
2638 : : {
2639 : : switch (type) {
2640 : : case RTE_FLOW_ACTION_TYPE_COUNT:
2641 : : case RTE_FLOW_ACTION_TYPE_AGE:
2642 : : return mlx5dr_action_counter_root_is_supported();
2643 : : default:
2644 : : return false;
2645 : : }
2646 : : }
2647 : :
2648 : : /**
2649 : : * Translate rte_flow actions to DR action.
2650 : : *
2651 : : * As the action template has already indicated the actions. Translate
2652 : : * the rte_flow actions to DR action if possbile. So in flow create
2653 : : * stage we will save cycles from handing the actions' organizing.
2654 : : * For the actions with limited information, need to add these to a
2655 : : * list.
2656 : : *
2657 : : * @param[in] dev
2658 : : * Pointer to the rte_eth_dev structure.
2659 : : * @param[in] cfg
2660 : : * Pointer to the table configuration.
2661 : : * @param[in/out] acts
2662 : : * Pointer to the template HW steering DR actions.
2663 : : * @param[in] at
2664 : : * Action template.
2665 : : * @param[in] nt_mode
2666 : : * Non template rule translate.
2667 : : * @param[out] error
2668 : : * Pointer to error structure.
2669 : : *
2670 : : * @return
2671 : : * 0 on success, a negative errno otherwise and rte_errno is set.
2672 : : */
2673 : : static int
2674 : 0 : __flow_hw_translate_actions_template(struct rte_eth_dev *dev,
2675 : : const struct mlx5_flow_template_table_cfg *cfg,
2676 : : struct mlx5_hw_actions *acts,
2677 : : struct rte_flow_actions_template *at,
2678 : : struct mlx5_tbl_multi_pattern_ctx *mp_ctx,
2679 : : bool nt_mode,
2680 : : struct rte_flow_error *error)
2681 : : {
2682 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
2683 : 0 : struct mlx5_hca_attr *hca_attr = &priv->sh->cdev->config.hca_attr;
2684 : 0 : const struct rte_flow_template_table_attr *table_attr = &cfg->attr;
2685 : 0 : const struct rte_flow_attr *attr = &table_attr->flow_attr;
2686 : 0 : struct rte_flow_action *actions = at->actions;
2687 : 0 : struct rte_flow_action *masks = at->masks;
2688 : : enum mlx5dr_action_type refmt_type = MLX5DR_ACTION_TYP_LAST;
2689 : : enum mlx5dr_action_type recom_type = MLX5DR_ACTION_TYP_LAST;
2690 : : const struct rte_flow_action_raw_encap *raw_encap_data;
2691 : : const struct rte_flow_action_ipv6_ext_push *ipv6_ext_data;
2692 : : uint16_t reformat_src = 0, recom_src = 0;
2693 : 0 : uint8_t converted_encap_data[MLX5_ENCAP_MAX_LEN] = { 0 };
2694 : : uint8_t *encap_data = NULL, *encap_data_m = NULL;
2695 : : uint8_t *push_data = NULL, *push_data_m = NULL;
2696 : 0 : size_t data_size = 0, push_size = 0;
2697 : : struct mlx5_hw_modify_header_action mhdr = { 0 };
2698 : 0 : struct rte_flow_error sub_error = {
2699 : : .type = RTE_FLOW_ERROR_TYPE_NONE,
2700 : : .cause = NULL,
2701 : : .message = NULL,
2702 : : };
2703 : : bool actions_end = false;
2704 : : uint32_t type;
2705 : : bool reformat_used = false;
2706 : : bool recom_used = false;
2707 : : unsigned int of_vlan_offset;
2708 : : uint32_t ct_idx;
2709 : : int ret, err;
2710 : 0 : bool is_root = mlx5_group_id_is_root(cfg->attr.flow_attr.group);
2711 : : bool unified_fdb = is_unified_fdb(priv);
2712 : : struct mlx5dr_action *dr_action = NULL;
2713 : :
2714 : : flow_hw_modify_field_init(&mhdr, at);
2715 : 0 : type = get_mlx5dr_table_type(attr, cfg->attr.specialize, unified_fdb);
2716 [ # # ]: 0 : for (; !actions_end; actions++, masks++) {
2717 : 0 : uint64_t pos = actions - at->actions;
2718 : 0 : uint16_t src_pos = pos - at->src_off[pos];
2719 : 0 : uint16_t dr_pos = at->dr_off[pos];
2720 : :
2721 [ # # # # : 0 : switch ((int)actions->type) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
2722 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT_LIST:
2723 [ # # ]: 0 : if (is_root) {
2724 : 0 : DRV_LOG(ERR, "Indirect action is not supported in root table.");
2725 : 0 : goto err;
2726 : : }
2727 : 0 : ret = table_template_translate_indirect_list
2728 : : (dev, actions, masks, acts, src_pos, dr_pos);
2729 [ # # ]: 0 : if (ret)
2730 : 0 : goto err;
2731 : : break;
2732 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT:
2733 [ # # ]: 0 : if (is_root && !is_indirect_action_type_supported_root(masks->type)) {
2734 : 0 : DRV_LOG(ERR, "Indirect action type (%d) is not supported on root.",
2735 : : masks->type);
2736 : 0 : goto err;
2737 : : }
2738 [ # # # # ]: 0 : if (actions->conf && masks->conf) {
2739 [ # # # # : 0 : if (flow_hw_shared_action_translate(dev, actions, acts,
# # # # ]
2740 : : src_pos, dr_pos, &sub_error))
2741 : 0 : goto err;
2742 : 0 : } else if (__flow_hw_act_data_indirect_append
2743 : : (priv, acts, RTE_FLOW_ACTION_TYPE_INDIRECT,
2744 : : masks->type, src_pos, dr_pos)){
2745 : 0 : goto err;
2746 : : }
2747 : : break;
2748 : : case RTE_FLOW_ACTION_TYPE_VOID:
2749 : : break;
2750 : 0 : case RTE_FLOW_ACTION_TYPE_DROP:
2751 : 0 : dr_action = mlx5_hws_global_action_drop_get(priv, type, is_root);
2752 [ # # ]: 0 : if (dr_action == NULL) {
2753 : 0 : DRV_LOG(ERR, "port %u failed to allocate drop action",
2754 : : priv->dev_data->port_id);
2755 : 0 : rte_flow_error_set(&sub_error, ENOMEM,
2756 : : RTE_FLOW_ERROR_TYPE_STATE, NULL,
2757 : : "failed to allocate drop action");
2758 : 0 : goto err;
2759 : : }
2760 : 0 : acts->rule_acts[dr_pos].action = dr_action;
2761 : 0 : break;
2762 : 0 : case RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:
2763 [ # # ]: 0 : if (is_root) {
2764 : 0 : DRV_LOG(ERR, "Port representor is not supported in root table.");
2765 : 0 : goto err;
2766 : : }
2767 : 0 : dr_action = mlx5_hws_global_action_def_miss_get(priv, type, is_root);
2768 [ # # ]: 0 : if (dr_action == NULL) {
2769 : 0 : DRV_LOG(ERR, "port %u failed to allocate port representor action",
2770 : : priv->dev_data->port_id);
2771 : 0 : rte_flow_error_set(&sub_error, ENOMEM,
2772 : : RTE_FLOW_ERROR_TYPE_STATE, NULL,
2773 : : "failed to allocate port representor action");
2774 : 0 : goto err;
2775 : : }
2776 : 0 : acts->rule_acts[dr_pos].action = dr_action;
2777 : 0 : break;
2778 : 0 : case RTE_FLOW_ACTION_TYPE_FLAG:
2779 : 0 : dr_action = mlx5_hws_global_action_tag_get(priv, type, is_root);
2780 [ # # ]: 0 : if (dr_action == NULL) {
2781 : 0 : DRV_LOG(ERR, "port %u failed to allocate flag action",
2782 : : priv->dev_data->port_id);
2783 : 0 : rte_flow_error_set(&sub_error, ENOMEM,
2784 : : RTE_FLOW_ERROR_TYPE_STATE, NULL,
2785 : : "failed to allocate flag action");
2786 : 0 : goto err;
2787 : : }
2788 : 0 : acts->mark = true;
2789 : 0 : acts->rule_acts[dr_pos].tag.value =
2790 : : mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
2791 : 0 : acts->rule_acts[dr_pos].action = dr_action;
2792 : 0 : rte_atomic_fetch_add_explicit(&priv->hws_mark_refcnt, 1,
2793 : : rte_memory_order_relaxed);
2794 : 0 : mlx5_flow_hw_rxq_flag_set(dev, true);
2795 : 0 : break;
2796 : 0 : case RTE_FLOW_ACTION_TYPE_MARK:
2797 : 0 : dr_action = mlx5_hws_global_action_tag_get(priv, type, is_root);
2798 [ # # ]: 0 : if (dr_action == NULL) {
2799 : 0 : DRV_LOG(ERR, "port %u failed to allocate mark action",
2800 : : priv->dev_data->port_id);
2801 : 0 : rte_flow_error_set(&sub_error, ENOMEM,
2802 : : RTE_FLOW_ERROR_TYPE_STATE, NULL,
2803 : : "failed to allocate mark action");
2804 : 0 : goto err;
2805 : : }
2806 : 0 : acts->mark = true;
2807 [ # # ]: 0 : if (masks->conf &&
2808 : : ((const struct rte_flow_action_mark *)
2809 [ # # ]: 0 : masks->conf)->id)
2810 : 0 : acts->rule_acts[dr_pos].tag.value =
2811 : 0 : mlx5_flow_mark_set
2812 : : (((const struct rte_flow_action_mark *)
2813 : 0 : (actions->conf))->id);
2814 : 0 : else if (__flow_hw_act_data_general_append(priv, acts,
2815 : : actions->type,
2816 : : src_pos, dr_pos))
2817 : 0 : goto err;
2818 : 0 : acts->rule_acts[dr_pos].action = dr_action;
2819 : 0 : rte_atomic_fetch_add_explicit(&priv->hws_mark_refcnt, 1,
2820 : : rte_memory_order_relaxed);
2821 : 0 : mlx5_flow_hw_rxq_flag_set(dev, true);
2822 : 0 : break;
2823 : 0 : case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
2824 : 0 : dr_action = mlx5_hws_global_action_push_vlan_get(priv, type, is_root);
2825 [ # # ]: 0 : if (dr_action == NULL) {
2826 : 0 : DRV_LOG(ERR, "port %u failed to allocate push VLAN action",
2827 : : priv->dev_data->port_id);
2828 : 0 : rte_flow_error_set(&sub_error, ENOMEM,
2829 : : RTE_FLOW_ERROR_TYPE_STATE, NULL,
2830 : : "failed to allocate push VLAN action");
2831 : 0 : goto err;
2832 : : }
2833 : 0 : acts->rule_acts[dr_pos].action = dr_action;
2834 [ # # # # ]: 0 : if (is_template_masked_push_vlan(masks->conf))
2835 : 0 : acts->rule_acts[dr_pos].push_vlan.vlan_hdr =
2836 : 0 : vlan_hdr_to_be32(actions);
2837 : 0 : else if (__flow_hw_act_data_general_append
2838 : : (priv, acts, actions->type,
2839 : : src_pos, dr_pos))
2840 : 0 : goto err;
2841 : : of_vlan_offset = is_of_vlan_pcp_present(actions) ?
2842 [ # # ]: 0 : MLX5_HW_VLAN_PUSH_PCP_IDX :
2843 : : MLX5_HW_VLAN_PUSH_VID_IDX;
2844 : 0 : actions += of_vlan_offset;
2845 : 0 : masks += of_vlan_offset;
2846 : 0 : break;
2847 : 0 : case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
2848 : 0 : dr_action = mlx5_hws_global_action_pop_vlan_get(priv, type, is_root);
2849 [ # # ]: 0 : if (dr_action == NULL) {
2850 : 0 : DRV_LOG(ERR, "port %u failed to allocate pop VLAN action",
2851 : : priv->dev_data->port_id);
2852 : 0 : rte_flow_error_set(&sub_error, ENOMEM,
2853 : : RTE_FLOW_ERROR_TYPE_STATE, NULL,
2854 : : "failed to allocate pop VLAN action");
2855 : 0 : goto err;
2856 : : }
2857 : 0 : acts->rule_acts[dr_pos].action = dr_action;
2858 : 0 : break;
2859 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP:
2860 [ # # ]: 0 : if (masks->conf &&
2861 : : ((const struct rte_flow_action_jump *)
2862 [ # # ]: 0 : masks->conf)->group) {
2863 : 0 : uint32_t jump_group =
2864 : : ((const struct rte_flow_action_jump *)
2865 : 0 : actions->conf)->group;
2866 : 0 : acts->jump = flow_hw_jump_action_register
2867 : : (dev, cfg, jump_group, &sub_error);
2868 [ # # ]: 0 : if (!acts->jump)
2869 : 0 : goto err;
2870 : 0 : acts->rule_acts[dr_pos].action = (!!attr->group) ?
2871 [ # # ]: 0 : acts->jump->hws_action :
2872 : : acts->jump->root_action;
2873 : : } else if (__flow_hw_act_data_general_append
2874 : : (priv, acts, actions->type,
2875 : : src_pos, dr_pos)){
2876 : 0 : goto err;
2877 : : }
2878 : : break;
2879 : 0 : case RTE_FLOW_ACTION_TYPE_QUEUE:
2880 [ # # ]: 0 : if (masks->conf &&
2881 : : ((const struct rte_flow_action_queue *)
2882 [ # # ]: 0 : masks->conf)->index) {
2883 : 0 : acts->tir = flow_hw_tir_action_register
2884 : 0 : (dev, mlx5_hw_act_flag[!!attr->group][type],
2885 : : actions);
2886 [ # # ]: 0 : if (!acts->tir)
2887 : 0 : goto err;
2888 : 0 : acts->rule_acts[dr_pos].action =
2889 : 0 : acts->tir->action;
2890 : : } else if (__flow_hw_act_data_general_append
2891 : : (priv, acts, actions->type,
2892 : : src_pos, dr_pos)) {
2893 : 0 : goto err;
2894 : : }
2895 : : break;
2896 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
2897 [ # # # # ]: 0 : if (actions->conf && masks->conf) {
2898 : 0 : acts->tir = flow_hw_tir_action_register
2899 : 0 : (dev, mlx5_hw_act_flag[!!attr->group][type],
2900 : : actions);
2901 [ # # ]: 0 : if (!acts->tir)
2902 : 0 : goto err;
2903 : 0 : acts->rule_acts[dr_pos].action =
2904 : 0 : acts->tir->action;
2905 : : } else if (__flow_hw_act_data_general_append
2906 : : (priv, acts, actions->type,
2907 : : src_pos, dr_pos)) {
2908 : 0 : goto err;
2909 : : }
2910 : : break;
2911 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
2912 : : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
2913 : : MLX5_ASSERT(!reformat_used);
2914 : 0 : ret = translate_l2_encap_action(actions, masks, converted_encap_data,
2915 : : &data_size, error);
2916 [ # # ]: 0 : if (ret < 0)
2917 : 0 : goto err;
2918 : : /* If masked action, then use converted encap data for shared action. */
2919 [ # # ]: 0 : if (ret > 0) {
2920 : : encap_data = converted_encap_data;
2921 : : encap_data_m = converted_encap_data;
2922 : : }
2923 : : reformat_used = true;
2924 : : reformat_src = src_pos;
2925 : : refmt_type = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;
2926 : : break;
2927 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
2928 : 0 : raw_encap_data =
2929 : : (const struct rte_flow_action_raw_encap *)
2930 : : masks->conf;
2931 [ # # ]: 0 : if (raw_encap_data)
2932 : 0 : encap_data_m = raw_encap_data->data;
2933 : 0 : raw_encap_data =
2934 : : (const struct rte_flow_action_raw_encap *)
2935 : : actions->conf;
2936 : 0 : encap_data = raw_encap_data->data;
2937 : 0 : data_size = raw_encap_data->size;
2938 [ # # ]: 0 : if (reformat_used) {
2939 : : refmt_type = data_size <
2940 : : MLX5_ENCAPSULATION_DECISION_SIZE ?
2941 [ # # ]: 0 : MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2 :
2942 : : MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3;
2943 : : } else {
2944 : : reformat_used = true;
2945 : : refmt_type =
2946 : : MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;
2947 : : }
2948 : : reformat_src = src_pos;
2949 : : break;
2950 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
2951 : : case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
2952 : : MLX5_ASSERT(!reformat_used);
2953 : : reformat_used = true;
2954 : : refmt_type = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2;
2955 : 0 : break;
2956 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
2957 : : reformat_used = true;
2958 : : refmt_type = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2;
2959 : 0 : break;
2960 : 0 : case RTE_FLOW_ACTION_TYPE_IPV6_EXT_PUSH:
2961 [ # # ]: 0 : if (!hca_attr->flex.query_match_sample_info ||
2962 : 0 : !hca_attr->flex.parse_graph_anchor ||
2963 [ # # ]: 0 : !priv->sh->srh_flex_parser.flex.mapnum) {
2964 : 0 : DRV_LOG(ERR, "SRv6 anchor is not supported.");
2965 : 0 : goto err;
2966 : : }
2967 : : MLX5_ASSERT(!recom_used && !recom_type);
2968 : : recom_used = true;
2969 : : recom_type = MLX5DR_ACTION_TYP_PUSH_IPV6_ROUTE_EXT;
2970 : 0 : ipv6_ext_data =
2971 : : (const struct rte_flow_action_ipv6_ext_push *)masks->conf;
2972 [ # # ]: 0 : if (ipv6_ext_data)
2973 : 0 : push_data_m = ipv6_ext_data->data;
2974 : 0 : ipv6_ext_data =
2975 : : (const struct rte_flow_action_ipv6_ext_push *)actions->conf;
2976 [ # # ]: 0 : if (ipv6_ext_data) {
2977 : 0 : push_data = ipv6_ext_data->data;
2978 : 0 : push_size = ipv6_ext_data->size;
2979 : : }
2980 : : recom_src = src_pos;
2981 : : break;
2982 : 0 : case RTE_FLOW_ACTION_TYPE_IPV6_EXT_REMOVE:
2983 [ # # ]: 0 : if (!hca_attr->flex.query_match_sample_info ||
2984 : 0 : !hca_attr->flex.parse_graph_anchor ||
2985 [ # # ]: 0 : !priv->sh->srh_flex_parser.flex.mapnum) {
2986 : 0 : DRV_LOG(ERR, "SRv6 anchor is not supported.");
2987 : 0 : goto err;
2988 : : }
2989 : : recom_used = true;
2990 : : recom_type = MLX5DR_ACTION_TYP_POP_IPV6_ROUTE_EXT;
2991 : : break;
2992 : 0 : case RTE_FLOW_ACTION_TYPE_SEND_TO_KERNEL:
2993 [ # # ]: 0 : if (is_root) {
2994 : 0 : rte_flow_error_set(&sub_error, ENOTSUP,
2995 : : RTE_FLOW_ERROR_TYPE_ACTION,
2996 : : NULL,
2997 : : "Send to kernel action on root table is not supported in HW steering mode");
2998 : 0 : goto err;
2999 : : }
3000 : 0 : dr_action = mlx5_hws_global_action_send_to_kernel_get(priv,
3001 : : type,
3002 : : MLX5_HW_LOWEST_PRIO_ROOT);
3003 [ # # ]: 0 : if (dr_action == NULL) {
3004 : 0 : DRV_LOG(ERR, "port %u failed to allocate send to kernel action",
3005 : : priv->dev_data->port_id);
3006 : 0 : rte_flow_error_set(&sub_error, ENOMEM,
3007 : : RTE_FLOW_ERROR_TYPE_STATE, NULL,
3008 : : "failed to allocate send to kernel action");
3009 : 0 : goto err;
3010 : : }
3011 : 0 : acts->rule_acts[dr_pos].action = dr_action;
3012 : 0 : break;
3013 [ # # ]: 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
3014 : : err = flow_hw_modify_field_compile(dev, attr, actions,
3015 : : masks, acts, &mhdr,
3016 : : src_pos, &sub_error);
3017 [ # # ]: 0 : if (err)
3018 : 0 : goto err;
3019 : : break;
3020 : 0 : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
3021 [ # # ]: 0 : if (flow_hw_represented_port_compile
3022 : : (dev, attr, actions,
3023 : : masks, acts, src_pos, dr_pos, &sub_error))
3024 : 0 : goto err;
3025 : : break;
3026 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
3027 [ # # ]: 0 : if (is_root && !mlx5dr_action_counter_root_is_supported()) {
3028 : 0 : rte_flow_error_set(&sub_error, ENOTSUP,
3029 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3030 : : "Age action is not supported on group 0");
3031 : 0 : goto err;
3032 : : }
3033 : : if (__flow_hw_act_data_general_append(priv, acts,
3034 : : actions->type,
3035 : : src_pos,
3036 : : dr_pos))
3037 : 0 : goto err;
3038 : : break;
3039 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
3040 [ # # ]: 0 : if (is_root && !mlx5dr_action_counter_root_is_supported()) {
3041 : 0 : rte_flow_error_set(&sub_error, ENOTSUP,
3042 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3043 : : "Count action is not supported on root table");
3044 : 0 : goto err;
3045 : : }
3046 [ # # ]: 0 : if ((at->action_flags & MLX5_FLOW_ACTION_AGE) ||
3047 : : (at->action_flags & MLX5_FLOW_ACTION_INDIRECT_AGE))
3048 : : /*
3049 : : * When both COUNT and AGE are requested, it is
3050 : : * saved as AGE action which creates also the
3051 : : * counter.
3052 : : */
3053 : : break;
3054 [ # # ]: 0 : if (masks->conf &&
3055 : : ((const struct rte_flow_action_count *)
3056 [ # # ]: 0 : masks->conf)->id) {
3057 [ # # ]: 0 : err = flow_hw_cnt_compile(dev, dr_pos, acts, is_root);
3058 : : if (err)
3059 : 0 : goto err;
3060 : : } else if (__flow_hw_act_data_general_append
3061 : : (priv, acts, actions->type,
3062 : : src_pos, dr_pos)) {
3063 : 0 : goto err;
3064 : : }
3065 : : break;
3066 : 0 : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
3067 [ # # ]: 0 : if (masks->conf) {
3068 : 0 : ct_idx = MLX5_INDIRECT_ACTION_IDX_GET(actions->conf);
3069 : : if (flow_hw_ct_compile(dev, MLX5_HW_INV_QUEUE, ct_idx,
3070 : 0 : &acts->rule_acts[dr_pos]))
3071 : 0 : goto err;
3072 : : } else if (__flow_hw_act_data_general_append
3073 : : (priv, acts, actions->type,
3074 : : src_pos, dr_pos)) {
3075 : 0 : goto err;
3076 : : }
3077 : : break;
3078 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
3079 [ # # # # ]: 0 : if (actions->conf && masks->conf &&
3080 : : ((const struct rte_flow_action_meter_mark *)
3081 [ # # ]: 0 : masks->conf)->profile) {
3082 : : err = flow_hw_meter_mark_compile(dev,
3083 : : dr_pos, actions,
3084 : 0 : acts->rule_acts,
3085 : : &acts->mtr_id,
3086 : : MLX5_HW_INV_QUEUE,
3087 : : &sub_error);
3088 : : if (err)
3089 : 0 : goto err;
3090 : : } else if (__flow_hw_act_data_general_append(priv, acts,
3091 : : actions->type,
3092 : : src_pos,
3093 : : dr_pos))
3094 : 0 : goto err;
3095 : : break;
3096 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
3097 : 0 : dr_action = mlx5_hws_global_action_def_miss_get(priv, type, is_root);
3098 [ # # ]: 0 : if (dr_action == NULL) {
3099 : 0 : DRV_LOG(ERR, "port %u failed to allocate default miss action",
3100 : : priv->dev_data->port_id);
3101 : 0 : rte_flow_error_set(&sub_error, ENOMEM,
3102 : : RTE_FLOW_ERROR_TYPE_STATE, NULL,
3103 : : "failed to allocate default miss action");
3104 : 0 : goto err;
3105 : : }
3106 : 0 : acts->rule_acts[dr_pos].action = dr_action;
3107 : 0 : break;
3108 : 0 : case RTE_FLOW_ACTION_TYPE_NAT64:
3109 [ # # ]: 0 : if (masks->conf &&
3110 [ # # ]: 0 : ((const struct rte_flow_action_nat64 *)masks->conf)->type) {
3111 : 0 : const struct rte_flow_action_nat64 *nat64_c =
3112 : : (const struct rte_flow_action_nat64 *)actions->conf;
3113 : 0 : dr_action = mlx5_hws_global_action_nat64_get(priv,
3114 : : type,
3115 : 0 : nat64_c->type);
3116 [ # # ]: 0 : if (dr_action == NULL) {
3117 : 0 : DRV_LOG(ERR, "port %u failed to allocate NAT64 action",
3118 : : priv->dev_data->port_id);
3119 : 0 : rte_flow_error_set(&sub_error, ENOMEM,
3120 : : RTE_FLOW_ERROR_TYPE_STATE, NULL,
3121 : : "failed to allocate NAT64 action");
3122 : 0 : goto err;
3123 : : }
3124 : 0 : acts->rule_acts[dr_pos].action = dr_action;
3125 : 0 : break;
3126 : : }
3127 : 0 : acts->nat64[RTE_FLOW_NAT64_6TO4] = mlx5_hws_global_action_nat64_get(priv,
3128 : : type,
3129 : : RTE_FLOW_NAT64_6TO4);
3130 : 0 : acts->nat64[RTE_FLOW_NAT64_4TO6] = mlx5_hws_global_action_nat64_get(priv,
3131 : : type,
3132 : : RTE_FLOW_NAT64_4TO6);
3133 [ # # # # ]: 0 : if (!acts->nat64[RTE_FLOW_NAT64_6TO4] ||
3134 : : !acts->nat64[RTE_FLOW_NAT64_4TO6]) {
3135 : 0 : DRV_LOG(ERR, "port %u failed to allocate both NAT64 actions",
3136 : : priv->dev_data->port_id);
3137 : 0 : rte_flow_error_set(&sub_error, ENOMEM,
3138 : : RTE_FLOW_ERROR_TYPE_STATE, NULL,
3139 : : "failed to allocate both NAT64 actions");
3140 : 0 : goto err;
3141 : : }
3142 : 0 : if (__flow_hw_act_data_general_append(priv, acts,
3143 : : actions->type,
3144 : : src_pos, dr_pos))
3145 : 0 : goto err;
3146 : : break;
3147 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
3148 [ # # ]: 0 : if (masks->conf &&
3149 : : ((const struct rte_flow_action_jump_to_table_index *)
3150 [ # # ]: 0 : masks->conf)->table) {
3151 : 0 : struct rte_flow_template_table *jump_table =
3152 : : ((const struct rte_flow_action_jump_to_table_index *)
3153 : 0 : actions->conf)->table;
3154 : 0 : acts->rule_acts[dr_pos].jump_to_matcher.offset =
3155 : : ((const struct rte_flow_action_jump_to_table_index *)
3156 : 0 : actions->conf)->index;
3157 [ # # ]: 0 : if (likely(!rte_flow_template_table_resizable(dev->data->port_id,
3158 : : &jump_table->cfg.attr))) {
3159 : 0 : acts->rule_acts[dr_pos].action =
3160 : 0 : jump_table->matcher_info[0].jump;
3161 : : } else {
3162 : : uint32_t selector;
3163 : 0 : rte_rwlock_read_lock(&jump_table->matcher_replace_rwlk);
3164 : 0 : selector = jump_table->matcher_selector;
3165 : 0 : acts->rule_acts[dr_pos].action =
3166 : 0 : jump_table->matcher_info[selector].jump;
3167 : 0 : rte_rwlock_read_unlock(&jump_table->matcher_replace_rwlk);
3168 : : }
3169 : : } else if (__flow_hw_act_data_general_append
3170 : : (priv, acts, actions->type,
3171 : : src_pos, dr_pos)){
3172 : 0 : goto err;
3173 : : }
3174 : : break;
3175 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_MIRROR:
3176 : : if (__flow_hw_act_data_general_append(priv, acts,
3177 : : actions->type,
3178 : : src_pos, dr_pos))
3179 : 0 : goto err;
3180 : : break;
3181 : 0 : case RTE_FLOW_ACTION_TYPE_END:
3182 : : actions_end = true;
3183 : 0 : break;
3184 : 0 : case RTE_FLOW_ACTION_TYPE_PORT_ID:
3185 : 0 : DRV_LOG(ERR, "RTE_FLOW_ACTION_TYPE_PORT_ID action is not supported. "
3186 : : "Use RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT instead.");
3187 : 0 : goto err;
3188 : : default:
3189 : : break;
3190 : : }
3191 : : }
3192 [ # # ]: 0 : if (mhdr.pos != UINT16_MAX) {
3193 : 0 : ret = mlx5_tbl_translate_modify_header(dev, cfg, acts, mp_ctx, &mhdr, &sub_error);
3194 [ # # ]: 0 : if (ret)
3195 : 0 : goto err;
3196 [ # # # # ]: 0 : if (!nt_mode && mhdr.shared) {
3197 : 0 : ret = mlx5_tbl_ensure_shared_modify_header(dev, cfg, acts, &sub_error);
3198 [ # # ]: 0 : if (ret)
3199 : 0 : goto err;
3200 : : }
3201 : : }
3202 [ # # ]: 0 : if (reformat_used) {
3203 : 0 : ret = mlx5_tbl_translate_reformat(priv, acts, at,
3204 : : encap_data, encap_data_m,
3205 : : mp_ctx, data_size,
3206 : : reformat_src,
3207 : : refmt_type, &sub_error);
3208 [ # # ]: 0 : if (ret)
3209 : 0 : goto err;
3210 [ # # # # ]: 0 : if (!nt_mode && acts->encap_decap->shared) {
3211 : 0 : ret = mlx5_tbl_create_reformat_action(priv, table_attr, acts, at,
3212 : : encap_data, data_size,
3213 : : refmt_type);
3214 [ # # ]: 0 : if (ret)
3215 : 0 : goto err;
3216 : : }
3217 : : }
3218 [ # # ]: 0 : if (recom_used) {
3219 : : MLX5_ASSERT(at->recom_off != UINT16_MAX);
3220 : 0 : ret = mlx5_create_ipv6_ext_reformat(dev, cfg, acts, at, push_data,
3221 : : push_data_m, push_size, recom_src,
3222 : : recom_type);
3223 [ # # ]: 0 : if (ret)
3224 : 0 : goto err;
3225 : : }
3226 : : return 0;
3227 : 0 : err:
3228 : : /* If rte_errno was not initialized and reached error state. */
3229 [ # # ]: 0 : if (!rte_errno)
3230 : 0 : rte_errno = EINVAL;
3231 : 0 : err = rte_errno;
3232 : : __flow_hw_action_template_destroy(dev, acts);
3233 [ # # # # ]: 0 : if (error != NULL && sub_error.type != RTE_FLOW_ERROR_TYPE_NONE) {
3234 : : rte_memcpy(error, &sub_error, sizeof(sub_error));
3235 : 0 : return -EINVAL;
3236 : : }
3237 : 0 : return rte_flow_error_set(error, err,
3238 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3239 : : "fail to create rte table");
3240 : : }
3241 : :
3242 : : /**
3243 : : * Translate rte_flow actions to DR action.
3244 : : *
3245 : : * As the action template has already indicated the actions. Translate
3246 : : * the rte_flow actions to DR action if possible. So in flow create
3247 : : * stage we will save cycles from handing the actions' organizing.
3248 : : * For the actions with limited information, need to add these to a
3249 : : * list.
3250 : : *
3251 : : * @param[in] dev
3252 : : * Pointer to the rte_eth_dev structure.
3253 : : * @param[in] cfg
3254 : : * Pointer to the table configuration.
3255 : : * @param[in/out] acts
3256 : : * Pointer to the template HW steering DR actions.
3257 : : * @param[in] at
3258 : : * Action template.
3259 : : * @param[out] error
3260 : : * Pointer to error structure.
3261 : : *
3262 : : * @return
3263 : : * 0 on success, a negative errno otherwise and rte_errno is set.
3264 : : */
3265 : : static int
3266 : : flow_hw_translate_actions_template(struct rte_eth_dev *dev,
3267 : : const struct mlx5_flow_template_table_cfg *cfg,
3268 : : struct mlx5_hw_actions *acts,
3269 : : struct rte_flow_actions_template *at,
3270 : : struct mlx5_tbl_multi_pattern_ctx *mp_ctx,
3271 : : struct rte_flow_error *error)
3272 : : {
3273 : 0 : return __flow_hw_translate_actions_template(dev, cfg, acts, at, mp_ctx, false, error);
3274 : : }
3275 : :
3276 : : static __rte_always_inline struct mlx5dr_rule_action *
3277 : : flow_hw_get_dr_action_buffer(struct mlx5_priv *priv,
3278 : : struct rte_flow_template_table *table,
3279 : : uint8_t action_template_index,
3280 : : uint32_t queue)
3281 : : {
3282 : 0 : uint32_t offset = action_template_index * priv->nb_queue + queue;
3283 : :
3284 : 0 : return &table->rule_acts[offset].acts[0];
3285 : : }
3286 : :
3287 : : static void
3288 : 0 : flow_hw_populate_rule_acts_caches(struct rte_eth_dev *dev,
3289 : : struct rte_flow_template_table *table,
3290 : : uint8_t at_idx)
3291 : : {
3292 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
3293 : : uint32_t q;
3294 : :
3295 [ # # ]: 0 : for (q = 0; q < priv->nb_queue; ++q) {
3296 : : struct mlx5dr_rule_action *rule_acts =
3297 : 0 : flow_hw_get_dr_action_buffer(priv, table, at_idx, q);
3298 : :
3299 [ # # ]: 0 : rte_memcpy(rule_acts, table->ats[at_idx].acts.rule_acts,
3300 : : sizeof(table->ats[at_idx].acts.rule_acts));
3301 : : }
3302 : 0 : }
3303 : :
3304 : : /**
3305 : : * Translate rte_flow actions to DR action.
3306 : : *
3307 : : * @param[in] dev
3308 : : * Pointer to the rte_eth_dev structure.
3309 : : * @param[in] tbl
3310 : : * Pointer to the flow template table.
3311 : : * @param[out] error
3312 : : * Pointer to error structure.
3313 : : *
3314 : : * @return
3315 : : * 0 on success, negative value otherwise and rte_errno is set.
3316 : : */
3317 : : static int
3318 : 0 : flow_hw_translate_all_actions_templates(struct rte_eth_dev *dev,
3319 : : struct rte_flow_template_table *tbl,
3320 : : struct rte_flow_error *error)
3321 : : {
3322 : : int ret;
3323 : : uint32_t i;
3324 : :
3325 [ # # ]: 0 : for (i = 0; i < tbl->nb_action_templates; i++) {
3326 [ # # ]: 0 : if (flow_hw_translate_actions_template(dev, &tbl->cfg,
3327 : : &tbl->ats[i].acts,
3328 : : tbl->ats[i].action_template,
3329 : : &tbl->mpctx, error))
3330 : 0 : goto err;
3331 : 0 : flow_hw_populate_rule_acts_caches(dev, tbl, i);
3332 : : }
3333 [ # # ]: 0 : ret = mlx5_tbl_multi_pattern_process(dev, tbl, &tbl->mpctx.segments[0],
3334 : : rte_log2_u32(tbl->cfg.attr.nb_flows),
3335 : : error);
3336 [ # # ]: 0 : if (ret)
3337 : 0 : goto err;
3338 : : return 0;
3339 : : err:
3340 [ # # ]: 0 : while (i--)
3341 : 0 : __flow_hw_action_template_destroy(dev, &tbl->ats[i].acts);
3342 : : return -1;
3343 : : }
3344 : :
3345 : : /**
3346 : : * Get shared indirect action.
3347 : : *
3348 : : * @param[in] dev
3349 : : * Pointer to the rte_eth_dev data structure.
3350 : : * @param[in] act_data
3351 : : * Pointer to the recorded action construct data.
3352 : : * @param[in] item_flags
3353 : : * The matcher itme_flags used for RSS lookup.
3354 : : * @param[in] rule_act
3355 : : * Pointer to the shared action's destination rule DR action.
3356 : : *
3357 : : * @return
3358 : : * 0 on success, negative value otherwise and rte_errno is set.
3359 : : */
3360 : : static __rte_always_inline int
3361 : : flow_hw_shared_action_get(struct rte_eth_dev *dev,
3362 : : struct mlx5_action_construct_data *act_data,
3363 : : const uint64_t item_flags,
3364 : : struct mlx5dr_rule_action *rule_act)
3365 : : {
3366 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
3367 : 0 : struct mlx5_flow_rss_desc rss_desc = { 0 };
3368 : 0 : uint64_t hash_fields = 0;
3369 : : uint32_t hrxq_idx = 0;
3370 : : struct mlx5_hrxq *hrxq = NULL;
3371 : : int act_type = act_data->type;
3372 : :
3373 : : switch (act_type) {
3374 : : case MLX5_RTE_FLOW_ACTION_TYPE_RSS:
3375 : 0 : rss_desc.level = act_data->shared_rss.level;
3376 : 0 : rss_desc.types = act_data->shared_rss.types;
3377 : 0 : rss_desc.symmetric_hash_function = act_data->shared_rss.symmetric_hash_function;
3378 : 0 : mlx5_flow_dv_hashfields_set(item_flags, &rss_desc, &hash_fields);
3379 : 0 : hrxq_idx = mlx5_flow_dv_action_rss_hrxq_lookup
3380 : : (dev, act_data->shared_rss.idx, hash_fields);
3381 [ # # # # : 0 : if (hrxq_idx)
# # # # #
# # # # #
# # # # #
# ]
3382 : 0 : hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
3383 : : hrxq_idx);
3384 [ # # # # : 0 : if (hrxq) {
# # # # #
# # # # #
# # # # #
# ]
3385 : 0 : rule_act->action = hrxq->action;
3386 : : return 0;
3387 : : }
3388 : : break;
3389 : : default:
3390 : : DRV_LOG(WARNING, "Unsupported shared action type:%d",
3391 : : act_data->type);
3392 : : break;
3393 : : }
3394 : : return -1;
3395 : : }
3396 : :
3397 : : static void
3398 : 0 : flow_hw_construct_quota(struct mlx5_priv *priv,
3399 : : struct mlx5dr_rule_action *rule_act, uint32_t qid)
3400 : : {
3401 : 0 : rule_act->action = priv->quota_ctx.dr_action;
3402 : 0 : rule_act->aso_meter.offset = qid - 1;
3403 : 0 : rule_act->aso_meter.init_color =
3404 : : MLX5DR_ACTION_ASO_METER_COLOR_GREEN;
3405 : 0 : }
3406 : :
3407 : : /**
3408 : : * Construct shared indirect action.
3409 : : *
3410 : : * @param[in] dev
3411 : : * Pointer to the rte_eth_dev data structure.
3412 : : * @param[in] queue
3413 : : * The flow creation queue index.
3414 : : * @param[in] action
3415 : : * Pointer to the shared indirect rte_flow action.
3416 : : * @param[in] table
3417 : : * Pointer to the flow table.
3418 : : * @param[in] item_flags
3419 : : * Item flags.
3420 : : * @param[in] action_flags
3421 : : * Actions bit-map detected in this template.
3422 : : * @param[in, out] flow
3423 : : * Pointer to the flow containing the counter.
3424 : : * @param[in] rule_act
3425 : : * Pointer to the shared action's destination rule DR action.
3426 : : *
3427 : : * @return
3428 : : * 0 on success, negative value otherwise and rte_errno is set.
3429 : : */
3430 : : static __rte_always_inline int
3431 : : flow_hw_shared_action_construct(struct rte_eth_dev *dev, uint32_t queue,
3432 : : const struct rte_flow_action *action,
3433 : : struct rte_flow_template_table *table,
3434 : : const uint64_t item_flags, uint64_t action_flags,
3435 : : struct rte_flow_hw *flow,
3436 : : struct mlx5dr_rule_action *rule_act)
3437 : : {
3438 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
3439 : 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
3440 : : struct mlx5_action_construct_data act_data;
3441 : : struct mlx5_shared_action_rss *shared_rss;
3442 : : struct mlx5_aso_mtr *aso_mtr;
3443 : : struct mlx5_age_info *age_info;
3444 : : struct mlx5_hws_age_param *param;
3445 : : struct rte_flow_hw_aux *aux;
3446 : 0 : uint32_t act_idx = (uint32_t)(uintptr_t)action->conf;
3447 : 0 : uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
3448 : 0 : uint32_t idx = act_idx &
3449 : : ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
3450 : : uint32_t *cnt_queue;
3451 : : cnt_id_t age_cnt;
3452 : 0 : bool is_root = mlx5_group_id_is_root(table->grp->group_id);
3453 : :
3454 : : memset(&act_data, 0, sizeof(act_data));
3455 [ # # # # : 0 : switch (type) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3456 : 0 : case MLX5_INDIRECT_ACTION_TYPE_RSS:
3457 : 0 : act_data.type = MLX5_RTE_FLOW_ACTION_TYPE_RSS;
3458 : 0 : shared_rss = mlx5_ipool_get
3459 : 0 : (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
3460 [ # # # # : 0 : if (!shared_rss)
# # # # #
# ]
3461 : : return -1;
3462 : 0 : act_data.shared_rss.idx = idx;
3463 : 0 : act_data.shared_rss.level = shared_rss->origin.level;
3464 : 0 : act_data.shared_rss.types = !shared_rss->origin.types ?
3465 [ # # # # : 0 : RTE_ETH_RSS_IP :
# # # # #
# ]
3466 : : shared_rss->origin.types;
3467 : 0 : act_data.shared_rss.symmetric_hash_function =
3468 : 0 : MLX5_RSS_IS_SYMM(shared_rss->origin.func);
3469 : :
3470 : : if (flow_hw_shared_action_get
3471 : : (dev, &act_data, item_flags, rule_act))
3472 : : return -1;
3473 : : break;
3474 : 0 : case MLX5_INDIRECT_ACTION_TYPE_COUNT:
3475 [ # # # # : 0 : if (mlx5_hws_cnt_pool_get_action_offset(priv->hws_cpool,
# # # # #
# ]
3476 : : act_idx,
3477 : : &rule_act->action,
3478 : : &rule_act->counter.offset,
3479 : : is_root))
3480 : : return -1;
3481 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_CNT_ID;
3482 : 0 : flow->cnt_id = act_idx;
3483 : : break;
3484 : 0 : case MLX5_INDIRECT_ACTION_TYPE_AGE:
3485 [ # # # # : 0 : aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
# # # # #
# ]
3486 : : /*
3487 : : * Save the index with the indirect type, to recognize
3488 : : * it in flow destroy.
3489 : : */
3490 : : mlx5_flow_hw_aux_set_age_idx(flow, aux, act_idx);
3491 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_AGE_IDX;
3492 [ # # # # : 0 : if (action_flags & MLX5_FLOW_ACTION_INDIRECT_COUNT)
# # # # #
# ]
3493 : : /*
3494 : : * The mutual update for idirect AGE & COUNT will be
3495 : : * performed later after we have ID for both of them.
3496 : : */
3497 : : break;
3498 : 0 : age_info = GET_PORT_AGE_INFO(priv);
3499 : 0 : param = mlx5_ipool_get(age_info->ages_ipool, idx);
3500 [ # # # # : 0 : if (param == NULL)
# # # # #
# ]
3501 : : return -1;
3502 [ # # # # : 0 : if (action_flags & MLX5_FLOW_ACTION_COUNT) {
# # # # #
# ]
3503 : : cnt_queue = mlx5_hws_cnt_get_queue(priv, &queue);
3504 [ # # # # : 0 : if (mlx5_hws_cnt_pool_get(priv->hws_cpool, cnt_queue, &age_cnt, idx, 0) < 0)
# # # # #
# ]
3505 : : return -1;
3506 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_CNT_ID;
3507 : 0 : flow->cnt_id = age_cnt;
3508 : 0 : param->nb_cnts++;
3509 : : } else {
3510 : : /*
3511 : : * Get the counter of this indirect AGE or create one
3512 : : * if doesn't exist.
3513 : : */
3514 : : age_cnt = mlx5_hws_age_cnt_get(priv, param, idx);
3515 [ # # # # : 0 : if (age_cnt == 0)
# # # # #
# ]
3516 : : return -1;
3517 : : }
3518 [ # # # # : 0 : if (mlx5_hws_cnt_pool_get_action_offset(priv->hws_cpool,
# # # # #
# ]
3519 : : age_cnt, &rule_act->action,
3520 : : &rule_act->counter.offset, is_root))
3521 : : return -1;
3522 : : break;
3523 : 0 : case MLX5_INDIRECT_ACTION_TYPE_CT:
3524 : : if (flow_hw_ct_compile(dev, queue, idx, rule_act))
3525 : : return -1;
3526 : : break;
3527 : 0 : case MLX5_INDIRECT_ACTION_TYPE_METER_MARK:
3528 : : /* Find ASO object. */
3529 : 0 : aso_mtr = mlx5_ipool_get(pool->idx_pool, idx);
3530 [ # # # # : 0 : if (!aso_mtr)
# # # # #
# ]
3531 : : return -1;
3532 : 0 : rule_act->action = pool->action;
3533 : 0 : rule_act->aso_meter.offset = aso_mtr->offset;
3534 : : break;
3535 : 0 : case MLX5_INDIRECT_ACTION_TYPE_QUOTA:
3536 : 0 : flow_hw_construct_quota(priv, rule_act, idx);
3537 : : break;
3538 : 0 : default:
3539 : 0 : DRV_LOG(WARNING, "Unsupported shared action type:%d", type);
3540 : : break;
3541 : : }
3542 : : return 0;
3543 : : }
3544 : :
3545 : : static __rte_always_inline int
3546 : : flow_hw_mhdr_cmd_is_nop(const struct mlx5_modification_cmd *cmd)
3547 : : {
3548 : : struct mlx5_modification_cmd cmd_he = {
3549 : 0 : .data0 = rte_be_to_cpu_32(cmd->data0),
3550 : : .data1 = 0,
3551 : : };
3552 : :
3553 : 0 : return cmd_he.action_type == MLX5_MODIFICATION_TYPE_NOP;
3554 : : }
3555 : :
3556 : : /**
3557 : : * Construct flow action array.
3558 : : *
3559 : : * For action template contains dynamic actions, these actions need to
3560 : : * be updated according to the rte_flow action during flow creation.
3561 : : *
3562 : : * @param[in] dev
3563 : : * Pointer to the rte_eth_dev structure.
3564 : : * @param[in] job
3565 : : * Pointer to job descriptor.
3566 : : * @param[in] hw_acts
3567 : : * Pointer to translated actions from template.
3568 : : * @param[in] it_idx
3569 : : * Item template index the action template refer to.
3570 : : * @param[in] actions
3571 : : * Array of rte_flow action need to be checked.
3572 : : * @param[in] rule_acts
3573 : : * Array of DR rule actions to be used during flow creation..
3574 : : * @param[in] acts_num
3575 : : * Pointer to the real acts_num flow has.
3576 : : *
3577 : : * @return
3578 : : * 0 on success, negative value otherwise and rte_errno is set.
3579 : : */
3580 : : static __rte_always_inline int
3581 : : flow_hw_modify_field_construct(struct mlx5_modification_cmd *mhdr_cmd,
3582 : : struct mlx5_action_construct_data *act_data,
3583 : : const struct mlx5_hw_actions *hw_acts,
3584 : : const struct rte_flow_action *action)
3585 : : {
3586 : 0 : const struct rte_flow_action_modify_field *mhdr_action = action->conf;
3587 : 0 : uint8_t values[16] = { 0 };
3588 : : unaligned_uint32_t *value_p;
3589 : : uint32_t i;
3590 : : struct field_modify_info *field;
3591 : :
3592 [ # # # # : 0 : if (!hw_acts->mhdr)
# # # # #
# ]
3593 : : return -1;
3594 [ # # # # : 0 : if (hw_acts->mhdr->shared || act_data->modify_header.shared)
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3595 : : return 0;
3596 : : MLX5_ASSERT(mhdr_action->operation == RTE_FLOW_MODIFY_SET ||
3597 : : mhdr_action->operation == RTE_FLOW_MODIFY_ADD);
3598 [ # # # # : 0 : if (mhdr_action->src.field != RTE_FLOW_FIELD_VALUE &&
# # # # #
# ]
3599 : : mhdr_action->src.field != RTE_FLOW_FIELD_POINTER)
3600 : : return 0;
3601 [ # # # # : 0 : if (mhdr_action->src.field == RTE_FLOW_FIELD_VALUE)
# # # # #
# ]
3602 : : rte_memcpy(values, &mhdr_action->src.value, sizeof(values));
3603 : : else
3604 : 0 : rte_memcpy(values, mhdr_action->src.pvalue, sizeof(values));
3605 [ # # # # : 0 : if (mhdr_action->dst.field == RTE_FLOW_FIELD_META ||
# # # # #
# ]
3606 [ # # # # : 0 : mhdr_action->dst.field == RTE_FLOW_FIELD_TAG ||
# # # # #
# ]
3607 [ # # # # : 0 : mhdr_action->dst.field == RTE_FLOW_FIELD_METER_COLOR ||
# # # # #
# ]
3608 : : mhdr_action->dst.field == (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG) {
3609 : 0 : uint8_t tag_index = flow_tag_index_get(&mhdr_action->dst);
3610 : :
3611 : : value_p = (unaligned_uint32_t *)values;
3612 [ # # # # : 0 : if (mhdr_action->dst.field == RTE_FLOW_FIELD_TAG &&
# # # # #
# # # # #
# # # # #
# ]
3613 : : tag_index == RTE_PMD_MLX5_LINEAR_HASH_TAG_INDEX)
3614 [ # # # # : 0 : *value_p = rte_cpu_to_be_32(*value_p << 16);
# # # # #
# ]
3615 : : else
3616 [ # # # # : 0 : *value_p = rte_cpu_to_be_32(*value_p);
# # # # #
# ]
3617 [ # # # # : 0 : } else if (mhdr_action->dst.field == RTE_FLOW_FIELD_GTP_PSC_QFI ||
# # # # #
# ]
3618 : : mhdr_action->dst.field == RTE_FLOW_FIELD_GENEVE_OPT_TYPE) {
3619 : : uint32_t tmp;
3620 : :
3621 : : /*
3622 : : * Both QFI and Geneve option type are passed as an uint8_t integer,
3623 : : * but it is accessed through a 2nd least significant byte of a 32-bit
3624 : : * field in modify header command.
3625 : : */
3626 : 0 : tmp = values[0];
3627 : : value_p = (unaligned_uint32_t *)values;
3628 [ # # # # : 0 : *value_p = rte_cpu_to_be_32(tmp << 8);
# # # # #
# ]
3629 : : }
3630 : 0 : i = act_data->modify_header.mhdr_cmds_off;
3631 : 0 : field = act_data->modify_header.field;
3632 : : do {
3633 : : uint32_t off_b;
3634 : : uint32_t mask;
3635 : : uint32_t data;
3636 : : const uint8_t *mask_src;
3637 : :
3638 [ # # # # : 0 : if (i >= act_data->modify_header.mhdr_cmds_end)
# # # # #
# # # # #
# # # # #
# ]
3639 : : return -1;
3640 [ # # # # : 0 : if (flow_hw_mhdr_cmd_is_nop(&mhdr_cmd[i])) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3641 : 0 : ++i;
3642 : 0 : continue;
3643 : : }
3644 : 0 : mask_src = (const uint8_t *)act_data->modify_header.mask;
3645 : 0 : mask = flow_dv_fetch_field(mask_src + field->offset, field->size);
3646 [ # # # # : 0 : if (!mask) {
# # # # #
# # # # #
# # # # #
# ]
3647 : 0 : ++field;
3648 : 0 : continue;
3649 : : }
3650 : 0 : off_b = rte_bsf32(mask);
3651 : 0 : data = flow_dv_fetch_field(values + field->offset, field->size);
3652 : : /*
3653 : : * IPv6 DSCP uses OUT_IPV6_TRAFFIC_CLASS as ID but it starts from 2
3654 : : * bits left. Shift the data left for IPv6 DSCP
3655 : : */
3656 [ # # # # : 0 : if (field->id == MLX5_MODI_OUT_IPV6_TRAFFIC_CLASS &&
# # # # #
# # # #
# ]
3657 [ # # # # : 0 : mhdr_action->dst.field == RTE_FLOW_FIELD_IPV6_DSCP)
# # ]
3658 : 0 : data <<= MLX5_IPV6_HDR_DSCP_SHIFT;
3659 : 0 : data = (data & mask) >> off_b;
3660 [ # # # # : 0 : mhdr_cmd[i++].data1 = rte_cpu_to_be_32(data);
# # # # #
# # # # #
# # # # #
# ]
3661 : 0 : ++field;
3662 [ # # # # : 0 : } while (field->size);
# # # # #
# # # # #
# # # # #
# ]
3663 : : return 0;
3664 : : }
3665 : :
3666 : : /**
3667 : : * Release any actions allocated for the flow rule during actions construction.
3668 : : *
3669 : : * @param[in] flow
3670 : : * Pointer to flow structure.
3671 : : */
3672 : : static void
3673 : 0 : flow_hw_release_actions(struct rte_eth_dev *dev,
3674 : : uint32_t queue,
3675 : : struct rte_flow_hw *flow)
3676 : : {
3677 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
3678 : 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
3679 [ # # ]: 0 : struct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
3680 : :
3681 [ # # ]: 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_FATE_JUMP)
3682 : 0 : flow_hw_jump_release(dev, flow->jump);
3683 [ # # ]: 0 : else if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_FATE_HRXQ)
3684 : 0 : mlx5_hrxq_obj_release(dev, flow->hrxq);
3685 [ # # ]: 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_CNT_ID)
3686 : 0 : flow_hw_age_count_release(priv, queue, flow, NULL);
3687 [ # # ]: 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_MTR_ID)
3688 : 0 : mlx5_ipool_free(pool->idx_pool, mlx5_flow_hw_aux_get_mtr_id(flow, aux));
3689 : 0 : }
3690 : :
3691 : : /**
3692 : : * Construct flow action array.
3693 : : *
3694 : : * For action template contains dynamic actions, these actions need to
3695 : : * be updated according to the rte_flow action during flow creation.
3696 : : *
3697 : : * @param[in] dev
3698 : : * Pointer to the rte_eth_dev structure.
3699 : : * @param[in] flow
3700 : : * Pointer to flow structure.
3701 : : * @param[in] ap
3702 : : * Pointer to container for temporarily constructed actions' parameters.
3703 : : * @param[in] hw_acts
3704 : : * Pointer to translated actions from template.
3705 : : * @param[in] items_flags
3706 : : * Item flags.
3707 : : * @param[in] table
3708 : : * Pointer to the template table.
3709 : : * @param[in] actions
3710 : : * Array of rte_flow action need to be checked.
3711 : : * @param[in] rule_acts
3712 : : * Array of DR rule actions to be used during flow creation..
3713 : : * @param[in] acts_num
3714 : : * Pointer to the real acts_num flow has.
3715 : : *
3716 : : * @return
3717 : : * 0 on success, negative value otherwise and rte_errno is set.
3718 : : */
3719 : : static __rte_always_inline int
3720 : : flow_hw_actions_construct(struct rte_eth_dev *dev,
3721 : : struct rte_flow_hw *flow,
3722 : : struct mlx5_flow_hw_action_params *ap,
3723 : : const struct mlx5_hw_action_template *hw_at,
3724 : : uint64_t item_flags,
3725 : : struct rte_flow_template_table *table,
3726 : : const struct rte_flow_action actions[],
3727 : : struct mlx5dr_rule_action *rule_acts,
3728 : : uint32_t queue,
3729 : : struct rte_flow_error *error)
3730 : : {
3731 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
3732 : 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
3733 : : struct mlx5_action_construct_data *act_data;
3734 : 0 : const struct rte_flow_actions_template *at = hw_at->action_template;
3735 : : const struct mlx5_hw_actions *hw_acts = &hw_at->acts;
3736 : : const struct rte_flow_action *action;
3737 : : const struct rte_flow_action_raw_encap *raw_encap_data;
3738 : : const struct rte_flow_action_ipv6_ext_push *ipv6_push;
3739 : : const struct rte_flow_item *enc_item = NULL;
3740 : : const struct rte_flow_action_ethdev *port_action = NULL;
3741 : : const struct rte_flow_action_age *age = NULL;
3742 : : const struct rte_flow_action_nat64 *nat64_c = NULL;
3743 : 0 : struct rte_flow_attr attr = {
3744 : : .ingress = 1,
3745 : : };
3746 : : uint32_t ft_flag;
3747 : : int ret;
3748 : 0 : size_t encap_len = 0;
3749 : : uint32_t age_idx = 0;
3750 : : uint32_t mtr_idx = 0;
3751 : : struct mlx5_aso_mtr *aso_mtr;
3752 : : struct mlx5_multi_pattern_segment *mp_segment = NULL;
3753 : : struct rte_flow_hw_aux *aux;
3754 : 0 : bool is_root = mlx5_group_id_is_root(table->grp->group_id);
3755 : :
3756 : : attr.group = table->grp->group_id;
3757 : 0 : ft_flag = mlx5_hw_act_flag[!!table->grp->group_id][table->type];
3758 : 0 : if (table->type >= MLX5DR_TABLE_TYPE_FDB && table->type < MLX5DR_TABLE_TYPE_MAX) {
3759 : 0 : attr.transfer = 1;
3760 : : attr.ingress = 1;
3761 [ # # # # : 0 : } else if (table->type == MLX5DR_TABLE_TYPE_NIC_TX) {
# # # # #
# ]
3762 : 0 : attr.egress = 1;
3763 : 0 : attr.ingress = 0;
3764 : : } else {
3765 : : attr.ingress = 1;
3766 : : }
3767 [ # # # # : 0 : if (hw_acts->mhdr && hw_acts->mhdr->mhdr_cmds_num > 0 && !hw_acts->mhdr->shared) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3768 : 0 : uint16_t pos = hw_acts->mhdr->pos;
3769 : :
3770 : 0 : mp_segment = mlx5_multi_pattern_segment_find(table, flow->res_idx);
3771 [ # # # # : 0 : if (!mp_segment || !mp_segment->mhdr_action)
# # # # #
# # # # #
# # # # #
# ]
3772 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3773 : : NULL, "No modify header action found");
3774 : 0 : rule_acts[pos].action = mp_segment->mhdr_action;
3775 : : /* offset is relative to DR action */
3776 : 0 : rule_acts[pos].modify_header.offset =
3777 : 0 : flow->res_idx - mp_segment->head_index;
3778 : 0 : rule_acts[pos].modify_header.data =
3779 : 0 : (uint8_t *)ap->mhdr_cmd;
3780 : : MLX5_ASSERT(hw_acts->mhdr->mhdr_cmds_num <= MLX5_MHDR_MAX_CMD);
3781 : 0 : rte_memcpy(ap->mhdr_cmd, hw_acts->mhdr->mhdr_cmds,
3782 [ # # # # : 0 : sizeof(*ap->mhdr_cmd) * hw_acts->mhdr->mhdr_cmds_num);
# # # # #
# ]
3783 : : }
3784 [ # # # # : 0 : LIST_FOREACH(act_data, &hw_acts->act_list, next) {
# # # # #
# ]
3785 : : uint32_t jump_group;
3786 : : uint32_t tag;
3787 : : struct mlx5_hw_jump_action *jump;
3788 : : struct mlx5_hrxq *hrxq;
3789 : : uint32_t ct_idx;
3790 : : cnt_id_t cnt_id;
3791 : : uint32_t *cnt_queue;
3792 : : uint32_t mtr_id;
3793 : : struct rte_flow_template_table *jump_table;
3794 : :
3795 : 0 : action = &actions[act_data->action_src];
3796 : : /*
3797 : : * action template construction replaces
3798 : : * OF_SET_VLAN_VID with MODIFY_FIELD
3799 : : */
3800 : 0 : if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)
3801 : : MLX5_ASSERT(act_data->type ==
3802 : : RTE_FLOW_ACTION_TYPE_MODIFY_FIELD);
3803 : : else
3804 : : MLX5_ASSERT(action->type ==
3805 : : RTE_FLOW_ACTION_TYPE_INDIRECT ||
3806 : : (int)action->type == act_data->type);
3807 [ # # # # : 0 : switch ((int)act_data->type) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3808 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT_LIST:
3809 : 0 : act_data->indirect_list_cb(dev, act_data, action,
3810 : 0 : &rule_acts[act_data->action_dst]);
3811 : 0 : break;
3812 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT:
3813 : 0 : if (flow_hw_shared_action_construct
3814 : : (dev, queue, action, table,
3815 : 0 : item_flags, at->action_flags, flow,
3816 [ # # # # : 0 : &rule_acts[act_data->action_dst]))
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3817 : 0 : goto error;
3818 : : break;
3819 : : case RTE_FLOW_ACTION_TYPE_VOID:
3820 : : break;
3821 : 0 : case RTE_FLOW_ACTION_TYPE_MARK:
3822 : 0 : tag = mlx5_flow_mark_set
3823 : : (((const struct rte_flow_action_mark *)
3824 : 0 : (action->conf))->id);
3825 : 0 : rule_acts[act_data->action_dst].tag.value = tag;
3826 : 0 : break;
3827 : 0 : case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
3828 : 0 : rule_acts[act_data->action_dst].push_vlan.vlan_hdr =
3829 : 0 : vlan_hdr_to_be32(action);
3830 : 0 : break;
3831 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP:
3832 : 0 : jump_group = ((const struct rte_flow_action_jump *)
3833 : 0 : action->conf)->group;
3834 : 0 : jump = flow_hw_jump_action_register
3835 : 0 : (dev, &table->cfg, jump_group, NULL);
3836 [ # # # # : 0 : if (!jump)
# # # # #
# ]
3837 : 0 : goto error;
3838 : 0 : rule_acts[act_data->action_dst].action =
3839 [ # # # # : 0 : (!!attr.group) ? jump->hws_action : jump->root_action;
# # # # #
# ]
3840 : 0 : flow->jump = jump;
3841 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_FATE_JUMP;
3842 : 0 : break;
3843 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
3844 : : case RTE_FLOW_ACTION_TYPE_QUEUE:
3845 : 0 : hrxq = flow_hw_tir_action_register(dev, ft_flag, action);
3846 [ # # # # : 0 : if (!hrxq)
# # # # #
# ]
3847 : 0 : goto error;
3848 : 0 : rule_acts[act_data->action_dst].action = hrxq->action;
3849 : 0 : flow->hrxq = hrxq;
3850 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_FATE_HRXQ;
3851 : 0 : break;
3852 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_RSS:
3853 : 0 : if (flow_hw_shared_action_get
3854 : : (dev, act_data, item_flags,
3855 : 0 : &rule_acts[act_data->action_dst]))
3856 : 0 : goto error;
3857 : : break;
3858 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
3859 : 0 : enc_item = ((const struct rte_flow_action_vxlan_encap *)
3860 : 0 : action->conf)->definition;
3861 [ # # # # : 0 : if (mlx5_flow_dv_convert_encap_data(enc_item, ap->encap_data,
# # # # #
# ]
3862 : : &encap_len, NULL))
3863 : 0 : goto error;
3864 : : break;
3865 : 0 : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
3866 : 0 : enc_item = ((const struct rte_flow_action_nvgre_encap *)
3867 : 0 : action->conf)->definition;
3868 [ # # # # : 0 : if (mlx5_flow_dv_convert_encap_data(enc_item, ap->encap_data,
# # # # #
# ]
3869 : : &encap_len, NULL))
3870 : 0 : goto error;
3871 : : break;
3872 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
3873 : 0 : raw_encap_data =
3874 : : (const struct rte_flow_action_raw_encap *)
3875 : : action->conf;
3876 : : MLX5_ASSERT(raw_encap_data->size == act_data->encap.len);
3877 [ # # # # : 0 : if (unlikely(act_data->encap.len > MLX5_ENCAP_MAX_LEN))
# # # # #
# ]
3878 : : return -1;
3879 [ # # # # : 0 : rte_memcpy(ap->encap_data, raw_encap_data->data, act_data->encap.len);
# # # # #
# ]
3880 : : break;
3881 : 0 : case RTE_FLOW_ACTION_TYPE_IPV6_EXT_PUSH:
3882 : 0 : ipv6_push =
3883 : : (const struct rte_flow_action_ipv6_ext_push *)action->conf;
3884 : : MLX5_ASSERT(ipv6_push->size == act_data->ipv6_ext.len);
3885 [ # # # # : 0 : if (unlikely(act_data->ipv6_ext.len > MLX5_PUSH_MAX_LEN))
# # # # #
# ]
3886 : : return -1;
3887 [ # # # # : 0 : rte_memcpy(ap->ipv6_push_data, ipv6_push->data,
# # # # #
# ]
3888 : : act_data->ipv6_ext.len);
3889 : : break;
3890 : 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
3891 [ # # # # : 0 : if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)
# # # # #
# ]
3892 : 0 : ret = flow_hw_set_vlan_vid_construct(dev, ap->mhdr_cmd,
3893 : : act_data,
3894 : : hw_acts,
3895 : : action);
3896 : : else
3897 [ # # # # : 0 : ret = flow_hw_modify_field_construct(ap->mhdr_cmd,
# # # # #
# ]
3898 : : act_data,
3899 : : hw_acts,
3900 : : action);
3901 [ # # # # : 0 : if (ret)
# # # # #
# ]
3902 : 0 : goto error;
3903 : : break;
3904 : 0 : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
3905 : 0 : port_action = action->conf;
3906 [ # # # # : 0 : if (!priv->hw_vport[port_action->port_id])
# # # # #
# ]
3907 : 0 : goto error;
3908 : 0 : rule_acts[act_data->action_dst].action =
3909 : : priv->hw_vport[port_action->port_id];
3910 : 0 : break;
3911 : 0 : case RTE_FLOW_ACTION_TYPE_QUOTA:
3912 : 0 : flow_hw_construct_quota(priv,
3913 : 0 : rule_acts + act_data->action_dst,
3914 : : act_data->shared_meter.id);
3915 : 0 : break;
3916 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
3917 [ # # # # : 0 : aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
# # # # #
# ]
3918 : 0 : age = action->conf;
3919 : : /*
3920 : : * First, create the AGE parameter, then create its
3921 : : * counter later:
3922 : : * Regular counter - in next case.
3923 : : * Indirect counter - update it after the loop.
3924 : : */
3925 : 0 : age_idx = mlx5_hws_age_action_create(priv, queue, 0,
3926 : : age,
3927 : : flow->res_idx,
3928 : : error);
3929 [ # # # # : 0 : if (age_idx == 0)
# # # # #
# ]
3930 : 0 : goto error;
3931 : : mlx5_flow_hw_aux_set_age_idx(flow, aux, age_idx);
3932 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_AGE_IDX;
3933 [ # # # # : 0 : if (at->action_flags & MLX5_FLOW_ACTION_INDIRECT_COUNT)
# # # # #
# ]
3934 : : /*
3935 : : * When AGE uses indirect counter, no need to
3936 : : * create counter but need to update it with the
3937 : : * AGE parameter, will be done after the loop.
3938 : : */
3939 : : break;
3940 : : /* Fall-through. */
3941 : : case RTE_FLOW_ACTION_TYPE_COUNT:
3942 : : cnt_queue = mlx5_hws_cnt_get_queue(priv, &queue);
3943 : : ret = mlx5_hws_cnt_pool_get(priv->hws_cpool, cnt_queue, &cnt_id,
3944 : : age_idx, 0);
3945 [ # # # # : 0 : if (ret != 0) {
# # # # #
# ]
3946 : 0 : rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_ACTION,
3947 : : action, "Failed to allocate flow counter");
3948 : 0 : goto error;
3949 : : }
3950 : 0 : ret = mlx5_hws_cnt_pool_get_action_offset
3951 : : (priv->hws_cpool,
3952 : : cnt_id,
3953 : : &rule_acts[act_data->action_dst].action,
3954 [ # # # # : 0 : &rule_acts[act_data->action_dst].counter.offset,
# # # # #
# ]
3955 : : is_root
3956 : : );
3957 : : if (ret != 0)
3958 : : goto error;
3959 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_CNT_ID;
3960 : 0 : flow->cnt_id = cnt_id;
3961 : 0 : break;
3962 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
3963 : 0 : ret = mlx5_hws_cnt_pool_get_action_offset
3964 : : (priv->hws_cpool,
3965 : : act_data->shared_counter.id,
3966 : : &rule_acts[act_data->action_dst].action,
3967 [ # # # # : 0 : &rule_acts[act_data->action_dst].counter.offset,
# # # # #
# ]
3968 : : is_root
3969 : : );
3970 : : if (ret != 0)
3971 : : goto error;
3972 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_CNT_ID;
3973 : 0 : flow->cnt_id = act_data->shared_counter.id;
3974 : 0 : break;
3975 : 0 : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
3976 : 0 : ct_idx = MLX5_INDIRECT_ACTION_IDX_GET(action->conf);
3977 : 0 : if (flow_hw_ct_compile(dev, queue, ct_idx,
3978 : 0 : &rule_acts[act_data->action_dst]))
3979 : 0 : goto error;
3980 : : break;
3981 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_METER_MARK:
3982 : 0 : mtr_id = act_data->shared_meter.id &
3983 : : ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
3984 : : /* Find ASO object. */
3985 : 0 : aso_mtr = mlx5_ipool_get(pool->idx_pool, mtr_id);
3986 [ # # # # : 0 : if (!aso_mtr)
# # # # #
# ]
3987 : 0 : goto error;
3988 : 0 : rule_acts[act_data->action_dst].action =
3989 : 0 : pool->action;
3990 : 0 : rule_acts[act_data->action_dst].aso_meter.offset =
3991 : 0 : aso_mtr->offset;
3992 : 0 : break;
3993 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
3994 : : /*
3995 : : * Allocate meter directly will slow down flow
3996 : : * insertion rate.
3997 : : */
3998 : : ret = flow_hw_meter_mark_compile(dev,
3999 : 0 : act_data->action_dst, action,
4000 : : rule_acts, &mtr_idx, MLX5_HW_INV_QUEUE, error);
4001 : : if (ret != 0)
4002 : 0 : goto error;
4003 [ # # # # : 0 : aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
# # # # #
# ]
4004 : : mlx5_flow_hw_aux_set_mtr_id(flow, aux, mtr_idx);
4005 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_MTR_ID;
4006 : 0 : break;
4007 : 0 : case RTE_FLOW_ACTION_TYPE_NAT64:
4008 : 0 : nat64_c = action->conf;
4009 : 0 : rule_acts[act_data->action_dst].action = hw_acts->nat64[nat64_c->type];
4010 : 0 : break;
4011 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
4012 : 0 : jump_table = ((const struct rte_flow_action_jump_to_table_index *)
4013 : 0 : action->conf)->table;
4014 [ # # # # : 0 : if (likely(!rte_flow_template_table_resizable(dev->data->port_id,
# # # # #
# ]
4015 : : &table->cfg.attr))) {
4016 : 0 : rule_acts[act_data->action_dst].action =
4017 : 0 : jump_table->matcher_info[0].jump;
4018 : : } else {
4019 : : uint32_t selector;
4020 : 0 : rte_rwlock_read_lock(&table->matcher_replace_rwlk);
4021 : 0 : selector = table->matcher_selector;
4022 : 0 : rule_acts[act_data->action_dst].action =
4023 : 0 : jump_table->matcher_info[selector].jump;
4024 : 0 : rte_rwlock_read_unlock(&table->matcher_replace_rwlk);
4025 : : }
4026 : 0 : rule_acts[act_data->action_dst].jump_to_matcher.offset =
4027 : : ((const struct rte_flow_action_jump_to_table_index *)
4028 : 0 : action->conf)->index;
4029 : 0 : break;
4030 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_MIRROR: {
4031 : 0 : const struct mlx5_mirror *mirror = action->conf;
4032 : :
4033 : 0 : rule_acts[act_data->action_dst].action = mirror->mirror_action;
4034 : 0 : break;
4035 : : }
4036 : : default:
4037 : : break;
4038 : : }
4039 : : }
4040 [ # # # # : 0 : if (at->action_flags & MLX5_FLOW_ACTION_INDIRECT_COUNT) {
# # # # #
# ]
4041 : : /* If indirect count is used, then CNT_ID flag should be set. */
4042 : : MLX5_ASSERT(flow->flags & MLX5_FLOW_HW_FLOW_FLAG_CNT_ID);
4043 [ # # # # : 0 : if (at->action_flags & MLX5_FLOW_ACTION_INDIRECT_AGE) {
# # # # #
# ]
4044 : : /* If indirect AGE is used, then AGE_IDX flag should be set. */
4045 : : MLX5_ASSERT(flow->flags & MLX5_FLOW_HW_FLOW_FLAG_AGE_IDX);
4046 [ # # # # : 0 : aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
# # # # #
# ]
4047 : 0 : age_idx = mlx5_flow_hw_aux_get_age_idx(flow, aux) &
4048 : : MLX5_HWS_AGE_IDX_MASK;
4049 [ # # # # : 0 : if (mlx5_hws_cnt_age_get(priv->hws_cpool, flow->cnt_id) != age_idx)
# # # # #
# # # # #
# # # # #
# ]
4050 : : /*
4051 : : * This is first use of this indirect counter
4052 : : * for this indirect AGE, need to increase the
4053 : : * number of counters.
4054 : : */
4055 : : mlx5_hws_age_nb_cnt_increase(priv, age_idx);
4056 : : }
4057 : : /*
4058 : : * Update this indirect counter the indirect/direct AGE in which
4059 : : * using it.
4060 : : */
4061 [ # # # # : 0 : mlx5_hws_cnt_age_set(priv->hws_cpool, flow->cnt_id, age_idx);
# # # # #
# ]
4062 : : }
4063 [ # # # # : 0 : if (hw_acts->encap_decap && !hw_acts->encap_decap->shared) {
# # # # #
# # # # #
# # # # #
# ]
4064 [ # # # # : 0 : int ix = mlx5_multi_pattern_reformat_to_index(hw_acts->encap_decap->action_type);
# # # # #
# ]
4065 : 0 : struct mlx5dr_rule_action *ra = &rule_acts[hw_acts->encap_decap_pos];
4066 : :
4067 [ # # # # : 0 : if (ix < 0)
# # # # #
# ]
4068 : 0 : goto error;
4069 [ # # # # : 0 : if (!mp_segment)
# # # # #
# ]
4070 : 0 : mp_segment = mlx5_multi_pattern_segment_find(table, flow->res_idx);
4071 [ # # # # : 0 : if (!mp_segment || !mp_segment->reformat_action[ix])
# # # # #
# # # # #
# # # # #
# ]
4072 : 0 : goto error;
4073 : 0 : ra->action = mp_segment->reformat_action[ix];
4074 : : /* reformat offset is relative to selected DR action */
4075 : 0 : ra->reformat.offset = flow->res_idx - mp_segment->head_index;
4076 : 0 : ra->reformat.data = ap->encap_data;
4077 : : }
4078 [ # # # # : 0 : if (hw_acts->push_remove && !hw_acts->push_remove->shared) {
# # # # #
# # # # #
# # # # #
# ]
4079 : 0 : rule_acts[hw_acts->push_remove_pos].ipv6_ext.offset =
4080 : 0 : flow->res_idx - 1;
4081 : 0 : rule_acts[hw_acts->push_remove_pos].ipv6_ext.header = ap->ipv6_push_data;
4082 : : }
4083 [ # # # # : 0 : if (mlx5_hws_cnt_id_valid(hw_acts->cnt_id)) {
# # # # #
# ]
4084 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_CNT_ID;
4085 : 0 : flow->cnt_id = hw_acts->cnt_id;
4086 : : }
4087 : : return 0;
4088 : :
4089 : 0 : error:
4090 : 0 : flow_hw_release_actions(dev, queue, flow);
4091 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4092 : : NULL, "Action construction failed");
4093 : : }
4094 : :
4095 : : static const struct rte_flow_item *
4096 : 0 : flow_hw_get_rule_items(struct rte_eth_dev *dev,
4097 : : const struct rte_flow_template_table *table,
4098 : : const struct rte_flow_item items[],
4099 : : uint8_t pattern_template_index,
4100 : : struct mlx5_flow_hw_pattern_params *pp)
4101 : : {
4102 : 0 : struct rte_flow_pattern_template *pt = table->its[pattern_template_index];
4103 : :
4104 : : /* Only one implicit item can be added to flow rule pattern. */
4105 : : MLX5_ASSERT(!pt->implicit_port || !pt->implicit_tag);
4106 : : /* At least one item was allocated in pattern params for items. */
4107 : : MLX5_ASSERT(MLX5_HW_MAX_ITEMS >= 1);
4108 [ # # ]: 0 : if (pt->implicit_port) {
4109 [ # # ]: 0 : if (pt->orig_item_nb + 1 > MLX5_HW_MAX_ITEMS) {
4110 : 0 : rte_errno = ENOMEM;
4111 : 0 : return NULL;
4112 : : }
4113 : : /* Set up represented port item in pattern params. */
4114 : 0 : pp->port_spec = (struct rte_flow_item_ethdev){
4115 : 0 : .port_id = dev->data->port_id,
4116 : : };
4117 : 0 : pp->items[0] = (struct rte_flow_item){
4118 : : .type = RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT,
4119 : 0 : .spec = &pp->port_spec,
4120 : : };
4121 [ # # ]: 0 : rte_memcpy(&pp->items[1], items, sizeof(*items) * pt->orig_item_nb);
4122 : 0 : return pp->items;
4123 [ # # ]: 0 : } else if (pt->implicit_tag) {
4124 [ # # ]: 0 : if (pt->orig_item_nb + 1 > MLX5_HW_MAX_ITEMS) {
4125 : 0 : rte_errno = ENOMEM;
4126 : 0 : return NULL;
4127 : : }
4128 : : /* Set up tag item in pattern params. */
4129 : 0 : pp->tag_spec = (struct rte_flow_item_tag){
4130 : : .data = flow_hw_tx_tag_regc_value(dev),
4131 : : };
4132 : 0 : pp->items[0] = (struct rte_flow_item){
4133 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_TAG,
4134 : 0 : .spec = &pp->tag_spec,
4135 : : };
4136 [ # # ]: 0 : rte_memcpy(&pp->items[1], items, sizeof(*items) * pt->orig_item_nb);
4137 : 0 : return pp->items;
4138 : : } else {
4139 : : return items;
4140 : : }
4141 : : }
4142 : :
4143 : : /**
4144 : : * Enqueue HW steering flow creation.
4145 : : *
4146 : : * The flow will be applied to the HW only if the postpone bit is not set or
4147 : : * the extra push function is called.
4148 : : * The flow creation status should be checked from dequeue result.
4149 : : *
4150 : : * @param[in] dev
4151 : : * Pointer to the rte_eth_dev structure.
4152 : : * @param[in] queue
4153 : : * The queue to create the flow.
4154 : : * @param[in] attr
4155 : : * Pointer to the flow operation attributes.
4156 : : * @param[in] table
4157 : : * Pointer to the template table.
4158 : : * @param[in] insertion_type
4159 : : * Insertion type for flow rules.
4160 : : * @param[in] rule_index
4161 : : * The item pattern flow follows from the table.
4162 : : * @param[in] items
4163 : : * Items with flow spec value.
4164 : : * @param[in] pattern_template_index
4165 : : * The item pattern flow follows from the table.
4166 : : * @param[in] actions
4167 : : * Action with flow spec value.
4168 : : * @param[in] action_template_index
4169 : : * The action pattern flow follows from the table.
4170 : : * @param[in] user_data
4171 : : * Pointer to the user_data.
4172 : : * @param[out] error
4173 : : * Pointer to error structure.
4174 : : *
4175 : : * @return
4176 : : * Flow pointer on success, NULL otherwise and rte_errno is set.
4177 : : */
4178 : : static __rte_always_inline struct rte_flow *
4179 : : flow_hw_async_flow_create_generic(struct rte_eth_dev *dev,
4180 : : uint32_t queue,
4181 : : const struct rte_flow_op_attr *attr,
4182 : : struct rte_flow_template_table *table,
4183 : : enum rte_flow_table_insertion_type insertion_type,
4184 : : uint32_t rule_index,
4185 : : const struct rte_flow_item items[],
4186 : : uint8_t pattern_template_index,
4187 : : const struct rte_flow_action actions[],
4188 : : uint8_t action_template_index,
4189 : : void *user_data,
4190 : : struct rte_flow_error *error)
4191 : : {
4192 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4193 : 0 : struct mlx5dr_rule_attr rule_attr = {
4194 : : .queue_id = queue,
4195 : : .user_data = user_data,
4196 : 0 : .burst = attr->postpone,
4197 : : };
4198 : : struct mlx5dr_rule_action *rule_acts;
4199 : : struct rte_flow_hw *flow = NULL;
4200 : : const struct rte_flow_item *rule_items;
4201 : 0 : struct rte_flow_error sub_error = { 0 };
4202 : 0 : uint32_t flow_idx = 0;
4203 : 0 : uint32_t res_idx = 0;
4204 : : int ret;
4205 : :
4206 : 0 : if (mlx5_fp_debug_enabled()) {
4207 [ # # # # : 0 : if (flow_hw_async_create_validate(dev, queue, table, insertion_type, rule_index,
# # ]
4208 : : items, pattern_template_index, actions, action_template_index, error))
4209 : : return NULL;
4210 : : }
4211 : 0 : flow = mlx5_ipool_malloc(table->flow_pool, &flow_idx);
4212 [ # # # # : 0 : if (!flow) {
# # ]
4213 : 0 : rte_errno = ENOMEM;
4214 : 0 : goto error;
4215 : : }
4216 : 0 : flow->nt_rule = false;
4217 : : rule_acts = flow_hw_get_dr_action_buffer(priv, table, action_template_index, queue);
4218 : : /*
4219 : : * Set the table here in order to know the destination table
4220 : : * when free the flow afterward.
4221 : : */
4222 : 0 : flow->table = table;
4223 : 0 : flow->mt_idx = pattern_template_index;
4224 : 0 : flow->idx = flow_idx;
4225 [ # # # # : 0 : if (table->resource) {
# # ]
4226 : 0 : mlx5_ipool_malloc(table->resource, &res_idx);
4227 [ # # # # : 0 : if (!res_idx) {
# # ]
4228 : 0 : rte_errno = ENOMEM;
4229 : 0 : goto error;
4230 : : }
4231 : 0 : flow->res_idx = res_idx;
4232 : : } else {
4233 : 0 : flow->res_idx = flow_idx;
4234 : : }
4235 : 0 : flow->flags = 0;
4236 : : /*
4237 : : * Set the flow operation type here in order to know if the flow memory
4238 : : * should be freed or not when get the result from dequeue.
4239 : : */
4240 : 0 : flow->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_CREATE;
4241 : 0 : flow->user_data = user_data;
4242 : 0 : rule_attr.user_data = flow;
4243 : : /*
4244 : : * Indexed pool returns 1-based indices, but mlx5dr expects 0-based indices
4245 : : * for rule insertion hints.
4246 : : */
4247 [ # # # # ]: 0 : flow->rule_idx = (rule_index == UINT32_MAX) ? flow->res_idx - 1 : rule_index;
4248 : 0 : rule_attr.rule_idx = flow->rule_idx;
4249 : : /*
4250 : : * Construct the flow actions based on the input actions.
4251 : : * The implicitly appended action is always fixed, like metadata
4252 : : * copy action from FDB to NIC Rx.
4253 : : * No need to copy and contrust a new "actions" list based on the
4254 : : * user's input, in order to save the cost.
4255 : : */
4256 [ # # # # : 0 : if (flow_hw_actions_construct(dev, flow, &priv->hw_q[queue].ap,
# # ]
4257 : 0 : &table->ats[action_template_index],
4258 [ # # # # : 0 : table->its[pattern_template_index]->item_flags,
# # ]
4259 : : flow->table, actions,
4260 : : rule_acts, queue, &sub_error))
4261 : 0 : goto error;
4262 : : if (insertion_type == RTE_FLOW_TABLE_INSERTION_TYPE_INDEX) {
4263 : : rule_items = items;
4264 : : } else {
4265 : 0 : rule_items = flow_hw_get_rule_items(dev, table, items,
4266 : 0 : pattern_template_index, &priv->hw_q[queue].pp);
4267 [ # # # # ]: 0 : if (!rule_items)
4268 : 0 : goto error;
4269 : : }
4270 [ # # # # : 0 : if (likely(!rte_flow_template_table_resizable(dev->data->port_id, &table->cfg.attr))) {
# # ]
4271 : 0 : ret = mlx5dr_rule_create(table->matcher_info[0].matcher,
4272 : : pattern_template_index, rule_items,
4273 : : action_template_index, rule_acts,
4274 : : &rule_attr,
4275 : 0 : (struct mlx5dr_rule *)flow->rule);
4276 : : } else {
4277 [ # # # # : 0 : struct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
# # ]
4278 : : uint32_t selector;
4279 : :
4280 : 0 : flow->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_CREATE;
4281 : 0 : rte_rwlock_read_lock(&table->matcher_replace_rwlk);
4282 : 0 : selector = table->matcher_selector;
4283 : 0 : ret = mlx5dr_rule_create(table->matcher_info[selector].matcher,
4284 : : pattern_template_index, rule_items,
4285 : : action_template_index, rule_acts,
4286 : : &rule_attr,
4287 : 0 : (struct mlx5dr_rule *)flow->rule);
4288 : 0 : rte_rwlock_read_unlock(&table->matcher_replace_rwlk);
4289 : 0 : aux->matcher_selector = selector;
4290 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_MATCHER_SELECTOR;
4291 : : }
4292 : :
4293 [ # # # # : 0 : if (likely(!ret)) {
# # ]
4294 : 0 : flow_hw_q_inc_flow_ops(priv, queue);
4295 : 0 : return (struct rte_flow *)flow;
4296 : : }
4297 : 0 : error:
4298 [ # # # # : 0 : if (table->resource && res_idx)
# # # # #
# # # ]
4299 : 0 : mlx5_ipool_free(table->resource, res_idx);
4300 [ # # # # : 0 : if (flow_idx)
# # ]
4301 : 0 : mlx5_ipool_free(table->flow_pool, flow_idx);
4302 [ # # # # : 0 : if (sub_error.cause != RTE_FLOW_ERROR_TYPE_NONE && error != NULL)
# # # # #
# # # ]
4303 : 0 : *error = sub_error;
4304 : : else
4305 : 0 : rte_flow_error_set(error, rte_errno,
4306 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4307 : : "fail to create rte flow");
4308 : : return NULL;
4309 : : }
4310 : :
4311 : : static struct rte_flow *
4312 : 0 : flow_hw_async_flow_create(struct rte_eth_dev *dev,
4313 : : uint32_t queue,
4314 : : const struct rte_flow_op_attr *attr,
4315 : : struct rte_flow_template_table *table,
4316 : : const struct rte_flow_item items[],
4317 : : uint8_t pattern_template_index,
4318 : : const struct rte_flow_action actions[],
4319 : : uint8_t action_template_index,
4320 : : void *user_data,
4321 : : struct rte_flow_error *error)
4322 : : {
4323 : : uint32_t rule_index = UINT32_MAX;
4324 : :
4325 [ # # ]: 0 : return flow_hw_async_flow_create_generic(dev, queue, attr, table,
4326 : : RTE_FLOW_TABLE_INSERTION_TYPE_PATTERN, rule_index,
4327 : : items, pattern_template_index, actions, action_template_index,
4328 : : user_data, error);
4329 : : }
4330 : :
4331 : : static struct rte_flow *
4332 : 0 : flow_hw_async_flow_create_by_index(struct rte_eth_dev *dev,
4333 : : uint32_t queue,
4334 : : const struct rte_flow_op_attr *attr,
4335 : : struct rte_flow_template_table *table,
4336 : : uint32_t rule_index,
4337 : : const struct rte_flow_action actions[],
4338 : : uint8_t action_template_index,
4339 : : void *user_data,
4340 : : struct rte_flow_error *error)
4341 : : {
4342 : 0 : struct rte_flow_item items[] = {{.type = RTE_FLOW_ITEM_TYPE_END,}};
4343 : : uint8_t pattern_template_index = 0;
4344 : :
4345 [ # # ]: 0 : return flow_hw_async_flow_create_generic(dev, queue, attr, table,
4346 : : RTE_FLOW_TABLE_INSERTION_TYPE_INDEX, rule_index,
4347 : : items, pattern_template_index, actions, action_template_index,
4348 : : user_data, error);
4349 : : }
4350 : :
4351 : : static struct rte_flow *
4352 : 0 : flow_hw_async_flow_create_by_index_with_pattern(struct rte_eth_dev *dev,
4353 : : uint32_t queue,
4354 : : const struct rte_flow_op_attr *attr,
4355 : : struct rte_flow_template_table *table,
4356 : : uint32_t rule_index,
4357 : : const struct rte_flow_item items[],
4358 : : uint8_t pattern_template_index,
4359 : : const struct rte_flow_action actions[],
4360 : : uint8_t action_template_index,
4361 : : void *user_data,
4362 : : struct rte_flow_error *error)
4363 : : {
4364 [ # # ]: 0 : return flow_hw_async_flow_create_generic(dev, queue, attr, table,
4365 : : RTE_FLOW_TABLE_INSERTION_TYPE_INDEX_WITH_PATTERN, rule_index,
4366 : : items, pattern_template_index, actions, action_template_index,
4367 : : user_data, error);
4368 : : }
4369 : :
4370 : : /**
4371 : : * Enqueue HW steering flow update.
4372 : : *
4373 : : * The flow will be applied to the HW only if the postpone bit is not set or
4374 : : * the extra push function is called.
4375 : : * The flow destruction status should be checked from dequeue result.
4376 : : *
4377 : : * @param[in] dev
4378 : : * Pointer to the rte_eth_dev structure.
4379 : : * @param[in] queue
4380 : : * The queue to destroy the flow.
4381 : : * @param[in] attr
4382 : : * Pointer to the flow operation attributes.
4383 : : * @param[in] flow
4384 : : * Pointer to the flow to be destroyed.
4385 : : * @param[in] actions
4386 : : * Action with flow spec value.
4387 : : * @param[in] action_template_index
4388 : : * The action pattern flow follows from the table.
4389 : : * @param[in] user_data
4390 : : * Pointer to the user_data.
4391 : : * @param[out] error
4392 : : * Pointer to error structure.
4393 : : *
4394 : : * @return
4395 : : * 0 on success, negative value otherwise and rte_errno is set.
4396 : : */
4397 : : static int
4398 : 0 : flow_hw_async_flow_update(struct rte_eth_dev *dev,
4399 : : uint32_t queue,
4400 : : const struct rte_flow_op_attr *attr,
4401 : : struct rte_flow *flow,
4402 : : const struct rte_flow_action actions[],
4403 : : uint8_t action_template_index,
4404 : : void *user_data,
4405 : : struct rte_flow_error *error)
4406 : : {
4407 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4408 : 0 : struct mlx5dr_rule_attr rule_attr = {
4409 : : .queue_id = queue,
4410 : : .user_data = user_data,
4411 : 0 : .burst = attr->postpone,
4412 : : };
4413 : : struct mlx5dr_rule_action *rule_acts;
4414 : : struct rte_flow_hw *of = (struct rte_flow_hw *)flow;
4415 : : struct rte_flow_hw *nf;
4416 : : struct rte_flow_hw_aux *aux;
4417 : 0 : struct rte_flow_template_table *table = of->table;
4418 : 0 : uint32_t res_idx = 0;
4419 : : int ret;
4420 : :
4421 [ # # ]: 0 : if (mlx5_fp_debug_enabled()) {
4422 [ # # ]: 0 : if (flow_hw_async_update_validate(dev, queue, of, actions, action_template_index,
4423 : : error))
4424 : 0 : return -rte_errno;
4425 : : }
4426 [ # # ]: 0 : aux = mlx5_flow_hw_aux(dev->data->port_id, of);
4427 : 0 : nf = &aux->upd_flow;
4428 : 0 : nf->nt_rule = false;
4429 : 0 : rule_acts = flow_hw_get_dr_action_buffer(priv, table, action_template_index, queue);
4430 : : /*
4431 : : * Set the table here in order to know the destination table
4432 : : * when free the flow afterwards.
4433 : : */
4434 : 0 : nf->table = table;
4435 : 0 : nf->mt_idx = of->mt_idx;
4436 : 0 : nf->idx = of->idx;
4437 [ # # ]: 0 : if (table->resource) {
4438 : 0 : mlx5_ipool_malloc(table->resource, &res_idx);
4439 [ # # ]: 0 : if (!res_idx) {
4440 : 0 : rte_errno = ENOMEM;
4441 : 0 : goto error;
4442 : : }
4443 : 0 : nf->res_idx = res_idx;
4444 : : } else {
4445 : 0 : nf->res_idx = of->res_idx;
4446 : : }
4447 : 0 : nf->flags = 0;
4448 : : /* Indicate the construction function to set the proper fields. */
4449 : 0 : nf->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE;
4450 : : /*
4451 : : * Indexed pool returns 1-based indices, but mlx5dr expects 0-based indices
4452 : : * for rule insertion hints.
4453 : : * If there is only one STE, the update will be atomic by nature.
4454 : : */
4455 : 0 : nf->rule_idx = nf->res_idx - 1;
4456 : 0 : rule_attr.rule_idx = nf->rule_idx;
4457 : : /*
4458 : : * Construct the flow actions based on the input actions.
4459 : : * The implicitly appended action is always fixed, like metadata
4460 : : * copy action from FDB to NIC Rx.
4461 : : * No need to copy and contrust a new "actions" list based on the
4462 : : * user's input, in order to save the cost.
4463 : : */
4464 [ # # ]: 0 : if (flow_hw_actions_construct(dev, nf, &priv->hw_q[queue].ap,
4465 : 0 : &table->ats[action_template_index],
4466 [ # # ]: 0 : table->its[nf->mt_idx]->item_flags,
4467 : : table, actions,
4468 : : rule_acts, queue, error)) {
4469 : 0 : rte_errno = EINVAL;
4470 : 0 : goto error;
4471 : : }
4472 : : /*
4473 : : * Set the flow operation type here in order to know if the flow memory
4474 : : * should be freed or not when get the result from dequeue.
4475 : : */
4476 : 0 : of->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE;
4477 : 0 : of->user_data = user_data;
4478 : 0 : of->flags |= MLX5_FLOW_HW_FLOW_FLAG_UPD_FLOW;
4479 : 0 : rule_attr.user_data = of;
4480 : 0 : ret = mlx5dr_rule_action_update((struct mlx5dr_rule *)of->rule,
4481 : : action_template_index, rule_acts, &rule_attr);
4482 [ # # ]: 0 : if (likely(!ret)) {
4483 : 0 : flow_hw_q_inc_flow_ops(priv, queue);
4484 : 0 : return 0;
4485 : : }
4486 : 0 : error:
4487 [ # # # # ]: 0 : if (table->resource && res_idx)
4488 : 0 : mlx5_ipool_free(table->resource, res_idx);
4489 : 0 : return rte_flow_error_set(error, rte_errno,
4490 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4491 : : "fail to update rte flow");
4492 : : }
4493 : :
4494 : : /**
4495 : : * Enqueue HW steering flow destruction.
4496 : : *
4497 : : * The flow will be applied to the HW only if the postpone bit is not set or
4498 : : * the extra push function is called.
4499 : : * The flow destruction status should be checked from dequeue result.
4500 : : *
4501 : : * @param[in] dev
4502 : : * Pointer to the rte_eth_dev structure.
4503 : : * @param[in] queue
4504 : : * The queue to destroy the flow.
4505 : : * @param[in] attr
4506 : : * Pointer to the flow operation attributes.
4507 : : * @param[in] flow
4508 : : * Pointer to the flow to be destroyed.
4509 : : * @param[in] user_data
4510 : : * Pointer to the user_data.
4511 : : * @param[out] error
4512 : : * Pointer to error structure.
4513 : : *
4514 : : * @return
4515 : : * 0 on success, negative value otherwise and rte_errno is set.
4516 : : */
4517 : : static int
4518 : 0 : flow_hw_async_flow_destroy(struct rte_eth_dev *dev,
4519 : : uint32_t queue,
4520 : : const struct rte_flow_op_attr *attr,
4521 : : struct rte_flow *flow,
4522 : : void *user_data,
4523 : : struct rte_flow_error *error)
4524 : : {
4525 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4526 : 0 : struct mlx5dr_rule_attr rule_attr = {
4527 : : .queue_id = queue,
4528 : : .user_data = user_data,
4529 : 0 : .burst = attr->postpone,
4530 : : };
4531 : : struct rte_flow_hw *fh = (struct rte_flow_hw *)flow;
4532 : 0 : bool resizable = rte_flow_template_table_resizable(dev->data->port_id,
4533 : 0 : &fh->table->cfg.attr);
4534 : : int ret;
4535 : :
4536 : : if (mlx5_fp_debug_enabled()) {
4537 : : if (flow_hw_async_destroy_validate(dev, queue, fh, error))
4538 : : return -rte_errno;
4539 : : }
4540 [ # # ]: 0 : fh->operation_type = !resizable ?
4541 : : MLX5_FLOW_HW_FLOW_OP_TYPE_DESTROY :
4542 : : MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_DESTROY;
4543 : 0 : fh->user_data = user_data;
4544 : 0 : rule_attr.user_data = fh;
4545 : 0 : rule_attr.rule_idx = fh->rule_idx;
4546 : 0 : ret = mlx5dr_rule_destroy((struct mlx5dr_rule *)fh->rule, &rule_attr);
4547 [ # # ]: 0 : if (ret) {
4548 : 0 : return rte_flow_error_set(error, rte_errno,
4549 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4550 : : "fail to destroy rte flow");
4551 : : }
4552 : : flow_hw_q_inc_flow_ops(priv, queue);
4553 : 0 : return 0;
4554 : : }
4555 : :
4556 : : /**
4557 : : * Release the AGE and counter for given flow.
4558 : : *
4559 : : * @param[in] priv
4560 : : * Pointer to the port private data structure.
4561 : : * @param[in] queue
4562 : : * The queue to release the counter.
4563 : : * @param[in, out] flow
4564 : : * Pointer to the flow containing the counter.
4565 : : * @param[out] error
4566 : : * Pointer to error structure.
4567 : : */
4568 : : static void
4569 : 0 : flow_hw_age_count_release(struct mlx5_priv *priv, uint32_t queue,
4570 : : struct rte_flow_hw *flow,
4571 : : struct rte_flow_error *error)
4572 : : {
4573 [ # # ]: 0 : struct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(priv->dev_data->port_id, flow);
4574 : : uint32_t *cnt_queue;
4575 : 0 : uint32_t age_idx = aux->orig.age_idx;
4576 : :
4577 : : MLX5_ASSERT(flow->flags & MLX5_FLOW_HW_FLOW_FLAG_CNT_ID);
4578 [ # # # # ]: 0 : if (mlx5_hws_cnt_is_shared(priv->hws_cpool, flow->cnt_id)) {
4579 [ # # # # ]: 0 : if ((flow->flags & MLX5_FLOW_HW_FLOW_FLAG_AGE_IDX) &&
4580 : : !mlx5_hws_age_is_indirect(age_idx)) {
4581 : : /* Remove this AGE parameter from indirect counter. */
4582 [ # # ]: 0 : mlx5_hws_cnt_age_set(priv->hws_cpool, flow->cnt_id, 0);
4583 : : /* Release the AGE parameter. */
4584 : 0 : mlx5_hws_age_action_destroy(priv, age_idx, error);
4585 : : }
4586 : 0 : return;
4587 : : }
4588 : : cnt_queue = mlx5_hws_cnt_get_queue(priv, &queue);
4589 : : /* Put the counter first to reduce the race risk in BG thread. */
4590 [ # # ]: 0 : mlx5_hws_cnt_pool_put(priv->hws_cpool, cnt_queue, &flow->cnt_id);
4591 [ # # ]: 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_AGE_IDX) {
4592 [ # # ]: 0 : if (mlx5_hws_age_is_indirect(age_idx)) {
4593 : 0 : uint32_t idx = age_idx & MLX5_HWS_AGE_IDX_MASK;
4594 : :
4595 : : mlx5_hws_age_nb_cnt_decrease(priv, idx);
4596 : : } else {
4597 : : /* Release the AGE parameter. */
4598 : 0 : mlx5_hws_age_action_destroy(priv, age_idx, error);
4599 : : }
4600 : : }
4601 : : }
4602 : :
4603 : : static __rte_always_inline void
4604 : : flow_hw_pull_legacy_indirect_comp(struct rte_eth_dev *dev, struct mlx5_hw_q_job *job,
4605 : : uint32_t queue)
4606 : : {
4607 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4608 : : struct mlx5_aso_ct_action *aso_ct;
4609 : : struct mlx5_aso_mtr *aso_mtr;
4610 : : uint32_t type, idx;
4611 : :
4612 [ # # ]: 0 : if (MLX5_INDIRECT_ACTION_TYPE_GET(job->action) ==
4613 : : MLX5_INDIRECT_ACTION_TYPE_QUOTA) {
4614 : 0 : mlx5_quota_async_completion(dev, queue, job);
4615 [ # # ]: 0 : } else if (job->type == MLX5_HW_Q_JOB_TYPE_DESTROY) {
4616 : : type = MLX5_INDIRECT_ACTION_TYPE_GET(job->action);
4617 [ # # ]: 0 : if (type == MLX5_INDIRECT_ACTION_TYPE_METER_MARK) {
4618 : 0 : idx = MLX5_INDIRECT_ACTION_IDX_GET(job->action);
4619 : 0 : mlx5_ipool_free(priv->hws_mpool->idx_pool, idx);
4620 : : }
4621 [ # # ]: 0 : } else if (job->type == MLX5_HW_Q_JOB_TYPE_CREATE) {
4622 : : type = MLX5_INDIRECT_ACTION_TYPE_GET(job->action);
4623 [ # # ]: 0 : if (type == MLX5_INDIRECT_ACTION_TYPE_METER_MARK) {
4624 : 0 : idx = MLX5_INDIRECT_ACTION_IDX_GET(job->action);
4625 : 0 : aso_mtr = mlx5_ipool_get(priv->hws_mpool->idx_pool, idx);
4626 : 0 : aso_mtr->state = ASO_METER_READY;
4627 [ # # ]: 0 : } else if (type == MLX5_INDIRECT_ACTION_TYPE_CT) {
4628 : 0 : idx = MLX5_INDIRECT_ACTION_IDX_GET(job->action);
4629 : 0 : aso_ct = mlx5_ipool_get(priv->hws_ctpool->cts, idx);
4630 : 0 : aso_ct->state = ASO_CONNTRACK_READY;
4631 : : }
4632 [ # # ]: 0 : } else if (job->type == MLX5_HW_Q_JOB_TYPE_QUERY) {
4633 : : type = MLX5_INDIRECT_ACTION_TYPE_GET(job->action);
4634 [ # # ]: 0 : if (type == MLX5_INDIRECT_ACTION_TYPE_CT) {
4635 : 0 : idx = MLX5_INDIRECT_ACTION_IDX_GET(job->action);
4636 : 0 : aso_ct = mlx5_ipool_get(priv->hws_ctpool->cts, idx);
4637 : 0 : mlx5_aso_ct_obj_analyze(job->query.user,
4638 : 0 : job->query.hw);
4639 : 0 : aso_ct->state = ASO_CONNTRACK_READY;
4640 : : }
4641 : : }
4642 : : }
4643 : :
4644 : : static __rte_always_inline int
4645 : : mlx5_hw_pull_flow_transfer_comp(struct rte_eth_dev *dev,
4646 : : uint32_t queue, struct rte_flow_op_result res[],
4647 : : uint16_t n_res)
4648 : : {
4649 : : uint32_t size, i;
4650 : 0 : struct rte_flow_hw *flow = NULL;
4651 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4652 : 0 : struct rte_ring *ring = priv->hw_q[queue].flow_transfer_completed;
4653 : :
4654 : 0 : if (ring == NULL)
4655 : : return 0;
4656 : :
4657 : 0 : size = RTE_MIN(rte_ring_count(ring), n_res);
4658 [ # # ]: 0 : for (i = 0; i < size; i++) {
4659 [ # # # # : 0 : res[i].status = RTE_FLOW_OP_SUCCESS;
# ]
4660 : : rte_ring_dequeue(ring, (void **)&flow);
4661 : 0 : res[i].user_data = flow->user_data;
4662 : : flow_hw_q_dec_flow_ops(priv, queue);
4663 : : }
4664 : 0 : return (int)size;
4665 : : }
4666 : :
4667 : : static inline int
4668 : 0 : __flow_hw_pull_indir_action_comp(struct rte_eth_dev *dev,
4669 : : uint32_t queue,
4670 : : struct rte_flow_op_result res[],
4671 : : uint16_t n_res)
4672 : :
4673 : : {
4674 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4675 : 0 : struct rte_ring *r = priv->hw_q[queue].indir_cq;
4676 : 0 : void *user_data = NULL;
4677 : : int ret_comp, i;
4678 : :
4679 : 0 : ret_comp = (int)rte_ring_count(r);
4680 : 0 : if (ret_comp > n_res)
4681 : : ret_comp = n_res;
4682 [ # # ]: 0 : for (i = 0; i < ret_comp; i++) {
4683 : : rte_ring_dequeue(r, &user_data);
4684 : 0 : res[i].user_data = user_data;
4685 : 0 : res[i].status = RTE_FLOW_OP_SUCCESS;
4686 : : }
4687 [ # # ]: 0 : if (!priv->shared_host) {
4688 [ # # # # ]: 0 : if (ret_comp < n_res && priv->hws_mpool)
4689 : 0 : ret_comp += mlx5_aso_pull_completion(&priv->hws_mpool->sq[queue],
4690 : 0 : &res[ret_comp], n_res - ret_comp);
4691 [ # # # # ]: 0 : if (ret_comp < n_res && priv->hws_ctpool)
4692 : 0 : ret_comp += mlx5_aso_pull_completion(&priv->ct_mng->aso_sqs[queue],
4693 : 0 : &res[ret_comp], n_res - ret_comp);
4694 : : }
4695 [ # # # # ]: 0 : if (ret_comp < n_res && priv->quota_ctx.sq)
4696 : 0 : ret_comp += mlx5_aso_pull_completion(&priv->quota_ctx.sq[queue],
4697 : 0 : &res[ret_comp],
4698 : 0 : n_res - ret_comp);
4699 [ # # ]: 0 : for (i = 0; i < ret_comp; i++) {
4700 : 0 : struct mlx5_hw_q_job *job = (struct mlx5_hw_q_job *)res[i].user_data;
4701 : :
4702 : : /* Restore user data. */
4703 : 0 : res[i].user_data = job->user_data;
4704 [ # # ]: 0 : if (job->indirect_type == MLX5_HW_INDIRECT_TYPE_LEGACY)
4705 : : flow_hw_pull_legacy_indirect_comp(dev, job, queue);
4706 : : /*
4707 : : * Current PMD supports 2 indirect action list types - MIRROR and REFORMAT.
4708 : : * These indirect list types do not post WQE to create action.
4709 : : * Future indirect list types that do post WQE will add
4710 : : * completion handlers here.
4711 : : */
4712 : : flow_hw_job_put(priv, job, queue);
4713 : : }
4714 : 0 : return ret_comp;
4715 : : }
4716 : :
4717 : : static __rte_always_inline void
4718 : : hw_cmpl_flow_update_or_destroy(struct rte_eth_dev *dev,
4719 : : struct rte_flow_hw *flow,
4720 : : uint32_t queue, struct rte_flow_error *error)
4721 : : {
4722 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4723 : 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
4724 : 0 : struct rte_flow_template_table *table = flow->table;
4725 : : /* Release the original resource index in case of update. */
4726 : 0 : uint32_t res_idx = flow->res_idx;
4727 : :
4728 [ # # ]: 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAGS_ALL) {
4729 [ # # # # : 0 : struct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
# # ]
4730 : :
4731 [ # # # # : 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_FATE_JUMP)
# # ]
4732 : 0 : flow_hw_jump_release(dev, flow->jump);
4733 [ # # # # : 0 : else if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_FATE_HRXQ)
# # ]
4734 : 0 : mlx5_hrxq_obj_release(dev, flow->hrxq);
4735 [ # # # # : 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_CNT_ID)
# # ]
4736 : 0 : flow_hw_age_count_release(priv, queue, flow, error);
4737 [ # # # # : 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_MTR_ID)
# # ]
4738 : 0 : mlx5_ipool_free(pool->idx_pool, aux->orig.mtr_id);
4739 [ # # # # : 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_UPD_FLOW) {
# # ]
4740 : : struct rte_flow_hw *upd_flow = &aux->upd_flow;
4741 : :
4742 : : rte_memcpy(flow, upd_flow, offsetof(struct rte_flow_hw, rule));
4743 : 0 : aux->orig = aux->upd;
4744 : 0 : flow->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_CREATE;
4745 [ # # # # : 0 : if (!flow->nt_rule && table->resource)
# # # # #
# # # ]
4746 : 0 : mlx5_ipool_free(table->resource, res_idx);
4747 : : }
4748 : : }
4749 [ # # # # : 0 : if (flow->operation_type == MLX5_FLOW_HW_FLOW_OP_TYPE_DESTROY ||
# # ]
4750 : : flow->operation_type == MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_DESTROY) {
4751 [ # # # # : 0 : if (!flow->nt_rule) {
# # ]
4752 [ # # # # : 0 : if (table->resource)
# # ]
4753 : 0 : mlx5_ipool_free(table->resource, res_idx);
4754 [ # # # # : 0 : if (table->flow_pool)
# # ]
4755 : 0 : mlx5_ipool_free(table->flow_pool, flow->idx);
4756 : : }
4757 : : }
4758 : : }
4759 : :
4760 : : static __rte_always_inline void
4761 : : hw_cmpl_resizable_tbl(struct rte_eth_dev *dev,
4762 : : struct rte_flow_hw *flow,
4763 : : uint32_t queue, enum rte_flow_op_status status,
4764 : : struct rte_flow_error *error)
4765 : : {
4766 : 0 : struct rte_flow_template_table *table = flow->table;
4767 : 0 : struct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
4768 : 0 : uint32_t selector = aux->matcher_selector;
4769 : 0 : uint32_t other_selector = (selector + 1) & 1;
4770 : :
4771 : : MLX5_ASSERT(flow->flags & MLX5_FLOW_HW_FLOW_FLAG_MATCHER_SELECTOR);
4772 [ # # # # ]: 0 : switch (flow->operation_type) {
4773 : 0 : case MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_CREATE:
4774 : 0 : rte_atomic_fetch_add_explicit
4775 : : (&table->matcher_info[selector].refcnt, 1,
4776 : : rte_memory_order_relaxed);
4777 : 0 : break;
4778 : 0 : case MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_DESTROY:
4779 [ # # ]: 0 : rte_atomic_fetch_sub_explicit
4780 : : (&table->matcher_info[selector].refcnt, 1,
4781 : : rte_memory_order_relaxed);
4782 : : hw_cmpl_flow_update_or_destroy(dev, flow, queue, error);
4783 : : break;
4784 : 0 : case MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_MOVE:
4785 [ # # ]: 0 : if (status == RTE_FLOW_OP_SUCCESS) {
4786 : 0 : rte_atomic_fetch_sub_explicit
4787 : : (&table->matcher_info[selector].refcnt, 1,
4788 : : rte_memory_order_relaxed);
4789 : 0 : rte_atomic_fetch_add_explicit
4790 : : (&table->matcher_info[other_selector].refcnt, 1,
4791 : : rte_memory_order_relaxed);
4792 : 0 : aux->matcher_selector = other_selector;
4793 : : }
4794 : : break;
4795 : : default:
4796 : : break;
4797 : : }
4798 : : }
4799 : :
4800 : : /**
4801 : : * Pull the enqueued flows.
4802 : : *
4803 : : * For flows enqueued from creation/destruction, the status should be
4804 : : * checked from the dequeue result.
4805 : : *
4806 : : * @param[in] dev
4807 : : * Pointer to the rte_eth_dev structure.
4808 : : * @param[in] queue
4809 : : * The queue to pull the result.
4810 : : * @param[in/out] res
4811 : : * Array to save the results.
4812 : : * @param[in] n_res
4813 : : * Available result with the array.
4814 : : * @param[out] error
4815 : : * Pointer to error structure.
4816 : : *
4817 : : * @return
4818 : : * Result number on success, negative value otherwise and rte_errno is set.
4819 : : */
4820 : : static int
4821 : 0 : flow_hw_pull(struct rte_eth_dev *dev,
4822 : : uint32_t queue,
4823 : : struct rte_flow_op_result res[],
4824 : : uint16_t n_res,
4825 : : struct rte_flow_error *error)
4826 : : {
4827 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4828 : : int ret, i;
4829 : :
4830 : : /* 1. Pull the flow completion. */
4831 : 0 : ret = mlx5dr_send_queue_poll(priv->dr_ctx, queue, res, n_res);
4832 [ # # ]: 0 : if (ret < 0)
4833 : 0 : return rte_flow_error_set(error, rte_errno,
4834 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4835 : : "fail to query flow queue");
4836 [ # # ]: 0 : for (i = 0; i < ret; i++) {
4837 : 0 : struct rte_flow_hw *flow = res[i].user_data;
4838 : :
4839 : : /* Restore user data. */
4840 : 0 : res[i].user_data = flow->user_data;
4841 [ # # # ]: 0 : switch (flow->operation_type) {
4842 : : case MLX5_FLOW_HW_FLOW_OP_TYPE_DESTROY:
4843 : : case MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE:
4844 : : hw_cmpl_flow_update_or_destroy(dev, flow, queue, error);
4845 : : break;
4846 : 0 : case MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_CREATE:
4847 : : case MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_DESTROY:
4848 : : case MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_MOVE:
4849 [ # # ]: 0 : hw_cmpl_resizable_tbl(dev, flow, queue, res[i].status, error);
4850 : : break;
4851 : : default:
4852 : : break;
4853 : : }
4854 : : flow_hw_q_dec_flow_ops(priv, queue);
4855 : : }
4856 : : /* 2. Pull indirect action comp. */
4857 [ # # ]: 0 : if (ret < n_res)
4858 : 0 : ret += __flow_hw_pull_indir_action_comp(dev, queue, &res[ret],
4859 : 0 : n_res - ret);
4860 [ # # ]: 0 : if (ret < n_res)
4861 : 0 : ret += mlx5_hw_pull_flow_transfer_comp(dev, queue, &res[ret],
4862 [ # # ]: 0 : n_res - ret);
4863 : :
4864 : : return ret;
4865 : : }
4866 : :
4867 : : static uint32_t
4868 : 0 : mlx5_hw_push_queue(struct rte_ring *pending_q, struct rte_ring *cmpl_q)
4869 : : {
4870 : 0 : void *job = NULL;
4871 : : uint32_t i, size = rte_ring_count(pending_q);
4872 : :
4873 [ # # ]: 0 : for (i = 0; i < size; i++) {
4874 : : rte_ring_dequeue(pending_q, &job);
4875 [ # # # # : 0 : rte_ring_enqueue(cmpl_q, job);
# ]
4876 : : }
4877 : 0 : return size;
4878 : : }
4879 : :
4880 : : static inline uint32_t
4881 : 0 : __flow_hw_push_action(struct rte_eth_dev *dev,
4882 : : uint32_t queue)
4883 : : {
4884 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4885 : 0 : struct mlx5_hw_q *hw_q = &priv->hw_q[queue];
4886 : :
4887 : 0 : mlx5_hw_push_queue(hw_q->indir_iq, hw_q->indir_cq);
4888 [ # # # # ]: 0 : if (hw_q->flow_transfer_pending != NULL && hw_q->flow_transfer_completed != NULL)
4889 : 0 : mlx5_hw_push_queue(hw_q->flow_transfer_pending,
4890 : : hw_q->flow_transfer_completed);
4891 [ # # ]: 0 : if (!priv->shared_host) {
4892 [ # # ]: 0 : if (priv->hws_ctpool)
4893 : 0 : mlx5_aso_push_wqe(priv->sh,
4894 : 0 : &priv->ct_mng->aso_sqs[queue]);
4895 [ # # ]: 0 : if (priv->hws_mpool)
4896 : 0 : mlx5_aso_push_wqe(priv->sh,
4897 : 0 : &priv->hws_mpool->sq[queue]);
4898 : : }
4899 : 0 : return flow_hw_q_pending(priv, queue);
4900 : : }
4901 : :
4902 : : static int
4903 : 0 : __flow_hw_push(struct rte_eth_dev *dev,
4904 : : uint32_t queue,
4905 : : struct rte_flow_error *error)
4906 : : {
4907 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4908 : : int ret, num;
4909 : :
4910 : 0 : num = __flow_hw_push_action(dev, queue);
4911 : 0 : ret = mlx5dr_send_queue_action(priv->dr_ctx, queue,
4912 : : MLX5DR_SEND_QUEUE_ACTION_DRAIN_ASYNC);
4913 [ # # ]: 0 : if (ret) {
4914 : 0 : rte_flow_error_set(error, rte_errno,
4915 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4916 : : "fail to push flows");
4917 : 0 : return ret;
4918 : : }
4919 : : return num;
4920 : : }
4921 : :
4922 : : /**
4923 : : * Push the enqueued flows to HW.
4924 : : *
4925 : : * Force apply all the enqueued flows to the HW.
4926 : : *
4927 : : * @param[in] dev
4928 : : * Pointer to the rte_eth_dev structure.
4929 : : * @param[in] queue
4930 : : * The queue to push the flow.
4931 : : * @param[out] error
4932 : : * Pointer to error structure.
4933 : : *
4934 : : * @return
4935 : : * 0 on success, negative value otherwise and rte_errno is set.
4936 : : */
4937 : : static int
4938 : 0 : flow_hw_push(struct rte_eth_dev *dev,
4939 : : uint32_t queue, struct rte_flow_error *error)
4940 : : {
4941 : 0 : int ret = __flow_hw_push(dev, queue, error);
4942 : :
4943 : 0 : return ret >= 0 ? 0 : ret;
4944 : : }
4945 : :
4946 : : /**
4947 : : * Drain the enqueued flows' completion.
4948 : : *
4949 : : * @param[in] dev
4950 : : * Pointer to the rte_eth_dev structure.
4951 : : * @param[in] queue
4952 : : * The queue to pull the flow.
4953 : : * @param[out] error
4954 : : * Pointer to error structure.
4955 : : *
4956 : : * @return
4957 : : * 0 on success, negative value otherwise and rte_errno is set.
4958 : : */
4959 : : static int
4960 : 0 : __flow_hw_pull_comp(struct rte_eth_dev *dev,
4961 : : uint32_t queue, struct rte_flow_error *error)
4962 : : {
4963 : : struct rte_flow_op_result comp[BURST_THR];
4964 : : int ret, i, empty_loop = 0;
4965 : : uint32_t pending_rules;
4966 : :
4967 : 0 : ret = __flow_hw_push(dev, queue, error);
4968 [ # # ]: 0 : if (ret < 0)
4969 : : return ret;
4970 : 0 : pending_rules = ret;
4971 [ # # ]: 0 : while (pending_rules) {
4972 : 0 : ret = flow_hw_pull(dev, queue, comp, BURST_THR, error);
4973 [ # # ]: 0 : if (ret < 0)
4974 : : return -1;
4975 [ # # ]: 0 : if (!ret) {
4976 : 0 : rte_delay_us_sleep(MLX5_ASO_WQE_CQE_RESPONSE_DELAY);
4977 [ # # ]: 0 : if (++empty_loop > 5) {
4978 : 0 : DRV_LOG(WARNING, "No available dequeue %u, quit.", pending_rules);
4979 : 0 : break;
4980 : : }
4981 : 0 : continue;
4982 : : }
4983 [ # # ]: 0 : for (i = 0; i < ret; i++) {
4984 [ # # ]: 0 : if (comp[i].status == RTE_FLOW_OP_ERROR)
4985 : 0 : DRV_LOG(WARNING, "Flow flush get error CQE.");
4986 : : }
4987 : : /*
4988 : : * Indirect **SYNC** METER_MARK and CT actions do not
4989 : : * remove completion after WQE post.
4990 : : * That implementation avoids HW timeout.
4991 : : * The completion is removed before the following WQE post.
4992 : : * However, HWS queue updates do not reflect that behaviour.
4993 : : * Therefore, during port destruction sync queue may have
4994 : : * pending completions.
4995 : : */
4996 : 0 : pending_rules -= RTE_MIN(pending_rules, (uint32_t)ret);
4997 : : empty_loop = 0;
4998 : : }
4999 : : return 0;
5000 : : }
5001 : :
5002 : : /**
5003 : : * Flush created flows.
5004 : : *
5005 : : * @param[in] dev
5006 : : * Pointer to the rte_eth_dev structure.
5007 : : * @param[out] error
5008 : : * Pointer to error structure.
5009 : : *
5010 : : * @return
5011 : : * 0 on success, negative value otherwise and rte_errno is set.
5012 : : */
5013 : : int
5014 : 0 : mlx5_flow_hw_q_flow_flush(struct rte_eth_dev *dev,
5015 : : struct rte_flow_error *error)
5016 : : {
5017 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
5018 : 0 : struct mlx5_hw_q *hw_q = &priv->hw_q[MLX5_DEFAULT_FLUSH_QUEUE];
5019 : : struct rte_flow_template_table *tbl;
5020 : : struct rte_flow_hw *flow;
5021 : 0 : struct rte_flow_op_attr attr = {
5022 : : .postpone = 0,
5023 : : };
5024 : : uint32_t pending_rules = 0;
5025 : : uint32_t queue;
5026 : : uint32_t fidx;
5027 : :
5028 : : /*
5029 : : * Ensure to push and dequeue all the enqueued flow
5030 : : * creation/destruction jobs in case user forgot to
5031 : : * dequeue. Or the enqueued created flows will be
5032 : : * leaked. The forgotten dequeues would also cause
5033 : : * flow flush get extra CQEs as expected and pending_rules
5034 : : * be minus value.
5035 : : */
5036 [ # # ]: 0 : for (queue = 0; queue < priv->nb_queue; queue++) {
5037 [ # # ]: 0 : if (__flow_hw_pull_comp(dev, queue, error))
5038 : : return -1;
5039 : : }
5040 : : /* Flush flow per-table from MLX5_DEFAULT_FLUSH_QUEUE. */
5041 [ # # ]: 0 : LIST_FOREACH(tbl, &priv->flow_hw_tbl, next) {
5042 [ # # ]: 0 : if (!tbl->cfg.external)
5043 : 0 : continue;
5044 [ # # ]: 0 : MLX5_IPOOL_FOREACH(tbl->flow_pool, fidx, flow) {
5045 [ # # ]: 0 : if (flow_hw_async_flow_destroy(dev,
5046 : : MLX5_DEFAULT_FLUSH_QUEUE,
5047 : : &attr,
5048 : : (struct rte_flow *)flow,
5049 : : NULL,
5050 : : error))
5051 : : return -1;
5052 : 0 : pending_rules++;
5053 : : /* Drain completion with queue size. */
5054 [ # # ]: 0 : if (pending_rules >= hw_q->size) {
5055 [ # # ]: 0 : if (__flow_hw_pull_comp(dev,
5056 : : MLX5_DEFAULT_FLUSH_QUEUE,
5057 : : error))
5058 : : return -1;
5059 : : pending_rules = 0;
5060 : : }
5061 : : }
5062 : : }
5063 : : /* Drain left completion. */
5064 [ # # # # ]: 0 : if (pending_rules &&
5065 : 0 : __flow_hw_pull_comp(dev, MLX5_DEFAULT_FLUSH_QUEUE, error))
5066 : 0 : return -1;
5067 : : return 0;
5068 : : }
5069 : :
5070 : : static int
5071 : 0 : mlx5_tbl_multi_pattern_process(struct rte_eth_dev *dev,
5072 : : struct rte_flow_template_table *tbl,
5073 : : struct mlx5_multi_pattern_segment *segment,
5074 : : uint32_t bulk_size,
5075 : : struct rte_flow_error *error)
5076 : : {
5077 : : int ret = 0;
5078 : : uint32_t i;
5079 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
5080 : : bool unified_fdb = is_unified_fdb(priv);
5081 : : struct mlx5_tbl_multi_pattern_ctx *mpctx = &tbl->mpctx;
5082 : : const struct rte_flow_template_table_attr *table_attr = &tbl->cfg.attr;
5083 : 0 : const struct rte_flow_attr *attr = &table_attr->flow_attr;
5084 : : enum mlx5dr_table_type type =
5085 : 0 : get_mlx5dr_table_type(attr, table_attr->specialize, unified_fdb);
5086 : 0 : uint32_t flags = mlx5_hw_act_flag[!!attr->group][type];
5087 : : struct mlx5dr_action *dr_action = NULL;
5088 : :
5089 [ # # ]: 0 : for (i = 0; i < MLX5_MULTIPATTERN_ENCAP_NUM; i++) {
5090 [ # # ]: 0 : typeof(mpctx->reformat[0]) *reformat = mpctx->reformat + i;
5091 : : enum mlx5dr_action_type reformat_type =
5092 : : mlx5_multi_pattern_reformat_index_to_type(i);
5093 : :
5094 [ # # ]: 0 : if (!reformat->elements_num)
5095 : 0 : continue;
5096 : : dr_action = reformat_type == MLX5DR_ACTION_TYP_INSERT_HEADER ?
5097 : : mlx5dr_action_create_insert_header
5098 : : (priv->dr_ctx, reformat->elements_num,
5099 : : reformat->insert_hdr, bulk_size, flags) :
5100 : 0 : mlx5dr_action_create_reformat
5101 : : (priv->dr_ctx, reformat_type, reformat->elements_num,
5102 : 0 : reformat->reformat_hdr, bulk_size, flags);
5103 [ # # ]: 0 : if (!dr_action) {
5104 : 0 : ret = rte_flow_error_set(error, rte_errno,
5105 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5106 : : NULL,
5107 : : "failed to create multi-pattern encap action");
5108 : 0 : goto error;
5109 : : }
5110 : 0 : segment->reformat_action[i] = dr_action;
5111 : : }
5112 [ # # ]: 0 : if (mpctx->mh.elements_num) {
5113 : : typeof(mpctx->mh) *mh = &mpctx->mh;
5114 : 0 : dr_action = mlx5dr_action_create_modify_header
5115 : 0 : (priv->dr_ctx, mpctx->mh.elements_num, mh->pattern,
5116 : : bulk_size, flags);
5117 [ # # ]: 0 : if (!dr_action) {
5118 : 0 : ret = rte_flow_error_set(error, rte_errno,
5119 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5120 : : NULL, "failed to create multi-pattern header modify action");
5121 : 0 : goto error;
5122 : : }
5123 : 0 : segment->mhdr_action = dr_action;
5124 : : }
5125 [ # # ]: 0 : if (dr_action) {
5126 : 0 : segment->capacity = RTE_BIT32(bulk_size);
5127 [ # # ]: 0 : if (segment != &mpctx->segments[MLX5_MAX_TABLE_RESIZE_NUM - 1])
5128 : 0 : segment[1].head_index = segment->head_index + segment->capacity;
5129 : : }
5130 : : return 0;
5131 : 0 : error:
5132 : 0 : mlx5_destroy_multi_pattern_segment(segment);
5133 : 0 : return ret;
5134 : : }
5135 : :
5136 : : static int
5137 : 0 : mlx5_hw_build_template_table(struct rte_eth_dev *dev,
5138 : : uint8_t nb_action_templates,
5139 : : struct rte_flow_actions_template *action_templates[],
5140 : : struct mlx5dr_action_template *at[],
5141 : : struct rte_flow_template_table *tbl,
5142 : : struct rte_flow_error *error)
5143 : : {
5144 : : int ret;
5145 : : uint8_t i;
5146 : :
5147 [ # # ]: 0 : for (i = 0; i < nb_action_templates; i++) {
5148 : 0 : uint32_t refcnt = rte_atomic_fetch_add_explicit(&action_templates[i]->refcnt, 1,
5149 : : rte_memory_order_relaxed) + 1;
5150 : :
5151 [ # # ]: 0 : if (refcnt <= 1) {
5152 : 0 : rte_flow_error_set(error, EINVAL,
5153 : : RTE_FLOW_ERROR_TYPE_ACTION,
5154 : : &action_templates[i], "invalid AT refcount");
5155 : 0 : goto at_error;
5156 : : }
5157 : 0 : at[i] = action_templates[i]->tmpl;
5158 : 0 : tbl->ats[i].action_template = action_templates[i];
5159 : 0 : LIST_INIT(&tbl->ats[i].acts.act_list);
5160 : : /* do NOT translate table action if `dev` was not started */
5161 [ # # ]: 0 : if (!dev->data->dev_started)
5162 : 0 : continue;
5163 : 0 : ret = flow_hw_translate_actions_template(dev, &tbl->cfg,
5164 : : &tbl->ats[i].acts,
5165 : : action_templates[i],
5166 : : &tbl->mpctx, error);
5167 [ # # ]: 0 : if (ret) {
5168 : 0 : i++;
5169 : 0 : goto at_error;
5170 : : }
5171 : 0 : flow_hw_populate_rule_acts_caches(dev, tbl, i);
5172 : : }
5173 [ # # ]: 0 : tbl->nb_action_templates = nb_action_templates;
5174 [ # # ]: 0 : if (mlx5_is_multi_pattern_active(&tbl->mpctx)) {
5175 [ # # ]: 0 : ret = mlx5_tbl_multi_pattern_process(dev, tbl,
5176 : : &tbl->mpctx.segments[0],
5177 : : rte_log2_u32(tbl->cfg.attr.nb_flows),
5178 : : error);
5179 [ # # ]: 0 : if (ret)
5180 : 0 : goto at_error;
5181 : : }
5182 : : return 0;
5183 : :
5184 : : at_error:
5185 [ # # ]: 0 : while (i--) {
5186 : 0 : __flow_hw_action_template_destroy(dev, &tbl->ats[i].acts);
5187 : 0 : rte_atomic_fetch_sub_explicit(&action_templates[i]->refcnt,
5188 : : 1, rte_memory_order_relaxed);
5189 : : }
5190 : 0 : return rte_errno;
5191 : : }
5192 : :
5193 : : static bool
5194 : : flow_hw_validate_template_domain(const struct rte_flow_attr *table_attr,
5195 : : uint32_t ingress, uint32_t egress, uint32_t transfer)
5196 : : {
5197 : 0 : if (table_attr->ingress)
5198 : : return ingress != 0;
5199 [ # # # # ]: 0 : else if (table_attr->egress)
5200 : : return egress != 0;
5201 : : else
5202 : 0 : return transfer;
5203 : : }
5204 : :
5205 : : static bool
5206 : : flow_hw_validate_table_domain(const struct rte_flow_attr *table_attr)
5207 : : {
5208 : 0 : return table_attr->ingress + table_attr->egress + table_attr->transfer
5209 : : == 1;
5210 : : }
5211 : :
5212 : : /**
5213 : : * Create flow table.
5214 : : *
5215 : : * The input item and action templates will be binded to the table.
5216 : : * Flow memory will also be allocated. Matcher will be created based
5217 : : * on the item template. Action will be translated to the dedicated
5218 : : * DR action if possible.
5219 : : *
5220 : : * @param[in] dev
5221 : : * Pointer to the rte_eth_dev structure.
5222 : : * @param[in] table_cfg
5223 : : * Pointer to the table configuration.
5224 : : * @param[in] item_templates
5225 : : * Item template array to be binded to the table.
5226 : : * @param[in] nb_item_templates
5227 : : * Number of item template.
5228 : : * @param[in] action_templates
5229 : : * Action template array to be binded to the table.
5230 : : * @param[in] nb_action_templates
5231 : : * Number of action template.
5232 : : * @param[out] error
5233 : : * Pointer to error structure.
5234 : : *
5235 : : * @return
5236 : : * Table on success, NULL otherwise and rte_errno is set.
5237 : : */
5238 : : static struct rte_flow_template_table *
5239 : 0 : flow_hw_table_create(struct rte_eth_dev *dev,
5240 : : const struct mlx5_flow_template_table_cfg *table_cfg,
5241 : : struct rte_flow_pattern_template *item_templates[],
5242 : : uint8_t nb_item_templates,
5243 : : struct rte_flow_actions_template *action_templates[],
5244 : : uint8_t nb_action_templates,
5245 : : struct rte_flow_error *error)
5246 : : {
5247 : 0 : struct rte_flow_error sub_error = {
5248 : : .type = RTE_FLOW_ERROR_TYPE_NONE,
5249 : : .cause = NULL,
5250 : : .message = NULL,
5251 : : };
5252 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
5253 : : bool unified_fdb = is_unified_fdb(priv);
5254 : 0 : struct mlx5dr_matcher_attr matcher_attr = {0};
5255 : 0 : struct mlx5dr_action_jump_to_matcher_attr jump_attr = {
5256 : : .type = MLX5DR_ACTION_JUMP_TO_MATCHER_BY_INDEX,
5257 : : .matcher = NULL,
5258 : : };
5259 : : struct rte_flow_template_table *tbl = NULL;
5260 : : struct mlx5_flow_group *grp;
5261 : : struct mlx5dr_match_template *mt[MLX5_HW_TBL_MAX_ITEM_TEMPLATE];
5262 : : struct mlx5dr_action_template *at[MLX5_HW_TBL_MAX_ACTION_TEMPLATE];
5263 : 0 : const struct rte_flow_template_table_attr *attr = &table_cfg->attr;
5264 : 0 : struct rte_flow_attr flow_attr = attr->flow_attr;
5265 : 0 : uint32_t specialize = table_cfg->attr.specialize;
5266 : 0 : struct mlx5_flow_cb_ctx ctx = {
5267 : : .dev = dev,
5268 : : .error = &sub_error,
5269 : : .data = &flow_attr,
5270 : : .data2 = &specialize,
5271 : : };
5272 : 0 : struct mlx5_indexed_pool_config cfg = {
5273 : : .trunk_size = 1 << 12,
5274 : : .per_core_cache = 1 << 13,
5275 : : .need_lock = 1,
5276 : 0 : .release_mem_en = !!priv->sh->config.reclaim_mode,
5277 : : .malloc = mlx5_malloc,
5278 : : .free = mlx5_free,
5279 : : .type = "mlx5_hw_table_flow",
5280 : : };
5281 : : struct mlx5_list_entry *ge;
5282 : : uint32_t i = 0, max_tpl = MLX5_HW_TBL_MAX_ITEM_TEMPLATE;
5283 [ # # ]: 0 : uint32_t nb_flows = rte_align32pow2(attr->nb_flows);
5284 : 0 : bool port_started = !!dev->data->dev_started;
5285 : : bool rpool_needed;
5286 : : size_t tbl_mem_size;
5287 : : enum mlx5dr_table_type table_type;
5288 : : int err;
5289 : :
5290 [ # # ]: 0 : if (!flow_hw_validate_table_domain(&attr->flow_attr)) {
5291 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ATTR,
5292 : : NULL, "invalid table domain attributes");
5293 : 0 : return NULL;
5294 : : }
5295 [ # # ]: 0 : for (i = 0; i < nb_item_templates; i++) {
5296 : : const struct rte_flow_pattern_template_attr *pt_attr =
5297 : 0 : &item_templates[i]->attr;
5298 : : bool match = flow_hw_validate_template_domain(&attr->flow_attr,
5299 : 0 : pt_attr->ingress,
5300 : 0 : pt_attr->egress,
5301 [ # # ]: 0 : pt_attr->transfer);
5302 [ # # ]: 0 : if (!match) {
5303 : 0 : rte_flow_error_set(error, EINVAL,
5304 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5305 : : NULL, "pattern template domain does not match table");
5306 : 0 : return NULL;
5307 : : }
5308 [ # # # # ]: 0 : if (item_templates[i]->item_flags & MLX5_FLOW_LAYER_ECPRI &&
5309 : 0 : !mlx5_flex_parser_ecpri_exist(dev))
5310 [ # # ]: 0 : if (mlx5_flex_parser_ecpri_alloc(dev)) {
5311 : 0 : rte_flow_error_set(error, EIO,
5312 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5313 : : NULL,
5314 : : "failed to create Flex parser "
5315 : : "profile for ECPRI");
5316 : 0 : goto error;
5317 : : }
5318 : : }
5319 [ # # ]: 0 : for (i = 0; i < nb_action_templates; i++) {
5320 : 0 : const struct rte_flow_actions_template *at = action_templates[i];
5321 : : bool match = flow_hw_validate_template_domain(&attr->flow_attr,
5322 : 0 : at->attr.ingress,
5323 : 0 : at->attr.egress,
5324 [ # # ]: 0 : at->attr.transfer);
5325 [ # # ]: 0 : if (!match) {
5326 : 0 : rte_flow_error_set(error, EINVAL,
5327 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5328 : : NULL, "action template domain does not match table");
5329 : 0 : return NULL;
5330 : : }
5331 : : }
5332 : : /* HWS layer accepts only 1 item template with root table. */
5333 [ # # ]: 0 : if (!attr->flow_attr.group)
5334 : : max_tpl = 1;
5335 : 0 : cfg.max_idx = nb_flows;
5336 [ # # ]: 0 : cfg.size = !rte_flow_template_table_resizable(dev->data->port_id, attr) ?
5337 : : mlx5_flow_hw_entry_size() :
5338 : : mlx5_flow_hw_auxed_entry_size();
5339 : : /* For table has very limited flows, disable cache. */
5340 [ # # ]: 0 : if (nb_flows < cfg.trunk_size) {
5341 : 0 : cfg.per_core_cache = 0;
5342 : 0 : cfg.trunk_size = nb_flows;
5343 [ # # ]: 0 : } else if (nb_flows <= MLX5_HW_IPOOL_SIZE_THRESHOLD) {
5344 : 0 : cfg.per_core_cache = MLX5_HW_IPOOL_CACHE_MIN;
5345 : : }
5346 : : /* Check if we requires too many templates. */
5347 [ # # # # ]: 0 : if (nb_item_templates > max_tpl ||
5348 : : nb_action_templates > MLX5_HW_TBL_MAX_ACTION_TEMPLATE) {
5349 : 0 : rte_errno = EINVAL;
5350 : 0 : goto error;
5351 : : }
5352 : : /*
5353 : : * Amount of memory required for rte_flow_template_table struct:
5354 : : * - Size of the struct itself.
5355 : : * - VLA of DR rule action containers at the end =
5356 : : * number of actions templates * number of queues * size of DR rule actions container.
5357 : : */
5358 : : tbl_mem_size = sizeof(*tbl);
5359 : 0 : tbl_mem_size += nb_action_templates * priv->nb_queue * sizeof(tbl->rule_acts[0]);
5360 : : /* Allocate the table memory. */
5361 : 0 : tbl = mlx5_malloc(MLX5_MEM_ZERO, tbl_mem_size, RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
5362 [ # # ]: 0 : if (!tbl)
5363 : 0 : goto error;
5364 : 0 : tbl->cfg = *table_cfg;
5365 : : /* Allocate flow indexed pool. */
5366 : 0 : tbl->flow_pool = mlx5_ipool_create(&cfg);
5367 [ # # ]: 0 : if (!tbl->flow_pool)
5368 : 0 : goto error;
5369 : : /* Allocate table of auxiliary flow rule structs. */
5370 : 0 : tbl->flow_aux = mlx5_malloc(MLX5_MEM_ZERO, sizeof(struct rte_flow_hw_aux) * nb_flows,
5371 : : RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
5372 [ # # ]: 0 : if (!tbl->flow_aux)
5373 : 0 : goto error;
5374 : : /* Register the flow group. */
5375 : 0 : ge = mlx5_hlist_register(priv->sh->groups, attr->flow_attr.group, &ctx);
5376 [ # # ]: 0 : if (!ge)
5377 : 0 : goto error;
5378 : : grp = container_of(ge, struct mlx5_flow_group, entry);
5379 : : /* Verify unified fdb sub domains consistency */
5380 : 0 : table_type = get_mlx5dr_table_type(&flow_attr, specialize, unified_fdb);
5381 [ # # ]: 0 : if (table_type != grp->type) {
5382 : 0 : DRV_LOG(ERR,
5383 : : "Group %u table type mismatch: group type is fixed on first use. "
5384 : : "This table requires %s but group was first used as %s. "
5385 : : "Create tables with transfer wire_orig or vf_orig before tables jumping to it.",
5386 : : grp->group_id,
5387 : : mlx5dr_table_type_name(table_type),
5388 : : mlx5dr_table_type_name(grp->type));
5389 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5390 : : NULL,
5391 : : "group table type mismatch: type is fixed on first use; "
5392 : : "create transfer wire_orig/vf_orig tables before tables jumping to it");
5393 : 0 : rte_errno = EINVAL;
5394 : 0 : goto error;
5395 : : }
5396 : 0 : tbl->grp = grp;
5397 : : /* Prepare matcher information. */
5398 : 0 : matcher_attr.resizable = !!rte_flow_template_table_resizable
5399 : 0 : (dev->data->port_id, &table_cfg->attr);
5400 : 0 : matcher_attr.optimize_flow_src = MLX5DR_MATCHER_FLOW_SRC_ANY;
5401 : 0 : matcher_attr.priority = attr->flow_attr.priority;
5402 : 0 : matcher_attr.optimize_using_rule_idx = true;
5403 : 0 : matcher_attr.mode = MLX5DR_MATCHER_RESOURCE_MODE_RULE;
5404 [ # # ]: 0 : matcher_attr.insert_mode = flow_hw_matcher_insert_mode_get(attr->insertion_type);
5405 [ # # ]: 0 : if (matcher_attr.insert_mode == MLX5DR_MATCHER_INSERT_BY_INDEX) {
5406 [ # # ]: 0 : if (attr->insertion_type == RTE_FLOW_TABLE_INSERTION_TYPE_INDEX_WITH_PATTERN) {
5407 : 0 : matcher_attr.isolated = true;
5408 : 0 : matcher_attr.match_mode = MLX5DR_MATCHER_MATCH_MODE_DEFAULT;
5409 : : } else {
5410 : 0 : matcher_attr.isolated = false;
5411 : 0 : matcher_attr.match_mode = MLX5DR_MATCHER_MATCH_MODE_ALWAYS_HIT;
5412 : : }
5413 : : }
5414 [ # # ]: 0 : if (attr->hash_func == RTE_FLOW_TABLE_HASH_FUNC_CRC16) {
5415 : 0 : DRV_LOG(ERR, "16-bit checksum hash type is not supported");
5416 : 0 : rte_errno = ENOTSUP;
5417 : 0 : goto it_error;
5418 : : }
5419 [ # # ]: 0 : matcher_attr.distribute_mode = flow_hw_matcher_distribute_mode_get(attr->hash_func);
5420 : 0 : matcher_attr.rule.num_log = rte_log2_u32(nb_flows);
5421 : : /* Parse hints information. */
5422 [ # # ]: 0 : if (attr->specialize) {
5423 : : uint32_t val = RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_WIRE_ORIG |
5424 : : RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_VPORT_ORIG;
5425 : :
5426 [ # # ]: 0 : if ((attr->specialize & val) == val) {
5427 : 0 : DRV_LOG(ERR, "Invalid hint value %x",
5428 : : attr->specialize);
5429 : 0 : rte_errno = EINVAL;
5430 : 0 : goto it_error;
5431 : : }
5432 [ # # ]: 0 : if (attr->specialize &
5433 : : RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_WIRE_ORIG) {
5434 : 0 : matcher_attr.optimize_flow_src =
5435 : : MLX5DR_MATCHER_FLOW_SRC_WIRE;
5436 [ # # ]: 0 : } else if (attr->specialize &
5437 : : RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_VPORT_ORIG) {
5438 : 0 : matcher_attr.optimize_flow_src =
5439 : : MLX5DR_MATCHER_FLOW_SRC_VPORT;
5440 : : }
5441 : : }
5442 : : /* Build the item template. */
5443 [ # # ]: 0 : for (i = 0; i < nb_item_templates; i++) {
5444 : : uint32_t ret;
5445 : :
5446 [ # # # # ]: 0 : if ((flow_attr.ingress && !item_templates[i]->attr.ingress) ||
5447 [ # # # # ]: 0 : (flow_attr.egress && !item_templates[i]->attr.egress) ||
5448 [ # # # # ]: 0 : (flow_attr.transfer && !item_templates[i]->attr.transfer)) {
5449 : 0 : DRV_LOG(ERR, "pattern template and template table attribute mismatch");
5450 : 0 : rte_errno = EINVAL;
5451 : 0 : goto it_error;
5452 : : }
5453 [ # # ]: 0 : if (item_templates[i]->item_flags & MLX5_FLOW_ITEM_COMPARE)
5454 : 0 : matcher_attr.mode = MLX5DR_MATCHER_RESOURCE_MODE_HTABLE;
5455 : 0 : ret = rte_atomic_fetch_add_explicit(&item_templates[i]->refcnt, 1,
5456 : : rte_memory_order_relaxed) + 1;
5457 [ # # ]: 0 : if (ret <= 1) {
5458 : 0 : rte_errno = EINVAL;
5459 : 0 : goto it_error;
5460 : : }
5461 : 0 : mt[i] = item_templates[i]->mt;
5462 : 0 : tbl->its[i] = item_templates[i];
5463 : : }
5464 : 0 : tbl->nb_item_templates = nb_item_templates;
5465 : : /* Build the action template. */
5466 : 0 : err = mlx5_hw_build_template_table(dev, nb_action_templates,
5467 : : action_templates, at, tbl, &sub_error);
5468 [ # # ]: 0 : if (err) {
5469 : : i = nb_item_templates;
5470 : 0 : goto it_error;
5471 : : }
5472 : 0 : tbl->matcher_info[0].matcher = mlx5dr_matcher_create
5473 : 0 : (tbl->grp->tbl, mt, nb_item_templates, at, nb_action_templates, &matcher_attr);
5474 [ # # ]: 0 : if (!tbl->matcher_info[0].matcher)
5475 : 0 : goto at_error;
5476 : 0 : tbl->matcher_attr = matcher_attr;
5477 : 0 : tbl->type = table_type;
5478 [ # # ]: 0 : if (matcher_attr.isolated) {
5479 : 0 : jump_attr.matcher = tbl->matcher_info[0].matcher;
5480 : 0 : tbl->matcher_info[0].jump = mlx5dr_action_create_jump_to_matcher(priv->dr_ctx,
5481 : 0 : &jump_attr, mlx5_hw_act_flag[!!attr->flow_attr.group][tbl->type]);
5482 [ # # ]: 0 : if (!tbl->matcher_info[0].jump)
5483 : 0 : goto jtm_error;
5484 : : }
5485 : : /*
5486 : : * Only the matcher supports update and needs more than 1 WQE, an additional
5487 : : * index is needed. Or else the flow index can be reused.
5488 : : */
5489 [ # # # # ]: 0 : rpool_needed = mlx5dr_matcher_is_updatable(tbl->matcher_info[0].matcher) &&
5490 : 0 : mlx5dr_matcher_is_dependent(tbl->matcher_info[0].matcher);
5491 [ # # ]: 0 : if (rpool_needed) {
5492 : : /* Allocate rule indexed pool. */
5493 : 0 : cfg.size = 0;
5494 : 0 : cfg.type = "mlx5_hw_table_rule";
5495 : 0 : cfg.max_idx += priv->hw_q[0].size;
5496 : 0 : tbl->resource = mlx5_ipool_create(&cfg);
5497 [ # # ]: 0 : if (!tbl->resource)
5498 : 0 : goto res_error;
5499 : : }
5500 [ # # ]: 0 : if (port_started)
5501 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->flow_hw_tbl, tbl, next);
5502 : : else
5503 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->flow_hw_tbl_ongo, tbl, next);
5504 : : rte_rwlock_init(&tbl->matcher_replace_rwlk);
5505 : 0 : return tbl;
5506 : : res_error:
5507 [ # # ]: 0 : if (tbl->matcher_info[0].jump)
5508 : 0 : mlx5dr_action_destroy(tbl->matcher_info[0].jump);
5509 : 0 : jtm_error:
5510 [ # # ]: 0 : if (tbl->matcher_info[0].matcher)
5511 : 0 : (void)mlx5dr_matcher_destroy(tbl->matcher_info[0].matcher);
5512 : 0 : at_error:
5513 [ # # ]: 0 : for (i = 0; i < nb_action_templates; i++) {
5514 : 0 : __flow_hw_action_template_destroy(dev, &tbl->ats[i].acts);
5515 : 0 : rte_atomic_fetch_sub_explicit(&action_templates[i]->refcnt,
5516 : : 1, rte_memory_order_relaxed);
5517 : : }
5518 : : i = nb_item_templates;
5519 : : it_error:
5520 [ # # ]: 0 : while (i--)
5521 : 0 : rte_atomic_fetch_sub_explicit(&item_templates[i]->refcnt,
5522 : : 1, rte_memory_order_relaxed);
5523 : 0 : error:
5524 : 0 : err = rte_errno;
5525 [ # # ]: 0 : if (tbl) {
5526 [ # # ]: 0 : if (tbl->grp)
5527 : 0 : mlx5_hlist_unregister(priv->sh->groups,
5528 : : &tbl->grp->entry);
5529 [ # # ]: 0 : if (tbl->flow_aux)
5530 : 0 : mlx5_free(tbl->flow_aux);
5531 [ # # ]: 0 : if (tbl->flow_pool)
5532 : 0 : mlx5_ipool_destroy(tbl->flow_pool);
5533 : 0 : mlx5_free(tbl);
5534 : : }
5535 [ # # ]: 0 : if (error != NULL) {
5536 [ # # ]: 0 : if (sub_error.type == RTE_FLOW_ERROR_TYPE_NONE)
5537 : 0 : rte_flow_error_set(error, err, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5538 : : "Failed to create template table");
5539 : : else
5540 : : rte_memcpy(error, &sub_error, sizeof(sub_error));
5541 : : }
5542 : : return NULL;
5543 : : }
5544 : :
5545 : : /**
5546 : : * Update flow template table.
5547 : : *
5548 : : * @param[in] dev
5549 : : * Pointer to the rte_eth_dev structure.
5550 : : * @param[out] error
5551 : : * Pointer to error structure.
5552 : : *
5553 : : * @return
5554 : : * 0 on success, negative value otherwise and rte_errno is set.
5555 : : */
5556 : : int
5557 : 0 : mlx5_flow_hw_table_update(struct rte_eth_dev *dev,
5558 : : struct rte_flow_error *error)
5559 : : {
5560 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
5561 : : struct rte_flow_template_table *tbl;
5562 : :
5563 [ # # ]: 0 : while ((tbl = LIST_FIRST(&priv->flow_hw_tbl_ongo)) != NULL) {
5564 [ # # ]: 0 : if (flow_hw_translate_all_actions_templates(dev, tbl, error))
5565 : : return -1;
5566 [ # # ]: 0 : LIST_REMOVE(tbl, next);
5567 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->flow_hw_tbl, tbl, next);
5568 : : }
5569 : : return 0;
5570 : : }
5571 : :
5572 : : static inline int
5573 : 0 : __translate_group(struct rte_eth_dev *dev,
5574 : : const struct rte_flow_attr *flow_attr,
5575 : : bool external,
5576 : : uint32_t group,
5577 : : uint32_t *table_group,
5578 : : struct rte_flow_error *error)
5579 : : {
5580 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
5581 : 0 : struct mlx5_sh_config *config = &priv->sh->config;
5582 : :
5583 [ # # ]: 0 : if (config->dv_esw_en &&
5584 [ # # # # ]: 0 : priv->fdb_def_rule &&
5585 [ # # ]: 0 : external &&
5586 : : flow_attr->transfer) {
5587 [ # # ]: 0 : if (group > MLX5_HW_MAX_TRANSFER_GROUP)
5588 : 0 : return rte_flow_error_set(error, EINVAL,
5589 : : RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5590 : : NULL,
5591 : : "group index not supported");
5592 : 0 : *table_group = group + 1;
5593 [ # # ]: 0 : } else if (config->dv_esw_en &&
5594 [ # # ]: 0 : config->dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS &&
5595 [ # # ]: 0 : external &&
5596 : : flow_attr->egress) {
5597 : : /*
5598 : : * On E-Switch setups, default egress flow rules are inserted to allow
5599 : : * representor matching and/or preserving metadata across steering domains.
5600 : : * These flow rules are inserted in group 0 and this group is reserved by PMD
5601 : : * for these purposes.
5602 : : *
5603 : : * As a result, if representor matching or extended metadata mode is enabled,
5604 : : * group provided by the user must be incremented to avoid inserting flow rules
5605 : : * in group 0.
5606 : : */
5607 [ # # ]: 0 : if (group > MLX5_HW_MAX_EGRESS_GROUP)
5608 : 0 : return rte_flow_error_set(error, EINVAL,
5609 : : RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5610 : : NULL,
5611 : : "group index not supported");
5612 : 0 : *table_group = group + 1;
5613 [ # # # # ]: 0 : } else if (mlx5_vport_tx_metadata_passing_enabled(priv->sh) &&
5614 [ # # ]: 0 : flow_attr->egress && external) {
5615 : : /*
5616 : : * If VM cross GVMI metadata Tx was enabled, PMD creates a default
5617 : : * flow rule in the group 0 to copy metadata value.
5618 : : */
5619 [ # # ]: 0 : if (group > MLX5_HW_MAX_EGRESS_GROUP)
5620 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5621 : : NULL, "group index not supported");
5622 : 0 : *table_group = group + 1;
5623 : : } else {
5624 : 0 : *table_group = group;
5625 : : }
5626 : : return 0;
5627 : : }
5628 : :
5629 : : /**
5630 : : * Translates group index specified by the user in @p attr to internal
5631 : : * group index.
5632 : : *
5633 : : * Translation is done by incrementing group index, so group n becomes n + 1.
5634 : : *
5635 : : * @param[in] dev
5636 : : * Pointer to Ethernet device.
5637 : : * @param[in] cfg
5638 : : * Pointer to the template table configuration.
5639 : : * @param[in] group
5640 : : * Currently used group index (table group or jump destination).
5641 : : * @param[out] table_group
5642 : : * Pointer to output group index.
5643 : : * @param[out] error
5644 : : * Pointer to error structure.
5645 : : *
5646 : : * @return
5647 : : * 0 on success. Otherwise, returns negative error code, rte_errno is set
5648 : : * and error structure is filled.
5649 : : */
5650 : : static int
5651 : : flow_hw_translate_group(struct rte_eth_dev *dev,
5652 : : const struct mlx5_flow_template_table_cfg *cfg,
5653 : : uint32_t group,
5654 : : uint32_t *table_group,
5655 : : struct rte_flow_error *error)
5656 : : {
5657 : 0 : const struct rte_flow_attr *flow_attr = &cfg->attr.flow_attr;
5658 : :
5659 : 0 : return __translate_group(dev, flow_attr, cfg->external, group, table_group, error);
5660 : : }
5661 : :
5662 : : /**
5663 : : * Create flow table.
5664 : : *
5665 : : * This function is a wrapper over @ref flow_hw_table_create(), which translates parameters
5666 : : * provided by user to proper internal values.
5667 : : *
5668 : : * @param[in] dev
5669 : : * Pointer to Ethernet device.
5670 : : * @param[in] attr
5671 : : * Pointer to the table attributes.
5672 : : * @param[in] item_templates
5673 : : * Item template array to be binded to the table.
5674 : : * @param[in] nb_item_templates
5675 : : * Number of item templates.
5676 : : * @param[in] action_templates
5677 : : * Action template array to be binded to the table.
5678 : : * @param[in] nb_action_templates
5679 : : * Number of action templates.
5680 : : * @param[out] error
5681 : : * Pointer to error structure.
5682 : : *
5683 : : * @return
5684 : : * Table on success, Otherwise, returns negative error code, rte_errno is set
5685 : : * and error structure is filled.
5686 : : */
5687 : : static struct rte_flow_template_table *
5688 : 0 : flow_hw_template_table_create(struct rte_eth_dev *dev,
5689 : : const struct rte_flow_template_table_attr *attr,
5690 : : struct rte_flow_pattern_template *item_templates[],
5691 : : uint8_t nb_item_templates,
5692 : : struct rte_flow_actions_template *action_templates[],
5693 : : uint8_t nb_action_templates,
5694 : : struct rte_flow_error *error)
5695 : : {
5696 : 0 : struct mlx5_flow_template_table_cfg cfg = {
5697 : : .attr = *attr,
5698 : : .external = true,
5699 : : };
5700 : 0 : uint32_t group = attr->flow_attr.group;
5701 : :
5702 [ # # ]: 0 : if (flow_hw_translate_group(dev, &cfg, group, &cfg.attr.flow_attr.group, error))
5703 : : return NULL;
5704 [ # # # # ]: 0 : if (!cfg.attr.flow_attr.group &&
5705 : 0 : rte_flow_template_table_resizable(dev->data->port_id, attr)) {
5706 : 0 : rte_flow_error_set(error, EINVAL,
5707 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5708 : : "table cannot be resized: invalid group");
5709 : 0 : return NULL;
5710 : : }
5711 : 0 : return flow_hw_table_create(dev, &cfg, item_templates, nb_item_templates,
5712 : : action_templates, nb_action_templates, error);
5713 : : }
5714 : :
5715 : : static void
5716 : 0 : mlx5_destroy_multi_pattern_segment(struct mlx5_multi_pattern_segment *segment)
5717 : : {
5718 : : int i;
5719 : :
5720 [ # # ]: 0 : if (segment->mhdr_action)
5721 : 0 : mlx5dr_action_destroy(segment->mhdr_action);
5722 [ # # ]: 0 : for (i = 0; i < MLX5_MULTIPATTERN_ENCAP_NUM; i++) {
5723 [ # # ]: 0 : if (segment->reformat_action[i])
5724 : 0 : mlx5dr_action_destroy(segment->reformat_action[i]);
5725 : : }
5726 : 0 : segment->capacity = 0;
5727 : 0 : }
5728 : :
5729 : : static void
5730 : : flow_hw_destroy_table_multi_pattern_ctx(struct rte_flow_template_table *table)
5731 : : {
5732 : : int sx;
5733 : :
5734 [ # # ]: 0 : for (sx = 0; sx < MLX5_MAX_TABLE_RESIZE_NUM; sx++)
5735 : 0 : mlx5_destroy_multi_pattern_segment(table->mpctx.segments + sx);
5736 : : }
5737 : : /**
5738 : : * Destroy flow table.
5739 : : *
5740 : : * @param[in] dev
5741 : : * Pointer to the rte_eth_dev structure.
5742 : : * @param[in] table
5743 : : * Pointer to the table to be destroyed.
5744 : : * @param[out] error
5745 : : * Pointer to error structure.
5746 : : *
5747 : : * @return
5748 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
5749 : : */
5750 : : static int
5751 : 0 : flow_hw_table_destroy(struct rte_eth_dev *dev,
5752 : : struct rte_flow_template_table *table,
5753 : : struct rte_flow_error *error)
5754 : : {
5755 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
5756 : : int i;
5757 : 0 : uint32_t fidx = 1;
5758 : 0 : uint32_t ridx = 1;
5759 : :
5760 : : /* Build ipool allocated object bitmap. */
5761 [ # # ]: 0 : if (table->resource)
5762 : 0 : mlx5_ipool_flush_cache(table->resource);
5763 : 0 : mlx5_ipool_flush_cache(table->flow_pool);
5764 : : /* Check if ipool has allocated objects. */
5765 [ # # # # ]: 0 : if (table->refcnt ||
5766 : 0 : mlx5_ipool_get_next(table->flow_pool, &fidx) ||
5767 [ # # # # ]: 0 : (table->resource && mlx5_ipool_get_next(table->resource, &ridx))) {
5768 : 0 : DRV_LOG(WARNING, "Table %p is still in use.", (void *)table);
5769 : 0 : return rte_flow_error_set(error, EBUSY,
5770 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5771 : : NULL,
5772 : : "table is in use");
5773 : : }
5774 [ # # ]: 0 : LIST_REMOVE(table, next);
5775 [ # # ]: 0 : for (i = 0; i < table->nb_item_templates; i++)
5776 : 0 : rte_atomic_fetch_sub_explicit(&table->its[i]->refcnt,
5777 : : 1, rte_memory_order_relaxed);
5778 [ # # ]: 0 : for (i = 0; i < table->nb_action_templates; i++) {
5779 : 0 : __flow_hw_action_template_destroy(dev, &table->ats[i].acts);
5780 : 0 : rte_atomic_fetch_sub_explicit(&table->ats[i].action_template->refcnt,
5781 : : 1, rte_memory_order_relaxed);
5782 : : }
5783 : : flow_hw_destroy_table_multi_pattern_ctx(table);
5784 [ # # ]: 0 : if (table->matcher_info[0].jump)
5785 : 0 : mlx5dr_action_destroy(table->matcher_info[0].jump);
5786 [ # # ]: 0 : if (table->matcher_info[0].matcher)
5787 : 0 : mlx5dr_matcher_destroy(table->matcher_info[0].matcher);
5788 [ # # ]: 0 : if (table->matcher_info[1].jump)
5789 : 0 : mlx5dr_action_destroy(table->matcher_info[1].jump);
5790 [ # # ]: 0 : if (table->matcher_info[1].matcher)
5791 : 0 : mlx5dr_matcher_destroy(table->matcher_info[1].matcher);
5792 : 0 : mlx5_hlist_unregister(priv->sh->groups, &table->grp->entry);
5793 [ # # ]: 0 : if (table->resource)
5794 : 0 : mlx5_ipool_destroy(table->resource);
5795 : 0 : mlx5_free(table->flow_aux);
5796 : 0 : mlx5_ipool_destroy(table->flow_pool);
5797 : 0 : mlx5_free(table);
5798 : 0 : return 0;
5799 : : }
5800 : :
5801 : : /**
5802 : : * Parse group's miss actions.
5803 : : *
5804 : : * @param[in] dev
5805 : : * Pointer to the rte_eth_dev structure.
5806 : : * @param[in] cfg
5807 : : * Pointer to the table_cfg structure.
5808 : : * @param[in] actions
5809 : : * Array of actions to perform on group miss. Supported types:
5810 : : * RTE_FLOW_ACTION_TYPE_JUMP, RTE_FLOW_ACTION_TYPE_VOID, RTE_FLOW_ACTION_TYPE_END.
5811 : : * @param[out] dst_group_id
5812 : : * Pointer to destination group id output. will be set to 0 if actions is END,
5813 : : * otherwise will be set to destination group id.
5814 : : * @param[out] error
5815 : : * Pointer to error structure.
5816 : : *
5817 : : * @return
5818 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
5819 : : */
5820 : :
5821 : : static int
5822 : 0 : flow_hw_group_parse_miss_actions(struct rte_eth_dev *dev,
5823 : : struct mlx5_flow_template_table_cfg *cfg,
5824 : : const struct rte_flow_action actions[],
5825 : : uint32_t *dst_group_id,
5826 : : struct rte_flow_error *error)
5827 : : {
5828 : : const struct rte_flow_action_jump *jump_conf;
5829 : 0 : uint32_t temp = 0;
5830 : : uint32_t i;
5831 : :
5832 [ # # ]: 0 : for (i = 0; actions[i].type != RTE_FLOW_ACTION_TYPE_END; i++) {
5833 [ # # # ]: 0 : switch (actions[i].type) {
5834 : 0 : case RTE_FLOW_ACTION_TYPE_VOID:
5835 : 0 : continue;
5836 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP:
5837 [ # # ]: 0 : if (temp)
5838 : 0 : return rte_flow_error_set(error, ENOTSUP,
5839 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, actions,
5840 : : "Miss actions can contain only a single JUMP");
5841 : :
5842 : 0 : jump_conf = (const struct rte_flow_action_jump *)actions[i].conf;
5843 [ # # ]: 0 : if (!jump_conf)
5844 : 0 : return rte_flow_error_set(error, EINVAL,
5845 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5846 : : jump_conf, "Jump conf must not be NULL");
5847 : :
5848 [ # # ]: 0 : if (flow_hw_translate_group(dev, cfg, jump_conf->group, &temp, error))
5849 : 0 : return -rte_errno;
5850 : :
5851 [ # # ]: 0 : if (!temp)
5852 : 0 : return rte_flow_error_set(error, EINVAL,
5853 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5854 : : "Failed to set group miss actions - Invalid target group");
5855 : : break;
5856 : 0 : default:
5857 : 0 : return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
5858 : : &actions[i], "Unsupported default miss action type");
5859 : : }
5860 : : }
5861 : :
5862 : 0 : *dst_group_id = temp;
5863 : 0 : return 0;
5864 : : }
5865 : :
5866 : : /**
5867 : : * Set group's miss group.
5868 : : *
5869 : : * @param[in] dev
5870 : : * Pointer to the rte_eth_dev structure.
5871 : : * @param[in] cfg
5872 : : * Pointer to the table_cfg structure.
5873 : : * @param[in] src_grp
5874 : : * Pointer to source group structure.
5875 : : * if NULL, a new group will be created based on group id from cfg->attr.flow_attr.group.
5876 : : * @param[in] dst_grp
5877 : : * Pointer to destination group structure.
5878 : : * @param[out] error
5879 : : * Pointer to error structure.
5880 : : *
5881 : : * @return
5882 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
5883 : : */
5884 : :
5885 : : static int
5886 : 0 : flow_hw_group_set_miss_group(struct rte_eth_dev *dev,
5887 : : struct mlx5_flow_template_table_cfg *cfg,
5888 : : struct mlx5_flow_group *src_grp,
5889 : : struct mlx5_flow_group *dst_grp,
5890 : : struct rte_flow_error *error)
5891 : : {
5892 : 0 : struct rte_flow_error sub_error = {
5893 : : .type = RTE_FLOW_ERROR_TYPE_NONE,
5894 : : .cause = NULL,
5895 : : .message = NULL,
5896 : : };
5897 : 0 : struct mlx5_flow_cb_ctx ctx = {
5898 : : .dev = dev,
5899 : : .error = &sub_error,
5900 : 0 : .data = &cfg->attr.flow_attr,
5901 : 0 : .data2 = &cfg->attr.specialize,
5902 : : };
5903 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
5904 : : struct mlx5_list_entry *ge;
5905 : : bool ref = false;
5906 : : int ret;
5907 : :
5908 [ # # ]: 0 : if (!dst_grp)
5909 : : return -EINVAL;
5910 : :
5911 : : /* If group doesn't exist - needs to be created. */
5912 [ # # ]: 0 : if (!src_grp) {
5913 : 0 : ge = mlx5_hlist_register(priv->sh->groups, cfg->attr.flow_attr.group, &ctx);
5914 [ # # ]: 0 : if (!ge)
5915 : 0 : return -rte_errno;
5916 : :
5917 : : src_grp = container_of(ge, struct mlx5_flow_group, entry);
5918 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->flow_hw_grp, src_grp, next);
5919 : : ref = true;
5920 [ # # ]: 0 : } else if (!src_grp->miss_group) {
5921 : : /* If group exists, but has no miss actions - need to increase ref_cnt. */
5922 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->flow_hw_grp, src_grp, next);
5923 : 0 : src_grp->entry.ref_cnt++;
5924 : : ref = true;
5925 : : }
5926 : :
5927 : 0 : ret = mlx5dr_table_set_default_miss(src_grp->tbl, dst_grp->tbl);
5928 [ # # ]: 0 : if (ret)
5929 : 0 : goto mlx5dr_error;
5930 : :
5931 : : /* If group existed and had old miss actions - ref_cnt is already correct.
5932 : : * However, need to reduce ref counter for old miss group.
5933 : : */
5934 [ # # ]: 0 : if (src_grp->miss_group)
5935 : 0 : mlx5_hlist_unregister(priv->sh->groups, &src_grp->miss_group->entry);
5936 : :
5937 : 0 : src_grp->miss_group = dst_grp;
5938 : 0 : return 0;
5939 : :
5940 : : mlx5dr_error:
5941 : : /* Reduce src_grp ref_cnt back & remove from grp list in case of mlx5dr error */
5942 [ # # ]: 0 : if (ref) {
5943 : 0 : mlx5_hlist_unregister(priv->sh->groups, &src_grp->entry);
5944 [ # # ]: 0 : LIST_REMOVE(src_grp, next);
5945 : : }
5946 : :
5947 : 0 : return rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5948 : : "Failed to set group miss actions");
5949 : : }
5950 : :
5951 : : /**
5952 : : * Unset group's miss group.
5953 : : *
5954 : : * @param[in] dev
5955 : : * Pointer to the rte_eth_dev structure.
5956 : : * @param[in] grp
5957 : : * Pointer to group structure.
5958 : : * @param[out] error
5959 : : * Pointer to error structure.
5960 : : *
5961 : : * @return
5962 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
5963 : : */
5964 : :
5965 : : static int
5966 : 0 : flow_hw_group_unset_miss_group(struct rte_eth_dev *dev,
5967 : : struct mlx5_flow_group *grp,
5968 : : struct rte_flow_error *error)
5969 : : {
5970 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
5971 : : int ret;
5972 : :
5973 : : /* If group doesn't exist - no need to change anything. */
5974 [ # # ]: 0 : if (!grp)
5975 : : return 0;
5976 : :
5977 : : /* If group exists, but miss actions is already default behavior -
5978 : : * no need to change anything.
5979 : : */
5980 [ # # ]: 0 : if (!grp->miss_group)
5981 : : return 0;
5982 : :
5983 : 0 : ret = mlx5dr_table_set_default_miss(grp->tbl, NULL);
5984 [ # # ]: 0 : if (ret)
5985 : 0 : return rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5986 : : "Failed to unset group miss actions");
5987 : :
5988 : 0 : mlx5_hlist_unregister(priv->sh->groups, &grp->miss_group->entry);
5989 : 0 : grp->miss_group = NULL;
5990 : :
5991 [ # # ]: 0 : LIST_REMOVE(grp, next);
5992 : 0 : mlx5_hlist_unregister(priv->sh->groups, &grp->entry);
5993 : :
5994 : 0 : return 0;
5995 : : }
5996 : :
5997 : : /**
5998 : : * Set group miss actions.
5999 : : *
6000 : : * @param[in] dev
6001 : : * Pointer to the rte_eth_dev structure.
6002 : : * @param[in] group_id
6003 : : * Group id.
6004 : : * @param[in] attr
6005 : : * Pointer to group attributes structure.
6006 : : * @param[in] actions
6007 : : * Array of actions to perform on group miss. Supported types:
6008 : : * RTE_FLOW_ACTION_TYPE_JUMP, RTE_FLOW_ACTION_TYPE_VOID, RTE_FLOW_ACTION_TYPE_END.
6009 : : * @param[out] error
6010 : : * Pointer to error structure.
6011 : : *
6012 : : * @return
6013 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
6014 : : */
6015 : :
6016 : : int
6017 : 0 : mlx5_flow_hw_group_set_miss_actions(struct rte_eth_dev *dev,
6018 : : uint32_t group_id,
6019 : : const struct rte_flow_group_attr *attr,
6020 : : const struct rte_flow_action actions[],
6021 : : struct rte_flow_error *error)
6022 : : {
6023 : 0 : struct rte_flow_error sub_error = {
6024 : : .type = RTE_FLOW_ERROR_TYPE_NONE,
6025 : : .cause = NULL,
6026 : : .message = NULL,
6027 : : };
6028 : 0 : struct mlx5_flow_template_table_cfg cfg = {
6029 : : .external = true,
6030 : : .attr = {
6031 : : .flow_attr = {
6032 : : .group = group_id,
6033 : 0 : .ingress = attr->ingress,
6034 : 0 : .egress = attr->egress,
6035 : 0 : .transfer = attr->transfer,
6036 : : },
6037 : : },
6038 : : };
6039 : 0 : struct mlx5_flow_cb_ctx ctx = {
6040 : : .dev = dev,
6041 : : .error = &sub_error,
6042 : : .data = &cfg.attr.flow_attr,
6043 : : .data2 = &cfg.attr.specialize,
6044 : : };
6045 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6046 : : struct mlx5_flow_group *src_grp = NULL;
6047 : : struct mlx5_flow_group *dst_grp = NULL;
6048 : : struct mlx5_list_entry *ge;
6049 : 0 : uint32_t dst_group_id = 0;
6050 : : int ret;
6051 : :
6052 [ # # ]: 0 : if (flow_hw_translate_group(dev, &cfg, group_id, &group_id, error))
6053 : 0 : return -rte_errno;
6054 : :
6055 [ # # ]: 0 : if (!group_id)
6056 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6057 : : NULL, "Failed to set group miss actions - invalid group id");
6058 : :
6059 : 0 : ret = flow_hw_group_parse_miss_actions(dev, &cfg, actions, &dst_group_id, error);
6060 [ # # ]: 0 : if (ret)
6061 : 0 : return -rte_errno;
6062 : :
6063 [ # # ]: 0 : if (dst_group_id == group_id) {
6064 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6065 : : NULL, "Failed to set group miss actions - target group id must differ from group_id");
6066 : : }
6067 : :
6068 : 0 : cfg.attr.flow_attr.group = group_id;
6069 : 0 : ge = mlx5_hlist_lookup(priv->sh->groups, group_id, &ctx);
6070 [ # # ]: 0 : if (ge)
6071 : : src_grp = container_of(ge, struct mlx5_flow_group, entry);
6072 : :
6073 [ # # ]: 0 : if (dst_group_id) {
6074 : : /* Increase ref_cnt for new miss group. */
6075 : 0 : cfg.attr.flow_attr.group = dst_group_id;
6076 : 0 : ge = mlx5_hlist_register(priv->sh->groups, dst_group_id, &ctx);
6077 [ # # ]: 0 : if (!ge)
6078 : 0 : return -rte_errno;
6079 : :
6080 : : dst_grp = container_of(ge, struct mlx5_flow_group, entry);
6081 : :
6082 : 0 : cfg.attr.flow_attr.group = group_id;
6083 : 0 : ret = flow_hw_group_set_miss_group(dev, &cfg, src_grp, dst_grp, error);
6084 [ # # ]: 0 : if (ret)
6085 : 0 : goto error;
6086 : : } else {
6087 : 0 : return flow_hw_group_unset_miss_group(dev, src_grp, error);
6088 : : }
6089 : :
6090 : : return 0;
6091 : :
6092 : : error:
6093 : : if (dst_grp)
6094 : 0 : mlx5_hlist_unregister(priv->sh->groups, &dst_grp->entry);
6095 : 0 : return -rte_errno;
6096 : : }
6097 : :
6098 : : static bool
6099 : : flow_hw_modify_field_is_used(const struct rte_flow_action_modify_field *action,
6100 : : enum rte_flow_field_id field)
6101 : : {
6102 [ # # # # : 0 : return action->src.field == field || action->dst.field == field;
# # # # #
# # # # #
# # # # #
# # # # #
# # # # ]
6103 : : }
6104 : :
6105 : : static bool
6106 : : flow_hw_modify_field_is_geneve_opt(enum rte_flow_field_id field)
6107 : : {
6108 : : return field == RTE_FLOW_FIELD_GENEVE_OPT_TYPE ||
6109 : 0 : field == RTE_FLOW_FIELD_GENEVE_OPT_CLASS ||
6110 : : field == RTE_FLOW_FIELD_GENEVE_OPT_DATA;
6111 : : }
6112 : :
6113 : : static bool
6114 : 0 : flow_hw_modify_field_is_add_dst_valid(const struct rte_flow_action_modify_field *conf)
6115 : : {
6116 [ # # ]: 0 : if (conf->operation != RTE_FLOW_MODIFY_ADD)
6117 : : return true;
6118 [ # # ]: 0 : if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
6119 : : conf->src.field == RTE_FLOW_FIELD_VALUE)
6120 : : return true;
6121 [ # # ]: 0 : switch (conf->dst.field) {
6122 : : case RTE_FLOW_FIELD_IPV4_TTL:
6123 : : case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
6124 : : case RTE_FLOW_FIELD_TCP_SEQ_NUM:
6125 : : case RTE_FLOW_FIELD_TCP_ACK_NUM:
6126 : : case RTE_FLOW_FIELD_TAG:
6127 : : case RTE_FLOW_FIELD_META:
6128 : : case RTE_FLOW_FIELD_FLEX_ITEM:
6129 : : case RTE_FLOW_FIELD_TCP_DATA_OFFSET:
6130 : : case RTE_FLOW_FIELD_IPV4_IHL:
6131 : : case RTE_FLOW_FIELD_IPV4_TOTAL_LEN:
6132 : : case RTE_FLOW_FIELD_IPV6_PAYLOAD_LEN:
6133 : : return true;
6134 : : default:
6135 : : break;
6136 : : }
6137 : 0 : return false;
6138 : : }
6139 : :
6140 : : /**
6141 : : * Validate the level value for modify field action.
6142 : : *
6143 : : * @param[in] data
6144 : : * Pointer to the rte_flow_field_data structure either src or dst.
6145 : : * @param[in] inner_supported
6146 : : * Indicator whether inner should be supported.
6147 : : * @param[out] error
6148 : : * Pointer to error structure.
6149 : : *
6150 : : * @return
6151 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
6152 : : */
6153 : : static int
6154 : 0 : flow_hw_validate_modify_field_level(const struct rte_flow_field_data *data,
6155 : : bool inner_supported,
6156 : : struct rte_flow_error *error)
6157 : : {
6158 [ # # # # : 0 : switch ((int)data->field) {
# ]
6159 : : case RTE_FLOW_FIELD_START:
6160 : : case RTE_FLOW_FIELD_VLAN_TYPE:
6161 : : case RTE_FLOW_FIELD_RANDOM:
6162 : : case RTE_FLOW_FIELD_FLEX_ITEM:
6163 : : /*
6164 : : * Level shouldn't be valid since field isn't supported or
6165 : : * doesn't use 'level'.
6166 : : */
6167 : : break;
6168 : : case RTE_FLOW_FIELD_MARK:
6169 : : case RTE_FLOW_FIELD_META:
6170 : : case RTE_FLOW_FIELD_METER_COLOR:
6171 : : case RTE_FLOW_FIELD_HASH_RESULT:
6172 : : /* For meta data fields encapsulation level is don't-care. */
6173 : : break;
6174 : 0 : case RTE_FLOW_FIELD_TAG:
6175 : : case MLX5_RTE_FLOW_FIELD_META_REG:
6176 : : /*
6177 : : * The tag array for RTE_FLOW_FIELD_TAG type is provided using
6178 : : * 'tag_index' field. In old API, it was provided using 'level'
6179 : : * field and it is still supported for backwards compatibility.
6180 : : * Therefore, for meta tag field only, level is matter. It is
6181 : : * taken as tag index when 'tag_index' field isn't set, and
6182 : : * return error otherwise.
6183 : : */
6184 [ # # ]: 0 : if (data->level > 0) {
6185 [ # # ]: 0 : if (data->tag_index > 0)
6186 : 0 : return rte_flow_error_set(error, EINVAL,
6187 : : RTE_FLOW_ERROR_TYPE_ACTION,
6188 : : data,
6189 : : "tag array can be provided using 'level' or 'tag_index' fields, not both");
6190 : 0 : DRV_LOG(WARNING,
6191 : : "tag array provided in 'level' field instead of 'tag_index' field.");
6192 : : }
6193 : : break;
6194 : 0 : case RTE_FLOW_FIELD_MAC_DST:
6195 : : case RTE_FLOW_FIELD_MAC_SRC:
6196 : : case RTE_FLOW_FIELD_MAC_TYPE:
6197 : : case RTE_FLOW_FIELD_IPV4_IHL:
6198 : : case RTE_FLOW_FIELD_IPV4_TOTAL_LEN:
6199 : : case RTE_FLOW_FIELD_IPV4_DSCP:
6200 : : case RTE_FLOW_FIELD_IPV4_ECN:
6201 : : case RTE_FLOW_FIELD_IPV4_TTL:
6202 : : case RTE_FLOW_FIELD_IPV4_SRC:
6203 : : case RTE_FLOW_FIELD_IPV4_DST:
6204 : : case RTE_FLOW_FIELD_IPV6_TRAFFIC_CLASS:
6205 : : case RTE_FLOW_FIELD_IPV6_FLOW_LABEL:
6206 : : case RTE_FLOW_FIELD_IPV6_PAYLOAD_LEN:
6207 : : case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
6208 : : case RTE_FLOW_FIELD_IPV6_SRC:
6209 : : case RTE_FLOW_FIELD_IPV6_DST:
6210 : : case RTE_FLOW_FIELD_TCP_PORT_SRC:
6211 : : case RTE_FLOW_FIELD_TCP_PORT_DST:
6212 : : case RTE_FLOW_FIELD_TCP_FLAGS:
6213 : : case RTE_FLOW_FIELD_TCP_DATA_OFFSET:
6214 : : case RTE_FLOW_FIELD_UDP_PORT_SRC:
6215 : : case RTE_FLOW_FIELD_UDP_PORT_DST:
6216 [ # # ]: 0 : if (data->level > 2)
6217 : 0 : return rte_flow_error_set(error, ENOTSUP,
6218 : : RTE_FLOW_ERROR_TYPE_ACTION,
6219 : : data,
6220 : : "second inner header fields modification is not supported");
6221 [ # # ]: 0 : if (inner_supported)
6222 : : break;
6223 : : /* Fallthrough */
6224 : : case RTE_FLOW_FIELD_VLAN_ID:
6225 : : case RTE_FLOW_FIELD_IPV4_PROTO:
6226 : : case RTE_FLOW_FIELD_IPV6_PROTO:
6227 : : case RTE_FLOW_FIELD_IPV6_DSCP:
6228 : : case RTE_FLOW_FIELD_IPV6_ECN:
6229 : : case RTE_FLOW_FIELD_TCP_SEQ_NUM:
6230 : : case RTE_FLOW_FIELD_TCP_ACK_NUM:
6231 : : case RTE_FLOW_FIELD_ESP_PROTO:
6232 : : case RTE_FLOW_FIELD_ESP_SPI:
6233 : : case RTE_FLOW_FIELD_ESP_SEQ_NUM:
6234 : : case RTE_FLOW_FIELD_VXLAN_VNI:
6235 : : case RTE_FLOW_FIELD_VXLAN_LAST_RSVD:
6236 : : case RTE_FLOW_FIELD_GENEVE_VNI:
6237 : : case RTE_FLOW_FIELD_GENEVE_OPT_TYPE:
6238 : : case RTE_FLOW_FIELD_GENEVE_OPT_CLASS:
6239 : : case RTE_FLOW_FIELD_GENEVE_OPT_DATA:
6240 : : case RTE_FLOW_FIELD_GTP_TEID:
6241 : : case RTE_FLOW_FIELD_GTP_PSC_QFI:
6242 [ # # ]: 0 : if (data->level > 1)
6243 : 0 : return rte_flow_error_set(error, ENOTSUP,
6244 : : RTE_FLOW_ERROR_TYPE_ACTION,
6245 : : data,
6246 : : "inner header fields modification is not supported");
6247 : : break;
6248 : 0 : case RTE_FLOW_FIELD_MPLS:
6249 [ # # ]: 0 : if (data->level == 1)
6250 : 0 : return rte_flow_error_set(error, ENOTSUP,
6251 : : RTE_FLOW_ERROR_TYPE_ACTION,
6252 : : data,
6253 : : "outer MPLS header modification is not supported");
6254 [ # # ]: 0 : if (data->level > 2)
6255 : 0 : return rte_flow_error_set(error, ENOTSUP,
6256 : : RTE_FLOW_ERROR_TYPE_ACTION,
6257 : : data,
6258 : : "inner MPLS header modification is not supported");
6259 : : break;
6260 : 0 : case RTE_FLOW_FIELD_POINTER:
6261 : : case RTE_FLOW_FIELD_VALUE:
6262 : : default:
6263 : : MLX5_ASSERT(false);
6264 : : }
6265 : : return 0;
6266 : : }
6267 : :
6268 : : static int
6269 : 0 : flow_hw_validate_action_modify_field(struct rte_eth_dev *dev,
6270 : : const struct rte_flow_action *action,
6271 : : const struct rte_flow_action *mask,
6272 : : struct rte_flow_error *error)
6273 : : {
6274 : 0 : const struct rte_flow_action_modify_field *action_conf = action->conf;
6275 : 0 : const struct rte_flow_action_modify_field *mask_conf = mask->conf;
6276 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6277 : 0 : struct mlx5_hca_attr *attr = &priv->sh->cdev->config.hca_attr;
6278 : : int ret;
6279 : :
6280 [ # # ]: 0 : if (!mask_conf)
6281 : 0 : return rte_flow_error_set(error, EINVAL,
6282 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6283 : : "modify_field mask conf is missing");
6284 [ # # ]: 0 : if (action_conf->operation != mask_conf->operation)
6285 : 0 : return rte_flow_error_set(error, EINVAL,
6286 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6287 : : "modify_field operation mask and template are not equal");
6288 [ # # ]: 0 : if (action_conf->dst.field != mask_conf->dst.field)
6289 : 0 : return rte_flow_error_set(error, EINVAL,
6290 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6291 : : "destination field mask and template are not equal");
6292 : 0 : if (action_conf->dst.field == RTE_FLOW_FIELD_POINTER ||
6293 [ # # ]: 0 : action_conf->dst.field == RTE_FLOW_FIELD_VALUE ||
6294 : : action_conf->dst.field == RTE_FLOW_FIELD_HASH_RESULT)
6295 : 0 : return rte_flow_error_set(error, EINVAL,
6296 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6297 : : "immediate value, pointer and hash result cannot be used as destination");
6298 : 0 : ret = flow_hw_validate_modify_field_level(&action_conf->dst, false, error);
6299 [ # # ]: 0 : if (ret)
6300 : : return ret;
6301 [ # # # # ]: 0 : if (action_conf->dst.field != RTE_FLOW_FIELD_FLEX_ITEM &&
6302 : : !flow_hw_modify_field_is_geneve_opt(action_conf->dst.field)) {
6303 [ # # ]: 0 : if (action_conf->dst.tag_index &&
6304 : : !flow_modify_field_support_tag_array(action_conf->dst.field))
6305 : 0 : return rte_flow_error_set(error, EINVAL,
6306 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6307 : : "destination tag index is not supported");
6308 : : }
6309 [ # # ]: 0 : if (mask_conf->dst.level != UINT8_MAX)
6310 : 0 : return rte_flow_error_set(error, EINVAL,
6311 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6312 : : "destination encapsulation level must be fully masked");
6313 [ # # ]: 0 : if (mask_conf->dst.offset != UINT32_MAX)
6314 : 0 : return rte_flow_error_set(error, EINVAL,
6315 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6316 : : "destination offset level must be fully masked");
6317 [ # # ]: 0 : if (action_conf->src.field != mask_conf->src.field)
6318 : 0 : return rte_flow_error_set(error, EINVAL,
6319 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6320 : : "destination field mask and template are not equal");
6321 [ # # ]: 0 : if (action_conf->src.field != RTE_FLOW_FIELD_POINTER &&
6322 : : action_conf->src.field != RTE_FLOW_FIELD_VALUE) {
6323 [ # # # # ]: 0 : if (action_conf->src.field != RTE_FLOW_FIELD_FLEX_ITEM &&
6324 : : !flow_hw_modify_field_is_geneve_opt(action_conf->src.field)) {
6325 [ # # ]: 0 : if (action_conf->src.tag_index &&
6326 : : !flow_modify_field_support_tag_array(action_conf->src.field))
6327 : 0 : return rte_flow_error_set(error, EINVAL,
6328 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6329 : : "source tag index is not supported");
6330 : : }
6331 [ # # ]: 0 : if (mask_conf->src.level != UINT8_MAX)
6332 : 0 : return rte_flow_error_set(error, EINVAL,
6333 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6334 : : "source encapsulation level must be fully masked");
6335 [ # # ]: 0 : if (mask_conf->src.offset != UINT32_MAX)
6336 : 0 : return rte_flow_error_set(error, EINVAL,
6337 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6338 : : "source offset level must be fully masked");
6339 : 0 : ret = flow_hw_validate_modify_field_level(&action_conf->src, true, error);
6340 [ # # ]: 0 : if (ret)
6341 : : return ret;
6342 : : }
6343 [ # # ]: 0 : if ((action_conf->dst.field == RTE_FLOW_FIELD_TAG &&
6344 [ # # # # ]: 0 : action_conf->dst.tag_index >= MLX5_FLOW_HW_TAGS_MAX &&
6345 : 0 : action_conf->dst.tag_index != RTE_PMD_MLX5_LINEAR_HASH_TAG_INDEX) ||
6346 [ # # ]: 0 : (action_conf->src.field == RTE_FLOW_FIELD_TAG &&
6347 [ # # # # ]: 0 : action_conf->src.tag_index >= MLX5_FLOW_HW_TAGS_MAX &&
6348 : : action_conf->src.tag_index != RTE_PMD_MLX5_LINEAR_HASH_TAG_INDEX))
6349 : 0 : return rte_flow_error_set(error, EINVAL,
6350 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6351 : : "tag index is out of range");
6352 [ # # # # ]: 0 : if ((action_conf->dst.field == RTE_FLOW_FIELD_TAG &&
6353 [ # # # # ]: 0 : flow_hw_get_reg_id(dev, RTE_FLOW_ITEM_TYPE_TAG, action_conf->dst.tag_index) == REG_NON) ||
6354 [ # # ]: 0 : (action_conf->src.field == RTE_FLOW_FIELD_TAG &&
6355 [ # # ]: 0 : flow_hw_get_reg_id(dev, RTE_FLOW_ITEM_TYPE_TAG, action_conf->src.tag_index) == REG_NON))
6356 : 0 : return rte_flow_error_set(error, EINVAL,
6357 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6358 : : "tag index is out of range");
6359 [ # # ]: 0 : if (mask_conf->width != UINT32_MAX)
6360 : 0 : return rte_flow_error_set(error, EINVAL,
6361 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6362 : : "modify_field width field must be fully masked");
6363 [ # # ]: 0 : if (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_START))
6364 : 0 : return rte_flow_error_set(error, EINVAL,
6365 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6366 : : "modifying arbitrary place in a packet is not supported");
6367 [ # # ]: 0 : if (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_VLAN_TYPE))
6368 : 0 : return rte_flow_error_set(error, EINVAL,
6369 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6370 : : "modifying vlan_type is not supported");
6371 [ # # ]: 0 : if (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_RANDOM))
6372 : 0 : return rte_flow_error_set(error, EINVAL,
6373 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6374 : : "modifying random value is not supported");
6375 : : /**
6376 : : * Geneve VNI modification is supported only when Geneve header is
6377 : : * parsed natively. When GENEVE options are supported, they both Geneve
6378 : : * and options headers are parsed as a flex parser.
6379 : : */
6380 [ # # ]: 0 : if (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_GENEVE_VNI) &&
6381 [ # # ]: 0 : attr->geneve_tlv_opt)
6382 : 0 : return rte_flow_error_set(error, EINVAL,
6383 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6384 : : "modifying Geneve VNI is not supported when GENEVE opt is supported");
6385 [ # # # # ]: 0 : if (priv->tlv_options == NULL &&
6386 [ # # ]: 0 : (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_GENEVE_OPT_TYPE) ||
6387 [ # # ]: 0 : flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_GENEVE_OPT_CLASS) ||
6388 : : flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_GENEVE_OPT_DATA)))
6389 : 0 : return rte_flow_error_set(error, EINVAL,
6390 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6391 : : "modifying Geneve TLV option is supported only after parser configuration");
6392 : : /* Due to HW bug, tunnel MPLS header is read only. */
6393 [ # # ]: 0 : if (action_conf->dst.field == RTE_FLOW_FIELD_MPLS)
6394 : 0 : return rte_flow_error_set(error, EINVAL,
6395 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6396 : : "MPLS cannot be used as destination");
6397 : : /* ADD_FIELD is not supported for all the fields. */
6398 [ # # ]: 0 : if (!flow_hw_modify_field_is_add_dst_valid(action_conf))
6399 : 0 : return rte_flow_error_set(error, EINVAL,
6400 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6401 : : "invalid add_field destination");
6402 : : return 0;
6403 : : }
6404 : :
6405 : : static int
6406 : 0 : flow_hw_validate_action_port_representor(struct rte_eth_dev *dev __rte_unused,
6407 : : const struct rte_flow_actions_template_attr *attr,
6408 : : const struct rte_flow_action *action,
6409 : : const struct rte_flow_action *mask,
6410 : : struct rte_flow_error *error)
6411 : : {
6412 : : const struct rte_flow_action_ethdev *action_conf = NULL;
6413 : : const struct rte_flow_action_ethdev *mask_conf = NULL;
6414 : :
6415 : : /* If transfer is set, port has been validated as proxy port. */
6416 [ # # ]: 0 : if (!attr->transfer)
6417 : 0 : return rte_flow_error_set(error, EINVAL,
6418 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6419 : : "cannot use port_representor actions"
6420 : : " without an E-Switch");
6421 [ # # ]: 0 : if (!action || !mask)
6422 : 0 : return rte_flow_error_set(error, EINVAL,
6423 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6424 : : "actiona and mask configuration must be set");
6425 : 0 : action_conf = action->conf;
6426 : 0 : mask_conf = mask->conf;
6427 [ # # # # : 0 : if (!mask_conf || mask_conf->port_id != MLX5_REPRESENTED_PORT_ESW_MGR ||
# # ]
6428 [ # # ]: 0 : !action_conf || action_conf->port_id != MLX5_REPRESENTED_PORT_ESW_MGR)
6429 : 0 : return rte_flow_error_set(error, EINVAL,
6430 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6431 : : "only eswitch manager port 0xffff is"
6432 : : " supported");
6433 : : return 0;
6434 : : }
6435 : :
6436 : : static int
6437 : 0 : flow_hw_validate_target_port_id(struct rte_eth_dev *dev,
6438 : : uint16_t target_port_id)
6439 : : {
6440 : : struct mlx5_priv *port_priv;
6441 : : struct mlx5_priv *dev_priv;
6442 : :
6443 [ # # ]: 0 : if (target_port_id == MLX5_REPRESENTED_PORT_ESW_MGR)
6444 : : return 0;
6445 : :
6446 : 0 : port_priv = mlx5_port_to_eswitch_info(target_port_id, false);
6447 [ # # ]: 0 : if (!port_priv) {
6448 : 0 : rte_errno = EINVAL;
6449 : 0 : DRV_LOG(ERR, "Port %u Failed to obtain E-Switch info for port %u",
6450 : : dev->data->port_id, target_port_id);
6451 : 0 : return -rte_errno;
6452 : : }
6453 : :
6454 : 0 : dev_priv = mlx5_dev_to_eswitch_info(dev);
6455 [ # # ]: 0 : if (!dev_priv) {
6456 : 0 : rte_errno = EINVAL;
6457 : 0 : DRV_LOG(ERR, "Port %u Failed to obtain E-Switch info for transfer proxy",
6458 : : dev->data->port_id);
6459 : 0 : return -rte_errno;
6460 : : }
6461 : :
6462 [ # # ]: 0 : if (port_priv->domain_id != dev_priv->domain_id) {
6463 : 0 : rte_errno = EINVAL;
6464 : 0 : DRV_LOG(ERR, "Port %u Failed to obtain E-Switch info for transfer proxy",
6465 : : dev->data->port_id);
6466 : 0 : return -rte_errno;
6467 : : }
6468 : :
6469 : : return 0;
6470 : : }
6471 : :
6472 : : static int
6473 : 0 : flow_hw_validate_action_represented_port(struct rte_eth_dev *dev,
6474 : : const struct rte_flow_action *action,
6475 : : const struct rte_flow_action *mask,
6476 : : struct rte_flow_error *error)
6477 : : {
6478 : 0 : const struct rte_flow_action_ethdev *action_conf = action->conf;
6479 : 0 : const struct rte_flow_action_ethdev *mask_conf = mask->conf;
6480 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6481 : :
6482 [ # # ]: 0 : if (!priv->sh->config.dv_esw_en)
6483 : 0 : return rte_flow_error_set(error, EINVAL,
6484 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6485 : : "cannot use represented_port actions"
6486 : : " without an E-Switch");
6487 [ # # # # ]: 0 : if (mask_conf && mask_conf->port_id) {
6488 [ # # ]: 0 : if (!action_conf)
6489 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
6490 : : action, "port index was not provided");
6491 : :
6492 [ # # ]: 0 : if (flow_hw_validate_target_port_id(dev, action_conf->port_id))
6493 : 0 : return rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
6494 : : action, "port index is invalid");
6495 : : }
6496 : : return 0;
6497 : : }
6498 : :
6499 : : /**
6500 : : * Validate AGE action.
6501 : : *
6502 : : * @param[in] dev
6503 : : * Pointer to rte_eth_dev structure.
6504 : : * @param[in] action
6505 : : * Pointer to the indirect action.
6506 : : * @param[in] action_flags
6507 : : * Holds the actions detected until now.
6508 : : * @param[in] fixed_cnt
6509 : : * Indicator if this list has a fixed COUNT action.
6510 : : * @param[out] error
6511 : : * Pointer to error structure.
6512 : : *
6513 : : * @return
6514 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
6515 : : */
6516 : : static int
6517 : 0 : flow_hw_validate_action_age(struct rte_eth_dev *dev,
6518 : : const struct rte_flow_action *action,
6519 : : uint64_t action_flags, bool fixed_cnt,
6520 : : struct rte_flow_error *error)
6521 : : {
6522 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6523 : 0 : struct mlx5_age_info *age_info = GET_PORT_AGE_INFO(priv);
6524 : :
6525 [ # # ]: 0 : if (!priv->sh->cdev->config.devx)
6526 : 0 : return rte_flow_error_set(error, ENOTSUP,
6527 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6528 : : NULL, "AGE action not supported");
6529 [ # # ]: 0 : if (age_info->ages_ipool == NULL)
6530 : 0 : return rte_flow_error_set(error, EINVAL,
6531 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6532 : : "aging pool not initialized");
6533 [ # # ]: 0 : if ((action_flags & MLX5_FLOW_ACTION_AGE) ||
6534 : : (action_flags & MLX5_FLOW_ACTION_INDIRECT_AGE))
6535 : 0 : return rte_flow_error_set(error, EINVAL,
6536 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6537 : : "duplicate AGE actions set");
6538 [ # # ]: 0 : if (fixed_cnt)
6539 : 0 : return rte_flow_error_set(error, EINVAL,
6540 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6541 : : "AGE and fixed COUNT combination is not supported");
6542 : : return 0;
6543 : : }
6544 : :
6545 : : /**
6546 : : * Validate count action.
6547 : : *
6548 : : * @param[in] dev
6549 : : * Pointer to rte_eth_dev structure.
6550 : : * @param[in] action
6551 : : * Pointer to the indirect action.
6552 : : * @param[in] mask
6553 : : * Pointer to the indirect action mask.
6554 : : * @param[in] action_flags
6555 : : * Holds the actions detected until now.
6556 : : * @param[out] error
6557 : : * Pointer to error structure.
6558 : : *
6559 : : * @return
6560 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
6561 : : */
6562 : : static int
6563 : 0 : flow_hw_validate_action_count(struct rte_eth_dev *dev,
6564 : : const struct rte_flow_action *action,
6565 : : const struct rte_flow_action *mask,
6566 : : uint64_t action_flags,
6567 : : struct rte_flow_error *error)
6568 : : {
6569 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6570 : 0 : const struct rte_flow_action_count *count = mask->conf;
6571 : :
6572 [ # # ]: 0 : if (!priv->sh->cdev->config.devx)
6573 : 0 : return rte_flow_error_set(error, ENOTSUP,
6574 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6575 : : "count action not supported");
6576 [ # # ]: 0 : if (!priv->hws_cpool)
6577 : 0 : return rte_flow_error_set(error, EINVAL,
6578 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6579 : : "counters pool not initialized");
6580 [ # # ]: 0 : if ((action_flags & MLX5_FLOW_ACTION_COUNT) ||
6581 : : (action_flags & MLX5_FLOW_ACTION_INDIRECT_COUNT))
6582 : 0 : return rte_flow_error_set(error, EINVAL,
6583 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6584 : : "duplicate count actions set");
6585 [ # # # # : 0 : if (count && count->id && (action_flags & MLX5_FLOW_ACTION_AGE))
# # ]
6586 : 0 : return rte_flow_error_set(error, EINVAL,
6587 : : RTE_FLOW_ERROR_TYPE_ACTION, mask,
6588 : : "AGE and COUNT action shared by mask combination is not supported");
6589 : : return 0;
6590 : : }
6591 : :
6592 : : /**
6593 : : * Validate meter_mark action.
6594 : : *
6595 : : * @param[in] dev
6596 : : * Pointer to rte_eth_dev structure.
6597 : : * @param[in] action
6598 : : * Pointer to the indirect action.
6599 : : * @param[in] indirect
6600 : : * If true, then provided action was passed using an indirect action.
6601 : : * @param[out] error
6602 : : * Pointer to error structure.
6603 : : *
6604 : : * @return
6605 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
6606 : : */
6607 : : static int
6608 : 0 : flow_hw_validate_action_meter_mark(struct rte_eth_dev *dev,
6609 : : const struct rte_flow_action *action,
6610 : : bool indirect,
6611 : : struct rte_flow_error *error)
6612 : : {
6613 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6614 : :
6615 : : RTE_SET_USED(action);
6616 : :
6617 [ # # ]: 0 : if (!priv->sh->cdev->config.devx)
6618 : 0 : return rte_flow_error_set(error, ENOTSUP,
6619 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6620 : : "meter_mark action not supported");
6621 [ # # # # ]: 0 : if (!indirect && priv->shared_host)
6622 : 0 : return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, action,
6623 : : "meter_mark action can only be used on host port");
6624 [ # # ]: 0 : if (!priv->hws_mpool)
6625 : 0 : return rte_flow_error_set(error, EINVAL,
6626 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6627 : : "meter_mark pool not initialized");
6628 : : return 0;
6629 : : }
6630 : :
6631 : : /**
6632 : : * Validate indirect action.
6633 : : *
6634 : : * @param[in] dev
6635 : : * Pointer to rte_eth_dev structure.
6636 : : * @param[in] action
6637 : : * Pointer to the indirect action.
6638 : : * @param[in] mask
6639 : : * Pointer to the indirect action mask.
6640 : : * @param[in] attr
6641 : : * Pointer to the action template attributes.
6642 : : * @param[in, out] action_flags
6643 : : * Holds the actions detected until now.
6644 : : * @param[in, out] fixed_cnt
6645 : : * Pointer to indicator if this list has a fixed COUNT action.
6646 : : * @param[out] error
6647 : : * Pointer to error structure.
6648 : : *
6649 : : * @return
6650 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
6651 : : */
6652 : : static int
6653 : 0 : flow_hw_validate_action_indirect(struct rte_eth_dev *dev,
6654 : : const struct rte_flow_action *action,
6655 : : const struct rte_flow_action *mask,
6656 : : const struct rte_flow_actions_template_attr *attr,
6657 : : uint64_t *action_flags, bool *fixed_cnt,
6658 : : struct rte_flow_error *error)
6659 : : {
6660 : : uint32_t type;
6661 : : int ret;
6662 : :
6663 [ # # ]: 0 : if (!mask)
6664 : 0 : return rte_flow_error_set(error, EINVAL,
6665 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6666 : : "Unable to determine indirect action type without a mask specified");
6667 : 0 : type = mask->type;
6668 [ # # # # : 0 : switch (type) {
# # # ]
6669 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
6670 : 0 : ret = flow_hw_validate_action_meter_mark(dev, mask, true, error);
6671 [ # # ]: 0 : if (ret < 0)
6672 : : return ret;
6673 : 0 : *action_flags |= MLX5_FLOW_ACTION_METER;
6674 : 0 : break;
6675 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
6676 : 0 : ret = mlx5_hw_validate_action_rss(dev, action, mask, attr,
6677 : : *action_flags, true, error);
6678 [ # # ]: 0 : if (ret < 0)
6679 : : return ret;
6680 : 0 : *action_flags |= MLX5_FLOW_ACTION_RSS;
6681 : 0 : break;
6682 : 0 : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
6683 : 0 : ret = mlx5_hw_validate_action_conntrack(dev, action, mask, attr,
6684 : : *action_flags, error);
6685 [ # # ]: 0 : if (ret < 0)
6686 : : return ret;
6687 : 0 : *action_flags |= MLX5_FLOW_ACTION_CT;
6688 : 0 : break;
6689 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
6690 [ # # # # ]: 0 : if (action->conf && mask->conf) {
6691 [ # # ]: 0 : if ((*action_flags & MLX5_FLOW_ACTION_AGE) ||
6692 : : (*action_flags & MLX5_FLOW_ACTION_INDIRECT_AGE))
6693 : : /*
6694 : : * AGE cannot use indirect counter which is
6695 : : * shared with enother flow rules.
6696 : : */
6697 : 0 : return rte_flow_error_set(error, EINVAL,
6698 : : RTE_FLOW_ERROR_TYPE_ACTION,
6699 : : NULL,
6700 : : "AGE and fixed COUNT combination is not supported");
6701 : 0 : *fixed_cnt = true;
6702 : : }
6703 : 0 : ret = flow_hw_validate_action_count(dev, action, mask,
6704 : : *action_flags, error);
6705 [ # # ]: 0 : if (ret < 0)
6706 : : return ret;
6707 : 0 : *action_flags |= MLX5_FLOW_ACTION_INDIRECT_COUNT;
6708 : 0 : break;
6709 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
6710 [ # # # # ]: 0 : if (action->conf && mask->conf)
6711 : 0 : return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
6712 : : action,
6713 : : "Fixed indirect age action is not supported");
6714 : 0 : ret = flow_hw_validate_action_age(dev, action, *action_flags,
6715 : 0 : *fixed_cnt, error);
6716 [ # # ]: 0 : if (ret < 0)
6717 : : return ret;
6718 : 0 : *action_flags |= MLX5_FLOW_ACTION_INDIRECT_AGE;
6719 : 0 : break;
6720 : 0 : case RTE_FLOW_ACTION_TYPE_QUOTA:
6721 : : /* TODO: add proper quota verification */
6722 : 0 : *action_flags |= MLX5_FLOW_ACTION_QUOTA;
6723 : 0 : break;
6724 : 0 : default:
6725 : 0 : DRV_LOG(WARNING, "Unsupported shared action type: %d", type);
6726 : 0 : return rte_flow_error_set(error, ENOTSUP,
6727 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, mask,
6728 : : "Unsupported indirect action type");
6729 : : }
6730 : : return 0;
6731 : : }
6732 : :
6733 : : /**
6734 : : * Validate ipv6_ext_push action.
6735 : : *
6736 : : * @param[in] dev
6737 : : * Pointer to rte_eth_dev structure.
6738 : : * @param[in] action
6739 : : * Pointer to the indirect action.
6740 : : * @param[out] error
6741 : : * Pointer to error structure.
6742 : : *
6743 : : * @return
6744 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
6745 : : */
6746 : : static int
6747 : 0 : flow_hw_validate_action_ipv6_ext_push(struct rte_eth_dev *dev __rte_unused,
6748 : : const struct rte_flow_action *action,
6749 : : struct rte_flow_error *error)
6750 : : {
6751 : 0 : const struct rte_flow_action_ipv6_ext_push *raw_push_data = action->conf;
6752 : :
6753 [ # # # # : 0 : if (!raw_push_data || !raw_push_data->size || !raw_push_data->data)
# # ]
6754 : 0 : return rte_flow_error_set(error, EINVAL,
6755 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6756 : : "invalid ipv6_ext_push data");
6757 [ # # # # ]: 0 : if (raw_push_data->type != IPPROTO_ROUTING ||
6758 : : raw_push_data->size > MLX5_PUSH_MAX_LEN)
6759 : 0 : return rte_flow_error_set(error, EINVAL,
6760 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6761 : : "Unsupported ipv6_ext_push type or length");
6762 : : return 0;
6763 : : }
6764 : :
6765 : : /**
6766 : : * Process `... / raw_decap / raw_encap / ...` actions sequence.
6767 : : * The PMD handles the sequence as a single encap or decap reformat action,
6768 : : * depending on the raw_encap configuration.
6769 : : *
6770 : : * The function assumes that the raw_decap / raw_encap location
6771 : : * in actions template list complies with relative HWS actions order:
6772 : : * for the required reformat configuration:
6773 : : * ENCAP configuration must appear before [JUMP|DROP|PORT]
6774 : : * DECAP configuration must appear at the template head.
6775 : : */
6776 : : static uint64_t
6777 : : mlx5_decap_encap_reformat_type(const struct rte_flow_action *actions,
6778 : : uint32_t encap_ind, uint64_t flags)
6779 : : {
6780 : 0 : const struct rte_flow_action_raw_encap *encap = actions[encap_ind].conf;
6781 : :
6782 [ # # ]: 0 : if ((flags & MLX5_FLOW_ACTION_DECAP) == 0)
6783 : : return MLX5_FLOW_ACTION_ENCAP;
6784 [ # # ]: 0 : if (actions[encap_ind - 1].type != RTE_FLOW_ACTION_TYPE_RAW_DECAP)
6785 : : return MLX5_FLOW_ACTION_ENCAP;
6786 : 0 : return encap->size >= MLX5_ENCAPSULATION_DECISION_SIZE ?
6787 [ # # ]: 0 : MLX5_FLOW_ACTION_ENCAP : MLX5_FLOW_ACTION_DECAP;
6788 : : }
6789 : :
6790 : : enum mlx5_hw_indirect_list_relative_position {
6791 : : MLX5_INDIRECT_LIST_POSITION_UNKNOWN = -1,
6792 : : MLX5_INDIRECT_LIST_POSITION_BEFORE_MH = 0,
6793 : : MLX5_INDIRECT_LIST_POSITION_AFTER_MH,
6794 : : };
6795 : :
6796 : : static enum mlx5_hw_indirect_list_relative_position
6797 : 0 : mlx5_hw_indirect_list_mh_position(const struct rte_flow_action *action)
6798 : : {
6799 : 0 : const struct rte_flow_action_indirect_list *conf = action->conf;
6800 [ # # # # ]: 0 : enum mlx5_indirect_list_type list_type = mlx5_get_indirect_list_type(conf->handle);
6801 : : enum mlx5_hw_indirect_list_relative_position pos = MLX5_INDIRECT_LIST_POSITION_UNKNOWN;
6802 : : const union {
6803 : : struct mlx5_indlst_legacy *legacy;
6804 : : struct mlx5_hw_encap_decap_action *reformat;
6805 : : struct rte_flow_action_list_handle *handle;
6806 : : } h = { .handle = conf->handle};
6807 : :
6808 [ # # # # ]: 0 : switch (list_type) {
6809 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY:
6810 [ # # # ]: 0 : switch (h.legacy->legacy_type) {
6811 : : case RTE_FLOW_ACTION_TYPE_AGE:
6812 : : case RTE_FLOW_ACTION_TYPE_COUNT:
6813 : : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
6814 : : case RTE_FLOW_ACTION_TYPE_METER_MARK:
6815 : : case RTE_FLOW_ACTION_TYPE_QUOTA:
6816 : : pos = MLX5_INDIRECT_LIST_POSITION_BEFORE_MH;
6817 : : break;
6818 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
6819 : : pos = MLX5_INDIRECT_LIST_POSITION_AFTER_MH;
6820 : 0 : break;
6821 : 0 : default:
6822 : : pos = MLX5_INDIRECT_LIST_POSITION_UNKNOWN;
6823 : 0 : break;
6824 : : }
6825 : : break;
6826 : : case MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR:
6827 : : pos = MLX5_INDIRECT_LIST_POSITION_AFTER_MH;
6828 : : break;
6829 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT:
6830 [ # # # ]: 0 : switch (h.reformat->action_type) {
6831 : : case MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2:
6832 : : case MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2:
6833 : : pos = MLX5_INDIRECT_LIST_POSITION_BEFORE_MH;
6834 : : break;
6835 : 0 : case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2:
6836 : : case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3:
6837 : : pos = MLX5_INDIRECT_LIST_POSITION_AFTER_MH;
6838 : 0 : break;
6839 : 0 : default:
6840 : : pos = MLX5_INDIRECT_LIST_POSITION_UNKNOWN;
6841 : 0 : break;
6842 : : }
6843 : : break;
6844 : 0 : default:
6845 : : pos = MLX5_INDIRECT_LIST_POSITION_UNKNOWN;
6846 : 0 : break;
6847 : : }
6848 : 0 : return pos;
6849 : : }
6850 : :
6851 : : #define MLX5_HW_EXPAND_MH_FAILED 0xffff
6852 : :
6853 : : static inline uint16_t
6854 : 0 : flow_hw_template_expand_modify_field(struct rte_flow_action actions[],
6855 : : struct rte_flow_action masks[],
6856 : : const struct rte_flow_action *mf_actions,
6857 : : const struct rte_flow_action *mf_masks,
6858 : : uint64_t flags, uint32_t act_num,
6859 : : uint32_t mf_num)
6860 : : {
6861 : : uint32_t i, tail;
6862 : :
6863 : : MLX5_ASSERT(actions && masks);
6864 : : MLX5_ASSERT(mf_num > 0);
6865 [ # # ]: 0 : if (flags & MLX5_FLOW_ACTION_MODIFY_FIELD) {
6866 : : /*
6867 : : * Application action template already has Modify Field.
6868 : : * It's location will be used in DR.
6869 : : * Expanded MF action can be added before the END.
6870 : : */
6871 : 0 : i = act_num - 1;
6872 : 0 : goto insert;
6873 : : }
6874 : : /**
6875 : : * Locate the first action positioned BEFORE the new MF.
6876 : : *
6877 : : * Search for a place to insert modify header
6878 : : * from the END action backwards:
6879 : : * 1. END is always present in actions array
6880 : : * 2. END location is always at action[act_num - 1]
6881 : : * 3. END always positioned AFTER modify field location
6882 : : *
6883 : : * Relative actions order is the same for RX, TX and FDB.
6884 : : *
6885 : : * Current actions order (draft-3)
6886 : : * @see action_order_arr[]
6887 : : */
6888 [ # # ]: 0 : for (i = act_num - 2; (int)i >= 0; i--) {
6889 : : enum mlx5_hw_indirect_list_relative_position pos;
6890 : 0 : enum rte_flow_action_type type = actions[i].type;
6891 : : uint64_t reformat_type;
6892 : :
6893 [ # # ]: 0 : if (type == RTE_FLOW_ACTION_TYPE_INDIRECT)
6894 : 0 : type = masks[i].type;
6895 [ # # # # ]: 0 : switch (type) {
6896 : : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
6897 : : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
6898 : : case RTE_FLOW_ACTION_TYPE_DROP:
6899 : : case RTE_FLOW_ACTION_TYPE_SEND_TO_KERNEL:
6900 : : case RTE_FLOW_ACTION_TYPE_JUMP:
6901 : : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
6902 : : case RTE_FLOW_ACTION_TYPE_QUEUE:
6903 : : case RTE_FLOW_ACTION_TYPE_RSS:
6904 : : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
6905 : : case RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:
6906 : : case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
6907 : : case RTE_FLOW_ACTION_TYPE_VOID:
6908 : : case RTE_FLOW_ACTION_TYPE_END:
6909 : : break;
6910 : : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
6911 : : reformat_type =
6912 : : mlx5_decap_encap_reformat_type(actions, i,
6913 : : flags);
6914 : : if (reformat_type == MLX5_FLOW_ACTION_DECAP) {
6915 : 0 : i++;
6916 : 0 : goto insert;
6917 : : }
6918 [ # # ]: 0 : if (actions[i - 1].type == RTE_FLOW_ACTION_TYPE_RAW_DECAP)
6919 : : i--;
6920 : : break;
6921 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT_LIST:
6922 : 0 : pos = mlx5_hw_indirect_list_mh_position(&actions[i]);
6923 [ # # ]: 0 : if (pos == MLX5_INDIRECT_LIST_POSITION_UNKNOWN)
6924 : : return MLX5_HW_EXPAND_MH_FAILED;
6925 [ # # ]: 0 : if (pos == MLX5_INDIRECT_LIST_POSITION_BEFORE_MH)
6926 : 0 : goto insert;
6927 : : break;
6928 : 0 : default:
6929 : 0 : i++; /* new MF inserted AFTER actions[i] */
6930 : 0 : goto insert;
6931 : : }
6932 : : }
6933 : : i = 0;
6934 : 0 : insert:
6935 : 0 : tail = act_num - i; /* num action to move */
6936 : 0 : memmove(actions + i + mf_num, actions + i, sizeof(actions[0]) * tail);
6937 : 0 : memcpy(actions + i, mf_actions, sizeof(actions[0]) * mf_num);
6938 : 0 : memmove(masks + i + mf_num, masks + i, sizeof(masks[0]) * tail);
6939 : : memcpy(masks + i, mf_masks, sizeof(masks[0]) * mf_num);
6940 : 0 : return i;
6941 : : }
6942 : :
6943 : : static int
6944 : 0 : flow_hw_validate_action_push_vlan(struct rte_eth_dev *dev,
6945 : : const
6946 : : struct rte_flow_actions_template_attr *attr,
6947 : : const struct rte_flow_action *action,
6948 : : const struct rte_flow_action *mask,
6949 : : struct rte_flow_error *error)
6950 : : {
6951 : : #define X_FIELD(ptr, t, f) (((ptr)->conf) && ((t *)((ptr)->conf))->f)
6952 : :
6953 : 0 : const bool masked_push =
6954 [ # # # # ]: 0 : X_FIELD(mask + MLX5_HW_VLAN_PUSH_TYPE_IDX,
6955 : : const struct rte_flow_action_of_push_vlan, ethertype);
6956 : : bool masked_param;
6957 : :
6958 : : /*
6959 : : * Mandatory actions order:
6960 : : * OF_PUSH_VLAN / OF_SET_VLAN_VID [ / OF_SET_VLAN_PCP ]
6961 : : */
6962 : : RTE_SET_USED(dev);
6963 : : RTE_SET_USED(attr);
6964 : : /* Check that mark matches OF_PUSH_VLAN */
6965 [ # # ]: 0 : if (mask[MLX5_HW_VLAN_PUSH_TYPE_IDX].type !=
6966 : : RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN)
6967 : 0 : return rte_flow_error_set(error, EINVAL,
6968 : : RTE_FLOW_ERROR_TYPE_ACTION,
6969 : : action, "OF_PUSH_VLAN: mask does not match");
6970 : : /* Check that the second template and mask items are SET_VLAN_VID */
6971 [ # # ]: 0 : if (action[MLX5_HW_VLAN_PUSH_VID_IDX].type !=
6972 : 0 : RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID ||
6973 [ # # ]: 0 : mask[MLX5_HW_VLAN_PUSH_VID_IDX].type !=
6974 : : RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)
6975 : 0 : return rte_flow_error_set(error, EINVAL,
6976 : : RTE_FLOW_ERROR_TYPE_ACTION,
6977 : : action, "OF_PUSH_VLAN: invalid actions order");
6978 [ # # # # ]: 0 : masked_param = X_FIELD(mask + MLX5_HW_VLAN_PUSH_VID_IDX,
6979 : : const struct rte_flow_action_of_set_vlan_vid,
6980 : : vlan_vid);
6981 : : /*
6982 : : * PMD requires OF_SET_VLAN_VID mask to must match OF_PUSH_VLAN
6983 : : */
6984 [ # # ]: 0 : if (masked_push ^ masked_param)
6985 : 0 : return rte_flow_error_set(error, EINVAL,
6986 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6987 : : "OF_SET_VLAN_VID: mask does not match OF_PUSH_VLAN");
6988 [ # # ]: 0 : if (is_of_vlan_pcp_present(action)) {
6989 [ # # ]: 0 : if (mask[MLX5_HW_VLAN_PUSH_PCP_IDX].type !=
6990 : : RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)
6991 : 0 : return rte_flow_error_set(error, EINVAL,
6992 : : RTE_FLOW_ERROR_TYPE_ACTION,
6993 : : action, "OF_SET_VLAN_PCP: missing mask configuration");
6994 [ # # # # ]: 0 : masked_param = X_FIELD(mask + MLX5_HW_VLAN_PUSH_PCP_IDX,
6995 : : const struct
6996 : : rte_flow_action_of_set_vlan_pcp,
6997 : : vlan_pcp);
6998 : : /*
6999 : : * PMD requires OF_SET_VLAN_PCP mask to must match OF_PUSH_VLAN
7000 : : */
7001 [ # # ]: 0 : if (masked_push ^ masked_param)
7002 : 0 : return rte_flow_error_set(error, EINVAL,
7003 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
7004 : : "OF_SET_VLAN_PCP: mask does not match OF_PUSH_VLAN");
7005 : : }
7006 : : return 0;
7007 : : #undef X_FIELD
7008 : : }
7009 : :
7010 : : static int
7011 : 0 : flow_hw_validate_action_default_miss(const struct rte_flow_actions_template_attr *attr,
7012 : : uint64_t action_flags,
7013 : : struct rte_flow_error *error)
7014 : : {
7015 : : /*
7016 : : * The private DEFAULT_MISS action is used internally for LACP in control
7017 : : * flows. So this validation can be ignored. It can be kept right now since
7018 : : * the validation will be done only once.
7019 : : */
7020 [ # # ]: 0 : if (!attr->ingress || attr->egress || attr->transfer)
7021 : 0 : return rte_flow_error_set(error, EINVAL,
7022 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7023 : : "DEFAULT MISS is only supported in ingress.");
7024 [ # # ]: 0 : if (action_flags & MLX5_FLOW_FATE_ACTIONS)
7025 : 0 : return rte_flow_error_set(error, EINVAL,
7026 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7027 : : "DEFAULT MISS should be the only termination.");
7028 : : return 0;
7029 : : }
7030 : :
7031 : : static int
7032 : 0 : flow_hw_validate_action_nat64(struct rte_eth_dev *dev, struct rte_flow_error *error)
7033 : : {
7034 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
7035 : :
7036 [ # # ]: 0 : if (!flow_hw_should_create_nat64_actions(priv))
7037 : 0 : return rte_flow_error_set(error, EOPNOTSUPP,
7038 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7039 : : "NAT64 action is not supported.");
7040 : :
7041 : : return 0;
7042 : : }
7043 : :
7044 : : static int
7045 : 0 : flow_hw_validate_action_jump(struct rte_eth_dev *dev,
7046 : : const struct rte_flow_actions_template_attr *attr,
7047 : : const struct rte_flow_action *action,
7048 : : const struct rte_flow_action *mask,
7049 : : struct rte_flow_error *error)
7050 : : {
7051 : 0 : const struct rte_flow_action_jump *m = mask->conf;
7052 : 0 : const struct rte_flow_action_jump *v = action->conf;
7053 : 0 : struct mlx5_flow_template_table_cfg cfg = {
7054 : : .external = true,
7055 : : .attr = {
7056 : : .flow_attr = {
7057 : 0 : .ingress = attr->ingress,
7058 : 0 : .egress = attr->egress,
7059 : 0 : .transfer = attr->transfer,
7060 : : },
7061 : : },
7062 : : };
7063 : 0 : uint32_t t_group = 0;
7064 : :
7065 [ # # # # ]: 0 : if (!m || !m->group)
7066 : : return 0;
7067 [ # # ]: 0 : if (!v)
7068 : 0 : return rte_flow_error_set(error, EINVAL,
7069 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
7070 : : "Invalid jump action configuration");
7071 [ # # ]: 0 : if (flow_hw_translate_group(dev, &cfg, v->group, &t_group, error))
7072 : 0 : return -rte_errno;
7073 [ # # ]: 0 : if (t_group == 0)
7074 : 0 : return rte_flow_error_set(error, EINVAL,
7075 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
7076 : : "Unsupported action - jump to root table");
7077 : : return 0;
7078 : : }
7079 : :
7080 : : static int
7081 : 0 : mlx5_flow_validate_action_jump_to_table_index(const struct rte_flow_action *action,
7082 : : const struct rte_flow_action *mask,
7083 : : struct rte_flow_error *error)
7084 : : {
7085 : 0 : const struct rte_flow_action_jump_to_table_index *m = mask->conf;
7086 : 0 : const struct rte_flow_action_jump_to_table_index *v = action->conf;
7087 : : struct mlx5dr_action *jump_action;
7088 : : uint32_t t_group = 0;
7089 : :
7090 [ # # # # ]: 0 : if (!m || !m->table)
7091 : : return 0;
7092 [ # # ]: 0 : if (!v)
7093 : 0 : return rte_flow_error_set(error, EINVAL,
7094 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
7095 : : "Invalid jump to matcher action configuration");
7096 : 0 : t_group = v->table->grp->group_id;
7097 [ # # ]: 0 : if (t_group == 0)
7098 : 0 : return rte_flow_error_set(error, EINVAL,
7099 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
7100 : : "Unsupported action - jump to root table");
7101 [ # # ]: 0 : if (likely(!rte_flow_template_table_resizable(0, &v->table->cfg.attr))) {
7102 : 0 : jump_action = v->table->matcher_info[0].jump;
7103 : : } else {
7104 : : uint32_t selector;
7105 : 0 : rte_rwlock_read_lock(&v->table->matcher_replace_rwlk);
7106 : 0 : selector = v->table->matcher_selector;
7107 : 0 : jump_action = v->table->matcher_info[selector].jump;
7108 : : rte_rwlock_read_unlock(&v->table->matcher_replace_rwlk);
7109 : : }
7110 [ # # ]: 0 : if (jump_action == NULL)
7111 : 0 : return rte_flow_error_set(error, EINVAL,
7112 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
7113 : : "Unsupported action - table is not an rule array");
7114 : : return 0;
7115 : : }
7116 : :
7117 : : static int
7118 : 0 : mlx5_hw_validate_action_mark(struct rte_eth_dev *dev,
7119 : : const struct rte_flow_action *template_action,
7120 : : const struct rte_flow_action *template_mask,
7121 : : uint64_t action_flags,
7122 : : const struct rte_flow_actions_template_attr *template_attr,
7123 : : struct rte_flow_error *error)
7124 : : {
7125 : 0 : const struct rte_flow_action_mark *mark_mask = template_mask->conf;
7126 : : const struct rte_flow_action *action =
7127 [ # # # # ]: 0 : mark_mask && mark_mask->id ? template_action :
7128 : 0 : &(const struct rte_flow_action) {
7129 : : .type = RTE_FLOW_ACTION_TYPE_MARK,
7130 : 0 : .conf = &(const struct rte_flow_action_mark) {
7131 : : .id = MLX5_FLOW_MARK_MAX - 1
7132 : : }
7133 : : };
7134 : 0 : const struct rte_flow_attr attr = {
7135 : 0 : .ingress = template_attr->ingress,
7136 : 0 : .egress = template_attr->egress,
7137 : 0 : .transfer = template_attr->transfer
7138 : : };
7139 : :
7140 [ # # ]: 0 : if (template_attr->transfer &&
7141 [ # # ]: 0 : !MLX5_SH(dev)->cdev->config.hca_attr.fdb_rx_set_flow_tag_stc)
7142 : 0 : return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
7143 : : action,
7144 : : "mark action not supported for transfer");
7145 : :
7146 : 0 : return mlx5_flow_validate_action_mark(dev, action, action_flags,
7147 : : &attr, error);
7148 : : }
7149 : :
7150 : : static int
7151 : 0 : mlx5_hw_validate_action_queue(struct rte_eth_dev *dev,
7152 : : const struct rte_flow_action *template_action,
7153 : : const struct rte_flow_action *template_mask,
7154 : : const struct rte_flow_actions_template_attr *template_attr,
7155 : : uint64_t action_flags,
7156 : : struct rte_flow_error *error)
7157 : : {
7158 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
7159 : 0 : const struct rte_flow_action_queue *queue_mask = template_mask->conf;
7160 : 0 : const struct rte_flow_attr attr = {
7161 : 0 : .ingress = template_attr->ingress,
7162 : 0 : .egress = template_attr->egress,
7163 : 0 : .transfer = template_attr->transfer
7164 : : };
7165 [ # # # # ]: 0 : bool masked = queue_mask != NULL && queue_mask->index;
7166 : :
7167 [ # # # # : 0 : if (template_attr->egress || (template_attr->transfer && !priv->jump_fdb_rx_en))
# # ]
7168 : 0 : return rte_flow_error_set(error, EINVAL,
7169 : : RTE_FLOW_ERROR_TYPE_ATTR, NULL,
7170 : : "QUEUE action supported for ingress only");
7171 [ # # ]: 0 : if (masked)
7172 : 0 : return mlx5_flow_validate_action_queue(template_action, action_flags, dev,
7173 : : &attr, error);
7174 : : else
7175 : : return 0;
7176 : : }
7177 : :
7178 : : static int
7179 : 0 : mlx5_hw_validate_action_rss(struct rte_eth_dev *dev,
7180 : : const struct rte_flow_action *template_action,
7181 : : const struct rte_flow_action *template_mask,
7182 : : const struct rte_flow_actions_template_attr *template_attr,
7183 : : __rte_unused uint64_t action_flags,
7184 : : bool is_indirect,
7185 : : struct rte_flow_error *error)
7186 : : {
7187 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
7188 : 0 : const struct rte_flow_action_rss *mask = template_mask->conf;
7189 : :
7190 [ # # # # : 0 : if (template_attr->egress || (template_attr->transfer && !priv->jump_fdb_rx_en))
# # ]
7191 : 0 : return rte_flow_error_set(error, EINVAL,
7192 : : RTE_FLOW_ERROR_TYPE_ATTR, NULL,
7193 : : "RSS action supported for ingress only");
7194 [ # # ]: 0 : if (is_indirect)
7195 : : return 0;
7196 [ # # ]: 0 : if (mask != NULL)
7197 : 0 : return mlx5_validate_action_rss(dev, template_action, error);
7198 : : else
7199 : : return 0;
7200 : : }
7201 : :
7202 : : static int
7203 : 0 : mlx5_hw_validate_action_l2_encap(struct rte_eth_dev *dev,
7204 : : const struct rte_flow_action *template_action,
7205 : : const struct rte_flow_action *template_mask,
7206 : : const struct rte_flow_actions_template_attr *template_attr,
7207 : : uint64_t action_flags,
7208 : : struct rte_flow_error *error)
7209 : : {
7210 : 0 : const struct rte_flow_action_vxlan_encap default_action_conf = {
7211 : : .definition = (struct rte_flow_item *)
7212 : 0 : (struct rte_flow_item [1]) {
7213 : : [0] = { .type = RTE_FLOW_ITEM_TYPE_END }
7214 : : }
7215 : : };
7216 : 0 : const struct rte_flow_action *action = template_mask->conf ?
7217 [ # # ]: 0 : template_action : &(const struct rte_flow_action) {
7218 : 0 : .type = template_mask->type,
7219 : : .conf = &default_action_conf
7220 : : };
7221 : 0 : const struct rte_flow_attr attr = {
7222 : 0 : .ingress = template_attr->ingress,
7223 : 0 : .egress = template_attr->egress,
7224 : 0 : .transfer = template_attr->transfer
7225 : : };
7226 : :
7227 : 0 : return mlx5_flow_dv_validate_action_l2_encap(dev, action_flags, action,
7228 : : &attr, error);
7229 : : }
7230 : :
7231 : : static int
7232 : 0 : mlx5_hw_validate_action_l2_decap(struct rte_eth_dev *dev,
7233 : : const struct rte_flow_action *template_action,
7234 : : const struct rte_flow_action *template_mask,
7235 : : const struct rte_flow_actions_template_attr *template_attr,
7236 : : uint64_t action_flags,
7237 : : struct rte_flow_error *error)
7238 : : {
7239 : 0 : const struct rte_flow_action_vxlan_encap default_action_conf = {
7240 : : .definition = (struct rte_flow_item *)
7241 : 0 : (struct rte_flow_item [1]) {
7242 : : [0] = { .type = RTE_FLOW_ITEM_TYPE_END }
7243 : : }
7244 : : };
7245 : 0 : const struct rte_flow_action *action = template_mask->conf ?
7246 [ # # ]: 0 : template_action : &(const struct rte_flow_action) {
7247 : 0 : .type = template_mask->type,
7248 : : .conf = &default_action_conf
7249 : : };
7250 : 0 : const struct rte_flow_attr attr = {
7251 : 0 : .ingress = template_attr->ingress,
7252 : 0 : .egress = template_attr->egress,
7253 : 0 : .transfer = template_attr->transfer
7254 : : };
7255 : : uint64_t item_flags =
7256 : 0 : action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
7257 [ # # ]: 0 : MLX5_FLOW_LAYER_VXLAN : 0;
7258 : :
7259 : 0 : return mlx5_flow_dv_validate_action_decap(dev, action_flags, action,
7260 : : item_flags, &attr, error);
7261 : : }
7262 : :
7263 : : static int
7264 : : mlx5_hw_validate_action_conntrack(struct rte_eth_dev *dev,
7265 : : const struct rte_flow_action *template_action,
7266 : : const struct rte_flow_action *template_mask,
7267 : : const struct rte_flow_actions_template_attr *template_attr,
7268 : : uint64_t action_flags,
7269 : : struct rte_flow_error *error)
7270 : : {
7271 : : RTE_SET_USED(template_action);
7272 : : RTE_SET_USED(template_mask);
7273 : : RTE_SET_USED(template_attr);
7274 : 0 : return mlx5_flow_dv_validate_action_aso_ct(dev, action_flags,
7275 : : MLX5_FLOW_LAYER_OUTER_L4_TCP,
7276 : : false, error);
7277 : : }
7278 : :
7279 : : static int
7280 : 0 : flow_hw_validate_action_raw_encap(const struct rte_flow_action *action,
7281 : : const struct rte_flow_action *mask,
7282 : : struct rte_flow_error *error)
7283 : : {
7284 : 0 : const struct rte_flow_action_raw_encap *mask_conf = mask->conf;
7285 : 0 : const struct rte_flow_action_raw_encap *action_conf = action->conf;
7286 : :
7287 [ # # # # ]: 0 : if (!mask_conf || !mask_conf->size)
7288 : 0 : return rte_flow_error_set(error, EINVAL,
7289 : : RTE_FLOW_ERROR_TYPE_ACTION, mask,
7290 : : "raw_encap: size must be masked");
7291 [ # # # # ]: 0 : if (!action_conf || !action_conf->size)
7292 : 0 : return rte_flow_error_set(error, EINVAL,
7293 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
7294 : : "raw_encap: invalid action configuration");
7295 [ # # # # ]: 0 : if (mask_conf->data && !action_conf->data)
7296 : 0 : return rte_flow_error_set(error, EINVAL,
7297 : : RTE_FLOW_ERROR_TYPE_ACTION,
7298 : : action, "raw_encap: masked data is missing");
7299 : : return 0;
7300 : : }
7301 : :
7302 : :
7303 : : static int
7304 : 0 : flow_hw_validate_action_raw_reformat(struct rte_eth_dev *dev,
7305 : : const struct rte_flow_action *template_action,
7306 : : const struct rte_flow_action *template_mask,
7307 : : const struct
7308 : : rte_flow_actions_template_attr *template_attr,
7309 : : uint64_t *action_flags,
7310 : : struct rte_flow_error *error)
7311 : : {
7312 : : const struct rte_flow_action *encap_action = NULL;
7313 : : const struct rte_flow_action *encap_mask = NULL;
7314 : : const struct rte_flow_action_raw_decap *raw_decap = NULL;
7315 : : const struct rte_flow_action_raw_encap *raw_encap = NULL;
7316 : 0 : const struct rte_flow_attr attr = {
7317 : 0 : .ingress = template_attr->ingress,
7318 : 0 : .egress = template_attr->egress,
7319 : 0 : .transfer = template_attr->transfer
7320 : : };
7321 : : uint64_t item_flags = 0;
7322 : 0 : int ret, actions_n = 0;
7323 : :
7324 [ # # ]: 0 : if (template_action->type == RTE_FLOW_ACTION_TYPE_RAW_DECAP) {
7325 : 0 : raw_decap = template_mask->conf ?
7326 [ # # ]: 0 : template_action->conf : &empty_decap;
7327 [ # # ]: 0 : if ((template_action + 1)->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7328 [ # # ]: 0 : if ((template_mask + 1)->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP)
7329 : 0 : return rte_flow_error_set(error, EINVAL,
7330 : : RTE_FLOW_ERROR_TYPE_ACTION,
7331 : 0 : template_mask + 1, "invalid mask type");
7332 : 0 : encap_action = template_action + 1;
7333 : 0 : encap_mask = template_mask + 1;
7334 : : }
7335 : : } else {
7336 : : encap_action = template_action;
7337 : : encap_mask = template_mask;
7338 : : }
7339 [ # # ]: 0 : if (encap_action) {
7340 : 0 : raw_encap = encap_action->conf;
7341 : 0 : ret = flow_hw_validate_action_raw_encap(encap_action,
7342 : : encap_mask, error);
7343 [ # # ]: 0 : if (ret)
7344 : : return ret;
7345 : : }
7346 : 0 : return mlx5_flow_dv_validate_action_raw_encap_decap(dev, raw_decap,
7347 : : raw_encap, &attr,
7348 : : action_flags,
7349 : : &actions_n,
7350 : : template_action,
7351 : : item_flags, error);
7352 : : }
7353 : :
7354 : :
7355 : :
7356 : : static int
7357 : 0 : mlx5_flow_hw_actions_validate(struct rte_eth_dev *dev,
7358 : : const struct rte_flow_actions_template_attr *attr,
7359 : : const struct rte_flow_action actions[],
7360 : : const struct rte_flow_action masks[],
7361 : : uint64_t *act_flags,
7362 : : struct rte_flow_error *error)
7363 : : {
7364 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
7365 : : const struct rte_flow_action_count *count_mask = NULL;
7366 : 0 : bool fixed_cnt = false;
7367 : 0 : uint64_t action_flags = 0;
7368 : : bool actions_end = false;
7369 : : uint16_t i;
7370 : : int ret;
7371 : : const struct rte_flow_action_ipv6_ext_remove *remove_data;
7372 : :
7373 [ # # ]: 0 : if (!mlx5_hw_ctx_validate(dev, error))
7374 : 0 : return -rte_errno;
7375 : : /* FDB actions are only valid to proxy port. */
7376 [ # # # # : 0 : if (attr->transfer && (!priv->sh->config.dv_esw_en || !priv->master))
# # ]
7377 : 0 : return rte_flow_error_set(error, EINVAL,
7378 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7379 : : NULL,
7380 : : "transfer actions are only valid to proxy port");
7381 [ # # ]: 0 : for (i = 0; !actions_end; ++i) {
7382 : 0 : const struct rte_flow_action *action = &actions[i];
7383 : 0 : const struct rte_flow_action *mask = &masks[i];
7384 : :
7385 : : MLX5_ASSERT(i < MLX5_HW_MAX_ACTS);
7386 [ # # ]: 0 : if (action->type != RTE_FLOW_ACTION_TYPE_INDIRECT &&
7387 [ # # ]: 0 : action->type != mask->type)
7388 : 0 : return rte_flow_error_set(error, ENOTSUP,
7389 : : RTE_FLOW_ERROR_TYPE_ACTION,
7390 : : action,
7391 : : "mask type does not match action type");
7392 [ # # # # : 0 : switch ((int)action->type) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # ]
7393 : : case RTE_FLOW_ACTION_TYPE_VOID:
7394 : 0 : break;
7395 : : case RTE_FLOW_ACTION_TYPE_INDIRECT_LIST:
7396 : : break;
7397 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT:
7398 : 0 : ret = flow_hw_validate_action_indirect(dev, action,
7399 : : mask,
7400 : : attr,
7401 : : &action_flags,
7402 : : &fixed_cnt,
7403 : : error);
7404 [ # # ]: 0 : if (ret < 0)
7405 : 0 : return ret;
7406 : : break;
7407 : 0 : case RTE_FLOW_ACTION_TYPE_FLAG:
7408 : : /* TODO: Validation logic */
7409 : 0 : action_flags |= MLX5_FLOW_ACTION_FLAG;
7410 : 0 : break;
7411 : 0 : case RTE_FLOW_ACTION_TYPE_MARK:
7412 : 0 : ret = mlx5_hw_validate_action_mark(dev, action, mask,
7413 : : action_flags,
7414 : : attr, error);
7415 [ # # ]: 0 : if (ret)
7416 : 0 : return ret;
7417 : 0 : action_flags |= MLX5_FLOW_ACTION_MARK;
7418 : 0 : break;
7419 : 0 : case RTE_FLOW_ACTION_TYPE_DROP:
7420 : 0 : ret = mlx5_flow_validate_action_drop
7421 : : (dev, action_flags,
7422 : 0 : &(struct rte_flow_attr){.egress = attr->egress},
7423 : : error);
7424 [ # # ]: 0 : if (ret)
7425 : 0 : return ret;
7426 : 0 : action_flags |= MLX5_FLOW_ACTION_DROP;
7427 : 0 : break;
7428 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP:
7429 : : /* Only validate the jump to root table in template stage. */
7430 : 0 : ret = flow_hw_validate_action_jump(dev, attr, action, mask, error);
7431 [ # # ]: 0 : if (ret)
7432 : 0 : return ret;
7433 : 0 : action_flags |= MLX5_FLOW_ACTION_JUMP;
7434 : 0 : break;
7435 : : #ifdef HAVE_MLX5DV_DR_ACTION_CREATE_DEST_ROOT_TABLE
7436 : : case RTE_FLOW_ACTION_TYPE_SEND_TO_KERNEL:
7437 : : if (priv->shared_host)
7438 : : return rte_flow_error_set(error, ENOTSUP,
7439 : : RTE_FLOW_ERROR_TYPE_ACTION,
7440 : : action,
7441 : : "action not supported in guest port");
7442 : : action_flags |= MLX5_FLOW_ACTION_SEND_TO_KERNEL;
7443 : : break;
7444 : : #endif
7445 : 0 : case RTE_FLOW_ACTION_TYPE_QUEUE:
7446 : 0 : ret = mlx5_hw_validate_action_queue(dev, action, mask,
7447 : : attr, action_flags,
7448 : : error);
7449 [ # # ]: 0 : if (ret)
7450 : 0 : return ret;
7451 : 0 : action_flags |= MLX5_FLOW_ACTION_QUEUE;
7452 : 0 : break;
7453 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
7454 : 0 : ret = mlx5_hw_validate_action_rss(dev, action, mask,
7455 : : attr, action_flags,
7456 : : false, error);
7457 [ # # ]: 0 : if (ret)
7458 : 0 : return ret;
7459 : 0 : action_flags |= MLX5_FLOW_ACTION_RSS;
7460 : 0 : break;
7461 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7462 : : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7463 : 0 : ret = mlx5_hw_validate_action_l2_encap(dev, action, mask,
7464 : : attr, action_flags,
7465 : : error);
7466 [ # # ]: 0 : if (ret)
7467 : 0 : return ret;
7468 : 0 : action_flags |= MLX5_FLOW_ACTION_ENCAP;
7469 : 0 : break;
7470 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7471 : : case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7472 : 0 : ret = mlx5_hw_validate_action_l2_decap(dev, action, mask,
7473 : : attr, action_flags,
7474 : : error);
7475 [ # # ]: 0 : if (ret)
7476 : 0 : return ret;
7477 : 0 : action_flags |= MLX5_FLOW_ACTION_DECAP;
7478 : 0 : break;
7479 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7480 : : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7481 : 0 : ret = flow_hw_validate_action_raw_reformat(dev, action,
7482 : : mask, attr,
7483 : : &action_flags,
7484 : : error);
7485 [ # # ]: 0 : if (ret)
7486 : 0 : return ret;
7487 [ # # ]: 0 : if (action->type == RTE_FLOW_ACTION_TYPE_RAW_DECAP &&
7488 [ # # ]: 0 : (action + 1)->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7489 : 0 : action_flags |= MLX5_FLOW_XCAP_ACTIONS;
7490 : 0 : i++;
7491 : : }
7492 : : break;
7493 : 0 : case RTE_FLOW_ACTION_TYPE_IPV6_EXT_PUSH:
7494 : 0 : ret = flow_hw_validate_action_ipv6_ext_push(dev, action, error);
7495 [ # # ]: 0 : if (ret < 0)
7496 : 0 : return ret;
7497 : 0 : action_flags |= MLX5_FLOW_ACTION_IPV6_ROUTING_PUSH;
7498 : 0 : break;
7499 : 0 : case RTE_FLOW_ACTION_TYPE_IPV6_EXT_REMOVE:
7500 : 0 : remove_data = action->conf;
7501 : : /* Remove action must be shared. */
7502 [ # # # # ]: 0 : if (remove_data->type != IPPROTO_ROUTING || !mask) {
7503 : 0 : DRV_LOG(ERR, "Only supports shared IPv6 routing remove");
7504 : 0 : return -EINVAL;
7505 : : }
7506 : 0 : action_flags |= MLX5_FLOW_ACTION_IPV6_ROUTING_REMOVE;
7507 : 0 : break;
7508 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
7509 : 0 : ret = flow_hw_validate_action_meter_mark(dev, action, false, error);
7510 [ # # ]: 0 : if (ret < 0)
7511 : 0 : return ret;
7512 : 0 : action_flags |= MLX5_FLOW_ACTION_METER;
7513 : 0 : break;
7514 : 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
7515 : 0 : ret = flow_hw_validate_action_modify_field(dev, action, mask,
7516 : : error);
7517 [ # # ]: 0 : if (ret < 0)
7518 : 0 : return ret;
7519 : 0 : action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
7520 : 0 : break;
7521 : 0 : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
7522 : 0 : ret = flow_hw_validate_action_represented_port
7523 : : (dev, action, mask, error);
7524 [ # # ]: 0 : if (ret < 0)
7525 : 0 : return ret;
7526 : 0 : action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7527 : 0 : break;
7528 : 0 : case RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:
7529 : 0 : ret = flow_hw_validate_action_port_representor
7530 : : (dev, attr, action, mask, error);
7531 [ # # ]: 0 : if (ret < 0)
7532 : 0 : return ret;
7533 : 0 : action_flags |= MLX5_FLOW_ACTION_PORT_REPRESENTOR;
7534 : 0 : break;
7535 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
7536 [ # # # # ]: 0 : if (count_mask && count_mask->id)
7537 : 0 : fixed_cnt = true;
7538 : 0 : ret = flow_hw_validate_action_age(dev, action,
7539 : : action_flags,
7540 : : fixed_cnt, error);
7541 [ # # ]: 0 : if (ret < 0)
7542 : 0 : return ret;
7543 : 0 : action_flags |= MLX5_FLOW_ACTION_AGE;
7544 : 0 : break;
7545 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
7546 : 0 : ret = flow_hw_validate_action_count(dev, action, mask,
7547 : : action_flags,
7548 : : error);
7549 [ # # ]: 0 : if (ret < 0)
7550 : 0 : return ret;
7551 : 0 : count_mask = mask->conf;
7552 : 0 : action_flags |= MLX5_FLOW_ACTION_COUNT;
7553 : 0 : break;
7554 : 0 : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
7555 : 0 : ret = mlx5_hw_validate_action_conntrack(dev, action, mask,
7556 : : attr, action_flags,
7557 : : error);
7558 [ # # ]: 0 : if (ret)
7559 : 0 : return ret;
7560 : 0 : action_flags |= MLX5_FLOW_ACTION_CT;
7561 : 0 : break;
7562 : 0 : case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7563 : 0 : action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7564 : 0 : break;
7565 : 0 : case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7566 : 0 : action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7567 : 0 : break;
7568 : 0 : case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7569 : 0 : ret = flow_hw_validate_action_push_vlan
7570 : : (dev, attr, action, mask, error);
7571 [ # # ]: 0 : if (ret != 0)
7572 : 0 : return ret;
7573 : 0 : i += is_of_vlan_pcp_present(action) ?
7574 [ # # ]: 0 : MLX5_HW_VLAN_PUSH_PCP_IDX :
7575 : : MLX5_HW_VLAN_PUSH_VID_IDX;
7576 : 0 : action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7577 : 0 : break;
7578 : 0 : case RTE_FLOW_ACTION_TYPE_NAT64:
7579 : 0 : ret = flow_hw_validate_action_nat64(dev, error);
7580 [ # # ]: 0 : if (ret != 0)
7581 : 0 : return ret;
7582 : 0 : action_flags |= MLX5_FLOW_ACTION_NAT64;
7583 : 0 : break;
7584 : 0 : case RTE_FLOW_ACTION_TYPE_END:
7585 : : actions_end = true;
7586 : 0 : break;
7587 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
7588 : 0 : ret = flow_hw_validate_action_default_miss(attr, action_flags, error);
7589 [ # # ]: 0 : if (ret < 0)
7590 : 0 : return ret;
7591 : 0 : action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
7592 : 0 : break;
7593 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
7594 : 0 : ret = mlx5_flow_validate_action_jump_to_table_index(action, mask, error);
7595 [ # # ]: 0 : if (ret < 0)
7596 : 0 : return ret;
7597 : 0 : action_flags |= MLX5_FLOW_ACTION_JUMP_TO_TABLE_INDEX;
7598 : 0 : break;
7599 : 0 : default:
7600 : 0 : return rte_flow_error_set(error, ENOTSUP,
7601 : : RTE_FLOW_ERROR_TYPE_ACTION,
7602 : : action,
7603 : : "action not supported in template API");
7604 : : }
7605 : : }
7606 [ # # ]: 0 : if (act_flags != NULL)
7607 : 0 : *act_flags = action_flags;
7608 : : return 0;
7609 : : }
7610 : :
7611 : : static int
7612 : 0 : flow_hw_actions_validate(struct rte_eth_dev *dev,
7613 : : const struct rte_flow_actions_template_attr *attr,
7614 : : const struct rte_flow_action actions[],
7615 : : const struct rte_flow_action masks[],
7616 : : struct rte_flow_error *error)
7617 : : {
7618 : 0 : return mlx5_flow_hw_actions_validate(dev, attr, actions, masks, NULL, error);
7619 : : }
7620 : :
7621 : :
7622 : : static enum mlx5dr_action_type mlx5_hw_dr_action_types[] = {
7623 : : [RTE_FLOW_ACTION_TYPE_MARK] = MLX5DR_ACTION_TYP_TAG,
7624 : : [RTE_FLOW_ACTION_TYPE_FLAG] = MLX5DR_ACTION_TYP_TAG,
7625 : : [RTE_FLOW_ACTION_TYPE_DROP] = MLX5DR_ACTION_TYP_DROP,
7626 : : [RTE_FLOW_ACTION_TYPE_JUMP] = MLX5DR_ACTION_TYP_TBL,
7627 : : [RTE_FLOW_ACTION_TYPE_QUEUE] = MLX5DR_ACTION_TYP_TIR,
7628 : : [RTE_FLOW_ACTION_TYPE_RSS] = MLX5DR_ACTION_TYP_TIR,
7629 : : [RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP] = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2,
7630 : : [RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP] = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2,
7631 : : [RTE_FLOW_ACTION_TYPE_VXLAN_DECAP] = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2,
7632 : : [RTE_FLOW_ACTION_TYPE_NVGRE_DECAP] = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2,
7633 : : [RTE_FLOW_ACTION_TYPE_MODIFY_FIELD] = MLX5DR_ACTION_TYP_MODIFY_HDR,
7634 : : [RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT] = MLX5DR_ACTION_TYP_VPORT,
7635 : : [RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR] = MLX5DR_ACTION_TYP_MISS,
7636 : : [RTE_FLOW_ACTION_TYPE_CONNTRACK] = MLX5DR_ACTION_TYP_ASO_CT,
7637 : : [RTE_FLOW_ACTION_TYPE_OF_POP_VLAN] = MLX5DR_ACTION_TYP_POP_VLAN,
7638 : : [RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN] = MLX5DR_ACTION_TYP_PUSH_VLAN,
7639 : : [RTE_FLOW_ACTION_TYPE_SEND_TO_KERNEL] = MLX5DR_ACTION_TYP_DEST_ROOT,
7640 : : [RTE_FLOW_ACTION_TYPE_IPV6_EXT_PUSH] = MLX5DR_ACTION_TYP_PUSH_IPV6_ROUTE_EXT,
7641 : : [RTE_FLOW_ACTION_TYPE_IPV6_EXT_REMOVE] = MLX5DR_ACTION_TYP_POP_IPV6_ROUTE_EXT,
7642 : : [RTE_FLOW_ACTION_TYPE_NAT64] = MLX5DR_ACTION_TYP_NAT64,
7643 : : [RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX] = MLX5DR_ACTION_TYP_JUMP_TO_MATCHER,
7644 : : };
7645 : :
7646 : : static inline void
7647 : : action_template_set_type(struct rte_flow_actions_template *at,
7648 : : enum mlx5dr_action_type *action_types,
7649 : : unsigned int action_src, uint16_t *curr_off,
7650 : : enum mlx5dr_action_type type)
7651 : : {
7652 : 0 : at->dr_off[action_src] = *curr_off;
7653 : 0 : action_types[*curr_off] = type;
7654 : 0 : *curr_off = *curr_off + 1;
7655 : 0 : }
7656 : :
7657 : : static int
7658 : 0 : flow_hw_dr_actions_template_handle_shared(int type, uint32_t action_src,
7659 : : enum mlx5dr_action_type *action_types,
7660 : : uint16_t *curr_off, uint16_t *cnt_off,
7661 : : struct rte_flow_actions_template *at)
7662 : : {
7663 [ # # # # : 0 : switch (type) {
# ]
7664 : : case RTE_FLOW_ACTION_TYPE_RSS:
7665 : : action_template_set_type(at, action_types, action_src, curr_off,
7666 : : MLX5DR_ACTION_TYP_TIR);
7667 : : break;
7668 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
7669 : : case RTE_FLOW_ACTION_TYPE_COUNT:
7670 : : /*
7671 : : * Both AGE and COUNT action need counter, the first one fills
7672 : : * the action_types array, and the second only saves the offset.
7673 : : */
7674 [ # # ]: 0 : if (*cnt_off == UINT16_MAX) {
7675 : 0 : *cnt_off = *curr_off;
7676 : : action_template_set_type(at, action_types,
7677 : : action_src, curr_off,
7678 : : MLX5DR_ACTION_TYP_CTR);
7679 : : }
7680 : 0 : at->dr_off[action_src] = *cnt_off;
7681 : 0 : break;
7682 : : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
7683 : : action_template_set_type(at, action_types, action_src, curr_off,
7684 : : MLX5DR_ACTION_TYP_ASO_CT);
7685 : : break;
7686 : : case RTE_FLOW_ACTION_TYPE_QUOTA:
7687 : : case RTE_FLOW_ACTION_TYPE_METER_MARK:
7688 : : action_template_set_type(at, action_types, action_src, curr_off,
7689 : : MLX5DR_ACTION_TYP_ASO_METER);
7690 : : break;
7691 : 0 : default:
7692 : 0 : DRV_LOG(WARNING, "Unsupported shared action type: %d", type);
7693 : 0 : return -EINVAL;
7694 : : }
7695 : : return 0;
7696 : : }
7697 : :
7698 : :
7699 : : static int
7700 : 0 : flow_hw_template_actions_list(struct rte_flow_actions_template *at,
7701 : : unsigned int action_src,
7702 : : enum mlx5dr_action_type *action_types,
7703 : : uint16_t *curr_off, uint16_t *cnt_off)
7704 : : {
7705 : : int ret;
7706 : 0 : const struct rte_flow_action_indirect_list *indlst_conf = at->actions[action_src].conf;
7707 [ # # # # ]: 0 : enum mlx5_indirect_list_type list_type = mlx5_get_indirect_list_type(indlst_conf->handle);
7708 : : const union {
7709 : : struct mlx5_indlst_legacy *legacy;
7710 : : struct rte_flow_action_list_handle *handle;
7711 : : } indlst_obj = { .handle = indlst_conf->handle };
7712 : : enum mlx5dr_action_type type;
7713 : :
7714 [ # # # # ]: 0 : switch (list_type) {
7715 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY:
7716 : 0 : ret = flow_hw_dr_actions_template_handle_shared
7717 : 0 : (indlst_obj.legacy->legacy_type, action_src,
7718 : : action_types, curr_off, cnt_off, at);
7719 [ # # ]: 0 : if (ret)
7720 : 0 : return ret;
7721 : : break;
7722 : : case MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR:
7723 : : action_template_set_type(at, action_types, action_src, curr_off,
7724 : : MLX5DR_ACTION_TYP_DEST_ARRAY);
7725 : : break;
7726 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT:
7727 : 0 : type = ((struct mlx5_hw_encap_decap_action *)
7728 : : (indlst_conf->handle))->action_type;
7729 : : action_template_set_type(at, action_types, action_src, curr_off, type);
7730 : : break;
7731 : 0 : default:
7732 : 0 : DRV_LOG(ERR, "Unsupported indirect list type");
7733 : 0 : return -EINVAL;
7734 : : }
7735 : : return 0;
7736 : : }
7737 : :
7738 : : /**
7739 : : * Create DR action template based on a provided sequence of flow actions.
7740 : : *
7741 : : * @param[in] dev
7742 : : * Pointer to the rte_eth_dev structure.
7743 : : * @param[in] at
7744 : : * Pointer to flow actions template to be updated.
7745 : : * @param[out] action_types
7746 : : * Action types array to be filled.
7747 : : * @param[out] tmpl_flags
7748 : : * Template DR flags to be filled.
7749 : : *
7750 : : * @return
7751 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
7752 : : */
7753 : : static int
7754 : 0 : flow_hw_parse_flow_actions_to_dr_actions(struct rte_eth_dev *dev,
7755 : : struct rte_flow_actions_template *at,
7756 : : enum mlx5dr_action_type action_types[MLX5_HW_MAX_ACTS],
7757 : : uint32_t *tmpl_flags __rte_unused)
7758 : : {
7759 : : unsigned int i;
7760 : : uint16_t curr_off;
7761 : : enum mlx5dr_action_type reformat_act_type = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2;
7762 : : uint16_t reformat_off = UINT16_MAX;
7763 : : uint16_t mhdr_off = UINT16_MAX;
7764 : : uint16_t recom_off = UINT16_MAX;
7765 : 0 : uint16_t cnt_off = UINT16_MAX;
7766 : : enum mlx5dr_action_type recom_type = MLX5DR_ACTION_TYP_LAST;
7767 : : int ret;
7768 : :
7769 [ # # ]: 0 : for (i = 0, curr_off = 0; at->actions[i].type != RTE_FLOW_ACTION_TYPE_END; ++i) {
7770 : : const struct rte_flow_action_raw_encap *raw_encap_data;
7771 : : size_t data_size;
7772 : : enum mlx5dr_action_type type;
7773 : :
7774 [ # # ]: 0 : if (curr_off >= MLX5_HW_MAX_ACTS)
7775 : 0 : goto err_actions_num;
7776 [ # # # # : 0 : switch ((int)at->actions[i].type) {
# # # # #
# # # # #
# # # ]
7777 : : case RTE_FLOW_ACTION_TYPE_VOID:
7778 : : break;
7779 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT_LIST:
7780 : 0 : ret = flow_hw_template_actions_list(at, i, action_types,
7781 : : &curr_off, &cnt_off);
7782 [ # # ]: 0 : if (ret)
7783 : 0 : return ret;
7784 : : break;
7785 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT:
7786 : 0 : ret = flow_hw_dr_actions_template_handle_shared
7787 : 0 : (at->masks[i].type, i, action_types,
7788 : : &curr_off, &cnt_off, at);
7789 [ # # ]: 0 : if (ret)
7790 : 0 : return ret;
7791 : : break;
7792 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7793 : : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7794 : : case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7795 : : case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7796 : : MLX5_ASSERT(reformat_off == UINT16_MAX);
7797 : 0 : reformat_off = curr_off++;
7798 : 0 : reformat_act_type = mlx5_hw_dr_action_types[at->actions[i].type];
7799 : 0 : break;
7800 : 0 : case RTE_FLOW_ACTION_TYPE_IPV6_EXT_PUSH:
7801 : : MLX5_ASSERT(recom_off == UINT16_MAX);
7802 : : recom_type = MLX5DR_ACTION_TYP_PUSH_IPV6_ROUTE_EXT;
7803 : 0 : recom_off = curr_off++;
7804 : 0 : break;
7805 : 0 : case RTE_FLOW_ACTION_TYPE_IPV6_EXT_REMOVE:
7806 : : MLX5_ASSERT(recom_off == UINT16_MAX);
7807 : : recom_type = MLX5DR_ACTION_TYP_POP_IPV6_ROUTE_EXT;
7808 : 0 : recom_off = curr_off++;
7809 : 0 : break;
7810 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7811 : 0 : raw_encap_data = at->actions[i].conf;
7812 : 0 : data_size = raw_encap_data->size;
7813 [ # # ]: 0 : if (reformat_off != UINT16_MAX) {
7814 : : reformat_act_type = data_size < MLX5_ENCAPSULATION_DECISION_SIZE ?
7815 [ # # ]: 0 : MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2 :
7816 : : MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3;
7817 : : } else {
7818 : 0 : reformat_off = curr_off++;
7819 : : reformat_act_type = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;
7820 : : }
7821 : : break;
7822 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7823 : 0 : reformat_off = curr_off++;
7824 : : reformat_act_type = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2;
7825 : 0 : break;
7826 : 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
7827 [ # # ]: 0 : if (mhdr_off == UINT16_MAX) {
7828 : 0 : mhdr_off = curr_off++;
7829 : 0 : type = mlx5_hw_dr_action_types[at->actions[i].type];
7830 : 0 : action_types[mhdr_off] = type;
7831 : : }
7832 : : break;
7833 : 0 : case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7834 : 0 : type = mlx5_hw_dr_action_types[at->actions[i].type];
7835 : 0 : at->dr_off[i] = curr_off;
7836 : 0 : action_types[curr_off++] = type;
7837 : 0 : i += is_of_vlan_pcp_present(at->actions + i) ?
7838 [ # # ]: 0 : MLX5_HW_VLAN_PUSH_PCP_IDX :
7839 : : MLX5_HW_VLAN_PUSH_VID_IDX;
7840 : 0 : break;
7841 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
7842 : 0 : at->dr_off[i] = curr_off;
7843 : 0 : action_types[curr_off++] = MLX5DR_ACTION_TYP_ASO_METER;
7844 [ # # ]: 0 : if (curr_off >= MLX5_HW_MAX_ACTS)
7845 : 0 : goto err_actions_num;
7846 : : break;
7847 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
7848 : : case RTE_FLOW_ACTION_TYPE_COUNT:
7849 : : /*
7850 : : * Both AGE and COUNT action need counter, the first
7851 : : * one fills the action_types array, and the second only
7852 : : * saves the offset.
7853 : : */
7854 [ # # ]: 0 : if (cnt_off == UINT16_MAX) {
7855 : 0 : cnt_off = curr_off++;
7856 : 0 : action_types[cnt_off] = MLX5DR_ACTION_TYP_CTR;
7857 : : }
7858 : 0 : at->dr_off[i] = cnt_off;
7859 : 0 : break;
7860 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
7861 : 0 : at->dr_off[i] = curr_off;
7862 : 0 : action_types[curr_off++] = MLX5DR_ACTION_TYP_MISS;
7863 : 0 : break;
7864 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
7865 : 0 : *tmpl_flags |= MLX5DR_ACTION_TEMPLATE_FLAG_RELAXED_ORDER;
7866 : 0 : at->dr_off[i] = curr_off;
7867 : 0 : action_types[curr_off++] = MLX5DR_ACTION_TYP_JUMP_TO_MATCHER;
7868 : 0 : break;
7869 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_MIRROR:
7870 : 0 : at->dr_off[i] = curr_off;
7871 : 0 : action_types[curr_off++] = MLX5DR_ACTION_TYP_DEST_ARRAY;
7872 : 0 : break;
7873 : 0 : case RTE_FLOW_ACTION_TYPE_PORT_ID:
7874 : 0 : DRV_LOG(ERR, "RTE_FLOW_ACTION_TYPE_PORT_ID action is not supported. "
7875 : : "Use RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT instead.");
7876 : 0 : return -EINVAL;
7877 : 0 : default:
7878 : 0 : type = mlx5_hw_dr_action_types[at->actions[i].type];
7879 : 0 : at->dr_off[i] = curr_off;
7880 : 0 : action_types[curr_off++] = type;
7881 : 0 : break;
7882 : : }
7883 : : }
7884 [ # # ]: 0 : if (curr_off >= MLX5_HW_MAX_ACTS)
7885 : 0 : goto err_actions_num;
7886 [ # # ]: 0 : if (mhdr_off != UINT16_MAX)
7887 : 0 : at->mhdr_off = mhdr_off;
7888 [ # # ]: 0 : if (reformat_off != UINT16_MAX) {
7889 : 0 : at->reformat_off = reformat_off;
7890 : 0 : action_types[reformat_off] = reformat_act_type;
7891 : : }
7892 [ # # ]: 0 : if (recom_off != UINT16_MAX) {
7893 : 0 : at->recom_off = recom_off;
7894 : 0 : action_types[recom_off] = recom_type;
7895 : : }
7896 : 0 : at->dr_actions_num = curr_off;
7897 : :
7898 : : /* Create srh flex parser for remove anchor. */
7899 [ # # ]: 0 : if ((recom_type == MLX5DR_ACTION_TYP_POP_IPV6_ROUTE_EXT ||
7900 [ # # ]: 0 : recom_type == MLX5DR_ACTION_TYP_PUSH_IPV6_ROUTE_EXT) &&
7901 : 0 : (ret = mlx5_alloc_srh_flex_parser(dev))) {
7902 : 0 : DRV_LOG(ERR, "Failed to create srv6 flex parser");
7903 : 0 : return ret;
7904 : : }
7905 : : return 0;
7906 : 0 : err_actions_num:
7907 : 0 : DRV_LOG(ERR, "Number of HW actions (%u) exceeded maximum (%u) allowed in template",
7908 : : curr_off, MLX5_HW_MAX_ACTS);
7909 : 0 : return -EINVAL;
7910 : : }
7911 : :
7912 : : static int
7913 : 0 : flow_hw_set_vlan_vid(struct rte_eth_dev *dev,
7914 : : struct rte_flow_action *ra,
7915 : : struct rte_flow_action *rm,
7916 : : struct rte_flow_action_modify_field *spec,
7917 : : struct rte_flow_action_modify_field *mask,
7918 : : int set_vlan_vid_ix,
7919 : : struct rte_flow_error *error)
7920 : : {
7921 [ # # ]: 0 : const bool masked = rm[set_vlan_vid_ix].conf &&
7922 : : (((const struct rte_flow_action_of_set_vlan_vid *)
7923 [ # # ]: 0 : rm[set_vlan_vid_ix].conf)->vlan_vid != 0);
7924 : 0 : const struct rte_flow_action_of_set_vlan_vid *conf =
7925 : 0 : ra[set_vlan_vid_ix].conf;
7926 : 0 : int width = mlx5_flow_item_field_width(dev, RTE_FLOW_FIELD_VLAN_ID, 0,
7927 : : NULL, error);
7928 : : MLX5_ASSERT(width);
7929 : 0 : *spec = (typeof(*spec)) {
7930 : : .operation = RTE_FLOW_MODIFY_SET,
7931 : : .dst = {
7932 : : .field = RTE_FLOW_FIELD_VLAN_ID,
7933 : : .level = 0, .offset = 0,
7934 : : },
7935 : : .src = {
7936 : : .field = RTE_FLOW_FIELD_VALUE,
7937 : : },
7938 : : .width = width,
7939 : : };
7940 : 0 : *mask = (typeof(*mask)) {
7941 : : .operation = RTE_FLOW_MODIFY_SET,
7942 : : .dst = {
7943 : : .field = RTE_FLOW_FIELD_VLAN_ID,
7944 : : .level = 0xff, .offset = 0xffffffff,
7945 : : },
7946 : : .src = {
7947 : : .field = RTE_FLOW_FIELD_VALUE,
7948 : : },
7949 : : .width = 0xffffffff,
7950 : : };
7951 [ # # ]: 0 : if (masked) {
7952 : : uint32_t mask_val = 0xffffffff;
7953 : :
7954 : : rte_memcpy(spec->src.value, &conf->vlan_vid, sizeof(conf->vlan_vid));
7955 : : rte_memcpy(mask->src.value, &mask_val, sizeof(mask_val));
7956 : : }
7957 : 0 : ra[set_vlan_vid_ix].type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD;
7958 : 0 : ra[set_vlan_vid_ix].conf = spec;
7959 : 0 : rm[set_vlan_vid_ix].type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD;
7960 : 0 : rm[set_vlan_vid_ix].conf = mask;
7961 : 0 : return 0;
7962 : : }
7963 : :
7964 : : static __rte_always_inline int
7965 : : flow_hw_set_vlan_vid_construct(struct rte_eth_dev *dev,
7966 : : struct mlx5_modification_cmd *mhdr_cmd,
7967 : : struct mlx5_action_construct_data *act_data,
7968 : : const struct mlx5_hw_actions *hw_acts,
7969 : : const struct rte_flow_action *action)
7970 : : {
7971 : : struct rte_flow_error error;
7972 : : rte_be16_t vid = ((const struct rte_flow_action_of_set_vlan_vid *)
7973 : 0 : action->conf)->vlan_vid;
7974 : 0 : int width = mlx5_flow_item_field_width(dev, RTE_FLOW_FIELD_VLAN_ID, 0,
7975 : : NULL, &error);
7976 [ # # # # : 0 : struct rte_flow_action_modify_field conf = {
# # # # #
# ]
7977 : : .operation = RTE_FLOW_MODIFY_SET,
7978 : : .dst = {
7979 : : .field = RTE_FLOW_FIELD_VLAN_ID,
7980 : : .level = 0, .offset = 0,
7981 : : },
7982 : : .src = {
7983 : : .field = RTE_FLOW_FIELD_VALUE,
7984 : : },
7985 : : .width = width,
7986 : : };
7987 : : struct rte_flow_action modify_action = {
7988 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
7989 : : .conf = &conf
7990 : : };
7991 : :
7992 : : rte_memcpy(conf.src.value, &vid, sizeof(vid));
7993 : : return flow_hw_modify_field_construct(mhdr_cmd, act_data, hw_acts, &modify_action);
7994 : : }
7995 : :
7996 : : static int
7997 : 0 : flow_hw_flex_item_acquire(struct rte_eth_dev *dev,
7998 : : struct rte_flow_item_flex_handle *handle,
7999 : : uint8_t *flex_item)
8000 : : {
8001 : 0 : int index = mlx5_flex_acquire_index(dev, handle, false);
8002 : :
8003 : : MLX5_ASSERT(index >= 0 && index < (int)(sizeof(uint32_t) * CHAR_BIT));
8004 [ # # ]: 0 : if (index < 0)
8005 : : return -1;
8006 [ # # ]: 0 : if (!(*flex_item & RTE_BIT32(index))) {
8007 : : /* Don't count same flex item again. */
8008 : 0 : if (mlx5_flex_acquire_index(dev, handle, true) != index)
8009 : : MLX5_ASSERT(false);
8010 : 0 : *flex_item |= (uint8_t)RTE_BIT32(index);
8011 : : }
8012 : : return 0;
8013 : : }
8014 : :
8015 : : static void
8016 : 0 : flow_hw_flex_item_release(struct rte_eth_dev *dev, uint8_t *flex_item)
8017 : : {
8018 [ # # ]: 0 : while (*flex_item) {
8019 : 0 : int index = rte_bsf32(*flex_item);
8020 : :
8021 : 0 : mlx5_flex_release_index(dev, index);
8022 : 0 : *flex_item &= ~(uint8_t)RTE_BIT32(index);
8023 : : }
8024 : 0 : }
8025 : : static __rte_always_inline void
8026 : : flow_hw_actions_template_replace_container(const
8027 : : struct rte_flow_action *actions,
8028 : : const
8029 : : struct rte_flow_action *masks,
8030 : : struct rte_flow_action *new_actions,
8031 : : struct rte_flow_action *new_masks,
8032 : : struct rte_flow_action **ra,
8033 : : struct rte_flow_action **rm,
8034 : : uint32_t act_num)
8035 : : {
8036 : 0 : memcpy(new_actions, actions, sizeof(actions[0]) * act_num);
8037 : : memcpy(new_masks, masks, sizeof(masks[0]) * act_num);
8038 : : *ra = (void *)(uintptr_t)new_actions;
8039 : : *rm = (void *)(uintptr_t)new_masks;
8040 : 0 : }
8041 : :
8042 : : /* Action template copies these actions in rte_flow_conv() */
8043 : :
8044 : : static const struct rte_flow_action rx_meta_copy_action = {
8045 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
8046 : : .conf = &(struct rte_flow_action_modify_field){
8047 : : .operation = RTE_FLOW_MODIFY_SET,
8048 : : .dst = {
8049 : : .field = (enum rte_flow_field_id)
8050 : : MLX5_RTE_FLOW_FIELD_META_REG,
8051 : : .tag_index = REG_B,
8052 : : },
8053 : : .src = {
8054 : : .field = (enum rte_flow_field_id)
8055 : : MLX5_RTE_FLOW_FIELD_META_REG,
8056 : : .tag_index = REG_C_1,
8057 : : },
8058 : : .width = 32,
8059 : : }
8060 : : };
8061 : :
8062 : : static const struct rte_flow_action rx_meta_copy_mask = {
8063 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
8064 : : .conf = &(struct rte_flow_action_modify_field){
8065 : : .operation = RTE_FLOW_MODIFY_SET,
8066 : : .dst = {
8067 : : .field = (enum rte_flow_field_id)
8068 : : MLX5_RTE_FLOW_FIELD_META_REG,
8069 : : .level = UINT8_MAX,
8070 : : .tag_index = UINT8_MAX,
8071 : : .offset = UINT32_MAX,
8072 : : },
8073 : : .src = {
8074 : : .field = (enum rte_flow_field_id)
8075 : : MLX5_RTE_FLOW_FIELD_META_REG,
8076 : : .level = UINT8_MAX,
8077 : : .tag_index = UINT8_MAX,
8078 : : .offset = UINT32_MAX,
8079 : : },
8080 : : .width = UINT32_MAX,
8081 : : }
8082 : : };
8083 : :
8084 : : static const struct rte_flow_action quota_color_inc_action = {
8085 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
8086 : : .conf = &(struct rte_flow_action_modify_field) {
8087 : : .operation = RTE_FLOW_MODIFY_ADD,
8088 : : .dst = {
8089 : : .field = RTE_FLOW_FIELD_METER_COLOR,
8090 : : .level = 0, .offset = 0
8091 : : },
8092 : : .src = {
8093 : : .field = RTE_FLOW_FIELD_VALUE,
8094 : : .level = 1,
8095 : : .offset = 0,
8096 : : },
8097 : : .width = 2
8098 : : }
8099 : : };
8100 : :
8101 : : static const struct rte_flow_action quota_color_inc_mask = {
8102 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
8103 : : .conf = &(struct rte_flow_action_modify_field) {
8104 : : .operation = RTE_FLOW_MODIFY_ADD,
8105 : : .dst = {
8106 : : .field = RTE_FLOW_FIELD_METER_COLOR,
8107 : : .level = UINT8_MAX,
8108 : : .tag_index = UINT8_MAX,
8109 : : .offset = UINT32_MAX,
8110 : : },
8111 : : .src = {
8112 : : .field = RTE_FLOW_FIELD_VALUE,
8113 : : .level = 3,
8114 : : .offset = 0
8115 : : },
8116 : : .width = UINT32_MAX
8117 : : }
8118 : : };
8119 : :
8120 : : /**
8121 : : * Create flow action template.
8122 : : *
8123 : : * @param[in] dev
8124 : : * Pointer to the rte_eth_dev structure.
8125 : : * @param[in] attr
8126 : : * Pointer to the action template attributes.
8127 : : * @param[in] actions
8128 : : * Associated actions (list terminated by the END action).
8129 : : * @param[in] masks
8130 : : * List of actions that marks which of the action's member is constant.
8131 : : * @param[in] nt_mode
8132 : : * Non template mode.
8133 : : * @param[out] error
8134 : : * Pointer to error structure.
8135 : : *
8136 : : * @return
8137 : : * Action template pointer on success, NULL otherwise and rte_errno is set.
8138 : : */
8139 : : static struct rte_flow_actions_template *
8140 : 0 : __flow_hw_actions_template_create(struct rte_eth_dev *dev,
8141 : : const struct rte_flow_actions_template_attr *attr,
8142 : : const struct rte_flow_action actions[],
8143 : : const struct rte_flow_action masks[],
8144 : : bool nt_mode,
8145 : : struct rte_flow_error *error)
8146 : : {
8147 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
8148 : : int len, act_len, mask_len;
8149 : : int orig_act_len;
8150 : : unsigned int act_num;
8151 : : unsigned int i;
8152 : : struct rte_flow_actions_template *at = NULL;
8153 : : uint16_t pos;
8154 : 0 : uint64_t action_flags = 0;
8155 : : struct rte_flow_action tmp_action[MLX5_HW_MAX_ACTS];
8156 : : struct rte_flow_action tmp_mask[MLX5_HW_MAX_ACTS];
8157 : : struct rte_flow_action *ra = (void *)(uintptr_t)actions;
8158 : : struct rte_flow_action *rm = (void *)(uintptr_t)masks;
8159 : : int set_vlan_vid_ix = -1;
8160 : 0 : struct rte_flow_action_modify_field set_vlan_vid_spec = {0, };
8161 : 0 : struct rte_flow_action_modify_field set_vlan_vid_mask = {0, };
8162 : : struct rte_flow_action mf_actions[MLX5_HW_MAX_ACTS];
8163 : : struct rte_flow_action mf_masks[MLX5_HW_MAX_ACTS];
8164 : : uint32_t expand_mf_num = 0;
8165 : 0 : uint16_t src_off[MLX5_HW_MAX_ACTS] = {0, };
8166 : 0 : enum mlx5dr_action_type action_types[MLX5_HW_MAX_ACTS] = { MLX5DR_ACTION_TYP_LAST };
8167 : 0 : uint32_t tmpl_flags = 0;
8168 : : int ret;
8169 : :
8170 [ # # # # ]: 0 : if (!nt_mode && mlx5_flow_hw_actions_validate(dev, attr, actions, masks,
8171 : : &action_flags, error))
8172 : : return NULL;
8173 [ # # ]: 0 : for (i = 0; ra[i].type != RTE_FLOW_ACTION_TYPE_END; ++i) {
8174 [ # # # ]: 0 : switch (ra[i].type) {
8175 : : /* OF_PUSH_VLAN *MUST* come before OF_SET_VLAN_VID */
8176 : 0 : case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
8177 : 0 : i += is_of_vlan_pcp_present(ra + i) ?
8178 [ # # ]: 0 : MLX5_HW_VLAN_PUSH_PCP_IDX :
8179 : : MLX5_HW_VLAN_PUSH_VID_IDX;
8180 : 0 : break;
8181 : 0 : case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
8182 : 0 : set_vlan_vid_ix = i;
8183 : 0 : break;
8184 : : default:
8185 : : break;
8186 : : }
8187 : : }
8188 : : /*
8189 : : * Count flow actions to allocate required space for storing DR offsets and to check
8190 : : * if temporary buffer would not be overrun.
8191 : : */
8192 : 0 : act_num = i + 1;
8193 [ # # ]: 0 : if (act_num >= MLX5_HW_MAX_ACTS) {
8194 : 0 : rte_flow_error_set(error, EINVAL,
8195 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL, "Too many actions");
8196 : 0 : return NULL;
8197 : : }
8198 [ # # ]: 0 : if (set_vlan_vid_ix != -1) {
8199 : : /* If temporary action buffer was not used, copy template actions to it */
8200 : : if (ra == actions)
8201 : : flow_hw_actions_template_replace_container(actions,
8202 : : masks,
8203 : : tmp_action,
8204 : : tmp_mask,
8205 : : &ra, &rm,
8206 : : act_num);
8207 : 0 : ret = flow_hw_set_vlan_vid(dev, ra, rm,
8208 : : &set_vlan_vid_spec, &set_vlan_vid_mask,
8209 : : set_vlan_vid_ix, error);
8210 [ # # ]: 0 : if (ret)
8211 : 0 : goto error;
8212 : 0 : action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
8213 : : }
8214 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_QUOTA) {
8215 : 0 : mf_actions[expand_mf_num] = quota_color_inc_action;
8216 : 0 : mf_masks[expand_mf_num] = quota_color_inc_mask;
8217 : : expand_mf_num++;
8218 : : }
8219 [ # # ]: 0 : if (attr->ingress &&
8220 [ # # ]: 0 : (action_flags & (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS))) {
8221 [ # # ]: 0 : if ((priv->sh->config.dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS &&
8222 [ # # ]: 0 : priv->sh->config.dv_esw_en) ||
8223 : 0 : mlx5_vport_rx_metadata_passing_enabled(priv->sh)) {
8224 : : /* Insert META copy */
8225 : 0 : mf_actions[expand_mf_num] = rx_meta_copy_action;
8226 : 0 : mf_masks[expand_mf_num] = rx_meta_copy_mask;
8227 : 0 : expand_mf_num++;
8228 : : MLX5_ASSERT(expand_mf_num <= MLX5_HW_MAX_ACTS);
8229 : : }
8230 : : }
8231 [ # # ]: 0 : if (expand_mf_num) {
8232 [ # # ]: 0 : if (act_num + expand_mf_num > MLX5_HW_MAX_ACTS) {
8233 : 0 : rte_flow_error_set(error, E2BIG,
8234 : : RTE_FLOW_ERROR_TYPE_ACTION,
8235 : : NULL, "cannot expand: too many actions");
8236 : 0 : return NULL;
8237 : : }
8238 [ # # ]: 0 : if (ra == actions)
8239 : : flow_hw_actions_template_replace_container(actions,
8240 : : masks,
8241 : : tmp_action,
8242 : : tmp_mask,
8243 : : &ra, &rm,
8244 : : act_num);
8245 : : /* Application should make sure only one Q/RSS exist in one rule. */
8246 : 0 : pos = flow_hw_template_expand_modify_field(ra, rm,
8247 : : mf_actions,
8248 : : mf_masks,
8249 : : action_flags,
8250 : : act_num,
8251 : : expand_mf_num);
8252 [ # # ]: 0 : if (pos == MLX5_HW_EXPAND_MH_FAILED) {
8253 : 0 : rte_flow_error_set(error, ENOMEM,
8254 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8255 : : NULL, "modify header expansion failed");
8256 : 0 : return NULL;
8257 : : }
8258 : : act_num += expand_mf_num;
8259 [ # # ]: 0 : for (i = pos + expand_mf_num; i < act_num; i++)
8260 : 0 : src_off[i] += expand_mf_num;
8261 : 0 : action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
8262 : : }
8263 : 0 : act_len = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, NULL, 0, ra, error);
8264 [ # # ]: 0 : if (act_len <= 0)
8265 : : return NULL;
8266 : 0 : len = RTE_ALIGN(act_len, 16);
8267 : 0 : mask_len = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, NULL, 0, rm, error);
8268 [ # # ]: 0 : if (mask_len <= 0)
8269 : : return NULL;
8270 : 0 : len += RTE_ALIGN(mask_len, 16);
8271 : 0 : len += RTE_ALIGN(act_num * sizeof(*at->dr_off), 16);
8272 : 0 : len += RTE_ALIGN(act_num * sizeof(*at->src_off), 16);
8273 : 0 : orig_act_len = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, NULL, 0, actions, error);
8274 [ # # ]: 0 : if (orig_act_len <= 0)
8275 : : return NULL;
8276 : 0 : len += RTE_ALIGN(orig_act_len, 16);
8277 : 0 : at = mlx5_malloc(MLX5_MEM_ZERO, len + sizeof(*at),
8278 : : RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
8279 [ # # ]: 0 : if (!at) {
8280 : 0 : rte_flow_error_set(error, ENOMEM,
8281 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8282 : : NULL,
8283 : : "cannot allocate action template");
8284 : 0 : return NULL;
8285 : : }
8286 : : /* Actions part is in the first part. */
8287 : 0 : at->attr = *attr;
8288 : 0 : at->actions = (struct rte_flow_action *)(at + 1);
8289 : 0 : act_len = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, at->actions,
8290 : : len, ra, error);
8291 [ # # ]: 0 : if (act_len <= 0)
8292 : 0 : goto error;
8293 : : /* Masks part is in the second part. */
8294 : 0 : at->masks = (struct rte_flow_action *)(((uint8_t *)at->actions) + act_len);
8295 : 0 : mask_len = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, at->masks,
8296 : 0 : len - act_len, rm, error);
8297 [ # # ]: 0 : if (mask_len <= 0)
8298 : 0 : goto error;
8299 : : /* DR actions offsets in the third part. */
8300 : 0 : at->dr_off = (uint16_t *)((uint8_t *)at->masks + mask_len);
8301 : 0 : at->src_off = RTE_PTR_ADD(at->dr_off,
8302 : : RTE_ALIGN(act_num * sizeof(*at->dr_off), 16));
8303 : : memcpy(at->src_off, src_off, act_num * sizeof(at->src_off[0]));
8304 : 0 : at->orig_actions = RTE_PTR_ADD(at->src_off,
8305 : : RTE_ALIGN(act_num * sizeof(*at->src_off), 16));
8306 : 0 : orig_act_len = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, at->orig_actions, orig_act_len,
8307 : : actions, error);
8308 [ # # ]: 0 : if (orig_act_len <= 0)
8309 : 0 : goto error;
8310 : 0 : at->actions_num = act_num;
8311 [ # # ]: 0 : for (i = 0; i < at->actions_num; ++i)
8312 : 0 : at->dr_off[i] = UINT16_MAX;
8313 : 0 : at->reformat_off = UINT16_MAX;
8314 : 0 : at->mhdr_off = UINT16_MAX;
8315 : 0 : at->recom_off = UINT16_MAX;
8316 [ # # ]: 0 : for (i = 0; actions->type != RTE_FLOW_ACTION_TYPE_END;
8317 : 0 : actions++, masks++, i++) {
8318 : : const struct rte_flow_action_modify_field *info;
8319 : :
8320 [ # # # ]: 0 : switch (actions->type) {
8321 : : /*
8322 : : * mlx5 PMD hacks indirect action index directly to the action conf.
8323 : : * The rte_flow_conv() function copies the content from conf pointer.
8324 : : * Need to restore the indirect action index from action conf here.
8325 : : */
8326 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT:
8327 : 0 : at->actions[i].conf = ra[i].conf;
8328 : 0 : at->masks[i].conf = rm[i].conf;
8329 : 0 : break;
8330 : 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
8331 : 0 : info = actions->conf;
8332 [ # # # # ]: 0 : if ((info->dst.field == RTE_FLOW_FIELD_FLEX_ITEM &&
8333 : 0 : flow_hw_flex_item_acquire(dev, info->dst.flex_handle,
8334 : 0 : &at->flex_item)) ||
8335 [ # # # # ]: 0 : (info->src.field == RTE_FLOW_FIELD_FLEX_ITEM &&
8336 : 0 : flow_hw_flex_item_acquire(dev, info->src.flex_handle,
8337 : : &at->flex_item)))
8338 : 0 : goto error;
8339 : : break;
8340 : : default:
8341 : : break;
8342 : : }
8343 : : }
8344 : 0 : ret = flow_hw_parse_flow_actions_to_dr_actions(dev, at, action_types, &tmpl_flags);
8345 [ # # ]: 0 : if (ret)
8346 : 0 : goto error;
8347 : 0 : at->action_flags = action_flags;
8348 : : /* In non template mode there is no need to create the dr template. */
8349 [ # # ]: 0 : if (nt_mode)
8350 : : return at;
8351 : 0 : at->tmpl = mlx5dr_action_template_create(action_types, tmpl_flags);
8352 [ # # ]: 0 : if (!at->tmpl) {
8353 : 0 : DRV_LOG(ERR, "Failed to create DR action template: %d", rte_errno);
8354 : 0 : goto error;
8355 : : }
8356 : 0 : rte_atomic_fetch_add_explicit(&at->refcnt, 1, rte_memory_order_relaxed);
8357 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->flow_hw_at, at, next);
8358 : 0 : return at;
8359 : 0 : error:
8360 : : if (at) {
8361 : 0 : mlx5_free(at);
8362 : : }
8363 : 0 : rte_flow_error_set(error, rte_errno,
8364 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8365 : : "Failed to create action template");
8366 : 0 : return NULL;
8367 : : }
8368 : :
8369 : : /**
8370 : : * Create flow action template.
8371 : : *
8372 : : * @param[in] dev
8373 : : * Pointer to the rte_eth_dev structure.
8374 : : * @param[in] attr
8375 : : * Pointer to the action template attributes.
8376 : : * @param[in] actions
8377 : : * Associated actions (list terminated by the END action).
8378 : : * @param[in] masks
8379 : : * List of actions that marks which of the action's member is constant.
8380 : : * @param[out] error
8381 : : * Pointer to error structure.
8382 : : *
8383 : : * @return
8384 : : * Action template pointer on success, NULL otherwise and rte_errno is set.
8385 : : */
8386 : : static struct rte_flow_actions_template *
8387 : 0 : flow_hw_actions_template_create(struct rte_eth_dev *dev,
8388 : : const struct rte_flow_actions_template_attr *attr,
8389 : : const struct rte_flow_action actions[],
8390 : : const struct rte_flow_action masks[],
8391 : : struct rte_flow_error *error)
8392 : : {
8393 : 0 : return __flow_hw_actions_template_create(dev, attr, actions, masks, false, error);
8394 : : }
8395 : :
8396 : : /**
8397 : : * Destroy flow action template.
8398 : : *
8399 : : * @param[in] dev
8400 : : * Pointer to the rte_eth_dev structure.
8401 : : * @param[in] template
8402 : : * Pointer to the action template to be destroyed.
8403 : : * @param[out] error
8404 : : * Pointer to error structure.
8405 : : *
8406 : : * @return
8407 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
8408 : : */
8409 : : static int
8410 : 0 : flow_hw_actions_template_destroy(struct rte_eth_dev *dev,
8411 : : struct rte_flow_actions_template *template,
8412 : : struct rte_flow_error *error __rte_unused)
8413 : : {
8414 : : uint64_t flag = MLX5_FLOW_ACTION_IPV6_ROUTING_REMOVE |
8415 : : MLX5_FLOW_ACTION_IPV6_ROUTING_PUSH;
8416 : :
8417 [ # # ]: 0 : if (rte_atomic_load_explicit(&template->refcnt, rte_memory_order_relaxed) > 1) {
8418 : 0 : DRV_LOG(WARNING, "Action template %p is still in use.",
8419 : : (void *)template);
8420 : 0 : return rte_flow_error_set(error, EBUSY,
8421 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8422 : : NULL,
8423 : : "action template is in use");
8424 : : }
8425 [ # # ]: 0 : if (template->action_flags & flag)
8426 : 0 : mlx5_free_srh_flex_parser(dev);
8427 [ # # ]: 0 : LIST_REMOVE(template, next);
8428 : 0 : flow_hw_flex_item_release(dev, &template->flex_item);
8429 [ # # ]: 0 : if (template->tmpl)
8430 : 0 : mlx5dr_action_template_destroy(template->tmpl);
8431 : 0 : mlx5_free(template);
8432 : 0 : return 0;
8433 : : }
8434 : :
8435 : : /*
8436 : : * Build a new item array prefixed with @p new_item.
8437 : : *
8438 : : * Callers typically build @p new_item on their stack with .spec / .mask
8439 : : * pointing at other stack locals, so a shallow copy of @p new_item would
8440 : : * leave dangling pointers as soon as the caller's frame goes away.
8441 : : *
8442 : : * To make the returned array self-contained, deep-copy @p new_item (item
8443 : : * header + spec/mask/last payloads) into the tail of the same allocation
8444 : : * via rte_flow_conv(RTE_FLOW_CONV_OP_ITEM, ...). The remaining items[]
8445 : : * are still shallow-copied: they reference the application-owned spec/
8446 : : * mask blobs handed to rte_flow_create() / rte_flow_pattern_template_
8447 : : * create(), whose lifetime already covers the returned array's use.
8448 : : *
8449 : : * Layout of the single mlx5_malloc() block:
8450 : : *
8451 : : * +--------------------------------------+ <- returned pointer
8452 : : * | rte_flow_item[nb_items + 1] | slot 0: copy of the deep-
8453 : : * | | copied header below
8454 : : * | | slots 1..nb_items: shallow
8455 : : * | | copies of items[]
8456 : : * +--------------------------------------+ <- new_item_buf
8457 : : * | rte_flow_item header (deep copy) | written by rte_flow_conv;
8458 : : * | + spec / mask / last payloads, | header.spec/.mask/.last point
8459 : : * | contiguous, self-referential | into the payloads right below
8460 : : * +--------------------------------------+
8461 : : *
8462 : : */
8463 : : static struct rte_flow_item *
8464 : 0 : flow_hw_prepend_item(const struct rte_flow_item *items,
8465 : : const uint32_t nb_items,
8466 : : const struct rte_flow_item *new_item,
8467 : : struct rte_flow_error *error)
8468 : : {
8469 : : struct rte_flow_item *copied_items;
8470 : : size_t header_size;
8471 : : size_t total_size;
8472 : : void *new_item_buf;
8473 : : int new_item_size;
8474 : : int rc;
8475 : :
8476 : : /*
8477 : : * Size the deep copy of the prepended item (header + payloads).
8478 : : * On error, rte_flow_conv() already populates @p error.
8479 : : */
8480 : 0 : new_item_size = rte_flow_conv(RTE_FLOW_CONV_OP_ITEM, NULL, 0, new_item, error);
8481 [ # # ]: 0 : if (new_item_size < 0)
8482 : : return NULL;
8483 : :
8484 : 0 : header_size = sizeof(*copied_items) * (nb_items + 1);
8485 : 0 : total_size = header_size + (size_t)new_item_size;
8486 : :
8487 : 0 : copied_items = mlx5_malloc(MLX5_MEM_ZERO, total_size, 0, SOCKET_ID_ANY);
8488 [ # # ]: 0 : if (!copied_items) {
8489 : 0 : rte_flow_error_set(error, ENOMEM,
8490 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8491 : : NULL,
8492 : : "cannot allocate item template");
8493 : 0 : return NULL;
8494 : : }
8495 : :
8496 : : /* Deep-copy the prepended item into the tail region. */
8497 : 0 : new_item_buf = (char *)copied_items + header_size;
8498 : 0 : rc = rte_flow_conv(RTE_FLOW_CONV_OP_ITEM, new_item_buf, (size_t)new_item_size, new_item,
8499 : : error);
8500 [ # # ]: 0 : if (rc < 0) {
8501 : 0 : mlx5_free(copied_items);
8502 : 0 : return NULL;
8503 : : }
8504 : :
8505 : : /*
8506 : : * Slot 0 is the prepended item header just written by rte_flow_conv,
8507 : : * with .spec/.mask/.last already pointing inside the same buffer.
8508 : : * The remaining items[] retain their (caller-owned, longer-lived)
8509 : : * spec/mask pointers via shallow copy.
8510 : : */
8511 : 0 : copied_items[0] = *(const struct rte_flow_item *)new_item_buf;
8512 [ # # ]: 0 : rte_memcpy(&copied_items[1], items, sizeof(*items) * nb_items);
8513 : : return copied_items;
8514 : : }
8515 : :
8516 : : static int
8517 : 0 : flow_hw_item_compare_field_validate(enum rte_flow_field_id arg_field,
8518 : : enum rte_flow_field_id base_field,
8519 : : struct rte_flow_error *error)
8520 : : {
8521 [ # # # ]: 0 : switch (arg_field) {
8522 : : case RTE_FLOW_FIELD_TAG:
8523 : : case RTE_FLOW_FIELD_META:
8524 : : case RTE_FLOW_FIELD_ESP_SEQ_NUM:
8525 : : break;
8526 : 0 : case RTE_FLOW_FIELD_RANDOM:
8527 [ # # ]: 0 : if (base_field == RTE_FLOW_FIELD_VALUE)
8528 : : return 0;
8529 : 0 : return rte_flow_error_set(error, EINVAL,
8530 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8531 : : NULL,
8532 : : "compare random is supported only with immediate value");
8533 : 0 : default:
8534 : 0 : return rte_flow_error_set(error, ENOTSUP,
8535 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8536 : : NULL,
8537 : : "compare item argument field is not supported");
8538 : : }
8539 [ # # ]: 0 : switch (base_field) {
8540 : : case RTE_FLOW_FIELD_TAG:
8541 : : case RTE_FLOW_FIELD_META:
8542 : : case RTE_FLOW_FIELD_VALUE:
8543 : : case RTE_FLOW_FIELD_ESP_SEQ_NUM:
8544 : : break;
8545 : 0 : default:
8546 : 0 : return rte_flow_error_set(error, ENOTSUP,
8547 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8548 : : NULL,
8549 : : "compare item base field is not supported");
8550 : : }
8551 : : return 0;
8552 : : }
8553 : :
8554 : : static inline uint32_t
8555 : : flow_hw_item_compare_width_supported(enum rte_flow_field_id field)
8556 : : {
8557 [ # # # ]: 0 : switch (field) {
8558 : : case RTE_FLOW_FIELD_TAG:
8559 : : case RTE_FLOW_FIELD_META:
8560 : : case RTE_FLOW_FIELD_ESP_SEQ_NUM:
8561 : : return 32;
8562 : 0 : case RTE_FLOW_FIELD_RANDOM:
8563 : 0 : return 16;
8564 : : default:
8565 : : break;
8566 : : }
8567 : 0 : return 0;
8568 : : }
8569 : :
8570 : : static int
8571 : 0 : flow_hw_validate_item_compare(const struct rte_flow_item *item,
8572 : : struct rte_flow_error *error)
8573 : : {
8574 : 0 : const struct rte_flow_item_compare *comp_m = item->mask;
8575 : 0 : const struct rte_flow_item_compare *comp_v = item->spec;
8576 : : int ret;
8577 : :
8578 [ # # ]: 0 : if (unlikely(!comp_m))
8579 : 0 : return rte_flow_error_set(error, EINVAL,
8580 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8581 : : NULL,
8582 : : "compare item mask is missing");
8583 [ # # ]: 0 : if (comp_m->width != UINT32_MAX)
8584 : 0 : return rte_flow_error_set(error, EINVAL,
8585 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8586 : : NULL,
8587 : : "compare item only support full mask");
8588 : 0 : ret = flow_hw_item_compare_field_validate(comp_m->a.field,
8589 : 0 : comp_m->b.field, error);
8590 [ # # ]: 0 : if (ret < 0)
8591 : : return ret;
8592 [ # # ]: 0 : if (comp_v) {
8593 : : uint32_t width;
8594 : :
8595 [ # # ]: 0 : if (comp_v->operation != comp_m->operation ||
8596 [ # # ]: 0 : comp_v->a.field != comp_m->a.field ||
8597 [ # # ]: 0 : comp_v->b.field != comp_m->b.field)
8598 : 0 : return rte_flow_error_set(error, EINVAL,
8599 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8600 : : NULL,
8601 : : "compare item spec/mask not matching");
8602 : : width = flow_hw_item_compare_width_supported(comp_v->a.field);
8603 : : MLX5_ASSERT(width > 0);
8604 [ # # ]: 0 : if ((comp_v->width & comp_m->width) != width)
8605 : 0 : return rte_flow_error_set(error, EINVAL,
8606 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8607 : : NULL,
8608 : : "compare item only support full mask");
8609 : : }
8610 : : return 0;
8611 : : }
8612 : :
8613 : : static inline int
8614 : : mlx5_hw_validate_item_nsh(struct rte_eth_dev *dev,
8615 : : const struct rte_flow_item *item,
8616 : : struct rte_flow_error *error)
8617 : : {
8618 : 0 : return mlx5_flow_validate_item_nsh(dev, item, error);
8619 : : }
8620 : :
8621 : : static inline uint8_t
8622 : 0 : mlx5_hw_flow_get_next_protocol(const struct rte_flow_item *item)
8623 : : {
8624 [ # # # # ]: 0 : if (!item || !item->spec)
8625 : : return 0xff;
8626 : :
8627 [ # # # # ]: 0 : switch (item->type) {
8628 : 0 : case RTE_FLOW_ITEM_TYPE_IPV4: {
8629 : : const struct rte_flow_item_ipv4 *spec = item->spec;
8630 : 0 : const struct rte_flow_item_ipv4 *mask = item->mask;
8631 : :
8632 : : /* If mask is NULL or next_proto_id field in mask is 0,
8633 : : * then next_protocol in spec should not be read
8634 : : */
8635 [ # # # # ]: 0 : if (!mask || mask->hdr.next_proto_id == 0)
8636 : : return 0xff;
8637 : :
8638 : 0 : return spec->hdr.next_proto_id & mask->hdr.next_proto_id;
8639 : : }
8640 : 0 : case RTE_FLOW_ITEM_TYPE_IPV6: {
8641 : : const struct rte_flow_item_ipv6 *spec = item->spec;
8642 : 0 : const struct rte_flow_item_ipv6 *mask = item->mask;
8643 : :
8644 : : /* If mask is NULL or proto field in mask is 0,
8645 : : * then proto in spec should not be read
8646 : : */
8647 [ # # # # ]: 0 : if (!mask || mask->hdr.proto == 0)
8648 : : return 0xff;
8649 : :
8650 : 0 : return spec->hdr.proto & mask->hdr.proto;
8651 : : }
8652 : 0 : case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT: {
8653 : : const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
8654 : 0 : const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
8655 : :
8656 : : /* If mask is NULL or next_header field in mask is 0,
8657 : : * then next_header in spec should not be read
8658 : : */
8659 [ # # # # ]: 0 : if (!mask || mask->hdr.next_header == 0)
8660 : : return 0xff;
8661 : :
8662 : 0 : return spec->hdr.next_header & mask->hdr.next_header;
8663 : : }
8664 : : default:
8665 : : return 0xff;
8666 : : }
8667 : : }
8668 : :
8669 : : static int
8670 : 0 : mlx5_hw_flow_tunnel_ip_check(uint64_t last_item,
8671 : : const struct rte_flow_item *last_l3_item,
8672 : : const struct rte_flow_item *item,
8673 : : uint64_t *item_flags,
8674 : : struct rte_flow_error *error)
8675 : : {
8676 : : uint64_t tunnel_flag = 0;
8677 : : uint8_t outer_protocol;
8678 : :
8679 : : /* IP tunnel detection - only single-level tunneling supported */
8680 [ # # ]: 0 : if (last_l3_item && (last_item == MLX5_FLOW_LAYER_OUTER_L3_IPV4 ||
8681 [ # # ]: 0 : last_item == MLX5_FLOW_LAYER_OUTER_L3_IPV6)) {
8682 : : /*
8683 : : * Tunnel type determination strategy:
8684 : : * 1. If previous L3 item has protocol field specified, use it (RFC compliant)
8685 : : * 2. Otherwise, fall back to inner header type (what's being encapsulated)
8686 : : */
8687 : 0 : outer_protocol = mlx5_hw_flow_get_next_protocol(last_l3_item);
8688 : :
8689 [ # # ]: 0 : if (outer_protocol != 0xff) {
8690 : : /* Proto field specified in outer hdr mask - use RFC-compliant detection */
8691 [ # # # ]: 0 : switch (outer_protocol) {
8692 : 0 : case IPPROTO_IPIP: /* 4 - IP-in-IP */
8693 : : /* Outer header indicates IPv4 payload */
8694 [ # # ]: 0 : if (item->type == RTE_FLOW_ITEM_TYPE_IPV6)
8695 : 0 : return rte_flow_error_set(error, EINVAL,
8696 : : RTE_FLOW_ERROR_TYPE_ITEM, item,
8697 : : "protocol mismatch: outer proto is IPIP but inner is IPv6");
8698 : : tunnel_flag = MLX5_FLOW_LAYER_IPIP;
8699 : : break;
8700 : 0 : case IPPROTO_IPV6: /* 41 - IPv6-in-IP */
8701 : : /* Outer header indicates IPv6 payload */
8702 [ # # ]: 0 : if (item->type == RTE_FLOW_ITEM_TYPE_IPV4)
8703 : 0 : return rte_flow_error_set(error, EINVAL,
8704 : : RTE_FLOW_ERROR_TYPE_ITEM, item,
8705 : : "protocol mismatch: outer proto is IPV6 but inner is IPv4");
8706 : : tunnel_flag = MLX5_FLOW_LAYER_IPV6_ENCAP;
8707 : : break;
8708 : 0 : default:
8709 : : /* Unknown/unsupported protocol, fall back to inner header type */
8710 : 0 : goto fallback_classification;
8711 : : }
8712 : : } else {
8713 : 0 : fallback_classification:
8714 : : /*
8715 : : * Protocol field not specified or unknown - classify based on
8716 : : * what is being encapsulated (inner header type)
8717 : : */
8718 [ # # ]: 0 : if (item->type == RTE_FLOW_ITEM_TYPE_IPV4)
8719 : : tunnel_flag = MLX5_FLOW_LAYER_IPIP;
8720 [ # # ]: 0 : else if (item->type == RTE_FLOW_ITEM_TYPE_IPV6)
8721 : : tunnel_flag = MLX5_FLOW_LAYER_IPV6_ENCAP;
8722 : : else
8723 : : return 0; /* Not an IP item - shouldn't happen, but be defensive */
8724 : : }
8725 : :
8726 : : /* Check for unsupported nested tunneling after tunnel is detected */
8727 [ # # ]: 0 : if (*item_flags & MLX5_FLOW_LAYER_TUNNEL)
8728 : 0 : return rte_flow_error_set(error, ENOTSUP,
8729 : : RTE_FLOW_ERROR_TYPE_ITEM, item,
8730 : : "multiple tunnel layers not supported");
8731 : :
8732 : 0 : *item_flags |= tunnel_flag;
8733 : 0 : return 1; /* Tunnel detected */
8734 [ # # ]: 0 : } else if (last_item == MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT) {
8735 : : /* Special case: IPv6 routing extension header */
8736 : : /* Check for unsupported nested tunneling */
8737 [ # # ]: 0 : if (*item_flags & MLX5_FLOW_LAYER_TUNNEL)
8738 : 0 : return rte_flow_error_set(error, ENOTSUP,
8739 : : RTE_FLOW_ERROR_TYPE_ITEM, item,
8740 : : "multiple tunnel layers not supported");
8741 : :
8742 : 0 : *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
8743 : 0 : return 1; /* Tunnel detected */
8744 : : }
8745 : :
8746 : : return 0; /* No tunnel */
8747 : : }
8748 : :
8749 : : const struct rte_flow_item_ipv4 hws_nic_ipv4_mask = {
8750 : : .hdr = {
8751 : : .version = 0xf,
8752 : : .ihl = 0xf,
8753 : : .type_of_service = 0xff,
8754 : : .total_length = RTE_BE16(0xffff),
8755 : : .packet_id = RTE_BE16(0xffff),
8756 : : .fragment_offset = RTE_BE16(0xffff),
8757 : : .time_to_live = 0xff,
8758 : : .next_proto_id = 0xff,
8759 : : .src_addr = RTE_BE32(0xffffffff),
8760 : : .dst_addr = RTE_BE32(0xffffffff),
8761 : : },
8762 : : };
8763 : :
8764 : : const struct rte_flow_item_ipv6 hws_nic_ipv6_mask = {
8765 : : .hdr = {
8766 : : .vtc_flow = RTE_BE32(0xffffffff),
8767 : : .payload_len = RTE_BE16(0xffff),
8768 : : .proto = 0xff,
8769 : : .hop_limits = 0xff,
8770 : : .src_addr = RTE_IPV6_MASK_FULL,
8771 : : .dst_addr = RTE_IPV6_MASK_FULL,
8772 : : },
8773 : : .has_frag_ext = 1,
8774 : : };
8775 : :
8776 : : const struct rte_flow_item_ecpri hws_nic_ecpri_mask = {
8777 : : .hdr = {
8778 : : .common = {
8779 : : .u32 = RTE_BE32(0xffffffff),
8780 : : },
8781 : : .dummy[0] = 0xffffffff,
8782 : : },
8783 : : };
8784 : :
8785 : :
8786 : : static int
8787 : 0 : flow_hw_validate_item_ptype(const struct rte_flow_item *item,
8788 : : struct rte_flow_error *error)
8789 : : {
8790 : 0 : const struct rte_flow_item_ptype *ptype = item->mask;
8791 : :
8792 : : /* HWS does not allow empty PTYPE mask */
8793 [ # # ]: 0 : if (!ptype)
8794 : 0 : return rte_flow_error_set(error, EINVAL,
8795 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8796 : : NULL, "empty ptype mask");
8797 [ # # ]: 0 : if (!(ptype->packet_type &
8798 : : (RTE_PTYPE_L2_MASK | RTE_PTYPE_L3_MASK | RTE_PTYPE_L4_MASK |
8799 : : RTE_PTYPE_INNER_L2_MASK | RTE_PTYPE_INNER_L3_MASK |
8800 : : RTE_PTYPE_INNER_L4_MASK)))
8801 : 0 : return rte_flow_error_set(error, ENOTSUP,
8802 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8803 : : NULL, "ptype mask not supported");
8804 : : return 0;
8805 : : }
8806 : :
8807 : : struct mlx5_hw_pattern_validation_ctx {
8808 : : const struct rte_flow_item *geneve_item;
8809 : : const struct rte_flow_item *flex_item;
8810 : : };
8811 : :
8812 : : static int
8813 : 0 : __flow_hw_pattern_validate(struct rte_eth_dev *dev,
8814 : : const struct rte_flow_pattern_template_attr *attr,
8815 : : const struct rte_flow_item items[],
8816 : : uint64_t *item_flags,
8817 : : bool nt_flow,
8818 : : struct rte_flow_error *error)
8819 : : {
8820 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
8821 : : const struct rte_flow_item *last_l3_item = NULL;
8822 : : const struct rte_flow_item *item;
8823 : : const struct rte_flow_item *gtp_item = NULL;
8824 : : const struct rte_flow_item *gre_item = NULL;
8825 : 0 : const struct rte_flow_attr flow_attr = {
8826 : 0 : .ingress = attr->ingress,
8827 : 0 : .egress = attr->egress,
8828 : 0 : .transfer = attr->transfer
8829 : : };
8830 : : int ret, tag_idx;
8831 : : uint32_t tag_bitmap = 0;
8832 : : uint64_t last_item = 0;
8833 : :
8834 [ # # ]: 0 : if (!mlx5_hw_ctx_validate(dev, error))
8835 : 0 : return -rte_errno;
8836 [ # # ]: 0 : if (!attr->ingress && !attr->egress && !attr->transfer)
8837 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ATTR, NULL,
8838 : : "at least one of the direction attributes"
8839 : : " must be specified");
8840 [ # # ]: 0 : if (priv->sh->config.dv_esw_en) {
8841 : : MLX5_ASSERT(priv->master || priv->representor);
8842 [ # # ]: 0 : if (priv->master) {
8843 [ # # ]: 0 : if ((attr->ingress && attr->egress) ||
8844 [ # # ]: 0 : (attr->ingress && attr->transfer) ||
8845 [ # # ]: 0 : (attr->egress && attr->transfer))
8846 : 0 : return rte_flow_error_set(error, EINVAL,
8847 : : RTE_FLOW_ERROR_TYPE_ATTR, NULL,
8848 : : "only one direction attribute at once"
8849 : : " can be used on transfer proxy port");
8850 : : } else {
8851 [ # # ]: 0 : if (attr->transfer)
8852 : 0 : return rte_flow_error_set(error, EINVAL,
8853 : : RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER, NULL,
8854 : : "transfer attribute cannot be used with"
8855 : : " port representors");
8856 [ # # ]: 0 : if (attr->ingress && attr->egress)
8857 : 0 : return rte_flow_error_set(error, EINVAL,
8858 : : RTE_FLOW_ERROR_TYPE_ATTR, NULL,
8859 : : "ingress and egress direction attributes"
8860 : : " cannot be used at the same time on"
8861 : : " port representors");
8862 : : }
8863 : : } else {
8864 [ # # ]: 0 : if (attr->transfer)
8865 : 0 : return rte_flow_error_set(error, EINVAL,
8866 : : RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER, NULL,
8867 : : "transfer attribute cannot be used when"
8868 : : " E-Switch is disabled");
8869 : : }
8870 [ # # ]: 0 : for (item = items; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
8871 : 0 : bool tunnel = *item_flags & MLX5_FLOW_LAYER_TUNNEL;
8872 : :
8873 [ # # # # : 0 : switch ((int)item->type) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # #
# ]
8874 : 0 : case RTE_FLOW_ITEM_TYPE_PTYPE:
8875 : 0 : ret = flow_hw_validate_item_ptype(item, error);
8876 [ # # ]: 0 : if (ret)
8877 : 0 : return ret;
8878 : : last_item = MLX5_FLOW_ITEM_PTYPE;
8879 : : break;
8880 : 0 : case RTE_FLOW_ITEM_TYPE_TAG:
8881 : : {
8882 : 0 : const struct rte_flow_item_tag *tag =
8883 : : (const struct rte_flow_item_tag *)item->spec;
8884 : :
8885 [ # # ]: 0 : if (tag == NULL)
8886 : 0 : return rte_flow_error_set(error, EINVAL,
8887 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8888 : : NULL,
8889 : : "Tag spec is NULL");
8890 [ # # ]: 0 : if (tag->index >= MLX5_FLOW_HW_TAGS_MAX &&
8891 : : tag->index != RTE_PMD_MLX5_LINEAR_HASH_TAG_INDEX)
8892 : 0 : return rte_flow_error_set(error, EINVAL,
8893 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8894 : : NULL,
8895 : : "Invalid tag index");
8896 [ # # ]: 0 : tag_idx = flow_hw_get_reg_id(dev, RTE_FLOW_ITEM_TYPE_TAG, tag->index);
8897 [ # # ]: 0 : if (tag_idx == REG_NON)
8898 : 0 : return rte_flow_error_set(error, EINVAL,
8899 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8900 : : NULL,
8901 : : "Unsupported tag index");
8902 [ # # ]: 0 : if (tag_bitmap & (1 << tag_idx))
8903 : 0 : return rte_flow_error_set(error, EINVAL,
8904 : : RTE_FLOW_ERROR_TYPE_ITEM,
8905 : : NULL,
8906 : : "Duplicated tag index");
8907 : 0 : tag_bitmap |= 1 << tag_idx;
8908 : : last_item = MLX5_FLOW_ITEM_TAG;
8909 : 0 : break;
8910 : : }
8911 : 0 : case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
8912 : : {
8913 : 0 : const struct rte_flow_item_tag *tag =
8914 : : (const struct rte_flow_item_tag *)item->spec;
8915 : 0 : uint16_t regcs = (uint8_t)priv->sh->cdev->config.hca_attr.set_reg_c;
8916 : :
8917 [ # # ]: 0 : if (!((1 << (tag->index - REG_C_0)) & regcs))
8918 : 0 : return rte_flow_error_set(error, EINVAL,
8919 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8920 : : NULL,
8921 : : "Unsupported internal tag index");
8922 [ # # ]: 0 : if (tag_bitmap & (1 << tag->index))
8923 : 0 : return rte_flow_error_set(error, EINVAL,
8924 : : RTE_FLOW_ERROR_TYPE_ITEM,
8925 : : NULL,
8926 : : "Duplicated tag index");
8927 : 0 : tag_bitmap |= 1 << tag->index;
8928 : 0 : break;
8929 : : }
8930 : 0 : case RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT:
8931 [ # # ]: 0 : if (attr->ingress)
8932 : 0 : return rte_flow_error_set(error, EINVAL,
8933 : : RTE_FLOW_ERROR_TYPE_ITEM, NULL,
8934 : : "represented port item cannot be used"
8935 : : " when ingress attribute is set");
8936 [ # # ]: 0 : if (attr->egress)
8937 : 0 : return rte_flow_error_set(error, EINVAL,
8938 : : RTE_FLOW_ERROR_TYPE_ITEM, NULL,
8939 : : "represented port item cannot be used"
8940 : : " when egress attribute is set");
8941 : : last_item = MLX5_FLOW_ITEM_REPRESENTED_PORT;
8942 : : break;
8943 : 0 : case RTE_FLOW_ITEM_TYPE_META:
8944 : : /* ingress + group 0 is not supported */
8945 : 0 : *item_flags |= MLX5_FLOW_ITEM_METADATA;
8946 : 0 : break;
8947 : : case RTE_FLOW_ITEM_TYPE_METER_COLOR:
8948 : : {
8949 : : int reg = flow_hw_get_reg_id(dev,
8950 : : RTE_FLOW_ITEM_TYPE_METER_COLOR,
8951 : : 0);
8952 [ # # ]: 0 : if (reg == REG_NON)
8953 : 0 : return rte_flow_error_set(error, EINVAL,
8954 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8955 : : NULL,
8956 : : "Unsupported meter color register");
8957 [ # # ]: 0 : if (*item_flags &
8958 : : (MLX5_FLOW_ITEM_QUOTA | MLX5_FLOW_LAYER_ASO_CT))
8959 : 0 : return rte_flow_error_set
8960 : : (error, EINVAL,
8961 : : RTE_FLOW_ERROR_TYPE_ITEM, NULL, "Only one ASO item is supported");
8962 : : last_item = MLX5_FLOW_ITEM_METER_COLOR;
8963 : : break;
8964 : : }
8965 : 0 : case RTE_FLOW_ITEM_TYPE_AGGR_AFFINITY:
8966 : : {
8967 [ # # ]: 0 : if (!priv->sh->lag_rx_port_affinity_en)
8968 : 0 : return rte_flow_error_set(error, EINVAL,
8969 : : RTE_FLOW_ERROR_TYPE_ITEM, NULL,
8970 : : "Unsupported aggregated affinity with Older FW");
8971 [ # # # # : 0 : if ((attr->transfer && priv->fdb_def_rule) || attr->egress)
# # ]
8972 : 0 : return rte_flow_error_set(error, EINVAL,
8973 : : RTE_FLOW_ERROR_TYPE_ITEM, NULL,
8974 : : "Aggregated affinity item not supported"
8975 : : " with egress or transfer"
8976 : : " attribute");
8977 : : last_item = MLX5_FLOW_ITEM_AGGR_AFFINITY;
8978 : : break;
8979 : : }
8980 : 0 : case RTE_FLOW_ITEM_TYPE_GENEVE:
8981 : : last_item = MLX5_FLOW_LAYER_GENEVE;
8982 : 0 : break;
8983 : 0 : case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
8984 : : {
8985 : : last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
8986 : : /*
8987 : : * For non template the parser is internally created before
8988 : : * the flow creation.
8989 : : */
8990 [ # # ]: 0 : if (!nt_flow) {
8991 : 0 : ret = mlx5_flow_geneve_tlv_option_validate(priv, item,
8992 : : error);
8993 [ # # ]: 0 : if (ret < 0)
8994 : 0 : return ret;
8995 : : }
8996 : : break;
8997 : : }
8998 : 0 : case RTE_FLOW_ITEM_TYPE_COMPARE:
8999 : : {
9000 : : last_item = MLX5_FLOW_ITEM_COMPARE;
9001 : 0 : ret = flow_hw_validate_item_compare(item, error);
9002 [ # # ]: 0 : if (ret)
9003 : 0 : return ret;
9004 : : break;
9005 : : }
9006 : 0 : case RTE_FLOW_ITEM_TYPE_ETH:
9007 : 0 : ret = mlx5_flow_validate_item_eth(dev, item,
9008 : : *item_flags,
9009 : : true, error);
9010 [ # # ]: 0 : if (ret < 0)
9011 : 0 : return ret;
9012 [ # # ]: 0 : last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
9013 : : MLX5_FLOW_LAYER_OUTER_L2;
9014 : : break;
9015 : 0 : case RTE_FLOW_ITEM_TYPE_VLAN:
9016 : 0 : ret = mlx5_flow_dv_validate_item_vlan(item, *item_flags,
9017 : : dev, error);
9018 [ # # ]: 0 : if (ret < 0)
9019 : 0 : return ret;
9020 [ # # ]: 0 : last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
9021 : : MLX5_FLOW_LAYER_OUTER_VLAN;
9022 : : break;
9023 : 0 : case RTE_FLOW_ITEM_TYPE_IPV4:
9024 : 0 : ret = mlx5_hw_flow_tunnel_ip_check(last_item, last_l3_item, item,
9025 : : item_flags, error);
9026 [ # # ]: 0 : if (ret < 0)
9027 : 0 : return ret;
9028 : 0 : tunnel |= (ret > 0);
9029 : 0 : ret = mlx5_flow_dv_validate_item_ipv4(dev, item,
9030 : : *item_flags,
9031 : : last_item, 0,
9032 : : &hws_nic_ipv4_mask,
9033 : : error);
9034 [ # # ]: 0 : if (ret)
9035 : 0 : return ret;
9036 [ # # ]: 0 : last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
9037 : : MLX5_FLOW_LAYER_OUTER_L3_IPV4;
9038 : : last_l3_item = item;
9039 : : break;
9040 : 0 : case RTE_FLOW_ITEM_TYPE_IPV6:
9041 : 0 : ret = mlx5_hw_flow_tunnel_ip_check(last_item, last_l3_item, item,
9042 : : item_flags, error);
9043 [ # # ]: 0 : if (ret < 0)
9044 : 0 : return ret;
9045 : 0 : tunnel |= (ret > 0);
9046 : 0 : ret = mlx5_flow_validate_item_ipv6(dev, item,
9047 : : *item_flags,
9048 : : last_item, 0,
9049 : : &hws_nic_ipv6_mask,
9050 : : error);
9051 [ # # ]: 0 : if (ret < 0)
9052 : 0 : return ret;
9053 [ # # ]: 0 : last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
9054 : : MLX5_FLOW_LAYER_OUTER_L3_IPV6;
9055 : : last_l3_item = item;
9056 : : break;
9057 : 0 : case RTE_FLOW_ITEM_TYPE_UDP:
9058 : 0 : ret = mlx5_flow_validate_item_udp(dev, item,
9059 : : *item_flags,
9060 : : 0xff, error);
9061 [ # # ]: 0 : if (ret)
9062 : 0 : return ret;
9063 [ # # ]: 0 : last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
9064 : : MLX5_FLOW_LAYER_OUTER_L4_UDP;
9065 : : break;
9066 : 0 : case RTE_FLOW_ITEM_TYPE_TCP:
9067 : 0 : ret = mlx5_flow_validate_item_tcp
9068 : : (dev, item, *item_flags,
9069 : : 0xff, &nic_tcp_mask, error);
9070 [ # # ]: 0 : if (ret < 0)
9071 : 0 : return ret;
9072 [ # # ]: 0 : last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
9073 : : MLX5_FLOW_LAYER_OUTER_L4_TCP;
9074 : : break;
9075 : 0 : case RTE_FLOW_ITEM_TYPE_GTP:
9076 : : gtp_item = item;
9077 : 0 : ret = mlx5_flow_dv_validate_item_gtp(dev, gtp_item,
9078 : : *item_flags, error);
9079 [ # # ]: 0 : if (ret < 0)
9080 : 0 : return ret;
9081 : : last_item = MLX5_FLOW_LAYER_GTP;
9082 : : break;
9083 : 0 : case RTE_FLOW_ITEM_TYPE_GTP_PSC:
9084 : 0 : ret = mlx5_flow_dv_validate_item_gtp_psc(dev, item,
9085 : : last_item,
9086 : : gtp_item,
9087 : : false, error);
9088 [ # # ]: 0 : if (ret < 0)
9089 : 0 : return ret;
9090 : : last_item = MLX5_FLOW_LAYER_GTP_PSC;
9091 : : break;
9092 : 0 : case RTE_FLOW_ITEM_TYPE_VXLAN:
9093 : 0 : ret = mlx5_flow_validate_item_vxlan(dev, 0, item,
9094 : : *item_flags,
9095 : : false, error);
9096 [ # # ]: 0 : if (ret < 0)
9097 : 0 : return ret;
9098 : : last_item = MLX5_FLOW_LAYER_VXLAN;
9099 : : break;
9100 : 0 : case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
9101 : 0 : ret = mlx5_flow_validate_item_vxlan_gpe(item,
9102 : : *item_flags,
9103 : : dev, error);
9104 [ # # ]: 0 : if (ret < 0)
9105 : 0 : return ret;
9106 : : last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
9107 : : break;
9108 : 0 : case RTE_FLOW_ITEM_TYPE_MPLS:
9109 : 0 : ret = mlx5_flow_validate_item_mpls(dev, item,
9110 : : *item_flags,
9111 : : last_item, error);
9112 [ # # ]: 0 : if (ret < 0)
9113 : 0 : return ret;
9114 : : last_item = MLX5_FLOW_LAYER_MPLS;
9115 : : break;
9116 : 0 : case MLX5_RTE_FLOW_ITEM_TYPE_SQ:
9117 : : case RTE_FLOW_ITEM_TYPE_TX_QUEUE:
9118 : : last_item = MLX5_FLOW_ITEM_SQ;
9119 : 0 : break;
9120 : 0 : case RTE_FLOW_ITEM_TYPE_GRE:
9121 : 0 : ret = mlx5_flow_validate_item_gre(dev, item,
9122 : : *item_flags,
9123 : : 0xff, error);
9124 [ # # ]: 0 : if (ret < 0)
9125 : 0 : return ret;
9126 : : gre_item = item;
9127 : : last_item = MLX5_FLOW_LAYER_GRE;
9128 : : break;
9129 : 0 : case RTE_FLOW_ITEM_TYPE_GRE_KEY:
9130 [ # # ]: 0 : if (!(*item_flags & MLX5_FLOW_LAYER_GRE))
9131 : 0 : return rte_flow_error_set
9132 : : (error, EINVAL,
9133 : : RTE_FLOW_ERROR_TYPE_ITEM, item, "GRE item is missing");
9134 : 0 : ret = mlx5_flow_validate_item_gre_key
9135 : : (dev, item, *item_flags, gre_item, error);
9136 [ # # ]: 0 : if (ret < 0)
9137 : 0 : return ret;
9138 : : last_item = MLX5_FLOW_LAYER_GRE_KEY;
9139 : : break;
9140 : 0 : case RTE_FLOW_ITEM_TYPE_GRE_OPTION:
9141 [ # # ]: 0 : if (!(*item_flags & MLX5_FLOW_LAYER_GRE))
9142 : 0 : return rte_flow_error_set
9143 : : (error, EINVAL,
9144 : : RTE_FLOW_ERROR_TYPE_ITEM, item, "GRE item is missing");
9145 : 0 : ret = mlx5_flow_validate_item_gre_option(dev, item,
9146 : : *item_flags,
9147 : : &flow_attr,
9148 : : gre_item,
9149 : : error);
9150 [ # # ]: 0 : if (ret < 0)
9151 : 0 : return ret;
9152 : : last_item = MLX5_FLOW_LAYER_GRE;
9153 : : break;
9154 : 0 : case RTE_FLOW_ITEM_TYPE_NVGRE:
9155 : 0 : ret = mlx5_flow_validate_item_nvgre(dev, item,
9156 : : *item_flags, 0xff,
9157 : : error);
9158 [ # # ]: 0 : if (ret)
9159 : 0 : return ret;
9160 : : last_item = MLX5_FLOW_LAYER_NVGRE;
9161 : : break;
9162 : 0 : case RTE_FLOW_ITEM_TYPE_ICMP:
9163 : 0 : ret = mlx5_flow_validate_item_icmp(dev, item,
9164 : : *item_flags, 0xff,
9165 : : error);
9166 [ # # ]: 0 : if (ret < 0)
9167 : 0 : return ret;
9168 : : last_item = MLX5_FLOW_LAYER_ICMP;
9169 : : break;
9170 : 0 : case RTE_FLOW_ITEM_TYPE_ICMP6:
9171 : 0 : ret = mlx5_flow_validate_item_icmp6(dev, item,
9172 : : *item_flags, 0xff,
9173 : : error);
9174 [ # # ]: 0 : if (ret < 0)
9175 : 0 : return ret;
9176 : : last_item = MLX5_FLOW_LAYER_ICMP6;
9177 : : break;
9178 : 0 : case RTE_FLOW_ITEM_TYPE_ICMP6_ECHO_REQUEST:
9179 : : case RTE_FLOW_ITEM_TYPE_ICMP6_ECHO_REPLY:
9180 : 0 : ret = mlx5_flow_validate_item_icmp6_echo(dev, item,
9181 : : *item_flags,
9182 : : 0xff, error);
9183 [ # # ]: 0 : if (ret < 0)
9184 : 0 : return ret;
9185 : : last_item = MLX5_FLOW_LAYER_ICMP6;
9186 : : break;
9187 : 0 : case RTE_FLOW_ITEM_TYPE_CONNTRACK:
9188 [ # # ]: 0 : if (*item_flags &
9189 : : (MLX5_FLOW_ITEM_QUOTA | MLX5_FLOW_LAYER_ASO_CT))
9190 : 0 : return rte_flow_error_set
9191 : : (error, EINVAL,
9192 : : RTE_FLOW_ERROR_TYPE_ITEM, NULL, "Only one ASO item is supported");
9193 : 0 : ret = mlx5_flow_dv_validate_item_aso_ct(dev, item,
9194 : : item_flags,
9195 : : error);
9196 [ # # ]: 0 : if (ret < 0)
9197 : 0 : return ret;
9198 : : break;
9199 : 0 : case RTE_FLOW_ITEM_TYPE_QUOTA:
9200 [ # # ]: 0 : if (*item_flags &
9201 : : (MLX5_FLOW_ITEM_METER_COLOR |
9202 : : MLX5_FLOW_LAYER_ASO_CT))
9203 : 0 : return rte_flow_error_set
9204 : : (error, EINVAL,
9205 : : RTE_FLOW_ERROR_TYPE_ITEM, NULL, "Only one ASO item is supported");
9206 : : last_item = MLX5_FLOW_ITEM_QUOTA;
9207 : : break;
9208 : 0 : case RTE_FLOW_ITEM_TYPE_ESP:
9209 : 0 : ret = mlx5_flow_os_validate_item_esp(dev, item, *item_flags,
9210 : : 0xff, true, error);
9211 [ # # ]: 0 : if (ret < 0)
9212 : 0 : return ret;
9213 : : last_item = MLX5_FLOW_ITEM_ESP;
9214 : : break;
9215 : 0 : case RTE_FLOW_ITEM_TYPE_IPV6_ROUTING_EXT:
9216 : : last_item = tunnel ?
9217 [ # # ]: 0 : MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT :
9218 : : MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT;
9219 : : break;
9220 : 0 : case RTE_FLOW_ITEM_TYPE_FLEX: {
9221 : 0 : enum rte_flow_item_flex_tunnel_mode tunnel_mode = FLEX_TUNNEL_MODE_SINGLE;
9222 : :
9223 : 0 : ret = mlx5_flex_get_tunnel_mode(item, &tunnel_mode);
9224 [ # # ]: 0 : if (ret < 0)
9225 : 0 : return rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_ITEM,
9226 : : item, "Unable to get flex item mode");
9227 [ # # ]: 0 : if (tunnel_mode == FLEX_TUNNEL_MODE_TUNNEL)
9228 : : last_item = MLX5_FLOW_ITEM_FLEX_TUNNEL;
9229 : : else
9230 : : last_item = tunnel ?
9231 [ # # ]: 0 : MLX5_FLOW_ITEM_INNER_FLEX :
9232 : : MLX5_FLOW_ITEM_OUTER_FLEX;
9233 : 0 : break;
9234 : : }
9235 : 0 : case RTE_FLOW_ITEM_TYPE_RANDOM:
9236 : : last_item = MLX5_FLOW_ITEM_RANDOM;
9237 : 0 : break;
9238 : 0 : case RTE_FLOW_ITEM_TYPE_NSH:
9239 : : last_item = MLX5_FLOW_ITEM_NSH;
9240 : : ret = mlx5_hw_validate_item_nsh(dev, item, error);
9241 [ # # ]: 0 : if (ret < 0)
9242 : 0 : return ret;
9243 : : break;
9244 : : case RTE_FLOW_ITEM_TYPE_INTEGRITY:
9245 : : /*
9246 : : * Integrity flow item validation require access to
9247 : : * both item mask and spec.
9248 : : * Current HWS model allows item mask in pattern
9249 : : * template and item spec in flow rule.
9250 : : */
9251 : : break;
9252 : 0 : case RTE_FLOW_ITEM_TYPE_ECPRI:
9253 : 0 : ret = mlx5_flow_validate_item_ecpri(dev, item, *item_flags, last_item,
9254 : : RTE_ETHER_TYPE_ECPRI,
9255 : : &hws_nic_ecpri_mask, error);
9256 [ # # ]: 0 : if (ret < 0)
9257 : 0 : return ret;
9258 : 0 : *item_flags |= MLX5_FLOW_LAYER_ECPRI;
9259 : 0 : break;
9260 : : case RTE_FLOW_ITEM_TYPE_IB_BTH:
9261 : : case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
9262 : : case RTE_FLOW_ITEM_TYPE_VOID:
9263 : : case RTE_FLOW_ITEM_TYPE_END:
9264 : : break;
9265 : 0 : default:
9266 : 0 : return rte_flow_error_set(error, EINVAL,
9267 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9268 : : NULL,
9269 : : "Unsupported item type");
9270 : : }
9271 : 0 : *item_flags |= last_item;
9272 : : }
9273 : 0 : return 1 + RTE_PTR_DIFF(item, items) / sizeof(item[0]);
9274 : : }
9275 : :
9276 : : static int
9277 : 0 : flow_hw_pattern_validate(struct rte_eth_dev *dev,
9278 : : const struct rte_flow_pattern_template_attr *attr,
9279 : : const struct rte_flow_item items[],
9280 : : uint64_t *item_flags,
9281 : : struct rte_flow_error *error)
9282 : : {
9283 : 0 : return __flow_hw_pattern_validate(dev, attr, items, item_flags, false, error);
9284 : : }
9285 : :
9286 : : /*
9287 : : * Verify that the tested flow patterns fits STE size limit in HWS group.
9288 : : *
9289 : : *
9290 : : * Return values:
9291 : : * 0 : Tested patterns fit STE size limit
9292 : : * -EINVAL : Invalid parameters detected
9293 : : * -E2BIG : Tested patterns exceed STE size limit
9294 : : */
9295 : : static int
9296 : 0 : pattern_template_validate(struct rte_eth_dev *dev,
9297 : : struct rte_flow_pattern_template *pt[],
9298 : : uint32_t pt_num,
9299 : : struct rte_flow_error *error)
9300 : : {
9301 : 0 : struct mlx5_flow_template_table_cfg tbl_cfg = {
9302 : : .attr = {
9303 : : .nb_flows = 64,
9304 : : .insertion_type = RTE_FLOW_TABLE_INSERTION_TYPE_PATTERN,
9305 : : .hash_func = RTE_FLOW_TABLE_HASH_FUNC_DEFAULT,
9306 : : .flow_attr = {
9307 : : .group = 1,
9308 : 0 : .ingress = pt[0]->attr.ingress,
9309 : 0 : .egress = pt[0]->attr.egress,
9310 : 0 : .transfer = pt[0]->attr.transfer
9311 : : }
9312 : : }
9313 : : };
9314 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
9315 : : struct rte_flow_actions_template *action_template;
9316 : : struct rte_flow_template_table *tmpl_tbl;
9317 : : int ret;
9318 : :
9319 [ # # ]: 0 : if (pt[0]->attr.ingress) {
9320 : 0 : action_template =
9321 : 0 : priv->action_template_drop[MLX5DR_TABLE_TYPE_NIC_RX];
9322 [ # # ]: 0 : } else if (pt[0]->attr.egress) {
9323 : 0 : action_template =
9324 : 0 : priv->action_template_drop[MLX5DR_TABLE_TYPE_NIC_TX];
9325 [ # # ]: 0 : } else if (pt[0]->attr.transfer) {
9326 : 0 : action_template =
9327 : 0 : priv->action_template_drop[MLX5DR_TABLE_TYPE_FDB];
9328 : : } else {
9329 : : ret = EINVAL;
9330 : 0 : goto end;
9331 : : }
9332 : :
9333 [ # # ]: 0 : if (pt[0]->item_flags & MLX5_FLOW_ITEM_COMPARE)
9334 : 0 : tbl_cfg.attr.nb_flows = 1;
9335 : 0 : tmpl_tbl = flow_hw_table_create(dev, &tbl_cfg, pt, pt_num,
9336 : : &action_template, 1, error);
9337 [ # # ]: 0 : if (tmpl_tbl) {
9338 : : ret = 0;
9339 : 0 : flow_hw_table_destroy(dev, tmpl_tbl, error);
9340 : : } else {
9341 [ # # # ]: 0 : switch (rte_errno) {
9342 : : case E2BIG:
9343 : : ret = E2BIG;
9344 : : break;
9345 : : case ENOTSUP:
9346 : : ret = EINVAL;
9347 : : break;
9348 : : default:
9349 : : ret = 0;
9350 : : break;
9351 : : }
9352 : : }
9353 : : end:
9354 : : if (ret)
9355 : 0 : rte_flow_error_set(error, ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9356 : : NULL, "failed to validate pattern template");
9357 : 0 : return -ret;
9358 : : }
9359 : :
9360 : : /*
9361 : : * Validate the user-supplied items and, in eSwitch mode, prepend the implicit
9362 : : * scoping item so the rule/template is bound to the current representor port:
9363 : : * - ingress -> RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT (dev->data->port_id)
9364 : : * - egress -> MLX5_RTE_FLOW_ITEM_TYPE_TAG on REG_C_0 (tx vport tag),
9365 : : * skipped when the user already supplied an SQ item.
9366 : : *
9367 : : * @param nt_flow
9368 : : * Selects between the two call paths that share this helper:
9369 : : * false -> pattern template creation (async API). The prepended item's
9370 : : * spec is left zeroed so mlx5dr matches any value; the live
9371 : : * port_id / tx-tag value is substituted later by
9372 : : * flow_hw_get_rule_items() at rule-create time.
9373 : : * true -> sync (non-template) flow creation. The prepended item's spec
9374 : : * is filled immediately with the live values, and the flag is
9375 : : * forwarded to __flow_hw_pattern_validate() so that validation
9376 : : * paths gated on nt_flow (e.g. GENEVE_OPT TLV parser creation)
9377 : : * take the non-template branch.
9378 : : *
9379 : : * Return / ownership:
9380 : : * - NULL on validation or allocation failure (error populated).
9381 : : * - `items` unchanged when no prepending is required; *copied_items == NULL.
9382 : : * - A newly-allocated array otherwise; also stored in *copied_items. The
9383 : : * caller must mlx5_free(*copied_items) on every path (it is safe to call
9384 : : * with NULL). Do not free the returned pointer directly.
9385 : : */
9386 : : static const struct rte_flow_item *
9387 : 0 : flow_hw_adjust_pattern(struct rte_eth_dev *dev, const struct rte_flow_pattern_template_attr *attr,
9388 : : bool nt_flow, const struct rte_flow_item *items, uint64_t *item_flags,
9389 : : uint64_t *nb_items, struct rte_flow_item **copied_items,
9390 : : struct rte_flow_error *error)
9391 : : {
9392 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
9393 : 0 : struct rte_flow_item_ethdev port_spec = {.port_id = dev->data->port_id};
9394 : 0 : struct rte_flow_item port = {
9395 : : .type = RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT,
9396 : : .mask = &rte_flow_item_ethdev_mask,
9397 : : };
9398 : 0 : struct rte_flow_item_tag tag_v = {
9399 : : .data = 0,
9400 : : .index = REG_C_0,
9401 : : };
9402 : 0 : struct rte_flow_item_tag tag_m = {
9403 : : .data = flow_hw_tx_tag_regc_mask(dev),
9404 : : .index = 0xff,
9405 : : };
9406 : 0 : struct rte_flow_item tag = {
9407 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_TAG,
9408 : : .spec = &tag_v,
9409 : : .mask = &tag_m,
9410 : : .last = NULL,
9411 : : };
9412 : : int rc;
9413 : :
9414 [ # # # # ]: 0 : if (!copied_items || !item_flags || !nb_items)
9415 : : return NULL;
9416 : :
9417 [ # # ]: 0 : if (nt_flow) {
9418 : 0 : port.spec = &port_spec;
9419 : 0 : tag_v.data = flow_hw_tx_tag_regc_value(dev);
9420 : : }
9421 : :
9422 : : /*
9423 : : * item_flags must be zero-initialized: __flow_hw_pattern_validate()
9424 : : * OR-accumulates bits into it and reads it (MLX5_FLOW_LAYER_TUNNEL)
9425 : : * on the first iteration.
9426 : : */
9427 : 0 : *item_flags = 0;
9428 : :
9429 : : /* Validate application items only */
9430 : 0 : rc = __flow_hw_pattern_validate(dev, attr, items, item_flags, nt_flow, error);
9431 [ # # ]: 0 : if (rc < 0)
9432 : : return NULL;
9433 : 0 : *nb_items = rc;
9434 : :
9435 [ # # # # ]: 0 : if (priv->sh->config.dv_esw_en && attr->ingress && !attr->egress && !attr->transfer) {
9436 : 0 : *copied_items = flow_hw_prepend_item(items, *nb_items, &port, error);
9437 [ # # ]: 0 : if (!*copied_items)
9438 : : return NULL;
9439 : 0 : return *copied_items;
9440 [ # # # # ]: 0 : } else if (priv->sh->config.dv_esw_en && !attr->ingress && attr->egress &&
9441 : : !attr->transfer) {
9442 [ # # ]: 0 : if (*item_flags & MLX5_FLOW_ITEM_SQ) {
9443 : 0 : DRV_LOG(DEBUG,
9444 : : "Port %u: explicit SQ item present, omitting implicit "
9445 : : "REG_C_0 match for egress pattern",
9446 : : dev->data->port_id);
9447 : 0 : return items;
9448 : : }
9449 : 0 : *copied_items = flow_hw_prepend_item(items, *nb_items, &tag, error);
9450 [ # # ]: 0 : if (!*copied_items)
9451 : : return NULL;
9452 : 0 : return *copied_items;
9453 : : }
9454 : : return items;
9455 : : }
9456 : :
9457 : : /**
9458 : : * Create flow item template.
9459 : : *
9460 : : * @param[in] dev
9461 : : * Pointer to the rte_eth_dev structure.
9462 : : * @param[in] attr
9463 : : * Pointer to the item template attributes.
9464 : : * @param[in] items
9465 : : * The template item pattern.
9466 : : * @param[out] error
9467 : : * Pointer to error structure.
9468 : : *
9469 : : * @return
9470 : : * Item template pointer on success, NULL otherwise and rte_errno is set.
9471 : : */
9472 : : static struct rte_flow_pattern_template *
9473 : 0 : flow_hw_pattern_template_create(struct rte_eth_dev *dev,
9474 : : const struct rte_flow_pattern_template_attr *attr,
9475 : : const struct rte_flow_item items[],
9476 : : bool external,
9477 : : struct rte_flow_error *error)
9478 : : {
9479 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
9480 : : struct rte_flow_pattern_template *it;
9481 : 0 : struct rte_flow_item *copied_items = NULL;
9482 : : const struct rte_flow_item *tmpl_items;
9483 : : int it_items_size;
9484 : : uint64_t orig_item_nb, item_flags;
9485 : : unsigned int i = 0;
9486 : : int rc;
9487 : :
9488 : 0 : tmpl_items = flow_hw_adjust_pattern(dev, attr, false, items, &item_flags, &orig_item_nb,
9489 : : &copied_items, error);
9490 [ # # ]: 0 : if (!tmpl_items)
9491 : : return NULL;
9492 : :
9493 : 0 : it = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*it), 0, SOCKET_ID_ANY);
9494 [ # # ]: 0 : if (!it) {
9495 : 0 : rte_flow_error_set(error, ENOMEM,
9496 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9497 : : NULL,
9498 : : "cannot allocate item template");
9499 : 0 : goto error;
9500 : : }
9501 : 0 : it->attr = *attr;
9502 : 0 : it->item_flags = item_flags;
9503 : 0 : it->orig_item_nb = orig_item_nb;
9504 : 0 : it_items_size = rte_flow_conv(RTE_FLOW_CONV_OP_PATTERN, NULL, 0, tmpl_items, error);
9505 [ # # ]: 0 : if (it_items_size <= 0) {
9506 : 0 : rte_flow_error_set(error, ENOMEM,
9507 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9508 : : NULL,
9509 : : "Failed to determine buffer size for pattern");
9510 : 0 : goto error;
9511 : : }
9512 : 0 : it_items_size = RTE_ALIGN(it_items_size, 16);
9513 : 0 : it->items = mlx5_malloc(MLX5_MEM_ZERO, it_items_size, 0, SOCKET_ID_ANY);
9514 [ # # ]: 0 : if (it->items == NULL) {
9515 : 0 : rte_flow_error_set(error, ENOMEM,
9516 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9517 : : NULL,
9518 : : "Cannot allocate memory for pattern");
9519 : 0 : goto error;
9520 : : }
9521 : 0 : rc = rte_flow_conv(RTE_FLOW_CONV_OP_PATTERN, it->items, it_items_size, tmpl_items, error);
9522 [ # # ]: 0 : if (rc <= 0) {
9523 : 0 : rte_flow_error_set(error, ENOMEM,
9524 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9525 : : NULL,
9526 : : "Failed to store pattern");
9527 : 0 : goto error;
9528 : : }
9529 : 0 : it->mt = mlx5dr_match_template_create(tmpl_items, attr->relaxed_matching);
9530 [ # # ]: 0 : if (!it->mt) {
9531 : 0 : rte_flow_error_set(error, rte_errno,
9532 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9533 : : NULL,
9534 : : "cannot create match template");
9535 : 0 : goto error;
9536 : : }
9537 [ # # ]: 0 : if (copied_items) {
9538 [ # # ]: 0 : if (attr->ingress)
9539 : 0 : it->implicit_port = true;
9540 [ # # ]: 0 : else if (attr->egress)
9541 : 0 : it->implicit_tag = true;
9542 : 0 : mlx5_free(copied_items);
9543 : 0 : copied_items = NULL;
9544 : : }
9545 : : /* Either inner or outer, can't both. */
9546 [ # # ]: 0 : if (it->item_flags & (MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT |
9547 : : MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT)) {
9548 [ # # ]: 0 : if (((it->item_flags & MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT) &&
9549 [ # # ]: 0 : (it->item_flags & MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT)) ||
9550 : 0 : (mlx5_alloc_srh_flex_parser(dev))) {
9551 : 0 : rte_flow_error_set(error, rte_errno,
9552 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9553 : : "cannot create IPv6 routing extension support");
9554 : 0 : goto error;
9555 : : }
9556 : : }
9557 [ # # ]: 0 : if (it->item_flags & MLX5_FLOW_ITEM_FLEX) {
9558 [ # # ]: 0 : for (i = 0; items[i].type != RTE_FLOW_ITEM_TYPE_END; i++) {
9559 : 0 : const struct rte_flow_item_flex *spec = items[i].spec;
9560 : : struct rte_flow_item_flex_handle *handle;
9561 : :
9562 [ # # ]: 0 : if (items[i].type != RTE_FLOW_ITEM_TYPE_FLEX)
9563 : 0 : continue;
9564 : 0 : handle = spec->handle;
9565 [ # # ]: 0 : if (flow_hw_flex_item_acquire(dev, handle,
9566 : 0 : &it->flex_item)) {
9567 : 0 : rte_flow_error_set(error, EINVAL,
9568 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9569 : : NULL, "cannot create hw FLEX item");
9570 : 0 : goto error;
9571 : : }
9572 : : }
9573 : : }
9574 [ # # ]: 0 : if (it->item_flags & MLX5_FLOW_LAYER_GENEVE_OPT) {
9575 [ # # ]: 0 : for (i = 0; items[i].type != RTE_FLOW_ITEM_TYPE_END; i++) {
9576 : 0 : const struct rte_flow_item_geneve_opt *spec =
9577 : : items[i].spec;
9578 : :
9579 [ # # ]: 0 : if (items[i].type != RTE_FLOW_ITEM_TYPE_GENEVE_OPT)
9580 : 0 : continue;
9581 [ # # ]: 0 : if (mlx5_geneve_tlv_option_register(priv, spec,
9582 : 0 : &it->geneve_opt_mng)) {
9583 : 0 : rte_flow_error_set(error, EINVAL,
9584 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9585 : : NULL, "cannot register GENEVE TLV option");
9586 : 0 : goto error;
9587 : : }
9588 : : }
9589 : : }
9590 : 0 : rte_atomic_fetch_add_explicit(&it->refcnt, 1, rte_memory_order_relaxed);
9591 [ # # ]: 0 : if (external) {
9592 : 0 : rc = pattern_template_validate(dev, &it, 1, error);
9593 [ # # ]: 0 : if (rc)
9594 : 0 : goto error;
9595 : : }
9596 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->flow_hw_itt, it, next);
9597 : 0 : return it;
9598 : 0 : error:
9599 [ # # ]: 0 : if (it) {
9600 [ # # ]: 0 : if (it->flex_item)
9601 : 0 : flow_hw_flex_item_release(dev, &it->flex_item);
9602 [ # # ]: 0 : if (it->geneve_opt_mng.nb_options)
9603 : 0 : mlx5_geneve_tlv_options_unregister(priv, &it->geneve_opt_mng);
9604 [ # # ]: 0 : if (it->mt)
9605 : 0 : claim_zero(mlx5dr_match_template_destroy(it->mt));
9606 : 0 : mlx5_free(it->items);
9607 : 0 : mlx5_free(it);
9608 : : }
9609 [ # # ]: 0 : if (copied_items)
9610 : 0 : mlx5_free(copied_items);
9611 : : return NULL;
9612 : : }
9613 : :
9614 : : static struct rte_flow_pattern_template *
9615 : 0 : flow_hw_external_pattern_template_create
9616 : : (struct rte_eth_dev *dev,
9617 : : const struct rte_flow_pattern_template_attr *attr,
9618 : : const struct rte_flow_item items[],
9619 : : struct rte_flow_error *error)
9620 : : {
9621 : 0 : return flow_hw_pattern_template_create(dev, attr, items, true, error);
9622 : : }
9623 : :
9624 : : /**
9625 : : * Destroy flow item template.
9626 : : *
9627 : : * @param[in] dev
9628 : : * Pointer to the rte_eth_dev structure.
9629 : : * @param[in] template
9630 : : * Pointer to the item template to be destroyed.
9631 : : * @param[out] error
9632 : : * Pointer to error structure.
9633 : : *
9634 : : * @return
9635 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
9636 : : */
9637 : : static int
9638 : 0 : flow_hw_pattern_template_destroy(struct rte_eth_dev *dev,
9639 : : struct rte_flow_pattern_template *template,
9640 : : struct rte_flow_error *error __rte_unused)
9641 : : {
9642 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
9643 : :
9644 [ # # ]: 0 : if (rte_atomic_load_explicit(&template->refcnt, rte_memory_order_relaxed) > 1) {
9645 : 0 : DRV_LOG(WARNING, "Item template %p is still in use.",
9646 : : (void *)template);
9647 : 0 : return rte_flow_error_set(error, EBUSY,
9648 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9649 : : NULL,
9650 : : "item template is in use");
9651 : : }
9652 [ # # ]: 0 : if (template->item_flags & (MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT |
9653 : : MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT))
9654 : 0 : mlx5_free_srh_flex_parser(dev);
9655 [ # # ]: 0 : LIST_REMOVE(template, next);
9656 : 0 : flow_hw_flex_item_release(dev, &template->flex_item);
9657 : 0 : mlx5_geneve_tlv_options_unregister(priv, &template->geneve_opt_mng);
9658 : 0 : claim_zero(mlx5dr_match_template_destroy(template->mt));
9659 : 0 : mlx5_free(template->items);
9660 : 0 : mlx5_free(template);
9661 : 0 : return 0;
9662 : : }
9663 : :
9664 : : /*
9665 : : * Get information about HWS pre-configurable resources.
9666 : : *
9667 : : * @param[in] dev
9668 : : * Pointer to the rte_eth_dev structure.
9669 : : * @param[out] port_info
9670 : : * Pointer to port information.
9671 : : * @param[out] queue_info
9672 : : * Pointer to queue information.
9673 : : * @param[out] error
9674 : : * Pointer to error structure.
9675 : : *
9676 : : * @return
9677 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
9678 : : */
9679 : : static int
9680 : 0 : flow_hw_info_get(struct rte_eth_dev *dev,
9681 : : struct rte_flow_port_info *port_info,
9682 : : struct rte_flow_queue_info *queue_info,
9683 : : struct rte_flow_error *error __rte_unused)
9684 : : {
9685 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
9686 : 0 : uint16_t port_id = dev->data->port_id;
9687 : : struct rte_mtr_capabilities mtr_cap;
9688 : : int ret;
9689 : :
9690 : : memset(port_info, 0, sizeof(*port_info));
9691 : : /* Queue size is unlimited from low-level. */
9692 : 0 : port_info->max_nb_queues = UINT32_MAX;
9693 : 0 : queue_info->max_size = UINT32_MAX;
9694 : :
9695 : : memset(&mtr_cap, 0, sizeof(struct rte_mtr_capabilities));
9696 : 0 : ret = rte_mtr_capabilities_get(port_id, &mtr_cap, NULL);
9697 [ # # ]: 0 : if (!ret)
9698 : 0 : port_info->max_nb_meters = mtr_cap.n_max;
9699 : 0 : port_info->max_nb_counters = priv->sh->hws_max_nb_counters;
9700 : 0 : port_info->max_nb_aging_objects = port_info->max_nb_counters;
9701 : 0 : return 0;
9702 : : }
9703 : :
9704 : : /**
9705 : : * Create group callback.
9706 : : *
9707 : : * @param[in] tool_ctx
9708 : : * Pointer to the hash list related context.
9709 : : * @param[in] cb_ctx
9710 : : * Pointer to the group creation context.
9711 : : *
9712 : : * @return
9713 : : * Group entry on success, NULL otherwise and rte_errno is set.
9714 : : */
9715 : : struct mlx5_list_entry *
9716 : 0 : mlx5_flow_hw_grp_create_cb(void *tool_ctx, void *cb_ctx)
9717 : : {
9718 : : struct mlx5_dev_ctx_shared *sh = tool_ctx;
9719 : : struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9720 : 0 : struct rte_eth_dev *dev = ctx->dev;
9721 : 0 : struct rte_flow_attr *attr = (struct rte_flow_attr *)ctx->data;
9722 : 0 : uint32_t *specialize = (uint32_t *)ctx->data2;
9723 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
9724 : : bool unified_fdb = is_unified_fdb(priv);
9725 : 0 : struct mlx5dr_table_attr dr_tbl_attr = {0};
9726 : 0 : struct rte_flow_error *error = ctx->error;
9727 : : struct mlx5_flow_group *grp_data;
9728 : : struct mlx5dr_table *tbl = NULL;
9729 : : struct mlx5dr_action *jump;
9730 : : uint32_t hws_flags;
9731 : 0 : uint32_t idx = 0;
9732 [ # # # # : 0 : MKSTR(matcher_name, "%s_%s_%u_%u_matcher_list",
# # # # ]
9733 : : attr->transfer ? "FDB" : "NIC", attr->egress ? "egress" : "ingress",
9734 : : attr->group, idx);
9735 : :
9736 : 0 : grp_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_HW_GRP], &idx);
9737 [ # # ]: 0 : if (!grp_data) {
9738 : 0 : rte_flow_error_set(error, ENOMEM,
9739 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9740 : : NULL,
9741 : : "cannot allocate flow table data entry");
9742 : 0 : return NULL;
9743 : : }
9744 : 0 : dr_tbl_attr.level = attr->group;
9745 : 0 : dr_tbl_attr.type = get_mlx5dr_table_type(attr, *specialize, unified_fdb);
9746 : 0 : tbl = mlx5dr_table_create(priv->dr_ctx, &dr_tbl_attr);
9747 [ # # ]: 0 : if (!tbl)
9748 : 0 : goto error;
9749 : 0 : grp_data->tbl = tbl;
9750 [ # # ]: 0 : if (attr->group) {
9751 : 0 : hws_flags = mlx5_hw_act_dest_table_flag[dr_tbl_attr.type];
9752 : : /* For case of jump from FDB Tx to FDB Rx as it is supported now. */
9753 [ # # # # ]: 0 : if (priv->jump_fdb_rx_en &&
9754 : : dr_tbl_attr.type == MLX5DR_TABLE_TYPE_FDB_RX)
9755 : 0 : hws_flags |= MLX5DR_ACTION_FLAG_HWS_FDB_TX;
9756 : : /* Jump action be used by non-root table. */
9757 : 0 : jump = mlx5dr_action_create_dest_table
9758 : : (priv->dr_ctx, tbl,
9759 : : hws_flags);
9760 [ # # ]: 0 : if (!jump)
9761 : 0 : goto error;
9762 : 0 : grp_data->jump.hws_action = jump;
9763 : : /* Jump action be used by root table. */
9764 : 0 : jump = mlx5dr_action_create_dest_table
9765 : : (priv->dr_ctx, tbl,
9766 : : mlx5_hw_act_flag[MLX5_HW_ACTION_FLAG_ROOT]
9767 : 0 : [dr_tbl_attr.type]);
9768 [ # # ]: 0 : if (!jump)
9769 : 0 : goto error;
9770 : 0 : grp_data->jump.root_action = jump;
9771 : : }
9772 : :
9773 : 0 : grp_data->matchers = mlx5_list_create(matcher_name, sh, true,
9774 : : mlx5_flow_matcher_create_cb,
9775 : : mlx5_flow_matcher_match_cb,
9776 : : mlx5_flow_matcher_remove_cb,
9777 : : mlx5_flow_matcher_clone_cb,
9778 : : mlx5_flow_matcher_clone_free_cb);
9779 : 0 : grp_data->dev = dev;
9780 : 0 : grp_data->idx = idx;
9781 : 0 : grp_data->group_id = attr->group;
9782 : 0 : grp_data->type = dr_tbl_attr.type;
9783 : 0 : return &grp_data->entry;
9784 : 0 : error:
9785 [ # # ]: 0 : if (grp_data->jump.root_action)
9786 : 0 : mlx5dr_action_destroy(grp_data->jump.root_action);
9787 [ # # ]: 0 : if (grp_data->jump.hws_action)
9788 : 0 : mlx5dr_action_destroy(grp_data->jump.hws_action);
9789 [ # # ]: 0 : if (tbl)
9790 : 0 : mlx5dr_table_destroy(tbl);
9791 [ # # ]: 0 : if (idx)
9792 : 0 : mlx5_ipool_free(sh->ipool[MLX5_IPOOL_HW_GRP], idx);
9793 : 0 : rte_flow_error_set(error, ENOMEM,
9794 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9795 : : NULL,
9796 : : "cannot allocate flow dr table");
9797 : 0 : return NULL;
9798 : : }
9799 : :
9800 : : /**
9801 : : * Remove group callback.
9802 : : *
9803 : : * @param[in] tool_ctx
9804 : : * Pointer to the hash list related context.
9805 : : * @param[in] entry
9806 : : * Pointer to the entry to be removed.
9807 : : */
9808 : : void
9809 : 0 : mlx5_flow_hw_grp_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
9810 : : {
9811 : : struct mlx5_dev_ctx_shared *sh = tool_ctx;
9812 : : struct mlx5_flow_group *grp_data =
9813 : : container_of(entry, struct mlx5_flow_group, entry);
9814 : :
9815 : : MLX5_ASSERT(entry && sh);
9816 : : /* To use the wrapper glue functions instead. */
9817 [ # # ]: 0 : if (grp_data->jump.hws_action)
9818 : 0 : mlx5dr_action_destroy(grp_data->jump.hws_action);
9819 [ # # ]: 0 : if (grp_data->jump.root_action)
9820 : 0 : mlx5dr_action_destroy(grp_data->jump.root_action);
9821 : 0 : mlx5_list_destroy(grp_data->matchers);
9822 : 0 : mlx5dr_table_destroy(grp_data->tbl);
9823 : 0 : mlx5_ipool_free(sh->ipool[MLX5_IPOOL_HW_GRP], grp_data->idx);
9824 : 0 : }
9825 : :
9826 : : /**
9827 : : * Match group callback.
9828 : : *
9829 : : * @param[in] tool_ctx
9830 : : * Pointer to the hash list related context.
9831 : : * @param[in] entry
9832 : : * Pointer to the group to be matched.
9833 : : * @param[in] cb_ctx
9834 : : * Pointer to the group matching context.
9835 : : *
9836 : : * @return
9837 : : * 0 on matched, 1 on miss matched.
9838 : : */
9839 : : int
9840 : 0 : mlx5_flow_hw_grp_match_cb(void *tool_ctx __rte_unused, struct mlx5_list_entry *entry,
9841 : : void *cb_ctx)
9842 : : {
9843 : : struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9844 : : struct mlx5_flow_group *grp_data =
9845 : : container_of(entry, struct mlx5_flow_group, entry);
9846 : 0 : struct rte_flow_attr *attr =
9847 : : (struct rte_flow_attr *)ctx->data;
9848 : :
9849 : 0 : return (grp_data->dev != ctx->dev) ||
9850 [ # # ]: 0 : (grp_data->group_id != attr->group) ||
9851 [ # # # # ]: 0 : ((grp_data->type < MLX5DR_TABLE_TYPE_FDB) &&
9852 [ # # ]: 0 : attr->transfer) ||
9853 [ # # ]: 0 : ((grp_data->type != MLX5DR_TABLE_TYPE_NIC_TX) &&
9854 [ # # # # ]: 0 : attr->egress) ||
9855 [ # # ]: 0 : ((grp_data->type != MLX5DR_TABLE_TYPE_NIC_RX) &&
9856 : : attr->ingress);
9857 : : }
9858 : :
9859 : : /**
9860 : : * Clone group entry callback.
9861 : : *
9862 : : * @param[in] tool_ctx
9863 : : * Pointer to the hash list related context.
9864 : : * @param[in] entry
9865 : : * Pointer to the group to be matched.
9866 : : * @param[in] cb_ctx
9867 : : * Pointer to the group matching context.
9868 : : *
9869 : : * @return
9870 : : * 0 on matched, 1 on miss matched.
9871 : : */
9872 : : struct mlx5_list_entry *
9873 : 0 : mlx5_flow_hw_grp_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
9874 : : void *cb_ctx)
9875 : : {
9876 : : struct mlx5_dev_ctx_shared *sh = tool_ctx;
9877 : : struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9878 : : struct mlx5_flow_group *grp_data;
9879 : : struct mlx5_flow_group *old_grp_data;
9880 : 0 : struct rte_flow_error *error = ctx->error;
9881 : 0 : uint32_t idx = 0;
9882 : :
9883 : 0 : grp_data = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_HW_GRP], &idx);
9884 [ # # ]: 0 : if (!grp_data) {
9885 : 0 : rte_flow_error_set(error, ENOMEM,
9886 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9887 : : NULL,
9888 : : "cannot allocate flow table data entry");
9889 : 0 : return NULL;
9890 : : }
9891 : : old_grp_data = container_of(oentry, typeof(*old_grp_data), entry);
9892 : : memcpy(grp_data, old_grp_data, sizeof(*grp_data));
9893 : 0 : grp_data->idx = idx;
9894 : 0 : return &grp_data->entry;
9895 : : }
9896 : :
9897 : : /**
9898 : : * Free cloned group entry callback.
9899 : : *
9900 : : * @param[in] tool_ctx
9901 : : * Pointer to the hash list related context.
9902 : : * @param[in] entry
9903 : : * Pointer to the group to be freed.
9904 : : */
9905 : : void
9906 : 0 : mlx5_flow_hw_grp_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
9907 : : {
9908 : : struct mlx5_dev_ctx_shared *sh = tool_ctx;
9909 : : struct mlx5_flow_group *grp_data =
9910 : : container_of(entry, struct mlx5_flow_group, entry);
9911 : :
9912 : 0 : mlx5_ipool_free(sh->ipool[MLX5_IPOOL_HW_GRP], grp_data->idx);
9913 : 0 : }
9914 : :
9915 : : /**
9916 : : * Create and cache a vport action for given @p dev port. vport actions
9917 : : * cache is used in HWS with FDB flows.
9918 : : *
9919 : : * This function does not create any function if proxy port for @p dev port
9920 : : * was not configured for HW Steering.
9921 : : *
9922 : : * This function assumes that E-Switch is enabled and PMD is running with
9923 : : * HW Steering configured.
9924 : : *
9925 : : * @param dev
9926 : : * Pointer to Ethernet device which will be the action destination.
9927 : : *
9928 : : * @return
9929 : : * 0 on success, positive value otherwise.
9930 : : */
9931 : : int
9932 : 0 : mlx5_flow_hw_create_vport_action(struct rte_eth_dev *dev)
9933 : : {
9934 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
9935 : : struct rte_eth_dev *proxy_dev;
9936 : : struct mlx5_priv *proxy_priv;
9937 : 0 : uint16_t port_id = dev->data->port_id;
9938 : 0 : uint16_t proxy_port_id = port_id;
9939 : : int ret;
9940 : :
9941 : 0 : ret = mlx5_flow_pick_transfer_proxy(dev, &proxy_port_id, NULL);
9942 [ # # ]: 0 : if (ret)
9943 : : return ret;
9944 : 0 : proxy_dev = &rte_eth_devices[proxy_port_id];
9945 : 0 : proxy_priv = proxy_dev->data->dev_private;
9946 [ # # ]: 0 : if (!proxy_priv->hw_vport)
9947 : : return 0;
9948 [ # # ]: 0 : if (proxy_priv->hw_vport[port_id]) {
9949 : 0 : DRV_LOG(ERR, "port %u HWS vport action already created",
9950 : : port_id);
9951 : 0 : return -EINVAL;
9952 : : }
9953 [ # # ]: 0 : proxy_priv->hw_vport[port_id] = mlx5dr_action_create_dest_vport
9954 : : (proxy_priv->dr_ctx, priv->dev_port,
9955 : : is_unified_fdb(priv) ?
9956 : : (MLX5DR_ACTION_FLAG_HWS_FDB_RX |
9957 : : MLX5DR_ACTION_FLAG_HWS_FDB_TX |
9958 : : MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED) :
9959 : : MLX5DR_ACTION_FLAG_HWS_FDB);
9960 [ # # ]: 0 : if (!proxy_priv->hw_vport[port_id]) {
9961 : 0 : DRV_LOG(ERR, "port %u unable to create HWS vport action",
9962 : : port_id);
9963 : 0 : return -EINVAL;
9964 : : }
9965 : : return 0;
9966 : : }
9967 : :
9968 : : /**
9969 : : * Destroys the vport action associated with @p dev device
9970 : : * from actions' cache.
9971 : : *
9972 : : * This function does not destroy any action if there is no action cached
9973 : : * for @p dev or proxy port was not configured for HW Steering.
9974 : : *
9975 : : * This function assumes that E-Switch is enabled and PMD is running with
9976 : : * HW Steering configured.
9977 : : *
9978 : : * @param dev
9979 : : * Pointer to Ethernet device which will be the action destination.
9980 : : */
9981 : : void
9982 : 0 : mlx5_flow_hw_destroy_vport_action(struct rte_eth_dev *dev)
9983 : : {
9984 : : struct rte_eth_dev *proxy_dev;
9985 : : struct mlx5_priv *proxy_priv;
9986 : 0 : uint16_t port_id = dev->data->port_id;
9987 : 0 : uint16_t proxy_port_id = port_id;
9988 : :
9989 [ # # ]: 0 : if (mlx5_flow_pick_transfer_proxy(dev, &proxy_port_id, NULL))
9990 : 0 : return;
9991 : 0 : proxy_dev = &rte_eth_devices[proxy_port_id];
9992 : 0 : proxy_priv = proxy_dev->data->dev_private;
9993 [ # # # # ]: 0 : if (!proxy_priv->hw_vport || !proxy_priv->hw_vport[port_id])
9994 : : return;
9995 : 0 : mlx5dr_action_destroy(proxy_priv->hw_vport[port_id]);
9996 : 0 : proxy_priv->hw_vport[port_id] = NULL;
9997 : : }
9998 : :
9999 : : static int
10000 : 0 : flow_hw_create_vport_actions(struct mlx5_priv *priv)
10001 : : {
10002 : : uint16_t port_id;
10003 : :
10004 : : MLX5_ASSERT(!priv->hw_vport);
10005 : : bool unified_fdb = is_unified_fdb(priv);
10006 : 0 : priv->hw_vport = mlx5_malloc(MLX5_MEM_ZERO,
10007 : : sizeof(*priv->hw_vport) * RTE_MAX_ETHPORTS,
10008 : : 0, SOCKET_ID_ANY);
10009 [ # # ]: 0 : if (!priv->hw_vport)
10010 : : return -ENOMEM;
10011 : 0 : DRV_LOG(DEBUG, "port %u :: creating vport actions", priv->dev_data->port_id);
10012 : 0 : DRV_LOG(DEBUG, "port %u :: domain_id=%u", priv->dev_data->port_id, priv->domain_id);
10013 [ # # ]: 0 : MLX5_ETH_FOREACH_DEV(port_id, NULL) {
10014 : 0 : struct mlx5_priv *port_priv = rte_eth_devices[port_id].data->dev_private;
10015 : :
10016 [ # # ]: 0 : if (!port_priv ||
10017 [ # # ]: 0 : port_priv->domain_id != priv->domain_id)
10018 : 0 : continue;
10019 : 0 : DRV_LOG(DEBUG, "port %u :: for port_id=%u, calling mlx5dr_action_create_dest_vport() with ibport=%u",
10020 : : priv->dev_data->port_id, port_id, port_priv->dev_port);
10021 [ # # ]: 0 : priv->hw_vport[port_id] = mlx5dr_action_create_dest_vport
10022 : : (priv->dr_ctx, port_priv->dev_port,
10023 : : unified_fdb ?
10024 : : (MLX5DR_ACTION_FLAG_HWS_FDB_RX |
10025 : : MLX5DR_ACTION_FLAG_HWS_FDB_TX |
10026 : : MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED) :
10027 : : MLX5DR_ACTION_FLAG_HWS_FDB);
10028 : 0 : DRV_LOG(DEBUG, "port %u :: priv->hw_vport[%u]=%p",
10029 : : priv->dev_data->port_id, port_id, (void *)priv->hw_vport[port_id]);
10030 [ # # ]: 0 : if (!priv->hw_vport[port_id])
10031 : : return -EINVAL;
10032 : : }
10033 : : return 0;
10034 : : }
10035 : :
10036 : : static void
10037 : 0 : flow_hw_free_vport_actions(struct mlx5_priv *priv)
10038 : : {
10039 : : uint16_t port_id;
10040 : :
10041 [ # # ]: 0 : if (!priv->hw_vport)
10042 : : return;
10043 [ # # ]: 0 : for (port_id = 0; port_id < RTE_MAX_ETHPORTS; ++port_id)
10044 [ # # ]: 0 : if (priv->hw_vport[port_id])
10045 : 0 : mlx5dr_action_destroy(priv->hw_vport[port_id]);
10046 : 0 : mlx5_free(priv->hw_vport);
10047 : 0 : priv->hw_vport = NULL;
10048 : : }
10049 : :
10050 : : static bool
10051 : : flow_hw_should_create_nat64_actions(struct mlx5_priv *priv)
10052 : : {
10053 : : int i;
10054 : :
10055 : : /* Check if all registers are available. */
10056 [ # # ]: 0 : for (i = 0; i < MLX5_FLOW_NAT64_REGS_MAX; ++i)
10057 [ # # ]: 0 : if (priv->sh->registers.nat64_regs[i] == REG_NON)
10058 : : return false;
10059 : :
10060 : : return true;
10061 : : }
10062 : :
10063 : : /**
10064 : : * Create an egress pattern template matching on source SQ.
10065 : : *
10066 : : * @param dev
10067 : : * Pointer to Ethernet device.
10068 : : * @param[out] error
10069 : : * Pointer to error structure.
10070 : : *
10071 : : * @return
10072 : : * Pointer to pattern template on success. NULL otherwise, and rte_errno is set.
10073 : : */
10074 : : static struct rte_flow_pattern_template *
10075 : 0 : flow_hw_create_tx_repr_sq_pattern_tmpl(struct rte_eth_dev *dev, struct rte_flow_error *error)
10076 : : {
10077 : 0 : struct rte_flow_pattern_template_attr attr = {
10078 : : .relaxed_matching = 0,
10079 : : .egress = 1,
10080 : : };
10081 : 0 : struct mlx5_rte_flow_item_sq sq_mask = {
10082 : : .queue = UINT32_MAX,
10083 : : };
10084 : 0 : struct rte_flow_item items[] = {
10085 : : {
10086 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_SQ,
10087 : : .mask = &sq_mask,
10088 : : },
10089 : : {
10090 : : .type = RTE_FLOW_ITEM_TYPE_END,
10091 : : },
10092 : : };
10093 : :
10094 : 0 : return flow_hw_pattern_template_create(dev, &attr, items, false, error);
10095 : : }
10096 : :
10097 : : static __rte_always_inline uint32_t
10098 : : flow_hw_tx_tag_regc_mask(struct rte_eth_dev *dev)
10099 : : {
10100 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
10101 : :
10102 [ # # ]: 0 : if (priv->vport_meta_mask != 0)
10103 : 0 : return priv->sh->dv_regc0_mask;
10104 : : else
10105 : : return UINT32_MAX;
10106 : : }
10107 : :
10108 : : static __rte_always_inline uint32_t
10109 : : flow_hw_tx_tag_regc_value(struct rte_eth_dev *dev)
10110 : : {
10111 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
10112 : :
10113 [ # # # # : 0 : if (priv->vport_meta_mask != 0)
# # ]
10114 : 0 : return priv->vport_meta_tag >> (rte_bsf32(priv->vport_meta_mask));
10115 : :
10116 : : /* Without REG_C match value available, resort to matching vport ID. */
10117 : 0 : return priv->vport_id | (priv->sh->cdev->config.hca_attr.vhca_id << 16);
10118 : : }
10119 : :
10120 : : static void
10121 : : flow_hw_update_action_mask(struct rte_flow_action *action,
10122 : : struct rte_flow_action *mask,
10123 : : enum rte_flow_action_type type,
10124 : : void *conf_v,
10125 : : void *conf_m)
10126 : : {
10127 : 0 : action->type = type;
10128 : 0 : action->conf = conf_v;
10129 : 0 : mask->type = type;
10130 : 0 : mask->conf = conf_m;
10131 : : }
10132 : :
10133 : : /**
10134 : : * Create an egress actions template with MODIFY_FIELD action for setting unused REG_C_0 bits
10135 : : * to vport tag and JUMP action to group 1.
10136 : : *
10137 : : * If extended metadata mode is enabled, then MODIFY_FIELD action for copying software metadata
10138 : : * to REG_C_1 is added as well.
10139 : : *
10140 : : * @param dev
10141 : : * Pointer to Ethernet device.
10142 : : * @param[out] error
10143 : : * Pointer to error structure.
10144 : : *
10145 : : * @return
10146 : : * Pointer to actions template on success. NULL otherwise, and rte_errno is set.
10147 : : */
10148 : : static struct rte_flow_actions_template *
10149 [ # # ]: 0 : flow_hw_create_tx_repr_tag_jump_acts_tmpl(struct rte_eth_dev *dev,
10150 : : struct rte_flow_error *error)
10151 : : {
10152 : : uint32_t tag_mask = flow_hw_tx_tag_regc_mask(dev);
10153 : : uint32_t tag_value = flow_hw_tx_tag_regc_value(dev);
10154 : 0 : struct rte_flow_actions_template_attr attr = {
10155 : : .egress = 1,
10156 : : };
10157 [ # # ]: 0 : struct rte_flow_action_modify_field set_tag_v = {
10158 : : .operation = RTE_FLOW_MODIFY_SET,
10159 : : .dst = {
10160 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
10161 : : .tag_index = REG_C_0,
10162 : : .offset = rte_bsf32(tag_mask),
10163 : : },
10164 : : .src = {
10165 : : .field = RTE_FLOW_FIELD_VALUE,
10166 : : },
10167 : : .width = rte_popcount32(tag_mask),
10168 : : };
10169 : 0 : struct rte_flow_action_modify_field set_tag_m = {
10170 : : .operation = RTE_FLOW_MODIFY_SET,
10171 : : .dst = {
10172 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
10173 : : .level = UINT8_MAX,
10174 : : .tag_index = UINT8_MAX,
10175 : : .offset = UINT32_MAX,
10176 : : },
10177 : : .src = {
10178 : : .field = RTE_FLOW_FIELD_VALUE,
10179 : : },
10180 : : .width = UINT32_MAX,
10181 : : };
10182 : 0 : struct rte_flow_action_modify_field copy_metadata_v = {
10183 : : .operation = RTE_FLOW_MODIFY_SET,
10184 : : .dst = {
10185 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
10186 : : .tag_index = REG_C_1,
10187 : : },
10188 : : .src = {
10189 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
10190 : : .tag_index = REG_A,
10191 : : },
10192 : : .width = 32,
10193 : : };
10194 : 0 : struct rte_flow_action_modify_field copy_metadata_m = {
10195 : : .operation = RTE_FLOW_MODIFY_SET,
10196 : : .dst = {
10197 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
10198 : : .level = UINT8_MAX,
10199 : : .tag_index = UINT8_MAX,
10200 : : .offset = UINT32_MAX,
10201 : : },
10202 : : .src = {
10203 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
10204 : : .level = UINT8_MAX,
10205 : : .tag_index = UINT8_MAX,
10206 : : .offset = UINT32_MAX,
10207 : : },
10208 : : .width = UINT32_MAX,
10209 : : };
10210 : 0 : struct rte_flow_action_jump jump_v = {
10211 : : .group = MLX5_HW_LOWEST_USABLE_GROUP,
10212 : : };
10213 : 0 : struct rte_flow_action_jump jump_m = {
10214 : : .group = UINT32_MAX,
10215 : : };
10216 : 0 : struct rte_flow_action actions_v[4] = { { 0 } };
10217 [ # # ]: 0 : struct rte_flow_action actions_m[4] = { { 0 } };
10218 : : unsigned int idx = 0;
10219 : :
10220 : : rte_memcpy(set_tag_v.src.value, &tag_value, sizeof(tag_value));
10221 : : rte_memcpy(set_tag_m.src.value, &tag_mask, sizeof(tag_mask));
10222 : : flow_hw_update_action_mask(&actions_v[idx], &actions_m[idx],
10223 : : RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
10224 : : &set_tag_v, &set_tag_m);
10225 : : idx++;
10226 [ # # ]: 0 : if (MLX5_SH(dev)->config.dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS) {
10227 : : flow_hw_update_action_mask(&actions_v[idx], &actions_m[idx],
10228 : : RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
10229 : : ©_metadata_v, ©_metadata_m);
10230 : : idx++;
10231 : : }
10232 : : flow_hw_update_action_mask(&actions_v[idx], &actions_m[idx], RTE_FLOW_ACTION_TYPE_JUMP,
10233 : : &jump_v, &jump_m);
10234 : 0 : idx++;
10235 : : flow_hw_update_action_mask(&actions_v[idx], &actions_m[idx], RTE_FLOW_ACTION_TYPE_END,
10236 : : NULL, NULL);
10237 : : idx++;
10238 : : MLX5_ASSERT(idx <= RTE_DIM(actions_v));
10239 : 0 : return flow_hw_actions_template_create(dev, &attr, actions_v, actions_m, error);
10240 : : }
10241 : :
10242 : : static void
10243 : 0 : flow_hw_cleanup_tx_repr_tagging(struct rte_eth_dev *dev)
10244 : : {
10245 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
10246 : :
10247 [ # # ]: 0 : if (priv->hw_tx_repr_tagging_tbl) {
10248 : 0 : flow_hw_table_destroy(dev, priv->hw_tx_repr_tagging_tbl, NULL);
10249 : 0 : priv->hw_tx_repr_tagging_tbl = NULL;
10250 : : }
10251 [ # # ]: 0 : if (priv->hw_tx_repr_tagging_at) {
10252 : 0 : flow_hw_actions_template_destroy(dev, priv->hw_tx_repr_tagging_at, NULL);
10253 : 0 : priv->hw_tx_repr_tagging_at = NULL;
10254 : : }
10255 [ # # ]: 0 : if (priv->hw_tx_repr_tagging_pt) {
10256 : 0 : flow_hw_pattern_template_destroy(dev, priv->hw_tx_repr_tagging_pt, NULL);
10257 : 0 : priv->hw_tx_repr_tagging_pt = NULL;
10258 : : }
10259 : 0 : }
10260 : :
10261 : : /**
10262 : : * Setup templates and table used to create default Tx flow rules. These default rules
10263 : : * allow for matching Tx representor traffic using a vport tag placed in unused bits of
10264 : : * REG_C_0 register.
10265 : : *
10266 : : * @param dev
10267 : : * Pointer to Ethernet device.
10268 : : * @param[out] error
10269 : : * Pointer to error structure.
10270 : : *
10271 : : * @return
10272 : : * 0 on success, negative errno value otherwise.
10273 : : */
10274 : : static int
10275 : 0 : flow_hw_setup_tx_repr_tagging(struct rte_eth_dev *dev, struct rte_flow_error *error)
10276 : : {
10277 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
10278 : 0 : struct rte_flow_template_table_attr attr = {
10279 : : .flow_attr = {
10280 : : .group = 0,
10281 : : .priority = MLX5_HW_LOWEST_PRIO_ROOT,
10282 : : .egress = 1,
10283 : : },
10284 : : .nb_flows = MLX5_HW_CTRL_FLOW_NB_RULES,
10285 : : };
10286 : 0 : struct mlx5_flow_template_table_cfg cfg = {
10287 : : .attr = attr,
10288 : : .external = false,
10289 : : };
10290 : :
10291 : : MLX5_ASSERT(priv->sh->config.dv_esw_en);
10292 : 0 : priv->hw_tx_repr_tagging_pt =
10293 : 0 : flow_hw_create_tx_repr_sq_pattern_tmpl(dev, error);
10294 [ # # ]: 0 : if (!priv->hw_tx_repr_tagging_pt)
10295 : 0 : goto err;
10296 : 0 : priv->hw_tx_repr_tagging_at =
10297 : 0 : flow_hw_create_tx_repr_tag_jump_acts_tmpl(dev, error);
10298 [ # # ]: 0 : if (!priv->hw_tx_repr_tagging_at)
10299 : 0 : goto err;
10300 : 0 : priv->hw_tx_repr_tagging_tbl = flow_hw_table_create(dev, &cfg,
10301 : : &priv->hw_tx_repr_tagging_pt, 1,
10302 : : &priv->hw_tx_repr_tagging_at, 1,
10303 : : error);
10304 [ # # ]: 0 : if (!priv->hw_tx_repr_tagging_tbl)
10305 : 0 : goto err;
10306 : : return 0;
10307 : 0 : err:
10308 : 0 : flow_hw_cleanup_tx_repr_tagging(dev);
10309 : 0 : return -rte_errno;
10310 : : }
10311 : :
10312 : : static uint32_t
10313 : : flow_hw_esw_mgr_regc_marker_mask(struct rte_eth_dev *dev)
10314 : : {
10315 : 0 : uint32_t mask = MLX5_SH(dev)->dv_regc0_mask;
10316 : :
10317 : : /* Mask is verified during device initialization. */
10318 : : MLX5_ASSERT(mask != 0);
10319 : : return mask;
10320 : : }
10321 : :
10322 : : static uint32_t
10323 : : flow_hw_esw_mgr_regc_marker(struct rte_eth_dev *dev)
10324 : : {
10325 : 0 : uint32_t mask = MLX5_SH(dev)->dv_regc0_mask;
10326 : :
10327 : : /* Mask is verified during device initialization. */
10328 : : MLX5_ASSERT(mask != 0);
10329 : 0 : return RTE_BIT32(rte_bsf32(mask));
10330 : : }
10331 : :
10332 : : /**
10333 : : * Creates a flow pattern template used to match on E-Switch Manager.
10334 : : * This template is used to set up a table for SQ miss default flow.
10335 : : *
10336 : : * @param dev
10337 : : * Pointer to Ethernet device.
10338 : : * @param error
10339 : : * Pointer to error structure.
10340 : : *
10341 : : * @return
10342 : : * Pointer to flow pattern template on success, NULL otherwise.
10343 : : */
10344 : : static struct rte_flow_pattern_template *
10345 : 0 : flow_hw_create_ctrl_esw_mgr_pattern_template(struct rte_eth_dev *dev,
10346 : : struct rte_flow_error *error)
10347 : : {
10348 : 0 : struct rte_flow_pattern_template_attr attr = {
10349 : : .relaxed_matching = 0,
10350 : : .transfer = 1,
10351 : : };
10352 : 0 : struct rte_flow_item_ethdev port_spec = {
10353 : : .port_id = MLX5_REPRESENTED_PORT_ESW_MGR,
10354 : : };
10355 : 0 : struct rte_flow_item_ethdev port_mask = {
10356 : : .port_id = UINT16_MAX,
10357 : : };
10358 : 0 : struct mlx5_rte_flow_item_sq sq_mask = {
10359 : : .queue = UINT32_MAX,
10360 : : };
10361 : 0 : struct rte_flow_item items[] = {
10362 : : {
10363 : : .type = RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT,
10364 : : .spec = &port_spec,
10365 : : .mask = &port_mask,
10366 : : },
10367 : : {
10368 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_SQ,
10369 : : .mask = &sq_mask,
10370 : : },
10371 : : {
10372 : : .type = RTE_FLOW_ITEM_TYPE_END,
10373 : : },
10374 : : };
10375 : :
10376 : 0 : return flow_hw_pattern_template_create(dev, &attr, items, false, error);
10377 : : }
10378 : :
10379 : : /**
10380 : : * Creates a flow pattern template used to match REG_C_0 and a SQ.
10381 : : * Matching on REG_C_0 is set up to match on all bits usable by user-space.
10382 : : * If traffic was sent from E-Switch Manager, then all usable bits will be set to 0,
10383 : : * except the least significant bit, which will be set to 1.
10384 : : *
10385 : : * This template is used to set up a table for SQ miss default flow.
10386 : : *
10387 : : * @param dev
10388 : : * Pointer to Ethernet device.
10389 : : * @param error
10390 : : * Pointer to error structure.
10391 : : *
10392 : : * @return
10393 : : * Pointer to flow pattern template on success, NULL otherwise.
10394 : : */
10395 : : static struct rte_flow_pattern_template *
10396 : 0 : flow_hw_create_ctrl_regc_sq_pattern_template(struct rte_eth_dev *dev,
10397 : : struct rte_flow_error *error)
10398 : : {
10399 : 0 : struct rte_flow_pattern_template_attr attr = {
10400 : : .relaxed_matching = 0,
10401 : : .transfer = 1,
10402 : : };
10403 : 0 : struct rte_flow_item_tag reg_c0_spec = {
10404 : : .index = (uint8_t)REG_C_0,
10405 : : };
10406 : 0 : struct rte_flow_item_tag reg_c0_mask = {
10407 : : .index = 0xff,
10408 : : .data = flow_hw_esw_mgr_regc_marker_mask(dev),
10409 : : };
10410 : 0 : struct mlx5_rte_flow_item_sq queue_mask = {
10411 : : .queue = UINT32_MAX,
10412 : : };
10413 : 0 : struct rte_flow_item items[] = {
10414 : : {
10415 : : .type = (enum rte_flow_item_type)
10416 : : MLX5_RTE_FLOW_ITEM_TYPE_TAG,
10417 : : .spec = ®_c0_spec,
10418 : : .mask = ®_c0_mask,
10419 : : },
10420 : : {
10421 : : .type = (enum rte_flow_item_type)
10422 : : MLX5_RTE_FLOW_ITEM_TYPE_SQ,
10423 : : .mask = &queue_mask,
10424 : : },
10425 : : {
10426 : : .type = RTE_FLOW_ITEM_TYPE_END,
10427 : : },
10428 : : };
10429 : :
10430 : 0 : return flow_hw_pattern_template_create(dev, &attr, items, false, error);
10431 : : }
10432 : :
10433 : : /**
10434 : : * Creates a flow pattern template with unmasked represented port matching.
10435 : : * This template is used to set up a table for default transfer flows
10436 : : * directing packets to group 1.
10437 : : *
10438 : : * @param dev
10439 : : * Pointer to Ethernet device.
10440 : : * @param error
10441 : : * Pointer to error structure.
10442 : : *
10443 : : * @return
10444 : : * Pointer to flow pattern template on success, NULL otherwise.
10445 : : */
10446 : : static struct rte_flow_pattern_template *
10447 : 0 : flow_hw_create_ctrl_port_pattern_template(struct rte_eth_dev *dev,
10448 : : struct rte_flow_error *error)
10449 : : {
10450 : 0 : struct rte_flow_pattern_template_attr attr = {
10451 : : .relaxed_matching = 0,
10452 : : .transfer = 1,
10453 : : };
10454 : 0 : struct rte_flow_item_ethdev port_mask = {
10455 : : .port_id = UINT16_MAX,
10456 : : };
10457 : 0 : struct rte_flow_item items[] = {
10458 : : {
10459 : : .type = RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT,
10460 : : .mask = &port_mask,
10461 : : },
10462 : : {
10463 : : .type = RTE_FLOW_ITEM_TYPE_END,
10464 : : },
10465 : : };
10466 : :
10467 : 0 : return flow_hw_pattern_template_create(dev, &attr, items, false, error);
10468 : : }
10469 : :
10470 : : /*
10471 : : * Creating a flow pattern template with all LACP packets matching, only for NIC
10472 : : * ingress domain.
10473 : : *
10474 : : * @param dev
10475 : : * Pointer to Ethernet device.
10476 : : * @param error
10477 : : * Pointer to error structure.
10478 : : *
10479 : : * @return
10480 : : * Pointer to flow pattern template on success, NULL otherwise.
10481 : : */
10482 : : static struct rte_flow_pattern_template *
10483 : 0 : flow_hw_create_lacp_rx_pattern_template(struct rte_eth_dev *dev, struct rte_flow_error *error)
10484 : : {
10485 : 0 : struct rte_flow_pattern_template_attr pa_attr = {
10486 : : .relaxed_matching = 0,
10487 : : .ingress = 1,
10488 : : };
10489 : 0 : struct rte_flow_item_eth lacp_mask = {
10490 : : .dst.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
10491 : : .src.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
10492 : : .type = 0xFFFF,
10493 : : };
10494 : 0 : struct rte_flow_item eth_all[] = {
10495 : : [0] = {
10496 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
10497 : : .mask = &lacp_mask,
10498 : : },
10499 : : [1] = {
10500 : : .type = RTE_FLOW_ITEM_TYPE_END,
10501 : : },
10502 : : };
10503 : 0 : return flow_hw_pattern_template_create(dev, &pa_attr, eth_all,
10504 : : false, error);
10505 : : }
10506 : :
10507 : : /**
10508 : : * Creates a flow actions template with modify field action and masked jump action.
10509 : : * Modify field action sets the least significant bit of REG_C_0 (usable by user-space)
10510 : : * to 1, meaning that packet was originated from E-Switch Manager. Jump action
10511 : : * transfers steering to group 1.
10512 : : *
10513 : : * @param dev
10514 : : * Pointer to Ethernet device.
10515 : : * @param error
10516 : : * Pointer to error structure.
10517 : : *
10518 : : * @return
10519 : : * Pointer to flow actions template on success, NULL otherwise.
10520 : : */
10521 : : static struct rte_flow_actions_template *
10522 : 0 : flow_hw_create_ctrl_regc_jump_actions_template(struct rte_eth_dev *dev,
10523 : : struct rte_flow_error *error)
10524 : : {
10525 : : uint32_t marker_mask = flow_hw_esw_mgr_regc_marker_mask(dev);
10526 : : uint32_t marker_bits = flow_hw_esw_mgr_regc_marker(dev);
10527 : 0 : struct rte_flow_actions_template_attr attr = {
10528 : : .transfer = 1,
10529 : : };
10530 : 0 : struct rte_flow_action_modify_field set_reg_v = {
10531 : : .operation = RTE_FLOW_MODIFY_SET,
10532 : : .dst = {
10533 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
10534 : : .tag_index = REG_C_0,
10535 : : },
10536 : : .src = {
10537 : : .field = RTE_FLOW_FIELD_VALUE,
10538 : : },
10539 : : .width = rte_popcount32(marker_mask),
10540 : : };
10541 : 0 : struct rte_flow_action_modify_field set_reg_m = {
10542 : : .operation = RTE_FLOW_MODIFY_SET,
10543 : : .dst = {
10544 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
10545 : : .level = UINT8_MAX,
10546 : : .tag_index = UINT8_MAX,
10547 : : .offset = UINT32_MAX,
10548 : : },
10549 : : .src = {
10550 : : .field = RTE_FLOW_FIELD_VALUE,
10551 : : },
10552 : : .width = UINT32_MAX,
10553 : : };
10554 : 0 : struct rte_flow_action_jump jump_v = {
10555 : : .group = MLX5_HW_LOWEST_USABLE_GROUP,
10556 : : };
10557 : 0 : struct rte_flow_action_jump jump_m = {
10558 : : .group = UINT32_MAX,
10559 : : };
10560 : 0 : struct rte_flow_action actions_v[] = {
10561 : : {
10562 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
10563 : : .conf = &set_reg_v,
10564 : : },
10565 : : {
10566 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
10567 : : .conf = &jump_v,
10568 : : },
10569 : : {
10570 : : .type = RTE_FLOW_ACTION_TYPE_END,
10571 : : }
10572 : : };
10573 : 0 : struct rte_flow_action actions_m[] = {
10574 : : {
10575 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
10576 : : .conf = &set_reg_m,
10577 : : },
10578 : : {
10579 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
10580 : : .conf = &jump_m,
10581 : : },
10582 : : {
10583 : : .type = RTE_FLOW_ACTION_TYPE_END,
10584 : : }
10585 : : };
10586 : :
10587 : 0 : set_reg_v.dst.offset = rte_bsf32(marker_mask);
10588 : : rte_memcpy(set_reg_v.src.value, &marker_bits, sizeof(marker_bits));
10589 : : rte_memcpy(set_reg_m.src.value, &marker_mask, sizeof(marker_mask));
10590 : 0 : return flow_hw_actions_template_create(dev, &attr, actions_v, actions_m, error);
10591 : : }
10592 : :
10593 : : /**
10594 : : * Creates a flow actions template with an unmasked JUMP action. Flows
10595 : : * based on this template will perform a jump to some group. This template
10596 : : * is used to set up tables for control flows.
10597 : : *
10598 : : * @param dev
10599 : : * Pointer to Ethernet device.
10600 : : * @param group
10601 : : * Destination group for this action template.
10602 : : * @param error
10603 : : * Pointer to error structure.
10604 : : *
10605 : : * @return
10606 : : * Pointer to flow actions template on success, NULL otherwise.
10607 : : */
10608 : : static struct rte_flow_actions_template *
10609 : 0 : flow_hw_create_ctrl_jump_actions_template(struct rte_eth_dev *dev,
10610 : : uint32_t group,
10611 : : struct rte_flow_error *error)
10612 : : {
10613 : 0 : struct rte_flow_actions_template_attr attr = {
10614 : : .transfer = 1,
10615 : : };
10616 : 0 : struct rte_flow_action_jump jump_v = {
10617 : : .group = group,
10618 : : };
10619 : 0 : struct rte_flow_action_jump jump_m = {
10620 : : .group = UINT32_MAX,
10621 : : };
10622 : 0 : struct rte_flow_action actions_v[] = {
10623 : : {
10624 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
10625 : : .conf = &jump_v,
10626 : : },
10627 : : {
10628 : : .type = RTE_FLOW_ACTION_TYPE_END,
10629 : : }
10630 : : };
10631 : 0 : struct rte_flow_action actions_m[] = {
10632 : : {
10633 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
10634 : : .conf = &jump_m,
10635 : : },
10636 : : {
10637 : : .type = RTE_FLOW_ACTION_TYPE_END,
10638 : : }
10639 : : };
10640 : :
10641 : 0 : return flow_hw_actions_template_create(dev, &attr, actions_v,
10642 : : actions_m, error);
10643 : : }
10644 : :
10645 : : /**
10646 : : * Creates a flow action template with a unmasked REPRESENTED_PORT action.
10647 : : * It is used to create control flow tables.
10648 : : *
10649 : : * @param dev
10650 : : * Pointer to Ethernet device.
10651 : : * @param error
10652 : : * Pointer to error structure.
10653 : : *
10654 : : * @return
10655 : : * Pointer to flow action template on success, NULL otherwise.
10656 : : */
10657 : : static struct rte_flow_actions_template *
10658 : 0 : flow_hw_create_ctrl_port_actions_template(struct rte_eth_dev *dev,
10659 : : struct rte_flow_error *error)
10660 : : {
10661 : 0 : struct rte_flow_actions_template_attr attr = {
10662 : : .transfer = 1,
10663 : : };
10664 : 0 : struct rte_flow_action_ethdev port_v = {
10665 : : .port_id = 0,
10666 : : };
10667 : 0 : struct rte_flow_action actions_v[] = {
10668 : : {
10669 : : .type = RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT,
10670 : : .conf = &port_v,
10671 : : },
10672 : : {
10673 : : .type = RTE_FLOW_ACTION_TYPE_END,
10674 : : }
10675 : : };
10676 : 0 : struct rte_flow_action_ethdev port_m = {
10677 : : .port_id = 0,
10678 : : };
10679 : 0 : struct rte_flow_action actions_m[] = {
10680 : : {
10681 : : .type = RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT,
10682 : : .conf = &port_m,
10683 : : },
10684 : : {
10685 : : .type = RTE_FLOW_ACTION_TYPE_END,
10686 : : }
10687 : : };
10688 : :
10689 : 0 : return flow_hw_actions_template_create(dev, &attr, actions_v, actions_m, error);
10690 : : }
10691 : :
10692 : : /*
10693 : : * Creating an actions template to use header modify action for register
10694 : : * copying. This template is used to set up a table for copy flow.
10695 : : *
10696 : : * @param dev
10697 : : * Pointer to Ethernet device.
10698 : : * @param error
10699 : : * Pointer to error structure.
10700 : : *
10701 : : * @return
10702 : : * Pointer to flow actions template on success, NULL otherwise.
10703 : : */
10704 : : static struct rte_flow_actions_template *
10705 : 0 : flow_hw_create_tx_default_mreg_copy_actions_template(struct rte_eth_dev *dev,
10706 : : struct rte_flow_error *error)
10707 : : {
10708 : 0 : struct rte_flow_actions_template_attr tx_act_attr = {
10709 : : .egress = 1,
10710 : : };
10711 : 0 : const struct rte_flow_action_modify_field mreg_action = {
10712 : : .operation = RTE_FLOW_MODIFY_SET,
10713 : : .dst = {
10714 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
10715 : : .tag_index = REG_C_1,
10716 : : },
10717 : : .src = {
10718 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
10719 : : .tag_index = REG_A,
10720 : : },
10721 : : .width = 32,
10722 : : };
10723 : 0 : const struct rte_flow_action_modify_field mreg_mask = {
10724 : : .operation = RTE_FLOW_MODIFY_SET,
10725 : : .dst = {
10726 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
10727 : : .level = UINT8_MAX,
10728 : : .tag_index = UINT8_MAX,
10729 : : .offset = UINT32_MAX,
10730 : : },
10731 : : .src = {
10732 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
10733 : : .level = UINT8_MAX,
10734 : : .tag_index = UINT8_MAX,
10735 : : .offset = UINT32_MAX,
10736 : : },
10737 : : .width = UINT32_MAX,
10738 : : };
10739 : 0 : const struct rte_flow_action_jump jump_action = {
10740 : : .group = 1,
10741 : : };
10742 : 0 : const struct rte_flow_action_jump jump_mask = {
10743 : : .group = UINT32_MAX,
10744 : : };
10745 : 0 : const struct rte_flow_action actions[] = {
10746 : : [0] = {
10747 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
10748 : : .conf = &mreg_action,
10749 : : },
10750 : : [1] = {
10751 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
10752 : : .conf = &jump_action,
10753 : : },
10754 : : [2] = {
10755 : : .type = RTE_FLOW_ACTION_TYPE_END,
10756 : : },
10757 : : };
10758 : 0 : const struct rte_flow_action masks[] = {
10759 : : [0] = {
10760 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
10761 : : .conf = &mreg_mask,
10762 : : },
10763 : : [1] = {
10764 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
10765 : : .conf = &jump_mask,
10766 : : },
10767 : : [2] = {
10768 : : .type = RTE_FLOW_ACTION_TYPE_END,
10769 : : },
10770 : : };
10771 : :
10772 : 0 : return flow_hw_actions_template_create(dev, &tx_act_attr, actions,
10773 : : masks, error);
10774 : : }
10775 : :
10776 : : /*
10777 : : * Creating an actions template to use default miss to re-route packets to the
10778 : : * kernel driver stack.
10779 : : * On root table, only DEFAULT_MISS action can be used.
10780 : : *
10781 : : * @param dev
10782 : : * Pointer to Ethernet device.
10783 : : * @param error
10784 : : * Pointer to error structure.
10785 : : *
10786 : : * @return
10787 : : * Pointer to flow actions template on success, NULL otherwise.
10788 : : */
10789 : : static struct rte_flow_actions_template *
10790 : 0 : flow_hw_create_lacp_rx_actions_template(struct rte_eth_dev *dev, struct rte_flow_error *error)
10791 : : {
10792 : 0 : struct rte_flow_actions_template_attr act_attr = {
10793 : : .ingress = 1,
10794 : : };
10795 : 0 : const struct rte_flow_action actions[] = {
10796 : : [0] = {
10797 : : .type = (enum rte_flow_action_type)
10798 : : MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS,
10799 : : },
10800 : : [1] = {
10801 : : .type = RTE_FLOW_ACTION_TYPE_END,
10802 : : },
10803 : : };
10804 : :
10805 : 0 : return flow_hw_actions_template_create(dev, &act_attr, actions, actions, error);
10806 : : }
10807 : :
10808 : : /**
10809 : : * Creates a control flow table used to transfer traffic from E-Switch Manager
10810 : : * and TX queues from group 0 to group 1.
10811 : : *
10812 : : * @param dev
10813 : : * Pointer to Ethernet device.
10814 : : * @param it
10815 : : * Pointer to flow pattern template.
10816 : : * @param at
10817 : : * Pointer to flow actions template.
10818 : : * @param error
10819 : : * Pointer to error structure.
10820 : : *
10821 : : * @return
10822 : : * Pointer to flow table on success, NULL otherwise.
10823 : : */
10824 : : static struct rte_flow_template_table*
10825 : 0 : flow_hw_create_ctrl_sq_miss_root_table(struct rte_eth_dev *dev,
10826 : : struct rte_flow_pattern_template *it,
10827 : : struct rte_flow_actions_template *at,
10828 : : struct rte_flow_error *error)
10829 : : {
10830 : 0 : struct rte_flow_template_table_attr attr = {
10831 : : .flow_attr = {
10832 : : .group = 0,
10833 : : .priority = MLX5_HW_LOWEST_PRIO_ROOT,
10834 : : .ingress = 0,
10835 : : .egress = 0,
10836 : : .transfer = 1,
10837 : : },
10838 : : .nb_flows = MLX5_HW_CTRL_FLOW_NB_RULES,
10839 : : };
10840 : 0 : struct mlx5_flow_template_table_cfg cfg = {
10841 : : .attr = attr,
10842 : : .external = false,
10843 : : };
10844 : :
10845 : 0 : return flow_hw_table_create(dev, &cfg, &it, 1, &at, 1, error);
10846 : : }
10847 : :
10848 : :
10849 : : /**
10850 : : * Creates a control flow table used to transfer traffic from E-Switch Manager
10851 : : * and TX queues from group 0 to group 1.
10852 : : *
10853 : : * @param dev
10854 : : * Pointer to Ethernet device.
10855 : : * @param it
10856 : : * Pointer to flow pattern template.
10857 : : * @param at
10858 : : * Pointer to flow actions template.
10859 : : * @param error
10860 : : * Pointer to error structure.
10861 : : *
10862 : : * @return
10863 : : * Pointer to flow table on success, NULL otherwise.
10864 : : */
10865 : : static struct rte_flow_template_table*
10866 : 0 : flow_hw_create_ctrl_sq_miss_table(struct rte_eth_dev *dev,
10867 : : struct rte_flow_pattern_template *it,
10868 : : struct rte_flow_actions_template *at,
10869 : : struct rte_flow_error *error)
10870 : : {
10871 : 0 : struct rte_flow_template_table_attr attr = {
10872 : : .flow_attr = {
10873 : : .group = 1,
10874 : : .priority = MLX5_HW_LOWEST_PRIO_NON_ROOT,
10875 : : .ingress = 0,
10876 : : .egress = 0,
10877 : : .transfer = 1,
10878 : : },
10879 : : .nb_flows = MLX5_HW_CTRL_FLOW_NB_RULES,
10880 : : };
10881 : 0 : struct mlx5_flow_template_table_cfg cfg = {
10882 : : .attr = attr,
10883 : : .external = false,
10884 : : };
10885 : :
10886 : 0 : return flow_hw_table_create(dev, &cfg, &it, 1, &at, 1, error);
10887 : : }
10888 : :
10889 : : /*
10890 : : * Creating the default Tx metadata copy table on NIC Tx group 0.
10891 : : *
10892 : : * @param dev
10893 : : * Pointer to Ethernet device.
10894 : : * @param pt
10895 : : * Pointer to flow pattern template.
10896 : : * @param at
10897 : : * Pointer to flow actions template.
10898 : : * @param error
10899 : : * Pointer to error structure.
10900 : : *
10901 : : * @return
10902 : : * Pointer to flow table on success, NULL otherwise.
10903 : : */
10904 : : static struct rte_flow_template_table*
10905 : 0 : flow_hw_create_tx_default_mreg_copy_table(struct rte_eth_dev *dev,
10906 : : struct rte_flow_pattern_template *pt,
10907 : : struct rte_flow_actions_template *at,
10908 : : struct rte_flow_error *error)
10909 : : {
10910 : 0 : struct rte_flow_template_table_attr tx_tbl_attr = {
10911 : : .flow_attr = {
10912 : : .group = 0, /* Root */
10913 : : .priority = MLX5_HW_LOWEST_PRIO_ROOT,
10914 : : .egress = 1,
10915 : : },
10916 : : .nb_flows = MLX5_HW_CTRL_FLOW_NB_RULES,
10917 : : };
10918 : 0 : struct mlx5_flow_template_table_cfg tx_tbl_cfg = {
10919 : : .attr = tx_tbl_attr,
10920 : : .external = false,
10921 : : };
10922 : :
10923 : 0 : return flow_hw_table_create(dev, &tx_tbl_cfg, &pt, 1, &at, 1, error);
10924 : : }
10925 : :
10926 : : /**
10927 : : * Creates a control flow table used to transfer traffic
10928 : : * from group 0 to group 1.
10929 : : *
10930 : : * @param dev
10931 : : * Pointer to Ethernet device.
10932 : : * @param it
10933 : : * Pointer to flow pattern template.
10934 : : * @param at
10935 : : * Pointer to flow actions template.
10936 : : * @param error
10937 : : * Pointer to error structure.
10938 : : *
10939 : : * @return
10940 : : * Pointer to flow table on success, NULL otherwise.
10941 : : */
10942 : : static struct rte_flow_template_table *
10943 : 0 : flow_hw_create_ctrl_jump_table(struct rte_eth_dev *dev,
10944 : : struct rte_flow_pattern_template *it,
10945 : : struct rte_flow_actions_template *at,
10946 : : struct rte_flow_error *error)
10947 : : {
10948 : 0 : struct rte_flow_template_table_attr attr = {
10949 : : .flow_attr = {
10950 : : .group = 0,
10951 : : .priority = 0,
10952 : : .ingress = 0,
10953 : : .egress = 0,
10954 : : .transfer = 1,
10955 : : },
10956 : : .nb_flows = MLX5_HW_CTRL_FLOW_NB_RULES,
10957 : : };
10958 : 0 : struct mlx5_flow_template_table_cfg cfg = {
10959 : : .attr = attr,
10960 : : .external = false,
10961 : : };
10962 : :
10963 : 0 : return flow_hw_table_create(dev, &cfg, &it, 1, &at, 1, error);
10964 : : }
10965 : :
10966 : : /**
10967 : : * Cleans up all template tables and pattern, and actions templates used for
10968 : : * FDB control flow rules.
10969 : : *
10970 : : * @param dev
10971 : : * Pointer to Ethernet device.
10972 : : */
10973 : : static void
10974 : 0 : flow_hw_cleanup_ctrl_fdb_tables(struct rte_eth_dev *dev)
10975 : : {
10976 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
10977 : : struct mlx5_flow_hw_ctrl_fdb *hw_ctrl_fdb;
10978 : :
10979 [ # # ]: 0 : if (!priv->hw_ctrl_fdb)
10980 : : return;
10981 : : hw_ctrl_fdb = priv->hw_ctrl_fdb;
10982 : : /* Clean up templates used for default FDB jump rule. */
10983 [ # # ]: 0 : if (hw_ctrl_fdb->hw_esw_zero_tbl)
10984 : 0 : claim_zero(flow_hw_table_destroy(dev, hw_ctrl_fdb->hw_esw_zero_tbl, NULL));
10985 [ # # ]: 0 : if (hw_ctrl_fdb->jump_one_actions_tmpl)
10986 : 0 : claim_zero(flow_hw_actions_template_destroy(dev, hw_ctrl_fdb->jump_one_actions_tmpl,
10987 : : NULL));
10988 [ # # ]: 0 : if (hw_ctrl_fdb->port_items_tmpl)
10989 : 0 : claim_zero(flow_hw_pattern_template_destroy(dev, hw_ctrl_fdb->port_items_tmpl,
10990 : : NULL));
10991 : : /* Clean up templates used for default SQ miss flow rules - non-root table. */
10992 [ # # ]: 0 : if (hw_ctrl_fdb->hw_esw_sq_miss_tbl)
10993 : 0 : claim_zero(flow_hw_table_destroy(dev, hw_ctrl_fdb->hw_esw_sq_miss_tbl, NULL));
10994 [ # # ]: 0 : if (hw_ctrl_fdb->regc_sq_items_tmpl)
10995 : 0 : claim_zero(flow_hw_pattern_template_destroy(dev, hw_ctrl_fdb->regc_sq_items_tmpl,
10996 : : NULL));
10997 [ # # ]: 0 : if (hw_ctrl_fdb->port_actions_tmpl)
10998 : 0 : claim_zero(flow_hw_actions_template_destroy(dev, hw_ctrl_fdb->port_actions_tmpl,
10999 : : NULL));
11000 : : /* Clean up templates used for default SQ miss flow rules - root table. */
11001 [ # # ]: 0 : if (hw_ctrl_fdb->hw_esw_sq_miss_root_tbl)
11002 : 0 : claim_zero(flow_hw_table_destroy(dev, hw_ctrl_fdb->hw_esw_sq_miss_root_tbl, NULL));
11003 [ # # ]: 0 : if (hw_ctrl_fdb->regc_jump_actions_tmpl)
11004 : 0 : claim_zero(flow_hw_actions_template_destroy(dev,
11005 : : hw_ctrl_fdb->regc_jump_actions_tmpl, NULL));
11006 [ # # ]: 0 : if (hw_ctrl_fdb->esw_mgr_items_tmpl)
11007 : 0 : claim_zero(flow_hw_pattern_template_destroy(dev, hw_ctrl_fdb->esw_mgr_items_tmpl,
11008 : : NULL));
11009 : : /* Clean up templates structure for FDB control flow rules. */
11010 : 0 : mlx5_free(hw_ctrl_fdb);
11011 : 0 : priv->hw_ctrl_fdb = NULL;
11012 : : }
11013 : :
11014 : : /*
11015 : : * Create a table on the root group to for the LACP traffic redirecting.
11016 : : *
11017 : : * @param dev
11018 : : * Pointer to Ethernet device.
11019 : : * @param it
11020 : : * Pointer to flow pattern template.
11021 : : * @param at
11022 : : * Pointer to flow actions template.
11023 : : *
11024 : : * @return
11025 : : * Pointer to flow table on success, NULL otherwise.
11026 : : */
11027 : : static struct rte_flow_template_table *
11028 : 0 : flow_hw_create_lacp_rx_table(struct rte_eth_dev *dev,
11029 : : struct rte_flow_pattern_template *it,
11030 : : struct rte_flow_actions_template *at,
11031 : : struct rte_flow_error *error)
11032 : : {
11033 : 0 : struct rte_flow_template_table_attr attr = {
11034 : : .flow_attr = {
11035 : : .group = 0,
11036 : : .priority = 0,
11037 : : .ingress = 1,
11038 : : .egress = 0,
11039 : : .transfer = 0,
11040 : : },
11041 : : .nb_flows = 1,
11042 : : };
11043 : 0 : struct mlx5_flow_template_table_cfg cfg = {
11044 : : .attr = attr,
11045 : : .external = false,
11046 : : };
11047 : :
11048 : 0 : return flow_hw_table_create(dev, &cfg, &it, 1, &at, 1, error);
11049 : : }
11050 : :
11051 : : /*
11052 : : * Clean up templates and table used for redirecting LACP traffic to kernel.
11053 : : *
11054 : : * @param dev
11055 : : * Pointer to Ethernet device.
11056 : : */
11057 : : static void
11058 : 0 : flow_hw_cleanup_lacp_miss_tables(struct rte_eth_dev *dev)
11059 : : {
11060 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11061 : : struct mlx5_flow_hw_lacp_miss *hw_lacp_miss;
11062 : :
11063 [ # # ]: 0 : if (priv->hw_lacp_miss == NULL)
11064 : : return;
11065 : :
11066 : : hw_lacp_miss = priv->hw_lacp_miss;
11067 : :
11068 [ # # ]: 0 : if (hw_lacp_miss->hw_lacp_rx_tbl)
11069 : 0 : claim_zero(flow_hw_table_destroy(dev, hw_lacp_miss->hw_lacp_rx_tbl, NULL));
11070 [ # # ]: 0 : if (hw_lacp_miss->lacp_rx_actions_tmpl)
11071 : 0 : claim_zero(flow_hw_actions_template_destroy(dev,
11072 : : hw_lacp_miss->lacp_rx_actions_tmpl,
11073 : : NULL));
11074 [ # # ]: 0 : if (hw_lacp_miss->lacp_rx_items_tmpl)
11075 : 0 : claim_zero(flow_hw_pattern_template_destroy(dev,
11076 : : hw_lacp_miss->lacp_rx_items_tmpl,
11077 : : NULL));
11078 : :
11079 : 0 : mlx5_free(hw_lacp_miss);
11080 : 0 : priv->hw_lacp_miss = NULL;
11081 : : }
11082 : :
11083 : : /*
11084 : : * Create templates and table for redirecting LACP traffic to kernel.
11085 : : *
11086 : : * LACP traffic redirection is needed whenever LACP bond is managed by the kernel.
11087 : : * Required rule has a following structure:
11088 : : *
11089 : : * - ingress rule on root table
11090 : : * - match EtherType 0x8809
11091 : : * - action DEFAULT_MISS
11092 : : *
11093 : : * @param dev
11094 : : * Pointer to Ethernet device.
11095 : : *
11096 : : * @return
11097 : : * 0 on success. Negative errno otherwise.
11098 : : */
11099 : : static int
11100 : 0 : flow_hw_create_lacp_miss_tables(struct rte_eth_dev *dev)
11101 : : {
11102 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11103 : : struct mlx5_flow_hw_lacp_miss *hw_lacp_miss;
11104 : :
11105 [ # # ]: 0 : if (mlx5_flow_is_steering_disabled())
11106 : : return 0;
11107 : :
11108 : 0 : hw_lacp_miss = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*hw_lacp_miss), 0, SOCKET_ID_ANY);
11109 [ # # ]: 0 : if (!hw_lacp_miss) {
11110 : 0 : DRV_LOG(ERR, "port %u Failed to allocate memory for LACP miss tables",
11111 : : dev->data->port_id);
11112 : 0 : return -ENOMEM;
11113 : : }
11114 : 0 : priv->hw_lacp_miss = hw_lacp_miss;
11115 : :
11116 : 0 : hw_lacp_miss->lacp_rx_items_tmpl = flow_hw_create_lacp_rx_pattern_template(dev, NULL);
11117 [ # # ]: 0 : if (!hw_lacp_miss->lacp_rx_items_tmpl) {
11118 : 0 : DRV_LOG(ERR, "port %u Failed to create pattern template for LACP Rx traffic",
11119 : : dev->data->port_id);
11120 : 0 : goto error;
11121 : : }
11122 : 0 : hw_lacp_miss->lacp_rx_actions_tmpl = flow_hw_create_lacp_rx_actions_template(dev, NULL);
11123 [ # # ]: 0 : if (!hw_lacp_miss->lacp_rx_actions_tmpl) {
11124 : 0 : DRV_LOG(ERR, "port %u Failed to create actions template for LACP Rx traffic",
11125 : : dev->data->port_id);
11126 : 0 : goto error;
11127 : : }
11128 : 0 : hw_lacp_miss->hw_lacp_rx_tbl =
11129 : 0 : flow_hw_create_lacp_rx_table(dev, hw_lacp_miss->lacp_rx_items_tmpl,
11130 : : hw_lacp_miss->lacp_rx_actions_tmpl, NULL);
11131 [ # # ]: 0 : if (!hw_lacp_miss->hw_lacp_rx_tbl) {
11132 : 0 : DRV_LOG(ERR, "port %u Failed to create template table for LACP Rx traffic",
11133 : : dev->data->port_id);
11134 : 0 : goto error;
11135 : : }
11136 : :
11137 : : return 0;
11138 : :
11139 : 0 : error:
11140 : 0 : flow_hw_cleanup_lacp_miss_tables(dev);
11141 : 0 : return -EINVAL;
11142 : : }
11143 : :
11144 : : /**
11145 : : * Creates a set of flow tables used to create control flows used
11146 : : * when E-Switch is engaged.
11147 : : *
11148 : : * @param dev
11149 : : * Pointer to Ethernet device.
11150 : : * @param error
11151 : : * Pointer to error structure.
11152 : : *
11153 : : * @return
11154 : : * 0 on success, negative values otherwise
11155 : : */
11156 : : static int
11157 : 0 : flow_hw_create_fdb_ctrl_tables(struct rte_eth_dev *dev, struct rte_flow_error *error)
11158 : : {
11159 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11160 : : struct mlx5_flow_hw_ctrl_fdb *hw_ctrl_fdb;
11161 : 0 : uint32_t fdb_def_rule = priv->sh->config.fdb_def_rule;
11162 : :
11163 : : MLX5_ASSERT(priv->hw_ctrl_fdb == NULL);
11164 : 0 : hw_ctrl_fdb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*hw_ctrl_fdb), 0, SOCKET_ID_ANY);
11165 [ # # ]: 0 : if (!hw_ctrl_fdb) {
11166 : 0 : DRV_LOG(ERR, "port %u failed to allocate memory for FDB control flow templates",
11167 : : dev->data->port_id);
11168 : 0 : rte_errno = ENOMEM;
11169 : 0 : goto err;
11170 : : }
11171 : 0 : priv->hw_ctrl_fdb = hw_ctrl_fdb;
11172 [ # # ]: 0 : if (fdb_def_rule) {
11173 : : /* Create templates and table for default SQ miss flow rules - root table. */
11174 : 0 : hw_ctrl_fdb->esw_mgr_items_tmpl =
11175 : 0 : flow_hw_create_ctrl_esw_mgr_pattern_template(dev, error);
11176 [ # # ]: 0 : if (!hw_ctrl_fdb->esw_mgr_items_tmpl) {
11177 : 0 : DRV_LOG(ERR, "port %u failed to create E-Switch Manager item"
11178 : : " template for control flows", dev->data->port_id);
11179 : 0 : goto err;
11180 : : }
11181 : 0 : hw_ctrl_fdb->regc_jump_actions_tmpl =
11182 : 0 : flow_hw_create_ctrl_regc_jump_actions_template(dev, error);
11183 [ # # ]: 0 : if (!hw_ctrl_fdb->regc_jump_actions_tmpl) {
11184 : 0 : DRV_LOG(ERR, "port %u failed to create REG_C set and jump action template"
11185 : : " for control flows", dev->data->port_id);
11186 : 0 : goto err;
11187 : : }
11188 : 0 : hw_ctrl_fdb->hw_esw_sq_miss_root_tbl =
11189 : 0 : flow_hw_create_ctrl_sq_miss_root_table
11190 : : (dev, hw_ctrl_fdb->esw_mgr_items_tmpl,
11191 : : hw_ctrl_fdb->regc_jump_actions_tmpl, error);
11192 [ # # ]: 0 : if (!hw_ctrl_fdb->hw_esw_sq_miss_root_tbl) {
11193 : 0 : DRV_LOG(ERR, "port %u failed to create table for default sq miss (root table)"
11194 : : " for control flows", dev->data->port_id);
11195 : 0 : goto err;
11196 : : }
11197 : : /* Create templates and table for default SQ miss flow rules - non-root table. */
11198 : 0 : hw_ctrl_fdb->regc_sq_items_tmpl =
11199 : 0 : flow_hw_create_ctrl_regc_sq_pattern_template(dev, error);
11200 [ # # ]: 0 : if (!hw_ctrl_fdb->regc_sq_items_tmpl) {
11201 : 0 : DRV_LOG(ERR, "port %u failed to create SQ item template for"
11202 : : " control flows", dev->data->port_id);
11203 : 0 : goto err;
11204 : : }
11205 : 0 : hw_ctrl_fdb->port_actions_tmpl =
11206 : 0 : flow_hw_create_ctrl_port_actions_template(dev, error);
11207 [ # # ]: 0 : if (!hw_ctrl_fdb->port_actions_tmpl) {
11208 : 0 : DRV_LOG(ERR, "port %u failed to create port action template"
11209 : : " for control flows", dev->data->port_id);
11210 : 0 : goto err;
11211 : : }
11212 : 0 : hw_ctrl_fdb->hw_esw_sq_miss_tbl =
11213 : 0 : flow_hw_create_ctrl_sq_miss_table
11214 : : (dev, hw_ctrl_fdb->regc_sq_items_tmpl,
11215 : : hw_ctrl_fdb->port_actions_tmpl, error);
11216 [ # # ]: 0 : if (!hw_ctrl_fdb->hw_esw_sq_miss_tbl) {
11217 : 0 : DRV_LOG(ERR, "port %u failed to create table for default sq miss (non-root table)"
11218 : : " for control flows", dev->data->port_id);
11219 : 0 : goto err;
11220 : : }
11221 : : /* Create templates and table for default FDB jump flow rules. */
11222 : 0 : hw_ctrl_fdb->port_items_tmpl =
11223 : 0 : flow_hw_create_ctrl_port_pattern_template(dev, error);
11224 [ # # ]: 0 : if (!hw_ctrl_fdb->port_items_tmpl) {
11225 : 0 : DRV_LOG(ERR, "port %u failed to create SQ item template for"
11226 : : " control flows", dev->data->port_id);
11227 : 0 : goto err;
11228 : : }
11229 : 0 : hw_ctrl_fdb->jump_one_actions_tmpl =
11230 : 0 : flow_hw_create_ctrl_jump_actions_template
11231 : : (dev, MLX5_HW_LOWEST_USABLE_GROUP, error);
11232 [ # # ]: 0 : if (!hw_ctrl_fdb->jump_one_actions_tmpl) {
11233 : 0 : DRV_LOG(ERR, "port %u failed to create jump action template"
11234 : : " for control flows", dev->data->port_id);
11235 : 0 : goto err;
11236 : : }
11237 : 0 : hw_ctrl_fdb->hw_esw_zero_tbl = flow_hw_create_ctrl_jump_table
11238 : : (dev, hw_ctrl_fdb->port_items_tmpl,
11239 : : hw_ctrl_fdb->jump_one_actions_tmpl, error);
11240 [ # # ]: 0 : if (!hw_ctrl_fdb->hw_esw_zero_tbl) {
11241 : 0 : DRV_LOG(ERR, "port %u failed to create table for default jump to group 1"
11242 : : " for control flows", dev->data->port_id);
11243 : 0 : goto err;
11244 : : }
11245 : : }
11246 : : return 0;
11247 : :
11248 : 0 : err:
11249 : 0 : flow_hw_cleanup_ctrl_fdb_tables(dev);
11250 : 0 : return -EINVAL;
11251 : : }
11252 : :
11253 : : static void
11254 : 0 : flow_hw_cleanup_ctrl_nic_tables(struct rte_eth_dev *dev)
11255 : : {
11256 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11257 : 0 : struct mlx5_flow_hw_ctrl_nic *ctrl = priv->hw_ctrl_nic;
11258 : :
11259 [ # # ]: 0 : if (ctrl == NULL)
11260 : : return;
11261 [ # # ]: 0 : if (ctrl->hw_tx_meta_cpy_tbl)
11262 : 0 : claim_zero(flow_hw_table_destroy(dev, ctrl->hw_tx_meta_cpy_tbl, NULL));
11263 [ # # ]: 0 : if (ctrl->tx_meta_items_tmpl != NULL)
11264 : 0 : claim_zero(flow_hw_pattern_template_destroy(dev, ctrl->tx_meta_items_tmpl, NULL));
11265 [ # # ]: 0 : if (ctrl->tx_meta_actions_tmpl != NULL)
11266 : 0 : claim_zero(flow_hw_actions_template_destroy(dev, ctrl->tx_meta_actions_tmpl, NULL));
11267 : 0 : mlx5_free(ctrl);
11268 : 0 : priv->hw_ctrl_nic = NULL;
11269 : : }
11270 : :
11271 : : static int
11272 : 0 : flow_hw_create_nic_ctrl_tables(struct rte_eth_dev *dev, struct rte_flow_error *error)
11273 : : {
11274 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11275 : :
11276 : 0 : struct mlx5_flow_hw_ctrl_nic *ctrl = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ctrl),
11277 : : 0, SOCKET_ID_ANY);
11278 [ # # ]: 0 : if (!ctrl)
11279 : 0 : return rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11280 : : "failed to allocate port control flow table");
11281 : 0 : priv->hw_ctrl_nic = ctrl;
11282 : 0 : ctrl->tx_meta_items_tmpl = flow_hw_create_tx_repr_sq_pattern_tmpl(dev, error);
11283 [ # # ]: 0 : if (ctrl->tx_meta_items_tmpl == NULL)
11284 : 0 : goto error;
11285 : 0 : ctrl->tx_meta_actions_tmpl =
11286 : 0 : flow_hw_create_tx_default_mreg_copy_actions_template(dev, error);
11287 [ # # ]: 0 : if (ctrl->tx_meta_actions_tmpl == NULL) {
11288 : 0 : rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11289 : : "failed to create default Tx metadata copy actions template");
11290 : 0 : goto error;
11291 : : }
11292 : 0 : ctrl->hw_tx_meta_cpy_tbl =
11293 : 0 : flow_hw_create_tx_default_mreg_copy_table(dev, ctrl->tx_meta_items_tmpl,
11294 : : ctrl->tx_meta_actions_tmpl, error);
11295 [ # # ]: 0 : if (ctrl->hw_tx_meta_cpy_tbl == NULL) {
11296 : 0 : rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11297 : : "failed to create default Tx metadata copy table");
11298 : : }
11299 : : return 0;
11300 : :
11301 : 0 : error:
11302 : 0 : flow_hw_cleanup_ctrl_nic_tables(dev);
11303 : 0 : return -rte_errno;
11304 : : }
11305 : :
11306 : : static void
11307 : : flow_hw_ct_mng_destroy(struct mlx5_aso_ct_pools_mng *ct_mng)
11308 : : {
11309 : 0 : mlx5_aso_ct_queue_uninit(ct_mng);
11310 : 0 : mlx5_free(ct_mng);
11311 : : }
11312 : :
11313 : : static void
11314 : 0 : flow_hw_ct_pool_destroy(struct rte_eth_dev *dev,
11315 : : struct mlx5_aso_ct_pool *pool)
11316 : : {
11317 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11318 : :
11319 [ # # ]: 0 : if (pool->dr_action)
11320 : 0 : mlx5dr_action_destroy(pool->dr_action);
11321 [ # # ]: 0 : if (!priv->shared_host) {
11322 [ # # ]: 0 : if (pool->devx_obj)
11323 : 0 : claim_zero(mlx5_devx_cmd_destroy(pool->devx_obj));
11324 [ # # ]: 0 : if (pool->cts)
11325 : 0 : mlx5_ipool_destroy(pool->cts);
11326 : : }
11327 : 0 : mlx5_free(pool);
11328 : 0 : }
11329 : :
11330 : : static struct mlx5_aso_ct_pool *
11331 : 0 : flow_hw_ct_pool_create(struct rte_eth_dev *dev,
11332 : : uint32_t nb_conn_tracks)
11333 : : {
11334 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
11335 : : struct mlx5_aso_ct_pool *pool;
11336 : : struct mlx5_devx_obj *obj;
11337 : : uint32_t nb_cts = rte_align32pow2(nb_conn_tracks);
11338 : : uint32_t log_obj_size = rte_log2_u32(nb_cts);
11339 : 0 : struct mlx5_indexed_pool_config cfg = {
11340 : : .size = sizeof(struct mlx5_aso_ct_action),
11341 : : .trunk_size = 1 << 12,
11342 : : .per_core_cache = 1 << 13,
11343 : : .need_lock = 1,
11344 : 0 : .release_mem_en = !!priv->sh->config.reclaim_mode,
11345 : : .malloc = mlx5_malloc,
11346 : : .free = mlx5_free,
11347 : : .type = "mlx5_hw_ct_action",
11348 : : };
11349 : : int reg_id;
11350 : : uint32_t flags = 0;
11351 : :
11352 : 0 : pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
11353 [ # # ]: 0 : if (!pool) {
11354 : 0 : rte_errno = ENOMEM;
11355 : 0 : return NULL;
11356 : : }
11357 [ # # ]: 0 : if (!priv->shared_host) {
11358 : : /*
11359 : : * No need for local cache if CT number is a small number. Since
11360 : : * flow insertion rate will be very limited in that case. Here let's
11361 : : * set the number to less than default trunk size 4K.
11362 : : */
11363 [ # # ]: 0 : if (nb_cts <= cfg.trunk_size) {
11364 : 0 : cfg.per_core_cache = 0;
11365 : 0 : cfg.trunk_size = nb_cts;
11366 [ # # ]: 0 : } else if (nb_cts <= MLX5_HW_IPOOL_SIZE_THRESHOLD) {
11367 : 0 : cfg.per_core_cache = MLX5_HW_IPOOL_CACHE_MIN;
11368 : : }
11369 : 0 : cfg.max_idx = nb_cts;
11370 : 0 : pool->cts = mlx5_ipool_create(&cfg);
11371 [ # # ]: 0 : if (!pool->cts)
11372 : 0 : goto err;
11373 : 0 : obj = mlx5_devx_cmd_create_conn_track_offload_obj(priv->sh->cdev->ctx,
11374 : 0 : priv->sh->cdev->pdn,
11375 : : log_obj_size);
11376 [ # # ]: 0 : if (!obj) {
11377 : 0 : rte_errno = ENODATA;
11378 : 0 : DRV_LOG(ERR, "Failed to create conn_track_offload_obj using DevX.");
11379 : 0 : goto err;
11380 : : }
11381 : 0 : pool->devx_obj = obj;
11382 : : } else {
11383 : : struct rte_eth_dev *host_dev = priv->shared_host;
11384 : 0 : struct mlx5_priv *host_priv = host_dev->data->dev_private;
11385 : :
11386 : 0 : pool->devx_obj = host_priv->hws_ctpool->devx_obj;
11387 : 0 : pool->cts = host_priv->hws_ctpool->cts;
11388 : : MLX5_ASSERT(pool->cts);
11389 : : MLX5_ASSERT(!nb_conn_tracks);
11390 : : }
11391 : 0 : reg_id = mlx5_flow_get_reg_id(dev, MLX5_ASO_CONNTRACK, 0, NULL);
11392 : : flags |= MLX5DR_ACTION_FLAG_HWS_RX | MLX5DR_ACTION_FLAG_HWS_TX;
11393 [ # # # # ]: 0 : if (priv->sh->config.dv_esw_en && priv->master) {
11394 : 0 : flags |= ((is_unified_fdb(priv)) ?
11395 : : (MLX5DR_ACTION_FLAG_HWS_FDB_RX |
11396 : : MLX5DR_ACTION_FLAG_HWS_FDB_TX |
11397 [ # # ]: 0 : MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED) :
11398 : : MLX5DR_ACTION_FLAG_HWS_FDB);
11399 : : }
11400 : 0 : pool->dr_action = mlx5dr_action_create_aso_ct(priv->dr_ctx,
11401 : 0 : (struct mlx5dr_devx_obj *)pool->devx_obj,
11402 : 0 : reg_id - REG_C_0, flags);
11403 [ # # ]: 0 : if (!pool->dr_action)
11404 : 0 : goto err;
11405 : 0 : pool->sq = priv->ct_mng->aso_sqs;
11406 : : /* Assign the last extra ASO SQ as public SQ. */
11407 : 0 : pool->shared_sq = &priv->ct_mng->aso_sqs[priv->nb_queue - 1];
11408 : 0 : return pool;
11409 : 0 : err:
11410 : 0 : flow_hw_ct_pool_destroy(dev, pool);
11411 : 0 : return NULL;
11412 : : }
11413 : :
11414 : : static int
11415 : 0 : mlx5_flow_ct_init(struct rte_eth_dev *dev,
11416 : : uint32_t nb_conn_tracks,
11417 : : uint16_t nb_queue)
11418 : : {
11419 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11420 : : uint32_t mem_size;
11421 : : int ret = -ENOMEM;
11422 : :
11423 [ # # ]: 0 : if (!priv->shared_host) {
11424 : 0 : mem_size = sizeof(struct mlx5_aso_sq) * nb_queue +
11425 : : sizeof(*priv->ct_mng);
11426 : 0 : priv->ct_mng = mlx5_malloc(MLX5_MEM_ZERO, mem_size,
11427 : : RTE_CACHE_LINE_SIZE,
11428 : : SOCKET_ID_ANY);
11429 [ # # ]: 0 : if (!priv->ct_mng)
11430 : 0 : goto err;
11431 : 0 : ret = mlx5_aso_ct_queue_init(priv->sh, priv->ct_mng,
11432 : : nb_queue);
11433 [ # # ]: 0 : if (ret)
11434 : 0 : goto err;
11435 : : }
11436 : 0 : priv->hws_ctpool = flow_hw_ct_pool_create(dev, nb_conn_tracks);
11437 [ # # ]: 0 : if (!priv->hws_ctpool)
11438 : 0 : goto err;
11439 : 0 : priv->sh->ct_aso_en = 1;
11440 : 0 : return 0;
11441 : :
11442 : 0 : err:
11443 [ # # ]: 0 : if (priv->hws_ctpool) {
11444 : 0 : flow_hw_ct_pool_destroy(dev, priv->hws_ctpool);
11445 : 0 : priv->hws_ctpool = NULL;
11446 : : }
11447 [ # # ]: 0 : if (priv->ct_mng) {
11448 : : flow_hw_ct_mng_destroy(priv->ct_mng);
11449 : 0 : priv->ct_mng = NULL;
11450 : : }
11451 : : return ret;
11452 : : }
11453 : :
11454 : : void
11455 : 0 : mlx5_flow_hw_cleanup_ctrl_rx_tables(struct rte_eth_dev *dev)
11456 : : {
11457 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11458 : : unsigned int i;
11459 : : unsigned int j;
11460 : :
11461 [ # # ]: 0 : if (!priv->hw_ctrl_rx)
11462 : : return;
11463 [ # # ]: 0 : for (i = 0; i < MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_MAX; ++i) {
11464 [ # # ]: 0 : for (j = 0; j < MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX; ++j) {
11465 : 0 : struct rte_flow_template_table *tbl = priv->hw_ctrl_rx->tables[i][j].tbl;
11466 : 0 : struct rte_flow_pattern_template *pt = priv->hw_ctrl_rx->tables[i][j].pt;
11467 : :
11468 [ # # ]: 0 : if (tbl)
11469 : 0 : claim_zero(flow_hw_table_destroy(dev, tbl, NULL));
11470 [ # # ]: 0 : if (pt)
11471 : 0 : claim_zero(flow_hw_pattern_template_destroy(dev, pt, NULL));
11472 : : }
11473 : : }
11474 [ # # ]: 0 : for (i = 0; i < MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX; ++i) {
11475 : 0 : struct rte_flow_actions_template *at = priv->hw_ctrl_rx->rss[i];
11476 : :
11477 [ # # ]: 0 : if (at)
11478 : 0 : claim_zero(flow_hw_actions_template_destroy(dev, at, NULL));
11479 : : }
11480 : 0 : mlx5_free(priv->hw_ctrl_rx);
11481 : 0 : priv->hw_ctrl_rx = NULL;
11482 : : }
11483 : :
11484 : : static uint64_t
11485 : : flow_hw_ctrl_rx_rss_type_hash_types(const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
11486 : : {
11487 : : switch (rss_type) {
11488 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_NON_IP:
11489 : : return 0;
11490 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4:
11491 : : return RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_FRAG_IPV4 | RTE_ETH_RSS_NONFRAG_IPV4_OTHER;
11492 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_UDP:
11493 : : return RTE_ETH_RSS_NONFRAG_IPV4_UDP;
11494 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_TCP:
11495 : : return RTE_ETH_RSS_NONFRAG_IPV4_TCP;
11496 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6:
11497 : : return RTE_ETH_RSS_IPV6 | RTE_ETH_RSS_FRAG_IPV6 | RTE_ETH_RSS_NONFRAG_IPV6_OTHER;
11498 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_UDP:
11499 : : return RTE_ETH_RSS_NONFRAG_IPV6_UDP | RTE_ETH_RSS_IPV6_UDP_EX;
11500 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_TCP:
11501 : : return RTE_ETH_RSS_NONFRAG_IPV6_TCP | RTE_ETH_RSS_IPV6_TCP_EX;
11502 : : default:
11503 : : /* Should not reach here. */
11504 : : MLX5_ASSERT(false);
11505 : : return 0;
11506 : : }
11507 : : }
11508 : :
11509 : : static struct rte_flow_actions_template *
11510 : 0 : flow_hw_create_ctrl_rx_rss_template(struct rte_eth_dev *dev,
11511 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
11512 : : {
11513 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11514 : 0 : struct rte_flow_actions_template_attr attr = {
11515 : : .ingress = 1,
11516 : : };
11517 : : uint16_t queue[RTE_MAX_QUEUES_PER_PORT];
11518 : 0 : struct rte_flow_action_rss rss_conf = {
11519 : : .func = RTE_ETH_HASH_FUNCTION_DEFAULT,
11520 : : .level = 0,
11521 : : .types = 0,
11522 : 0 : .key_len = priv->rss_conf.rss_key_len,
11523 : 0 : .key = priv->rss_conf.rss_key,
11524 : 0 : .queue_num = priv->reta_idx_n,
11525 : : .queue = queue,
11526 : : };
11527 : 0 : struct rte_flow_action actions[] = {
11528 : : {
11529 : : .type = RTE_FLOW_ACTION_TYPE_RSS,
11530 : : .conf = &rss_conf,
11531 : : },
11532 : : {
11533 : : .type = RTE_FLOW_ACTION_TYPE_END,
11534 : : }
11535 : : };
11536 [ # # ]: 0 : struct rte_flow_action masks[] = {
11537 : : {
11538 : : .type = RTE_FLOW_ACTION_TYPE_RSS,
11539 : : .conf = &rss_conf,
11540 : : },
11541 : : {
11542 : : .type = RTE_FLOW_ACTION_TYPE_END,
11543 : : }
11544 : : };
11545 : : struct rte_flow_actions_template *at;
11546 : : struct rte_flow_error error;
11547 : : unsigned int i;
11548 : :
11549 : : MLX5_ASSERT(priv->reta_idx_n > 0 && priv->reta_idx);
11550 : : /* Select proper RSS hash types and based on that configure the actions template. */
11551 : 0 : rss_conf.types = flow_hw_ctrl_rx_rss_type_hash_types(rss_type);
11552 [ # # ]: 0 : if (rss_conf.types) {
11553 [ # # ]: 0 : for (i = 0; i < priv->reta_idx_n; ++i)
11554 : 0 : queue[i] = (*priv->reta_idx)[i];
11555 : : } else {
11556 : 0 : rss_conf.queue_num = 1;
11557 : 0 : queue[0] = (*priv->reta_idx)[0];
11558 : : }
11559 : : at = flow_hw_actions_template_create(dev, &attr, actions, masks, &error);
11560 [ # # ]: 0 : if (!at)
11561 [ # # ]: 0 : DRV_LOG(ERR,
11562 : : "Failed to create ctrl flow actions template: rte_errno(%d), type(%d): %s",
11563 : : rte_errno, error.type,
11564 : : error.message ? error.message : "(no stated reason)");
11565 : 0 : return at;
11566 : : }
11567 : :
11568 : : static uint32_t ctrl_rx_rss_priority_map[MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX] = {
11569 : : [MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_NON_IP] = MLX5_HW_CTRL_RX_PRIO_L2,
11570 : : [MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4] = MLX5_HW_CTRL_RX_PRIO_L3,
11571 : : [MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_UDP] = MLX5_HW_CTRL_RX_PRIO_L4,
11572 : : [MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_TCP] = MLX5_HW_CTRL_RX_PRIO_L4,
11573 : : [MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6] = MLX5_HW_CTRL_RX_PRIO_L3,
11574 : : [MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_UDP] = MLX5_HW_CTRL_RX_PRIO_L4,
11575 : : [MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_TCP] = MLX5_HW_CTRL_RX_PRIO_L4,
11576 : : };
11577 : :
11578 : : static uint32_t ctrl_rx_nb_flows_map[MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_MAX] = {
11579 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL] = 1,
11580 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL_MCAST] = 1,
11581 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST] = 1,
11582 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST_VLAN] = MLX5_MAX_VLAN_IDS,
11583 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST] = 1,
11584 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST_VLAN] = MLX5_MAX_VLAN_IDS,
11585 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST] = 1,
11586 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST_VLAN] = MLX5_MAX_VLAN_IDS,
11587 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC] = MLX5_MAX_UC_MAC_ADDRESSES,
11588 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN] =
11589 : : MLX5_MAX_UC_MAC_ADDRESSES * MLX5_MAX_VLAN_IDS,
11590 : : };
11591 : :
11592 : : static struct rte_flow_template_table_attr
11593 : : flow_hw_get_ctrl_rx_table_attr(enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type,
11594 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
11595 : : {
11596 : 0 : return (struct rte_flow_template_table_attr){
11597 : : .flow_attr = {
11598 : : .group = 0,
11599 : 0 : .priority = ctrl_rx_rss_priority_map[rss_type],
11600 : : .ingress = 1,
11601 : : },
11602 : 0 : .nb_flows = ctrl_rx_nb_flows_map[eth_pattern_type],
11603 : : };
11604 : : }
11605 : :
11606 : : static struct rte_flow_item
11607 : : flow_hw_get_ctrl_rx_eth_item(const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type)
11608 : : {
11609 : : struct rte_flow_item item = {
11610 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
11611 : : .mask = NULL,
11612 : : };
11613 : :
11614 : 0 : switch (eth_pattern_type) {
11615 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL:
11616 : : item.mask = &ctrl_rx_eth_promisc_mask;
11617 : : break;
11618 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL_MCAST:
11619 : : item.mask = &ctrl_rx_eth_mcast_mask;
11620 : 0 : break;
11621 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST:
11622 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST_VLAN:
11623 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC:
11624 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN:
11625 : : item.mask = &ctrl_rx_eth_dmac_mask;
11626 : 0 : break;
11627 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST:
11628 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST_VLAN:
11629 : : item.mask = &ctrl_rx_eth_ipv4_mcast_mask;
11630 : 0 : break;
11631 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST:
11632 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST_VLAN:
11633 : : item.mask = &ctrl_rx_eth_ipv6_mcast_mask;
11634 : 0 : break;
11635 : 0 : default:
11636 : : /* Should not reach here - ETH mask must be present. */
11637 : : item.type = RTE_FLOW_ITEM_TYPE_END;
11638 : : MLX5_ASSERT(false);
11639 : 0 : break;
11640 : : }
11641 : 0 : return item;
11642 : : }
11643 : :
11644 : : static struct rte_flow_item
11645 : : flow_hw_get_ctrl_rx_vlan_item(const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type)
11646 : : {
11647 : : struct rte_flow_item item = {
11648 : : .type = RTE_FLOW_ITEM_TYPE_VOID,
11649 : : .mask = NULL,
11650 : : };
11651 : :
11652 [ # # ]: 0 : switch (eth_pattern_type) {
11653 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST_VLAN:
11654 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST_VLAN:
11655 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST_VLAN:
11656 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN:
11657 : : item.type = RTE_FLOW_ITEM_TYPE_VLAN;
11658 : : item.mask = &rte_flow_item_vlan_mask;
11659 : 0 : break;
11660 : : default:
11661 : : /* Nothing to update. */
11662 : : break;
11663 : : }
11664 : 0 : return item;
11665 : : }
11666 : :
11667 : : static struct rte_flow_item
11668 : : flow_hw_get_ctrl_rx_l3_item(const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
11669 : : {
11670 : : struct rte_flow_item item = {
11671 : : .type = RTE_FLOW_ITEM_TYPE_VOID,
11672 : : .mask = NULL,
11673 : : };
11674 : :
11675 [ # # # ]: 0 : switch (rss_type) {
11676 : 0 : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4:
11677 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_UDP:
11678 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_TCP:
11679 : : item.type = RTE_FLOW_ITEM_TYPE_IPV4;
11680 : 0 : break;
11681 : 0 : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6:
11682 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_UDP:
11683 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_TCP:
11684 : : item.type = RTE_FLOW_ITEM_TYPE_IPV6;
11685 : 0 : break;
11686 : : default:
11687 : : /* Nothing to update. */
11688 : : break;
11689 : : }
11690 : 0 : return item;
11691 : : }
11692 : :
11693 : : static struct rte_flow_item
11694 : : flow_hw_get_ctrl_rx_l4_item(const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
11695 : : {
11696 : : struct rte_flow_item item = {
11697 : : .type = RTE_FLOW_ITEM_TYPE_VOID,
11698 : : .mask = NULL,
11699 : : };
11700 : :
11701 [ # # # ]: 0 : switch (rss_type) {
11702 : 0 : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_UDP:
11703 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_UDP:
11704 : : item.type = RTE_FLOW_ITEM_TYPE_UDP;
11705 : 0 : break;
11706 : 0 : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_TCP:
11707 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_TCP:
11708 : : item.type = RTE_FLOW_ITEM_TYPE_TCP;
11709 : 0 : break;
11710 : : default:
11711 : : /* Nothing to update. */
11712 : : break;
11713 : : }
11714 : 0 : return item;
11715 : : }
11716 : :
11717 : : static struct rte_flow_pattern_template *
11718 : 0 : flow_hw_create_ctrl_rx_pattern_template
11719 : : (struct rte_eth_dev *dev,
11720 : : const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type,
11721 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
11722 : : {
11723 : 0 : const struct rte_flow_pattern_template_attr attr = {
11724 : : .relaxed_matching = 0,
11725 : : .ingress = 1,
11726 : : };
11727 [ # # # # : 0 : struct rte_flow_item items[] = {
# # ]
11728 : : /* Matching patterns */
11729 : : flow_hw_get_ctrl_rx_eth_item(eth_pattern_type),
11730 : : flow_hw_get_ctrl_rx_vlan_item(eth_pattern_type),
11731 : : flow_hw_get_ctrl_rx_l3_item(rss_type),
11732 : : flow_hw_get_ctrl_rx_l4_item(rss_type),
11733 : : /* Terminate pattern */
11734 : : { .type = RTE_FLOW_ITEM_TYPE_END }
11735 : : };
11736 : :
11737 : 0 : return flow_hw_pattern_template_create(dev, &attr, items, false, NULL);
11738 : : }
11739 : :
11740 : : int
11741 : 0 : mlx5_flow_hw_create_ctrl_rx_tables(struct rte_eth_dev *dev)
11742 : : {
11743 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11744 : : unsigned int i;
11745 : : unsigned int j;
11746 : : int ret;
11747 : :
11748 : : MLX5_ASSERT(!priv->hw_ctrl_rx);
11749 : 0 : priv->hw_ctrl_rx = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*priv->hw_ctrl_rx),
11750 : : RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
11751 [ # # ]: 0 : if (!priv->hw_ctrl_rx) {
11752 : 0 : DRV_LOG(ERR, "Failed to allocate memory for Rx control flow tables");
11753 : 0 : rte_errno = ENOMEM;
11754 : 0 : return -rte_errno;
11755 : : }
11756 : : /* Create all pattern template variants. */
11757 [ # # ]: 0 : for (i = 0; i < MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_MAX; ++i) {
11758 : : enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type = i;
11759 : :
11760 [ # # ]: 0 : for (j = 0; j < MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX; ++j) {
11761 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type = j;
11762 : : struct rte_flow_template_table_attr attr;
11763 : : struct rte_flow_pattern_template *pt;
11764 : :
11765 : : attr = flow_hw_get_ctrl_rx_table_attr(eth_pattern_type, rss_type);
11766 : 0 : pt = flow_hw_create_ctrl_rx_pattern_template(dev, eth_pattern_type,
11767 : : rss_type);
11768 [ # # ]: 0 : if (!pt)
11769 : 0 : goto err;
11770 : 0 : priv->hw_ctrl_rx->tables[i][j].attr = attr;
11771 : 0 : priv->hw_ctrl_rx->tables[i][j].pt = pt;
11772 : : }
11773 : : }
11774 : : return 0;
11775 : : err:
11776 : 0 : ret = rte_errno;
11777 : 0 : return -ret;
11778 : : }
11779 : :
11780 : : void
11781 : 0 : mlx5_flow_hw_cleanup_ctrl_rx_templates(struct rte_eth_dev *dev)
11782 : : {
11783 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11784 : : struct mlx5_flow_hw_ctrl_rx *hw_ctrl_rx;
11785 : : unsigned int i;
11786 : : unsigned int j;
11787 : :
11788 [ # # ]: 0 : if (!priv->dr_ctx)
11789 : : return;
11790 [ # # ]: 0 : if (!priv->hw_ctrl_rx)
11791 : : return;
11792 : : hw_ctrl_rx = priv->hw_ctrl_rx;
11793 [ # # ]: 0 : for (i = 0; i < MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_MAX; ++i) {
11794 [ # # ]: 0 : for (j = 0; j < MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX; ++j) {
11795 : : struct mlx5_flow_hw_ctrl_rx_table *tmpls = &hw_ctrl_rx->tables[i][j];
11796 : :
11797 [ # # ]: 0 : if (tmpls->tbl) {
11798 : 0 : claim_zero(flow_hw_table_destroy(dev, tmpls->tbl, NULL));
11799 : 0 : tmpls->tbl = NULL;
11800 : : }
11801 : : }
11802 : : }
11803 [ # # ]: 0 : for (j = 0; j < MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX; ++j) {
11804 [ # # ]: 0 : if (hw_ctrl_rx->rss[j]) {
11805 : 0 : claim_zero(flow_hw_actions_template_destroy(dev, hw_ctrl_rx->rss[j], NULL));
11806 : 0 : hw_ctrl_rx->rss[j] = NULL;
11807 : : }
11808 : : }
11809 : : }
11810 : :
11811 : : /**
11812 : : * Copy the provided HWS configuration to a newly allocated buffer.
11813 : : *
11814 : : * @param[in] port_attr
11815 : : * Port configuration attributes.
11816 : : * @param[in] nb_queue
11817 : : * Number of queue.
11818 : : * @param[in] queue_attr
11819 : : * Array that holds attributes for each flow queue.
11820 : : * @param[in] nt_mode
11821 : : * Non template mode.
11822 : : *
11823 : : * @return
11824 : : * Pointer to copied HWS configuration is returned on success.
11825 : : * Otherwise, NULL is returned and rte_errno is set.
11826 : : */
11827 : : static struct mlx5_flow_hw_attr *
11828 : 0 : flow_hw_alloc_copy_config(const struct rte_flow_port_attr *port_attr,
11829 : : const uint16_t nb_queue,
11830 : : const struct rte_flow_queue_attr *queue_attr[],
11831 : : bool nt_mode,
11832 : : struct rte_flow_error *error)
11833 : : {
11834 : : struct mlx5_flow_hw_attr *hw_attr;
11835 : : size_t hw_attr_size;
11836 : : unsigned int i;
11837 : :
11838 : 0 : hw_attr_size = sizeof(*hw_attr) + nb_queue * sizeof(*hw_attr->queue_attr);
11839 : 0 : hw_attr = mlx5_malloc(MLX5_MEM_ZERO, hw_attr_size, 0, SOCKET_ID_ANY);
11840 [ # # ]: 0 : if (!hw_attr) {
11841 : 0 : rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11842 : : "Not enough memory to store configuration");
11843 : 0 : return NULL;
11844 : : }
11845 : 0 : memcpy(&hw_attr->port_attr, port_attr, sizeof(*port_attr));
11846 : 0 : hw_attr->nb_queue = nb_queue;
11847 : : /* Queue attributes are placed after the mlx5_flow_hw_attr. */
11848 : 0 : hw_attr->queue_attr = (struct rte_flow_queue_attr *)(hw_attr + 1);
11849 [ # # ]: 0 : for (i = 0; i < nb_queue; ++i)
11850 : 0 : memcpy(&hw_attr->queue_attr[i], queue_attr[i], sizeof(hw_attr->queue_attr[i]));
11851 : 0 : hw_attr->nt_mode = nt_mode;
11852 : 0 : return hw_attr;
11853 : : }
11854 : :
11855 : : /**
11856 : : * Compares the preserved HWS configuration with the provided one.
11857 : : *
11858 : : * @param[in] hw_attr
11859 : : * Pointer to preserved HWS configuration.
11860 : : * @param[in] new_pa
11861 : : * Port configuration attributes to compare.
11862 : : * @param[in] new_nbq
11863 : : * Number of queues to compare.
11864 : : * @param[in] new_qa
11865 : : * Array that holds attributes for each flow queue.
11866 : : *
11867 : : * @return
11868 : : * True if configurations are the same, false otherwise.
11869 : : */
11870 : : static bool
11871 : 0 : flow_hw_compare_config(const struct mlx5_flow_hw_attr *hw_attr,
11872 : : const struct rte_flow_port_attr *new_pa,
11873 : : const uint16_t new_nbq,
11874 : : const struct rte_flow_queue_attr *new_qa[])
11875 : : {
11876 : : const struct rte_flow_port_attr *old_pa = &hw_attr->port_attr;
11877 : 0 : const uint16_t old_nbq = hw_attr->nb_queue;
11878 : 0 : const struct rte_flow_queue_attr *old_qa = hw_attr->queue_attr;
11879 : : unsigned int i;
11880 : :
11881 [ # # ]: 0 : if (old_pa->nb_counters != new_pa->nb_counters ||
11882 [ # # ]: 0 : old_pa->nb_aging_objects != new_pa->nb_aging_objects ||
11883 [ # # ]: 0 : old_pa->nb_meters != new_pa->nb_meters ||
11884 [ # # ]: 0 : old_pa->nb_conn_tracks != new_pa->nb_conn_tracks ||
11885 [ # # ]: 0 : old_pa->flags != new_pa->flags)
11886 : : return false;
11887 [ # # ]: 0 : if (old_nbq != new_nbq)
11888 : : return false;
11889 [ # # ]: 0 : for (i = 0; i < old_nbq; ++i)
11890 [ # # ]: 0 : if (old_qa[i].size != new_qa[i]->size)
11891 : : return false;
11892 : : return true;
11893 : : }
11894 : :
11895 : : /*
11896 : : * No need to explicitly release drop action templates on port stop.
11897 : : * Drop action templates release with other action templates during
11898 : : * mlx5_dev_close -> flow_hw_resource_release -> flow_hw_actions_template_destroy
11899 : : */
11900 : : static void
11901 : 0 : flow_hw_action_template_drop_release(struct rte_eth_dev *dev)
11902 : : {
11903 : : int i;
11904 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11905 : :
11906 [ # # ]: 0 : for (i = 0; i < MLX5DR_TABLE_TYPE_MAX; i++) {
11907 [ # # ]: 0 : if (!priv->action_template_drop[i])
11908 : 0 : continue;
11909 : 0 : flow_hw_actions_template_destroy(dev,
11910 : : priv->action_template_drop[i],
11911 : : NULL);
11912 : 0 : priv->action_template_drop[i] = NULL;
11913 : : }
11914 : 0 : }
11915 : :
11916 : : static int
11917 : 0 : flow_hw_action_template_drop_init(struct rte_eth_dev *dev,
11918 : : struct rte_flow_error *error)
11919 : : {
11920 : : uint32_t i, from, to;
11921 : 0 : const struct rte_flow_action drop[2] = {
11922 : : [0] = { .type = RTE_FLOW_ACTION_TYPE_DROP },
11923 : : [1] = { .type = RTE_FLOW_ACTION_TYPE_END },
11924 : : };
11925 : : const struct rte_flow_action *actions = drop;
11926 : : const struct rte_flow_action *masks = drop;
11927 : 0 : const struct rte_flow_actions_template_attr attr[MLX5DR_TABLE_TYPE_MAX] = {
11928 : : [MLX5DR_TABLE_TYPE_NIC_RX] = { .ingress = 1 },
11929 : : [MLX5DR_TABLE_TYPE_NIC_TX] = { .egress = 1 },
11930 : : [MLX5DR_TABLE_TYPE_FDB] = { .transfer = 1 },
11931 : : [MLX5DR_TABLE_TYPE_FDB_RX] = { .transfer = 1 },
11932 : : [MLX5DR_TABLE_TYPE_FDB_TX] = { .transfer = 1 },
11933 : : [MLX5DR_TABLE_TYPE_FDB_UNIFIED] = { .transfer = 1 },
11934 : : };
11935 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11936 : :
11937 : : from = MLX5DR_TABLE_TYPE_NIC_RX;
11938 : : to = MLX5DR_TABLE_TYPE_NIC_TX;
11939 [ # # ]: 0 : for (i = from; i <= to; i++) {
11940 : 0 : priv->action_template_drop[i] =
11941 : 0 : flow_hw_actions_template_create(dev, &attr[i], actions, masks, error);
11942 [ # # ]: 0 : if (!priv->action_template_drop[i])
11943 : : return -1;
11944 : : }
11945 : :
11946 [ # # # # ]: 0 : if (!(priv->sh->config.dv_esw_en && priv->master))
11947 : : return 0;
11948 : :
11949 : : from = MLX5DR_TABLE_TYPE_FDB;
11950 [ # # ]: 0 : to = is_unified_fdb(priv) ? MLX5DR_TABLE_TYPE_FDB_UNIFIED : MLX5DR_TABLE_TYPE_FDB;
11951 [ # # ]: 0 : for (i = from; i <= to; i++) {
11952 : 0 : priv->action_template_drop[i] =
11953 : 0 : flow_hw_actions_template_create(dev, &attr[i], actions, masks, error);
11954 [ # # ]: 0 : if (!priv->action_template_drop[i])
11955 : : return -1;
11956 : : }
11957 : : return 0;
11958 : : }
11959 : :
11960 : : static void
11961 : 0 : __mlx5_flow_hw_resource_release(struct rte_eth_dev *dev, bool ctx_close)
11962 : : {
11963 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11964 : : struct rte_flow_template_table *tbl, *temp_tbl;
11965 : : struct rte_flow_pattern_template *it, *temp_it;
11966 : : struct rte_flow_actions_template *at, *temp_at;
11967 : : struct mlx5_flow_group *grp, *temp_grp;
11968 : : uint32_t i;
11969 : :
11970 : 0 : mlx5_flow_hw_rxq_flag_set(dev, false);
11971 : 0 : flow_hw_flush_all_ctrl_flows(dev);
11972 : 0 : flow_hw_cleanup_lacp_miss_tables(dev);
11973 : 0 : flow_hw_cleanup_ctrl_fdb_tables(dev);
11974 : 0 : flow_hw_cleanup_ctrl_nic_tables(dev);
11975 : 0 : flow_hw_cleanup_tx_repr_tagging(dev);
11976 : 0 : flow_hw_action_template_drop_release(dev);
11977 : 0 : grp = LIST_FIRST(&priv->flow_hw_grp);
11978 [ # # ]: 0 : while (grp) {
11979 : 0 : temp_grp = LIST_NEXT(grp, next);
11980 : 0 : claim_zero(flow_hw_group_unset_miss_group(dev, grp, NULL));
11981 : : grp = temp_grp;
11982 : : }
11983 : 0 : tbl = LIST_FIRST(&priv->flow_hw_tbl_ongo);
11984 [ # # ]: 0 : while (tbl) {
11985 : 0 : temp_tbl = LIST_NEXT(tbl, next);
11986 : 0 : claim_zero(flow_hw_table_destroy(dev, tbl, NULL));
11987 : : tbl = temp_tbl;
11988 : : }
11989 : 0 : tbl = LIST_FIRST(&priv->flow_hw_tbl);
11990 [ # # ]: 0 : while (tbl) {
11991 : 0 : temp_tbl = LIST_NEXT(tbl, next);
11992 : 0 : claim_zero(flow_hw_table_destroy(dev, tbl, NULL));
11993 : : tbl = temp_tbl;
11994 : : }
11995 : 0 : it = LIST_FIRST(&priv->flow_hw_itt);
11996 [ # # ]: 0 : while (it) {
11997 : 0 : temp_it = LIST_NEXT(it, next);
11998 : 0 : claim_zero(flow_hw_pattern_template_destroy(dev, it, NULL));
11999 : : it = temp_it;
12000 : : }
12001 : 0 : at = LIST_FIRST(&priv->flow_hw_at);
12002 [ # # ]: 0 : while (at) {
12003 : 0 : temp_at = LIST_NEXT(at, next);
12004 : 0 : claim_zero(flow_hw_actions_template_destroy(dev, at, NULL));
12005 : : at = temp_at;
12006 : : }
12007 : 0 : flow_hw_free_vport_actions(priv);
12008 [ # # ]: 0 : if (priv->acts_ipool) {
12009 : 0 : mlx5_ipool_destroy(priv->acts_ipool);
12010 : 0 : priv->acts_ipool = NULL;
12011 : : }
12012 [ # # ]: 0 : if (priv->hws_age_req)
12013 : 0 : mlx5_hws_age_pool_destroy(priv);
12014 [ # # # # ]: 0 : if (!priv->shared_host && priv->hws_cpool) {
12015 : 0 : mlx5_hws_cnt_pool_destroy(priv->sh, priv->hws_cpool);
12016 : 0 : priv->hws_cpool = NULL;
12017 : : }
12018 [ # # ]: 0 : if (priv->hws_ctpool) {
12019 : 0 : flow_hw_ct_pool_destroy(dev, priv->hws_ctpool);
12020 : 0 : priv->hws_ctpool = NULL;
12021 : : }
12022 [ # # ]: 0 : if (priv->ct_mng) {
12023 : : flow_hw_ct_mng_destroy(priv->ct_mng);
12024 : 0 : priv->ct_mng = NULL;
12025 : : }
12026 : 0 : mlx5_flow_quota_destroy(dev);
12027 : 0 : mlx5_hws_global_actions_cleanup(priv);
12028 [ # # ]: 0 : if (priv->hw_q) {
12029 [ # # ]: 0 : for (i = 0; i < priv->nb_queue; i++) {
12030 : 0 : struct mlx5_hw_q *hwq = &priv->hw_q[i];
12031 : 0 : rte_ring_free(hwq->indir_iq);
12032 : 0 : rte_ring_free(hwq->indir_cq);
12033 : 0 : rte_ring_free(hwq->flow_transfer_pending);
12034 : 0 : rte_ring_free(hwq->flow_transfer_completed);
12035 : : }
12036 : 0 : mlx5_free(priv->hw_q);
12037 : 0 : priv->hw_q = NULL;
12038 : : }
12039 [ # # ]: 0 : if (ctx_close) {
12040 [ # # ]: 0 : if (priv->dr_ctx) {
12041 : 0 : claim_zero(mlx5dr_context_close(priv->dr_ctx));
12042 : 0 : priv->dr_ctx = NULL;
12043 : : }
12044 : : }
12045 [ # # ]: 0 : if (priv->shared_host) {
12046 : 0 : struct mlx5_priv *host_priv = priv->shared_host->data->dev_private;
12047 : 0 : rte_atomic_fetch_sub_explicit(&host_priv->shared_refcnt, 1,
12048 : : rte_memory_order_relaxed);
12049 : 0 : priv->shared_host = NULL;
12050 : : }
12051 [ # # ]: 0 : if (priv->hw_attr) {
12052 : 0 : mlx5_free(priv->hw_attr);
12053 : 0 : priv->hw_attr = NULL;
12054 : : }
12055 : 0 : priv->nb_queue = 0;
12056 : 0 : }
12057 : :
12058 : : static __rte_always_inline struct rte_ring *
12059 : : mlx5_hwq_ring_create(uint16_t port_id, uint32_t queue, uint32_t size, const char *str)
12060 : : {
12061 : : char mz_name[RTE_MEMZONE_NAMESIZE];
12062 : :
12063 : : snprintf(mz_name, sizeof(mz_name), "port_%u_%s_%u", port_id, str, queue);
12064 : 0 : return rte_ring_create(mz_name, size, SOCKET_ID_ANY,
12065 : : RING_F_SP_ENQ | RING_F_SC_DEQ | RING_F_EXACT_SZ);
12066 : : }
12067 : :
12068 : : static int
12069 : 0 : flow_hw_queue_setup_rings(struct rte_eth_dev *dev,
12070 : : uint16_t queue,
12071 : : uint32_t queue_size,
12072 : : bool nt_mode)
12073 : : {
12074 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12075 : :
12076 : : /* HWS queue info container must be already allocated. */
12077 : : MLX5_ASSERT(priv->hw_q != NULL);
12078 : :
12079 : : /* Notice ring name length is limited. */
12080 : 0 : priv->hw_q[queue].indir_cq = mlx5_hwq_ring_create
12081 : 0 : (dev->data->port_id, queue, queue_size, "indir_act_cq");
12082 [ # # ]: 0 : if (!priv->hw_q[queue].indir_cq) {
12083 : 0 : DRV_LOG(ERR, "port %u failed to allocate indir_act_cq ring for HWS",
12084 : : dev->data->port_id);
12085 : 0 : return -ENOMEM;
12086 : : }
12087 : :
12088 : 0 : priv->hw_q[queue].indir_iq = mlx5_hwq_ring_create
12089 : 0 : (dev->data->port_id, queue, queue_size, "indir_act_iq");
12090 [ # # ]: 0 : if (!priv->hw_q[queue].indir_iq) {
12091 : 0 : DRV_LOG(ERR, "port %u failed to allocate indir_act_iq ring for HWS",
12092 : : dev->data->port_id);
12093 : 0 : return -ENOMEM;
12094 : : }
12095 : :
12096 : : /*
12097 : : * Sync flow API does not require rings used for table resize handling,
12098 : : * because these rings are only used through async flow APIs.
12099 : : */
12100 [ # # ]: 0 : if (nt_mode)
12101 : : return 0;
12102 : :
12103 : 0 : priv->hw_q[queue].flow_transfer_pending = mlx5_hwq_ring_create
12104 : 0 : (dev->data->port_id, queue, queue_size, "tx_pending");
12105 [ # # ]: 0 : if (!priv->hw_q[queue].flow_transfer_pending) {
12106 : 0 : DRV_LOG(ERR, "port %u failed to allocate tx_pending ring for HWS",
12107 : : dev->data->port_id);
12108 : 0 : return -ENOMEM;
12109 : : }
12110 : :
12111 : 0 : priv->hw_q[queue].flow_transfer_completed = mlx5_hwq_ring_create
12112 : 0 : (dev->data->port_id, queue, queue_size, "tx_done");
12113 [ # # ]: 0 : if (!priv->hw_q[queue].flow_transfer_completed) {
12114 : 0 : DRV_LOG(ERR, "port %u failed to allocate tx_done ring for HWS",
12115 : : dev->data->port_id);
12116 : 0 : return -ENOMEM;
12117 : : }
12118 : :
12119 : : return 0;
12120 : : }
12121 : :
12122 : : static int
12123 : 0 : flow_hw_validate_attributes(const struct rte_flow_port_attr *port_attr,
12124 : : uint16_t nb_queue,
12125 : : const struct rte_flow_queue_attr *queue_attr[],
12126 : : bool nt_mode, struct rte_flow_error *error)
12127 : : {
12128 : : uint32_t size;
12129 : : unsigned int i;
12130 : :
12131 [ # # ]: 0 : if (port_attr == NULL)
12132 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12133 : : "Port attributes must be non-NULL");
12134 : :
12135 [ # # ]: 0 : if (nb_queue == 0 && !nt_mode)
12136 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12137 : : "At least one flow queue is required");
12138 : :
12139 [ # # ]: 0 : if (queue_attr == NULL)
12140 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12141 : : "Queue attributes must be non-NULL");
12142 : :
12143 : 0 : size = queue_attr[0]->size;
12144 [ # # ]: 0 : for (i = 1; i < nb_queue; ++i) {
12145 [ # # ]: 0 : if (queue_attr[i]->size != size)
12146 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12147 : : NULL,
12148 : : "All flow queues must have the same size");
12149 : : }
12150 : :
12151 : : return 0;
12152 : : }
12153 : :
12154 : : /**
12155 : : * Configure port HWS resources.
12156 : : *
12157 : : * @param[in] dev
12158 : : * Pointer to the rte_eth_dev structure.
12159 : : * @param[in] port_attr
12160 : : * Port configuration attributes.
12161 : : * @param[in] nb_queue
12162 : : * Number of queue.
12163 : : * @param[in] queue_attr
12164 : : * Array that holds attributes for each flow queue.
12165 : : * @param[in] nt_mode
12166 : : * Non-template mode.
12167 : : * @param[out] error
12168 : : * Pointer to error structure.
12169 : : *
12170 : : * @return
12171 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
12172 : : */
12173 : : static int
12174 : 0 : __flow_hw_configure(struct rte_eth_dev *dev,
12175 : : const struct rte_flow_port_attr *port_attr,
12176 : : uint16_t nb_queue,
12177 : : const struct rte_flow_queue_attr *queue_attr[],
12178 : : bool nt_mode,
12179 : : struct rte_flow_error *error)
12180 : : {
12181 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12182 : : struct mlx5_priv *host_priv = NULL;
12183 : 0 : struct mlx5dr_context_attr dr_ctx_attr = {0};
12184 : : struct mlx5_hw_q *hw_q;
12185 : : struct mlx5_hw_q_job *job = NULL;
12186 : : uint32_t mem_size, i, j;
12187 : 0 : struct mlx5_indexed_pool_config cfg = {
12188 : : .size = sizeof(struct mlx5_action_construct_data),
12189 : : .trunk_size = 4096,
12190 : : .need_lock = 1,
12191 : 0 : .release_mem_en = !!priv->sh->config.reclaim_mode,
12192 : : .malloc = mlx5_malloc,
12193 : : .free = mlx5_free,
12194 : : .type = "mlx5_hw_action_construct_data",
12195 : : };
12196 : : /*
12197 : : * Adds one queue to be used by PMD.
12198 : : * The last queue will be used by the PMD.
12199 : : */
12200 : : uint16_t nb_q_updated = 0;
12201 : : struct rte_flow_queue_attr **_queue_attr = NULL;
12202 : 0 : struct rte_flow_queue_attr ctrl_queue_attr = {0};
12203 [ # # # # ]: 0 : bool is_proxy = !!(priv->sh->config.dv_esw_en && priv->master);
12204 : : int ret = 0;
12205 : : bool strict_queue = false;
12206 : :
12207 : 0 : error->type = RTE_FLOW_ERROR_TYPE_NONE;
12208 [ # # ]: 0 : if (mlx5dr_rule_get_handle_size() != MLX5_DR_RULE_SIZE) {
12209 : 0 : rte_errno = EINVAL;
12210 : 0 : goto err;
12211 : : }
12212 [ # # ]: 0 : if (flow_hw_validate_attributes(port_attr, nb_queue, queue_attr, nt_mode, error))
12213 : 0 : return -rte_errno;
12214 : : /*
12215 : : * Calling rte_flow_configure() again is allowed if
12216 : : * provided configuration matches the initially provided one,
12217 : : * or previous configuration was default non template one.
12218 : : */
12219 [ # # ]: 0 : if (priv->dr_ctx) {
12220 : : MLX5_ASSERT(priv->hw_attr != NULL);
12221 [ # # ]: 0 : for (i = 0; i < priv->nb_queue; i++) {
12222 : 0 : hw_q = &priv->hw_q[i];
12223 : : /* Make sure all queues are empty. */
12224 [ # # ]: 0 : if (hw_q->size != hw_q->job_idx) {
12225 : 0 : rte_errno = EBUSY;
12226 : 0 : goto err;
12227 : : }
12228 : : }
12229 : : /* If previous configuration was not default non template mode config. */
12230 [ # # ]: 0 : if (!priv->hw_attr->nt_mode) {
12231 [ # # ]: 0 : if (flow_hw_compare_config(priv->hw_attr, port_attr, nb_queue, queue_attr))
12232 : : return 0;
12233 : : else
12234 : 0 : return rte_flow_error_set(error, ENOTSUP,
12235 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12236 : : "Changing HWS configuration attributes "
12237 : : "is not supported");
12238 : : }
12239 : : /* Reconfiguration, need to release all resources from previous allocation. */
12240 : 0 : __mlx5_flow_hw_resource_release(dev, true);
12241 : : }
12242 : 0 : priv->hw_attr = flow_hw_alloc_copy_config(port_attr, nb_queue, queue_attr, nt_mode, error);
12243 [ # # ]: 0 : if (!priv->hw_attr) {
12244 : 0 : ret = -rte_errno;
12245 : 0 : goto err;
12246 : : }
12247 : 0 : ctrl_queue_attr.size = queue_attr[0]->size;
12248 : 0 : nb_q_updated = nb_queue + 1;
12249 : 0 : _queue_attr = mlx5_malloc(MLX5_MEM_ZERO,
12250 : : nb_q_updated *
12251 : : sizeof(struct rte_flow_queue_attr *),
12252 : : 64, SOCKET_ID_ANY);
12253 [ # # ]: 0 : if (!_queue_attr) {
12254 : 0 : rte_errno = ENOMEM;
12255 : 0 : goto err;
12256 : : }
12257 : :
12258 : 0 : memcpy(_queue_attr, queue_attr, sizeof(void *) * nb_queue);
12259 : 0 : _queue_attr[nb_queue] = &ctrl_queue_attr;
12260 : 0 : priv->acts_ipool = mlx5_ipool_create(&cfg);
12261 [ # # ]: 0 : if (!priv->acts_ipool)
12262 : 0 : goto err;
12263 : : /* Allocate the queue job descriptor LIFO. */
12264 : 0 : mem_size = sizeof(priv->hw_q[0]) * nb_q_updated;
12265 [ # # ]: 0 : for (i = 0; i < nb_q_updated; i++) {
12266 : 0 : mem_size += (sizeof(struct mlx5_hw_q_job *) +
12267 : 0 : sizeof(struct mlx5_hw_q_job)) * _queue_attr[i]->size;
12268 : : }
12269 : 0 : priv->hw_q = mlx5_malloc(MLX5_MEM_ZERO, mem_size,
12270 : : 64, SOCKET_ID_ANY);
12271 [ # # ]: 0 : if (!priv->hw_q) {
12272 : 0 : rte_errno = ENOMEM;
12273 : 0 : goto err;
12274 : : }
12275 [ # # ]: 0 : for (i = 0; i < nb_q_updated; i++) {
12276 : 0 : priv->hw_q[i].job_idx = _queue_attr[i]->size;
12277 : 0 : priv->hw_q[i].size = _queue_attr[i]->size;
12278 : 0 : priv->hw_q[i].ongoing_flow_ops = 0;
12279 [ # # ]: 0 : if (i == 0)
12280 : 0 : priv->hw_q[i].job = (struct mlx5_hw_q_job **)
12281 : 0 : &priv->hw_q[nb_q_updated];
12282 : : else
12283 : 0 : priv->hw_q[i].job = (struct mlx5_hw_q_job **)&job[_queue_attr[i - 1]->size];
12284 : 0 : job = (struct mlx5_hw_q_job *)
12285 : 0 : &priv->hw_q[i].job[_queue_attr[i]->size];
12286 [ # # ]: 0 : for (j = 0; j < _queue_attr[i]->size; j++)
12287 : 0 : priv->hw_q[i].job[j] = &job[j];
12288 : :
12289 [ # # ]: 0 : if (flow_hw_queue_setup_rings(dev, i, _queue_attr[i]->size, nt_mode) < 0)
12290 : 0 : goto err;
12291 : : }
12292 : 0 : dr_ctx_attr.pd = priv->sh->cdev->pd;
12293 : 0 : dr_ctx_attr.queues = nb_q_updated;
12294 : : /* Assign initial value of STC numbers for representors. */
12295 [ # # ]: 0 : if (priv->representor)
12296 : 0 : dr_ctx_attr.initial_log_stc_memory = MLX5_REPR_STC_MEMORY_LOG;
12297 : : /* Queue size should all be the same. Take the first one. */
12298 : 0 : dr_ctx_attr.queue_size = _queue_attr[0]->size;
12299 [ # # ]: 0 : if (port_attr->flags & RTE_FLOW_PORT_FLAG_SHARE_INDIRECT) {
12300 : : struct rte_eth_dev *host_dev = NULL;
12301 : : uint16_t port_id;
12302 : :
12303 : : MLX5_ASSERT(rte_eth_dev_is_valid_port(port_attr->host_port_id));
12304 [ # # ]: 0 : if (is_proxy) {
12305 : 0 : DRV_LOG(ERR, "cross vHCA shared mode not supported "
12306 : : "for E-Switch confgiurations");
12307 : 0 : rte_errno = ENOTSUP;
12308 : 0 : goto err;
12309 : : }
12310 [ # # ]: 0 : MLX5_ETH_FOREACH_DEV(port_id, dev->device) {
12311 [ # # ]: 0 : if (port_id == port_attr->host_port_id) {
12312 : 0 : host_dev = &rte_eth_devices[port_id];
12313 : 0 : break;
12314 : : }
12315 : : }
12316 [ # # ]: 0 : if (!host_dev || host_dev == dev ||
12317 [ # # # # ]: 0 : !host_dev->data || !host_dev->data->dev_private) {
12318 : 0 : DRV_LOG(ERR, "Invalid cross vHCA host port %u",
12319 : : port_attr->host_port_id);
12320 : 0 : rte_errno = EINVAL;
12321 : 0 : goto err;
12322 : : }
12323 : : host_priv = host_dev->data->dev_private;
12324 [ # # ]: 0 : if (host_priv->sh->cdev->ctx == priv->sh->cdev->ctx) {
12325 : 0 : DRV_LOG(ERR, "Sibling ports %u and %u do not "
12326 : : "require cross vHCA sharing mode",
12327 : : dev->data->port_id, port_attr->host_port_id);
12328 : 0 : rte_errno = EINVAL;
12329 : 0 : goto err;
12330 : : }
12331 [ # # ]: 0 : if (host_priv->shared_host) {
12332 : 0 : DRV_LOG(ERR, "Host port %u is not the sharing base",
12333 : : port_attr->host_port_id);
12334 : 0 : rte_errno = EINVAL;
12335 : 0 : goto err;
12336 : : }
12337 [ # # ]: 0 : if (port_attr->nb_counters ||
12338 [ # # ]: 0 : port_attr->nb_aging_objects ||
12339 [ # # ]: 0 : port_attr->nb_meters ||
12340 [ # # ]: 0 : port_attr->nb_conn_tracks) {
12341 : 0 : DRV_LOG(ERR,
12342 : : "Object numbers on guest port must be zeros");
12343 : 0 : rte_errno = EINVAL;
12344 : 0 : goto err;
12345 : : }
12346 : 0 : dr_ctx_attr.shared_ibv_ctx = host_priv->sh->cdev->ctx;
12347 : 0 : priv->shared_host = host_dev;
12348 : 0 : rte_atomic_fetch_add_explicit(&host_priv->shared_refcnt, 1,
12349 : : rte_memory_order_relaxed);
12350 : : }
12351 : : /* Set backward compatibale mode to support non template RTE FLOW API.*/
12352 : 0 : dr_ctx_attr.bwc = true;
12353 : 0 : priv->dr_ctx = mlx5dr_context_open(priv->sh->cdev->ctx, &dr_ctx_attr);
12354 : : /* rte_errno has been updated by HWS layer. */
12355 [ # # ]: 0 : if (!priv->dr_ctx)
12356 : 0 : goto err;
12357 : 0 : priv->nb_queue = nb_q_updated;
12358 : 0 : ret = flow_hw_action_template_drop_init(dev, error);
12359 [ # # ]: 0 : if (ret)
12360 : 0 : goto err;
12361 : : /* Initialize quotas */
12362 [ # # # # : 0 : if (port_attr->nb_quotas || (host_priv && host_priv->quota_ctx.devx_obj)) {
# # ]
12363 : 0 : ret = mlx5_flow_quota_init(dev, port_attr->nb_quotas);
12364 [ # # ]: 0 : if (ret) {
12365 : 0 : rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12366 : : "Failed to initialize quota.");
12367 : 0 : goto err;
12368 : : }
12369 : : }
12370 : : /* Initialize meter library*/
12371 [ # # # # : 0 : if (port_attr->nb_meters || (host_priv && host_priv->hws_mpool))
# # ]
12372 [ # # ]: 0 : if (mlx5_flow_meter_init(dev, port_attr->nb_meters, 0, 0, nb_q_updated))
12373 : 0 : goto err;
12374 [ # # ]: 0 : if (priv->sh->config.dv_esw_en) {
12375 : 0 : ret = flow_hw_setup_tx_repr_tagging(dev, error);
12376 [ # # ]: 0 : if (ret)
12377 : 0 : goto err;
12378 : : }
12379 [ # # ]: 0 : if (mlx5_flow_lacp_miss_needed(dev)) {
12380 : 0 : ret = flow_hw_create_lacp_miss_tables(dev);
12381 [ # # ]: 0 : if (ret) {
12382 : 0 : rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12383 : : "Unable to create LACP miss flow tables");
12384 : 0 : goto err;
12385 : : }
12386 : : }
12387 [ # # ]: 0 : if (is_proxy) {
12388 : 0 : ret = flow_hw_create_vport_actions(priv);
12389 [ # # ]: 0 : if (ret) {
12390 : 0 : rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12391 : : NULL, "Failed to create vport actions.");
12392 : 0 : goto err;
12393 : : }
12394 : 0 : ret = flow_hw_create_fdb_ctrl_tables(dev, error);
12395 [ # # ]: 0 : if (ret) {
12396 : 0 : rte_errno = -ret;
12397 : 0 : goto err;
12398 : : }
12399 : : }
12400 [ # # ]: 0 : if (mlx5_vport_tx_metadata_passing_enabled(priv->sh)) {
12401 : 0 : ret = flow_hw_create_nic_ctrl_tables(dev, error);
12402 [ # # ]: 0 : if (ret != 0) {
12403 : 0 : rte_errno = -ret;
12404 : 0 : goto err;
12405 : : }
12406 : : }
12407 [ # # # # : 0 : if (port_attr->nb_conn_tracks || (host_priv && host_priv->hws_ctpool)) {
# # ]
12408 [ # # ]: 0 : if (mlx5_flow_ct_init(dev, port_attr->nb_conn_tracks, nb_q_updated))
12409 : 0 : goto err;
12410 : : }
12411 [ # # # # : 0 : if (port_attr->nb_counters || (host_priv && host_priv->hws_cpool)) {
# # ]
12412 [ # # ]: 0 : struct mlx5_hws_cnt_pool *hws_cpool = host_priv ? host_priv->hws_cpool : NULL;
12413 : :
12414 : 0 : ret = mlx5_hws_cnt_pool_create(dev, port_attr->nb_counters,
12415 : : nb_queue, hws_cpool, error);
12416 [ # # ]: 0 : if (ret)
12417 : 0 : goto err;
12418 : : }
12419 [ # # ]: 0 : if (port_attr->nb_aging_objects) {
12420 [ # # ]: 0 : if (port_attr->nb_counters == 0) {
12421 : : /*
12422 : : * Aging management uses counter. Number counters
12423 : : * requesting should take into account a counter for
12424 : : * each flow rules containing AGE without counter.
12425 : : */
12426 : 0 : DRV_LOG(ERR, "Port %u AGE objects are requested (%u) "
12427 : : "without counters requesting.",
12428 : : dev->data->port_id,
12429 : : port_attr->nb_aging_objects);
12430 : 0 : rte_errno = EINVAL;
12431 : 0 : goto err;
12432 : : }
12433 [ # # ]: 0 : if (port_attr->flags & RTE_FLOW_PORT_FLAG_SHARE_INDIRECT) {
12434 : 0 : DRV_LOG(ERR, "Aging is not supported "
12435 : : "in cross vHCA sharing mode");
12436 : : ret = -ENOTSUP;
12437 : 0 : goto err;
12438 : : }
12439 : 0 : strict_queue = !!(port_attr->flags & RTE_FLOW_PORT_FLAG_STRICT_QUEUE);
12440 : 0 : ret = mlx5_hws_age_pool_init(dev, port_attr->nb_aging_objects,
12441 : : nb_queue, strict_queue);
12442 [ # # ]: 0 : if (ret < 0)
12443 : 0 : goto err;
12444 : : }
12445 : : if (_queue_attr)
12446 : 0 : mlx5_free(_queue_attr);
12447 [ # # ]: 0 : if (port_attr->flags & RTE_FLOW_PORT_FLAG_STRICT_QUEUE)
12448 : 0 : priv->hws_strict_queue = 1;
12449 : 0 : dev->flow_fp_ops = &mlx5_flow_hw_fp_ops;
12450 : 0 : return 0;
12451 : 0 : err:
12452 : 0 : __mlx5_flow_hw_resource_release(dev, true);
12453 [ # # ]: 0 : if (_queue_attr)
12454 : 0 : mlx5_free(_queue_attr);
12455 : : /* Do not overwrite the internal errno information. */
12456 [ # # # # ]: 0 : if (ret && error->type != RTE_FLOW_ERROR_TYPE_NONE)
12457 : : return ret;
12458 : 0 : return rte_flow_error_set(error, rte_errno,
12459 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12460 : : "fail to configure port");
12461 : : }
12462 : :
12463 : : /**
12464 : : * Configure port HWS resources.
12465 : : *
12466 : : * @param[in] dev
12467 : : * Pointer to the rte_eth_dev structure.
12468 : : * @param[in] port_attr
12469 : : * Port configuration attributes.
12470 : : * @param[in] nb_queue
12471 : : * Number of queue.
12472 : : * @param[in] queue_attr
12473 : : * Array that holds attributes for each flow queue.
12474 : : * @param[out] error
12475 : : * Pointer to error structure.
12476 : : *
12477 : : * @return
12478 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
12479 : : */
12480 : : static int
12481 : 0 : flow_hw_configure(struct rte_eth_dev *dev,
12482 : : const struct rte_flow_port_attr *port_attr,
12483 : : uint16_t nb_queue,
12484 : : const struct rte_flow_queue_attr *queue_attr[],
12485 : : struct rte_flow_error *error)
12486 : : {
12487 : 0 : struct rte_flow_error shadow_error = {0, };
12488 : :
12489 [ # # ]: 0 : if (!error)
12490 : : error = &shadow_error;
12491 : 0 : return __flow_hw_configure(dev, port_attr, nb_queue, queue_attr, false, error);
12492 : : }
12493 : :
12494 : : /**
12495 : : * Release HWS resources.
12496 : : *
12497 : : * @param[in] dev
12498 : : * Pointer to the rte_eth_dev structure.
12499 : : */
12500 : : void
12501 : 0 : mlx5_flow_hw_resource_release(struct rte_eth_dev *dev)
12502 : : {
12503 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12504 : :
12505 [ # # ]: 0 : if (!priv->dr_ctx)
12506 : : return;
12507 : 0 : __mlx5_flow_hw_resource_release(dev, false);
12508 : : }
12509 : :
12510 : : /* Sets vport tag and mask, for given port, used in HWS rules. */
12511 : : void
12512 : 0 : mlx5_flow_hw_set_port_info(struct rte_eth_dev *dev)
12513 : : {
12514 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12515 : 0 : uint16_t port_id = dev->data->port_id;
12516 : : struct flow_hw_port_info *info;
12517 : :
12518 : : MLX5_ASSERT(port_id < RTE_MAX_ETHPORTS);
12519 : 0 : info = &mlx5_flow_hw_port_infos[port_id];
12520 : 0 : info->regc_mask = priv->vport_meta_mask;
12521 : 0 : info->regc_value = priv->vport_meta_tag;
12522 [ # # ]: 0 : info->vhca_id = priv->vport_vhca_id;
12523 [ # # ]: 0 : info->is_wire = mlx5_is_port_on_mpesw_device(priv) ? priv->mpesw_uplink : priv->master;
12524 : 0 : info->is_set = 1;
12525 : 0 : }
12526 : :
12527 : : /* Clears vport tag and mask used for HWS rules. */
12528 : : void
12529 : 0 : mlx5_flow_hw_clear_port_info(struct rte_eth_dev *dev)
12530 : : {
12531 : 0 : uint16_t port_id = dev->data->port_id;
12532 : : struct flow_hw_port_info *info;
12533 : :
12534 : : MLX5_ASSERT(port_id < RTE_MAX_ETHPORTS);
12535 : 0 : info = &mlx5_flow_hw_port_infos[port_id];
12536 : : memset(info, 0, sizeof(*info));
12537 : 0 : }
12538 : :
12539 : : static int
12540 : 0 : flow_hw_conntrack_destroy(struct rte_eth_dev *dev,
12541 : : uint32_t idx,
12542 : : struct rte_flow_error *error)
12543 : : {
12544 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12545 : 0 : struct mlx5_aso_ct_pool *pool = priv->hws_ctpool;
12546 : : struct mlx5_aso_ct_action *ct;
12547 : :
12548 [ # # ]: 0 : if (priv->shared_host)
12549 : 0 : return rte_flow_error_set(error, ENOTSUP,
12550 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12551 : : NULL,
12552 : : "CT destruction is not allowed to guest port");
12553 : 0 : ct = mlx5_ipool_get(pool->cts, idx);
12554 [ # # ]: 0 : if (!ct) {
12555 : 0 : return rte_flow_error_set(error, EINVAL,
12556 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12557 : : NULL,
12558 : : "Invalid CT destruction index");
12559 : : }
12560 : 0 : rte_atomic_store_explicit(&ct->state, ASO_CONNTRACK_FREE,
12561 : : rte_memory_order_relaxed);
12562 : 0 : mlx5_ipool_free(pool->cts, idx);
12563 : 0 : return 0;
12564 : : }
12565 : :
12566 : : static int
12567 : 0 : flow_hw_conntrack_query(struct rte_eth_dev *dev, uint32_t queue, uint32_t idx,
12568 : : struct rte_flow_action_conntrack *profile,
12569 : : void *user_data, bool push,
12570 : : struct rte_flow_error *error)
12571 : : {
12572 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12573 : 0 : struct mlx5_aso_ct_pool *pool = priv->hws_ctpool;
12574 : : struct mlx5_aso_ct_action *ct;
12575 : :
12576 [ # # ]: 0 : if (priv->shared_host)
12577 : 0 : return rte_flow_error_set(error, ENOTSUP,
12578 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12579 : : NULL,
12580 : : "CT query is not allowed to guest port");
12581 : 0 : ct = mlx5_ipool_get(pool->cts, idx);
12582 [ # # ]: 0 : if (!ct) {
12583 : 0 : return rte_flow_error_set(error, EINVAL,
12584 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12585 : : NULL,
12586 : : "Invalid CT query index");
12587 : : }
12588 : 0 : profile->peer_port = ct->peer;
12589 : 0 : profile->is_original_dir = ct->is_original;
12590 [ # # ]: 0 : if (mlx5_aso_ct_query_by_wqe(priv->sh, queue, ct, profile, user_data, push))
12591 : 0 : return rte_flow_error_set(error, EIO,
12592 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12593 : : NULL,
12594 : : "Failed to query CT context");
12595 : : return 0;
12596 : : }
12597 : :
12598 : :
12599 : : static int
12600 : 0 : flow_hw_conntrack_update(struct rte_eth_dev *dev, uint32_t queue,
12601 : : const struct rte_flow_modify_conntrack *action_conf,
12602 : : uint32_t idx, void *user_data, bool push,
12603 : : struct rte_flow_error *error)
12604 : : {
12605 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12606 : 0 : struct mlx5_aso_ct_pool *pool = priv->hws_ctpool;
12607 : : struct mlx5_aso_ct_action *ct;
12608 : : const struct rte_flow_action_conntrack *new_prf;
12609 : : int ret = 0;
12610 : :
12611 [ # # ]: 0 : if (priv->shared_host)
12612 : 0 : return rte_flow_error_set(error, ENOTSUP,
12613 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12614 : : NULL,
12615 : : "CT update is not allowed to guest port");
12616 : 0 : ct = mlx5_ipool_get(pool->cts, idx);
12617 [ # # ]: 0 : if (!ct) {
12618 : 0 : return rte_flow_error_set(error, EINVAL,
12619 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12620 : : NULL,
12621 : : "Invalid CT update index");
12622 : : }
12623 : 0 : new_prf = &action_conf->new_ct;
12624 [ # # ]: 0 : if (action_conf->direction)
12625 : 0 : ct->is_original = !!new_prf->is_original_dir;
12626 [ # # ]: 0 : if (action_conf->state) {
12627 : : /* Only validate the profile when it needs to be updated. */
12628 : 0 : ret = mlx5_validate_action_ct(dev, new_prf, error);
12629 [ # # ]: 0 : if (ret)
12630 : : return ret;
12631 : 0 : ret = mlx5_aso_ct_update_by_wqe(priv->sh, queue, ct, new_prf,
12632 : : user_data, push);
12633 [ # # ]: 0 : if (ret)
12634 : 0 : return rte_flow_error_set(error, EIO,
12635 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12636 : : NULL,
12637 : : "Failed to send CT context update WQE");
12638 [ # # ]: 0 : if (queue != MLX5_HW_INV_QUEUE)
12639 : : return 0;
12640 : : /* Block until ready or a failure in synchronous mode. */
12641 : 0 : ret = mlx5_aso_ct_available(priv->sh, queue, ct);
12642 [ # # ]: 0 : if (ret)
12643 : 0 : rte_flow_error_set(error, rte_errno,
12644 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12645 : : NULL,
12646 : : "Timeout to get the CT update");
12647 : : }
12648 : : return ret;
12649 : : }
12650 : :
12651 : : static struct rte_flow_action_handle *
12652 : 0 : flow_hw_conntrack_create(struct rte_eth_dev *dev, uint32_t queue,
12653 : : const struct rte_flow_action_conntrack *pro,
12654 : : void *user_data, bool push,
12655 : : struct rte_flow_error *error)
12656 : : {
12657 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12658 : 0 : struct mlx5_aso_ct_pool *pool = priv->hws_ctpool;
12659 : : struct mlx5_aso_ct_action *ct;
12660 : 0 : uint32_t ct_idx = 0;
12661 : : int ret;
12662 : : bool async = !!(queue != MLX5_HW_INV_QUEUE);
12663 : :
12664 [ # # ]: 0 : if (priv->shared_host) {
12665 : 0 : rte_flow_error_set(error, ENOTSUP,
12666 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12667 : : NULL,
12668 : : "CT create is not allowed to guest port");
12669 : 0 : return NULL;
12670 : : }
12671 [ # # ]: 0 : if (!pool) {
12672 : 0 : rte_flow_error_set(error, EINVAL,
12673 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12674 : : "CT is not enabled");
12675 : 0 : return 0;
12676 : : }
12677 : 0 : ct = mlx5_ipool_zmalloc(pool->cts, &ct_idx);
12678 [ # # ]: 0 : if (!ct) {
12679 : 0 : rte_flow_error_set(error, rte_errno,
12680 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12681 : : "Failed to allocate CT object");
12682 : 0 : return 0;
12683 : : }
12684 : 0 : ct->offset = ct_idx - 1;
12685 : 0 : ct->is_original = !!pro->is_original_dir;
12686 : 0 : ct->peer = pro->peer_port;
12687 : 0 : ct->pool = pool;
12688 [ # # ]: 0 : if (mlx5_aso_ct_update_by_wqe(priv->sh, queue, ct, pro, user_data, push)) {
12689 : 0 : mlx5_ipool_free(pool->cts, ct_idx);
12690 : 0 : rte_flow_error_set(error, EBUSY,
12691 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12692 : : "Failed to update CT");
12693 : 0 : return 0;
12694 : : }
12695 [ # # ]: 0 : if (!async) {
12696 : 0 : ret = mlx5_aso_ct_available(priv->sh, queue, ct);
12697 [ # # ]: 0 : if (ret) {
12698 : 0 : mlx5_ipool_free(pool->cts, ct_idx);
12699 : 0 : rte_flow_error_set(error, rte_errno,
12700 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12701 : : NULL,
12702 : : "Timeout to get the CT update");
12703 : 0 : return 0;
12704 : : }
12705 : : }
12706 : 0 : return MLX5_INDIRECT_ACT_HWS_CT_GEN_IDX(ct_idx);
12707 : : }
12708 : :
12709 : : /**
12710 : : * Validate shared action.
12711 : : *
12712 : : * @param[in] dev
12713 : : * Pointer to the rte_eth_dev structure.
12714 : : * @param[in] queue
12715 : : * Which queue to be used.
12716 : : * @param[in] attr
12717 : : * Operation attribute.
12718 : : * @param[in] conf
12719 : : * Indirect action configuration.
12720 : : * @param[in] action
12721 : : * rte_flow action detail.
12722 : : * @param[in] user_data
12723 : : * Pointer to the user_data.
12724 : : * @param[out] error
12725 : : * Pointer to error structure.
12726 : : *
12727 : : * @return
12728 : : * 0 on success, otherwise negative errno value.
12729 : : */
12730 : : static int
12731 : 0 : flow_hw_action_handle_validate(struct rte_eth_dev *dev, uint32_t queue,
12732 : : const struct rte_flow_op_attr *attr,
12733 : : const struct rte_flow_indir_action_conf *conf,
12734 : : const struct rte_flow_action *action,
12735 : : void *user_data,
12736 : : struct rte_flow_error *error)
12737 : : {
12738 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12739 : :
12740 : : RTE_SET_USED(attr);
12741 : : RTE_SET_USED(queue);
12742 : : RTE_SET_USED(user_data);
12743 [ # # # # : 0 : switch (action->type) {
# # # ]
12744 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
12745 [ # # ]: 0 : if (!priv->hws_age_req) {
12746 [ # # ]: 0 : if (flow_hw_allocate_actions(dev, MLX5_FLOW_ACTION_AGE,
12747 : : error))
12748 : 0 : return rte_flow_error_set
12749 : : (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
12750 : : NULL, "aging pool not initialized");
12751 : : }
12752 : : break;
12753 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
12754 [ # # ]: 0 : if (!priv->hws_cpool) {
12755 [ # # ]: 0 : if (flow_hw_allocate_actions(dev, MLX5_FLOW_ACTION_COUNT,
12756 : : error))
12757 : 0 : return rte_flow_error_set
12758 : : (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
12759 : : NULL, "counters pool not initialized");
12760 : : }
12761 : : break;
12762 : 0 : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
12763 [ # # ]: 0 : if (priv->hws_ctpool == NULL) {
12764 [ # # ]: 0 : if (flow_hw_allocate_actions(dev, MLX5_FLOW_ACTION_CT,
12765 : : error))
12766 : 0 : return rte_flow_error_set
12767 : : (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
12768 : : NULL, "CT pool not initialized");
12769 : : }
12770 : 0 : return mlx5_validate_action_ct(dev, action->conf, error);
12771 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
12772 : 0 : return flow_hw_validate_action_meter_mark(dev, action, true, error);
12773 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
12774 : 0 : return mlx5_flow_dv_action_validate(dev, conf, action, error);
12775 : : case RTE_FLOW_ACTION_TYPE_QUOTA:
12776 : : return 0;
12777 : 0 : default:
12778 : 0 : return rte_flow_error_set(error, ENOTSUP,
12779 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12780 : : "action type not supported");
12781 : : }
12782 : : return 0;
12783 : : }
12784 : :
12785 : : static __rte_always_inline bool
12786 : : flow_hw_action_push(const struct rte_flow_op_attr *attr)
12787 : : {
12788 [ # # # # : 0 : return attr ? !attr->postpone : true;
# # # # #
# # # #
# ]
12789 : : }
12790 : :
12791 : : static __rte_always_inline struct mlx5_hw_q_job *
12792 : : flow_hw_action_job_init(struct mlx5_priv *priv, uint32_t queue,
12793 : : const struct rte_flow_action_handle *handle,
12794 : : void *user_data, void *query_data,
12795 : : enum mlx5_hw_job_type type,
12796 : : enum mlx5_hw_indirect_type indirect_type,
12797 : : struct rte_flow_error *error)
12798 : : {
12799 : : struct mlx5_hw_q_job *job;
12800 : :
12801 [ # # # # : 0 : if (queue == MLX5_HW_INV_QUEUE)
# # # # #
# # # #
# ]
12802 [ # # # # : 0 : queue = CTRL_QUEUE_ID(priv);
# # # # #
# # # ]
12803 : : job = flow_hw_job_get(priv, queue);
12804 [ # # # # : 0 : if (!job) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # ]
12805 : 0 : rte_flow_error_set(error, ENOMEM,
12806 : : RTE_FLOW_ERROR_TYPE_ACTION_NUM, NULL,
12807 : : "Action destroy failed due to queue full.");
12808 : 0 : return NULL;
12809 : : }
12810 : 0 : job->type = type;
12811 : 0 : job->action = handle;
12812 : 0 : job->user_data = user_data;
12813 : 0 : job->query.user = query_data;
12814 [ # # # # : 0 : job->indirect_type = indirect_type;
# # # # #
# # # ]
12815 : 0 : return job;
12816 : : }
12817 : :
12818 : : struct mlx5_hw_q_job *
12819 [ # # ]: 0 : mlx5_flow_action_job_init(struct mlx5_priv *priv, uint32_t queue,
12820 : : const struct rte_flow_action_handle *handle,
12821 : : void *user_data, void *query_data,
12822 : : enum mlx5_hw_job_type type,
12823 : : struct rte_flow_error *error)
12824 : : {
12825 : 0 : return flow_hw_action_job_init(priv, queue, handle, user_data, query_data,
12826 : : type, MLX5_HW_INDIRECT_TYPE_LEGACY, error);
12827 : : }
12828 : :
12829 : : static __rte_always_inline void
12830 : : flow_hw_action_finalize(struct rte_eth_dev *dev, uint32_t queue,
12831 : : struct mlx5_hw_q_job *job,
12832 : : bool push, bool aso, bool status)
12833 : : {
12834 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12835 : :
12836 [ # # ]: 0 : if (queue == MLX5_HW_INV_QUEUE)
12837 : 0 : queue = CTRL_QUEUE_ID(priv);
12838 [ # # # # : 0 : if (likely(status)) {
# # # # #
# # # ]
12839 : : /* 1. add new job to a queue */
12840 [ # # # # : 0 : if (!aso)
# # # # #
# ]
12841 [ # # # # : 0 : rte_ring_enqueue(push ?
# # # # #
# # # #
# ]
12842 : 0 : priv->hw_q[queue].indir_cq :
12843 : 0 : priv->hw_q[queue].indir_iq,
12844 : : job);
12845 : : /* 2. send pending jobs */
12846 [ # # # # : 0 : if (push)
# # # # #
# # # #
# ]
12847 : 0 : __flow_hw_push_action(dev, queue);
12848 : : } else {
12849 : : flow_hw_job_put(priv, job, queue);
12850 : : }
12851 : : }
12852 : :
12853 : : /**
12854 : : * Create shared action.
12855 : : *
12856 : : * @param[in] dev
12857 : : * Pointer to the rte_eth_dev structure.
12858 : : * @param[in] queue
12859 : : * Which queue to be used.
12860 : : * @param[in] attr
12861 : : * Operation attribute.
12862 : : * @param[in] conf
12863 : : * Indirect action configuration.
12864 : : * @param[in] action
12865 : : * rte_flow action detail.
12866 : : * @param[in] user_data
12867 : : * Pointer to the user_data.
12868 : : * @param[out] error
12869 : : * Pointer to error structure.
12870 : : *
12871 : : * @return
12872 : : * Action handle on success, NULL otherwise and rte_errno is set.
12873 : : */
12874 : : static struct rte_flow_action_handle *
12875 : 0 : flow_hw_action_handle_create(struct rte_eth_dev *dev, uint32_t queue,
12876 : : const struct rte_flow_op_attr *attr,
12877 : : const struct rte_flow_indir_action_conf *conf,
12878 : : const struct rte_flow_action *action,
12879 : : void *user_data,
12880 : : struct rte_flow_error *error)
12881 : : {
12882 : : struct rte_flow_action_handle *handle = NULL;
12883 : : struct mlx5_hw_q_job *job = NULL;
12884 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
12885 : : const struct rte_flow_action_age *age;
12886 : : struct mlx5_aso_mtr *aso_mtr = NULL;
12887 : : cnt_id_t cnt_id;
12888 : : uint32_t age_idx;
12889 : : bool push = flow_hw_action_push(attr);
12890 : : bool aso = false;
12891 : 0 : bool force_job = action->type == RTE_FLOW_ACTION_TYPE_METER_MARK;
12892 : : int ret;
12893 : :
12894 [ # # ]: 0 : if (!mlx5_hw_ctx_validate(dev, error))
12895 : : return NULL;
12896 [ # # ]: 0 : if (attr || force_job) {
12897 : : job = flow_hw_action_job_init(priv, queue, NULL, user_data,
12898 : : NULL, MLX5_HW_Q_JOB_TYPE_CREATE,
12899 : : MLX5_HW_INDIRECT_TYPE_LEGACY, error);
12900 : : if (!job)
12901 : 0 : return NULL;
12902 : : }
12903 [ # # # # : 0 : switch (action->type) {
# # # ]
12904 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
12905 [ # # ]: 0 : if (priv->hws_strict_queue) {
12906 : 0 : struct mlx5_age_info *info = GET_PORT_AGE_INFO(priv);
12907 : :
12908 [ # # ]: 0 : if (queue >= info->hw_q_age->nb_rings) {
12909 : 0 : rte_flow_error_set(error, EINVAL,
12910 : : RTE_FLOW_ERROR_TYPE_ACTION,
12911 : : NULL,
12912 : : "Invalid queue ID for indirect AGE.");
12913 : 0 : rte_errno = EINVAL;
12914 : 0 : return NULL;
12915 : : }
12916 : : }
12917 : 0 : age = action->conf;
12918 : 0 : age_idx = mlx5_hws_age_action_create(priv, queue, true, age,
12919 : : 0, error);
12920 [ # # ]: 0 : if (age_idx == 0) {
12921 : 0 : rte_flow_error_set(error, ENODEV,
12922 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12923 : : "AGE are not configured!");
12924 : : } else {
12925 : 0 : age_idx = (MLX5_INDIRECT_ACTION_TYPE_AGE <<
12926 : : MLX5_INDIRECT_ACTION_TYPE_OFFSET) | age_idx;
12927 : 0 : handle =
12928 : 0 : (struct rte_flow_action_handle *)(uintptr_t)age_idx;
12929 : : }
12930 : : break;
12931 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
12932 [ # # ]: 0 : if (mlx5_hws_cnt_shared_get(priv->hws_cpool, &cnt_id, 0))
12933 : 0 : rte_flow_error_set(error, ENODEV,
12934 : : RTE_FLOW_ERROR_TYPE_ACTION,
12935 : : NULL,
12936 : : "counter are not configured!");
12937 : : else
12938 : 0 : handle = (struct rte_flow_action_handle *)
12939 : 0 : (uintptr_t)cnt_id;
12940 : : break;
12941 : 0 : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
12942 : : aso = true;
12943 : 0 : handle = flow_hw_conntrack_create(dev, queue, action->conf, job,
12944 : : push, error);
12945 : 0 : break;
12946 [ # # ]: 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
12947 : : aso = true;
12948 : : ret = flow_hw_meter_mark_alloc(dev, queue, action, job, push, &aso_mtr, error);
12949 [ # # ]: 0 : if (ret) {
12950 [ # # ]: 0 : if (ret != -EIO) {
12951 [ # # ]: 0 : if (queue == MLX5_HW_INV_QUEUE)
12952 : 0 : queue = CTRL_QUEUE_ID(priv);
12953 : : flow_hw_job_put(priv, job, queue);
12954 : : }
12955 : : break;
12956 : : }
12957 : 0 : handle = (void *)(uintptr_t)job->action;
12958 : 0 : break;
12959 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
12960 : 0 : handle = mlx5_flow_dv_action_create(dev, conf, action, error);
12961 : 0 : break;
12962 : 0 : case RTE_FLOW_ACTION_TYPE_QUOTA:
12963 : : aso = true;
12964 : 0 : handle = mlx5_quota_alloc(dev, queue, action->conf,
12965 : : job, push, error);
12966 : 0 : break;
12967 : 0 : default:
12968 : 0 : rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
12969 : : NULL, "action type not supported");
12970 : 0 : break;
12971 : : }
12972 [ # # # # ]: 0 : if (job && (!force_job || handle)) {
12973 [ # # ]: 0 : job->action = handle;
12974 : : flow_hw_action_finalize(dev, queue, job, push, aso,
12975 : : handle != NULL);
12976 : : }
12977 : : return handle;
12978 : : }
12979 : :
12980 : : static int
12981 : 0 : mlx5_flow_update_meter_mark(struct rte_eth_dev *dev, uint32_t queue,
12982 : : const struct rte_flow_update_meter_mark *upd_meter_mark,
12983 : : uint32_t idx, bool push,
12984 : : struct mlx5_hw_q_job *job, struct rte_flow_error *error)
12985 : : {
12986 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12987 : 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
12988 : : const struct rte_flow_action_meter_mark *meter_mark = &upd_meter_mark->meter_mark;
12989 : 0 : struct mlx5_aso_mtr *aso_mtr = mlx5_ipool_get(pool->idx_pool, idx);
12990 : : struct mlx5_flow_meter_info *fm;
12991 : :
12992 [ # # ]: 0 : if (!aso_mtr)
12993 : 0 : return rte_flow_error_set(error, EINVAL,
12994 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12995 : : NULL, "Invalid meter_mark update index");
12996 : : fm = &aso_mtr->fm;
12997 [ # # ]: 0 : if (upd_meter_mark->profile_valid)
12998 : 0 : fm->profile = (struct mlx5_flow_meter_profile *)
12999 : 0 : (meter_mark->profile);
13000 [ # # ]: 0 : if (upd_meter_mark->color_mode_valid)
13001 : 0 : fm->color_aware = meter_mark->color_mode;
13002 [ # # ]: 0 : if (upd_meter_mark->state_valid)
13003 : 0 : fm->is_enable = meter_mark->state;
13004 [ # # ]: 0 : aso_mtr->state = (queue == MLX5_HW_INV_QUEUE) ?
13005 : : ASO_METER_WAIT : ASO_METER_WAIT_ASYNC;
13006 : : /* Update ASO flow meter by wqe. */
13007 [ # # ]: 0 : if (mlx5_aso_meter_update_by_wqe(priv, queue,
13008 : : aso_mtr, &priv->mtr_bulk, job, push))
13009 : 0 : return rte_flow_error_set(error, EINVAL,
13010 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13011 : : NULL, "Unable to update ASO meter WQE");
13012 : : /* Wait for ASO object completion. */
13013 [ # # # # ]: 0 : if (queue == MLX5_HW_INV_QUEUE &&
13014 : 0 : mlx5_aso_mtr_wait(priv, aso_mtr, true))
13015 : 0 : return rte_flow_error_set(error, EINVAL,
13016 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13017 : : NULL, "Unable to wait for ASO meter CQE");
13018 : : return 0;
13019 : : }
13020 : :
13021 : : /**
13022 : : * Update shared action.
13023 : : *
13024 : : * @param[in] dev
13025 : : * Pointer to the rte_eth_dev structure.
13026 : : * @param[in] queue
13027 : : * Which queue to be used.
13028 : : * @param[in] attr
13029 : : * Operation attribute.
13030 : : * @param[in] handle
13031 : : * Action handle to be updated.
13032 : : * @param[in] update
13033 : : * Update value.
13034 : : * @param[in] user_data
13035 : : * Pointer to the user_data.
13036 : : * @param[out] error
13037 : : * Pointer to error structure.
13038 : : *
13039 : : * @return
13040 : : * 0 on success, negative value otherwise and rte_errno is set.
13041 : : */
13042 : : static int
13043 : 0 : flow_hw_action_handle_update(struct rte_eth_dev *dev, uint32_t queue,
13044 : : const struct rte_flow_op_attr *attr,
13045 : : struct rte_flow_action_handle *handle,
13046 : : const void *update,
13047 : : void *user_data,
13048 : : struct rte_flow_error *error)
13049 : : {
13050 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13051 : : const struct rte_flow_modify_conntrack *ct_conf =
13052 : : (const struct rte_flow_modify_conntrack *)update;
13053 : : struct mlx5_hw_q_job *job = NULL;
13054 : 0 : uint32_t act_idx = (uint32_t)(uintptr_t)handle;
13055 : 0 : uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
13056 [ # # ]: 0 : uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
13057 : : int ret = 0;
13058 : : bool push = flow_hw_action_push(attr);
13059 : : bool aso = false;
13060 : 0 : bool force_job = type == MLX5_INDIRECT_ACTION_TYPE_METER_MARK;
13061 : :
13062 [ # # ]: 0 : if (attr || force_job) {
13063 : : job = flow_hw_action_job_init(priv, queue, handle, user_data,
13064 : : NULL, MLX5_HW_Q_JOB_TYPE_UPDATE,
13065 : : MLX5_HW_INDIRECT_TYPE_LEGACY, error);
13066 : : if (!job)
13067 : 0 : return -rte_errno;
13068 : : }
13069 [ # # # # : 0 : switch (type) {
# # ]
13070 : 0 : case MLX5_INDIRECT_ACTION_TYPE_AGE:
13071 : 0 : ret = mlx5_hws_age_action_update(priv, idx, update, error);
13072 : 0 : break;
13073 : 0 : case MLX5_INDIRECT_ACTION_TYPE_CT:
13074 [ # # ]: 0 : if (ct_conf->state)
13075 : : aso = true;
13076 : 0 : ret = flow_hw_conntrack_update(dev, queue, update, idx,
13077 : : job, push, error);
13078 : 0 : break;
13079 : 0 : case MLX5_INDIRECT_ACTION_TYPE_METER_MARK:
13080 : : aso = true;
13081 : 0 : ret = mlx5_flow_update_meter_mark(dev, queue, update, idx, push,
13082 : : job, error);
13083 : 0 : break;
13084 : 0 : case MLX5_INDIRECT_ACTION_TYPE_RSS:
13085 : 0 : ret = mlx5_flow_dv_action_update(dev, handle, update, error);
13086 : 0 : break;
13087 : 0 : case MLX5_INDIRECT_ACTION_TYPE_QUOTA:
13088 : : aso = true;
13089 : 0 : ret = mlx5_quota_query_update(dev, queue, handle, update, NULL,
13090 : : job, push, error);
13091 : 0 : break;
13092 : 0 : default:
13093 : : ret = -ENOTSUP;
13094 : 0 : rte_flow_error_set(error, ENOTSUP,
13095 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13096 : : "action type not supported");
13097 : 0 : break;
13098 : : }
13099 [ # # ]: 0 : if (job && !force_job)
13100 [ # # ]: 0 : flow_hw_action_finalize(dev, queue, job, push, aso, ret == 0);
13101 : : return ret;
13102 : : }
13103 : :
13104 : : /**
13105 : : * Destroy shared action.
13106 : : *
13107 : : * @param[in] dev
13108 : : * Pointer to the rte_eth_dev structure.
13109 : : * @param[in] queue
13110 : : * Which queue to be used.
13111 : : * @param[in] attr
13112 : : * Operation attribute.
13113 : : * @param[in] handle
13114 : : * Action handle to be destroyed.
13115 : : * @param[in] user_data
13116 : : * Pointer to the user_data.
13117 : : * @param[out] error
13118 : : * Pointer to error structure.
13119 : : *
13120 : : * @return
13121 : : * 0 on success, negative value otherwise and rte_errno is set.
13122 : : */
13123 : : static int
13124 : 0 : flow_hw_action_handle_destroy(struct rte_eth_dev *dev, uint32_t queue,
13125 : : const struct rte_flow_op_attr *attr,
13126 : : struct rte_flow_action_handle *handle,
13127 : : void *user_data,
13128 : : struct rte_flow_error *error)
13129 : : {
13130 : 0 : uint32_t act_idx = (uint32_t)(uintptr_t)handle;
13131 : 0 : uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
13132 : 0 : uint32_t age_idx = act_idx & MLX5_HWS_AGE_IDX_MASK;
13133 : : uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
13134 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13135 [ # # ]: 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
13136 : : struct mlx5_hw_q_job *job = NULL;
13137 : : struct mlx5_aso_mtr *aso_mtr;
13138 : : struct mlx5_flow_meter_info *fm;
13139 : : bool push = flow_hw_action_push(attr);
13140 : : bool aso = false;
13141 : : int ret = 0;
13142 : 0 : bool force_job = type == MLX5_INDIRECT_ACTION_TYPE_METER_MARK;
13143 : :
13144 [ # # ]: 0 : if (attr || force_job) {
13145 : : job = flow_hw_action_job_init(priv, queue, handle, user_data,
13146 : : NULL, MLX5_HW_Q_JOB_TYPE_DESTROY,
13147 : : MLX5_HW_INDIRECT_TYPE_LEGACY, error);
13148 : : if (!job)
13149 : 0 : return -rte_errno;
13150 : : }
13151 [ # # # # : 0 : switch (type) {
# # # ]
13152 : 0 : case MLX5_INDIRECT_ACTION_TYPE_AGE:
13153 : 0 : ret = mlx5_hws_age_action_destroy(priv, age_idx, error);
13154 : 0 : break;
13155 : 0 : case MLX5_INDIRECT_ACTION_TYPE_COUNT:
13156 [ # # ]: 0 : age_idx = mlx5_hws_cnt_age_get(priv->hws_cpool, act_idx);
13157 [ # # ]: 0 : if (age_idx != 0)
13158 : : /*
13159 : : * If this counter belongs to indirect AGE, here is the
13160 : : * time to update the AGE.
13161 : : */
13162 : : mlx5_hws_age_nb_cnt_decrease(priv, age_idx);
13163 [ # # ]: 0 : mlx5_hws_cnt_shared_put(priv->hws_cpool, &act_idx);
13164 : : break;
13165 : 0 : case MLX5_INDIRECT_ACTION_TYPE_CT:
13166 : 0 : ret = flow_hw_conntrack_destroy(dev, idx, error);
13167 : 0 : break;
13168 : 0 : case MLX5_INDIRECT_ACTION_TYPE_METER_MARK:
13169 : 0 : aso_mtr = mlx5_ipool_get(pool->idx_pool, idx);
13170 [ # # ]: 0 : if (!aso_mtr) {
13171 : : ret = -EINVAL;
13172 : 0 : rte_flow_error_set(error, EINVAL,
13173 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13174 : : NULL, "Invalid meter_mark destroy index");
13175 : 0 : break;
13176 : : }
13177 : : fm = &aso_mtr->fm;
13178 : 0 : fm->is_enable = 0;
13179 : : /* Update ASO flow meter by wqe. */
13180 [ # # ]: 0 : if (mlx5_aso_meter_update_by_wqe(priv, queue, aso_mtr,
13181 : : &priv->mtr_bulk, job, push)) {
13182 : : ret = -EINVAL;
13183 : 0 : rte_flow_error_set(error, EINVAL,
13184 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13185 : : NULL, "Unable to update ASO meter WQE");
13186 : 0 : break;
13187 : : }
13188 : : /* Wait for ASO object completion. */
13189 [ # # ]: 0 : if (queue == MLX5_HW_INV_QUEUE) {
13190 [ # # ]: 0 : if (mlx5_aso_mtr_wait(priv, aso_mtr, true)) {
13191 : : ret = -EINVAL;
13192 : 0 : rte_flow_error_set(error, EINVAL,
13193 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13194 : : NULL, "Unable to wait for ASO meter CQE");
13195 : : }
13196 : 0 : mlx5_ipool_free(pool->idx_pool, idx);
13197 [ # # ]: 0 : if (ret < 0)
13198 : : break;
13199 : : }
13200 : : aso = true;
13201 : : break;
13202 : 0 : case MLX5_INDIRECT_ACTION_TYPE_RSS:
13203 : 0 : ret = mlx5_flow_dv_action_destroy(dev, handle, error);
13204 : 0 : break;
13205 : : case MLX5_INDIRECT_ACTION_TYPE_QUOTA:
13206 : : break;
13207 : 0 : default:
13208 : : ret = -ENOTSUP;
13209 : 0 : rte_flow_error_set(error, ENOTSUP,
13210 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13211 : : "action type not supported");
13212 : 0 : break;
13213 : : }
13214 [ # # ]: 0 : if (job && !force_job)
13215 [ # # ]: 0 : flow_hw_action_finalize(dev, queue, job, push, aso, ret == 0);
13216 : : return ret;
13217 : : }
13218 : :
13219 : : static int
13220 : 0 : flow_hw_query_counter(const struct rte_eth_dev *dev, uint32_t counter,
13221 : : void *data, struct rte_flow_error *error)
13222 : : {
13223 : : struct mlx5_hws_cnt_pool *hpool;
13224 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
13225 : : struct mlx5_hws_cnt *cnt;
13226 : : struct rte_flow_query_count *qc = data;
13227 : : uint32_t iidx;
13228 : : uint64_t pkts, bytes;
13229 : :
13230 [ # # ]: 0 : if (!mlx5_hws_cnt_id_valid(counter))
13231 : 0 : return rte_flow_error_set(error, EINVAL,
13232 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13233 : : "counter are not available");
13234 [ # # ]: 0 : hpool = mlx5_hws_cnt_host_pool(priv->hws_cpool);
13235 : : iidx = mlx5_hws_cnt_iidx(hpool, counter);
13236 : 0 : cnt = &hpool->pool[iidx];
13237 : : __hws_cnt_query_raw(priv->hws_cpool, counter, &pkts, &bytes);
13238 : 0 : qc->hits_set = 1;
13239 : 0 : qc->bytes_set = 1;
13240 : 0 : qc->hits = pkts - cnt->reset.hits;
13241 : 0 : qc->bytes = bytes - cnt->reset.bytes;
13242 [ # # ]: 0 : if (qc->reset) {
13243 : 0 : cnt->reset.bytes = bytes;
13244 : 0 : cnt->reset.hits = pkts;
13245 : : }
13246 : : return 0;
13247 : : }
13248 : :
13249 : : /**
13250 : : * Query a flow rule AGE action for aging information.
13251 : : *
13252 : : * @param[in] dev
13253 : : * Pointer to Ethernet device.
13254 : : * @param[in] age_idx
13255 : : * Index of AGE action parameter.
13256 : : * @param[out] data
13257 : : * Data retrieved by the query.
13258 : : * @param[out] error
13259 : : * Perform verbose error reporting if not NULL.
13260 : : *
13261 : : * @return
13262 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
13263 : : */
13264 : : static int
13265 : 0 : flow_hw_query_age(const struct rte_eth_dev *dev, uint32_t age_idx, void *data,
13266 : : struct rte_flow_error *error)
13267 : : {
13268 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13269 : 0 : struct mlx5_age_info *age_info = GET_PORT_AGE_INFO(priv);
13270 : 0 : struct mlx5_indexed_pool *ipool = age_info->ages_ipool;
13271 : 0 : struct mlx5_hws_age_param *param = mlx5_ipool_get(ipool, age_idx);
13272 : : struct rte_flow_query_age *resp = data;
13273 : :
13274 [ # # # # ]: 0 : if (!param || !param->timeout)
13275 : 0 : return rte_flow_error_set(error, EINVAL,
13276 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13277 : : NULL, "age data not available");
13278 [ # # # ]: 0 : switch (rte_atomic_load_explicit(¶m->state, rte_memory_order_relaxed)) {
13279 : 0 : case HWS_AGE_AGED_OUT_REPORTED:
13280 : : case HWS_AGE_AGED_OUT_NOT_REPORTED:
13281 : 0 : resp->aged = 1;
13282 : 0 : break;
13283 : 0 : case HWS_AGE_CANDIDATE:
13284 : : case HWS_AGE_CANDIDATE_INSIDE_RING:
13285 : 0 : resp->aged = 0;
13286 : 0 : break;
13287 : : case HWS_AGE_FREE:
13288 : : /*
13289 : : * When state is FREE the flow itself should be invalid.
13290 : : * Fall-through.
13291 : : */
13292 : : default:
13293 : : MLX5_ASSERT(0);
13294 : : break;
13295 : : }
13296 : 0 : resp->sec_since_last_hit_valid = !resp->aged;
13297 [ # # ]: 0 : if (resp->sec_since_last_hit_valid)
13298 : 0 : resp->sec_since_last_hit = rte_atomic_load_explicit
13299 : : (¶m->sec_since_last_hit, rte_memory_order_relaxed);
13300 : : return 0;
13301 : : }
13302 : :
13303 : : static int
13304 : 0 : flow_hw_query(struct rte_eth_dev *dev, struct rte_flow *flow,
13305 : : const struct rte_flow_action *actions, void *data,
13306 : : struct rte_flow_error *error)
13307 : : {
13308 : : int ret = -EINVAL;
13309 : : struct rte_flow_hw *hw_flow = (struct rte_flow_hw *)flow;
13310 : : struct rte_flow_hw_aux *aux;
13311 : :
13312 [ # # ]: 0 : for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
13313 [ # # # # ]: 0 : switch (actions->type) {
13314 : : case RTE_FLOW_ACTION_TYPE_VOID:
13315 : : break;
13316 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
13317 [ # # ]: 0 : if (!(hw_flow->flags & MLX5_FLOW_HW_FLOW_FLAG_CNT_ID))
13318 : 0 : return rte_flow_error_set(error, EINVAL,
13319 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13320 : : "counter not defined in the rule");
13321 : 0 : ret = flow_hw_query_counter(dev, hw_flow->cnt_id, data,
13322 : : error);
13323 : 0 : break;
13324 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
13325 [ # # ]: 0 : if (!(hw_flow->flags & MLX5_FLOW_HW_FLOW_FLAG_AGE_IDX))
13326 : 0 : return rte_flow_error_set(error, EINVAL,
13327 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13328 : : "age data not available");
13329 [ # # ]: 0 : aux = mlx5_flow_hw_aux(dev->data->port_id, hw_flow);
13330 : 0 : ret = flow_hw_query_age(dev, mlx5_flow_hw_aux_get_age_idx(hw_flow, aux),
13331 : : data, error);
13332 : 0 : break;
13333 : 0 : default:
13334 : 0 : return rte_flow_error_set(error, ENOTSUP,
13335 : : RTE_FLOW_ERROR_TYPE_ACTION,
13336 : : actions,
13337 : : "action not supported");
13338 : : }
13339 : : }
13340 : : return ret;
13341 : : }
13342 : :
13343 : : /**
13344 : : * Validate indirect action.
13345 : : *
13346 : : * @param[in] dev
13347 : : * Pointer to the Ethernet device structure.
13348 : : * @param[in] conf
13349 : : * Shared action configuration.
13350 : : * @param[in] action
13351 : : * Action specification used to create indirect action.
13352 : : * @param[out] error
13353 : : * Perform verbose error reporting if not NULL. Initialized in case of
13354 : : * error only.
13355 : : *
13356 : : * @return
13357 : : * 0 on success, otherwise negative errno value.
13358 : : */
13359 : : static int
13360 : 0 : flow_hw_action_validate(struct rte_eth_dev *dev,
13361 : : const struct rte_flow_indir_action_conf *conf,
13362 : : const struct rte_flow_action *action,
13363 : : struct rte_flow_error *err)
13364 : : {
13365 : 0 : struct rte_flow_error shadow_error = {0, };
13366 : :
13367 [ # # ]: 0 : if (!err)
13368 : : err = &shadow_error;
13369 : 0 : return flow_hw_action_handle_validate(dev, MLX5_HW_INV_QUEUE, NULL,
13370 : : conf, action, NULL, err);
13371 : : }
13372 : :
13373 : : /**
13374 : : * Create indirect action.
13375 : : *
13376 : : * @param[in] dev
13377 : : * Pointer to the Ethernet device structure.
13378 : : * @param[in] conf
13379 : : * Shared action configuration.
13380 : : * @param[in] action
13381 : : * Action specification used to create indirect action.
13382 : : * @param[out] error
13383 : : * Perform verbose error reporting if not NULL. Initialized in case of
13384 : : * error only.
13385 : : *
13386 : : * @return
13387 : : * A valid shared action handle in case of success, NULL otherwise and
13388 : : * rte_errno is set.
13389 : : */
13390 : : static struct rte_flow_action_handle *
13391 : 0 : flow_hw_action_create(struct rte_eth_dev *dev,
13392 : : const struct rte_flow_indir_action_conf *conf,
13393 : : const struct rte_flow_action *action,
13394 : : struct rte_flow_error *err)
13395 : : {
13396 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13397 : :
13398 [ # # # # ]: 0 : if (action->type == RTE_FLOW_ACTION_TYPE_AGE && priv->hws_strict_queue) {
13399 : 0 : rte_flow_error_set(err, EINVAL, RTE_FLOW_ERROR_TYPE_STATE, NULL,
13400 : : "Cannot create age action synchronously with strict queueing");
13401 : 0 : return NULL;
13402 : : }
13403 : :
13404 : 0 : return flow_hw_action_handle_create(dev, MLX5_HW_INV_QUEUE,
13405 : : NULL, conf, action, NULL, err);
13406 : : }
13407 : :
13408 : : /**
13409 : : * Destroy the indirect action.
13410 : : * Release action related resources on the NIC and the memory.
13411 : : * Lock free, (mutex should be acquired by caller).
13412 : : * Dispatcher for action type specific call.
13413 : : *
13414 : : * @param[in] dev
13415 : : * Pointer to the Ethernet device structure.
13416 : : * @param[in] handle
13417 : : * The indirect action object handle to be removed.
13418 : : * @param[out] error
13419 : : * Perform verbose error reporting if not NULL. Initialized in case of
13420 : : * error only.
13421 : : *
13422 : : * @return
13423 : : * 0 on success, otherwise negative errno value.
13424 : : */
13425 : : static int
13426 : 0 : flow_hw_action_destroy(struct rte_eth_dev *dev,
13427 : : struct rte_flow_action_handle *handle,
13428 : : struct rte_flow_error *error)
13429 : : {
13430 : 0 : return flow_hw_action_handle_destroy(dev, MLX5_HW_INV_QUEUE,
13431 : : NULL, handle, NULL, error);
13432 : : }
13433 : :
13434 : : /**
13435 : : * Updates in place shared action configuration.
13436 : : *
13437 : : * @param[in] dev
13438 : : * Pointer to the Ethernet device structure.
13439 : : * @param[in] handle
13440 : : * The indirect action object handle to be updated.
13441 : : * @param[in] update
13442 : : * Action specification used to modify the action pointed by *handle*.
13443 : : * *update* could be of same type with the action pointed by the *handle*
13444 : : * handle argument, or some other structures like a wrapper, depending on
13445 : : * the indirect action type.
13446 : : * @param[out] error
13447 : : * Perform verbose error reporting if not NULL. Initialized in case of
13448 : : * error only.
13449 : : *
13450 : : * @return
13451 : : * 0 on success, otherwise negative errno value.
13452 : : */
13453 : : static int
13454 : 0 : flow_hw_action_update(struct rte_eth_dev *dev,
13455 : : struct rte_flow_action_handle *handle,
13456 : : const void *update,
13457 : : struct rte_flow_error *err)
13458 : : {
13459 : 0 : return flow_hw_action_handle_update(dev, MLX5_HW_INV_QUEUE,
13460 : : NULL, handle, update, NULL, err);
13461 : : }
13462 : :
13463 : : static int
13464 : 0 : flow_hw_action_handle_query(struct rte_eth_dev *dev, uint32_t queue,
13465 : : const struct rte_flow_op_attr *attr,
13466 : : const struct rte_flow_action_handle *handle,
13467 : : void *data, void *user_data,
13468 : : struct rte_flow_error *error)
13469 : : {
13470 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13471 : : struct mlx5_hw_q_job *job = NULL;
13472 : 0 : uint32_t act_idx = (uint32_t)(uintptr_t)handle;
13473 : 0 : uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
13474 [ # # ]: 0 : uint32_t idx = MLX5_INDIRECT_ACTION_IDX_GET(handle);
13475 : : uint32_t age_idx = act_idx & MLX5_HWS_AGE_IDX_MASK;
13476 : : int ret;
13477 : : bool push = flow_hw_action_push(attr);
13478 : : bool aso = false;
13479 : :
13480 [ # # ]: 0 : if (attr) {
13481 : : job = flow_hw_action_job_init(priv, queue, handle, user_data,
13482 : : data, MLX5_HW_Q_JOB_TYPE_QUERY,
13483 : : MLX5_HW_INDIRECT_TYPE_LEGACY, error);
13484 : : if (!job)
13485 : 0 : return -rte_errno;
13486 : : }
13487 [ # # # # : 0 : switch (type) {
# ]
13488 : 0 : case MLX5_INDIRECT_ACTION_TYPE_AGE:
13489 : 0 : ret = flow_hw_query_age(dev, age_idx, data, error);
13490 : 0 : break;
13491 : 0 : case MLX5_INDIRECT_ACTION_TYPE_COUNT:
13492 : 0 : ret = flow_hw_query_counter(dev, act_idx, data, error);
13493 : 0 : break;
13494 : 0 : case MLX5_INDIRECT_ACTION_TYPE_CT:
13495 : : aso = true;
13496 [ # # ]: 0 : if (job)
13497 : 0 : job->query.user = data;
13498 : 0 : ret = flow_hw_conntrack_query(dev, queue, idx, data,
13499 : : job, push, error);
13500 : 0 : break;
13501 : 0 : case MLX5_INDIRECT_ACTION_TYPE_QUOTA:
13502 : : aso = true;
13503 : 0 : ret = mlx5_quota_query(dev, queue, handle, data,
13504 : : job, push, error);
13505 : 0 : break;
13506 : 0 : default:
13507 : : ret = -ENOTSUP;
13508 : 0 : rte_flow_error_set(error, ENOTSUP,
13509 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13510 : : "action type not supported");
13511 : 0 : break;
13512 : : }
13513 [ # # ]: 0 : if (job)
13514 [ # # ]: 0 : flow_hw_action_finalize(dev, queue, job, push, aso, ret == 0);
13515 : : return ret;
13516 : : }
13517 : :
13518 : : static int
13519 : 0 : flow_hw_async_action_handle_query_update
13520 : : (struct rte_eth_dev *dev, uint32_t queue,
13521 : : const struct rte_flow_op_attr *attr,
13522 : : struct rte_flow_action_handle *handle,
13523 : : const void *update, void *query,
13524 : : enum rte_flow_query_update_mode qu_mode,
13525 : : void *user_data, struct rte_flow_error *error)
13526 : : {
13527 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
13528 : : bool push = flow_hw_action_push(attr);
13529 : : bool aso = false;
13530 : : struct mlx5_hw_q_job *job = NULL;
13531 : : int ret = 0;
13532 : :
13533 [ # # ]: 0 : if (attr) {
13534 : : job = flow_hw_action_job_init(priv, queue, handle, user_data,
13535 : : query,
13536 : : MLX5_HW_Q_JOB_TYPE_UPDATE_QUERY,
13537 : : MLX5_HW_INDIRECT_TYPE_LEGACY, error);
13538 : : if (!job)
13539 : 0 : return -rte_errno;
13540 : : }
13541 [ # # ]: 0 : switch (MLX5_INDIRECT_ACTION_TYPE_GET(handle)) {
13542 : 0 : case MLX5_INDIRECT_ACTION_TYPE_QUOTA:
13543 [ # # ]: 0 : if (qu_mode != RTE_FLOW_QU_QUERY_FIRST) {
13544 : 0 : ret = rte_flow_error_set
13545 : : (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION_CONF,
13546 : : NULL, "quota action must query before update");
13547 : 0 : break;
13548 : : }
13549 : : aso = true;
13550 : 0 : ret = mlx5_quota_query_update(dev, queue, handle,
13551 : : update, query, job, push, error);
13552 : 0 : break;
13553 : 0 : default:
13554 : 0 : ret = rte_flow_error_set(error, ENOTSUP,
13555 : : RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, "update and query not supportred");
13556 : : }
13557 [ # # ]: 0 : if (job)
13558 [ # # ]: 0 : flow_hw_action_finalize(dev, queue, job, push, aso, ret == 0);
13559 : : return ret;
13560 : : }
13561 : :
13562 : : static int
13563 : 0 : flow_hw_action_query(struct rte_eth_dev *dev,
13564 : : const struct rte_flow_action_handle *handle, void *data,
13565 : : struct rte_flow_error *error)
13566 : : {
13567 : 0 : return flow_hw_action_handle_query(dev, MLX5_HW_INV_QUEUE, NULL,
13568 : : handle, data, NULL, error);
13569 : : }
13570 : :
13571 : : static int
13572 : 0 : flow_hw_action_query_update(struct rte_eth_dev *dev,
13573 : : struct rte_flow_action_handle *handle,
13574 : : const void *update, void *query,
13575 : : enum rte_flow_query_update_mode qu_mode,
13576 : : struct rte_flow_error *error)
13577 : : {
13578 : 0 : return flow_hw_async_action_handle_query_update(dev, MLX5_HW_INV_QUEUE,
13579 : : NULL, handle, update,
13580 : : query, qu_mode, NULL,
13581 : : error);
13582 : : }
13583 : :
13584 : : /**
13585 : : * Get aged-out flows of a given port on the given HWS flow queue.
13586 : : *
13587 : : * @param[in] dev
13588 : : * Pointer to the Ethernet device structure.
13589 : : * @param[in] queue_id
13590 : : * Flow queue to query. Ignored when RTE_FLOW_PORT_FLAG_STRICT_QUEUE not set.
13591 : : * @param[in, out] contexts
13592 : : * The address of an array of pointers to the aged-out flows contexts.
13593 : : * @param[in] nb_contexts
13594 : : * The length of context array pointers.
13595 : : * @param[out] error
13596 : : * Perform verbose error reporting if not NULL. Initialized in case of
13597 : : * error only.
13598 : : *
13599 : : * @return
13600 : : * if nb_contexts is 0, return the amount of all aged contexts.
13601 : : * if nb_contexts is not 0 , return the amount of aged flows reported
13602 : : * in the context array, otherwise negative errno value.
13603 : : */
13604 : : static int
13605 : 0 : flow_hw_get_q_aged_flows(struct rte_eth_dev *dev, uint32_t queue_id,
13606 : : void **contexts, uint32_t nb_contexts,
13607 : : struct rte_flow_error *error)
13608 : : {
13609 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13610 : 0 : struct mlx5_age_info *age_info = GET_PORT_AGE_INFO(priv);
13611 : : struct rte_ring *r;
13612 : : int nb_flows = 0;
13613 : :
13614 [ # # ]: 0 : if (nb_contexts && !contexts)
13615 : 0 : return rte_flow_error_set(error, EINVAL,
13616 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13617 : : NULL, "empty context");
13618 [ # # ]: 0 : if (!priv->hws_age_req)
13619 : 0 : return rte_flow_error_set(error, ENOENT,
13620 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13621 : : NULL, "No aging initialized");
13622 [ # # ]: 0 : if (priv->hws_strict_queue) {
13623 : : /* Queue is invalid in sync query. Sync query and strict queueing is disallowed. */
13624 : : MLX5_ASSERT(queue_id != MLX5_HW_INV_QUEUE);
13625 [ # # ]: 0 : if (queue_id >= age_info->hw_q_age->nb_rings)
13626 : 0 : return rte_flow_error_set(error, EINVAL,
13627 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13628 : : NULL, "invalid queue id");
13629 : 0 : r = age_info->hw_q_age->aged_lists[queue_id];
13630 : : } else {
13631 : 0 : r = age_info->hw_age.aged_list;
13632 : 0 : MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
13633 : : }
13634 [ # # ]: 0 : if (nb_contexts == 0)
13635 : 0 : return rte_ring_count(r);
13636 [ # # ]: 0 : while ((uint32_t)nb_flows < nb_contexts) {
13637 : : uint32_t age_idx;
13638 : :
13639 : : if (rte_ring_dequeue_elem(r, &age_idx, sizeof(uint32_t)) < 0)
13640 : : break;
13641 : : /* get the AGE context if the aged-out index is still valid. */
13642 : 0 : contexts[nb_flows] = mlx5_hws_age_context_get(priv, age_idx);
13643 [ # # ]: 0 : if (!contexts[nb_flows])
13644 : 0 : continue;
13645 : 0 : nb_flows++;
13646 : : }
13647 : : return nb_flows;
13648 : : }
13649 : :
13650 : : /**
13651 : : * Get aged-out flows.
13652 : : *
13653 : : * This function is relevant only if RTE_FLOW_PORT_FLAG_STRICT_QUEUE isn't set.
13654 : : *
13655 : : * @param[in] dev
13656 : : * Pointer to the Ethernet device structure.
13657 : : * @param[in] contexts
13658 : : * The address of an array of pointers to the aged-out flows contexts.
13659 : : * @param[in] nb_contexts
13660 : : * The length of context array pointers.
13661 : : * @param[out] error
13662 : : * Perform verbose error reporting if not NULL. Initialized in case of
13663 : : * error only.
13664 : : *
13665 : : * @return
13666 : : * how many contexts get in success, otherwise negative errno value.
13667 : : * if nb_contexts is 0, return the amount of all aged contexts.
13668 : : * if nb_contexts is not 0 , return the amount of aged flows reported
13669 : : * in the context array.
13670 : : */
13671 : : static int
13672 : 0 : flow_hw_get_aged_flows(struct rte_eth_dev *dev, void **contexts,
13673 : : uint32_t nb_contexts, struct rte_flow_error *error)
13674 : : {
13675 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13676 : :
13677 [ # # ]: 0 : if (priv->hws_strict_queue)
13678 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_STATE, NULL,
13679 : : "Cannot get aged flows synchronously with strict queueing");
13680 : :
13681 : 0 : return flow_hw_get_q_aged_flows(dev, MLX5_HW_INV_QUEUE, contexts, nb_contexts, error);
13682 : : }
13683 : : /**
13684 : : * Initialization function for non template API which calls
13685 : : * flow_hw_configure with default values.
13686 : : * Configure non queues cause 1 queue is configured by default for inner usage.
13687 : : *
13688 : : * @param[in] dev
13689 : : * Pointer to the Ethernet device structure.
13690 : : * @param[out] error
13691 : : * Pointer to the error structure.
13692 : : *
13693 : : * @return
13694 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
13695 : : */
13696 : : int
13697 : 0 : mlx5_flow_hw_init(struct rte_eth_dev *dev,
13698 : : struct rte_flow_error *error)
13699 : : {
13700 : 0 : const struct rte_flow_port_attr port_attr = {0};
13701 : 0 : const struct rte_flow_queue_attr queue_attr = {.size = MLX5_NT_DEFAULT_QUEUE_SIZE};
13702 : 0 : const struct rte_flow_queue_attr *attr_list = &queue_attr;
13703 : :
13704 : : /**
13705 : : * If user uses template and non template API:
13706 : : * User will call flow_hw_configure and non template
13707 : : * API will use the allocated actions.
13708 : : * Init function will not call flow_hw_configure.
13709 : : *
13710 : : * If user uses only non template API's:
13711 : : * Init function will call flow_hw_configure.
13712 : : * It will not allocate memory for actions.
13713 : : * When needed allocation, it will handle same as for SWS today,
13714 : : * meaning using bulk allocations and resize as needed.
13715 : : */
13716 : : /* Configure hws with default values. */
13717 : 0 : DRV_LOG(DEBUG, "Apply default configuration, zero number of queues, inner control queue size is %u",
13718 : : MLX5_NT_DEFAULT_QUEUE_SIZE);
13719 : 0 : return __flow_hw_configure(dev, &port_attr, 0, &attr_list, true, error);
13720 : : }
13721 : :
13722 : 0 : static int flow_hw_prepare(struct rte_eth_dev *dev,
13723 : : const struct rte_flow_action actions[] __rte_unused,
13724 : : enum mlx5_flow_type type,
13725 : : struct rte_flow_hw **flow,
13726 : : struct rte_flow_error *error)
13727 : : {
13728 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13729 : 0 : uint32_t idx = 0;
13730 : :
13731 : : /*
13732 : : * Notice pool idx size = (sizeof(struct rte_flow_hw)
13733 : : * + sizeof(struct rte_flow_nt2hws)) for HWS mode.
13734 : : */
13735 : 0 : *flow = mlx5_ipool_zmalloc(priv->flows[type], &idx);
13736 [ # # ]: 0 : if (!(*flow))
13737 : 0 : return rte_flow_error_set(error, ENOMEM,
13738 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13739 : : "cannot allocate flow memory");
13740 : : /* Allocating 2 structures in one pool slot, updating nt2hw pointer.*/
13741 : 0 : (*flow)->nt2hws = (struct rte_flow_nt2hws *)
13742 : 0 : ((uintptr_t)(*flow) + sizeof(struct rte_flow_hw));
13743 : 0 : (*flow)->idx = idx;
13744 : 0 : (*flow)->nt2hws->flow_aux = (struct rte_flow_hw_aux *)
13745 : 0 : ((uintptr_t)((*flow)->nt2hws) + sizeof(struct rte_flow_nt2hws));
13746 : :
13747 [ # # ]: 0 : if (!(*flow)->nt2hws->flow_aux)
13748 : 0 : return rte_flow_error_set(error, ENOMEM,
13749 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13750 : : "cannot allocate flow aux memory");
13751 : : return 0;
13752 : : }
13753 : :
13754 : : static inline void
13755 : 0 : flow_hw_set_dv_fields(struct rte_flow_template_table_attr *table_attr, uint32_t fdb_unified_en,
13756 : : bool *root, uint8_t *ft_type, uint64_t *flags)
13757 : : {
13758 [ # # ]: 0 : if (table_attr->flow_attr.transfer)
13759 : 0 : *ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
13760 : : else
13761 : 0 : *ft_type = table_attr->flow_attr.egress ?
13762 : 0 : MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
13763 : : MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
13764 : 0 : uint32_t group = table_attr->flow_attr.group;
13765 : 0 : *root = group ? 0 : 1;
13766 : 0 : *flags = mlx5_hw_act_flag[!!group][get_mlx5dr_table_type(&table_attr->flow_attr,
13767 : : table_attr->specialize,
13768 : : fdb_unified_en)];
13769 : 0 : }
13770 : :
13771 : : static int
13772 : 0 : flow_hw_modify_hdr_resource_register
13773 : : (struct rte_eth_dev *dev,
13774 : : struct rte_flow_template_table *table,
13775 : : struct mlx5_hw_actions *hw_acts,
13776 : : struct rte_flow_hw *dev_flow,
13777 : : struct rte_flow_error *error)
13778 : : {
13779 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
13780 : : bool unified_fdb = is_unified_fdb(priv);
13781 : 0 : struct rte_flow_template_table_attr *table_attr = &table->cfg.attr;
13782 : 0 : struct mlx5_flow_dv_modify_hdr_resource *dv_resource_ptr = NULL;
13783 : : union {
13784 : : struct mlx5_flow_dv_modify_hdr_resource dv_resource;
13785 : : uint8_t data[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
13786 : : sizeof(struct mlx5_modification_cmd) * MLX5_MHDR_MAX_CMD];
13787 : : } dummy;
13788 : : int ret;
13789 : :
13790 [ # # ]: 0 : if (hw_acts->mhdr) {
13791 : 0 : dummy.dv_resource.actions_num = hw_acts->mhdr->mhdr_cmds_num;
13792 : 0 : memcpy(dummy.dv_resource.actions, hw_acts->mhdr->mhdr_cmds,
13793 : 0 : sizeof(struct mlx5_modification_cmd) * dummy.dv_resource.actions_num);
13794 : : } else {
13795 : : return 0;
13796 : : }
13797 : 0 : flow_hw_set_dv_fields(table_attr, unified_fdb,
13798 : : &dummy.dv_resource.root, &dummy.dv_resource.ft_type,
13799 : : &dummy.dv_resource.flags);
13800 : 0 : dummy.dv_resource.flags |= MLX5DR_ACTION_FLAG_SHARED;
13801 : 0 : ret = mlx5_flow_modify_hdr_resource_register(dev, &dummy.dv_resource,
13802 : : &dv_resource_ptr, error);
13803 [ # # ]: 0 : if (ret)
13804 : : return ret;
13805 : : MLX5_ASSERT(dv_resource_ptr);
13806 : 0 : dev_flow->nt2hws->modify_hdr = dv_resource_ptr;
13807 : : /* keep action for the rule construction. */
13808 : 0 : hw_acts->rule_acts[hw_acts->mhdr->pos].action = dv_resource_ptr->action;
13809 : : /* Bulk size is 1, so index is 1. */
13810 : 0 : dev_flow->res_idx = 1;
13811 : 0 : return 0;
13812 : : }
13813 : :
13814 : : static int
13815 : 0 : flow_hw_encap_decap_resource_register
13816 : : (struct rte_eth_dev *dev,
13817 : : struct rte_flow_template_table *table,
13818 : : struct mlx5_hw_actions *hw_acts,
13819 : : struct rte_flow_hw *dev_flow,
13820 : : struct rte_flow_error *error)
13821 : : {
13822 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
13823 : : bool unified_fdb = is_unified_fdb(priv);
13824 : 0 : struct rte_flow_template_table_attr *table_attr = &table->cfg.attr;
13825 : 0 : struct mlx5_flow_dv_encap_decap_resource *dv_resource_ptr = NULL;
13826 : : struct mlx5_flow_dv_encap_decap_resource dv_resource;
13827 : : struct mlx5_tbl_multi_pattern_ctx *mpctx = &table->mpctx;
13828 : : int ret;
13829 : : bool is_root;
13830 : : int ix;
13831 : :
13832 [ # # ]: 0 : if (hw_acts->encap_decap)
13833 : 0 : dv_resource.reformat_type = hw_acts->encap_decap->action_type;
13834 : : else
13835 : : return 0;
13836 : 0 : flow_hw_set_dv_fields(table_attr, unified_fdb, &is_root, &dv_resource.ft_type,
13837 : : &dv_resource.flags);
13838 [ # # ]: 0 : ix = mlx5_bwc_multi_pattern_reformat_to_index((enum mlx5dr_action_type)
13839 : : dv_resource.reformat_type);
13840 : : if (ix < 0)
13841 : 0 : return ix;
13842 [ # # ]: 0 : if (hw_acts->encap_decap->shared) {
13843 : 0 : dv_resource.size = hw_acts->encap_decap->data_size;
13844 : : MLX5_ASSERT(dv_resource.size <= MLX5_ENCAP_MAX_LEN);
13845 : 0 : memcpy(&dv_resource.buf, hw_acts->encap_decap->data, dv_resource.size);
13846 : 0 : dv_resource.flags |= MLX5DR_ACTION_FLAG_SHARED;
13847 : : } else {
13848 : 0 : typeof(mpctx->reformat[0]) *reformat = mpctx->reformat + ix;
13849 [ # # ]: 0 : if (!reformat->elements_num)
13850 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
13851 : : NULL, "No reformat action exist in the table.");
13852 : 0 : dv_resource.size = reformat->reformat_hdr->sz;
13853 : : MLX5_ASSERT(dv_resource.size <= MLX5_ENCAP_MAX_LEN);
13854 : 0 : memcpy(&dv_resource.buf, reformat->reformat_hdr->data, dv_resource.size);
13855 : : }
13856 : 0 : ret = mlx5_flow_encap_decap_resource_register(dev, &dv_resource, is_root,
13857 : : &dv_resource_ptr, error);
13858 [ # # ]: 0 : if (ret)
13859 : : return ret;
13860 : : MLX5_ASSERT(dv_resource_ptr);
13861 : 0 : dev_flow->nt2hws->rix_encap_decap = dv_resource_ptr->idx;
13862 : : /* keep action for the rule construction. */
13863 [ # # ]: 0 : if (hw_acts->encap_decap->shared)
13864 : 0 : hw_acts->rule_acts[hw_acts->encap_decap_pos].action = dv_resource_ptr->action;
13865 : : else
13866 : 0 : mpctx->segments[0].reformat_action[ix] = dv_resource_ptr->action;
13867 : : /* Bulk size is 1, so index is 1. */
13868 : 0 : dev_flow->res_idx = 1;
13869 : 0 : return 0;
13870 : : }
13871 : :
13872 : : static enum rte_flow_action_type
13873 : : flow_nta_get_indirect_action_type(const struct rte_flow_action *action)
13874 : : {
13875 [ # # ]: 0 : switch (MLX5_INDIRECT_ACTION_TYPE_GET(action->conf)) {
13876 : : case MLX5_INDIRECT_ACTION_TYPE_RSS:
13877 : : return RTE_FLOW_ACTION_TYPE_RSS;
13878 : : case MLX5_INDIRECT_ACTION_TYPE_AGE:
13879 : : return RTE_FLOW_ACTION_TYPE_AGE;
13880 : : case MLX5_INDIRECT_ACTION_TYPE_COUNT:
13881 : : return RTE_FLOW_ACTION_TYPE_COUNT;
13882 : : case MLX5_INDIRECT_ACTION_TYPE_CT:
13883 : : return RTE_FLOW_ACTION_TYPE_CONNTRACK;
13884 : : default:
13885 : : break;
13886 : : }
13887 : : return RTE_FLOW_ACTION_TYPE_END;
13888 : : }
13889 : :
13890 : : static void
13891 : : flow_nta_set_mh_mask_conf(const struct rte_flow_action_modify_field *action_conf,
13892 : : struct rte_flow_action_modify_field *mask_conf)
13893 : : {
13894 : : memset(mask_conf, 0xff, sizeof(*mask_conf));
13895 : 0 : mask_conf->operation = action_conf->operation;
13896 : 0 : mask_conf->dst.field = action_conf->dst.field;
13897 : 0 : mask_conf->src.field = action_conf->src.field;
13898 : : }
13899 : :
13900 : : union actions_conf {
13901 : : struct rte_flow_action_modify_field modify_field;
13902 : : struct rte_flow_action_raw_encap raw_encap;
13903 : : struct rte_flow_action_vxlan_encap vxlan_encap;
13904 : : struct rte_flow_action_nvgre_encap nvgre_encap;
13905 : : };
13906 : :
13907 : : static int
13908 : 0 : flow_nta_build_template_mask(const struct rte_flow_action actions[],
13909 : : struct rte_flow_action masks[MLX5_HW_MAX_ACTS],
13910 : : union actions_conf mask_conf[MLX5_HW_MAX_ACTS])
13911 : : {
13912 : : int i;
13913 : :
13914 [ # # # # ]: 0 : for (i = 0; i == 0 || actions[i - 1].type != RTE_FLOW_ACTION_TYPE_END; i++) {
13915 : 0 : const struct rte_flow_action *action = &actions[i];
13916 : 0 : struct rte_flow_action *mask = &masks[i];
13917 : 0 : union actions_conf *conf = &mask_conf[i];
13918 : :
13919 : 0 : mask->type = action->type;
13920 [ # # # # : 0 : switch (action->type) {
# # # ]
13921 : : case RTE_FLOW_ACTION_TYPE_INDIRECT:
13922 : 0 : mask->type = flow_nta_get_indirect_action_type(action);
13923 [ # # ]: 0 : if (!mask->type)
13924 : : return -EINVAL;
13925 : : break;
13926 : 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
13927 : 0 : flow_nta_set_mh_mask_conf(action->conf, (void *)conf);
13928 : 0 : mask->conf = conf;
13929 : 0 : break;
13930 : : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
13931 : : /* This mask will set this action as shared. */
13932 : : memset(conf, 0xff, sizeof(struct rte_flow_action_raw_encap));
13933 : 0 : mask->conf = conf;
13934 : 0 : break;
13935 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
13936 : : /* This mask will set this action as shared. */
13937 : 0 : conf->vxlan_encap.definition =
13938 : : ((const struct rte_flow_action_vxlan_encap *)
13939 : 0 : action->conf)->definition;
13940 : 0 : mask->conf = conf;
13941 : 0 : break;
13942 : 0 : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
13943 : : /* This mask will set this action as shared. */
13944 : 0 : conf->nvgre_encap.definition =
13945 : : ((const struct rte_flow_action_nvgre_encap *)
13946 : 0 : action->conf)->definition;
13947 : 0 : mask->conf = conf;
13948 : 0 : break;
13949 : : case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
13950 : : memset(conf, 0xff, sizeof(struct rte_flow_action_of_set_vlan_vid));
13951 : 0 : mask->conf = conf;
13952 : 0 : break;
13953 : : default:
13954 : : break;
13955 : : }
13956 : : }
13957 : : return 0;
13958 : : #undef NTA_CHECK_CONF_BUF_SIZE
13959 : : }
13960 : :
13961 : : static int
13962 : 0 : flow_hw_translate_flow_actions(struct rte_eth_dev *dev,
13963 : : const struct rte_flow_attr *attr,
13964 : : const struct rte_flow_action actions[],
13965 : : struct rte_flow_hw *flow,
13966 : : struct mlx5_flow_hw_action_params *ap,
13967 : : struct mlx5_hw_actions *hw_acts,
13968 : : uint64_t item_flags, uint64_t action_flags,
13969 : : bool external,
13970 : : struct rte_flow_error *error)
13971 : : {
13972 : : int ret = 0;
13973 : 0 : uint32_t src_group = 0;
13974 : : enum mlx5dr_table_type table_type;
13975 : : struct mlx5_flow_group grp;
13976 : : struct rte_flow_actions_template *at = NULL;
13977 : 0 : struct rte_flow_actions_template_attr template_attr = {
13978 : 0 : .egress = attr->egress,
13979 : 0 : .ingress = attr->ingress,
13980 : 0 : .transfer = attr->transfer,
13981 : : };
13982 : : struct rte_flow_action masks[MLX5_HW_MAX_ACTS];
13983 : : union actions_conf mask_conf[MLX5_HW_MAX_ACTS];
13984 : :
13985 : : RTE_SET_USED(action_flags);
13986 : : memset(masks, 0, sizeof(masks));
13987 : : memset(mask_conf, 0, sizeof(mask_conf));
13988 : : /* Only set the needed fields explicitly. */
13989 : 0 : struct mlx5_flow_workspace *wks = mlx5_flow_push_thread_workspace();
13990 : : struct rte_flow_template_table *table;
13991 : :
13992 : : /*
13993 : : * Notice All direct actions will be unmasked,
13994 : : * except for modify header and encap,
13995 : : * and therefore will be parsed as part of action construct.
13996 : : * Modify header is always shared in HWS,
13997 : : * encap is masked such that it will be treated as shared.
13998 : : * shared actions will be parsed as part of template translation
13999 : : * and not during action construct.
14000 : : */
14001 [ # # ]: 0 : if (!wks)
14002 : 0 : return rte_flow_error_set(error, ENOMEM,
14003 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14004 : : NULL,
14005 : : "failed to push flow workspace");
14006 : 0 : table = wks->table;
14007 : 0 : flow_nta_build_template_mask(actions, masks, mask_conf);
14008 : : /* The group in the attribute translation was done in advance. */
14009 : 0 : ret = __translate_group(dev, attr, external, attr->group, &src_group, error);
14010 [ # # ]: 0 : if (ret)
14011 : : return ret;
14012 [ # # ]: 0 : if (attr->transfer)
14013 : : table_type = MLX5DR_TABLE_TYPE_FDB;
14014 [ # # ]: 0 : else if (attr->egress)
14015 : : table_type = MLX5DR_TABLE_TYPE_NIC_TX;
14016 : : else
14017 : : table_type = MLX5DR_TABLE_TYPE_NIC_RX;
14018 : 0 : at = __flow_hw_actions_template_create(dev, &template_attr, actions, masks, true, error);
14019 [ # # ]: 0 : if (!at) {
14020 : 0 : ret = -rte_errno;
14021 : 0 : goto end;
14022 : : }
14023 : 0 : grp.group_id = src_group;
14024 : 0 : table->grp = &grp;
14025 : 0 : table->type = table_type;
14026 : 0 : table->cfg.external = external;
14027 : 0 : table->nb_action_templates = 1;
14028 : 0 : memcpy(&table->cfg.attr.flow_attr, attr, sizeof(*attr));
14029 : 0 : table->cfg.attr.flow_attr.group = src_group;
14030 : 0 : table->ats[0].action_template = at;
14031 : 0 : ret = __flow_hw_translate_actions_template(dev, &table->cfg, hw_acts, at,
14032 : : &table->mpctx, true, error);
14033 [ # # ]: 0 : if (ret)
14034 : 0 : goto end;
14035 : : /* handle bulk actions register. */
14036 : 0 : ret = flow_hw_encap_decap_resource_register(dev, table, hw_acts, flow, error);
14037 [ # # ]: 0 : if (ret)
14038 : 0 : goto end;
14039 : 0 : ret = flow_hw_modify_hdr_resource_register(dev, table, hw_acts, flow, error);
14040 [ # # ]: 0 : if (ret)
14041 : 0 : goto end;
14042 : 0 : table->ats[0].acts = *hw_acts;
14043 : 0 : ret = flow_hw_actions_construct(dev, flow, ap,
14044 : : &table->ats[0], item_flags, table,
14045 [ # # ]: 0 : actions, hw_acts->rule_acts, 0, error);
14046 [ # # ]: 0 : if (ret)
14047 : 0 : goto end;
14048 : 0 : goto end;
14049 : 0 : end:
14050 [ # # ]: 0 : if (ret)
14051 : : /* Make sure that there is no garbage in the actions. */
14052 : 0 : __flow_hw_action_template_destroy(dev, hw_acts);
14053 : : else
14054 : 0 : __flow_hw_act_data_flush(dev, hw_acts);
14055 [ # # ]: 0 : if (at)
14056 : 0 : mlx5_free(at);
14057 : 0 : mlx5_flow_pop_thread_workspace();
14058 : 0 : return ret;
14059 : : }
14060 : :
14061 : : static int
14062 : 0 : flow_hw_unregister_matcher(struct rte_eth_dev *dev,
14063 : : struct mlx5_flow_dv_matcher *matcher)
14064 : : {
14065 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14066 : 0 : struct mlx5_flow_group *group = matcher->group;
14067 : : int ret = 0;
14068 : :
14069 [ # # ]: 0 : if (group) {
14070 [ # # ]: 0 : if (matcher->matcher_object)
14071 : 0 : ret |= mlx5_list_unregister(group->matchers, &matcher->entry);
14072 : 0 : ret |= mlx5_hlist_unregister(priv->sh->groups, &group->entry);
14073 : : }
14074 : 0 : return ret;
14075 : : }
14076 : :
14077 : 0 : static int flow_hw_register_matcher(struct rte_eth_dev *dev,
14078 : : const struct rte_flow_attr *attr,
14079 : : const struct rte_flow_item items[],
14080 : : bool external,
14081 : : struct rte_flow_hw *flow,
14082 : : struct mlx5_flow_dv_matcher *matcher,
14083 : : struct rte_flow_error *error)
14084 : : {
14085 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14086 : 0 : struct rte_flow_error sub_error = {
14087 : : .type = RTE_FLOW_ERROR_TYPE_NONE,
14088 : : .cause = NULL,
14089 : : .message = NULL,
14090 : : };
14091 : 0 : struct rte_flow_attr flow_attr = *attr;
14092 : 0 : uint32_t specialize = 0; /* No unified FDB. */
14093 : 0 : struct mlx5_flow_cb_ctx ctx = {
14094 : : .dev = dev,
14095 : : .error = &sub_error,
14096 : : .data = &flow_attr,
14097 : : .data2 = &specialize,
14098 : : };
14099 : : void *items_ptr = &items;
14100 : 0 : struct mlx5_flow_cb_ctx matcher_ctx = {
14101 : : .error = &sub_error,
14102 : : .data = matcher,
14103 : : .data2 = items_ptr,
14104 : : };
14105 : : struct mlx5_list_entry *group_entry = NULL;
14106 : : struct mlx5_list_entry *matcher_entry = NULL;
14107 : : struct mlx5_flow_dv_matcher *resource;
14108 : : struct mlx5_list *matchers_list;
14109 : : struct mlx5_flow_group *flow_group;
14110 : : int ret;
14111 : :
14112 : :
14113 : 0 : matcher->crc = rte_raw_cksum((const void *)matcher->mask.buf,
14114 : : matcher->mask.size);
14115 : 0 : matcher->priority = attr->priority;
14116 : 0 : ret = __translate_group(dev, attr, external, attr->group, &flow_attr.group, error);
14117 [ # # ]: 0 : if (ret)
14118 : : return ret;
14119 : :
14120 : : /* Register the flow group. */
14121 : 0 : group_entry = mlx5_hlist_register(priv->sh->groups, flow_attr.group, &ctx);
14122 [ # # ]: 0 : if (!group_entry)
14123 : 0 : goto error;
14124 : : flow_group = container_of(group_entry, struct mlx5_flow_group, entry);
14125 : :
14126 : 0 : matchers_list = flow_group->matchers;
14127 : 0 : matcher->group = flow_group;
14128 : 0 : matcher_entry = mlx5_list_register(matchers_list, &matcher_ctx);
14129 [ # # ]: 0 : if (!matcher_entry)
14130 : 0 : goto error;
14131 : : resource = container_of(matcher_entry, typeof(*resource), entry);
14132 : 0 : flow->nt2hws->matcher = resource;
14133 : 0 : return 0;
14134 : :
14135 : 0 : error:
14136 [ # # ]: 0 : if (group_entry)
14137 : 0 : mlx5_hlist_unregister(priv->sh->groups, group_entry);
14138 [ # # ]: 0 : if (error) {
14139 [ # # ]: 0 : if (sub_error.type != RTE_FLOW_ERROR_TYPE_NONE)
14140 : : rte_memcpy(error, &sub_error, sizeof(sub_error));
14141 : : }
14142 : 0 : return rte_flow_error_set(error, rte_errno,
14143 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14144 : : NULL, "fail to register matcher");
14145 : : }
14146 : :
14147 : : static int
14148 : 0 : flow_hw_allocate_actions(struct rte_eth_dev *dev,
14149 : : uint64_t action_flags,
14150 : : struct rte_flow_error *error)
14151 : : {
14152 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14153 : : int ret;
14154 : : uint obj_num;
14155 : :
14156 : 0 : error->type = RTE_FLOW_ERROR_TYPE_NONE;
14157 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_AGE) {
14158 : : /* If no age objects were previously allocated. */
14159 [ # # ]: 0 : if (!priv->hws_age_req) {
14160 : : /* If no counters were previously allocated. */
14161 [ # # ]: 0 : if (!priv->hws_cpool) {
14162 : 0 : obj_num = MLX5_CNT_NT_MAX(priv);
14163 : 0 : ret = mlx5_hws_cnt_pool_create(dev, obj_num,
14164 : 0 : priv->nb_queue,
14165 : : NULL, error);
14166 [ # # ]: 0 : if (ret)
14167 : 0 : goto err;
14168 : : }
14169 : : /* Allocate same number of counters. */
14170 : 0 : ret = mlx5_hws_age_pool_init(dev, priv->hws_cpool->cfg.request_num,
14171 : 0 : priv->nb_queue, false);
14172 [ # # ]: 0 : if (ret)
14173 : 0 : goto err;
14174 : : }
14175 : : }
14176 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_COUNT) {
14177 : : /* If no counters were previously allocated. */
14178 [ # # ]: 0 : if (!priv->hws_cpool) {
14179 : 0 : obj_num = MLX5_CNT_NT_MAX(priv);
14180 : 0 : ret = mlx5_hws_cnt_pool_create(dev, obj_num,
14181 : 0 : priv->nb_queue, NULL,
14182 : : error);
14183 [ # # ]: 0 : if (ret)
14184 : 0 : goto err;
14185 : : }
14186 : : }
14187 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_CT) {
14188 : : /* If no CT were previously allocated. */
14189 [ # # ]: 0 : if (!priv->hws_ctpool) {
14190 : 0 : obj_num = MLX5_CT_NT_MAX(priv);
14191 : 0 : ret = mlx5_flow_ct_init(dev, obj_num, priv->nb_queue);
14192 [ # # ]: 0 : if (ret)
14193 : 0 : goto err;
14194 : : }
14195 : : }
14196 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_METER) {
14197 : : /* If no meters were previously allocated. */
14198 [ # # ]: 0 : if (!priv->hws_mpool) {
14199 : 0 : obj_num = MLX5_MTR_NT_MAX(priv);
14200 : 0 : ret = mlx5_flow_meter_init(dev, obj_num, 0, 0,
14201 : : priv->nb_queue);
14202 [ # # ]: 0 : if (ret)
14203 : 0 : goto err;
14204 : : }
14205 : : }
14206 : : return 0;
14207 : 0 : err:
14208 [ # # ]: 0 : if (ret && error->type != RTE_FLOW_ERROR_TYPE_NONE)
14209 : : return ret;
14210 : 0 : return rte_flow_error_set(error, ret,
14211 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14212 : : NULL, "fail to allocate actions");
14213 : : }
14214 : :
14215 : 0 : static int flow_hw_apply(const struct rte_flow_item items[],
14216 : : struct mlx5dr_rule_action rule_actions[],
14217 : : struct rte_flow_hw *flow,
14218 : : struct rte_flow_error *error)
14219 : : {
14220 : : struct mlx5dr_bwc_rule *rule = NULL;
14221 : :
14222 : 0 : rule = mlx5dr_bwc_rule_create((struct mlx5dr_bwc_matcher *)
14223 : 0 : flow->nt2hws->matcher->matcher_object,
14224 : : items, rule_actions);
14225 : 0 : flow->nt2hws->nt_rule = rule;
14226 [ # # ]: 0 : if (!rule) {
14227 : 0 : return rte_flow_error_set(error, EINVAL,
14228 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14229 : : NULL, "fail to create rte flow");
14230 : : }
14231 : : return 0;
14232 : : }
14233 : :
14234 : : #ifdef HAVE_MLX5_HWS_SUPPORT
14235 : : /**
14236 : : * Create a flow.
14237 : : *
14238 : : * @param[in] dev
14239 : : * Pointer to Ethernet device.
14240 : : * @param[in] type
14241 : : * Flow type.
14242 : : * @param[in] attr
14243 : : * Flow rule attributes.
14244 : : * @param[in] items
14245 : : * Pattern specification (list terminated by the END pattern item).
14246 : : * @param[in] actions
14247 : : * Associated actions (list terminated by the END action).
14248 : : * @param[in] external
14249 : : * This flow rule is created by request external to PMD.
14250 : : * @param[out] flow
14251 : : * Flow pointer
14252 : : * @param[out] error
14253 : : * Perform verbose error reporting if not NULL.
14254 : : *
14255 : : * @return
14256 : : * 0 on success, negative errno value otherwise and rte_errno set.
14257 : : */
14258 : : int
14259 : 0 : mlx5_flow_hw_create_flow(struct rte_eth_dev *dev, enum mlx5_flow_type type,
14260 : : const struct rte_flow_attr *attr,
14261 : : const struct rte_flow_item items[],
14262 : : const struct rte_flow_action actions[],
14263 : : uint64_t item_flags, uint64_t action_flags, bool external,
14264 : : struct rte_flow_hw **flow, struct rte_flow_error *error)
14265 : : {
14266 : : int ret;
14267 : 0 : struct mlx5_hw_actions hw_act = { { NULL } };
14268 : : struct mlx5_flow_hw_action_params ap;
14269 : 0 : struct mlx5_flow_dv_matcher matcher = {
14270 : : .mask = {
14271 : : .size = sizeof(matcher.mask.buf),
14272 : : },
14273 : : };
14274 : : uint32_t tbl_type;
14275 : :
14276 : 0 : struct mlx5_flow_attr flow_attr = {
14277 : 0 : .port_id = dev->data->port_id,
14278 : 0 : .group = attr->group,
14279 : 0 : .priority = attr->priority,
14280 : : .rss_level = 0,
14281 : : .act_flags = action_flags,
14282 : : .tbl_type = 0,
14283 : : };
14284 : :
14285 [ # # ]: 0 : if (attr->transfer)
14286 : : tbl_type = MLX5DR_TABLE_TYPE_FDB;
14287 [ # # ]: 0 : else if (attr->egress)
14288 : : tbl_type = MLX5DR_TABLE_TYPE_NIC_TX;
14289 : : else
14290 : : tbl_type = MLX5DR_TABLE_TYPE_NIC_RX;
14291 : 0 : flow_attr.tbl_type = tbl_type;
14292 : :
14293 : : /* Allocate needed memory. */
14294 : 0 : ret = flow_hw_prepare(dev, actions, type, flow, error);
14295 [ # # ]: 0 : if (ret)
14296 : 0 : goto error;
14297 : :
14298 : : /* TODO TBD flow_hw_handle_tunnel_offload(). */
14299 : 0 : (*flow)->nt_rule = true;
14300 : 0 : (*flow)->nt2hws->matcher = &matcher;
14301 : 0 : ret = mlx5_flow_dv_translate_items_hws_impl(items, &flow_attr, &matcher.mask.buf,
14302 : : MLX5_SET_MATCHER_HS_M, NULL,
14303 : : NULL, true, error);
14304 : :
14305 [ # # ]: 0 : if (ret)
14306 : 0 : goto error;
14307 : :
14308 [ # # # # ]: 0 : if (item_flags & MLX5_FLOW_LAYER_ECPRI && !mlx5_flex_parser_ecpri_exist(dev))
14309 [ # # ]: 0 : if (mlx5_flex_parser_ecpri_alloc(dev)) {
14310 : 0 : rte_flow_error_set(error, EIO,
14311 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14312 : : NULL,
14313 : : "failed to create Flex parser "
14314 : : "profile for ECPRI");
14315 : 0 : goto error;
14316 : : }
14317 : 0 : ret = flow_hw_register_matcher(dev, attr, items, external, *flow, &matcher, error);
14318 [ # # ]: 0 : if (ret) {
14319 [ # # ]: 0 : if (rte_errno == E2BIG)
14320 : 0 : rte_flow_error_set(error, E2BIG, RTE_FLOW_ERROR_TYPE_ITEM, NULL,
14321 : : "flow pattern is too big");
14322 : 0 : goto error;
14323 : : }
14324 : :
14325 : : /*
14326 : : * ASO allocation – iterating on actions list to allocate missing resources.
14327 : : * In the future when validate function in hws will be added,
14328 : : * The output actions bit mask instead of
14329 : : * looping on the actions array twice.
14330 : : */
14331 : 0 : ret = flow_hw_allocate_actions(dev, action_flags, error);
14332 [ # # ]: 0 : if (ret)
14333 : 0 : goto error;
14334 : :
14335 : : /* Note: the actions should be saved in the sub-flow rule itself for reference. */
14336 : 0 : ret = flow_hw_translate_flow_actions(dev, attr, actions, *flow, &ap, &hw_act,
14337 : : item_flags, action_flags, external, error);
14338 [ # # ]: 0 : if (ret)
14339 : 0 : goto error;
14340 : :
14341 : : /*
14342 : : * If the flow is external (from application) OR device is started,
14343 : : * OR mreg discover, then apply immediately.
14344 : : */
14345 [ # # # # ]: 0 : if (external || dev->data->dev_started ||
14346 [ # # ]: 0 : (attr->group == MLX5_FLOW_MREG_CP_TABLE_GROUP &&
14347 [ # # ]: 0 : attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR)) {
14348 : 0 : ret = flow_hw_apply(items, hw_act.rule_acts, *flow, error);
14349 [ # # ]: 0 : if (ret)
14350 : 0 : goto error;
14351 : : }
14352 : : ret = 0;
14353 : 0 : error:
14354 : : /*
14355 : : * Release memory allocated.
14356 : : * Cannot use __flow_hw_actions_release(dev, &hw_act);
14357 : : * since it destroys the actions as well.
14358 : : */
14359 [ # # ]: 0 : if (hw_act.encap_decap)
14360 : 0 : mlx5_free(hw_act.encap_decap);
14361 [ # # ]: 0 : if (hw_act.push_remove)
14362 : 0 : mlx5_free(hw_act.push_remove);
14363 [ # # ]: 0 : if (hw_act.mhdr)
14364 : 0 : mlx5_free(hw_act.mhdr);
14365 : 0 : return ret;
14366 : : }
14367 : : #endif
14368 : :
14369 : : void
14370 : 0 : mlx5_flow_hw_destroy(struct rte_eth_dev *dev, struct rte_flow_hw *flow)
14371 : : {
14372 : : int ret;
14373 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14374 : :
14375 [ # # # # ]: 0 : if (!flow || !flow->nt2hws)
14376 : : return;
14377 : :
14378 [ # # ]: 0 : if (flow->nt2hws->nt_rule) {
14379 : 0 : ret = mlx5dr_bwc_rule_destroy(flow->nt2hws->nt_rule);
14380 [ # # ]: 0 : if (ret)
14381 : 0 : DRV_LOG(ERR, "bwc rule destroy failed");
14382 : 0 : flow->nt2hws->nt_rule = NULL;
14383 : : }
14384 [ # # ]: 0 : flow->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_DESTROY;
14385 : : /* Notice this function does not handle shared/static actions. */
14386 : : hw_cmpl_flow_update_or_destroy(dev, flow, 0, NULL);
14387 : :
14388 : : /**
14389 : : * TODO: TBD - Release tunnel related memory allocations(mlx5_flow_tunnel_free)
14390 : : * – needed only if supporting tunnel offloads, notice update RX queue flags in SWS.
14391 : : */
14392 : :
14393 : : /**
14394 : : * Notice matcher destroy will take place when matcher's list is destroyed
14395 : : * , same as for DV.
14396 : : */
14397 [ # # ]: 0 : if (flow->nt2hws->flow_aux)
14398 : 0 : flow->nt2hws->flow_aux = NULL;
14399 [ # # ]: 0 : if (flow->nt2hws->rix_encap_decap) {
14400 : 0 : mlx5_flow_encap_decap_resource_release(dev, flow->nt2hws->rix_encap_decap);
14401 : 0 : flow->nt2hws->rix_encap_decap = 0;
14402 : : }
14403 [ # # ]: 0 : if (flow->nt2hws->modify_hdr) {
14404 : : MLX5_ASSERT(flow->nt2hws->modify_hdr->action);
14405 : 0 : mlx5_hlist_unregister(priv->sh->modify_cmds,
14406 : : &flow->nt2hws->modify_hdr->entry);
14407 : 0 : flow->nt2hws->modify_hdr = NULL;
14408 : : }
14409 [ # # ]: 0 : if (flow->nt2hws->matcher) {
14410 : 0 : flow_hw_unregister_matcher(dev, flow->nt2hws->matcher);
14411 : 0 : flow->nt2hws->matcher = NULL;
14412 : : }
14413 [ # # ]: 0 : if (flow->nt2hws->sample_release_ctx != NULL) {
14414 : 0 : mlx5_nta_sample_mirror_entry_release(dev, flow->nt2hws->sample_release_ctx);
14415 : 0 : flow->nt2hws->sample_release_ctx = NULL;
14416 : : }
14417 : : }
14418 : :
14419 : : #ifdef HAVE_MLX5_HWS_SUPPORT
14420 : : /**
14421 : : * Destroy a flow.
14422 : : *
14423 : : * @param[in] dev
14424 : : * Pointer to Ethernet device.
14425 : : * @param[in] type
14426 : : * Flow type.
14427 : : * @param[in] flow_addr
14428 : : * Address of flow to destroy.
14429 : : */
14430 : : void
14431 : 0 : mlx5_flow_hw_list_destroy(struct rte_eth_dev *dev, enum mlx5_flow_type type,
14432 : : uintptr_t flow_addr)
14433 : : {
14434 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14435 : 0 : struct rte_flow_hw *flow = (struct rte_flow_hw *)flow_addr;
14436 : : struct mlx5_nta_rss_flow_head head = { .slh_first = flow };
14437 : :
14438 [ # # # # : 0 : if (!flow || !flow->nt2hws || flow->nt2hws->chaned_flow)
# # ]
14439 : : return;
14440 : 0 : mlx5_flow_nta_del_copy_action(dev, flow->nt2hws->rix_mreg_copy);
14441 [ # # ]: 0 : while (!SLIST_EMPTY(&head)) {
14442 : : flow = SLIST_FIRST(&head);
14443 : 0 : SLIST_REMOVE_HEAD(&head, nt2hws->next);
14444 : 0 : mlx5_flow_hw_destroy(dev, flow);
14445 : : /* Release flow memory by idx */
14446 : 0 : mlx5_ipool_free(priv->flows[type], flow->idx);
14447 : : }
14448 : : }
14449 : : #endif
14450 : :
14451 : : /**
14452 : : * Create a flow.
14453 : : *
14454 : : * @param[in] dev
14455 : : * Pointer to Ethernet device.
14456 : : * @param[in] type
14457 : : * Flow type.
14458 : : * @param[in] attr
14459 : : * Flow rule attributes.
14460 : : * @param[in] items
14461 : : * Pattern specification (list terminated by the END pattern item).
14462 : : * @param[in] actions
14463 : : * Associated actions (list terminated by the END action).
14464 : : * @param[in] external
14465 : : * This flow rule is created by request external to PMD.
14466 : : * @param[out] error
14467 : : * Perform verbose error reporting if not NULL.
14468 : : *
14469 : : * @return
14470 : : * A flow addr on success, 0 otherwise and rte_errno is set.
14471 : : */
14472 : 0 : static uintptr_t flow_hw_list_create(struct rte_eth_dev *dev,
14473 : : enum mlx5_flow_type type,
14474 : : const struct rte_flow_attr *attr,
14475 : : const struct rte_flow_item items[],
14476 : : const struct rte_flow_action actions[],
14477 : : bool external,
14478 : : struct rte_flow_error *error)
14479 : : {
14480 : : int ret;
14481 : : int split;
14482 : : int encap_idx;
14483 : 0 : uint32_t cpy_idx = 0;
14484 : 0 : int actions_n = 0;
14485 : 0 : struct rte_flow_hw *flow = NULL;
14486 : 0 : struct rte_flow_hw *prfx_flow = NULL;
14487 : 0 : const struct rte_flow_action *qrss = NULL;
14488 : 0 : const struct rte_flow_action *mark = NULL;
14489 : 0 : uint64_t action_flags = mlx5_flow_hw_action_flags_get(actions, &qrss, &mark,
14490 : : &encap_idx, &actions_n, error);
14491 : 0 : struct mlx5_flow_hw_split_resource resource = {
14492 : : .suffix = {
14493 : : .attr = attr,
14494 : : .items = items,
14495 : : .actions = actions,
14496 : : },
14497 : : };
14498 : 0 : struct rte_flow_error shadow_error = {0, };
14499 : 0 : const struct rte_flow_pattern_template_attr pattern_template_attr = {
14500 : : .relaxed_matching = 0,
14501 : 0 : .ingress = attr->ingress,
14502 : 0 : .egress = attr->egress,
14503 : 0 : .transfer = attr->transfer,
14504 : : };
14505 : 0 : struct rte_flow_item *copied_items = NULL;
14506 : : const struct rte_flow_item *prepend_items;
14507 : : uint64_t orig_item_nb, item_flags;
14508 : :
14509 : : RTE_SET_USED(encap_idx);
14510 [ # # ]: 0 : if (!error)
14511 : : error = &shadow_error;
14512 : :
14513 : 0 : prepend_items = flow_hw_adjust_pattern(dev, &pattern_template_attr, true, items,
14514 : : &item_flags, &orig_item_nb, &copied_items, error);
14515 [ # # ]: 0 : if (!prepend_items)
14516 : : return 0;
14517 : :
14518 : 0 : split = mlx5_flow_nta_split_metadata(dev, attr, actions, qrss, action_flags,
14519 : : actions_n, external, &resource, error);
14520 [ # # ]: 0 : if (split < 0) {
14521 : 0 : mlx5_free(copied_items);
14522 : 0 : return 0;
14523 [ # # ]: 0 : } else if (!split) {
14524 : 0 : resource.suffix.items = prepend_items;
14525 : : }
14526 : :
14527 : : /* Update the metadata copy table - MLX5_FLOW_MREG_CP_TABLE_GROUP */
14528 [ # # # # : 0 : if (((attr->ingress && attr->group != MLX5_FLOW_MREG_CP_TABLE_GROUP) ||
# # ]
14529 [ # # ]: 0 : attr->transfer) && external) {
14530 : 0 : ret = mlx5_flow_nta_update_copy_table(dev, &cpy_idx, mark,
14531 : : action_flags, error);
14532 [ # # ]: 0 : if (ret)
14533 : 0 : goto free;
14534 : : }
14535 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
14536 : 0 : flow = mlx5_nta_sample_flow_list_create(dev, type, attr, prepend_items, actions,
14537 : : item_flags, action_flags, error);
14538 [ # # ]: 0 : if (flow != NULL) {
14539 : 0 : mlx5_free(copied_items);
14540 : 0 : return (uintptr_t)flow;
14541 : : }
14542 : 0 : goto free;
14543 : : }
14544 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_RSS) {
14545 : : const struct rte_flow_action_rss
14546 : 0 : *rss_conf = mlx5_flow_nta_locate_rss(dev, actions, error);
14547 : 0 : flow = mlx5_flow_nta_handle_rss(dev, attr, prepend_items, actions, rss_conf,
14548 : : item_flags, action_flags, external, type, error);
14549 [ # # ]: 0 : if (flow) {
14550 : 0 : flow->nt2hws->rix_mreg_copy = cpy_idx;
14551 : 0 : cpy_idx = 0;
14552 [ # # ]: 0 : if (!split) {
14553 : 0 : mlx5_free(copied_items);
14554 : 0 : return (uintptr_t)flow;
14555 : : }
14556 : 0 : goto prefix_flow;
14557 : : }
14558 : 0 : goto free;
14559 : : }
14560 : : /* Create single flow. */
14561 : 0 : ret = mlx5_flow_hw_create_flow(dev, type, resource.suffix.attr, resource.suffix.items,
14562 : : resource.suffix.actions, item_flags, action_flags,
14563 : : external, &flow, error);
14564 [ # # ]: 0 : if (ret)
14565 : 0 : goto free;
14566 [ # # ]: 0 : if (flow) {
14567 : 0 : flow->nt2hws->rix_mreg_copy = cpy_idx;
14568 : 0 : cpy_idx = 0;
14569 [ # # ]: 0 : if (!split) {
14570 : 0 : mlx5_free(copied_items);
14571 : 0 : return (uintptr_t)flow;
14572 : : }
14573 : : /* Fall Through to prefix flow creation. */
14574 : : }
14575 : 0 : prefix_flow:
14576 : 0 : ret = mlx5_flow_hw_create_flow(dev, type, attr, prepend_items, resource.prefix.actions,
14577 : : item_flags, action_flags, external, &prfx_flow, error);
14578 [ # # ]: 0 : if (ret)
14579 : 0 : goto free;
14580 [ # # ]: 0 : if (prfx_flow) {
14581 : 0 : prfx_flow->nt2hws->rix_mreg_copy = flow->nt2hws->rix_mreg_copy;
14582 : 0 : flow->nt2hws->chaned_flow = 1;
14583 : 0 : SLIST_INSERT_AFTER(prfx_flow, flow, nt2hws->next);
14584 : 0 : mlx5_flow_nta_split_resource_free(dev, &resource);
14585 : 0 : mlx5_free(copied_items);
14586 : 0 : return (uintptr_t)prfx_flow;
14587 : : }
14588 : 0 : free:
14589 [ # # ]: 0 : if (prfx_flow)
14590 : 0 : mlx5_flow_hw_list_destroy(dev, type, (uintptr_t)prfx_flow);
14591 [ # # ]: 0 : if (flow)
14592 : 0 : mlx5_flow_hw_list_destroy(dev, type, (uintptr_t)flow);
14593 [ # # ]: 0 : if (cpy_idx)
14594 : 0 : mlx5_flow_nta_del_copy_action(dev, cpy_idx);
14595 [ # # ]: 0 : if (split > 0)
14596 : 0 : mlx5_flow_nta_split_resource_free(dev, &resource);
14597 : 0 : mlx5_free(copied_items);
14598 : 0 : return 0;
14599 : : }
14600 : :
14601 : : static void
14602 : 0 : mlx5_mirror_destroy_clone(struct rte_eth_dev *dev,
14603 : : struct mlx5_mirror_clone *clone)
14604 : : {
14605 [ # # # ]: 0 : switch (clone->type) {
14606 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
14607 : : case RTE_FLOW_ACTION_TYPE_QUEUE:
14608 : 0 : mlx5_hrxq_release(dev,
14609 : 0 : ((struct mlx5_hrxq *)(clone->action_ctx))->idx);
14610 : 0 : break;
14611 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP:
14612 : 0 : flow_hw_jump_release(dev, clone->action_ctx);
14613 : : break;
14614 : : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
14615 : : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
14616 : : case RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:
14617 : : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
14618 : : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
14619 : : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
14620 : : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
14621 : : default:
14622 : : break;
14623 : : }
14624 : 0 : }
14625 : :
14626 : : void
14627 [ # # ]: 0 : mlx5_hw_mirror_destroy(struct rte_eth_dev *dev, struct mlx5_mirror *mirror)
14628 : : {
14629 : : uint32_t i;
14630 : :
14631 : : mlx5_indirect_list_remove_entry(&mirror->indirect);
14632 [ # # ]: 0 : for (i = 0; i < mirror->clones_num; i++)
14633 : 0 : mlx5_mirror_destroy_clone(dev, &mirror->clone[i]);
14634 [ # # ]: 0 : if (mirror->mirror_action)
14635 : 0 : mlx5dr_action_destroy(mirror->mirror_action);
14636 : 0 : mlx5_free(mirror);
14637 : 0 : }
14638 : :
14639 : : static __rte_always_inline bool
14640 : : mlx5_mirror_terminal_action(const struct rte_flow_action *action)
14641 : : {
14642 : 0 : switch (action->type) {
14643 : : case RTE_FLOW_ACTION_TYPE_JUMP:
14644 : : case RTE_FLOW_ACTION_TYPE_RSS:
14645 : : case RTE_FLOW_ACTION_TYPE_QUEUE:
14646 : : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
14647 : : case RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:
14648 : : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
14649 : : case RTE_FLOW_ACTION_TYPE_DROP:
14650 : : return true;
14651 : : default:
14652 : : break;
14653 : : }
14654 : : return false;
14655 : : }
14656 : :
14657 : : static bool
14658 : 0 : mlx5_mirror_validate_sample_action(struct rte_eth_dev *dev,
14659 : : const struct rte_flow_attr *flow_attr,
14660 : : const struct rte_flow_action *action)
14661 : : {
14662 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14663 : : const struct rte_flow_action_ethdev *port = NULL;
14664 [ # # # # ]: 0 : bool is_proxy = MLX5_HW_PORT_IS_PROXY(priv);
14665 : :
14666 [ # # ]: 0 : if (!action)
14667 : : return false;
14668 [ # # # # : 0 : switch (action->type) {
# ]
14669 : 0 : case RTE_FLOW_ACTION_TYPE_QUEUE:
14670 : : case RTE_FLOW_ACTION_TYPE_RSS:
14671 [ # # ]: 0 : if (flow_attr->transfer)
14672 : : return false;
14673 : : break;
14674 : 0 : case RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:
14675 [ # # # # ]: 0 : if (!is_proxy || !flow_attr->transfer)
14676 : : return false;
14677 : 0 : port = action->conf;
14678 [ # # # # ]: 0 : if (!port || port->port_id != MLX5_REPRESENTED_PORT_ESW_MGR)
14679 : : return false;
14680 : : break;
14681 : 0 : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
14682 : : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
14683 : : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
14684 : : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
14685 : : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
14686 [ # # # # ]: 0 : if (!is_proxy || !flow_attr->transfer)
14687 : : return false;
14688 [ # # ]: 0 : if (action[0].type == RTE_FLOW_ACTION_TYPE_RAW_DECAP &&
14689 [ # # ]: 0 : action[1].type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP)
14690 : : return false;
14691 : : break;
14692 : : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
14693 : : case RTE_FLOW_ACTION_TYPE_JUMP:
14694 : : case RTE_FLOW_ACTION_TYPE_DROP:
14695 : : break;
14696 : : default:
14697 : : return false;
14698 : : }
14699 : 0 : return true;
14700 : : }
14701 : :
14702 : : /**
14703 : : * Valid mirror actions list includes one or two SAMPLE actions
14704 : : * followed by JUMP.
14705 : : *
14706 : : * @return
14707 : : * Number of mirrors *action* list was valid.
14708 : : * -EINVAL otherwise.
14709 : : */
14710 : : static int
14711 : 0 : mlx5_hw_mirror_actions_list_validate(struct rte_eth_dev *dev,
14712 : : const struct rte_flow_attr *flow_attr,
14713 : : const struct rte_flow_action *actions)
14714 : : {
14715 [ # # ]: 0 : if (actions[0].type == RTE_FLOW_ACTION_TYPE_SAMPLE) {
14716 : : int i = 1;
14717 : : bool valid;
14718 : 0 : const struct rte_flow_action_sample *sample = actions[0].conf;
14719 : 0 : valid = mlx5_mirror_validate_sample_action(dev, flow_attr,
14720 : 0 : sample->actions);
14721 [ # # ]: 0 : if (!valid)
14722 : : return -EINVAL;
14723 [ # # ]: 0 : if (actions[1].type == RTE_FLOW_ACTION_TYPE_SAMPLE) {
14724 : : i = 2;
14725 : 0 : sample = actions[1].conf;
14726 : 0 : valid = mlx5_mirror_validate_sample_action(dev, flow_attr,
14727 : 0 : sample->actions);
14728 [ # # ]: 0 : if (!valid)
14729 : : return -EINVAL;
14730 : : }
14731 [ # # ]: 0 : return mlx5_mirror_terminal_action(actions + i) ? i + 1 : -EINVAL;
14732 : : }
14733 : : return -EINVAL;
14734 : : }
14735 : :
14736 : : static int
14737 : 0 : mirror_format_tir(struct rte_eth_dev *dev,
14738 : : struct mlx5_mirror_clone *clone,
14739 : : const struct mlx5_flow_template_table_cfg *table_cfg,
14740 : : const struct rte_flow_action *action,
14741 : : struct mlx5dr_action_dest_attr *dest_attr,
14742 : : struct rte_flow_error *error)
14743 : : {
14744 : : uint32_t hws_flags;
14745 : : enum mlx5dr_table_type table_type;
14746 : : struct mlx5_hrxq *tir_ctx;
14747 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14748 : : bool unified_fdb = is_unified_fdb(priv);
14749 : :
14750 : 0 : table_type = get_mlx5dr_table_type(&table_cfg->attr.flow_attr, table_cfg->attr.specialize,
14751 : : unified_fdb);
14752 : 0 : hws_flags = mlx5_hw_act_flag[MLX5_HW_ACTION_FLAG_NONE_ROOT][table_type];
14753 : 0 : tir_ctx = flow_hw_tir_action_register(dev, hws_flags, action);
14754 [ # # ]: 0 : if (!tir_ctx)
14755 : 0 : return rte_flow_error_set(error, EINVAL,
14756 : : RTE_FLOW_ERROR_TYPE_ACTION,
14757 : : action, "failed to create QUEUE action for mirror clone");
14758 : 0 : dest_attr->dest = tir_ctx->action;
14759 : 0 : clone->action_ctx = tir_ctx;
14760 : 0 : return 0;
14761 : : }
14762 : :
14763 : : static int
14764 : 0 : mirror_format_jump(struct rte_eth_dev *dev,
14765 : : struct mlx5_mirror_clone *clone,
14766 : : const struct mlx5_flow_template_table_cfg *table_cfg,
14767 : : const struct rte_flow_action *action,
14768 : : struct mlx5dr_action_dest_attr *dest_attr,
14769 : : struct rte_flow_error *error)
14770 : : {
14771 : 0 : const struct rte_flow_action_jump *jump_conf = action->conf;
14772 : 0 : struct mlx5_hw_jump_action *jump = flow_hw_jump_action_register
14773 : : (dev, table_cfg,
14774 : 0 : jump_conf->group, error);
14775 : :
14776 [ # # ]: 0 : if (!jump)
14777 : 0 : return rte_flow_error_set(error, EINVAL,
14778 : : RTE_FLOW_ERROR_TYPE_ACTION,
14779 : : action, "failed to create JUMP action for mirror clone");
14780 : 0 : dest_attr->dest = jump->hws_action;
14781 : 0 : clone->action_ctx = jump;
14782 : 0 : return 0;
14783 : : }
14784 : :
14785 : : static int
14786 : : mirror_format_port(struct rte_eth_dev *dev,
14787 : : const struct rte_flow_action *action,
14788 : : struct mlx5dr_action_dest_attr *dest_attr,
14789 : : struct rte_flow_error __rte_unused *error)
14790 : : {
14791 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14792 : 0 : const struct rte_flow_action_ethdev *port_action = action->conf;
14793 : :
14794 : 0 : dest_attr->dest = priv->hw_vport[port_action->port_id];
14795 : : return 0;
14796 : : }
14797 : :
14798 : : static int
14799 : 0 : hw_mirror_clone_reformat(const struct rte_flow_action *actions,
14800 : : struct mlx5dr_action_dest_attr *dest_attr,
14801 : : enum mlx5dr_action_type *action_type,
14802 : : uint8_t *reformat_buf, bool decap)
14803 : : {
14804 : : int ret;
14805 : : const struct rte_flow_item *encap_item = NULL;
14806 : : const struct rte_flow_action_raw_encap *encap_conf = NULL;
14807 : : typeof(dest_attr->reformat) *reformat = &dest_attr->reformat;
14808 : :
14809 [ # # # # ]: 0 : switch (actions[0].type) {
14810 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
14811 : 0 : encap_conf = actions[0].conf;
14812 : 0 : break;
14813 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
14814 : 0 : encap_item = MLX5_CONST_ENCAP_ITEM(rte_flow_action_vxlan_encap,
14815 : : actions);
14816 : 0 : break;
14817 : 0 : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
14818 : 0 : encap_item = MLX5_CONST_ENCAP_ITEM(rte_flow_action_nvgre_encap,
14819 : : actions);
14820 : 0 : break;
14821 : : default:
14822 : : return -EINVAL;
14823 : : }
14824 : 0 : *action_type = decap ?
14825 [ # # ]: 0 : MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3 :
14826 : : MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;
14827 [ # # ]: 0 : if (encap_item) {
14828 : 0 : ret = mlx5_flow_dv_convert_encap_data(encap_item, reformat_buf,
14829 : : &reformat->reformat_data_sz, NULL);
14830 [ # # ]: 0 : if (ret)
14831 : : return -EINVAL;
14832 : 0 : reformat->reformat_data = reformat_buf;
14833 : : } else {
14834 : 0 : reformat->reformat_data = (void *)(uintptr_t)encap_conf->data;
14835 : 0 : reformat->reformat_data_sz = encap_conf->size;
14836 : : }
14837 : : return 0;
14838 : : }
14839 : :
14840 : : static int
14841 : 0 : hw_mirror_format_clone(struct rte_eth_dev *dev,
14842 : : struct mlx5_mirror_clone *clone,
14843 : : const struct mlx5_flow_template_table_cfg *table_cfg,
14844 : : const struct rte_flow_action *actions,
14845 : : struct mlx5dr_action_dest_attr *dest_attr,
14846 : : uint8_t *reformat_buf,
14847 : : enum mlx5dr_table_type table_type,
14848 : : struct rte_flow_error *error)
14849 : : {
14850 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14851 : : int ret;
14852 : : uint32_t i;
14853 : : bool decap_seen = false;
14854 : :
14855 [ # # ]: 0 : for (i = 0; actions[i].type != RTE_FLOW_ACTION_TYPE_END; i++) {
14856 : 0 : dest_attr->action_type[i] = mlx5_hw_dr_action_types[actions[i].type];
14857 [ # # # # : 0 : switch (actions[i].type) {
# # # # ]
14858 : 0 : case RTE_FLOW_ACTION_TYPE_QUEUE:
14859 : : case RTE_FLOW_ACTION_TYPE_RSS:
14860 : 0 : ret = mirror_format_tir(dev, clone, table_cfg,
14861 : : &actions[i], dest_attr, error);
14862 [ # # ]: 0 : if (ret)
14863 : 0 : return ret;
14864 : : break;
14865 : 0 : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
14866 : : ret = mirror_format_port(dev, &actions[i],
14867 : : dest_attr, error);
14868 : : if (ret)
14869 : : return ret;
14870 : : break;
14871 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP:
14872 : 0 : ret = mirror_format_jump(dev, clone, table_cfg,
14873 : : &actions[i], dest_attr, error);
14874 [ # # ]: 0 : if (ret)
14875 : 0 : return ret;
14876 : : break;
14877 : 0 : case RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:
14878 : 0 : dest_attr->dest = mlx5_hws_global_action_def_miss_get(priv,
14879 : : table_type,
14880 : : false);
14881 [ # # ]: 0 : if (dest_attr->dest == NULL)
14882 : 0 : return rte_flow_error_set(error, ENOMEM,
14883 : : RTE_FLOW_ERROR_TYPE_STATE, NULL,
14884 : : "failed to allocate port representor action");
14885 : : break;
14886 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
14887 : : decap_seen = true;
14888 : 0 : break;
14889 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
14890 : : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
14891 : : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
14892 : 0 : ret = hw_mirror_clone_reformat(&actions[i], dest_attr,
14893 : : &dest_attr->action_type[i],
14894 : : reformat_buf, decap_seen);
14895 [ # # ]: 0 : if (ret < 0)
14896 : 0 : return rte_flow_error_set(error, EINVAL,
14897 : : RTE_FLOW_ERROR_TYPE_ACTION,
14898 : : &actions[i],
14899 : : "failed to create reformat action");
14900 : : break;
14901 : : case RTE_FLOW_ACTION_TYPE_DROP:
14902 : : break;
14903 : 0 : default:
14904 : 0 : return rte_flow_error_set(error, EINVAL,
14905 : : RTE_FLOW_ERROR_TYPE_ACTION,
14906 : : &actions[i], "unsupported sample action");
14907 : : }
14908 : 0 : clone->type = actions->type;
14909 : : }
14910 : 0 : dest_attr->action_type[i] = MLX5DR_ACTION_TYP_LAST;
14911 : 0 : return 0;
14912 : : }
14913 : :
14914 : : struct mlx5_mirror *
14915 : 0 : mlx5_hw_create_mirror(struct rte_eth_dev *dev,
14916 : : const struct mlx5_flow_template_table_cfg *table_cfg,
14917 : : const struct rte_flow_action *actions,
14918 : : struct rte_flow_error *error)
14919 : : {
14920 : : uint32_t hws_flags;
14921 : : int ret = 0, i, clones_num;
14922 : : struct mlx5_mirror *mirror;
14923 : : enum mlx5dr_table_type table_type;
14924 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
14925 : : bool unified_fdb = is_unified_fdb(priv);
14926 [ # # ]: 0 : const struct rte_flow_attr *flow_attr = &table_cfg->attr.flow_attr;
14927 : : uint8_t reformat_buf[MLX5_MIRROR_MAX_CLONES_NUM][MLX5_ENCAP_MAX_LEN];
14928 : : struct mlx5dr_action_dest_attr mirror_attr[MLX5_MIRROR_MAX_CLONES_NUM + 1];
14929 : : enum mlx5dr_action_type array_action_types[MLX5_MIRROR_MAX_CLONES_NUM + 1]
14930 : : [MLX5_MIRROR_MAX_SAMPLE_ACTIONS_LEN + 1];
14931 : :
14932 : : memset(mirror_attr, 0, sizeof(mirror_attr));
14933 : : memset(array_action_types, 0, sizeof(array_action_types));
14934 : 0 : table_type = get_mlx5dr_table_type(flow_attr, table_cfg->attr.specialize, unified_fdb);
14935 : 0 : hws_flags = mlx5_hw_act_flag[MLX5_HW_ACTION_FLAG_NONE_ROOT][table_type];
14936 : 0 : clones_num = mlx5_hw_mirror_actions_list_validate(dev, flow_attr,
14937 : : actions);
14938 [ # # ]: 0 : if (clones_num < 0) {
14939 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14940 : : actions, "Invalid mirror list format");
14941 : 0 : return NULL;
14942 : : }
14943 : 0 : mirror = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mirror),
14944 : : 0, SOCKET_ID_ANY);
14945 [ # # ]: 0 : if (!mirror) {
14946 : 0 : rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_ACTION,
14947 : : actions, "Failed to allocate mirror context");
14948 : 0 : return NULL;
14949 : : }
14950 : :
14951 : 0 : mirror->indirect.type = MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR;
14952 : 0 : mirror->clones_num = clones_num;
14953 [ # # ]: 0 : for (i = 0; i < clones_num; i++) {
14954 : : const struct rte_flow_action *clone_actions;
14955 : :
14956 : 0 : mirror_attr[i].action_type = array_action_types[i];
14957 [ # # ]: 0 : if (actions[i].type == RTE_FLOW_ACTION_TYPE_SAMPLE) {
14958 : 0 : const struct rte_flow_action_sample *sample = actions[i].conf;
14959 : :
14960 : 0 : clone_actions = sample->actions;
14961 : : } else {
14962 : : clone_actions = &actions[i];
14963 : : }
14964 : 0 : ret = hw_mirror_format_clone(dev, &mirror->clone[i], table_cfg,
14965 : : clone_actions, &mirror_attr[i],
14966 : 0 : reformat_buf[i], table_type, error);
14967 : :
14968 [ # # ]: 0 : if (ret)
14969 : 0 : goto error;
14970 : : }
14971 : 0 : hws_flags |= MLX5DR_ACTION_FLAG_SHARED;
14972 : 0 : mirror->mirror_action = mlx5dr_action_create_dest_array(priv->dr_ctx,
14973 : : clones_num,
14974 : : mirror_attr,
14975 : : hws_flags);
14976 [ # # ]: 0 : if (!mirror->mirror_action) {
14977 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14978 : : actions, "Failed to create HWS mirror action");
14979 : 0 : goto error;
14980 : : }
14981 : : return mirror;
14982 : 0 : error:
14983 : 0 : mlx5_hw_mirror_destroy(dev, mirror);
14984 : 0 : return NULL;
14985 : : }
14986 : :
14987 : : static struct rte_flow_action_list_handle *
14988 : 0 : mlx5_hw_mirror_handle_create(struct rte_eth_dev *dev,
14989 : : const struct mlx5_flow_template_table_cfg *table_cfg,
14990 : : const struct rte_flow_action *actions,
14991 : : struct rte_flow_error *error)
14992 : : {
14993 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14994 : 0 : struct mlx5_mirror *mirror = mlx5_hw_create_mirror(dev, table_cfg, actions, error);
14995 : :
14996 [ # # ]: 0 : if (mirror)
14997 [ # # ]: 0 : mlx5_indirect_list_add_entry(&priv->indirect_list_head, &mirror->indirect);
14998 : 0 : return (struct rte_flow_action_list_handle *)mirror;
14999 : : }
15000 : :
15001 : : void
15002 : 0 : mlx5_destroy_legacy_indirect(__rte_unused struct rte_eth_dev *dev,
15003 : : struct mlx5_indirect_list *ptr)
15004 : : {
15005 : : struct mlx5_indlst_legacy *obj = (typeof(obj))ptr;
15006 : :
15007 : : switch (obj->legacy_type) {
15008 : : case RTE_FLOW_ACTION_TYPE_METER_MARK:
15009 : : break; /* ASO meters were released in mlx5_flow_meter_flush() */
15010 : : default:
15011 : : break;
15012 : : }
15013 : 0 : mlx5_free(obj);
15014 : 0 : }
15015 : :
15016 : : static struct rte_flow_action_list_handle *
15017 : 0 : mlx5_create_legacy_indlst(struct rte_eth_dev *dev, uint32_t queue,
15018 : : const struct rte_flow_op_attr *attr,
15019 : : const struct rte_flow_indir_action_conf *conf,
15020 : : const struct rte_flow_action *actions,
15021 : : void *user_data, struct rte_flow_error *error)
15022 : : {
15023 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
15024 : 0 : struct mlx5_indlst_legacy *indlst_obj = mlx5_malloc(MLX5_MEM_ZERO,
15025 : : sizeof(*indlst_obj),
15026 : : 0, SOCKET_ID_ANY);
15027 : :
15028 [ # # ]: 0 : if (!indlst_obj)
15029 : : return NULL;
15030 : 0 : indlst_obj->handle = flow_hw_action_handle_create(dev, queue, attr, conf,
15031 : : actions, user_data,
15032 : : error);
15033 [ # # ]: 0 : if (!indlst_obj->handle) {
15034 : 0 : mlx5_free(indlst_obj);
15035 : 0 : return NULL;
15036 : : }
15037 : 0 : indlst_obj->legacy_type = actions[0].type;
15038 : 0 : indlst_obj->indirect.type = MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY;
15039 [ # # ]: 0 : mlx5_indirect_list_add_entry(&priv->indirect_list_head, &indlst_obj->indirect);
15040 : 0 : return (struct rte_flow_action_list_handle *)indlst_obj;
15041 : : }
15042 : :
15043 : : static __rte_always_inline enum mlx5_indirect_list_type
15044 : : flow_hw_inlist_type_get(const struct rte_flow_action *actions)
15045 : : {
15046 [ # # # # ]: 0 : switch (actions[0].type) {
15047 : : case RTE_FLOW_ACTION_TYPE_SAMPLE:
15048 : : return MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR;
15049 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
15050 : 0 : return actions[1].type == RTE_FLOW_ACTION_TYPE_END ?
15051 : 0 : MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY :
15052 : : MLX5_INDIRECT_ACTION_LIST_TYPE_ERR;
15053 : : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
15054 : : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
15055 : : return MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT;
15056 : : default:
15057 : : break;
15058 : : }
15059 : : return MLX5_INDIRECT_ACTION_LIST_TYPE_ERR;
15060 : : }
15061 : :
15062 : : static struct rte_flow_action_list_handle*
15063 : 0 : mlx5_hw_decap_encap_handle_create(struct rte_eth_dev *dev,
15064 : : const struct mlx5_flow_template_table_cfg *table_cfg,
15065 : : const struct rte_flow_action *actions,
15066 : : struct rte_flow_error *error)
15067 : : {
15068 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
15069 : : const struct rte_flow_attr *flow_attr = &table_cfg->attr.flow_attr;
15070 : : const struct rte_flow_action *encap = NULL;
15071 : : const struct rte_flow_action *decap = NULL;
15072 : 0 : struct rte_flow_indir_action_conf indirect_conf = {
15073 : 0 : .ingress = flow_attr->ingress,
15074 : 0 : .egress = flow_attr->egress,
15075 : 0 : .transfer = flow_attr->transfer,
15076 : : };
15077 : : struct mlx5_hw_encap_decap_action *handle;
15078 : : uint64_t action_flags = 0;
15079 : :
15080 : : /*
15081 : : * Allow
15082 : : * 1. raw_decap / raw_encap / end
15083 : : * 2. raw_encap / end
15084 : : * 3. raw_decap / end
15085 : : */
15086 [ # # ]: 0 : while (actions->type != RTE_FLOW_ACTION_TYPE_END) {
15087 [ # # ]: 0 : if (actions->type == RTE_FLOW_ACTION_TYPE_RAW_DECAP) {
15088 [ # # ]: 0 : if (action_flags) {
15089 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
15090 : : actions, "Invalid indirect action list sequence");
15091 : 0 : return NULL;
15092 : : }
15093 : : action_flags |= MLX5_FLOW_ACTION_DECAP;
15094 : : decap = actions;
15095 [ # # ]: 0 : } else if (actions->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
15096 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_ENCAP) {
15097 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
15098 : : actions, "Invalid indirect action list sequence");
15099 : 0 : return NULL;
15100 : : }
15101 : 0 : action_flags |= MLX5_FLOW_ACTION_ENCAP;
15102 : : encap = actions;
15103 : : } else {
15104 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
15105 : : actions, "Invalid indirect action type in list");
15106 : 0 : return NULL;
15107 : : }
15108 : 0 : actions++;
15109 : : }
15110 [ # # ]: 0 : if (!decap && !encap) {
15111 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
15112 : : actions, "Invalid indirect action combinations");
15113 : 0 : return NULL;
15114 : : }
15115 : 0 : handle = mlx5_reformat_action_create(dev, &indirect_conf, encap, decap, error);
15116 [ # # ]: 0 : if (!handle) {
15117 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
15118 : : actions, "Failed to create HWS decap_encap action");
15119 : 0 : return NULL;
15120 : : }
15121 : 0 : handle->indirect.type = MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT;
15122 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->indirect_list_head, &handle->indirect, entry);
15123 : 0 : return (struct rte_flow_action_list_handle *)handle;
15124 : : }
15125 : :
15126 : : static struct rte_flow_action_list_handle *
15127 [ # # ]: 0 : flow_hw_async_action_list_handle_create(struct rte_eth_dev *dev, uint32_t queue,
15128 : : const struct rte_flow_op_attr *attr,
15129 : : const struct rte_flow_indir_action_conf *conf,
15130 : : const struct rte_flow_action *actions,
15131 : : void *user_data,
15132 : : struct rte_flow_error *error)
15133 : : {
15134 : : struct mlx5_hw_q_job *job = NULL;
15135 : : bool push = flow_hw_action_push(attr);
15136 : : enum mlx5_indirect_list_type list_type;
15137 : : struct rte_flow_action_list_handle *handle;
15138 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
15139 : 0 : struct mlx5_flow_template_table_cfg table_cfg = {
15140 : : .external = true,
15141 : : .attr = {
15142 : : .flow_attr = {
15143 : 0 : .ingress = conf->ingress,
15144 : 0 : .egress = conf->egress,
15145 : 0 : .transfer = conf->transfer
15146 : : }
15147 : : }
15148 : : };
15149 : :
15150 [ # # ]: 0 : if (!mlx5_hw_ctx_validate(dev, error))
15151 : : return NULL;
15152 [ # # ]: 0 : if (!actions) {
15153 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
15154 : : NULL, "No action list");
15155 : 0 : return NULL;
15156 : : }
15157 : : list_type = flow_hw_inlist_type_get(actions);
15158 [ # # ]: 0 : if (list_type == MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY) {
15159 : : /*
15160 : : * Legacy indirect actions already have
15161 : : * async resources management. No need to do it twice.
15162 : : */
15163 : 0 : handle = mlx5_create_legacy_indlst(dev, queue, attr, conf,
15164 : : actions, user_data, error);
15165 : 0 : goto end;
15166 : : }
15167 [ # # ]: 0 : if (attr) {
15168 : : job = flow_hw_action_job_init(priv, queue, NULL, user_data,
15169 : : NULL, MLX5_HW_Q_JOB_TYPE_CREATE,
15170 : : MLX5_HW_INDIRECT_TYPE_LIST, error);
15171 : : if (!job)
15172 : 0 : return NULL;
15173 : : }
15174 [ # # # ]: 0 : switch (list_type) {
15175 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR:
15176 : : /*
15177 : : * Mirror action is only supported in HWS group. Setting group to
15178 : : * non-zero will ensure that the action resources are allocated correctly.
15179 : : */
15180 : 0 : table_cfg.attr.flow_attr.group = 1;
15181 : 0 : handle = mlx5_hw_mirror_handle_create(dev, &table_cfg,
15182 : : actions, error);
15183 : 0 : break;
15184 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT:
15185 : 0 : handle = mlx5_hw_decap_encap_handle_create(dev, &table_cfg,
15186 : : actions, error);
15187 : 0 : break;
15188 : 0 : default:
15189 : : handle = NULL;
15190 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
15191 : : actions, "Invalid list");
15192 : : }
15193 [ # # ]: 0 : if (job) {
15194 : 0 : job->action = handle;
15195 [ # # ]: 0 : flow_hw_action_finalize(dev, queue, job, push, false,
15196 : : handle != NULL);
15197 : : }
15198 : 0 : end:
15199 : : return handle;
15200 : : }
15201 : :
15202 : : static struct rte_flow_action_list_handle *
15203 : 0 : flow_hw_action_list_handle_create(struct rte_eth_dev *dev,
15204 : : const struct rte_flow_indir_action_conf *conf,
15205 : : const struct rte_flow_action *actions,
15206 : : struct rte_flow_error *error)
15207 : : {
15208 : 0 : return flow_hw_async_action_list_handle_create(dev, MLX5_HW_INV_QUEUE,
15209 : : NULL, conf, actions,
15210 : : NULL, error);
15211 : : }
15212 : :
15213 : : static int
15214 [ # # ]: 0 : flow_hw_async_action_list_handle_destroy
15215 : : (struct rte_eth_dev *dev, uint32_t queue,
15216 : : const struct rte_flow_op_attr *attr,
15217 : : struct rte_flow_action_list_handle *handle,
15218 : : void *user_data, struct rte_flow_error *error)
15219 : : {
15220 : : int ret = 0;
15221 : : struct mlx5_hw_q_job *job = NULL;
15222 : : bool push = flow_hw_action_push(attr);
15223 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
15224 : : enum mlx5_indirect_list_type type =
15225 : : mlx5_get_indirect_list_type((void *)handle);
15226 : :
15227 [ # # ]: 0 : if (type == MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY) {
15228 : : struct mlx5_indlst_legacy *legacy = (typeof(legacy))handle;
15229 : :
15230 : 0 : ret = flow_hw_action_handle_destroy(dev, queue, attr,
15231 : : legacy->handle,
15232 : : user_data, error);
15233 : : mlx5_indirect_list_remove_entry(&legacy->indirect);
15234 : 0 : mlx5_free(legacy);
15235 : 0 : goto end;
15236 : : }
15237 [ # # ]: 0 : if (attr) {
15238 : : job = flow_hw_action_job_init(priv, queue, NULL, user_data,
15239 : : NULL, MLX5_HW_Q_JOB_TYPE_DESTROY,
15240 : : MLX5_HW_INDIRECT_TYPE_LIST, error);
15241 : : if (!job)
15242 : 0 : return rte_errno;
15243 : : }
15244 [ # # # ]: 0 : switch (type) {
15245 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR:
15246 : 0 : mlx5_hw_mirror_destroy(dev, (struct mlx5_mirror *)handle);
15247 : 0 : break;
15248 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT:
15249 [ # # ]: 0 : LIST_REMOVE(&((struct mlx5_hw_encap_decap_action *)handle)->indirect,
15250 : : entry);
15251 : 0 : mlx5_reformat_action_destroy(dev, handle, error);
15252 : 0 : break;
15253 : 0 : default:
15254 : 0 : ret = rte_flow_error_set(error, EINVAL,
15255 : : RTE_FLOW_ERROR_TYPE_ACTION,
15256 : : NULL, "Invalid indirect list handle");
15257 : : }
15258 [ # # ]: 0 : if (job) {
15259 : : flow_hw_action_finalize(dev, queue, job, push, false, true);
15260 : : }
15261 : 0 : end:
15262 : : return ret;
15263 : : }
15264 : :
15265 : : static int
15266 : 0 : flow_hw_action_list_handle_destroy(struct rte_eth_dev *dev,
15267 : : struct rte_flow_action_list_handle *handle,
15268 : : struct rte_flow_error *error)
15269 : : {
15270 : 0 : return flow_hw_async_action_list_handle_destroy(dev, MLX5_HW_INV_QUEUE,
15271 : : NULL, handle, NULL,
15272 : : error);
15273 : : }
15274 : :
15275 : : static int
15276 [ # # ]: 0 : flow_hw_async_action_list_handle_query_update
15277 : : (struct rte_eth_dev *dev, uint32_t queue_id,
15278 : : const struct rte_flow_op_attr *attr,
15279 : : const struct rte_flow_action_list_handle *handle,
15280 : : const void **update, void **query,
15281 : : enum rte_flow_query_update_mode mode,
15282 : : void *user_data, struct rte_flow_error *error)
15283 : : {
15284 : : enum mlx5_indirect_list_type type =
15285 : : mlx5_get_indirect_list_type((const void *)handle);
15286 : :
15287 [ # # ]: 0 : if (type == MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY) {
15288 : : struct mlx5_indlst_legacy *legacy = (void *)(uintptr_t)handle;
15289 : :
15290 [ # # ]: 0 : if (update && query)
15291 : 0 : return flow_hw_async_action_handle_query_update
15292 : : (dev, queue_id, attr, legacy->handle,
15293 : : update, query, mode, user_data, error);
15294 [ # # # # ]: 0 : else if (update && update[0])
15295 : 0 : return flow_hw_action_handle_update(dev, queue_id, attr,
15296 : : legacy->handle, update[0],
15297 : : user_data, error);
15298 [ # # # # ]: 0 : else if (query && query[0])
15299 : 0 : return flow_hw_action_handle_query(dev, queue_id, attr,
15300 : 0 : legacy->handle, query[0],
15301 : : user_data, error);
15302 : : else
15303 : 0 : return rte_flow_error_set(error, EINVAL,
15304 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15305 : : NULL, "invalid legacy handle query_update parameters");
15306 : : }
15307 : : return -ENOTSUP;
15308 : : }
15309 : :
15310 : : static int
15311 : 0 : flow_hw_action_list_handle_query_update(struct rte_eth_dev *dev,
15312 : : const struct rte_flow_action_list_handle *handle,
15313 : : const void **update, void **query,
15314 : : enum rte_flow_query_update_mode mode,
15315 : : struct rte_flow_error *error)
15316 : : {
15317 : 0 : return flow_hw_async_action_list_handle_query_update
15318 : : (dev, MLX5_HW_INV_QUEUE, NULL, handle,
15319 : : update, query, mode, NULL, error);
15320 : : }
15321 : :
15322 : : static int
15323 : 0 : flow_hw_calc_table_hash(struct rte_eth_dev *dev,
15324 : : const struct rte_flow_template_table *table,
15325 : : const struct rte_flow_item pattern[],
15326 : : uint8_t pattern_template_index,
15327 : : uint32_t *hash, struct rte_flow_error *error)
15328 : : {
15329 : : const struct rte_flow_item *items;
15330 : : struct mlx5_flow_hw_pattern_params pp;
15331 : : int res;
15332 : :
15333 : 0 : items = flow_hw_get_rule_items(dev, table, pattern,
15334 : : pattern_template_index,
15335 : : &pp);
15336 : 0 : res = mlx5dr_rule_hash_calculate(mlx5_table_matcher(table), items,
15337 : : pattern_template_index,
15338 : : MLX5DR_RULE_HASH_CALC_MODE_RAW,
15339 : : hash);
15340 [ # # ]: 0 : if (res)
15341 : 0 : return rte_flow_error_set(error, res,
15342 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15343 : : NULL,
15344 : : "hash could not be calculated");
15345 : : return 0;
15346 : : }
15347 : :
15348 : : static int
15349 : 0 : flow_hw_calc_encap_hash(struct rte_eth_dev *dev,
15350 : : const struct rte_flow_item pattern[],
15351 : : enum rte_flow_encap_hash_field dest_field,
15352 : : uint8_t *hash,
15353 : : struct rte_flow_error *error)
15354 : : {
15355 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
15356 : : struct mlx5dr_crc_encap_entropy_hash_fields data;
15357 : 0 : enum mlx5dr_crc_encap_entropy_hash_size res_size =
15358 : : dest_field == RTE_FLOW_ENCAP_HASH_FIELD_SRC_PORT ?
15359 : 0 : MLX5DR_CRC_ENCAP_ENTROPY_HASH_SIZE_16 :
15360 : : MLX5DR_CRC_ENCAP_ENTROPY_HASH_SIZE_8;
15361 : : int res;
15362 : :
15363 : : memset(&data, 0, sizeof(struct mlx5dr_crc_encap_entropy_hash_fields));
15364 : :
15365 [ # # ]: 0 : for (; pattern->type != RTE_FLOW_ITEM_TYPE_END; pattern++) {
15366 [ # # # # : 0 : switch (pattern->type) {
# # # # ]
15367 : 0 : case RTE_FLOW_ITEM_TYPE_IPV4:
15368 : 0 : data.dst.ipv4_addr =
15369 : 0 : ((const struct rte_flow_item_ipv4 *)(pattern->spec))->hdr.dst_addr;
15370 : 0 : data.src.ipv4_addr =
15371 : 0 : ((const struct rte_flow_item_ipv4 *)(pattern->spec))->hdr.src_addr;
15372 : 0 : data.next_protocol = ((const struct rte_flow_item_ipv4 *)
15373 : 0 : (pattern->spec))->hdr.next_proto_id;
15374 : 0 : break;
15375 : 0 : case RTE_FLOW_ITEM_TYPE_IPV6:
15376 : : memcpy(data.dst.ipv6_addr,
15377 : 0 : &((const struct rte_flow_item_ipv6 *)(pattern->spec))->hdr.dst_addr,
15378 : : sizeof(data.dst.ipv6_addr));
15379 : : memcpy(data.src.ipv6_addr,
15380 : : &((const struct rte_flow_item_ipv6 *)(pattern->spec))->hdr.src_addr,
15381 : : sizeof(data.src.ipv6_addr));
15382 : 0 : data.next_protocol = ((const struct rte_flow_item_ipv6 *)
15383 : 0 : (pattern->spec))->hdr.proto;
15384 : 0 : break;
15385 : 0 : case RTE_FLOW_ITEM_TYPE_UDP:
15386 : 0 : data.next_protocol = IPPROTO_UDP;
15387 : 0 : data.dst_port =
15388 : 0 : ((const struct rte_flow_item_udp *)(pattern->spec))->hdr.dst_port;
15389 : 0 : data.src_port =
15390 : 0 : ((const struct rte_flow_item_udp *)(pattern->spec))->hdr.src_port;
15391 : 0 : break;
15392 : 0 : case RTE_FLOW_ITEM_TYPE_TCP:
15393 : 0 : data.next_protocol = IPPROTO_TCP;
15394 : 0 : data.dst_port =
15395 : 0 : ((const struct rte_flow_item_tcp *)(pattern->spec))->hdr.dst_port;
15396 : 0 : data.src_port =
15397 : 0 : ((const struct rte_flow_item_tcp *)(pattern->spec))->hdr.src_port;
15398 : 0 : break;
15399 : 0 : case RTE_FLOW_ITEM_TYPE_ICMP:
15400 : 0 : data.next_protocol = IPPROTO_ICMP;
15401 : 0 : break;
15402 : 0 : case RTE_FLOW_ITEM_TYPE_ICMP6:
15403 : 0 : data.next_protocol = IPPROTO_ICMPV6;
15404 : 0 : break;
15405 : 0 : case RTE_FLOW_ITEM_TYPE_GRE:
15406 : 0 : data.next_protocol = IPPROTO_GRE;
15407 : 0 : break;
15408 : : default:
15409 : : break;
15410 : : }
15411 : : }
15412 : 0 : res = mlx5dr_crc_encap_entropy_hash_calc(priv->dr_ctx, &data, hash, res_size);
15413 [ # # ]: 0 : if (res)
15414 : 0 : return rte_flow_error_set(error, res,
15415 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15416 : : NULL, "error while calculating encap hash");
15417 : : return 0;
15418 : : }
15419 : :
15420 : : static int
15421 : 0 : flow_hw_table_resize_multi_pattern_actions(struct rte_eth_dev *dev,
15422 : : struct rte_flow_template_table *table,
15423 : : uint32_t nb_flows,
15424 : : struct rte_flow_error *error)
15425 : : {
15426 : 0 : struct mlx5_multi_pattern_segment *segment = table->mpctx.segments;
15427 : : uint32_t bulk_size;
15428 : : int i, ret;
15429 : :
15430 : : /**
15431 : : * Segment always allocates Modify Header Argument Objects number in
15432 : : * powers of 2.
15433 : : * On resize, PMD adds minimal required argument objects number.
15434 : : * For example, if table size was 10, it allocated 16 argument objects.
15435 : : * Resize to 15 will not add new objects.
15436 : : */
15437 : 0 : for (i = 1;
15438 [ # # # # ]: 0 : i < MLX5_MAX_TABLE_RESIZE_NUM && segment->capacity;
15439 : 0 : i++, segment++) {
15440 : : /* keep the devtools/checkpatches.sh happy */
15441 : : }
15442 [ # # ]: 0 : if (i == MLX5_MAX_TABLE_RESIZE_NUM)
15443 : 0 : return rte_flow_error_set(error, EINVAL,
15444 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15445 : : table, "too many resizes");
15446 [ # # ]: 0 : if (segment->head_index - 1 >= nb_flows)
15447 : : return 0;
15448 [ # # ]: 0 : bulk_size = rte_align32pow2(nb_flows - segment->head_index + 1);
15449 : 0 : ret = mlx5_tbl_multi_pattern_process(dev, table, segment,
15450 : : rte_log2_u32(bulk_size),
15451 : : error);
15452 [ # # ]: 0 : if (ret)
15453 : 0 : return rte_flow_error_set(error, EINVAL,
15454 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15455 : : table, "too many resizes");
15456 : : return i;
15457 : : }
15458 : :
15459 : : static int
15460 : 0 : flow_hw_table_resize(struct rte_eth_dev *dev,
15461 : : struct rte_flow_template_table *table,
15462 : : uint32_t nb_flows,
15463 : : struct rte_flow_error *error)
15464 : : {
15465 : : struct mlx5dr_action_template *at[MLX5_HW_TBL_MAX_ACTION_TEMPLATE];
15466 : : struct mlx5dr_match_template *mt[MLX5_HW_TBL_MAX_ITEM_TEMPLATE];
15467 : 0 : struct mlx5dr_matcher_attr matcher_attr = table->matcher_attr;
15468 : 0 : struct mlx5dr_action_jump_to_matcher_attr jump_attr = {
15469 : : .type = MLX5DR_ACTION_JUMP_TO_MATCHER_BY_INDEX,
15470 : : .matcher = NULL,
15471 : : };
15472 : : struct mlx5_multi_pattern_segment *segment = NULL;
15473 : : struct mlx5dr_matcher *matcher = NULL;
15474 : : struct mlx5dr_action *jump = NULL;
15475 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
15476 : 0 : uint32_t i, selector = table->matcher_selector;
15477 : 0 : uint32_t other_selector = (selector + 1) & 1;
15478 : : int ret;
15479 : :
15480 [ # # ]: 0 : if (!rte_flow_template_table_resizable(dev->data->port_id, &table->cfg.attr))
15481 : 0 : return rte_flow_error_set(error, EINVAL,
15482 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15483 : : table, "no resizable attribute");
15484 [ # # ]: 0 : if (table->matcher_info[other_selector].matcher)
15485 : 0 : return rte_flow_error_set(error, EINVAL,
15486 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15487 : : table, "last table resize was not completed");
15488 [ # # ]: 0 : if (nb_flows <= table->cfg.attr.nb_flows)
15489 : 0 : return rte_flow_error_set(error, EINVAL,
15490 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15491 : : table, "shrinking table is not supported");
15492 : 0 : ret = mlx5_ipool_resize(table->flow_pool, nb_flows, error);
15493 [ # # ]: 0 : if (ret)
15494 : : return ret;
15495 : : /*
15496 : : * A resizable matcher doesn't support rule update. In this case, the ipool
15497 : : * for the resource is not created and there is no need to resize it.
15498 : : */
15499 : : MLX5_ASSERT(!table->resource);
15500 [ # # ]: 0 : if (mlx5_is_multi_pattern_active(&table->mpctx)) {
15501 : 0 : ret = flow_hw_table_resize_multi_pattern_actions(dev, table, nb_flows, error);
15502 [ # # ]: 0 : if (ret < 0)
15503 : : return ret;
15504 [ # # ]: 0 : if (ret > 0)
15505 : 0 : segment = table->mpctx.segments + ret;
15506 : : }
15507 [ # # ]: 0 : for (i = 0; i < table->nb_item_templates; i++)
15508 : 0 : mt[i] = table->its[i]->mt;
15509 [ # # ]: 0 : for (i = 0; i < table->nb_action_templates; i++)
15510 : 0 : at[i] = table->ats[i].action_template->tmpl;
15511 : : nb_flows = rte_align32pow2(nb_flows);
15512 : 0 : matcher_attr.rule.num_log = rte_log2_u32(nb_flows);
15513 : 0 : matcher = mlx5dr_matcher_create(table->grp->tbl, mt,
15514 : : table->nb_item_templates, at,
15515 : : table->nb_action_templates,
15516 : : &matcher_attr);
15517 [ # # ]: 0 : if (!matcher) {
15518 : 0 : ret = rte_flow_error_set(error, rte_errno,
15519 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15520 : : table, "failed to create new matcher");
15521 : 0 : goto error;
15522 : : }
15523 [ # # ]: 0 : if (matcher_attr.isolated) {
15524 : 0 : jump_attr.matcher = matcher;
15525 : 0 : jump = mlx5dr_action_create_jump_to_matcher(priv->dr_ctx, &jump_attr,
15526 : 0 : mlx5_hw_act_flag[!!table->cfg.attr.flow_attr.group][table->type]);
15527 [ # # ]: 0 : if (!jump) {
15528 : 0 : ret = rte_flow_error_set(error, rte_errno,
15529 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15530 : : table, "failed to create jump to matcher action");
15531 : 0 : goto error;
15532 : : }
15533 : : }
15534 : 0 : rte_rwlock_write_lock(&table->matcher_replace_rwlk);
15535 : 0 : ret = mlx5dr_matcher_resize_set_target
15536 : : (table->matcher_info[selector].matcher, matcher);
15537 [ # # ]: 0 : if (ret) {
15538 : : rte_rwlock_write_unlock(&table->matcher_replace_rwlk);
15539 : 0 : ret = rte_flow_error_set(error, rte_errno,
15540 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15541 : : table, "failed to initiate matcher swap");
15542 : 0 : goto error;
15543 : : }
15544 : 0 : table->cfg.attr.nb_flows = nb_flows;
15545 : 0 : table->matcher_info[other_selector].matcher = matcher;
15546 : 0 : table->matcher_info[other_selector].jump = jump;
15547 : 0 : table->matcher_selector = other_selector;
15548 : 0 : rte_atomic_store_explicit(&table->matcher_info[other_selector].refcnt,
15549 : : 0, rte_memory_order_relaxed);
15550 : : rte_rwlock_write_unlock(&table->matcher_replace_rwlk);
15551 : 0 : return 0;
15552 : 0 : error:
15553 [ # # ]: 0 : if (segment)
15554 : 0 : mlx5_destroy_multi_pattern_segment(segment);
15555 [ # # ]: 0 : if (jump)
15556 : 0 : mlx5dr_action_destroy(jump);
15557 [ # # ]: 0 : if (matcher) {
15558 : 0 : ret = mlx5dr_matcher_destroy(matcher);
15559 : 0 : return rte_flow_error_set(error, rte_errno,
15560 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15561 : : table, "failed to destroy new matcher");
15562 : : }
15563 : : return ret;
15564 : : }
15565 : :
15566 : : static int
15567 : 0 : flow_hw_table_resize_complete(struct rte_eth_dev *dev,
15568 : : struct rte_flow_template_table *table,
15569 : : struct rte_flow_error *error)
15570 : : {
15571 : : int ret;
15572 : 0 : uint32_t selector = table->matcher_selector;
15573 : 0 : uint32_t other_selector = (selector + 1) & 1;
15574 : : struct mlx5_matcher_info *matcher_info = &table->matcher_info[other_selector];
15575 : : uint32_t matcher_refcnt;
15576 : :
15577 [ # # ]: 0 : if (!rte_flow_template_table_resizable(dev->data->port_id, &table->cfg.attr))
15578 : 0 : return rte_flow_error_set(error, EINVAL,
15579 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15580 : : table, "no resizable attribute");
15581 [ # # ]: 0 : if (matcher_info->matcher == NULL)
15582 : 0 : return rte_flow_error_set(error, EINVAL,
15583 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15584 : : table, "table resize was not started");
15585 : 0 : matcher_refcnt = rte_atomic_load_explicit(&matcher_info->refcnt,
15586 : : rte_memory_order_relaxed);
15587 [ # # ]: 0 : if (matcher_refcnt > 0)
15588 : 0 : return rte_flow_error_set(error, EBUSY,
15589 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15590 : : table, "all rules not yet updated");
15591 [ # # ]: 0 : if (matcher_info->jump)
15592 : 0 : mlx5dr_action_destroy(matcher_info->jump);
15593 : 0 : ret = mlx5dr_matcher_destroy(matcher_info->matcher);
15594 [ # # ]: 0 : if (ret)
15595 : 0 : return rte_flow_error_set(error, rte_errno,
15596 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15597 : : table, "failed to destroy retired matcher");
15598 : 0 : matcher_info->matcher = NULL;
15599 : 0 : return 0;
15600 : : }
15601 : :
15602 : : static int
15603 : 0 : flow_hw_update_resized(struct rte_eth_dev *dev, uint32_t queue,
15604 : : const struct rte_flow_op_attr *attr,
15605 : : struct rte_flow *flow, void *user_data,
15606 : : struct rte_flow_error *error)
15607 : : {
15608 : : int ret;
15609 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
15610 : : struct rte_flow_hw *hw_flow = (struct rte_flow_hw *)flow;
15611 : 0 : struct rte_flow_template_table *table = hw_flow->table;
15612 [ # # ]: 0 : struct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(dev->data->port_id, hw_flow);
15613 : 0 : uint32_t table_selector = table->matcher_selector;
15614 : 0 : uint32_t rule_selector = aux->matcher_selector;
15615 : : uint32_t other_selector;
15616 : : struct mlx5dr_matcher *other_matcher;
15617 : 0 : struct mlx5dr_rule_attr rule_attr = {
15618 : : .queue_id = queue,
15619 : 0 : .burst = attr->postpone,
15620 : : };
15621 : :
15622 : : MLX5_ASSERT(hw_flow->flags & MLX5_FLOW_HW_FLOW_FLAG_MATCHER_SELECTOR);
15623 : : /*
15624 : : * Update resized can be called only through async flow API.
15625 : : * These rings are allocated if and only if async flow API was configured.
15626 : : */
15627 : : MLX5_ASSERT(priv->hw_q[queue].flow_transfer_completed != NULL);
15628 : : MLX5_ASSERT(priv->hw_q[queue].flow_transfer_pending != NULL);
15629 : : /**
15630 : : * mlx5dr_matcher_resize_rule_move() accepts original table matcher -
15631 : : * the one that was used BEFORE table resize.
15632 : : * Since the function is called AFTER table resize,
15633 : : * `table->matcher_selector` always points to the new matcher and
15634 : : * `aux->matcher_selector` points to a matcher used to create the flow.
15635 : : */
15636 : : other_selector = rule_selector == table_selector ?
15637 [ # # ]: 0 : (rule_selector + 1) & 1 : rule_selector;
15638 : 0 : other_matcher = table->matcher_info[other_selector].matcher;
15639 [ # # ]: 0 : if (!other_matcher)
15640 : 0 : return rte_flow_error_set(error, EINVAL,
15641 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
15642 : : "no active table resize");
15643 : 0 : hw_flow->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_MOVE;
15644 : 0 : hw_flow->user_data = user_data;
15645 : 0 : rule_attr.user_data = hw_flow;
15646 [ # # ]: 0 : if (rule_selector == table_selector) {
15647 : 0 : struct rte_ring *ring = !attr->postpone ?
15648 [ # # ]: 0 : priv->hw_q[queue].flow_transfer_completed :
15649 : 0 : priv->hw_q[queue].flow_transfer_pending;
15650 : 0 : rte_ring_enqueue(ring, hw_flow);
15651 : : flow_hw_q_inc_flow_ops(priv, queue);
15652 : 0 : return 0;
15653 : : }
15654 : 0 : ret = mlx5dr_matcher_resize_rule_move(other_matcher,
15655 : 0 : (struct mlx5dr_rule *)hw_flow->rule,
15656 : : &rule_attr);
15657 [ # # ]: 0 : if (ret) {
15658 : 0 : return rte_flow_error_set(error, rte_errno,
15659 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
15660 : : "flow transfer failed");
15661 : : }
15662 : : flow_hw_q_inc_flow_ops(priv, queue);
15663 : 0 : return 0;
15664 : : }
15665 : :
15666 : : /**
15667 : : * Internal validation function. For validating both actions and items.
15668 : : *
15669 : : * @param[in] dev
15670 : : * Pointer to the rte_eth_dev structure.
15671 : : * @param[in] attr
15672 : : * Pointer to the flow attributes.
15673 : : * @param[in] items
15674 : : * Pointer to the list of items.
15675 : : * @param[in] actions
15676 : : * Pointer to the list of actions.
15677 : : * @param[in] external
15678 : : * This flow rule is created by request external to PMD.
15679 : : * @param[in] hairpin
15680 : : * Number of hairpin TX actions, 0 means classic flow.
15681 : : * @param[out] error
15682 : : * Pointer to the error structure.
15683 : : *
15684 : : * @return
15685 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
15686 : : */
15687 : : static int
15688 : 0 : flow_hw_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
15689 : : const struct rte_flow_item items[],
15690 : : const struct rte_flow_action actions[] __rte_unused,
15691 : : bool external, int hairpin __rte_unused,
15692 : : struct rte_flow_error *error)
15693 : : {
15694 : 0 : const struct rte_flow_pattern_template_attr pattern_template_attr = {
15695 : : .relaxed_matching = 0,
15696 : 0 : .ingress = attr->ingress,
15697 : 0 : .egress = attr->egress,
15698 : 0 : .transfer = attr->transfer,
15699 : : };
15700 : 0 : uint64_t item_flags = 0;
15701 : : int ret = 0;
15702 : :
15703 [ # # ]: 0 : if (external) {
15704 : : /* Validate application items only */
15705 : 0 : ret = __flow_hw_pattern_validate(dev, &pattern_template_attr, items,
15706 : : &item_flags, true, error);
15707 [ # # ]: 0 : if (ret < 0)
15708 : 0 : return -rte_errno;
15709 : : }
15710 : : return 0;
15711 : : }
15712 : :
15713 : :
15714 : : const struct mlx5_flow_driver_ops mlx5_flow_hw_drv_ops = {
15715 : : .list_create = flow_hw_list_create,
15716 : : .list_destroy = mlx5_flow_hw_list_destroy,
15717 : : .validate = flow_hw_validate,
15718 : : .info_get = flow_hw_info_get,
15719 : : .configure = flow_hw_configure,
15720 : : .pattern_validate = flow_hw_pattern_validate,
15721 : : .pattern_template_create = flow_hw_external_pattern_template_create,
15722 : : .pattern_template_destroy = flow_hw_pattern_template_destroy,
15723 : : .actions_validate = flow_hw_actions_validate,
15724 : : .actions_template_create = flow_hw_actions_template_create,
15725 : : .actions_template_destroy = flow_hw_actions_template_destroy,
15726 : : .template_table_create = flow_hw_template_table_create,
15727 : : .template_table_destroy = flow_hw_table_destroy,
15728 : : .table_resize = flow_hw_table_resize,
15729 : : .group_set_miss_actions = mlx5_flow_hw_group_set_miss_actions,
15730 : : .async_flow_create = flow_hw_async_flow_create,
15731 : : .async_flow_create_by_index = flow_hw_async_flow_create_by_index,
15732 : : .async_flow_update = flow_hw_async_flow_update,
15733 : : .async_flow_destroy = flow_hw_async_flow_destroy,
15734 : : .flow_update_resized = flow_hw_update_resized,
15735 : : .table_resize_complete = flow_hw_table_resize_complete,
15736 : : .pull = flow_hw_pull,
15737 : : .push = flow_hw_push,
15738 : : .async_action_create = flow_hw_action_handle_create,
15739 : : .async_action_destroy = flow_hw_action_handle_destroy,
15740 : : .async_action_update = flow_hw_action_handle_update,
15741 : : .async_action_query_update = flow_hw_async_action_handle_query_update,
15742 : : .async_action_query = flow_hw_action_handle_query,
15743 : : .action_validate = flow_hw_action_validate,
15744 : : .action_create = flow_hw_action_create,
15745 : : .action_destroy = flow_hw_action_destroy,
15746 : : .action_update = flow_hw_action_update,
15747 : : .action_query = flow_hw_action_query,
15748 : : .action_query_update = flow_hw_action_query_update,
15749 : : .action_list_handle_create = flow_hw_action_list_handle_create,
15750 : : .action_list_handle_destroy = flow_hw_action_list_handle_destroy,
15751 : : .action_list_handle_query_update =
15752 : : flow_hw_action_list_handle_query_update,
15753 : : .async_action_list_handle_create =
15754 : : flow_hw_async_action_list_handle_create,
15755 : : .async_action_list_handle_destroy =
15756 : : flow_hw_async_action_list_handle_destroy,
15757 : : .async_action_list_handle_query_update =
15758 : : flow_hw_async_action_list_handle_query_update,
15759 : : .query = flow_hw_query,
15760 : : .get_aged_flows = flow_hw_get_aged_flows,
15761 : : .get_q_aged_flows = flow_hw_get_q_aged_flows,
15762 : : .item_create = mlx5_flow_dv_item_create,
15763 : : .item_release = mlx5_flow_dv_item_release,
15764 : : .flow_calc_table_hash = flow_hw_calc_table_hash,
15765 : : .flow_calc_encap_hash = flow_hw_calc_encap_hash,
15766 : : };
15767 : :
15768 : : /**
15769 : : * Creates a control flow using flow template API on @p proxy_dev device,
15770 : : * on behalf of @p owner_dev device.
15771 : : *
15772 : : * This function uses locks internally to synchronize access to the
15773 : : * flow queue.
15774 : : *
15775 : : * Created flow is stored in private list associated with @p proxy_dev device.
15776 : : *
15777 : : * @param owner_dev
15778 : : * Pointer to Ethernet device on behalf of which flow is created.
15779 : : * @param proxy_dev
15780 : : * Pointer to Ethernet device on which flow is created.
15781 : : * @param table
15782 : : * Pointer to flow table.
15783 : : * @param items
15784 : : * Pointer to flow rule items.
15785 : : * @param item_template_idx
15786 : : * Index of an item template associated with @p table.
15787 : : * @param actions
15788 : : * Pointer to flow rule actions.
15789 : : * @param action_template_idx
15790 : : * Index of an action template associated with @p table.
15791 : : * @param info
15792 : : * Additional info about control flow rule.
15793 : : * @param external
15794 : : * External ctrl flow.
15795 : : *
15796 : : * @return
15797 : : * 0 on success, negative errno value otherwise and rte_errno set.
15798 : : */
15799 : : static __rte_unused int
15800 : 0 : flow_hw_create_ctrl_flow(struct rte_eth_dev *owner_dev,
15801 : : struct rte_eth_dev *proxy_dev,
15802 : : struct rte_flow_template_table *table,
15803 : : struct rte_flow_item items[],
15804 : : uint8_t item_template_idx,
15805 : : struct rte_flow_action actions[],
15806 : : uint8_t action_template_idx,
15807 : : struct mlx5_ctrl_flow_info *info,
15808 : : bool external)
15809 : : {
15810 : 0 : struct mlx5_priv *priv = proxy_dev->data->dev_private;
15811 : 0 : uint32_t queue = CTRL_QUEUE_ID(priv);
15812 : 0 : struct rte_flow_op_attr op_attr = {
15813 : : .postpone = 0,
15814 : : };
15815 : : struct rte_flow *flow = NULL;
15816 : : struct mlx5_ctrl_flow_entry *entry = NULL;
15817 : : int ret;
15818 : :
15819 : 0 : rte_spinlock_lock(&priv->hw_ctrl_lock);
15820 : 0 : entry = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_SYS, sizeof(*entry),
15821 : : 0, SOCKET_ID_ANY);
15822 [ # # ]: 0 : if (!entry) {
15823 : 0 : DRV_LOG(ERR, "port %u not enough memory to create control flows",
15824 : : proxy_dev->data->port_id);
15825 : 0 : rte_errno = ENOMEM;
15826 : : ret = -rte_errno;
15827 : 0 : goto error;
15828 : : }
15829 : 0 : flow = flow_hw_async_flow_create(proxy_dev, queue, &op_attr, table,
15830 : : items, item_template_idx,
15831 : : actions, action_template_idx,
15832 : : NULL, NULL);
15833 [ # # ]: 0 : if (!flow) {
15834 : 0 : DRV_LOG(ERR, "port %u failed to enqueue create control"
15835 : : " flow operation", proxy_dev->data->port_id);
15836 : 0 : ret = -rte_errno;
15837 : 0 : goto error;
15838 : : }
15839 : 0 : ret = __flow_hw_pull_comp(proxy_dev, queue, NULL);
15840 [ # # ]: 0 : if (ret) {
15841 : 0 : DRV_LOG(ERR, "port %u failed to insert control flow",
15842 : : proxy_dev->data->port_id);
15843 : 0 : rte_errno = EINVAL;
15844 : : ret = -rte_errno;
15845 : 0 : goto error;
15846 : : }
15847 : 0 : entry->owner_dev = owner_dev;
15848 : 0 : entry->flow = flow;
15849 [ # # ]: 0 : if (info)
15850 : 0 : entry->info = *info;
15851 : : else
15852 : 0 : entry->info.type = MLX5_CTRL_FLOW_TYPE_GENERAL;
15853 [ # # ]: 0 : if (external)
15854 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->hw_ext_ctrl_flows, entry, next);
15855 : : else
15856 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->hw_ctrl_flows, entry, next);
15857 : : rte_spinlock_unlock(&priv->hw_ctrl_lock);
15858 : 0 : return 0;
15859 : 0 : error:
15860 [ # # ]: 0 : if (entry)
15861 : 0 : mlx5_free(entry);
15862 : : rte_spinlock_unlock(&priv->hw_ctrl_lock);
15863 : 0 : return ret;
15864 : : }
15865 : :
15866 : : /**
15867 : : * Destroys a control flow @p flow using flow template API on @p dev device.
15868 : : *
15869 : : * This function uses locks internally to synchronize access to the
15870 : : * flow queue.
15871 : : *
15872 : : * If the @p flow is stored on any private list/pool, then caller must free up
15873 : : * the relevant resources.
15874 : : *
15875 : : * @param dev
15876 : : * Pointer to Ethernet device.
15877 : : * @param flow
15878 : : * Pointer to flow rule.
15879 : : *
15880 : : * @return
15881 : : * 0 on success, non-zero value otherwise.
15882 : : */
15883 : : static int
15884 : 0 : flow_hw_destroy_ctrl_flow(struct rte_eth_dev *dev, struct rte_flow *flow)
15885 : : {
15886 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
15887 : 0 : uint32_t queue = CTRL_QUEUE_ID(priv);
15888 : 0 : struct rte_flow_op_attr op_attr = {
15889 : : .postpone = 0,
15890 : : };
15891 : : int ret;
15892 : :
15893 : 0 : rte_spinlock_lock(&priv->hw_ctrl_lock);
15894 : 0 : ret = flow_hw_async_flow_destroy(dev, queue, &op_attr, flow, NULL, NULL);
15895 [ # # ]: 0 : if (ret) {
15896 : 0 : DRV_LOG(ERR, "port %u failed to enqueue destroy control"
15897 : : " flow operation", dev->data->port_id);
15898 : 0 : goto exit;
15899 : : }
15900 : 0 : ret = __flow_hw_pull_comp(dev, queue, NULL);
15901 [ # # ]: 0 : if (ret) {
15902 : 0 : DRV_LOG(ERR, "port %u failed to destroy control flow",
15903 : : dev->data->port_id);
15904 : 0 : rte_errno = EINVAL;
15905 : : ret = -rte_errno;
15906 : 0 : goto exit;
15907 : : }
15908 : 0 : exit:
15909 : : rte_spinlock_unlock(&priv->hw_ctrl_lock);
15910 : 0 : return ret;
15911 : : }
15912 : :
15913 : : /**
15914 : : * Destroys control flows created on behalf of @p owner device on @p dev device.
15915 : : *
15916 : : * @param dev
15917 : : * Pointer to Ethernet device on which control flows were created.
15918 : : * @param owner
15919 : : * Pointer to Ethernet device owning control flows.
15920 : : *
15921 : : * @return
15922 : : * 0 on success, otherwise negative error code is returned and
15923 : : * rte_errno is set.
15924 : : */
15925 : : static int
15926 : 0 : flow_hw_flush_ctrl_flows_owned_by(struct rte_eth_dev *dev, struct rte_eth_dev *owner)
15927 : : {
15928 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
15929 : : struct mlx5_ctrl_flow_entry *cf;
15930 : : struct mlx5_ctrl_flow_entry *cf_next;
15931 : : int ret;
15932 : :
15933 : 0 : cf = LIST_FIRST(&priv->hw_ctrl_flows);
15934 [ # # ]: 0 : while (cf != NULL) {
15935 : 0 : cf_next = LIST_NEXT(cf, next);
15936 [ # # ]: 0 : if (cf->owner_dev == owner) {
15937 : 0 : ret = flow_hw_destroy_ctrl_flow(dev, cf->flow);
15938 [ # # ]: 0 : if (ret) {
15939 : 0 : rte_errno = ret;
15940 : 0 : return -ret;
15941 : : }
15942 [ # # ]: 0 : LIST_REMOVE(cf, next);
15943 : 0 : mlx5_free(cf);
15944 : : }
15945 : : cf = cf_next;
15946 : : }
15947 : : return 0;
15948 : : }
15949 : :
15950 : : /**
15951 : : * Destroys control flows created for @p owner_dev device.
15952 : : *
15953 : : * @param owner_dev
15954 : : * Pointer to Ethernet device owning control flows.
15955 : : *
15956 : : * @return
15957 : : * 0 on success, otherwise negative error code is returned and
15958 : : * rte_errno is set.
15959 : : */
15960 : : int
15961 : 0 : mlx5_flow_hw_flush_ctrl_flows(struct rte_eth_dev *owner_dev)
15962 : : {
15963 : 0 : struct mlx5_priv *owner_priv = owner_dev->data->dev_private;
15964 : : struct rte_eth_dev *proxy_dev;
15965 : 0 : uint16_t owner_port_id = owner_dev->data->port_id;
15966 : 0 : uint16_t proxy_port_id = owner_dev->data->port_id;
15967 : : int ret;
15968 : :
15969 : : /* Flush all flows created by this port for itself. */
15970 : 0 : ret = flow_hw_flush_ctrl_flows_owned_by(owner_dev, owner_dev);
15971 [ # # ]: 0 : if (ret)
15972 : : return ret;
15973 : : /* Flush all flows created for this port on proxy port. */
15974 [ # # ]: 0 : if (owner_priv->sh->config.dv_esw_en) {
15975 : 0 : ret = rte_flow_pick_transfer_proxy(owner_port_id, &proxy_port_id, NULL);
15976 [ # # ]: 0 : if (ret == -ENODEV) {
15977 : 0 : DRV_LOG(DEBUG, "Unable to find transfer proxy port for port %u. It was "
15978 : : "probably closed. Control flows were cleared.",
15979 : : owner_port_id);
15980 : 0 : rte_errno = 0;
15981 : 0 : return 0;
15982 [ # # ]: 0 : } else if (ret) {
15983 : 0 : DRV_LOG(ERR, "Unable to find proxy port for port %u (ret = %d)",
15984 : : owner_port_id, ret);
15985 : 0 : return ret;
15986 : : }
15987 : 0 : proxy_dev = &rte_eth_devices[proxy_port_id];
15988 : : } else {
15989 : : proxy_dev = owner_dev;
15990 : : }
15991 : 0 : return flow_hw_flush_ctrl_flows_owned_by(proxy_dev, owner_dev);
15992 : : }
15993 : :
15994 : : /**
15995 : : * Destroys all control flows created on @p dev device.
15996 : : *
15997 : : * @param owner_dev
15998 : : * Pointer to Ethernet device.
15999 : : *
16000 : : * @return
16001 : : * 0 on success, otherwise negative error code is returned and
16002 : : * rte_errno is set.
16003 : : */
16004 : : static int
16005 : 0 : flow_hw_flush_all_ctrl_flows(struct rte_eth_dev *dev)
16006 : : {
16007 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16008 : : struct mlx5_ctrl_flow_entry *cf;
16009 : : struct mlx5_ctrl_flow_entry *cf_next;
16010 : : int ret;
16011 : :
16012 : 0 : cf = LIST_FIRST(&priv->hw_ctrl_flows);
16013 [ # # ]: 0 : while (cf != NULL) {
16014 : 0 : cf_next = LIST_NEXT(cf, next);
16015 : 0 : ret = flow_hw_destroy_ctrl_flow(dev, cf->flow);
16016 [ # # ]: 0 : if (ret) {
16017 : 0 : rte_errno = ret;
16018 : 0 : return -ret;
16019 : : }
16020 [ # # ]: 0 : LIST_REMOVE(cf, next);
16021 : 0 : mlx5_free(cf);
16022 : : cf = cf_next;
16023 : : }
16024 : 0 : cf = LIST_FIRST(&priv->hw_ext_ctrl_flows);
16025 [ # # ]: 0 : while (cf != NULL) {
16026 : 0 : cf_next = LIST_NEXT(cf, next);
16027 : 0 : ret = flow_hw_destroy_ctrl_flow(dev, cf->flow);
16028 [ # # ]: 0 : if (ret) {
16029 : 0 : rte_errno = ret;
16030 : 0 : return -ret;
16031 : : }
16032 [ # # ]: 0 : LIST_REMOVE(cf, next);
16033 : 0 : mlx5_free(cf);
16034 : : cf = cf_next;
16035 : : }
16036 : : return 0;
16037 : : }
16038 : :
16039 : : int
16040 : 0 : mlx5_flow_hw_esw_create_sq_miss_flow(struct rte_eth_dev *dev, uint32_t sqn, bool external)
16041 : : {
16042 : 0 : uint16_t port_id = dev->data->port_id;
16043 : 0 : struct rte_flow_item_ethdev esw_mgr_spec = {
16044 : : .port_id = MLX5_REPRESENTED_PORT_ESW_MGR,
16045 : : };
16046 : 0 : struct rte_flow_item_ethdev esw_mgr_mask = {
16047 : : .port_id = MLX5_REPRESENTED_PORT_ESW_MGR,
16048 : : };
16049 : 0 : struct rte_flow_item_tag reg_c0_spec = {
16050 : : .index = (uint8_t)REG_C_0,
16051 : : .data = flow_hw_esw_mgr_regc_marker(dev),
16052 : : };
16053 : 0 : struct rte_flow_item_tag reg_c0_mask = {
16054 : : .index = 0xff,
16055 : : .data = flow_hw_esw_mgr_regc_marker_mask(dev),
16056 : : };
16057 : 0 : struct mlx5_rte_flow_item_sq sq_spec = {
16058 : : .queue = sqn,
16059 : : };
16060 : 0 : struct rte_flow_action_ethdev port = {
16061 : : .port_id = port_id,
16062 : : };
16063 : 0 : struct rte_flow_item items[3] = { { 0 } };
16064 : 0 : struct rte_flow_action actions[3] = { { 0 } };
16065 : 0 : struct mlx5_ctrl_flow_info flow_info = {
16066 : : .type = MLX5_CTRL_FLOW_TYPE_SQ_MISS_ROOT,
16067 : : .esw_mgr_sq = sqn,
16068 : : };
16069 : : struct rte_eth_dev *proxy_dev;
16070 : : struct mlx5_priv *proxy_priv;
16071 : 0 : uint16_t proxy_port_id = dev->data->port_id;
16072 : : int ret;
16073 : :
16074 : 0 : ret = rte_flow_pick_transfer_proxy(port_id, &proxy_port_id, NULL);
16075 [ # # ]: 0 : if (ret) {
16076 : 0 : DRV_LOG(ERR, "Unable to pick transfer proxy port for port %u. Transfer proxy "
16077 : : "port must be present to create default SQ miss flows.",
16078 : : port_id);
16079 : 0 : return ret;
16080 : : }
16081 : 0 : proxy_dev = &rte_eth_devices[proxy_port_id];
16082 : 0 : proxy_priv = proxy_dev->data->dev_private;
16083 [ # # ]: 0 : if (!proxy_priv->dr_ctx) {
16084 : 0 : DRV_LOG(DEBUG, "Transfer proxy port (port %u) of port %u must be configured "
16085 : : "for HWS to create default SQ miss flows. Default flows will "
16086 : : "not be created.",
16087 : : proxy_port_id, port_id);
16088 : 0 : return 0;
16089 : : }
16090 [ # # ]: 0 : if (!proxy_priv->hw_ctrl_fdb ||
16091 [ # # ]: 0 : !proxy_priv->hw_ctrl_fdb->hw_esw_sq_miss_root_tbl ||
16092 [ # # ]: 0 : !proxy_priv->hw_ctrl_fdb->hw_esw_sq_miss_tbl) {
16093 : 0 : DRV_LOG(ERR, "Transfer proxy port (port %u) of port %u was configured, but "
16094 : : "default flow tables were not created.",
16095 : : proxy_port_id, port_id);
16096 : 0 : rte_errno = ENOMEM;
16097 : 0 : return -rte_errno;
16098 : : }
16099 : : /*
16100 : : * Create a root SQ miss flow rule - match E-Switch Manager and SQ,
16101 : : * and jump to group 1.
16102 : : */
16103 : 0 : items[0] = (struct rte_flow_item){
16104 : : .type = RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT,
16105 : : .spec = &esw_mgr_spec,
16106 : : .mask = &esw_mgr_mask,
16107 : : };
16108 : 0 : items[1] = (struct rte_flow_item){
16109 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_SQ,
16110 : : .spec = &sq_spec,
16111 : : };
16112 : 0 : items[2] = (struct rte_flow_item){
16113 : : .type = RTE_FLOW_ITEM_TYPE_END,
16114 : : };
16115 : 0 : actions[0] = (struct rte_flow_action){
16116 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
16117 : : };
16118 : 0 : actions[1] = (struct rte_flow_action){
16119 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
16120 : : };
16121 : 0 : actions[2] = (struct rte_flow_action) {
16122 : : .type = RTE_FLOW_ACTION_TYPE_END,
16123 : : };
16124 : 0 : ret = flow_hw_create_ctrl_flow(dev, proxy_dev,
16125 : : proxy_priv->hw_ctrl_fdb->hw_esw_sq_miss_root_tbl,
16126 : : items, 0, actions, 0, &flow_info, external);
16127 [ # # ]: 0 : if (ret) {
16128 : 0 : DRV_LOG(ERR, "Port %u failed to create root SQ miss flow rule for SQ %u, ret %d",
16129 : : port_id, sqn, ret);
16130 : 0 : return ret;
16131 : : }
16132 : : /*
16133 : : * Create a non-root SQ miss flow rule - match REG_C_0 marker and SQ,
16134 : : * and forward to port.
16135 : : */
16136 : 0 : items[0] = (struct rte_flow_item){
16137 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_TAG,
16138 : : .spec = ®_c0_spec,
16139 : : .mask = ®_c0_mask,
16140 : : };
16141 : 0 : items[1] = (struct rte_flow_item){
16142 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_SQ,
16143 : : .spec = &sq_spec,
16144 : : };
16145 : 0 : items[2] = (struct rte_flow_item){
16146 : : .type = RTE_FLOW_ITEM_TYPE_END,
16147 : : };
16148 : 0 : actions[0] = (struct rte_flow_action){
16149 : : .type = RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT,
16150 : : .conf = &port,
16151 : : };
16152 : 0 : actions[1] = (struct rte_flow_action){
16153 : : .type = RTE_FLOW_ACTION_TYPE_END,
16154 : : };
16155 : 0 : flow_info.type = MLX5_CTRL_FLOW_TYPE_SQ_MISS;
16156 : 0 : ret = flow_hw_create_ctrl_flow(dev, proxy_dev,
16157 : 0 : proxy_priv->hw_ctrl_fdb->hw_esw_sq_miss_tbl,
16158 : : items, 0, actions, 0, &flow_info, external);
16159 [ # # ]: 0 : if (ret) {
16160 : 0 : DRV_LOG(ERR, "Port %u failed to create HWS SQ miss flow rule for SQ %u, ret %d",
16161 : : port_id, sqn, ret);
16162 : 0 : return ret;
16163 : : }
16164 : : return 0;
16165 : : }
16166 : :
16167 : : static bool
16168 : : flow_hw_is_matching_sq_miss_flow(struct mlx5_ctrl_flow_entry *cf,
16169 : : struct rte_eth_dev *dev,
16170 : : uint32_t sqn)
16171 : : {
16172 : 0 : if (cf->owner_dev != dev)
16173 : : return false;
16174 [ # # # # ]: 0 : if (cf->info.type == MLX5_CTRL_FLOW_TYPE_SQ_MISS_ROOT && cf->info.esw_mgr_sq == sqn)
16175 : : return true;
16176 [ # # # # ]: 0 : if (cf->info.type == MLX5_CTRL_FLOW_TYPE_SQ_MISS && cf->info.esw_mgr_sq == sqn)
16177 : : return true;
16178 : : return false;
16179 : : }
16180 : :
16181 : : int
16182 : 0 : mlx5_flow_hw_esw_destroy_sq_miss_flow(struct rte_eth_dev *dev, uint32_t sqn, bool external)
16183 : : {
16184 : 0 : uint16_t port_id = dev->data->port_id;
16185 : 0 : uint16_t proxy_port_id = dev->data->port_id;
16186 : : struct rte_eth_dev *proxy_dev;
16187 : : struct mlx5_priv *proxy_priv;
16188 : : struct mlx5_ctrl_flow_entry *cf;
16189 : : struct mlx5_ctrl_flow_entry *cf_next;
16190 : : int ret;
16191 : :
16192 : 0 : ret = rte_flow_pick_transfer_proxy(port_id, &proxy_port_id, NULL);
16193 [ # # ]: 0 : if (ret) {
16194 : 0 : DRV_LOG(ERR, "Unable to pick transfer proxy port for port %u. Transfer proxy "
16195 : : "port must be present for default SQ miss flow rules to exist.",
16196 : : port_id);
16197 : 0 : return ret;
16198 : : }
16199 : 0 : proxy_dev = &rte_eth_devices[proxy_port_id];
16200 : 0 : proxy_priv = proxy_dev->data->dev_private;
16201 : : /* FDB default flow rules must be enabled. */
16202 : : MLX5_ASSERT(proxy_priv->sh->config.fdb_def_rule);
16203 [ # # ]: 0 : if (!proxy_priv->dr_ctx)
16204 : : return 0;
16205 [ # # ]: 0 : if (!proxy_priv->hw_ctrl_fdb ||
16206 [ # # ]: 0 : !proxy_priv->hw_ctrl_fdb->hw_esw_sq_miss_root_tbl ||
16207 [ # # ]: 0 : !proxy_priv->hw_ctrl_fdb->hw_esw_sq_miss_tbl)
16208 : : return 0;
16209 [ # # ]: 0 : cf = external ? LIST_FIRST(&proxy_priv->hw_ext_ctrl_flows) :
16210 : : LIST_FIRST(&proxy_priv->hw_ctrl_flows);
16211 [ # # ]: 0 : while (cf != NULL) {
16212 [ # # ]: 0 : cf_next = LIST_NEXT(cf, next);
16213 : : if (flow_hw_is_matching_sq_miss_flow(cf, dev, sqn)) {
16214 : 0 : claim_zero(flow_hw_destroy_ctrl_flow(proxy_dev, cf->flow));
16215 [ # # ]: 0 : LIST_REMOVE(cf, next);
16216 : 0 : mlx5_free(cf);
16217 : : }
16218 : : cf = cf_next;
16219 : : }
16220 : : return 0;
16221 : : }
16222 : :
16223 : : int
16224 : 0 : mlx5_flow_hw_esw_create_default_jump_flow(struct rte_eth_dev *dev)
16225 : : {
16226 : 0 : uint16_t port_id = dev->data->port_id;
16227 : 0 : struct rte_flow_item_ethdev port_spec = {
16228 : : .port_id = port_id,
16229 : : };
16230 : 0 : struct rte_flow_item items[] = {
16231 : : {
16232 : : .type = RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT,
16233 : : .spec = &port_spec,
16234 : : },
16235 : : {
16236 : : .type = RTE_FLOW_ITEM_TYPE_END,
16237 : : },
16238 : : };
16239 : 0 : struct rte_flow_action_jump jump = {
16240 : : .group = 1,
16241 : : };
16242 : 0 : struct rte_flow_action actions[] = {
16243 : : {
16244 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
16245 : : .conf = &jump,
16246 : : },
16247 : : {
16248 : : .type = RTE_FLOW_ACTION_TYPE_END,
16249 : : }
16250 : : };
16251 : 0 : struct mlx5_ctrl_flow_info flow_info = {
16252 : : .type = MLX5_CTRL_FLOW_TYPE_DEFAULT_JUMP,
16253 : : };
16254 : : struct rte_eth_dev *proxy_dev;
16255 : : struct mlx5_priv *proxy_priv;
16256 : 0 : uint16_t proxy_port_id = dev->data->port_id;
16257 : : int ret;
16258 : :
16259 : 0 : ret = rte_flow_pick_transfer_proxy(port_id, &proxy_port_id, NULL);
16260 [ # # ]: 0 : if (ret) {
16261 : 0 : DRV_LOG(ERR, "Unable to pick transfer proxy port for port %u. Transfer proxy "
16262 : : "port must be present to create default FDB jump rule.",
16263 : : port_id);
16264 : 0 : return ret;
16265 : : }
16266 : 0 : proxy_dev = &rte_eth_devices[proxy_port_id];
16267 : 0 : proxy_priv = proxy_dev->data->dev_private;
16268 : : /* FDB default flow rules must be enabled. */
16269 : : MLX5_ASSERT(proxy_priv->sh->config.fdb_def_rule);
16270 [ # # ]: 0 : if (!proxy_priv->dr_ctx) {
16271 : 0 : DRV_LOG(DEBUG, "Transfer proxy port (port %u) of port %u must be configured "
16272 : : "for HWS to create default FDB jump rule. Default rule will "
16273 : : "not be created.",
16274 : : proxy_port_id, port_id);
16275 : 0 : return 0;
16276 : : }
16277 [ # # # # ]: 0 : if (!proxy_priv->hw_ctrl_fdb || !proxy_priv->hw_ctrl_fdb->hw_esw_zero_tbl) {
16278 : 0 : DRV_LOG(ERR, "Transfer proxy port (port %u) of port %u was configured, but "
16279 : : "default flow tables were not created.",
16280 : : proxy_port_id, port_id);
16281 : 0 : rte_errno = EINVAL;
16282 : 0 : return -rte_errno;
16283 : : }
16284 : 0 : return flow_hw_create_ctrl_flow(dev, proxy_dev,
16285 : : proxy_priv->hw_ctrl_fdb->hw_esw_zero_tbl,
16286 : : items, 0, actions, 0, &flow_info, false);
16287 : : }
16288 : :
16289 : : int
16290 : 0 : mlx5_flow_hw_create_nic_tx_default_mreg_copy_flow(struct rte_eth_dev *dev, uint32_t sqn)
16291 : : {
16292 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16293 : 0 : struct mlx5_rte_flow_item_sq sq_spec = {
16294 : : .queue = sqn,
16295 : : };
16296 : 0 : struct rte_flow_item items[] = {
16297 : : {
16298 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_SQ,
16299 : : .spec = &sq_spec,
16300 : : },
16301 : : {
16302 : : .type = RTE_FLOW_ITEM_TYPE_END,
16303 : : },
16304 : : };
16305 : 0 : struct rte_flow_action_modify_field mreg_action = {
16306 : : .operation = RTE_FLOW_MODIFY_SET,
16307 : : .dst = {
16308 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
16309 : : .tag_index = REG_C_1,
16310 : : },
16311 : : .src = {
16312 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
16313 : : .tag_index = REG_A,
16314 : : },
16315 : : .width = 32,
16316 : : };
16317 : 0 : struct rte_flow_action copy_reg_action[] = {
16318 : : [0] = {
16319 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
16320 : : .conf = &mreg_action,
16321 : : },
16322 : : [1] = {
16323 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
16324 : : },
16325 : : [2] = {
16326 : : .type = RTE_FLOW_ACTION_TYPE_END,
16327 : : },
16328 : : };
16329 : 0 : struct mlx5_ctrl_flow_info flow_info = {
16330 : : .type = MLX5_CTRL_FLOW_TYPE_TX_META_COPY,
16331 : : .tx_repr_sq = sqn,
16332 : : };
16333 : :
16334 : 0 : return flow_hw_create_ctrl_flow(dev, dev,
16335 : 0 : priv->hw_ctrl_nic->hw_tx_meta_cpy_tbl,
16336 : : items, 0, copy_reg_action, 0, &flow_info, false);
16337 : : }
16338 : :
16339 : : int
16340 : 0 : mlx5_flow_hw_create_tx_repr_matching_flow(struct rte_eth_dev *dev, uint32_t sqn, bool external)
16341 : : {
16342 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16343 : 0 : struct mlx5_rte_flow_item_sq sq_spec = {
16344 : : .queue = sqn,
16345 : : };
16346 : 0 : struct rte_flow_item items[] = {
16347 : : {
16348 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_SQ,
16349 : : .spec = &sq_spec,
16350 : : },
16351 : : {
16352 : : .type = RTE_FLOW_ITEM_TYPE_END,
16353 : : },
16354 : : };
16355 : : /*
16356 : : * Allocate actions array suitable for all cases - extended metadata enabled or not.
16357 : : * With extended metadata there will be an additional MODIFY_FIELD action before JUMP.
16358 : : */
16359 : 0 : struct rte_flow_action actions[] = {
16360 : : { .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD },
16361 : : { .type = RTE_FLOW_ACTION_TYPE_JUMP },
16362 : : { .type = RTE_FLOW_ACTION_TYPE_END },
16363 : : { .type = RTE_FLOW_ACTION_TYPE_END },
16364 : : };
16365 : 0 : struct mlx5_ctrl_flow_info flow_info = {
16366 : : .type = MLX5_CTRL_FLOW_TYPE_TX_REPR_MATCH,
16367 : : .tx_repr_sq = sqn,
16368 : : };
16369 : :
16370 [ # # ]: 0 : if (!priv->dr_ctx) {
16371 : 0 : DRV_LOG(DEBUG, "Port %u must be configured for HWS, before creating "
16372 : : "default egress flow rules. Omitting creation.",
16373 : : dev->data->port_id);
16374 : 0 : return 0;
16375 : : }
16376 [ # # ]: 0 : if (!priv->hw_tx_repr_tagging_tbl) {
16377 : 0 : DRV_LOG(ERR, "Port %u is configured for HWS, but table for default "
16378 : : "egress flow rules does not exist.",
16379 : : dev->data->port_id);
16380 : 0 : rte_errno = EINVAL;
16381 : 0 : return -rte_errno;
16382 : : }
16383 : : /*
16384 : : * If extended metadata mode is enabled, then an additional MODIFY_FIELD action must be
16385 : : * placed before terminating JUMP action.
16386 : : */
16387 [ # # ]: 0 : if (priv->sh->config.dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS) {
16388 : 0 : actions[1].type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD;
16389 : 0 : actions[2].type = RTE_FLOW_ACTION_TYPE_JUMP;
16390 : : }
16391 : 0 : return flow_hw_create_ctrl_flow(dev, dev, priv->hw_tx_repr_tagging_tbl,
16392 : : items, 0, actions, 0, &flow_info, external);
16393 : : }
16394 : :
16395 : : static bool
16396 : : flow_hw_is_tx_matching_repr_matching_flow(struct mlx5_ctrl_flow_entry *cf,
16397 : : struct rte_eth_dev *dev,
16398 : : uint32_t sqn)
16399 : : {
16400 : 0 : if (cf->owner_dev != dev)
16401 : : return false;
16402 [ # # # # ]: 0 : if (cf->info.type == MLX5_CTRL_FLOW_TYPE_TX_REPR_MATCH && cf->info.tx_repr_sq == sqn)
16403 : : return true;
16404 : : return false;
16405 : : }
16406 : :
16407 : : int
16408 : 0 : mlx5_flow_hw_destroy_tx_repr_matching_flow(struct rte_eth_dev *dev, uint32_t sqn, bool external)
16409 : : {
16410 : 0 : uint16_t port_id = dev->data->port_id;
16411 : 0 : uint16_t proxy_port_id = dev->data->port_id;
16412 : : struct rte_eth_dev *proxy_dev;
16413 : : struct mlx5_priv *proxy_priv;
16414 : : struct mlx5_ctrl_flow_entry *cf;
16415 : : struct mlx5_ctrl_flow_entry *cf_next;
16416 : : int ret;
16417 : :
16418 : 0 : ret = rte_flow_pick_transfer_proxy(port_id, &proxy_port_id, NULL);
16419 [ # # ]: 0 : if (ret) {
16420 : 0 : DRV_LOG(ERR, "Unable to pick transfer proxy port for port %u. Transfer proxy "
16421 : : "port must be present for default SQ miss flow rules to exist.",
16422 : : port_id);
16423 : 0 : return ret;
16424 : : }
16425 : 0 : proxy_dev = &rte_eth_devices[proxy_port_id];
16426 : 0 : proxy_priv = proxy_dev->data->dev_private;
16427 [ # # ]: 0 : if (!proxy_priv->dr_ctx ||
16428 [ # # ]: 0 : !proxy_priv->hw_tx_repr_tagging_tbl)
16429 : : return 0;
16430 [ # # ]: 0 : cf = external ? LIST_FIRST(&proxy_priv->hw_ext_ctrl_flows) :
16431 : : LIST_FIRST(&proxy_priv->hw_ctrl_flows);
16432 [ # # ]: 0 : while (cf != NULL) {
16433 [ # # ]: 0 : cf_next = LIST_NEXT(cf, next);
16434 : : if (flow_hw_is_tx_matching_repr_matching_flow(cf, dev, sqn)) {
16435 : 0 : claim_zero(flow_hw_destroy_ctrl_flow(proxy_dev, cf->flow));
16436 [ # # ]: 0 : LIST_REMOVE(cf, next);
16437 : 0 : mlx5_free(cf);
16438 : : }
16439 : : cf = cf_next;
16440 : : }
16441 : : return 0;
16442 : : }
16443 : :
16444 : : int
16445 : 0 : mlx5_flow_hw_lacp_rx_flow(struct rte_eth_dev *dev)
16446 : : {
16447 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16448 : 0 : struct rte_flow_item_eth lacp_item = {
16449 : : .type = RTE_BE16(RTE_ETHER_TYPE_SLOW),
16450 : : };
16451 : 0 : struct rte_flow_item eth_lacp[] = {
16452 : : [0] = {
16453 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
16454 : : .spec = &lacp_item,
16455 : : .mask = &lacp_item,
16456 : : },
16457 : : [1] = {
16458 : : .type = RTE_FLOW_ITEM_TYPE_END,
16459 : : },
16460 : : };
16461 : 0 : struct rte_flow_action miss_action[] = {
16462 : : [0] = {
16463 : : .type = (enum rte_flow_action_type)
16464 : : MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS,
16465 : : },
16466 : : [1] = {
16467 : : .type = RTE_FLOW_ACTION_TYPE_END,
16468 : : },
16469 : : };
16470 : 0 : struct mlx5_ctrl_flow_info flow_info = {
16471 : : .type = MLX5_CTRL_FLOW_TYPE_LACP_RX,
16472 : : };
16473 : :
16474 [ # # # # : 0 : if (!priv->dr_ctx || !priv->hw_lacp_miss || !priv->hw_lacp_miss->hw_lacp_rx_tbl)
# # ]
16475 : : return 0;
16476 : 0 : return flow_hw_create_ctrl_flow(dev, dev,
16477 : : priv->hw_lacp_miss->hw_lacp_rx_tbl,
16478 : : eth_lacp, 0, miss_action, 0, &flow_info, false);
16479 : : }
16480 : :
16481 : : static uint32_t
16482 : : __calc_pattern_flags(const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type)
16483 : : {
16484 : : switch (eth_pattern_type) {
16485 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL:
16486 : : return MLX5_CTRL_PROMISCUOUS;
16487 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL_MCAST:
16488 : : return MLX5_CTRL_ALL_MULTICAST;
16489 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST:
16490 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST_VLAN:
16491 : : return MLX5_CTRL_BROADCAST;
16492 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST:
16493 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST_VLAN:
16494 : : return MLX5_CTRL_IPV4_MULTICAST;
16495 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST:
16496 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST_VLAN:
16497 : : return MLX5_CTRL_IPV6_MULTICAST;
16498 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC:
16499 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN:
16500 : : return MLX5_CTRL_DMAC;
16501 : : default:
16502 : : /* Should not reach here. */
16503 : : MLX5_ASSERT(false);
16504 : : return 0;
16505 : : }
16506 : : }
16507 : :
16508 : : static uint32_t
16509 : : __calc_vlan_flags(const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type)
16510 : : {
16511 [ # # ]: 0 : switch (eth_pattern_type) {
16512 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST_VLAN:
16513 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST_VLAN:
16514 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST_VLAN:
16515 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN:
16516 : : return MLX5_CTRL_VLAN_FILTER;
16517 : 0 : default:
16518 : 0 : return 0;
16519 : : }
16520 : : }
16521 : :
16522 : : static bool
16523 [ # # ]: 0 : eth_pattern_type_is_requested(const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type,
16524 : : uint32_t flags)
16525 : : {
16526 : : uint32_t pattern_flags = __calc_pattern_flags(eth_pattern_type);
16527 : : uint32_t vlan_flags = __calc_vlan_flags(eth_pattern_type);
16528 : 0 : bool pattern_requested = !!(pattern_flags & flags);
16529 [ # # # # ]: 0 : bool consider_vlan = vlan_flags || (MLX5_CTRL_VLAN_FILTER & flags);
16530 : 0 : bool vlan_requested = !!(vlan_flags & flags);
16531 : :
16532 [ # # ]: 0 : if (consider_vlan)
16533 : 0 : return pattern_requested && vlan_requested;
16534 : : else
16535 : : return pattern_requested;
16536 : : }
16537 : :
16538 : : static bool
16539 : : rss_type_is_requested(struct mlx5_priv *priv,
16540 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
16541 : : {
16542 : 0 : struct rte_flow_actions_template *at = priv->hw_ctrl_rx->rss[rss_type];
16543 : : unsigned int i;
16544 : :
16545 [ # # # # ]: 0 : for (i = 0; at->actions[i].type != RTE_FLOW_ACTION_TYPE_END; ++i) {
16546 [ # # # # ]: 0 : if (at->actions[i].type == RTE_FLOW_ACTION_TYPE_RSS) {
16547 : 0 : const struct rte_flow_action_rss *rss = at->actions[i].conf;
16548 : 0 : uint64_t rss_types = rss->types;
16549 : :
16550 [ # # # # ]: 0 : if ((rss_types & priv->rss_conf.rss_hf) != rss_types)
16551 : : return false;
16552 : : }
16553 : : }
16554 : : return true;
16555 : : }
16556 : :
16557 : : static const struct rte_flow_item_eth *
16558 : : __get_eth_spec(const enum mlx5_flow_ctrl_rx_eth_pattern_type pattern)
16559 : : {
16560 : 0 : switch (pattern) {
16561 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL:
16562 : : return &ctrl_rx_eth_promisc_spec;
16563 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL_MCAST:
16564 : 0 : return &ctrl_rx_eth_mcast_spec;
16565 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST:
16566 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST_VLAN:
16567 : 0 : return &ctrl_rx_eth_bcast_spec;
16568 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST:
16569 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST_VLAN:
16570 : 0 : return &ctrl_rx_eth_ipv4_mcast_spec;
16571 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST:
16572 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST_VLAN:
16573 : 0 : return &ctrl_rx_eth_ipv6_mcast_spec;
16574 : 0 : default:
16575 : : /* This case should not be reached. */
16576 : : MLX5_ASSERT(false);
16577 : 0 : return NULL;
16578 : : }
16579 : : }
16580 : :
16581 : : static int
16582 [ # # # # : 0 : __flow_hw_ctrl_flows_single(struct rte_eth_dev *dev,
# # ]
16583 : : struct rte_flow_template_table *tbl,
16584 : : const enum mlx5_flow_ctrl_rx_eth_pattern_type pattern_type,
16585 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
16586 : : {
16587 : : const struct rte_flow_item_eth *eth_spec = __get_eth_spec(pattern_type);
16588 : : struct rte_flow_item items[5];
16589 : 0 : struct rte_flow_action actions[] = {
16590 : : { .type = RTE_FLOW_ACTION_TYPE_RSS },
16591 : : { .type = RTE_FLOW_ACTION_TYPE_END },
16592 : : };
16593 : 0 : struct mlx5_ctrl_flow_info flow_info = {
16594 : : .type = MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS,
16595 : : };
16596 : :
16597 [ # # ]: 0 : if (!eth_spec)
16598 : : return -EINVAL;
16599 : : memset(items, 0, sizeof(items));
16600 : 0 : items[0] = (struct rte_flow_item){
16601 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
16602 : : .spec = eth_spec,
16603 : : };
16604 [ # # # ]: 0 : items[1] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_VOID };
16605 [ # # # ]: 0 : items[2] = flow_hw_get_ctrl_rx_l3_item(rss_type);
16606 : 0 : items[3] = flow_hw_get_ctrl_rx_l4_item(rss_type);
16607 : 0 : items[4] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_END };
16608 : : /* Without VLAN filtering, only a single flow rule must be created. */
16609 : 0 : return flow_hw_create_ctrl_flow(dev, dev, tbl, items, 0, actions, 0, &flow_info, false);
16610 : : }
16611 : :
16612 : : static int
16613 : 0 : __flow_hw_ctrl_flows_single_vlan(struct rte_eth_dev *dev,
16614 : : struct rte_flow_template_table *tbl,
16615 : : const enum mlx5_flow_ctrl_rx_eth_pattern_type pattern_type,
16616 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
16617 : : {
16618 [ # # # # : 0 : struct mlx5_priv *priv = dev->data->dev_private;
# # ]
16619 : : const struct rte_flow_item_eth *eth_spec = __get_eth_spec(pattern_type);
16620 : : struct rte_flow_item items[5];
16621 : 0 : struct rte_flow_action actions[] = {
16622 : : { .type = RTE_FLOW_ACTION_TYPE_RSS },
16623 : : { .type = RTE_FLOW_ACTION_TYPE_END },
16624 : : };
16625 : 0 : struct mlx5_ctrl_flow_info flow_info = {
16626 : : .type = MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS,
16627 : : };
16628 : : unsigned int i;
16629 : :
16630 [ # # ]: 0 : if (!eth_spec)
16631 : : return -EINVAL;
16632 : : memset(items, 0, sizeof(items));
16633 : 0 : items[0] = (struct rte_flow_item){
16634 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
16635 : : .spec = eth_spec,
16636 : : };
16637 : : /* Optional VLAN for now will be VOID - will be filled later. */
16638 [ # # # ]: 0 : items[1] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_VLAN };
16639 [ # # # ]: 0 : items[2] = flow_hw_get_ctrl_rx_l3_item(rss_type);
16640 : 0 : items[3] = flow_hw_get_ctrl_rx_l4_item(rss_type);
16641 : 0 : items[4] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_END };
16642 : : /* Since VLAN filtering is done, create a single flow rule for each registered vid. */
16643 [ # # ]: 0 : for (i = 0; i < priv->vlan_filter_n; ++i) {
16644 : 0 : uint16_t vlan = priv->vlan_filter[i];
16645 : 0 : struct rte_flow_item_vlan vlan_spec = {
16646 [ # # ]: 0 : .hdr.vlan_tci = rte_cpu_to_be_16(vlan),
16647 : : };
16648 : :
16649 : 0 : items[1].spec = &vlan_spec;
16650 [ # # ]: 0 : if (flow_hw_create_ctrl_flow(dev, dev,
16651 : : tbl, items, 0, actions, 0, &flow_info, false))
16652 : 0 : return -rte_errno;
16653 : : }
16654 : : return 0;
16655 : : }
16656 : :
16657 : : static int
16658 : 0 : __flow_hw_ctrl_flows_unicast_create(struct rte_eth_dev *dev,
16659 : : struct rte_flow_template_table *tbl,
16660 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type,
16661 : : const struct rte_ether_addr *addr)
16662 : : {
16663 : 0 : struct rte_flow_item_eth eth_spec = {
16664 : : .hdr.dst_addr = *addr,
16665 : : };
16666 : : struct rte_flow_item items[5];
16667 : 0 : struct rte_flow_action actions[] = {
16668 : : { .type = RTE_FLOW_ACTION_TYPE_RSS },
16669 : : { .type = RTE_FLOW_ACTION_TYPE_END },
16670 : : };
16671 [ # # # ]: 0 : struct mlx5_ctrl_flow_info flow_info = {
16672 : : .type = MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC,
16673 : : .uc = {
16674 : : .dmac = *addr,
16675 : : },
16676 : : };
16677 : :
16678 : : memset(items, 0, sizeof(items));
16679 : 0 : items[0] = (struct rte_flow_item){
16680 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
16681 : : .spec = ð_spec,
16682 : : };
16683 [ # # # ]: 0 : items[1] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_VOID };
16684 [ # # # ]: 0 : items[2] = flow_hw_get_ctrl_rx_l3_item(rss_type);
16685 : 0 : items[3] = flow_hw_get_ctrl_rx_l4_item(rss_type);
16686 : 0 : items[4] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_END };
16687 : :
16688 [ # # ]: 0 : if (flow_hw_create_ctrl_flow(dev, dev, tbl, items, 0, actions, 0, &flow_info, false))
16689 : 0 : return -rte_errno;
16690 : :
16691 : : return 0;
16692 : : }
16693 : :
16694 : : static int
16695 : 0 : __flow_hw_ctrl_flows_unicast(struct rte_eth_dev *dev,
16696 : : struct rte_flow_template_table *tbl,
16697 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
16698 : : {
16699 : : unsigned int i;
16700 : : int ret;
16701 : :
16702 [ # # ]: 0 : for (i = 0; i < MLX5_MAX_MAC_ADDRESSES; ++i) {
16703 [ # # ]: 0 : struct rte_ether_addr *mac = &dev->data->mac_addrs[i];
16704 : :
16705 [ # # ]: 0 : if (rte_is_zero_ether_addr(mac))
16706 : 0 : continue;
16707 : :
16708 : 0 : ret = __flow_hw_ctrl_flows_unicast_create(dev, tbl, rss_type, mac);
16709 [ # # ]: 0 : if (ret < 0)
16710 : 0 : return ret;
16711 : : }
16712 : : return 0;
16713 : : }
16714 : :
16715 : : static int
16716 : 0 : __flow_hw_ctrl_flows_unicast_vlan_create(struct rte_eth_dev *dev,
16717 : : struct rte_flow_template_table *tbl,
16718 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type,
16719 : : const struct rte_ether_addr *addr,
16720 : : const uint16_t vid)
16721 : : {
16722 : 0 : struct rte_flow_item_eth eth_spec = {
16723 : : .hdr.dst_addr = *addr,
16724 : : };
16725 : 0 : struct rte_flow_item_vlan vlan_spec = {
16726 [ # # ]: 0 : .tci = rte_cpu_to_be_16(vid),
16727 : : };
16728 : : struct rte_flow_item items[5];
16729 : 0 : struct rte_flow_action actions[] = {
16730 : : { .type = RTE_FLOW_ACTION_TYPE_RSS },
16731 : : { .type = RTE_FLOW_ACTION_TYPE_END },
16732 : : };
16733 [ # # # ]: 0 : struct mlx5_ctrl_flow_info flow_info = {
16734 : : .type = MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC_VLAN,
16735 : : .uc = {
16736 : : .dmac = *addr,
16737 : : .vlan = vid,
16738 : : },
16739 : : };
16740 : :
16741 : : memset(items, 0, sizeof(items));
16742 : 0 : items[0] = (struct rte_flow_item){
16743 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
16744 : : .spec = ð_spec,
16745 : : };
16746 [ # # # ]: 0 : items[1] = (struct rte_flow_item){
16747 : : .type = RTE_FLOW_ITEM_TYPE_VLAN,
16748 : : .spec = &vlan_spec,
16749 : : };
16750 [ # # # ]: 0 : items[2] = flow_hw_get_ctrl_rx_l3_item(rss_type);
16751 : 0 : items[3] = flow_hw_get_ctrl_rx_l4_item(rss_type);
16752 : 0 : items[4] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_END };
16753 : :
16754 [ # # ]: 0 : if (flow_hw_create_ctrl_flow(dev, dev, tbl, items, 0, actions, 0, &flow_info, false))
16755 : 0 : return -rte_errno;
16756 : :
16757 : : return 0;
16758 : : }
16759 : :
16760 : : static int
16761 : 0 : __flow_hw_ctrl_flows_unicast_vlan(struct rte_eth_dev *dev,
16762 : : struct rte_flow_template_table *tbl,
16763 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
16764 : : {
16765 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16766 : : unsigned int i;
16767 : : unsigned int j;
16768 : :
16769 [ # # ]: 0 : for (i = 0; i < MLX5_MAX_MAC_ADDRESSES; ++i) {
16770 [ # # ]: 0 : struct rte_ether_addr *mac = &dev->data->mac_addrs[i];
16771 : :
16772 [ # # ]: 0 : if (rte_is_zero_ether_addr(mac))
16773 : 0 : continue;
16774 : :
16775 [ # # ]: 0 : for (j = 0; j < priv->vlan_filter_n; ++j) {
16776 : 0 : uint16_t vlan = priv->vlan_filter[j];
16777 : : int ret;
16778 : :
16779 : 0 : ret = __flow_hw_ctrl_flows_unicast_vlan_create(dev, tbl, rss_type,
16780 : : mac, vlan);
16781 [ # # ]: 0 : if (ret < 0)
16782 : 0 : return ret;
16783 : : }
16784 : : }
16785 : : return 0;
16786 : : }
16787 : :
16788 : : static int
16789 : 0 : __flow_hw_ctrl_flows(struct rte_eth_dev *dev,
16790 : : struct rte_flow_template_table *tbl,
16791 : : const enum mlx5_flow_ctrl_rx_eth_pattern_type pattern_type,
16792 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
16793 : : {
16794 [ # # # # : 0 : switch (pattern_type) {
# ]
16795 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL:
16796 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL_MCAST:
16797 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST:
16798 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST:
16799 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST:
16800 : 0 : return __flow_hw_ctrl_flows_single(dev, tbl, pattern_type, rss_type);
16801 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST_VLAN:
16802 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST_VLAN:
16803 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST_VLAN:
16804 : 0 : return __flow_hw_ctrl_flows_single_vlan(dev, tbl, pattern_type, rss_type);
16805 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC:
16806 : 0 : return __flow_hw_ctrl_flows_unicast(dev, tbl, rss_type);
16807 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN:
16808 : 0 : return __flow_hw_ctrl_flows_unicast_vlan(dev, tbl, rss_type);
16809 : 0 : default:
16810 : : /* Should not reach here. */
16811 : : MLX5_ASSERT(false);
16812 : 0 : rte_errno = EINVAL;
16813 : 0 : return -EINVAL;
16814 : : }
16815 : : }
16816 : :
16817 : :
16818 : : int
16819 : 0 : mlx5_flow_hw_ctrl_flows(struct rte_eth_dev *dev, uint32_t flags)
16820 : : {
16821 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16822 : : struct mlx5_flow_hw_ctrl_rx *hw_ctrl_rx;
16823 : : unsigned int i;
16824 : : int j;
16825 : : int ret = 0;
16826 : :
16827 : : RTE_SET_USED(priv);
16828 : : RTE_SET_USED(flags);
16829 [ # # ]: 0 : if (!priv->dr_ctx) {
16830 : 0 : DRV_LOG(DEBUG, "port %u Control flow rules will not be created. "
16831 : : "HWS needs to be configured beforehand.",
16832 : : dev->data->port_id);
16833 : 0 : return 0;
16834 : : }
16835 [ # # ]: 0 : if (!priv->hw_ctrl_rx) {
16836 : 0 : DRV_LOG(ERR, "port %u Control flow rules templates were not created.",
16837 : : dev->data->port_id);
16838 : 0 : rte_errno = EINVAL;
16839 : 0 : return -rte_errno;
16840 : : }
16841 : : hw_ctrl_rx = priv->hw_ctrl_rx;
16842 [ # # ]: 0 : for (i = 0; i < MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_MAX; ++i) {
16843 : : const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type = i;
16844 : :
16845 [ # # ]: 0 : if (!eth_pattern_type_is_requested(eth_pattern_type, flags))
16846 : 0 : continue;
16847 [ # # ]: 0 : for (j = 0; j < MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX; ++j) {
16848 : 0 : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type = j;
16849 : : struct rte_flow_actions_template *at;
16850 : : struct mlx5_flow_hw_ctrl_rx_table *tmpls = &hw_ctrl_rx->tables[i][j];
16851 : 0 : const struct mlx5_flow_template_table_cfg cfg = {
16852 : : .attr = tmpls->attr,
16853 : : .external = 0,
16854 : : };
16855 : :
16856 [ # # ]: 0 : if (!hw_ctrl_rx->rss[rss_type]) {
16857 : 0 : at = flow_hw_create_ctrl_rx_rss_template(dev, rss_type);
16858 [ # # ]: 0 : if (!at)
16859 : 0 : return -rte_errno;
16860 : 0 : hw_ctrl_rx->rss[rss_type] = at;
16861 : : } else {
16862 : 0 : at = hw_ctrl_rx->rss[rss_type];
16863 : : }
16864 [ # # ]: 0 : if (!rss_type_is_requested(priv, rss_type))
16865 : 0 : continue;
16866 [ # # ]: 0 : if (!tmpls->tbl) {
16867 : 0 : tmpls->tbl = flow_hw_table_create(dev, &cfg,
16868 : : &tmpls->pt, 1, &at, 1, NULL);
16869 [ # # ]: 0 : if (!tmpls->tbl) {
16870 : 0 : DRV_LOG(ERR, "port %u Failed to create template table "
16871 : : "for control flow rules. Unable to create "
16872 : : "control flow rules.",
16873 : : dev->data->port_id);
16874 : 0 : return -rte_errno;
16875 : : }
16876 : : }
16877 : :
16878 : 0 : ret = __flow_hw_ctrl_flows(dev, tmpls->tbl, eth_pattern_type, rss_type);
16879 [ # # ]: 0 : if (ret) {
16880 : 0 : DRV_LOG(ERR, "port %u Failed to create control flow rule.",
16881 : : dev->data->port_id);
16882 : 0 : return ret;
16883 : : }
16884 : : }
16885 : : }
16886 : : return 0;
16887 : : }
16888 : :
16889 : : static int
16890 : 0 : mlx5_flow_hw_ctrl_flow_single(struct rte_eth_dev *dev,
16891 : : const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type,
16892 : : const struct rte_ether_addr *addr,
16893 : : const uint16_t vlan)
16894 : : {
16895 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16896 : : struct mlx5_flow_hw_ctrl_rx *hw_ctrl_rx;
16897 : : unsigned int j;
16898 : : int ret = 0;
16899 : :
16900 [ # # ]: 0 : if (!priv->dr_ctx) {
16901 : 0 : DRV_LOG(DEBUG, "port %u Control flow rules will not be created. "
16902 : : "HWS needs to be configured beforehand.",
16903 : : dev->data->port_id);
16904 : 0 : return 0;
16905 : : }
16906 [ # # ]: 0 : if (!priv->hw_ctrl_rx) {
16907 : 0 : DRV_LOG(ERR, "port %u Control flow rules templates were not created.",
16908 : : dev->data->port_id);
16909 : 0 : rte_errno = EINVAL;
16910 : 0 : return -rte_errno;
16911 : : }
16912 : : hw_ctrl_rx = priv->hw_ctrl_rx;
16913 : :
16914 : : /* TODO: this part should be somehow refactored. It's common with common flow creation. */
16915 [ # # ]: 0 : for (j = 0; j < MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX; ++j) {
16916 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type = j;
16917 : : const unsigned int pti = eth_pattern_type;
16918 : : struct rte_flow_actions_template *at;
16919 : : struct mlx5_flow_hw_ctrl_rx_table *tmpls = &hw_ctrl_rx->tables[pti][j];
16920 : 0 : const struct mlx5_flow_template_table_cfg cfg = {
16921 : : .attr = tmpls->attr,
16922 : : .external = 0,
16923 : : };
16924 : :
16925 [ # # ]: 0 : if (!hw_ctrl_rx->rss[rss_type]) {
16926 : 0 : at = flow_hw_create_ctrl_rx_rss_template(dev, rss_type);
16927 [ # # ]: 0 : if (!at)
16928 : 0 : return -rte_errno;
16929 : 0 : hw_ctrl_rx->rss[rss_type] = at;
16930 : : } else {
16931 : 0 : at = hw_ctrl_rx->rss[rss_type];
16932 : : }
16933 [ # # ]: 0 : if (!rss_type_is_requested(priv, rss_type))
16934 : 0 : continue;
16935 [ # # ]: 0 : if (!tmpls->tbl) {
16936 : 0 : tmpls->tbl = flow_hw_table_create(dev, &cfg,
16937 : : &tmpls->pt, 1, &at, 1, NULL);
16938 [ # # ]: 0 : if (!tmpls->tbl) {
16939 : 0 : DRV_LOG(ERR, "port %u Failed to create template table "
16940 : : "for control flow rules. Unable to create "
16941 : : "control flow rules.",
16942 : : dev->data->port_id);
16943 : 0 : return -rte_errno;
16944 : : }
16945 : : }
16946 : :
16947 : : MLX5_ASSERT(eth_pattern_type == MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC ||
16948 : : eth_pattern_type == MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN);
16949 : :
16950 [ # # ]: 0 : if (eth_pattern_type == MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC)
16951 : 0 : ret = __flow_hw_ctrl_flows_unicast_create(dev, tmpls->tbl, rss_type, addr);
16952 : : else
16953 : 0 : ret = __flow_hw_ctrl_flows_unicast_vlan_create(dev, tmpls->tbl, rss_type,
16954 : : addr, vlan);
16955 [ # # ]: 0 : if (ret) {
16956 : 0 : DRV_LOG(ERR, "port %u Failed to create unicast control flow rule.",
16957 : : dev->data->port_id);
16958 : 0 : return ret;
16959 : : }
16960 : : }
16961 : :
16962 : : return 0;
16963 : : }
16964 : :
16965 : : int
16966 : 0 : mlx5_flow_hw_ctrl_flow_dmac(struct rte_eth_dev *dev,
16967 : : const struct rte_ether_addr *addr)
16968 : : {
16969 : 0 : return mlx5_flow_hw_ctrl_flow_single(dev, MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC,
16970 : : addr, 0);
16971 : : }
16972 : :
16973 : :
16974 : : int
16975 : 0 : mlx5_flow_hw_ctrl_flow_dmac_destroy(struct rte_eth_dev *dev,
16976 : : const struct rte_ether_addr *addr)
16977 : : {
16978 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16979 : : struct mlx5_ctrl_flow_entry *entry;
16980 : : struct mlx5_ctrl_flow_entry *tmp;
16981 : : int ret;
16982 : :
16983 : : /*
16984 : : * HWS does not have automatic RSS flow expansion,
16985 : : * so each variant of the control flow rule is a separate entry in the list.
16986 : : * In that case, the whole list must be traversed.
16987 : : */
16988 : 0 : entry = LIST_FIRST(&priv->hw_ctrl_flows);
16989 [ # # ]: 0 : while (entry != NULL) {
16990 : 0 : tmp = LIST_NEXT(entry, next);
16991 : :
16992 [ # # # # ]: 0 : if (entry->info.type != MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC ||
16993 : : !rte_is_same_ether_addr(addr, &entry->info.uc.dmac)) {
16994 : : entry = tmp;
16995 : 0 : continue;
16996 : : }
16997 : :
16998 : 0 : ret = flow_hw_destroy_ctrl_flow(dev, entry->flow);
16999 [ # # ]: 0 : LIST_REMOVE(entry, next);
17000 : 0 : mlx5_free(entry);
17001 [ # # ]: 0 : if (ret)
17002 : 0 : return ret;
17003 : :
17004 : : entry = tmp;
17005 : : }
17006 : : return 0;
17007 : : }
17008 : :
17009 : : int
17010 : 0 : mlx5_flow_hw_ctrl_flow_dmac_vlan(struct rte_eth_dev *dev,
17011 : : const struct rte_ether_addr *addr,
17012 : : const uint16_t vlan)
17013 : : {
17014 : 0 : return mlx5_flow_hw_ctrl_flow_single(dev, MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN,
17015 : : addr, vlan);
17016 : : }
17017 : :
17018 : : int
17019 : 0 : mlx5_flow_hw_ctrl_flow_dmac_vlan_destroy(struct rte_eth_dev *dev,
17020 : : const struct rte_ether_addr *addr,
17021 : : const uint16_t vlan)
17022 : : {
17023 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
17024 : : struct mlx5_ctrl_flow_entry *entry;
17025 : : struct mlx5_ctrl_flow_entry *tmp;
17026 : : int ret;
17027 : :
17028 : : /*
17029 : : * HWS does not have automatic RSS flow expansion,
17030 : : * so each variant of the control flow rule is a separate entry in the list.
17031 : : * In that case, the whole list must be traversed.
17032 : : */
17033 : 0 : entry = LIST_FIRST(&priv->hw_ctrl_flows);
17034 [ # # ]: 0 : while (entry != NULL) {
17035 : 0 : tmp = LIST_NEXT(entry, next);
17036 : :
17037 [ # # # # ]: 0 : if (entry->info.type != MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC_VLAN ||
17038 : 0 : !rte_is_same_ether_addr(addr, &entry->info.uc.dmac) ||
17039 [ # # ]: 0 : vlan != entry->info.uc.vlan) {
17040 : : entry = tmp;
17041 : 0 : continue;
17042 : : }
17043 : :
17044 : 0 : ret = flow_hw_destroy_ctrl_flow(dev, entry->flow);
17045 [ # # ]: 0 : LIST_REMOVE(entry, next);
17046 : 0 : mlx5_free(entry);
17047 [ # # ]: 0 : if (ret)
17048 : 0 : return ret;
17049 : :
17050 : : entry = tmp;
17051 : : }
17052 : : return 0;
17053 : : }
17054 : :
17055 : : struct mlx5_ecpri_parser_profile *
17056 : 0 : mlx5_flow_hw_get_ecpri_parser_profile(void *dr_ctx)
17057 : : {
17058 : : uint16_t port_id;
17059 : : bool found = false;
17060 : : struct mlx5_priv *priv;
17061 : :
17062 [ # # ]: 0 : MLX5_ETH_FOREACH_DEV(port_id, NULL) {
17063 : 0 : priv = rte_eth_devices[port_id].data->dev_private;
17064 [ # # ]: 0 : if (priv->dr_ctx == dr_ctx) {
17065 : : found = true;
17066 : : break;
17067 : : }
17068 : : }
17069 [ # # ]: 0 : if (found)
17070 : 0 : return &priv->sh->ecpri_parser;
17071 : 0 : rte_errno = ENODEV;
17072 : 0 : return NULL;
17073 : : }
17074 : :
17075 : :
17076 : : static __rte_always_inline uint32_t
17077 : : mlx5_reformat_domain_to_tbl_type(const struct rte_flow_indir_action_conf *domain,
17078 : : bool fdb_unified_en)
17079 : : {
17080 : : uint32_t tbl_type;
17081 : :
17082 [ # # ]: 0 : if (domain->transfer)
17083 : : tbl_type = (fdb_unified_en ?
17084 : : (MLX5DR_ACTION_FLAG_HWS_FDB_RX |
17085 : : MLX5DR_ACTION_FLAG_HWS_FDB_TX |
17086 [ # # ]: 0 : MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED) :
17087 : : MLX5DR_ACTION_FLAG_HWS_FDB);
17088 [ # # ]: 0 : else if (domain->egress)
17089 : : tbl_type = MLX5DR_ACTION_FLAG_HWS_TX;
17090 [ # # ]: 0 : else if (domain->ingress)
17091 : : tbl_type = MLX5DR_ACTION_FLAG_HWS_RX;
17092 : : else
17093 : : tbl_type = UINT32_MAX;
17094 : : return tbl_type;
17095 : : }
17096 : :
17097 : : static struct mlx5_hw_encap_decap_action *
17098 : 0 : __mlx5_reformat_create(struct rte_eth_dev *dev,
17099 : : const struct rte_flow_action_raw_encap *encap_conf,
17100 : : const struct rte_flow_indir_action_conf *domain,
17101 : : enum mlx5dr_action_type type)
17102 : : {
17103 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
17104 : : struct mlx5_hw_encap_decap_action *handle;
17105 : : struct mlx5dr_action_reformat_header hdr;
17106 : : uint32_t flags;
17107 : : bool unified_fdb = is_unified_fdb(priv);
17108 : :
17109 : : flags = mlx5_reformat_domain_to_tbl_type(domain, unified_fdb);
17110 : 0 : flags |= (uint32_t)MLX5DR_ACTION_FLAG_SHARED;
17111 [ # # ]: 0 : if (flags == UINT32_MAX) {
17112 : 0 : DRV_LOG(ERR, "Reformat: invalid indirect action configuration");
17113 : 0 : return NULL;
17114 : : }
17115 : : /* Allocate new list entry. */
17116 : 0 : handle = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*handle), 0, SOCKET_ID_ANY);
17117 [ # # ]: 0 : if (!handle) {
17118 : 0 : DRV_LOG(ERR, "Reformat: failed to allocate reformat entry");
17119 : 0 : return NULL;
17120 : : }
17121 : 0 : handle->action_type = type;
17122 [ # # ]: 0 : hdr.sz = encap_conf ? encap_conf->size : 0;
17123 [ # # ]: 0 : hdr.data = encap_conf ? encap_conf->data : NULL;
17124 : 0 : handle->action = mlx5dr_action_create_reformat(priv->dr_ctx,
17125 : : type, 1, &hdr, 0, flags);
17126 [ # # ]: 0 : if (!handle->action) {
17127 : 0 : DRV_LOG(ERR, "Reformat: failed to create reformat action");
17128 : 0 : mlx5_free(handle);
17129 : 0 : return NULL;
17130 : : }
17131 : : return handle;
17132 : : }
17133 : :
17134 : : /**
17135 : : * Create mlx5 reformat action.
17136 : : *
17137 : : * @param[in] dev
17138 : : * Pointer to rte_eth_dev structure.
17139 : : * @param[in] conf
17140 : : * Pointer to the indirect action parameters.
17141 : : * @param[in] encap_action
17142 : : * Pointer to the raw_encap action configuration.
17143 : : * @param[in] decap_action
17144 : : * Pointer to the raw_decap action configuration.
17145 : : * @param[out] error
17146 : : * Pointer to error structure.
17147 : : *
17148 : : * @return
17149 : : * A valid shared action handle in case of success, NULL otherwise and
17150 : : * rte_errno is set.
17151 : : */
17152 : : struct mlx5_hw_encap_decap_action*
17153 : 0 : mlx5_reformat_action_create(struct rte_eth_dev *dev,
17154 : : const struct rte_flow_indir_action_conf *conf,
17155 : : const struct rte_flow_action *encap_action,
17156 : : const struct rte_flow_action *decap_action,
17157 : : struct rte_flow_error *error)
17158 : : {
17159 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
17160 : : struct mlx5_hw_encap_decap_action *handle;
17161 : : const struct rte_flow_action_raw_encap *encap = NULL;
17162 : : const struct rte_flow_action_raw_decap *decap = NULL;
17163 : : enum mlx5dr_action_type type = MLX5DR_ACTION_TYP_LAST;
17164 : :
17165 : : MLX5_ASSERT(!encap_action || encap_action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP);
17166 : : MLX5_ASSERT(!decap_action || decap_action->type == RTE_FLOW_ACTION_TYPE_RAW_DECAP);
17167 [ # # ]: 0 : if (priv->sh->config.dv_flow_en != 2) {
17168 : 0 : rte_flow_error_set(error, ENOTSUP,
17169 : : RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
17170 : : "Reformat: hardware does not support");
17171 : 0 : return NULL;
17172 : : }
17173 [ # # # # ]: 0 : if (!conf || (conf->transfer + conf->egress + conf->ingress != 1)) {
17174 : 0 : rte_flow_error_set(error, EINVAL,
17175 : : RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
17176 : : "Reformat: domain should be specified");
17177 : 0 : return NULL;
17178 : : }
17179 [ # # # # : 0 : if ((encap_action && !encap_action->conf) || (decap_action && !decap_action->conf)) {
# # # # ]
17180 : 0 : rte_flow_error_set(error, EINVAL,
17181 : : RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
17182 : : "Reformat: missed action configuration");
17183 : 0 : return NULL;
17184 : : }
17185 [ # # ]: 0 : if (encap_action && !decap_action) {
17186 : 0 : encap = (const struct rte_flow_action_raw_encap *)encap_action->conf;
17187 [ # # ]: 0 : if (!encap->size || encap->size > MLX5_ENCAP_MAX_LEN ||
17188 : : encap->size < MLX5_ENCAPSULATION_DECISION_SIZE) {
17189 : 0 : rte_flow_error_set(error, EINVAL,
17190 : : RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
17191 : : "Reformat: Invalid encap length");
17192 : 0 : return NULL;
17193 : : }
17194 : : type = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;
17195 [ # # ]: 0 : } else if (decap_action && !encap_action) {
17196 : 0 : decap = (const struct rte_flow_action_raw_decap *)decap_action->conf;
17197 [ # # ]: 0 : if (!decap->size || decap->size < MLX5_ENCAPSULATION_DECISION_SIZE) {
17198 : 0 : rte_flow_error_set(error, EINVAL,
17199 : : RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
17200 : : "Reformat: Invalid decap length");
17201 : 0 : return NULL;
17202 : : }
17203 : : type = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2;
17204 [ # # ]: 0 : } else if (encap_action && decap_action) {
17205 : 0 : decap = (const struct rte_flow_action_raw_decap *)decap_action->conf;
17206 : 0 : encap = (const struct rte_flow_action_raw_encap *)encap_action->conf;
17207 [ # # ]: 0 : if (decap->size < MLX5_ENCAPSULATION_DECISION_SIZE &&
17208 [ # # # # ]: 0 : encap->size >= MLX5_ENCAPSULATION_DECISION_SIZE &&
17209 : : encap->size <= MLX5_ENCAP_MAX_LEN) {
17210 : : type = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3;
17211 [ # # ]: 0 : } else if (decap->size >= MLX5_ENCAPSULATION_DECISION_SIZE &&
17212 [ # # ]: 0 : encap->size < MLX5_ENCAPSULATION_DECISION_SIZE) {
17213 : : type = MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2;
17214 : : } else {
17215 : 0 : rte_flow_error_set(error, EINVAL,
17216 : : RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
17217 : : "Reformat: Invalid decap & encap length");
17218 : 0 : return NULL;
17219 : : }
17220 [ # # ]: 0 : } else if (!encap_action && !decap_action) {
17221 : 0 : rte_flow_error_set(error, EINVAL,
17222 : : RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
17223 : : "Reformat: Invalid decap & encap configurations");
17224 : 0 : return NULL;
17225 : : }
17226 [ # # ]: 0 : if (!priv->dr_ctx) {
17227 : 0 : rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
17228 : : encap_action, "Reformat: HWS not supported");
17229 : 0 : return NULL;
17230 : : }
17231 : 0 : handle = __mlx5_reformat_create(dev, encap, conf, type);
17232 [ # # ]: 0 : if (!handle) {
17233 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
17234 : : "Reformat: failed to create indirect action");
17235 : 0 : return NULL;
17236 : : }
17237 : : return handle;
17238 : : }
17239 : :
17240 : : /**
17241 : : * Destroy the indirect reformat action.
17242 : : * Release action related resources on the NIC and the memory.
17243 : : * Lock free, (mutex should be acquired by caller).
17244 : : *
17245 : : * @param[in] dev
17246 : : * Pointer to the Ethernet device structure.
17247 : : * @param[in] handle
17248 : : * The indirect action list handle to be removed.
17249 : : * @param[out] error
17250 : : * Perform verbose error reporting if not NULL. Initialized in case of
17251 : : * error only.
17252 : : *
17253 : : * @return
17254 : : * 0 on success, otherwise negative errno value.
17255 : : */
17256 : : int
17257 : 0 : mlx5_reformat_action_destroy(struct rte_eth_dev *dev,
17258 : : struct rte_flow_action_list_handle *handle,
17259 : : struct rte_flow_error *error)
17260 : : {
17261 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
17262 : : struct mlx5_hw_encap_decap_action *action;
17263 : :
17264 : : action = (struct mlx5_hw_encap_decap_action *)handle;
17265 [ # # # # ]: 0 : if (!priv->dr_ctx || !action)
17266 : 0 : return rte_flow_error_set(error, ENOTSUP,
17267 : : RTE_FLOW_ERROR_TYPE_ACTION, handle,
17268 : : "Reformat: invalid action handle");
17269 : 0 : mlx5dr_action_destroy(action->action);
17270 : 0 : mlx5_free(handle);
17271 : 0 : return 0;
17272 : : }
17273 : :
17274 : : static bool
17275 : 0 : flow_hw_is_item_masked(const struct rte_flow_item *item)
17276 : : {
17277 : : const uint8_t *byte;
17278 : : int size;
17279 : : int i;
17280 : :
17281 [ # # ]: 0 : if (item->mask == NULL)
17282 : : return false;
17283 : :
17284 [ # # ]: 0 : switch ((int)item->type) {
17285 : : case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
17286 : : size = sizeof(struct rte_flow_item_tag);
17287 : : break;
17288 : : case MLX5_RTE_FLOW_ITEM_TYPE_SQ:
17289 : : size = sizeof(struct mlx5_rte_flow_item_sq);
17290 : : break;
17291 : 0 : default:
17292 : 0 : size = rte_flow_conv(RTE_FLOW_CONV_OP_ITEM_MASK, NULL, 0, item, NULL);
17293 : : /*
17294 : : * Pattern template items are passed to this function.
17295 : : * These items were already validated, so error is not expected.
17296 : : * Also, if mask is NULL, then spec size is bigger than 0 always.
17297 : : */
17298 : : MLX5_ASSERT(size > 0);
17299 : : }
17300 : :
17301 : 0 : byte = (const uint8_t *)item->mask;
17302 [ # # ]: 0 : for (i = 0; i < size; ++i)
17303 [ # # ]: 0 : if (byte[i])
17304 : : return true;
17305 : :
17306 : : return false;
17307 : : }
17308 : :
17309 : : static int
17310 : 0 : flow_hw_validate_rule_pattern(struct rte_eth_dev *dev,
17311 : : const struct rte_flow_template_table *table,
17312 : : const uint8_t pattern_template_idx,
17313 : : const struct rte_flow_item items[],
17314 : : struct rte_flow_error *error)
17315 : : {
17316 : : const struct rte_flow_pattern_template *pt;
17317 : : const struct rte_flow_item *pt_item;
17318 : :
17319 [ # # ]: 0 : if (pattern_template_idx >= table->nb_item_templates)
17320 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17321 : : "Pattern template index out of range");
17322 : :
17323 : 0 : pt = table->its[pattern_template_idx];
17324 : 0 : pt_item = pt->items;
17325 : :
17326 : : /* If any item was prepended, skip it. */
17327 [ # # ]: 0 : if (pt->implicit_port || pt->implicit_tag)
17328 : 0 : pt_item++;
17329 : :
17330 [ # # ]: 0 : for (; pt_item->type != RTE_FLOW_ITEM_TYPE_END; pt_item++, items++) {
17331 [ # # ]: 0 : if (pt_item->type != items->type)
17332 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM,
17333 : : items, "Item type does not match the template");
17334 : :
17335 : : /*
17336 : : * Assumptions:
17337 : : * - Currently mlx5dr layer contains info on which fields in masks are supported.
17338 : : * - This info is not exposed to PMD directly.
17339 : : * - Because of that, it is assumed that since pattern template is correct,
17340 : : * then, items' masks in pattern template have nonzero values only in
17341 : : * supported fields.
17342 : : * This is known, because a temporary mlx5dr matcher is created during pattern
17343 : : * template creation to validate the template.
17344 : : * - As a result, it is safe to look for nonzero bytes in mask to determine if
17345 : : * item spec is needed in a flow rule.
17346 : : */
17347 [ # # ]: 0 : if (!flow_hw_is_item_masked(pt_item))
17348 : 0 : continue;
17349 : :
17350 [ # # ]: 0 : if (items->spec == NULL)
17351 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
17352 : : items, "Item spec is required");
17353 : :
17354 [ # # # # ]: 0 : switch (items->type) {
17355 : : const struct rte_flow_item_ethdev *ethdev;
17356 : : const struct rte_flow_item_tx_queue *tx_queue;
17357 : : const struct rte_flow_item_conntrack *spec;
17358 : : struct mlx5_txq_ctrl *txq;
17359 : :
17360 : 0 : case RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT:
17361 : : ethdev = items->spec;
17362 [ # # ]: 0 : if (flow_hw_validate_target_port_id(dev, ethdev->port_id)) {
17363 : 0 : return rte_flow_error_set(error, EINVAL,
17364 : : RTE_FLOW_ERROR_TYPE_ITEM_SPEC, items,
17365 : : "Invalid port");
17366 : : }
17367 : : break;
17368 : 0 : case RTE_FLOW_ITEM_TYPE_TX_QUEUE:
17369 : : tx_queue = items->spec;
17370 [ # # # # ]: 0 : if (mlx5_is_external_txq(dev, tx_queue->tx_queue))
17371 : 0 : continue;
17372 : 0 : txq = mlx5_txq_get(dev, tx_queue->tx_queue);
17373 [ # # ]: 0 : if (!txq)
17374 : 0 : return rte_flow_error_set(error, EINVAL,
17375 : : RTE_FLOW_ERROR_TYPE_ITEM_SPEC, items,
17376 : : "Invalid Tx queue");
17377 : 0 : mlx5_txq_release(dev, tx_queue->tx_queue);
17378 : 0 : break;
17379 : 0 : case RTE_FLOW_ITEM_TYPE_CONNTRACK:
17380 : : spec = items->spec;
17381 [ # # ]: 0 : if (spec->flags & ~MLX5_FLOW_CONNTRACK_PKT_STATE_ALL)
17382 : 0 : return rte_flow_error_set(error, EINVAL,
17383 : : RTE_FLOW_ERROR_TYPE_ITEM,
17384 : : NULL,
17385 : : "Invalid CT item flags");
17386 : : break;
17387 : : default:
17388 : : break;
17389 : : }
17390 : : }
17391 : :
17392 : : return 0;
17393 : : }
17394 : :
17395 : : static bool
17396 : 0 : flow_hw_valid_indirect_action_type(const struct rte_flow_action *user_action,
17397 : : const enum rte_flow_action_type expected_type)
17398 : : {
17399 : 0 : uint32_t user_indirect_type = MLX5_INDIRECT_ACTION_TYPE_GET(user_action->conf);
17400 : : uint32_t expected_indirect_type;
17401 : :
17402 [ # # # # : 0 : switch ((int)expected_type) {
# # # ]
17403 : : case RTE_FLOW_ACTION_TYPE_RSS:
17404 : : case MLX5_RTE_FLOW_ACTION_TYPE_RSS:
17405 : : expected_indirect_type = MLX5_INDIRECT_ACTION_TYPE_RSS;
17406 : : break;
17407 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
17408 : : case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
17409 : : expected_indirect_type = MLX5_INDIRECT_ACTION_TYPE_COUNT;
17410 : 0 : break;
17411 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
17412 : : expected_indirect_type = MLX5_INDIRECT_ACTION_TYPE_AGE;
17413 : 0 : break;
17414 : 0 : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
17415 : : expected_indirect_type = MLX5_INDIRECT_ACTION_TYPE_CT;
17416 : 0 : break;
17417 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
17418 : : case MLX5_RTE_FLOW_ACTION_TYPE_METER_MARK:
17419 : : expected_indirect_type = MLX5_INDIRECT_ACTION_TYPE_METER_MARK;
17420 : 0 : break;
17421 : 0 : case RTE_FLOW_ACTION_TYPE_QUOTA:
17422 : : expected_indirect_type = MLX5_INDIRECT_ACTION_TYPE_QUOTA;
17423 : 0 : break;
17424 : : default:
17425 : : return false;
17426 : : }
17427 : :
17428 : 0 : return user_indirect_type == expected_indirect_type;
17429 : : }
17430 : :
17431 : : static int
17432 : 0 : flow_hw_validate_rule_actions(struct rte_eth_dev *dev,
17433 : : const struct rte_flow_template_table *table,
17434 : : const uint8_t actions_template_idx,
17435 : : const struct rte_flow_action actions[],
17436 : : struct rte_flow_error *error)
17437 : : {
17438 : : const struct rte_flow_actions_template *at;
17439 : : const struct mlx5_hw_actions *hw_acts;
17440 : : const struct mlx5_action_construct_data *act_data;
17441 : : unsigned int idx;
17442 : :
17443 [ # # ]: 0 : if (actions_template_idx >= table->nb_action_templates)
17444 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17445 : : "Actions template index out of range");
17446 : :
17447 : 0 : at = table->ats[actions_template_idx].action_template;
17448 : : hw_acts = &table->ats[actions_template_idx].acts;
17449 : :
17450 [ # # ]: 0 : for (idx = 0; actions[idx].type != RTE_FLOW_ACTION_TYPE_END; ++idx) {
17451 : : const struct rte_flow_action *user_action = &actions[idx];
17452 : 0 : const struct rte_flow_action *tmpl_action = &at->orig_actions[idx];
17453 : :
17454 [ # # ]: 0 : if (user_action->type != tmpl_action->type)
17455 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
17456 : : user_action,
17457 : : "Action type does not match type specified in "
17458 : : "actions template");
17459 : : }
17460 : :
17461 : : /*
17462 : : * Only go through unmasked actions and check if configuration is provided.
17463 : : * Configuration of masked actions is ignored.
17464 : : */
17465 [ # # ]: 0 : LIST_FOREACH(act_data, &hw_acts->act_list, next) {
17466 : : const struct rte_flow_action *user_action;
17467 : :
17468 : 0 : user_action = &actions[act_data->action_src];
17469 : :
17470 : : /* Skip actions which do not require conf. */
17471 [ # # ]: 0 : switch ((int)act_data->type) {
17472 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
17473 : : case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
17474 : : case MLX5_RTE_FLOW_ACTION_TYPE_METER_MARK:
17475 : : case MLX5_RTE_FLOW_ACTION_TYPE_RSS:
17476 : 0 : continue;
17477 : : default:
17478 : : break;
17479 : : }
17480 : :
17481 [ # # ]: 0 : if (user_action->conf == NULL)
17482 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
17483 : : user_action,
17484 : : "Action requires configuration");
17485 : :
17486 [ # # # # : 0 : switch ((int)user_action->type) {
# # ]
17487 : : enum rte_flow_action_type expected_type;
17488 : : const struct rte_flow_action_ethdev *ethdev;
17489 : : const struct rte_flow_action_modify_field *mf;
17490 : :
17491 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT:
17492 : 0 : expected_type = act_data->indirect.expected_type;
17493 [ # # ]: 0 : if (!flow_hw_valid_indirect_action_type(user_action, expected_type))
17494 : 0 : return rte_flow_error_set(error, EINVAL,
17495 : : RTE_FLOW_ERROR_TYPE_ACTION_CONF,
17496 : : user_action,
17497 : : "Indirect action type does not match "
17498 : : "the type specified in the mask");
17499 : : break;
17500 : 0 : case RTE_FLOW_ACTION_TYPE_QUEUE:
17501 [ # # ]: 0 : if (mlx5_flow_validate_target_queue(dev, user_action, error))
17502 : 0 : return -rte_errno;
17503 : : break;
17504 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
17505 [ # # ]: 0 : if (mlx5_validate_action_rss(dev, user_action, error))
17506 : 0 : return -rte_errno;
17507 : : break;
17508 : 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
17509 : : /* TODO: Compare other fields if needed. */
17510 : : mf = user_action->conf;
17511 [ # # ]: 0 : if (mf->operation != act_data->modify_header.action.operation ||
17512 [ # # ]: 0 : mf->src.field != act_data->modify_header.action.src.field ||
17513 [ # # ]: 0 : mf->dst.field != act_data->modify_header.action.dst.field ||
17514 [ # # ]: 0 : mf->width != act_data->modify_header.action.width)
17515 : 0 : return rte_flow_error_set(error, EINVAL,
17516 : : RTE_FLOW_ERROR_TYPE_ACTION_CONF,
17517 : : user_action,
17518 : : "Modify field configuration does not "
17519 : : "match configuration from actions "
17520 : : "template");
17521 : : break;
17522 : 0 : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
17523 : : ethdev = user_action->conf;
17524 [ # # ]: 0 : if (flow_hw_validate_target_port_id(dev, ethdev->port_id)) {
17525 : 0 : return rte_flow_error_set(error, EINVAL,
17526 : : RTE_FLOW_ERROR_TYPE_ACTION_CONF,
17527 : : user_action, "Invalid port");
17528 : : }
17529 : : break;
17530 : : default:
17531 : : break;
17532 : : }
17533 : : }
17534 : :
17535 : : return 0;
17536 : : }
17537 : :
17538 : : static int
17539 : 0 : flow_hw_async_op_validate(struct rte_eth_dev *dev,
17540 : : const uint32_t queue,
17541 : : const struct rte_flow_template_table *table,
17542 : : struct rte_flow_error *error)
17543 : : {
17544 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
17545 : :
17546 : : MLX5_ASSERT(table != NULL);
17547 : :
17548 [ # # # # ]: 0 : if (table->cfg.external && queue >= priv->hw_attr->nb_queue)
17549 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17550 : : "Incorrect queue");
17551 : :
17552 : : return 0;
17553 : : }
17554 : :
17555 : : /**
17556 : : * Validate user input for rte_flow_async_create() implementation.
17557 : : *
17558 : : * If RTE_PMD_MLX5_DEBUG macro is not defined, this function is a no-op.
17559 : : *
17560 : : * @param[in] dev
17561 : : * Pointer to the rte_eth_dev structure.
17562 : : * @param[in] queue
17563 : : * The queue to create the flow.
17564 : : * @param[in] table
17565 : : * Pointer to template table.
17566 : : * @param[in] rule_index
17567 : : * The item pattern flow follows from the table.
17568 : : * @param[in] items
17569 : : * Items with flow spec value.
17570 : : * @param[in] pattern_template_index
17571 : : * The item pattern flow follows from the table.
17572 : : * @param[in] actions
17573 : : * Action with flow spec value.
17574 : : * @param[in] action_template_index
17575 : : * The action pattern flow follows from the table.
17576 : : * @param[out] error
17577 : : * Pointer to error structure.
17578 : : *
17579 : : * @return
17580 : : * 0 if user input is valid.
17581 : : * Negative errno otherwise, rte_errno and error struct is populated.
17582 : : */
17583 : : static int
17584 : 0 : flow_hw_async_create_validate(struct rte_eth_dev *dev,
17585 : : const uint32_t queue,
17586 : : const struct rte_flow_template_table *table,
17587 : : enum rte_flow_table_insertion_type insertion_type,
17588 : : uint32_t rule_index,
17589 : : const struct rte_flow_item items[],
17590 : : const uint8_t pattern_template_index,
17591 : : const struct rte_flow_action actions[],
17592 : : const uint8_t action_template_index,
17593 : : struct rte_flow_error *error)
17594 : : {
17595 [ # # ]: 0 : if (flow_hw_async_op_validate(dev, queue, table, error))
17596 : 0 : return -rte_errno;
17597 : :
17598 [ # # ]: 0 : if (insertion_type != table->cfg.attr.insertion_type)
17599 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
17600 : : NULL, "Flow rule insertion type mismatch with table configuration");
17601 : :
17602 [ # # ]: 0 : if (table->cfg.attr.insertion_type != RTE_FLOW_TABLE_INSERTION_TYPE_PATTERN)
17603 [ # # ]: 0 : if (rule_index >= table->cfg.attr.nb_flows)
17604 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
17605 : : NULL, "Flow rule index exceeds table size");
17606 : :
17607 [ # # ]: 0 : if (table->cfg.attr.insertion_type != RTE_FLOW_TABLE_INSERTION_TYPE_INDEX)
17608 [ # # ]: 0 : if (flow_hw_validate_rule_pattern(dev, table, pattern_template_index, items, error))
17609 : 0 : return -rte_errno;
17610 : :
17611 [ # # ]: 0 : if (flow_hw_validate_rule_actions(dev, table, action_template_index, actions, error))
17612 : 0 : return -rte_errno;
17613 : :
17614 : : return 0;
17615 : : }
17616 : :
17617 : : /**
17618 : : * Validate user input for rte_flow_async_update() implementation.
17619 : : *
17620 : : * If RTE_PMD_MLX5_DEBUG macro is not defined, this function is a no-op.
17621 : : *
17622 : : * @param[in] dev
17623 : : * Pointer to the rte_eth_dev structure.
17624 : : * @param[in] queue
17625 : : * The queue to create the flow.
17626 : : * @param[in] flow
17627 : : * Flow rule to be updated.
17628 : : * @param[in] actions
17629 : : * Action with flow spec value.
17630 : : * @param[in] action_template_index
17631 : : * The action pattern flow follows from the table.
17632 : : * @param[out] error
17633 : : * Pointer to error structure.
17634 : : *
17635 : : * @return
17636 : : * 0 if user input is valid.
17637 : : * Negative errno otherwise, rte_errno and error struct is set.
17638 : : */
17639 : : static int
17640 : 0 : flow_hw_async_update_validate(struct rte_eth_dev *dev,
17641 : : const uint32_t queue,
17642 : : const struct rte_flow_hw *flow,
17643 : : const struct rte_flow_action actions[],
17644 : : const uint8_t action_template_index,
17645 : : struct rte_flow_error *error)
17646 : : {
17647 [ # # ]: 0 : if (flow_hw_async_op_validate(dev, queue, flow->table, error))
17648 : 0 : return -rte_errno;
17649 : :
17650 [ # # ]: 0 : if (flow_hw_validate_rule_actions(dev, flow->table, action_template_index, actions, error))
17651 : 0 : return -rte_errno;
17652 : :
17653 : : return 0;
17654 : : }
17655 : :
17656 : : /**
17657 : : * Validate user input for rte_flow_async_destroy() implementation.
17658 : : *
17659 : : * If RTE_PMD_MLX5_DEBUG macro is not defined, this function is a no-op.
17660 : : *
17661 : : * @param[in] dev
17662 : : * Pointer to the rte_eth_dev structure.
17663 : : * @param[in] queue
17664 : : * The queue to create the flow.
17665 : : * @param[in] flow
17666 : : * Flow rule to be destroyed.
17667 : : * @param[out] error
17668 : : * Pointer to error structure.
17669 : : *
17670 : : * @return
17671 : : * 0 if user input is valid.
17672 : : * Negative errno otherwise, rte_errno and error struct is set.
17673 : : */
17674 : : static int
17675 : : flow_hw_async_destroy_validate(struct rte_eth_dev *dev,
17676 : : const uint32_t queue,
17677 : : const struct rte_flow_hw *flow,
17678 : : struct rte_flow_error *error)
17679 : : {
17680 : : if (flow_hw_async_op_validate(dev, queue, flow->table, error))
17681 : : return -rte_errno;
17682 : :
17683 : : return 0;
17684 : : }
17685 : :
17686 : : static struct rte_flow_fp_ops mlx5_flow_hw_fp_ops = {
17687 : : .async_create = flow_hw_async_flow_create,
17688 : : .async_create_by_index = flow_hw_async_flow_create_by_index,
17689 : : .async_create_by_index_with_pattern = flow_hw_async_flow_create_by_index_with_pattern,
17690 : : .async_actions_update = flow_hw_async_flow_update,
17691 : : .async_destroy = flow_hw_async_flow_destroy,
17692 : : .push = flow_hw_push,
17693 : : .pull = flow_hw_pull,
17694 : : .async_action_handle_create = flow_hw_action_handle_create,
17695 : : .async_action_handle_destroy = flow_hw_action_handle_destroy,
17696 : : .async_action_handle_update = flow_hw_action_handle_update,
17697 : : .async_action_handle_query = flow_hw_action_handle_query,
17698 : : .async_action_handle_query_update = flow_hw_async_action_handle_query_update,
17699 : : .async_action_list_handle_create = flow_hw_async_action_list_handle_create,
17700 : : .async_action_list_handle_destroy = flow_hw_async_action_list_handle_destroy,
17701 : : .async_action_list_handle_query_update =
17702 : : flow_hw_async_action_list_handle_query_update,
17703 : : };
17704 : :
17705 : : #endif
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