Branch data Line data Source code
1 : : /* SPDX-License-Identifier: BSD-3-Clause
2 : : * Copyright(c) 2024 Realtek Corporation. All rights reserved
3 : : */
4 : :
5 : : #include "../r8169_ethdev.h"
6 : : #include "../r8169_hw.h"
7 : : #include "../r8169_phy.h"
8 : : #include "rtl8127_mcu.h"
9 : :
10 : : /* For RTL8127, CFG_METHOD_91 */
11 : :
12 : : static void
13 : 0 : hw_init_rxcfg_8127(struct rtl_hw *hw)
14 : : {
15 [ # # ]: 0 : switch (hw->mcfg) {
16 : 0 : case CFG_METHOD_91:
17 : 0 : RTL_W32(hw, RxConfig, Rx_Fetch_Number_12 | Rx_Close_Multiple |
18 : : RxCfg_pause_slot_en | (RX_DMA_BURST_512 << RxCfgDMAShift));
19 : : break;
20 : : }
21 : 0 : }
22 : :
23 : : static void
24 : 0 : hw_ephy_config_8127(struct rtl_hw *hw)
25 : : {
26 [ # # ]: 0 : switch (hw->mcfg) {
27 : 0 : case CFG_METHOD_91:
28 : 0 : rtl_ephy_write(hw, 0x8088, 0x0064);
29 : 0 : rtl_ephy_write(hw, 0x8488, 0x0064);
30 : 0 : rtl_ephy_write(hw, 0x8888, 0x0064);
31 : 0 : rtl_ephy_write(hw, 0x8C88, 0x0064);
32 : 0 : rtl_ephy_write(hw, 0x8188, 0x0064);
33 : 0 : rtl_ephy_write(hw, 0x8588, 0x0064);
34 : 0 : rtl_ephy_write(hw, 0x8988, 0x0064);
35 : 0 : rtl_ephy_write(hw, 0x8D88, 0x0064);
36 : 0 : rtl_ephy_write(hw, 0x808C, 0x09B0);
37 : 0 : rtl_ephy_write(hw, 0x848C, 0x09B0);
38 : 0 : rtl_ephy_write(hw, 0x888C, 0x0F90);
39 : 0 : rtl_ephy_write(hw, 0x8C8C, 0x0F90);
40 : 0 : rtl_ephy_write(hw, 0x818C, 0x09B0);
41 : 0 : rtl_ephy_write(hw, 0x858C, 0x09B0);
42 : 0 : rtl_ephy_write(hw, 0x898C, 0x0F90);
43 : 0 : rtl_ephy_write(hw, 0x8D8C, 0x0F90);
44 : 0 : rtl_ephy_write(hw, 0x808A, 0x09B8);
45 : 0 : rtl_ephy_write(hw, 0x848A, 0x09B8);
46 : 0 : rtl_ephy_write(hw, 0x888A, 0x0F98);
47 : 0 : rtl_ephy_write(hw, 0x8C8A, 0x0F98);
48 : 0 : rtl_ephy_write(hw, 0x818A, 0x09B8);
49 : 0 : rtl_ephy_write(hw, 0x858A, 0x09B8);
50 : 0 : rtl_ephy_write(hw, 0x898A, 0x0F98);
51 : 0 : rtl_ephy_write(hw, 0x8D8A, 0x0F98);
52 : 0 : rtl_ephy_write(hw, 0x9020, 0x0080);
53 : 0 : rtl_ephy_write(hw, 0x9420, 0x0080);
54 : 0 : rtl_ephy_write(hw, 0x9820, 0x0080);
55 : 0 : rtl_ephy_write(hw, 0x9C20, 0x0080);
56 : 0 : rtl_ephy_write(hw, 0x901E, 0x0190);
57 : 0 : rtl_ephy_write(hw, 0x941E, 0x0190);
58 : 0 : rtl_ephy_write(hw, 0x981E, 0x0140);
59 : 0 : rtl_ephy_write(hw, 0x9C1E, 0x0140);
60 : 0 : rtl_ephy_write(hw, 0x901C, 0x0190);
61 : 0 : rtl_ephy_write(hw, 0x941C, 0x0190);
62 : 0 : rtl_ephy_write(hw, 0x981C, 0x0140);
63 : 0 : rtl_ephy_write(hw, 0x9C1C, 0x0140);
64 : :
65 : : /* Clear extended address */
66 : 0 : rtl8127_clear_ephy_ext_addr(hw);
67 : 0 : break;
68 : : default:
69 : : /* nothing to do */
70 : : break;
71 : : }
72 : 0 : }
73 : :
74 : : static void
75 : 0 : rtl8127_tgphy_irq_mask_and_ack(struct rtl_hw *hw)
76 : : {
77 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA4D2, 0x0000);
78 : 0 : (void)rtl_mdio_direct_read_phy_ocp(hw, 0xA4D4);
79 : 0 : }
80 : :
81 : : static void
82 : 0 : rtl_hw_phy_config_8127a_1(struct rtl_hw *hw)
83 : : {
84 : 0 : rtl8127_tgphy_irq_mask_and_ack(hw);
85 : :
86 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA442, BIT_11);
87 : :
88 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8415);
89 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x9300);
90 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x81A3);
91 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x0F00);
92 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x81AE);
93 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x0F00);
94 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x81B9);
95 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xB900);
96 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x83B0);
97 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xB87E, 0x0E00);
98 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x83C5);
99 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xB87E, 0x0E00);
100 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x83DA);
101 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xB87E, 0x0E00);
102 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x83EF);
103 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xB87E, 0x0E00);
104 : :
105 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBF38, 0x01F0, 0x0160);
106 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBF3A, 0x001F, 0x0014);
107 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xBF28, 0x6000);
108 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xBF2C, 0xC000);
109 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBF28, 0x1FFF, 0x0187);
110 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBF2A, 0x003F, 0x0003);
111 : :
112 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8173);
113 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8620);
114 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8175);
115 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8671);
116 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x817C);
117 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA438, BIT_13);
118 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8187);
119 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA438, BIT_13);
120 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8192);
121 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA438, BIT_13);
122 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x819D);
123 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA438, BIT_13);
124 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x81A8);
125 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA438, BIT_13);
126 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x81B3);
127 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA438, BIT_13);
128 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x81BE);
129 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA438, BIT_13);
130 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x817D);
131 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xA600);
132 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8188);
133 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xA600);
134 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8193);
135 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xA600);
136 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x819E);
137 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xA600);
138 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x81A9);
139 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x1400);
140 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x81B4);
141 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x1400);
142 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x81BF);
143 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xA600);
144 : :
145 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xAEAA, BIT_5 | BIT_3);
146 : :
147 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x84F0);
148 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x201C);
149 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x84F2);
150 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x3117);
151 : :
152 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xAEC6, 0x0000);
153 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xAE20, 0xFFFF);
154 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xAECE, 0xFFFF);
155 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xAED2, 0xFFFF);
156 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xAEC8, 0x0000);
157 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xAED0, BIT_0);
158 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xADB8, 0x0150);
159 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8197);
160 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x5000);
161 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8231);
162 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x5000);
163 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x82CB);
164 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x5000);
165 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x82CD);
166 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x5700);
167 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8233);
168 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x5700);
169 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8199);
170 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x5700);
171 : :
172 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x815A);
173 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0150);
174 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x81F4);
175 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0150);
176 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x828E);
177 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0150);
178 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x81B1);
179 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0000);
180 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x824B);
181 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0000);
182 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x82E5);
183 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0000);
184 : :
185 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x84F7);
186 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x2800);
187 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xAEC2, BIT_12);
188 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x81B3);
189 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0xAD00);
190 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x824D);
191 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0xAD00);
192 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x82E7);
193 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0xAD00);
194 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAE4E, 0x000F, 0x0001);
195 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x82CE);
196 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xF000, 0x4000);
197 : :
198 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x83A5);
199 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0400);
200 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x83A6);
201 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0400);
202 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x83A7);
203 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0400);
204 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x83A8);
205 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0400);
206 : :
207 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x84AC);
208 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0000);
209 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x84AE);
210 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0000);
211 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x84B0);
212 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0xF818);
213 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x84B2);
214 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x6000);
215 : :
216 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FFC);
217 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x6008);
218 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FFE);
219 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0xF4FF);
220 : :
221 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8015);
222 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xB87E, BIT_9);
223 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8016);
224 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xB87E, BIT_11);
225 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FE6);
226 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0800);
227 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FE4);
228 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x2114);
229 : :
230 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8647);
231 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0xA7B1);
232 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8649);
233 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0xBBCA);
234 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x864B);
235 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0xDC00);
236 : :
237 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8154);
238 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xC000, 0x4000);
239 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8158);
240 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xB87E, 0xC000);
241 : :
242 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x826C);
243 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0xFFFF);
244 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x826E);
245 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0xFFFF);
246 : :
247 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8872);
248 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0E00);
249 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8012);
250 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA438, BIT_11);
251 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8012);
252 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA438, BIT_14);
253 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xB576, BIT_0);
254 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x834A);
255 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x0700);
256 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8217);
257 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0x3F00, 0x2A00);
258 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x81B1);
259 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x0B00);
260 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FED);
261 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x4E00);
262 : :
263 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x88AC);
264 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x2300);
265 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xBF0C, 0x3800);
266 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x88DE);
267 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00);
268 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x80B4);
269 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x5195);
270 : :
271 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8370);
272 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8671);
273 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8372);
274 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x86C8);
275 : :
276 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8401);
277 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x86C8);
278 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8403);
279 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x86DA);
280 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8406);
281 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0x1800, 0x1000);
282 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8408);
283 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0x1800, 0x1000);
284 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x840A);
285 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0x1800, 0x1000);
286 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x840C);
287 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0x1800, 0x1000);
288 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x840E);
289 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0x1800, 0x1000);
290 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8410);
291 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0x1800, 0x1000);
292 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8412);
293 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0x1800, 0x1000);
294 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8414);
295 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0x1800, 0x1000);
296 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8416);
297 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0x1800, 0x1000);
298 : :
299 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x82BD);
300 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1F40);
301 : :
302 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBFB4, 0x07FF, 0x0328);
303 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xBFB6, 0x3E14);
304 : :
305 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x81C4);
306 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x003B);
307 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0086);
308 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00B7);
309 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00DB);
310 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00FE);
311 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00FE);
312 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00FE);
313 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00FE);
314 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00C3);
315 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0078);
316 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0047);
317 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0023);
318 : :
319 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x88D7);
320 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x01A0);
321 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x88D9);
322 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x01A0);
323 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FFA);
324 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x002A);
325 : :
326 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FEE);
327 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0xFFDF);
328 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FF0);
329 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0xFFFF);
330 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FF2);
331 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0A4A);
332 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FF4);
333 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0xAA5A);
334 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FF6);
335 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0A4A);
336 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FF8);
337 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0xAA5A);
338 : :
339 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x88D5);
340 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0200);
341 : :
342 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x84BB);
343 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x0A00);
344 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x84C0);
345 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x1600);
346 : :
347 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA430, BIT_1 | BIT_0);
348 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA442, BIT_7);
349 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA430, BIT_12);
350 : 0 : }
351 : :
352 : : static void
353 : 0 : hw_phy_config_8127(struct rtl_hw *hw)
354 : : {
355 [ # # ]: 0 : switch (hw->mcfg) {
356 : 0 : case CFG_METHOD_91:
357 : 0 : rtl_hw_phy_config_8127a_1(hw);
358 : 0 : break;
359 : : }
360 : 0 : }
361 : :
362 : : static void
363 : 0 : hw_mac_mcu_config_8127(struct rtl_hw *hw)
364 : : {
365 [ # # ]: 0 : if (hw->NotWrMcuPatchCode)
366 : : return;
367 : :
368 : 0 : rtl_hw_disable_mac_mcu_bps(hw);
369 : :
370 : : /* Get H/W mac mcu patch code version */
371 : 0 : hw->hw_mcu_patch_code_ver = rtl_get_hw_mcu_patch_code_ver(hw);
372 : :
373 [ # # ]: 0 : switch (hw->mcfg) {
374 : 0 : case CFG_METHOD_91:
375 : 0 : rtl_set_mac_mcu_8127a_1(hw);
376 : 0 : break;
377 : : }
378 : : }
379 : :
380 : : static void
381 : 0 : hw_phy_mcu_config_8127(struct rtl_hw *hw)
382 : : {
383 [ # # ]: 0 : switch (hw->mcfg) {
384 : 0 : case CFG_METHOD_91:
385 : 0 : rtl_set_phy_mcu_8127a_1(hw);
386 : 0 : break;
387 : : }
388 : 0 : }
389 : :
390 : : const struct rtl_hw_ops rtl8127_ops = {
391 : : .hw_init_rxcfg = hw_init_rxcfg_8127,
392 : : .hw_ephy_config = hw_ephy_config_8127,
393 : : .hw_phy_config = hw_phy_config_8127,
394 : : .hw_mac_mcu_config = hw_mac_mcu_config_8127,
395 : : .hw_phy_mcu_config = hw_phy_mcu_config_8127,
396 : : };
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