Branch data Line data Source code
1 : : /* SPDX-License-Identifier: BSD-3-Clause
2 : : * Copyright(c) 2024 Realtek Corporation. All rights reserved
3 : : */
4 : :
5 : : #include "../r8169_ethdev.h"
6 : : #include "../r8169_hw.h"
7 : : #include "../r8169_phy.h"
8 : : #include "rtl8126a_mcu.h"
9 : :
10 : : /* For RTL8126A, CFG_METHOD_70,71 */
11 : :
12 : : static void
13 : 0 : hw_init_rxcfg_8126a(struct rtl_hw *hw)
14 : : {
15 [ # # ]: 0 : switch (hw->mcfg) {
16 : 0 : case CFG_METHOD_70:
17 : : case CFG_METHOD_71:
18 : 0 : RTL_W32(hw, RxConfig, Rx_Fetch_Number_20 | Rx_Close_Multiple |
19 : : RxCfg_pause_slot_en | (RX_DMA_BURST_512 << RxCfgDMAShift));
20 : : break;
21 : : }
22 : 0 : }
23 : :
24 : : static void
25 : 0 : hw_ephy_config_8126a(struct rtl_hw *hw)
26 : : {
27 : : switch (hw->mcfg) {
28 : : case CFG_METHOD_70:
29 : : case CFG_METHOD_71:
30 : : /* nothing to do */
31 : : break;
32 : : }
33 : 0 : }
34 : :
35 : : static void
36 : 0 : rtl_hw_phy_config_8126a_2(struct rtl_hw *hw)
37 : : {
38 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA442, BIT_11);
39 : :
40 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80BF);
41 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xED00);
42 : :
43 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80CD);
44 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x1000);
45 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80D1);
46 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xC800);
47 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80D4);
48 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xC800);
49 : :
50 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80E1);
51 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x10CC);
52 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80E5);
53 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x4F0C);
54 : :
55 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8387);
56 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x4700);
57 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA80C, (BIT_7 | BIT_6), BIT_7);
58 : :
59 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xAC90, BIT_4);
60 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xAD2C, BIT_15);
61 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8321);
62 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x1100);
63 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xACF8, (BIT_3 | BIT_2));
64 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8183);
65 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x5900);
66 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xAD94, BIT_5);
67 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA654, BIT_11);
68 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xB648, BIT_14);
69 : :
70 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x839E);
71 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x2F00);
72 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x83F2);
73 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0800);
74 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xADA0, BIT_1);
75 : :
76 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x80F3);
77 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x9900);
78 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8126);
79 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0xC100);
80 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x893A);
81 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x8080);
82 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8647);
83 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0xE600);
84 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x862C);
85 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x1200);
86 : :
87 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x864A);
88 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0xE600);
89 : :
90 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x80A0);
91 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0xBCBC);
92 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x805E);
93 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0xBCBC);
94 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8056);
95 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x3077);
96 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8058);
97 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x5A00);
98 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8098);
99 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x3077);
100 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x809A);
101 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x5A00);
102 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8052);
103 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x3733);
104 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8094);
105 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x3733);
106 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x807F);
107 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x7C75);
108 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x803D);
109 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x7C75);
110 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8036);
111 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x3000);
112 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8078);
113 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x3000);
114 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8031);
115 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x3300);
116 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8073);
117 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x3300);
118 : :
119 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAE06, 0xFC00, 0x7C00);
120 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x89D1);
121 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0004);
122 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8FBD);
123 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x0A00);
124 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8FBE);
125 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0D09);
126 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x89CD);
127 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0F0F);
128 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x89CF);
129 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0F0F);
130 : :
131 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x83A4);
132 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x6600);
133 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x83A6);
134 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x6601);
135 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x83C0);
136 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x6600);
137 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x83C2);
138 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x6601);
139 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8414);
140 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x6600);
141 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8416);
142 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x6601);
143 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x83F8);
144 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x6600);
145 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x83FA);
146 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x6601);
147 : :
148 : 0 : rtl_set_phy_mcu_patch_request(hw);
149 : :
150 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBD96, 0x1F00, 0x1000);
151 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBF1C, 0x0007, 0x0007);
152 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xBFBE, BIT_15);
153 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBF40, 0x0380, 0x0280);
154 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBF90, BIT_7, (BIT_6 | BIT_5));
155 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBF90, BIT_4, (BIT_3 | BIT_2));
156 : 0 : rtl_clear_phy_mcu_patch_request(hw);
157 : :
158 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x843B);
159 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x2000);
160 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x843D);
161 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x2000);
162 : :
163 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xB516, 0x7F);
164 : :
165 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xBF80, (BIT_5 | BIT_4));
166 : :
167 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8188);
168 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0044);
169 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00A8);
170 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00D6);
171 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00EC);
172 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00F6);
173 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00FC);
174 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00FE);
175 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00FE);
176 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00BC);
177 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0058);
178 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x002A);
179 : :
180 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8015);
181 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0800);
182 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FFD);
183 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0000);
184 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FFF);
185 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x7F00);
186 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FFB);
187 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
188 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FE9);
189 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0002);
190 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FEF);
191 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x00A5);
192 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FF1);
193 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0106);
194 : :
195 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FE1);
196 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0102);
197 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FE3);
198 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0400);
199 : :
200 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA654, BIT_11);
201 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0XA65A, (BIT_1 | BIT_0));
202 : :
203 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xAC3A, 0x5851);
204 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0XAC3C, (BIT_15 | BIT_14 | BIT_12),
205 : : BIT_13);
206 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAC42, BIT_9, (BIT_8 | BIT_7 | BIT_6));
207 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xAC3E, (BIT_15 | BIT_14 | BIT_13));
208 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xAC42, (BIT_5 | BIT_4 | BIT_3));
209 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAC42, BIT_1, (BIT_2 | BIT_0));
210 : :
211 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xAC1A, 0x00DB);
212 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xADE4, 0x01B5);
213 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xAD9C, (BIT_11 | BIT_10));
214 : :
215 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x814B);
216 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x1100);
217 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x814D);
218 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x1100);
219 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x814F);
220 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0B00);
221 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8142);
222 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
223 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8144);
224 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
225 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8150);
226 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
227 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8118);
228 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0700);
229 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x811A);
230 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0700);
231 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x811C);
232 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0500);
233 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x810F);
234 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
235 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8111);
236 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
237 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x811D);
238 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
239 : :
240 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xAC36, BIT_12);
241 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xAD1C, BIT_8);
242 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xADE8, 0xFFC0, 0x1400);
243 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x864B);
244 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x9D00);
245 : :
246 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8F97);
247 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x003F);
248 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x3F02);
249 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x023C);
250 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x3B0A);
251 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1C00);
252 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
253 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
254 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
255 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
256 : :
257 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xAD9C, BIT_5);
258 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8122);
259 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0C00);
260 : :
261 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x82C8);
262 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03ED);
263 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03FF);
264 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0009);
265 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03FE);
266 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x000B);
267 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0021);
268 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03F7);
269 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03B8);
270 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03E0);
271 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0049);
272 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0049);
273 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03E0);
274 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03B8);
275 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03F7);
276 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0021);
277 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x000B);
278 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03FE);
279 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0009);
280 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03FF);
281 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03ED);
282 : :
283 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x80EF);
284 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0C00);
285 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x82A0);
286 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x000E);
287 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03FE);
288 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03ED);
289 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0006);
290 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x001A);
291 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03F1);
292 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03D8);
293 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0023);
294 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0054);
295 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0322);
296 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x00DD);
297 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03AB);
298 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03DC);
299 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0027);
300 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x000E);
301 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03E5);
302 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03F9);
303 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0012);
304 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0001);
305 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03F1);
306 : :
307 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8018);
308 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA438, BIT_13);
309 : :
310 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FE4);
311 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0000);
312 : :
313 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB54C, 0xFFC0, 0x3700);
314 : 0 : }
315 : :
316 : : static void
317 : 0 : rtl_hw_phy_config_8126a_3(struct rtl_hw *hw)
318 : : {
319 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA442, BIT_11);
320 : :
321 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8183);
322 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x5900);
323 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA654, BIT_11);
324 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xB648, BIT_14);
325 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xAD2C, BIT_15);
326 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xAD94, BIT_5);
327 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xADA0, BIT_1);
328 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAE06, (BIT_15 | BIT_14 |
329 : : BIT_13 | BIT_12 | BIT_11 | BIT_10),
330 : : (BIT_14 | BIT_13 | BIT_12 | BIT_11 | BIT_10));
331 : :
332 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8647);
333 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0xE600);
334 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8036);
335 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x3000);
336 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8078);
337 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x3000);
338 : :
339 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x89E9);
340 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00);
341 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FFD);
342 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
343 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FFE);
344 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0200);
345 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FFF);
346 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0400);
347 : :
348 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8018);
349 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x7700);
350 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8F9C);
351 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0005);
352 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
353 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00ED);
354 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0502);
355 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0B00);
356 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xD401);
357 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8FA8);
358 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x2900);
359 : :
360 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x814B);
361 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x1100);
362 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x814D);
363 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x1100);
364 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x814F);
365 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0B00);
366 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8142);
367 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
368 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8144);
369 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
370 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8150);
371 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
372 : :
373 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8118);
374 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0700);
375 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x811A);
376 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0700);
377 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x811C);
378 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0500);
379 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x810F);
380 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
381 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8111);
382 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
383 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x811D);
384 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
385 : :
386 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xAD1C, BIT_8);
387 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xADE8, (BIT_15 | BIT_14 |
388 : : BIT_13 | BIT_12 | BIT_11 | BIT_10 |
389 : : BIT_9 | BIT_8 | BIT_7 | BIT_6),
390 : : (BIT_12 | BIT_10));
391 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x864B);
392 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x9D00);
393 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x862C);
394 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x1200);
395 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8566);
396 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x003F);
397 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x3F02);
398 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x023C);
399 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x3B0A);
400 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1C00);
401 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
402 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
403 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
404 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
405 : :
406 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xAD9C, BIT_5);
407 : :
408 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8122);
409 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0C00);
410 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x82C8);
411 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03ED);
412 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03FF);
413 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0009);
414 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03FE);
415 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x000B);
416 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0021);
417 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03F7);
418 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03B8);
419 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03E0);
420 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0049);
421 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0049);
422 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03E0);
423 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03B8);
424 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03F7);
425 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0021);
426 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x000B);
427 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03FE);
428 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0009);
429 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03FF);
430 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03ED);
431 : :
432 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x80EF);
433 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0C00);
434 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x82A0);
435 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x000E);
436 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03FE);
437 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03ED);
438 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0006);
439 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x001A);
440 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03F1);
441 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03D8);
442 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0023);
443 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0054);
444 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0322);
445 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x00DD);
446 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03AB);
447 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03DC);
448 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0027);
449 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x000E);
450 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03E5);
451 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03F9);
452 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0012);
453 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0001);
454 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03F1);
455 : :
456 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA430, BIT_1 | BIT_0);
457 : :
458 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB54C, 0xFFC0, 0x3700);
459 : :
460 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xB648, BIT_6);
461 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8082);
462 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x5D00);
463 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x807C);
464 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x5000);
465 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x809D);
466 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x5000);
467 : 0 : }
468 : :
469 : : static void
470 : 0 : hw_phy_config_8126a(struct rtl_hw *hw)
471 : : {
472 [ # # # ]: 0 : switch (hw->mcfg) {
473 : 0 : case CFG_METHOD_70:
474 : 0 : rtl_hw_phy_config_8126a_2(hw);
475 : 0 : break;
476 : 0 : case CFG_METHOD_71:
477 : 0 : rtl_hw_phy_config_8126a_3(hw);
478 : 0 : break;
479 : : }
480 : 0 : }
481 : :
482 : : static void
483 : 0 : hw_mac_mcu_config_8126a(struct rtl_hw *hw)
484 : : {
485 [ # # ]: 0 : if (hw->NotWrMcuPatchCode)
486 : : return;
487 : :
488 : 0 : rtl_hw_disable_mac_mcu_bps(hw);
489 : :
490 : : /* Get H/W mac mcu patch code version */
491 : 0 : hw->hw_mcu_patch_code_ver = rtl_get_hw_mcu_patch_code_ver(hw);
492 : :
493 [ # # # ]: 0 : switch (hw->mcfg) {
494 : 0 : case CFG_METHOD_70:
495 : 0 : rtl_set_mac_mcu_8126a_2(hw);
496 : 0 : break;
497 : 0 : case CFG_METHOD_71:
498 : 0 : rtl_set_mac_mcu_8126a_3(hw);
499 : 0 : break;
500 : : }
501 : : }
502 : :
503 : : static void
504 : 0 : hw_phy_mcu_config_8126a(struct rtl_hw *hw)
505 : : {
506 [ # # # ]: 0 : switch (hw->mcfg) {
507 : 0 : case CFG_METHOD_70:
508 : 0 : rtl_set_phy_mcu_8126a_2(hw);
509 : 0 : break;
510 : 0 : case CFG_METHOD_71:
511 : 0 : rtl_set_phy_mcu_8126a_3(hw);
512 : 0 : break;
513 : : }
514 : 0 : }
515 : :
516 : : const struct rtl_hw_ops rtl8126a_ops = {
517 : : .hw_init_rxcfg = hw_init_rxcfg_8126a,
518 : : .hw_ephy_config = hw_ephy_config_8126a,
519 : : .hw_phy_config = hw_phy_config_8126a,
520 : : .hw_mac_mcu_config = hw_mac_mcu_config_8126a,
521 : : .hw_phy_mcu_config = hw_phy_mcu_config_8126a,
522 : : };
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