Branch data Line data Source code
1 : : /* SPDX-License-Identifier: BSD-3-Clause
2 : : * Copyright(c) 2024 Realtek Corporation. All rights reserved
3 : : */
4 : :
5 : : #include "../r8169_ethdev.h"
6 : : #include "../r8169_hw.h"
7 : : #include "../r8169_phy.h"
8 : : #include "rtl8125d_mcu.h"
9 : :
10 : : /*
11 : : * For RTL8125D, CFG_METHOD_56,57
12 : : * For RTL8168KD, CFG_METHOD_59
13 : : * For RTL8125K, CFG_METHOD_61
14 : : */
15 : :
16 : : static void
17 : 0 : hw_init_rxcfg_8125d(struct rtl_hw *hw)
18 : : {
19 : 0 : RTL_W32(hw, RxConfig, Rx_Fetch_Number_8 | Rx_Close_Multiple |
20 : : RxCfg_pause_slot_en | (RX_DMA_BURST_256 << RxCfgDMAShift));
21 : 0 : }
22 : :
23 : : static void
24 : 0 : hw_ephy_config_8125d(struct rtl_hw *hw)
25 : : {
26 : : switch (hw->mcfg) {
27 : : case CFG_METHOD_56:
28 : : case CFG_METHOD_57:
29 : : case CFG_METHOD_59:
30 : : case CFG_METHOD_61:
31 : : /* Nothing to do */
32 : : break;
33 : : }
34 : 0 : }
35 : :
36 : : static void
37 : 0 : rtl_hw_phy_config_8125d_1(struct rtl_hw *hw)
38 : : {
39 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA442, BIT_11);
40 : :
41 : 0 : rtl_set_phy_mcu_patch_request(hw);
42 : :
43 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xBF96, BIT_15);
44 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBF94, 0x0007, 0x0005);
45 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBF8E, 0x3C00, 0x2800);
46 : :
47 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBCD8, 0xC000, 0x4000);
48 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xBCD8, BIT_15 | BIT_14);
49 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBCD8, 0xC000, 0x4000);
50 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBC80, 0x001F, 0x0004);
51 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xBC82, BIT_15 | BIT_14 | BIT_13);
52 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xBC82, BIT_12 | BIT_11 | BIT_10);
53 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBC80, 0x001F, 0x0005);
54 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBC82, 0x00E0, 0x0040);
55 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xBC82, BIT_4 | BIT_3 | BIT_2);
56 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xBCD8, BIT_15 | BIT_14);
57 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBCD8, 0xC000, 0x8000);
58 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xBCD8, BIT_15 | BIT_14);
59 : :
60 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xBD70, BIT_8);
61 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA466, BIT_1);
62 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x836a);
63 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA438, 0xFF00);
64 : :
65 : 0 : rtl_clear_phy_mcu_patch_request(hw);
66 : :
67 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x832C);
68 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0500);
69 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB106, 0x0700, 0x0100);
70 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB206, 0x0700, 0x0200);
71 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB306, 0x0700, 0x0300);
72 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x80CB);
73 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0300);
74 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xBCF4, 0x0000);
75 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xBCF6, 0x0000);
76 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xBC12, 0x0000);
77 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x844d);
78 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0200);
79 [ # # ]: 0 : if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(hw)) {
80 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8feb);
81 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
82 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8fe9);
83 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0600);
84 : : }
85 : :
86 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAC7E, 0x01FC, 0x00B4);
87 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8105);
88 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x7A00);
89 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8117);
90 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x3A00);
91 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8103);
92 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x7400);
93 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8115);
94 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x3400);
95 : :
96 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xAD40, BIT_5 | BIT_4);
97 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAD66, 0x000F, 0x0007);
98 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAD68, 0xF000, 0x8000);
99 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAD68, 0x0F00, 0x0500);
100 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAD68, 0x000F, 0x0002);
101 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAD6A, 0xF000, 0x7000);
102 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xAC50, 0x01E8);
103 : :
104 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x81FA);
105 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x5400);
106 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA864, 0x00F0, 0x00C0);
107 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA42C, 0x00FF, 0x0002);
108 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80E1);
109 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x0F00);
110 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80DE);
111 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xF000, 0x0700);
112 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA846, BIT_7);
113 : :
114 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80BA);
115 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8A04);
116 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80BD);
117 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xCA00);
118 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80B7);
119 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xB300);
120 : :
121 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80CE);
122 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8A04);
123 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80D1);
124 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xCA00);
125 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80CB);
126 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xBB00);
127 : :
128 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80A6);
129 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x4909);
130 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80A8);
131 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x05B8);
132 : :
133 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8200);
134 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x5800);
135 : :
136 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8FF1);
137 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x7078);
138 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8FF3);
139 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x5D78);
140 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8FF5);
141 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x7862);
142 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8FF7);
143 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x1400);
144 : :
145 [ # # ]: 0 : if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(hw)) {
146 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x814C);
147 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8455);
148 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x814E);
149 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x84A6);
150 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8163);
151 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x0600);
152 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x816A);
153 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x0500);
154 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8171);
155 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x1f00);
156 : : }
157 : :
158 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBC3A, 0x000F, 0x0006);
159 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8064);
160 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA438, BIT_10 | BIT_9 | BIT_8);
161 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8067);
162 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA438, BIT_10 | BIT_9 | BIT_8);
163 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x806A);
164 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA438, BIT_10 | BIT_9 | BIT_8);
165 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x806D);
166 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA438, BIT_10 | BIT_9 | BIT_8);
167 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8070);
168 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA438, BIT_10 | BIT_9 | BIT_8);
169 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8073);
170 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA438, BIT_10 | BIT_9 | BIT_8);
171 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8076);
172 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA438, BIT_10 | BIT_9 | BIT_8);
173 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8079);
174 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA438, BIT_10 | BIT_9 | BIT_8);
175 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x807C);
176 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA438, BIT_10 | BIT_9 | BIT_8);
177 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x807F);
178 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA438, BIT_10 | BIT_9 | BIT_8);
179 : :
180 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBFA0, 0xFF70, 0x5500);
181 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xBFA2, 0x9D00);
182 : :
183 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8165);
184 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0x0700, 0x0200);
185 : :
186 [ # # ]: 0 : if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(hw)) {
187 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8019);
188 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA438, BIT_8);
189 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8FE3);
190 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0005);
191 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
192 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00ED);
193 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0502);
194 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0B00);
195 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xD401);
196 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x2900);
197 : : }
198 : :
199 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8018);
200 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x1700);
201 : :
202 [ # # ]: 0 : if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(hw)) {
203 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x815B);
204 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x1700);
205 : : }
206 : :
207 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA4E0, BIT_15);
208 : :
209 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA5D4, BIT_5);
210 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA654, BIT_11);
211 : :
212 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA430, BIT_12 | BIT_0);
213 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA442, BIT_7);
214 : 0 : }
215 : :
216 : : static void
217 : 0 : rtl_hw_phy_config_8125d_2(struct rtl_hw *hw)
218 : : {
219 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA442, BIT_11);
220 : :
221 : 0 : rtl_set_phy_mcu_patch_request(hw);
222 : :
223 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBCD8, 0xC000, 0x4000);
224 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xBCD8, BIT_15 | BIT_14);
225 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBCD8, 0xC000, 0x4000);
226 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBC80, 0x001F, 0x0004);
227 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xBC82, BIT_15 | BIT_14 | BIT_13);
228 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xBC82, BIT_12 | BIT_11 | BIT_10);
229 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBC80, 0x001F, 0x0005);
230 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBC82, 0x00E0, 0x0040);
231 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xBC82, BIT_4 | BIT_3 | BIT_2);
232 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xBCD8, BIT_15 | BIT_14);
233 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBCD8, 0xC000, 0x8000);
234 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xBCD8, BIT_15 | BIT_14);
235 : :
236 : 0 : rtl_clear_phy_mcu_patch_request(hw);
237 : :
238 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAC7E, 0x01FC, 0x00B4);
239 : :
240 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8105);
241 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x7A00);
242 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8117);
243 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x3A00);
244 : :
245 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8103);
246 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x7400);
247 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8115);
248 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x3400);
249 : :
250 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FEB);
251 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0500);
252 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FEA);
253 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0700);
254 : :
255 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x80D6);
256 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0xEF00);
257 : :
258 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA5D4, BIT_5);
259 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA654, BIT_11);
260 : :
261 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA448, BIT_10);
262 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA586, BIT_10);
263 : :
264 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA4E0, BIT_15);
265 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8155);
266 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x0200);
267 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x815C);
268 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x0200);
269 : :
270 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA430, BIT_12 | BIT_0);
271 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA442, BIT_7);
272 : 0 : }
273 : :
274 : : static void
275 : 0 : hw_phy_config_8125d(struct rtl_hw *hw)
276 : : {
277 [ # # # ]: 0 : switch (hw->mcfg) {
278 : 0 : case CFG_METHOD_56:
279 : 0 : rtl_hw_phy_config_8125d_1(hw);
280 : 0 : break;
281 : 0 : case CFG_METHOD_57:
282 : : case CFG_METHOD_59:
283 : : case CFG_METHOD_61:
284 : 0 : rtl_hw_phy_config_8125d_2(hw);
285 : 0 : break;
286 : : }
287 : 0 : }
288 : :
289 : : static void
290 : 0 : hw_mac_mcu_config_8125d(struct rtl_hw *hw)
291 : : {
292 [ # # ]: 0 : if (hw->NotWrMcuPatchCode)
293 : : return;
294 : :
295 : 0 : rtl_hw_disable_mac_mcu_bps(hw);
296 : :
297 : : /* Get H/W mac mcu patch code version */
298 : 0 : hw->hw_mcu_patch_code_ver = rtl_get_hw_mcu_patch_code_ver(hw);
299 : :
300 [ # # # ]: 0 : switch (hw->mcfg) {
301 : 0 : case CFG_METHOD_56:
302 : 0 : rtl_set_mac_mcu_8125d_1(hw);
303 : 0 : break;
304 : 0 : case CFG_METHOD_57:
305 : : case CFG_METHOD_59:
306 : 0 : rtl_set_mac_mcu_8125d_2(hw);
307 : 0 : break;
308 : : default:
309 : : /* no mac mcu patch code */
310 : : break;
311 : : }
312 : : }
313 : :
314 : : static void
315 : 0 : hw_phy_mcu_config_8125d(struct rtl_hw *hw)
316 : : {
317 [ # # # ]: 0 : switch (hw->mcfg) {
318 : 0 : case CFG_METHOD_56:
319 : 0 : rtl_set_phy_mcu_8125d_1(hw);
320 : 0 : break;
321 : 0 : case CFG_METHOD_57:
322 : : case CFG_METHOD_59:
323 : : case CFG_METHOD_61:
324 : 0 : rtl_set_phy_mcu_8125d_2(hw);
325 : 0 : break;
326 : : }
327 : 0 : }
328 : :
329 : : const struct rtl_hw_ops rtl8125d_ops = {
330 : : .hw_init_rxcfg = hw_init_rxcfg_8125d,
331 : : .hw_ephy_config = hw_ephy_config_8125d,
332 : : .hw_phy_config = hw_phy_config_8125d,
333 : : .hw_mac_mcu_config = hw_mac_mcu_config_8125d,
334 : : .hw_phy_mcu_config = hw_phy_mcu_config_8125d,
335 : : };
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