Branch data Line data Source code
1 : : /* SPDX-License-Identifier: BSD-3-Clause
2 : : * Copyright 2015 6WIND S.A.
3 : : * Copyright 2015 Mellanox Technologies, Ltd
4 : : */
5 : :
6 : : #ifndef RTE_PMD_MLX5_H_
7 : : #define RTE_PMD_MLX5_H_
8 : :
9 : : #include <stddef.h>
10 : : #include <stdbool.h>
11 : : #include <stdint.h>
12 : : #include <limits.h>
13 : : #include <sys/queue.h>
14 : :
15 : : #include <rte_pci.h>
16 : : #include <rte_ether.h>
17 : : #include <ethdev_driver.h>
18 : : #include <rte_rwlock.h>
19 : : #include <rte_interrupts.h>
20 : : #include <rte_errno.h>
21 : : #include <rte_flow.h>
22 : : #include <rte_mtr.h>
23 : :
24 : : #include <mlx5_glue.h>
25 : : #include <mlx5_devx_cmds.h>
26 : : #include <mlx5_prm.h>
27 : : #include <mlx5_common_mp.h>
28 : : #include <mlx5_common_mr.h>
29 : : #include <mlx5_common_devx.h>
30 : : #include <mlx5_common_defs.h>
31 : :
32 : : #include "mlx5_defs.h"
33 : : #include "mlx5_utils.h"
34 : : #include "mlx5_os.h"
35 : : #include "mlx5_autoconf.h"
36 : : #include "rte_pmd_mlx5.h"
37 : : #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
38 : : #ifndef RTE_EXEC_ENV_WINDOWS
39 : : #define HAVE_MLX5_HWS_SUPPORT 1
40 : : #endif
41 : : #include "hws/mlx5dr.h"
42 : : #include "mlx5_hws_global_actions.h"
43 : : #endif
44 : :
45 : : #define MLX5_SH(dev) (((struct mlx5_priv *)(dev)->data->dev_private)->sh)
46 : :
47 : : #define MLX5_HW_INV_QUEUE UINT32_MAX
48 : :
49 : : /*
50 : : * The default ipool threshold value indicates which per_core_cache
51 : : * value to set.
52 : : */
53 : : #define MLX5_HW_IPOOL_SIZE_THRESHOLD (1 << 19)
54 : : /* The default min local cache size. */
55 : : #define MLX5_HW_IPOOL_CACHE_MIN (1 << 9)
56 : :
57 : : /*
58 : : * Number of modification commands.
59 : : * The maximal actions amount in FW is some constant, and it is 16 in the
60 : : * latest releases. In some old releases, it will be limited to 8.
61 : : * Since there is no interface to query the capacity, the maximal value should
62 : : * be used to allow PMD to create the flow. The validation will be done in the
63 : : * lower driver layer or FW. A failure will be returned if exceeds the maximal
64 : : * supported actions number on the root table.
65 : : * On non-root tables, there is no limitation, but 32 is enough right now.
66 : : */
67 : : #define MLX5_MAX_MODIFY_NUM 32
68 : : #define MLX5_ROOT_TBL_MODIFY_NUM 16
69 : :
70 : : /* Maximal number of flex items created on the port.*/
71 : : #define MLX5_PORT_FLEX_ITEM_NUM 8
72 : :
73 : : /* Maximal number of field/field parts to map into sample registers .*/
74 : : #define MLX5_FLEX_ITEM_MAPPING_NUM 32
75 : :
76 : : /* Number of bytes not included in MTU. */
77 : : #define MLX5_ETH_OVERHEAD (RTE_ETHER_HDR_LEN + RTE_VLAN_HLEN + RTE_ETHER_CRC_LEN)
78 : :
79 : : /* Minimum allowed MTU to be reported whenever PMD cannot query it from OS. */
80 : : #define MLX5_ETH_MIN_MTU (RTE_ETHER_MIN_MTU)
81 : :
82 : : /* Maximum allowed MTU to be reported whenever PMD cannot query it from OS. */
83 : : #define MLX5_ETH_MAX_MTU (9978)
84 : :
85 : : enum mlx5_ipool_index {
86 : : #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
87 : : MLX5_IPOOL_DECAP_ENCAP = 0, /* Pool for encap/decap resource. */
88 : : MLX5_IPOOL_PUSH_VLAN, /* Pool for push vlan resource. */
89 : : MLX5_IPOOL_TAG, /* Pool for tag resource. */
90 : : MLX5_IPOOL_PORT_ID, /* Pool for port id resource. */
91 : : MLX5_IPOOL_JUMP, /* Pool for SWS jump resource. */
92 : : /* Pool for HWS group. Jump action will be created internally. */
93 : : MLX5_IPOOL_HW_GRP = MLX5_IPOOL_JUMP,
94 : : MLX5_IPOOL_SAMPLE, /* Pool for sample resource. */
95 : : MLX5_IPOOL_DEST_ARRAY, /* Pool for destination array resource. */
96 : : MLX5_IPOOL_TUNNEL_ID, /* Pool for tunnel offload context */
97 : : MLX5_IPOOL_TNL_TBL_ID, /* Pool for tunnel table ID. */
98 : : #endif
99 : : MLX5_IPOOL_MTR, /* Pool for meter resource. */
100 : : MLX5_IPOOL_MCP, /* Pool for metadata resource. */
101 : : MLX5_IPOOL_HRXQ, /* Pool for hrxq resource. */
102 : : MLX5_IPOOL_MLX5_FLOW, /* Pool for mlx5 flow handle. */
103 : : MLX5_IPOOL_RTE_FLOW, /* Pool for rte_flow. */
104 : : MLX5_IPOOL_RSS_EXPANTION_FLOW_ID, /* Pool for Queue/RSS flow ID. */
105 : : MLX5_IPOOL_RSS_SHARED_ACTIONS, /* Pool for RSS shared actions. */
106 : : MLX5_IPOOL_MTR_POLICY, /* Pool for meter policy resource. */
107 : : MLX5_IPOOL_MAX,
108 : : };
109 : :
110 : : /*
111 : : * There are three reclaim memory mode supported.
112 : : * 0(none) means no memory reclaim.
113 : : * 1(light) means only PMD level reclaim.
114 : : * 2(aggressive) means both PMD and rdma-core level reclaim.
115 : : */
116 : : enum mlx5_reclaim_mem_mode {
117 : : MLX5_RCM_NONE, /* Don't reclaim memory. */
118 : : MLX5_RCM_LIGHT, /* Reclaim PMD level. */
119 : : MLX5_RCM_AGGR, /* Reclaim PMD and rdma-core level. */
120 : : };
121 : :
122 : : /* The type of flow. */
123 : : enum mlx5_flow_type {
124 : : MLX5_FLOW_TYPE_CTL, /* Control flow. */
125 : : MLX5_FLOW_TYPE_GEN, /* General flow. */
126 : : MLX5_FLOW_TYPE_MCP, /* MCP flow. */
127 : : MLX5_FLOW_TYPE_MAXI,
128 : : };
129 : :
130 : : /* The mode of delay drop for Rx queues. */
131 : : enum mlx5_delay_drop_mode {
132 : : MLX5_DELAY_DROP_NONE = 0, /* All disabled. */
133 : : MLX5_DELAY_DROP_STANDARD = RTE_BIT32(0), /* Standard queues enable. */
134 : : MLX5_DELAY_DROP_HAIRPIN = RTE_BIT32(1), /* Hairpin queues enable. */
135 : : };
136 : :
137 : : /* The HWS action type root/non-root. */
138 : : enum mlx5_hw_action_flag_type {
139 : : MLX5_HW_ACTION_FLAG_ROOT, /* Root action. */
140 : : MLX5_HW_ACTION_FLAG_NONE_ROOT, /* Non-root ation. */
141 : : MLX5_HW_ACTION_FLAG_MAX, /* Maximum action flag. */
142 : : };
143 : :
144 : : /* Hlist and list callback context. */
145 : : struct mlx5_flow_cb_ctx {
146 : : struct rte_eth_dev *dev;
147 : : struct rte_flow_error *error;
148 : : void *data;
149 : : void *data2;
150 : : };
151 : :
152 : : struct flow_hw_port_info {
153 : : uint32_t regc_mask;
154 : : uint32_t regc_value;
155 : : uint32_t is_wire:1;
156 : : uint32_t direction:2;
157 : : };
158 : :
159 : : enum mlx5_vport_direction {
160 : : MLX5_VPORT_DIRECTION_ANY = 0,
161 : : MLX5_VPORT_DIRECTION_NORTH,
162 : : MLX5_VPORT_DIRECTION_SOUTH,
163 : : };
164 : :
165 : : /* Device capabilities structure which isn't changed in any stage. */
166 : : struct mlx5_dev_cap {
167 : : int max_cq; /* Maximum number of supported CQs */
168 : : int max_qp; /* Maximum number of supported QPs. */
169 : : int max_qp_wr; /* Maximum number of outstanding WR on any WQ. */
170 : : int max_sge;
171 : : /* Maximum number of s/g per WR for SQ & RQ of QP for non RDMA Read
172 : : * operations.
173 : : */
174 : : int mps; /* Multi-packet send supported mode. */
175 : : uint32_t vf:1; /* This is a VF. */
176 : : uint32_t sf:1; /* This is a SF. */
177 : : uint32_t txpp_en:1; /* Tx packet pacing is supported. */
178 : : uint32_t mpls_en:1; /* MPLS over GRE/UDP is supported. */
179 : : uint32_t cqe_comp:1; /* CQE compression is supported. */
180 : : uint32_t hw_csum:1; /* Checksum offload is supported. */
181 : : uint32_t hw_padding:1; /* End alignment padding is supported. */
182 : : uint32_t dest_tir:1; /* Whether advanced DR API is available. */
183 : : uint32_t dv_esw_en:1; /* E-Switch DV flow is supported. */
184 : : uint32_t dv_flow_en:1; /* DV flow is supported. */
185 : : uint32_t swp:3; /* Tx generic tunnel checksum and TSO offload. */
186 : : uint32_t hw_vlan_strip:1; /* VLAN stripping is supported. */
187 : : uint32_t scatter_fcs_w_decap_disable:1;
188 : : /* HW has bug working with tunnel packet decap and scatter FCS. */
189 : : uint32_t hw_fcs_strip:1; /* FCS stripping is supported. */
190 : : uint32_t rt_timestamp:1; /* Realtime timestamp format. */
191 : : uint32_t rq_delay_drop_en:1; /* Enable RxQ delay drop. */
192 : : uint32_t tunnel_en:3;
193 : : /* Whether tunnel stateless offloads are supported. */
194 : : uint32_t ind_table_max_size;
195 : : /* Maximum receive WQ indirection table size. */
196 : : uint32_t tso:1; /* Whether TSO is supported. */
197 : : uint32_t tso_max_payload_sz; /* Maximum TCP payload for TSO. */
198 : : struct {
199 : : uint32_t enabled:1; /* Whether MPRQ is enabled. */
200 : : uint32_t log_min_stride_size; /* Log min size of a stride. */
201 : : uint32_t log_max_stride_size; /* Log max size of a stride. */
202 : : uint32_t log_min_stride_num; /* Log min num of strides. */
203 : : uint32_t log_max_stride_num; /* Log max num of strides. */
204 : : uint32_t log_min_stride_wqe_size;
205 : : /* Log min WQE size, (size of single stride)*(num of strides).*/
206 : : } mprq; /* Capability for Multi-Packet RQ. */
207 : : char fw_ver[64]; /* Firmware version of this device. */
208 : : struct flow_hw_port_info esw_info; /* E-switch manager reg_c0. */
209 : : };
210 : :
211 : : #define MLX5_MPESW_PORT_INVALID (-1)
212 : :
213 : : /** Data associated with devices to spawn. */
214 : : struct mlx5_dev_spawn_data {
215 : : uint32_t ifindex; /**< Network interface index. */
216 : : uint32_t max_port; /**< Device maximal port index. */
217 : : uint32_t nb_uplinks; /**< Number of uplinks associated with IB device. */
218 : : uint32_t nb_hpfs; /**< Number of host PFs associated with IB device. */
219 : : uint32_t phys_port; /**< Device physical port index. */
220 : : int pf_bond; /**< bonding device PF index. < 0 - no bonding */
221 : : int mpesw_port; /**< MPESW uplink index. Valid if mpesw_owner_port >= 0. */
222 : : struct mlx5_switch_info info; /**< Switch information. */
223 : : const char *phys_dev_name; /**< Name of physical device. */
224 : : struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */
225 : : struct rte_pci_device *pci_dev; /**< Backend PCI device. */
226 : : struct mlx5_common_device *cdev; /**< Backend common device. */
227 : : struct mlx5_bond_info *bond_info;
228 : : };
229 : :
230 : : /**
231 : : * Check if the port requested to be probed is MPESW physical device
232 : : * or a representor port.
233 : : *
234 : : * @param spawn
235 : : * Parameters of the probed port.
236 : : *
237 : : * @return
238 : : * True if the probed port is a physical device or representor in MPESW setup.
239 : : * False otherwise or MPESW was not configured.
240 : : */
241 : : static inline bool
242 : : mlx5_is_probed_port_on_mpesw_device(struct mlx5_dev_spawn_data *spawn)
243 : : {
244 : : return spawn->mpesw_port >= 0;
245 : : }
246 : :
247 : : /** Data associated with socket messages. */
248 : : struct __rte_packed_begin mlx5_flow_dump_req {
249 : : uint32_t port_id; /**< There are plans in DPDK to extend port_id. */
250 : : uint64_t flow_id;
251 : : } __rte_packed_end;
252 : :
253 : : struct mlx5_flow_dump_ack {
254 : : int rc; /**< Return code. */
255 : : };
256 : :
257 : : LIST_HEAD(mlx5_dev_list, mlx5_dev_ctx_shared);
258 : :
259 : : /* Shared data between primary and secondary processes. */
260 : : struct mlx5_shared_data {
261 : : rte_spinlock_t lock;
262 : : /* Global spinlock for primary and secondary processes. */
263 : : int init_done; /* Whether primary has done initialization. */
264 : : unsigned int secondary_cnt; /* Number of secondary processes init'd. */
265 : : };
266 : :
267 : : /* Per-process data structure, not visible to other processes. */
268 : : struct mlx5_local_data {
269 : : int init_done; /* Whether a secondary has done initialization. */
270 : : };
271 : :
272 : : extern struct mlx5_shared_data *mlx5_shared_data;
273 : :
274 : : int mlx5_xstats_enable(struct rte_eth_dev *dev, uint64_t id);
275 : : int mlx5_xstats_disable(struct rte_eth_dev *dev, uint64_t id);
276 : : int mlx5_xstats_query_state(struct rte_eth_dev *dev, uint64_t id);
277 : :
278 : : /* Dev ops structs */
279 : : extern const struct eth_dev_ops mlx5_dev_ops;
280 : : extern const struct eth_dev_ops mlx5_dev_sec_ops;
281 : : extern const struct eth_dev_ops mlx5_dev_ops_isolate;
282 : :
283 : : typedef int (*mlx5_enable_counter_t)(struct rte_eth_dev *dev, uint64_t id);
284 : : typedef int (*mlx5_disable_counter_t)(struct rte_eth_dev *dev, uint64_t id);
285 : :
286 : : struct mlx5_stat_counter_ctrl {
287 : : mlx5_enable_counter_t enable;
288 : : mlx5_disable_counter_t disable;
289 : : uint32_t enabled;
290 : : };
291 : :
292 : : struct mlx5_counter_ctrl {
293 : : /* Name of the counter. */
294 : : char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE];
295 : : /* Name of the counter on the device table. */
296 : : char ctr_name[RTE_ETH_XSTATS_NAME_SIZE];
297 : : uint32_t dev:1; /**< Nonzero for dev counters. */
298 : : struct mlx5_stat_counter_ctrl ctrl;
299 : : };
300 : :
301 : : struct mlx5_xstats_ctrl {
302 : : /* Number of device stats. */
303 : : uint16_t stats_n;
304 : : /* Number of device stats, for the 2nd port in bond. */
305 : : uint16_t stats_n_2nd;
306 : : /* Number of device stats identified by PMD. */
307 : : uint16_t mlx5_stats_n;
308 : : /* First device counters index. */
309 : : uint16_t dev_cnt_start;
310 : : /* Index in the device counters table. */
311 : : uint16_t dev_table_idx[MLX5_MAX_XSTATS];
312 : : /* Index in the output table. */
313 : : uint16_t xstats_o_idx[MLX5_MAX_XSTATS];
314 : : uint64_t base[MLX5_MAX_XSTATS];
315 : : uint64_t xstats[MLX5_MAX_XSTATS];
316 : : uint64_t hw_stats[MLX5_MAX_XSTATS];
317 : : struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS];
318 : : /* Index in the device counters table, for the 2nd port in bond. */
319 : : uint16_t dev_table_idx_2nd[MLX5_MAX_XSTATS];
320 : : /* Index in the output table, for the 2nd port in bond. */
321 : : uint16_t xstats_o_idx_2nd[MLX5_MAX_XSTATS];
322 : : };
323 : :
324 : : /* xstats array size. */
325 : : extern const unsigned int xstats_n;
326 : :
327 : : struct mlx5_stats_ctrl {
328 : : /* Base for imissed counter. */
329 : : uint64_t imissed_base;
330 : : uint64_t imissed;
331 : : };
332 : :
333 : : /* Maximal size of coalesced segment for LRO is set in chunks of 256 Bytes. */
334 : : #define MLX5_LRO_SEG_CHUNK_SIZE 256u
335 : :
336 : : /* Maximal size of aggregated LRO packet. */
337 : : #define MLX5_MAX_LRO_SIZE (UINT8_MAX * MLX5_LRO_SEG_CHUNK_SIZE)
338 : :
339 : : /* Maximal number of segments to split. */
340 : : #define MLX5_MAX_RXQ_NSEG (1u << MLX5_MAX_LOG_RQ_SEGS)
341 : :
342 : : /*
343 : : * Port configuration structure.
344 : : * User device parameters disabled features.
345 : : * This structure contains all configurations coming from devargs which
346 : : * oriented to port. When probing again, devargs doesn't have to be compatible
347 : : * with primary devargs. It is updated for each port in spawn function.
348 : : */
349 : : struct mlx5_port_config {
350 : : unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */
351 : : unsigned int hw_padding:1; /* End alignment padding is supported. */
352 : : unsigned int cqe_comp:1; /* CQE compression is enabled. */
353 : : unsigned int enh_cqe_comp:1; /* Enhanced CQE compression is enabled. */
354 : : unsigned int cqe_comp_fmt:3; /* CQE compression format. */
355 : : unsigned int rx_vec_en:1; /* Rx vector is enabled. */
356 : : unsigned int std_delay_drop:1; /* Enable standard Rxq delay drop. */
357 : : unsigned int hp_delay_drop:1; /* Enable hairpin Rxq delay drop. */
358 : : struct {
359 : : unsigned int enabled:1; /* Whether MPRQ is enabled. */
360 : : unsigned int log_stride_num; /* Log number of strides. */
361 : : unsigned int log_stride_size; /* Log size of a stride. */
362 : : unsigned int max_memcpy_len;
363 : : /* Maximum packet size to memcpy Rx packets. */
364 : : unsigned int min_rxqs_num;
365 : : /* Rx queue count threshold to enable MPRQ. */
366 : : } mprq; /* Configurations for Multi-Packet RQ. */
367 : : int mps; /* Multi-packet send supported mode. */
368 : : unsigned int max_dump_files_num; /* Maximum dump files per queue. */
369 : : unsigned int log_hp_size; /* Single hairpin queue data size in total. */
370 : : unsigned int lro_timeout; /* LRO user configuration. */
371 : : int txqs_inline; /* Queue number threshold for inlining. */
372 : : int txq_inline_min; /* Minimal amount of data bytes to inline. */
373 : : int txq_inline_max; /* Max packet size for inlining with SEND. */
374 : : int txq_inline_mpw; /* Max packet size for inlining with eMPW. */
375 : : };
376 : :
377 : : /*
378 : : * Share context device configuration structure.
379 : : * User device parameters disabled features.
380 : : * This structure updated once for device in mlx5_alloc_shared_dev_ctx()
381 : : * function and cannot change even when probing again.
382 : : */
383 : : struct mlx5_sh_config {
384 : : int tx_pp; /* Timestamp scheduling granularity in nanoseconds. */
385 : : int tx_skew; /* Tx scheduling skew between WQE and data on wire. */
386 : : uint32_t reclaim_mode:2; /* Memory reclaim mode. */
387 : : uint32_t dv_esw_en:1; /* Enable E-Switch DV flow. */
388 : : /* Enable DV flow. 1 means SW steering, 2 means HW steering. */
389 : : uint32_t dv_flow_en:2; /* Enable DV flow. */
390 : : uint32_t dv_xmeta_en:3; /* Enable extensive flow metadata. */
391 : : uint32_t dv_miss_info:1; /* Restore packet after partial hw miss. */
392 : : uint32_t l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */
393 : : uint32_t vf_nl_en:1; /* Enable Netlink requests in VF mode. */
394 : : uint32_t lacp_by_user:1; /* Enable user to manage LACP traffic. */
395 : : uint32_t decap_en:1; /* Whether decap will be used or not. */
396 : : uint32_t hw_fcs_strip:1; /* FCS stripping is supported. */
397 : : uint32_t allow_duplicate_pattern:1;
398 : : uint32_t lro_allowed:1; /* Whether LRO is allowed. */
399 : : /* Allow/Prevent the duplicate rules pattern. */
400 : : uint32_t fdb_def_rule:1; /* Create FDB default jump rule */
401 : : uint32_t txq_mem_algn; /* logarithm value of the TxQ address alignment. */
402 : : struct {
403 : : uint16_t service_core;
404 : : uint32_t cycle_time; /* query cycle time in milli-second. */
405 : : } cnt_svc; /* configure for HW steering's counter's service. */
406 : : };
407 : :
408 : : /* Structure for VF VLAN workaround. */
409 : : struct mlx5_vf_vlan {
410 : : uint32_t tag:12;
411 : : uint32_t created:1;
412 : : };
413 : :
414 : : /* Flow drop context necessary due to Verbs API. */
415 : : struct mlx5_drop {
416 : : struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */
417 : : struct mlx5_rxq_priv *rxq; /* Rx queue. */
418 : : };
419 : :
420 : : /* Loopback dummy queue resources required due to Verbs API. */
421 : : struct mlx5_lb_ctx {
422 : : struct ibv_qp *qp; /* QP object. */
423 : : void *ibv_cq; /* Completion queue. */
424 : : RTE_ATOMIC(uint16_t) refcnt; /* Reference count for representors. */
425 : : };
426 : :
427 : : /* External queue descriptor. */
428 : : struct mlx5_external_q {
429 : : uint32_t hw_id; /* Queue index in the Hardware. */
430 : : RTE_ATOMIC(uint32_t) refcnt; /* Reference counter. */
431 : : };
432 : :
433 : : /* HW steering queue job descriptor type. */
434 : : enum mlx5_hw_job_type {
435 : : MLX5_HW_Q_JOB_TYPE_CREATE, /* Flow create job type. */
436 : : MLX5_HW_Q_JOB_TYPE_DESTROY, /* Flow destroy job type. */
437 : : MLX5_HW_Q_JOB_TYPE_UPDATE, /* Flow update job type. */
438 : : MLX5_HW_Q_JOB_TYPE_QUERY, /* Flow query job type. */
439 : : MLX5_HW_Q_JOB_TYPE_UPDATE_QUERY, /* Flow update and query job type. */
440 : : MLX5_HW_Q_JOB_TYPE_RSZTBL_FLOW_CREATE, /* Non-optimized flow create job type. */
441 : : MLX5_HW_Q_JOB_TYPE_RSZTBL_FLOW_DESTROY, /* Non-optimized destroy create job type. */
442 : : MLX5_HW_Q_JOB_TYPE_RSZTBL_FLOW_MOVE, /* Move flow after table resize. */
443 : : };
444 : :
445 : : enum mlx5_hw_indirect_type {
446 : : MLX5_HW_INDIRECT_TYPE_LEGACY,
447 : : MLX5_HW_INDIRECT_TYPE_LIST
448 : : };
449 : :
450 : : #define MLX5_HW_MAX_ITEMS (16)
451 : :
452 : : #define MLX5_MHDR_MAX_CMD ((MLX5_MAX_MODIFY_NUM) * 2 + 1)
453 : : #define MLX5_PUSH_MAX_LEN 128
454 : : #define MLX5_ENCAP_MAX_LEN 132
455 : :
456 : : /** Container for flow action data constructed during flow rule creation. */
457 : : struct mlx5_flow_hw_action_params {
458 : : /** Array of constructed modify header commands. */
459 : : struct mlx5_modification_cmd mhdr_cmd[MLX5_MHDR_MAX_CMD];
460 : : /** Constructed encap/decap data buffer. */
461 : : uint8_t encap_data[MLX5_ENCAP_MAX_LEN];
462 : : /** Constructed IPv6 routing data buffer. */
463 : : uint8_t ipv6_push_data[MLX5_PUSH_MAX_LEN];
464 : : };
465 : :
466 : : /** Container for dynamically generated flow items used during flow rule creation. */
467 : : struct mlx5_flow_hw_pattern_params {
468 : : /** Array of dynamically generated flow items. */
469 : : struct rte_flow_item items[MLX5_HW_MAX_ITEMS];
470 : : /** Temporary REPRESENTED_PORT item generated by PMD. */
471 : : struct rte_flow_item_ethdev port_spec;
472 : : /** Temporary TAG item generated by PMD. */
473 : : struct rte_flow_item_tag tag_spec;
474 : : };
475 : :
476 : : /* HW steering flow management job descriptor. */
477 : : struct mlx5_hw_q_job {
478 : : uint32_t type; /* Job type. */
479 : : uint32_t indirect_type;
480 : : const void *action; /* Indirect action attached to the job. */
481 : : void *user_data; /* Job user data. */
482 : : struct {
483 : : /* User memory for query output */
484 : : void *user;
485 : : /* Data extracted from hardware */
486 : : void *hw;
487 : : } query;
488 : : };
489 : :
490 : : /* HW steering job descriptor LIFO pool. */
491 : : struct __rte_cache_aligned mlx5_hw_q {
492 : : uint32_t job_idx; /* Free job index. */
493 : : uint32_t size; /* Job LIFO queue size. */
494 : : uint32_t ongoing_flow_ops; /* Number of ongoing flow operations. */
495 : : struct mlx5_hw_q_job **job; /* LIFO header. */
496 : : struct rte_ring *indir_cq; /* Indirect action SW completion queue. */
497 : : struct rte_ring *indir_iq; /* Indirect action SW in progress queue. */
498 : : struct rte_ring *flow_transfer_pending;
499 : : struct rte_ring *flow_transfer_completed;
500 : : /* Action's ARGUMENT resource buffer for rule creation. */
501 : : struct mlx5_flow_hw_action_params ap;
502 : : /* Holds spec value for any implicitly added item. */
503 : : struct mlx5_flow_hw_pattern_params pp;
504 : : };
505 : :
506 : :
507 : : #define MLX5_COUNTER_POOLS_MAX_NUM (1 << 15)
508 : : #define MLX5_COUNTERS_PER_POOL 512
509 : : #define MLX5_MAX_PENDING_QUERIES 4
510 : : #define MLX5_CNT_MR_ALLOC_BULK 64
511 : : #define MLX5_CNT_SHARED_OFFSET 0x80000000
512 : : #define MLX5_CNT_SIZE (sizeof(struct mlx5_flow_counter))
513 : : #define MLX5_AGE_SIZE (sizeof(struct mlx5_age_param))
514 : :
515 : : #define MLX5_CNT_LEN(pool) \
516 : : (MLX5_CNT_SIZE + \
517 : : ((pool)->is_aged ? MLX5_AGE_SIZE : 0))
518 : : #define MLX5_POOL_GET_CNT(pool, index) \
519 : : ((struct mlx5_flow_counter *) \
520 : : ((uint8_t *)((pool) + 1) + (index) * (MLX5_CNT_LEN(pool))))
521 : : #define MLX5_CNT_ARRAY_IDX(pool, cnt) \
522 : : ((int)(((uint8_t *)(cnt) - (uint8_t *)((pool) + 1)) / \
523 : : MLX5_CNT_LEN(pool)))
524 : : #define MLX5_TS_MASK_SECS 8ull
525 : : /* timestamp wrapping in seconds, must be power of 2. */
526 : :
527 : : /*
528 : : * The pool index and offset of counter in the pool array makes up the
529 : : * counter index. In case the counter is from pool 0 and offset 0, it
530 : : * should plus 1 to avoid index 0, since 0 means invalid counter index
531 : : * currently.
532 : : */
533 : : #define MLX5_MAKE_CNT_IDX(pi, offset) \
534 : : ((pi) * MLX5_COUNTERS_PER_POOL + (offset) + 1)
535 : : #define MLX5_CNT_TO_AGE(cnt) \
536 : : ((struct mlx5_age_param *)((cnt) + 1))
537 : : /*
538 : : * The maximum single counter is 0x800000 as MLX5_CNT_BATCH_OFFSET
539 : : * defines. The pool size is 512, pool index should never reach
540 : : * INT16_MAX.
541 : : */
542 : : #define POOL_IDX_INVALID UINT16_MAX
543 : :
544 : : /* Age status. */
545 : : enum {
546 : : AGE_FREE, /* Initialized state. */
547 : : AGE_CANDIDATE, /* Counter assigned to flows. */
548 : : AGE_TMOUT, /* Timeout, wait for rte_flow_get_aged_flows and destroy. */
549 : : };
550 : :
551 : : enum mlx5_counter_type {
552 : : MLX5_COUNTER_TYPE_ORIGIN,
553 : : MLX5_COUNTER_TYPE_AGE,
554 : : MLX5_COUNTER_TYPE_MAX,
555 : : };
556 : :
557 : : /* Counter age parameter. */
558 : : struct mlx5_age_param {
559 : : RTE_ATOMIC(uint16_t) state; /**< Age state (atomically accessed). */
560 : : uint16_t port_id; /**< Port id of the counter. */
561 : : uint32_t timeout:24; /**< Aging timeout in seconds. */
562 : : RTE_ATOMIC(uint32_t) sec_since_last_hit;
563 : : /**< Time in seconds since last hit (atomically accessed). */
564 : : void *context; /**< Flow counter age context. */
565 : : };
566 : :
567 : : struct flow_counter_stats {
568 : : uint64_t hits;
569 : : uint64_t bytes;
570 : : };
571 : :
572 : : /* Shared counters information for counters. */
573 : : struct mlx5_flow_counter_shared {
574 : : union {
575 : : RTE_ATOMIC(uint32_t) refcnt; /* Only for shared action management. */
576 : : uint32_t id; /* User counter ID for legacy sharing. */
577 : : };
578 : : };
579 : :
580 : : struct mlx5_flow_counter_pool;
581 : : /* Generic counters information. */
582 : : struct mlx5_flow_counter {
583 : : union {
584 : : /*
585 : : * User-defined counter shared info is only used during
586 : : * counter active time. And aging counter sharing is not
587 : : * supported, so active shared counter will not be chained
588 : : * to the aging list. For shared counter, only when it is
589 : : * released, the TAILQ entry memory will be used, at that
590 : : * time, shared memory is not used anymore.
591 : : *
592 : : * Similarly to none-batch counter dcs, since it doesn't
593 : : * support aging, while counter is allocated, the entry
594 : : * memory is not used anymore. In this case, as bytes
595 : : * memory is used only when counter is allocated, and
596 : : * entry memory is used only when counter is free. The
597 : : * dcs pointer can be saved to these two different place
598 : : * at different stage. It will eliminate the individual
599 : : * counter extend struct.
600 : : */
601 : : TAILQ_ENTRY(mlx5_flow_counter) next;
602 : : /**< Pointer to the next flow counter structure. */
603 : : struct {
604 : : struct mlx5_flow_counter_shared shared_info;
605 : : /**< Shared counter information. */
606 : : void *dcs_when_active;
607 : : /*
608 : : * For non-batch mode, the dcs will be saved
609 : : * here when the counter is free.
610 : : */
611 : : };
612 : : };
613 : : union {
614 : : uint64_t hits; /**< Reset value of hits packets. */
615 : : struct mlx5_flow_counter_pool *pool; /**< Counter pool. */
616 : : };
617 : : union {
618 : : uint64_t bytes; /**< Reset value of bytes. */
619 : : void *dcs_when_free;
620 : : /*
621 : : * For non-batch mode, the dcs will be saved here
622 : : * when the counter is free.
623 : : */
624 : : };
625 : : void *action; /**< Pointer to the dv action. */
626 : : };
627 : :
628 : : TAILQ_HEAD(mlx5_counters, mlx5_flow_counter);
629 : :
630 : : /* Generic counter pool structure - query is in pool resolution. */
631 : : struct mlx5_flow_counter_pool {
632 : : TAILQ_ENTRY(mlx5_flow_counter_pool) next;
633 : : struct mlx5_counters counters[2]; /* Free counter list. */
634 : : struct mlx5_devx_obj *min_dcs;
635 : : /* The devx object of the minimum counter ID. */
636 : : uint64_t time_of_last_age_check;
637 : : /* System time (from rte_rdtsc()) read in the last aging check. */
638 : : uint32_t index:30; /* Pool index in container. */
639 : : uint32_t is_aged:1; /* Pool with aging counter. */
640 : : volatile uint32_t query_gen:1; /* Query round. */
641 : : rte_spinlock_t sl; /* The pool lock. */
642 : : rte_spinlock_t csl; /* The pool counter free list lock. */
643 : : struct mlx5_counter_stats_raw *raw;
644 : : struct mlx5_counter_stats_raw *raw_hw;
645 : : /* The raw on HW working. */
646 : : };
647 : :
648 : : /* Memory management structure for group of counter statistics raws. */
649 : : struct mlx5_counter_stats_mem_mng {
650 : : LIST_ENTRY(mlx5_counter_stats_mem_mng) next;
651 : : struct mlx5_counter_stats_raw *raws;
652 : : struct mlx5_pmd_wrapped_mr wm;
653 : : };
654 : :
655 : : /* Raw memory structure for the counter statistics values of a pool. */
656 : : struct mlx5_counter_stats_raw {
657 : : LIST_ENTRY(mlx5_counter_stats_raw) next;
658 : : struct mlx5_counter_stats_mem_mng *mem_mng;
659 : : volatile struct flow_counter_stats *data;
660 : : };
661 : :
662 : : TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool);
663 : :
664 : : /* Counter global management structure. */
665 : : struct mlx5_flow_counter_mng {
666 : : volatile RTE_ATOMIC(uint16_t) n_valid; /* Number of valid pools. */
667 : : uint16_t last_pool_idx; /* Last used pool index */
668 : : int min_id; /* The minimum counter ID in the pools. */
669 : : int max_id; /* The maximum counter ID in the pools. */
670 : : rte_spinlock_t pool_update_sl; /* The pool update lock. */
671 : : rte_spinlock_t csl[MLX5_COUNTER_TYPE_MAX];
672 : : /* The counter free list lock. */
673 : : struct mlx5_counters counters[MLX5_COUNTER_TYPE_MAX];
674 : : /* Free counter list. */
675 : : struct mlx5_flow_counter_pool **pools; /* Counter pool array. */
676 : : struct mlx5_counter_stats_mem_mng *mem_mng;
677 : : /* Hold the memory management for the next allocated pools raws. */
678 : : struct mlx5_counters flow_counters; /* Legacy flow counter list. */
679 : : uint8_t pending_queries;
680 : : uint16_t pool_index;
681 : : uint8_t query_thread_on;
682 : : bool counter_fallback; /* Use counter fallback management. */
683 : : LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs;
684 : : LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws;
685 : : };
686 : :
687 : : /* ASO structures. */
688 : : #define MLX5_ASO_QUEUE_LOG_DESC 10
689 : :
690 : : struct mlx5_aso_cq {
691 : : uint16_t log_desc_n;
692 : : uint32_t cq_ci:24;
693 : : struct mlx5_devx_cq cq_obj;
694 : : uint64_t errors;
695 : : };
696 : :
697 : : struct mlx5_aso_sq_elem {
698 : : union {
699 : : struct {
700 : : struct mlx5_aso_age_pool *pool;
701 : : uint16_t burst_size;
702 : : };
703 : : struct mlx5_aso_mtr *mtr;
704 : : struct {
705 : : struct mlx5_aso_ct_action *ct;
706 : : char *query_data;
707 : : };
708 : : void *user_data;
709 : : struct mlx5_quota *quota_obj;
710 : : };
711 : : };
712 : :
713 : : struct mlx5_aso_sq {
714 : : uint16_t log_desc_n;
715 : : rte_spinlock_t sqsl;
716 : : struct mlx5_aso_cq cq;
717 : : struct mlx5_devx_sq sq_obj;
718 : : struct mlx5_pmd_mr mr;
719 : : volatile struct mlx5_aso_wqe *db;
720 : : uint16_t pi;
721 : : uint16_t db_pi;
722 : : uint32_t head;
723 : : uint32_t tail;
724 : : uint32_t sqn;
725 : : struct mlx5_aso_sq_elem elts[1 << MLX5_ASO_QUEUE_LOG_DESC];
726 : : uint16_t next; /* Pool index of the next pool to query. */
727 : : };
728 : :
729 : : struct mlx5_aso_age_action {
730 : : LIST_ENTRY(mlx5_aso_age_action) next;
731 : : void *dr_action;
732 : : RTE_ATOMIC(uint32_t) refcnt;
733 : : /* Following fields relevant only when action is active. */
734 : : uint16_t offset; /* Offset of ASO Flow Hit flag in DevX object. */
735 : : struct mlx5_age_param age_params;
736 : : };
737 : :
738 : : #define MLX5_ASO_AGE_ACTIONS_PER_POOL 512
739 : : #define MLX5_ASO_AGE_CONTAINER_RESIZE 64
740 : :
741 : : struct mlx5_aso_age_pool {
742 : : struct mlx5_devx_obj *flow_hit_aso_obj;
743 : : uint16_t index; /* Pool index in pools array. */
744 : : uint64_t time_of_last_age_check; /* In seconds. */
745 : : struct mlx5_aso_age_action actions[MLX5_ASO_AGE_ACTIONS_PER_POOL];
746 : : };
747 : :
748 : : LIST_HEAD(aso_age_list, mlx5_aso_age_action);
749 : :
750 : : struct mlx5_aso_age_mng {
751 : : struct mlx5_aso_age_pool **pools;
752 : : uint16_t n; /* Total number of pools. */
753 : : uint16_t next; /* Number of pools in use, index of next free pool. */
754 : : rte_rwlock_t resize_rwl; /* Lock for resize objects. */
755 : : rte_spinlock_t free_sl; /* Lock for free list access. */
756 : : struct aso_age_list free; /* Free age actions list - ready to use. */
757 : : struct mlx5_aso_sq aso_sq; /* ASO queue objects. */
758 : : };
759 : :
760 : : /* Management structure for geneve tlv option */
761 : : struct mlx5_geneve_tlv_option_resource {
762 : : struct mlx5_devx_obj *obj; /* Pointer to the geneve tlv opt object. */
763 : : rte_be16_t option_class; /* geneve tlv opt class.*/
764 : : uint8_t option_type; /* geneve tlv opt type.*/
765 : : uint8_t length; /* geneve tlv opt length. */
766 : : RTE_ATOMIC(uint32_t) refcnt; /* geneve tlv object reference counter */
767 : : };
768 : :
769 : :
770 : : #define MLX5_AGE_EVENT_NEW 1
771 : : #define MLX5_AGE_TRIGGER 2
772 : : #define MLX5_AGE_SET(age_info, BIT) \
773 : : ((age_info)->flags |= (1 << (BIT)))
774 : : #define MLX5_AGE_UNSET(age_info, BIT) \
775 : : ((age_info)->flags &= ~(1 << (BIT)))
776 : : #define MLX5_AGE_GET(age_info, BIT) \
777 : : ((age_info)->flags & (1 << (BIT)))
778 : : #define GET_PORT_AGE_INFO(priv) \
779 : : (&((priv)->sh->port[(priv)->dev_port - 1].age_info))
780 : : /* Current time in seconds. */
781 : : #define MLX5_CURR_TIME_SEC (rte_rdtsc() / rte_get_tsc_hz())
782 : :
783 : : /*
784 : : * HW steering queue oriented AGE info.
785 : : * It contains an array of rings, one for each HWS queue.
786 : : */
787 : : struct mlx5_hws_q_age_info {
788 : : uint16_t nb_rings; /* Number of aged-out ring lists. */
789 : : struct rte_ring *aged_lists[]; /* Aged-out lists. */
790 : : };
791 : :
792 : : /*
793 : : * HW steering AGE info.
794 : : * It has a ring list containing all aged out flow rules.
795 : : */
796 : : struct mlx5_hws_age_info {
797 : : struct rte_ring *aged_list; /* Aged out lists. */
798 : : };
799 : :
800 : : /* Aging information for per port. */
801 : : struct mlx5_age_info {
802 : : uint8_t flags; /* Indicate if is new event or need to be triggered. */
803 : : union {
804 : : /* SW/FW steering AGE info. */
805 : : struct {
806 : : struct mlx5_counters aged_counters;
807 : : /* Aged counter list. */
808 : : struct aso_age_list aged_aso;
809 : : /* Aged ASO actions list. */
810 : : rte_spinlock_t aged_sl; /* Aged flow list lock. */
811 : : };
812 : : struct {
813 : : struct mlx5_indexed_pool *ages_ipool;
814 : : union {
815 : : struct mlx5_hws_age_info hw_age;
816 : : /* HW steering AGE info. */
817 : : struct mlx5_hws_q_age_info *hw_q_age;
818 : : /* HW steering queue oriented AGE info. */
819 : : };
820 : : };
821 : : };
822 : : };
823 : :
824 : : /* Per port data of shared IB device. */
825 : : struct mlx5_dev_shared_port {
826 : : uint32_t ih_port_id;
827 : : uint32_t devx_ih_port_id;
828 : : uint32_t nl_ih_port_id;
829 : : /*
830 : : * Interrupt handler port_id. Used by shared interrupt
831 : : * handler to find the corresponding rte_eth device
832 : : * by IB port index. If value is equal or greater
833 : : * RTE_MAX_ETHPORTS it means there is no subhandler
834 : : * installed for specified IB port index.
835 : : */
836 : : struct mlx5_age_info age_info;
837 : : /* Aging information for per port. */
838 : : };
839 : :
840 : : /*
841 : : * Max number of actions per DV flow.
842 : : * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
843 : : * in rdma-core file providers/mlx5/verbs.c.
844 : : */
845 : : #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
846 : :
847 : : /* ASO flow meter structures */
848 : : /* Modify this value if enum rte_mtr_color changes. */
849 : : #define RTE_MTR_DROPPED RTE_COLORS
850 : : /* Yellow is now supported. */
851 : : #define MLX5_MTR_RTE_COLORS (RTE_COLOR_YELLOW + 1)
852 : : /* table_id 22 bits in mlx5_flow_tbl_key so limit policy number. */
853 : : #define MLX5_MAX_SUB_POLICY_TBL_NUM 0x3FFFFF
854 : : #define MLX5_INVALID_POLICY_ID UINT32_MAX
855 : : /* Suffix table_id on MLX5_FLOW_TABLE_LEVEL_METER. */
856 : : #define MLX5_MTR_TABLE_ID_SUFFIX 1
857 : : /* Drop table_id on MLX5_FLOW_TABLE_LEVEL_METER. */
858 : : #define MLX5_MTR_TABLE_ID_DROP 2
859 : : /* Priority of the meter policy matcher. */
860 : : #define MLX5_MTR_POLICY_MATCHER_PRIO 0
861 : : /* Green & yellow color valid for now. */
862 : : #define MLX5_MTR_POLICY_MODE_ALL 0
863 : : /* Default policy. */
864 : : #define MLX5_MTR_POLICY_MODE_DEF 1
865 : : /* Only green color valid. */
866 : : #define MLX5_MTR_POLICY_MODE_OG 2
867 : : /* Only yellow color valid. */
868 : : #define MLX5_MTR_POLICY_MODE_OY 3
869 : :
870 : : /* Max number of meters. */
871 : : #define MLX5_MTR_MAX(priv) (mlx5_flow_mtr_max_get(priv))
872 : : /* Max number of meters allocated in non template mode. */
873 : : #define MLX5_MTR_NT_MAX(priv) (MLX5_MTR_MAX(priv) >> 1)
874 : : /* Max number of connection tracking. */
875 : : #define MLX5_CT_MAX(priv) (1 << (priv)->sh->cdev->config.hca_attr.log_max_conn_track_offload)
876 : : /* Max number of connection tracking allocated in non template mode. */
877 : : #define MLX5_CT_NT_MAX(priv) (MLX5_CT_MAX(priv) >> 1)
878 : : /* Max number of counters. */
879 : : #define MLX5_CNT_MAX(priv) ((priv)->sh->hws_max_nb_counters)
880 : : /* Max number of counters allocated in non template mode. */
881 : : #define MLX5_CNT_NT_MAX(priv) (MLX5_CNT_MAX(priv) >> 1)
882 : :
883 : : enum mlx5_meter_domain {
884 : : MLX5_MTR_DOMAIN_INGRESS,
885 : : MLX5_MTR_DOMAIN_EGRESS,
886 : : MLX5_MTR_DOMAIN_TRANSFER,
887 : : MLX5_MTR_DOMAIN_MAX,
888 : : };
889 : : #define MLX5_MTR_DOMAIN_INGRESS_BIT (1 << MLX5_MTR_DOMAIN_INGRESS)
890 : : #define MLX5_MTR_DOMAIN_EGRESS_BIT (1 << MLX5_MTR_DOMAIN_EGRESS)
891 : : #define MLX5_MTR_DOMAIN_TRANSFER_BIT (1 << MLX5_MTR_DOMAIN_TRANSFER)
892 : : #define MLX5_MTR_ALL_DOMAIN_BIT (MLX5_MTR_DOMAIN_INGRESS_BIT | \
893 : : MLX5_MTR_DOMAIN_EGRESS_BIT | \
894 : : MLX5_MTR_DOMAIN_TRANSFER_BIT)
895 : :
896 : : /* The color tag rule structure. */
897 : : struct mlx5_sub_policy_color_rule {
898 : : void *rule;
899 : : /* The color rule. */
900 : : struct mlx5_flow_dv_matcher *matcher;
901 : : /* The color matcher. */
902 : : TAILQ_ENTRY(mlx5_sub_policy_color_rule) next_port;
903 : : /**< Pointer to the next color rule structure. */
904 : : int32_t src_port;
905 : : /* On which src port this rule applied. */
906 : : };
907 : :
908 : : TAILQ_HEAD(mlx5_sub_policy_color_rules, mlx5_sub_policy_color_rule);
909 : :
910 : : /*
911 : : * Meter sub-policy structure.
912 : : * Each RSS TIR in meter policy need its own sub-policy resource.
913 : : */
914 : : struct mlx5_flow_meter_sub_policy {
915 : : uint32_t main_policy_id:1;
916 : : /* Main policy id is same as this sub_policy id. */
917 : : uint32_t idx:31;
918 : : /* Index to sub_policy ipool entity. */
919 : : void *main_policy;
920 : : /* Point to struct mlx5_flow_meter_policy. */
921 : : struct mlx5_flow_tbl_resource *tbl_rsc;
922 : : /* The sub-policy table resource. */
923 : : uint32_t rix_hrxq[MLX5_MTR_RTE_COLORS];
924 : : /* Index to TIR resource. */
925 : : struct mlx5_flow_tbl_resource *jump_tbl[MLX5_MTR_RTE_COLORS];
926 : : /* Meter jump/drop table. */
927 : : struct mlx5_sub_policy_color_rules color_rules[RTE_COLORS];
928 : : /* List for the color rules. */
929 : : };
930 : :
931 : : struct mlx5_meter_policy_acts {
932 : : uint8_t actions_n;
933 : : /* Number of actions. */
934 : : void *dv_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS];
935 : : /* Action list. */
936 : : };
937 : :
938 : : struct mlx5_meter_policy_action_container {
939 : : uint32_t rix_mark;
940 : : /* Index to the mark action. */
941 : : struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
942 : : /* Pointer to modify header resource in cache. */
943 : : uint8_t fate_action;
944 : : /* Fate action type. */
945 : : union {
946 : : struct rte_flow_action *rss;
947 : : /* Rss action configuration. */
948 : : uint32_t rix_port_id_action;
949 : : /* Index to port ID action resource. */
950 : : void *dr_jump_action[MLX5_MTR_DOMAIN_MAX];
951 : : /* Jump/drop action per color. */
952 : : uint16_t queue;
953 : : /* Queue action configuration. */
954 : : struct {
955 : : uint32_t next_mtr_id;
956 : : /* The next meter id. */
957 : : void *next_sub_policy;
958 : : /* Next meter's sub-policy. */
959 : : };
960 : : };
961 : : };
962 : :
963 : : /* Flow meter policy parameter structure. */
964 : : struct mlx5_flow_meter_policy {
965 : : uint32_t is_rss:1;
966 : : /* Is RSS policy table. */
967 : : uint32_t ingress:1;
968 : : /* Rule applies to ingress domain. */
969 : : uint32_t egress:1;
970 : : /* Rule applies to egress domain. */
971 : : uint32_t transfer:1;
972 : : /* Rule applies to transfer domain. */
973 : : uint32_t is_queue:1;
974 : : /* Is queue action in policy table. */
975 : : uint32_t is_hierarchy:1;
976 : : /* Is meter action in policy table. */
977 : : uint32_t match_port:1;
978 : : /* If policy flows match src port. */
979 : : uint32_t hierarchy_match_port:1;
980 : : /* Is any meter in hierarchy contains policy flow that matches src port. */
981 : : uint32_t skip_r:1;
982 : : /* If red color policy is skipped. */
983 : : uint32_t skip_y:1;
984 : : /* If yellow color policy is skipped. */
985 : : uint32_t skip_g:1;
986 : : /* If green color policy is skipped. */
987 : : uint32_t mark:1;
988 : : /* If policy contains mark action. */
989 : : uint32_t initialized:1;
990 : : /* Initialized. */
991 : : uint16_t group;
992 : : /* The group. */
993 : : rte_spinlock_t sl;
994 : : RTE_ATOMIC(uint32_t) ref_cnt;
995 : : /* Use count. */
996 : : struct rte_flow_pattern_template *hws_item_templ;
997 : : /* Hardware steering item templates. */
998 : : struct rte_flow_actions_template *hws_act_templ[MLX5_MTR_DOMAIN_MAX];
999 : : /* Hardware steering action templates. */
1000 : : struct rte_flow_template_table *hws_flow_table[MLX5_MTR_DOMAIN_MAX];
1001 : : /* Hardware steering tables. */
1002 : : struct rte_flow *hws_flow_rule[MLX5_MTR_DOMAIN_MAX][RTE_COLORS];
1003 : : /* Hardware steering rules. */
1004 : : struct mlx5_meter_policy_action_container act_cnt[MLX5_MTR_RTE_COLORS];
1005 : : /* Policy actions container. */
1006 : : void *dr_drop_action[MLX5_MTR_DOMAIN_MAX];
1007 : : /* drop action for red color. */
1008 : : uint16_t sub_policy_num;
1009 : : /* Count sub policy tables, 3 bits per domain. */
1010 : : struct mlx5_flow_meter_sub_policy **sub_policys[MLX5_MTR_DOMAIN_MAX];
1011 : : /* Sub policy table array must be the end of struct. */
1012 : : };
1013 : :
1014 : : /* The maximum sub policy is relate to struct mlx5_rss_hash_fields[]. */
1015 : : #define MLX5_MTR_RSS_MAX_SUB_POLICY 7
1016 : : #define MLX5_MTR_SUB_POLICY_NUM_SHIFT 3
1017 : : #define MLX5_MTR_SUB_POLICY_NUM_MASK 0x7
1018 : : #define MLX5_MTRS_DEFAULT_RULE_PRIORITY 0xFFFF
1019 : : #define MLX5_MTR_CHAIN_MAX_NUM 8
1020 : :
1021 : : /* Flow meter default policy parameter structure.
1022 : : * Policy index 0 is reserved by default policy table.
1023 : : * Action per color as below:
1024 : : * green - do nothing, yellow - do nothing, red - drop
1025 : : */
1026 : : struct mlx5_flow_meter_def_policy {
1027 : : struct mlx5_flow_meter_sub_policy sub_policy;
1028 : : /* Policy rules jump to other tables. */
1029 : : void *dr_jump_action[RTE_COLORS];
1030 : : /* Jump action per color. */
1031 : : };
1032 : :
1033 : : /* Meter parameter structure. */
1034 : : struct mlx5_flow_meter_info {
1035 : : uint32_t meter_id;
1036 : : /**< Meter id. */
1037 : : uint32_t policy_id;
1038 : : /* Policy id, the first sub_policy idx. */
1039 : : struct mlx5_flow_meter_profile *profile;
1040 : : /**< Meter profile parameters. */
1041 : : rte_spinlock_t sl; /**< Meter action spinlock. */
1042 : : /** Set of stats counters to be enabled.
1043 : : * @see enum rte_mtr_stats_type
1044 : : */
1045 : : uint32_t bytes_dropped:1;
1046 : : /** Set bytes dropped stats to be enabled. */
1047 : : uint32_t pkts_dropped:1;
1048 : : /** Set packets dropped stats to be enabled. */
1049 : : uint32_t active_state:1;
1050 : : /**< Meter hw active state. */
1051 : : uint32_t shared:1;
1052 : : /**< Meter shared or not. */
1053 : : uint32_t is_enable:1;
1054 : : /**< Meter disable/enable state. */
1055 : : uint32_t ingress:1;
1056 : : /**< Rule applies to egress traffic. */
1057 : : uint32_t egress:1;
1058 : : /**
1059 : : * Instead of simply matching the properties of traffic as it would
1060 : : * appear on a given DPDK port ID, enabling this attribute transfers
1061 : : * a flow rule to the lowest possible level of any device endpoints
1062 : : * found in the pattern.
1063 : : *
1064 : : * When supported, this effectively enables an application to
1065 : : * re-route traffic not necessarily intended for it (e.g. coming
1066 : : * from or addressed to different physical ports, VFs or
1067 : : * applications) at the device level.
1068 : : *
1069 : : * It complements the behavior of some pattern items such as
1070 : : * RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT and is meaningless without them.
1071 : : *
1072 : : * When transferring flow rules, ingress and egress attributes keep
1073 : : * their original meaning, as if processing traffic emitted or
1074 : : * received by the application.
1075 : : */
1076 : : uint32_t transfer:1;
1077 : : uint32_t def_policy:1;
1078 : : uint32_t initialized:1;
1079 : : /* Meter points to default policy. */
1080 : : uint32_t color_aware:1;
1081 : : /* Meter is color aware mode. */
1082 : : void *drop_rule[MLX5_MTR_DOMAIN_MAX];
1083 : : /* Meter drop rule in drop table. */
1084 : : uint32_t drop_cnt;
1085 : : /**< Color counter for drop. */
1086 : : uint32_t ref_cnt;
1087 : : /**< Use count. */
1088 : : struct mlx5_indexed_pool *flow_ipool;
1089 : : /**< Index pool for flow id. */
1090 : : void *meter_action_g;
1091 : : /**< Flow meter action. */
1092 : : void *meter_action_y;
1093 : : /**< Flow meter action for yellow init_color. */
1094 : : uint32_t meter_offset;
1095 : : /**< Flow meter offset. */
1096 : : uint16_t group;
1097 : : /**< Flow meter group. */
1098 : : };
1099 : :
1100 : : /* PPS(packets per second) map to BPS(Bytes per second).
1101 : : * HW treat packet as 128bytes in PPS mode
1102 : : */
1103 : : #define MLX5_MTRS_PPS_MAP_BPS_SHIFT 7
1104 : :
1105 : : /* RFC2697 parameter structure. */
1106 : : struct mlx5_flow_meter_srtcm_rfc2697_prm {
1107 : : rte_be32_t cbs_cir;
1108 : : /*
1109 : : * bit 24-28: cbs_exponent, bit 16-23 cbs_mantissa,
1110 : : * bit 8-12: cir_exponent, bit 0-7 cir_mantissa.
1111 : : */
1112 : : rte_be32_t ebs_eir;
1113 : : /*
1114 : : * bit 24-28: ebs_exponent, bit 16-23 ebs_mantissa,
1115 : : * bit 8-12: eir_exponent, bit 0-7 eir_mantissa.
1116 : : */
1117 : : };
1118 : :
1119 : : /* Flow meter profile structure. */
1120 : : struct mlx5_flow_meter_profile {
1121 : : TAILQ_ENTRY(mlx5_flow_meter_profile) next;
1122 : : /**< Pointer to the next flow meter structure. */
1123 : : uint32_t id; /**< Profile id. */
1124 : : struct rte_mtr_meter_profile profile; /**< Profile detail. */
1125 : : union {
1126 : : struct mlx5_flow_meter_srtcm_rfc2697_prm srtcm_prm;
1127 : : /**< srtcm_rfc2697 struct. */
1128 : : };
1129 : : RTE_ATOMIC(uint32_t) ref_cnt; /**< Use count. */
1130 : : uint32_t g_support:1; /**< If G color will be generated. */
1131 : : uint32_t y_support:1; /**< If Y color will be generated. */
1132 : : uint32_t initialized:1; /**< Initialized. */
1133 : : };
1134 : :
1135 : : /* 2 meters in each ASO cache line */
1136 : : #define MLX5_MTRS_CONTAINER_RESIZE 64
1137 : : /*
1138 : : * The pool index and offset of meter in the pool array makes up the
1139 : : * meter index. In case the meter is from pool 0 and offset 0, it
1140 : : * should plus 1 to avoid index 0, since 0 means invalid meter index
1141 : : * currently.
1142 : : */
1143 : : #define MLX5_MAKE_MTR_IDX(pi, offset) \
1144 : : ((pi) * MLX5_ASO_MTRS_PER_POOL + (offset) + 1)
1145 : :
1146 : : /*aso flow meter state*/
1147 : : enum mlx5_aso_mtr_state {
1148 : : ASO_METER_FREE, /* In free list. */
1149 : : ASO_METER_WAIT, /* ACCESS_ASO WQE in progress. */
1150 : : ASO_METER_WAIT_ASYNC, /* CQE will be handled by async pull. */
1151 : : ASO_METER_READY, /* CQE received. */
1152 : : };
1153 : :
1154 : : /*aso flow meter type*/
1155 : : enum mlx5_aso_mtr_type {
1156 : : ASO_METER_INDIRECT,
1157 : : ASO_METER_DIRECT,
1158 : : };
1159 : :
1160 : : /* Generic aso_flow_meter information. */
1161 : : struct mlx5_aso_mtr {
1162 : : union {
1163 : : LIST_ENTRY(mlx5_aso_mtr) next;
1164 : : struct mlx5_aso_mtr_pool *pool;
1165 : : };
1166 : : enum mlx5_aso_mtr_type type;
1167 : : struct mlx5_flow_meter_info fm;
1168 : : /**< Pointer to the next aso flow meter structure. */
1169 : : RTE_ATOMIC(uint8_t) state; /**< ASO flow meter state. */
1170 : : uint32_t offset;
1171 : : enum rte_color init_color;
1172 : : };
1173 : :
1174 : : /* Generic aso_flow_meter pool structure. */
1175 : : struct mlx5_aso_mtr_pool {
1176 : : struct mlx5_aso_mtr mtrs[MLX5_ASO_MTRS_PER_POOL];
1177 : : /*Must be the first in pool*/
1178 : : struct mlx5_devx_obj *devx_obj;
1179 : : /* The devx object of the minimum aso flow meter ID. */
1180 : : struct mlx5dr_action *action; /* HWS action. */
1181 : : struct mlx5_indexed_pool *idx_pool; /* HWS index pool. */
1182 : : uint32_t index; /* Pool index in management structure. */
1183 : : uint32_t nb_sq; /* Number of ASO SQ. */
1184 : : struct mlx5_aso_sq *sq; /* ASO SQs. */
1185 : : };
1186 : :
1187 : : LIST_HEAD(aso_meter_list, mlx5_aso_mtr);
1188 : : /* Pools management structure for ASO flow meter pools. */
1189 : : struct mlx5_aso_mtr_pools_mng {
1190 : : volatile uint16_t n_valid; /* Number of valid pools. */
1191 : : uint16_t n; /* Number of pools. */
1192 : : rte_spinlock_t mtrsl; /* The ASO flow meter free list lock. */
1193 : : rte_rwlock_t resize_mtrwl; /* Lock for resize objects. */
1194 : : struct aso_meter_list meters; /* Free ASO flow meter list. */
1195 : : struct mlx5_aso_sq sq; /*SQ using by ASO flow meter. */
1196 : : struct mlx5_aso_mtr_pool **pools; /* ASO flow meter pool array. */
1197 : : };
1198 : :
1199 : : /* Bulk management structure for ASO flow meter. */
1200 : : struct mlx5_mtr_bulk {
1201 : : uint32_t size; /* Number of ASO objects. */
1202 : : struct mlx5dr_action *action; /* HWS action */
1203 : : struct mlx5_devx_obj *devx_obj; /* DEVX object. */
1204 : : struct mlx5_aso_mtr *aso; /* Array of ASO objects. */
1205 : : };
1206 : :
1207 : : /* Meter management structure for global flow meter resource. */
1208 : : struct mlx5_flow_mtr_mng {
1209 : : struct mlx5_aso_mtr_pools_mng pools_mng;
1210 : : /* Pools management structure for ASO flow meter pools. */
1211 : : struct mlx5_flow_meter_def_policy *def_policy[MLX5_MTR_DOMAIN_MAX];
1212 : : /* Default policy table. */
1213 : : uint32_t def_policy_id;
1214 : : /* Default policy id. */
1215 : : RTE_ATOMIC(uint32_t) def_policy_ref_cnt;
1216 : : /** def_policy meter use count. */
1217 : : struct mlx5_flow_tbl_resource *drop_tbl[MLX5_MTR_DOMAIN_MAX];
1218 : : /* Meter drop table. */
1219 : : struct mlx5_flow_dv_matcher *
1220 : : drop_matcher[MLX5_MTR_DOMAIN_MAX][MLX5_REG_BITS];
1221 : : /* Matcher meter in drop table. */
1222 : : struct mlx5_flow_dv_matcher *def_matcher[MLX5_MTR_DOMAIN_MAX];
1223 : : /* Default matcher in drop table. */
1224 : : void *def_rule[MLX5_MTR_DOMAIN_MAX];
1225 : : /* Default rule in drop table. */
1226 : : uint8_t max_mtr_bits;
1227 : : /* Indicate how many bits are used by meter id at the most. */
1228 : : uint8_t max_mtr_flow_bits;
1229 : : /* Indicate how many bits are used by meter flow id at the most. */
1230 : : };
1231 : :
1232 : : /* Table key of the hash organization. */
1233 : : union mlx5_flow_tbl_key {
1234 : : struct {
1235 : : /* Table ID should be at the lowest address. */
1236 : : uint32_t level; /**< Level of the table. */
1237 : : uint32_t id:22; /**< ID of the table. */
1238 : : uint32_t dummy:1; /**< Dummy table for DV API. */
1239 : : uint32_t is_fdb:1; /**< 1 - FDB, 0 - NIC TX/RX. */
1240 : : uint32_t is_egress:1; /**< 1 - egress, 0 - ingress. */
1241 : : uint32_t reserved:7; /**< must be zero for comparison. */
1242 : : };
1243 : : uint64_t v64; /**< full 64bits value of key */
1244 : : };
1245 : :
1246 : : /* Table structure. */
1247 : : struct mlx5_flow_tbl_resource {
1248 : : void *obj; /**< Pointer to DR table object. */
1249 : : };
1250 : :
1251 : : #define MLX5_MAX_TABLES UINT16_MAX
1252 : : #define MLX5_HAIRPIN_TX_TABLE (UINT16_MAX - 1)
1253 : : /* Reserve the last two tables for metadata register copy. */
1254 : : #define MLX5_FLOW_MREG_ACT_TABLE_GROUP (MLX5_MAX_TABLES - 1)
1255 : : #define MLX5_FLOW_MREG_CP_TABLE_GROUP (MLX5_MAX_TABLES - 2)
1256 : : /* Tables for metering splits should be added here. */
1257 : : #define MLX5_FLOW_TABLE_LEVEL_METER (MLX5_MAX_TABLES - 3)
1258 : : #define MLX5_FLOW_TABLE_LEVEL_POLICY (MLX5_MAX_TABLES - 4)
1259 : : #define MLX5_MAX_TABLES_EXTERNAL MLX5_FLOW_TABLE_LEVEL_POLICY
1260 : : #define MLX5_MAX_TABLES_FDB UINT16_MAX
1261 : : #define MLX5_FLOW_TABLE_PTYPE_RSS_NUM 1024
1262 : : #define MLX5_FLOW_TABLE_PTYPE_RSS_LAST (MLX5_MAX_TABLES - 11)
1263 : : #define MLX5_FLOW_TABLE_PTYPE_RSS_BASE \
1264 : : (1 + MLX5_FLOW_TABLE_PTYPE_RSS_LAST - MLX5_FLOW_TABLE_PTYPE_RSS_NUM)
1265 : : #define MLX5_FLOW_TABLE_SAMPLE_NUM 1024
1266 : : #define MLX5_FLOW_TABLE_SAMPLE_LAST (MLX5_FLOW_TABLE_PTYPE_RSS_BASE - 1)
1267 : : #define MLX5_FLOW_TABLE_SAMPLE_BASE \
1268 : : (1 + MLX5_FLOW_TABLE_SAMPLE_LAST - MLX5_FLOW_TABLE_SAMPLE_NUM)
1269 : :
1270 : : #define MLX5_FLOW_TABLE_FACTOR 10
1271 : :
1272 : : /* ID generation structure. */
1273 : : struct mlx5_flow_id_pool {
1274 : : uint32_t *free_arr; /**< Pointer to the a array of free values. */
1275 : : uint32_t base_index;
1276 : : /**< The next index that can be used without any free elements. */
1277 : : uint32_t *curr; /**< Pointer to the index to pop. */
1278 : : uint32_t *last; /**< Pointer to the last element in the empty array. */
1279 : : uint32_t max_id; /**< Maximum id can be allocated from the pool. */
1280 : : };
1281 : :
1282 : : /* Tx pacing queue structure - for Clock and Rearm queues. */
1283 : : struct mlx5_txpp_wq {
1284 : : /* Completion Queue related data.*/
1285 : : struct mlx5_devx_cq cq_obj;
1286 : : uint32_t cq_ci:24;
1287 : : uint32_t arm_sn:2;
1288 : : /* Send Queue related data.*/
1289 : : struct mlx5_devx_sq sq_obj;
1290 : : uint16_t sq_size; /* Number of WQEs in the queue. */
1291 : : uint16_t sq_ci; /* Next WQE to execute. */
1292 : : };
1293 : :
1294 : : /* Tx packet pacing internal timestamp. */
1295 : : struct mlx5_txpp_ts {
1296 : : RTE_ATOMIC(uint64_t) ci_ts;
1297 : : RTE_ATOMIC(uint64_t) ts;
1298 : : };
1299 : :
1300 : : /* Tx packet pacing structure. */
1301 : : struct mlx5_dev_txpp {
1302 : : pthread_mutex_t mutex; /* Pacing create/destroy mutex. */
1303 : : uint32_t refcnt; /* Pacing reference counter. */
1304 : : uint32_t freq; /* Timestamp frequency, Hz. */
1305 : : uint32_t tick; /* Completion tick duration in nanoseconds. */
1306 : : uint32_t test; /* Packet pacing test mode. */
1307 : : int32_t skew; /* Scheduling skew. */
1308 : : struct rte_intr_handle *intr_handle; /* Periodic interrupt. */
1309 : : void *echan; /* Event Channel. */
1310 : : struct mlx5_txpp_wq clock_queue; /* Clock Queue. */
1311 : : struct mlx5_txpp_wq rearm_queue; /* Clock Queue. */
1312 : : void *pp; /* Packet pacing context. */
1313 : : uint16_t pp_id; /* Packet pacing context index. */
1314 : : uint16_t ts_n; /* Number of captured timestamps. */
1315 : : uint16_t ts_p; /* Pointer to statistics timestamp. */
1316 : : struct mlx5_txpp_ts *tsa; /* Timestamps sliding window stats. */
1317 : : struct mlx5_txpp_ts ts; /* Cached completion id/timestamp. */
1318 : : uint32_t sync_lost:1; /* ci/timestamp synchronization lost. */
1319 : : /* Statistics counters. */
1320 : : RTE_ATOMIC(uint64_t) err_miss_int; /* Missed service interrupt. */
1321 : : RTE_ATOMIC(uint64_t) err_rearm_queue; /* Rearm Queue errors. */
1322 : : RTE_ATOMIC(uint64_t) err_clock_queue; /* Clock Queue errors. */
1323 : : RTE_ATOMIC(uint64_t) err_ts_past; /* Timestamp in the past. */
1324 : : RTE_ATOMIC(uint64_t) err_ts_future; /* Timestamp in the distant future. */
1325 : : RTE_ATOMIC(uint64_t) err_ts_order; /* Timestamp not in ascending order. */
1326 : : };
1327 : :
1328 : : /* Sample ID information of eCPRI flex parser structure. */
1329 : : struct mlx5_ecpri_parser_profile {
1330 : : uint32_t num; /* Actual number of samples. */
1331 : : uint32_t ids[8]; /* Sample IDs for this profile. */
1332 : : uint8_t offset[8]; /* Bytes offset of each parser. */
1333 : : void *obj; /* Flex parser node object. */
1334 : : };
1335 : :
1336 : : /* Max member ports per bonding device. */
1337 : : #define MLX5_BOND_MAX_PORTS 4
1338 : :
1339 : : /* Bonding device information. */
1340 : : struct mlx5_bond_info {
1341 : : int n_port; /* Number of bond member ports. */
1342 : : uint32_t ifindex;
1343 : : char ifname[MLX5_NAMESIZE + 1];
1344 : : struct {
1345 : : char ifname[MLX5_NAMESIZE + 1];
1346 : : uint32_t ifindex;
1347 : : struct rte_pci_addr pci_addr;
1348 : : } ports[MLX5_BOND_MAX_PORTS];
1349 : : };
1350 : :
1351 : : /* Number of connection tracking objects per pool: must be a power of 2. */
1352 : : #define MLX5_ASO_CT_ACTIONS_PER_POOL 64
1353 : :
1354 : : /* Generate incremental and unique CT index from pool and offset. */
1355 : : #define MLX5_MAKE_CT_IDX(pool, offset) \
1356 : : ((pool) * MLX5_ASO_CT_ACTIONS_PER_POOL + (offset) + 1)
1357 : :
1358 : : /* ASO Conntrack state. */
1359 : : enum mlx5_aso_ct_state {
1360 : : ASO_CONNTRACK_FREE, /* Inactive, in the free list. */
1361 : : ASO_CONNTRACK_WAIT, /* WQE sent in the SQ. */
1362 : : ASO_CONNTRACK_WAIT_ASYNC, /* CQE will be handled by async pull. */
1363 : : ASO_CONNTRACK_READY, /* CQE received w/o error. */
1364 : : ASO_CONNTRACK_QUERY, /* WQE for query sent. */
1365 : : ASO_CONNTRACK_MAX, /* Guard. */
1366 : : };
1367 : :
1368 : : /* Generic ASO connection tracking structure. */
1369 : : struct mlx5_aso_ct_action {
1370 : : union {
1371 : : /* SWS mode struct. */
1372 : : struct {
1373 : : /* Pointer to the next ASO CT. Used only in SWS. */
1374 : : LIST_ENTRY(mlx5_aso_ct_action) next;
1375 : : };
1376 : : /* HWS mode struct. */
1377 : : struct {
1378 : : /* Pointer to action pool. Used only in HWS. */
1379 : : struct mlx5_aso_ct_pool *pool;
1380 : : };
1381 : : };
1382 : : /* General action object for original dir. */
1383 : : void *dr_action_orig;
1384 : : /* General action object for reply dir. */
1385 : : void *dr_action_rply;
1386 : : RTE_ATOMIC(uint32_t) refcnt; /* Action used count in device flows. */
1387 : : uint32_t offset; /* Offset of ASO CT in DevX objects bulk. */
1388 : : uint16_t peer; /* The only peer port index could also use this CT. */
1389 : : RTE_ATOMIC(enum mlx5_aso_ct_state) state; /* ASO CT state. */
1390 : : bool is_original; /* The direction of the DR action to be used. */
1391 : : };
1392 : :
1393 : : /* CT action object state update. */
1394 : : #define MLX5_ASO_CT_UPDATE_STATE(c, s) \
1395 : : rte_atomic_store_explicit(&((c)->state), (s), rte_memory_order_relaxed)
1396 : :
1397 : : #ifdef PEDANTIC
1398 : : #pragma GCC diagnostic ignored "-Wpedantic"
1399 : : #endif
1400 : :
1401 : : /* ASO connection tracking software pool definition. */
1402 : : struct mlx5_aso_ct_pool {
1403 : : uint16_t index; /* Pool index in pools array. */
1404 : : /* Free ASO CT index in the pool. Used by HWS. */
1405 : : struct mlx5_indexed_pool *cts;
1406 : : struct mlx5_devx_obj *devx_obj;
1407 : : union {
1408 : : void *dummy_action;
1409 : : /* Dummy action to increase the reference count in the driver. */
1410 : : struct mlx5dr_action *dr_action;
1411 : : /* HWS action. */
1412 : : };
1413 : : struct mlx5_aso_sq *sq; /* Async ASO SQ. */
1414 : : struct mlx5_aso_sq *shared_sq; /* Shared ASO SQ. */
1415 : : struct mlx5_aso_ct_action actions[];
1416 : : /* CT action structures bulk. */
1417 : : };
1418 : :
1419 : : LIST_HEAD(aso_ct_list, mlx5_aso_ct_action);
1420 : :
1421 : : #define MLX5_ASO_CT_SQ_NUM 16
1422 : :
1423 : : /* Pools management structure for ASO connection tracking pools. */
1424 : : struct mlx5_aso_ct_pools_mng {
1425 : : struct mlx5_aso_ct_pool **pools;
1426 : : uint16_t n; /* Total number of pools. */
1427 : : uint16_t next; /* Number of pools in use, index of next free pool. */
1428 : : uint32_t nb_sq; /* Number of ASO SQ. */
1429 : : rte_spinlock_t ct_sl; /* The ASO CT free list lock. */
1430 : : rte_rwlock_t resize_rwl; /* The ASO CT pool resize lock. */
1431 : : struct aso_ct_list free_cts; /* Free ASO CT objects list. */
1432 : : struct mlx5_aso_sq aso_sqs[]; /* ASO queue objects. */
1433 : : };
1434 : :
1435 : : #ifdef PEDANTIC
1436 : : #pragma GCC diagnostic error "-Wpedantic"
1437 : : #endif
1438 : :
1439 : : /* LAG attr. */
1440 : : struct mlx5_lag {
1441 : : uint8_t tx_remap_affinity[16]; /* The PF port number of affinity */
1442 : : uint8_t affinity_mode; /* TIS or hash based affinity */
1443 : : };
1444 : :
1445 : : /* DevX flex parser context. */
1446 : : struct mlx5_flex_parser_devx {
1447 : : struct mlx5_list_entry entry; /* List element at the beginning. */
1448 : : uint32_t num_samples;
1449 : : uint8_t anchor_id;
1450 : : void *devx_obj;
1451 : : struct mlx5_devx_graph_node_attr devx_conf;
1452 : : uint32_t sample_ids[MLX5_GRAPH_NODE_SAMPLE_NUM];
1453 : : struct mlx5_devx_match_sample_info_query_attr sample_info[MLX5_GRAPH_NODE_SAMPLE_NUM];
1454 : : };
1455 : :
1456 : : /* Pattern field descriptor - how to translate flex pattern into samples. */
1457 : : __extension__
1458 : : struct mlx5_flex_pattern_field {
1459 : : uint16_t width:6;
1460 : : uint16_t shift:5;
1461 : : uint16_t reg_id:5;
1462 : : };
1463 : :
1464 : : #define MLX5_INVALID_SAMPLE_REG_ID 0x1F
1465 : :
1466 : : /* Port flex item context. */
1467 : : struct mlx5_flex_item {
1468 : : struct mlx5_flex_parser_devx *devx_fp; /* DevX flex parser object. */
1469 : : RTE_ATOMIC(uint32_t) refcnt; /* Atomically accessed refcnt by flows. */
1470 : : enum rte_flow_item_flex_tunnel_mode tunnel_mode; /* Tunnel mode. */
1471 : : uint32_t mapnum; /* Number of pattern translation entries. */
1472 : : struct mlx5_flex_pattern_field map[MLX5_FLEX_ITEM_MAPPING_NUM];
1473 : : };
1474 : :
1475 : : /*
1476 : : * Sample IPv6 address in the first segment list
1477 : : * and the first dword of SRv6 header.
1478 : : * Then it is 16 + 4 = 20 bytes which is 5 dwords.
1479 : : */
1480 : : #define MLX5_SRV6_SAMPLE_NUM 5
1481 : : /* Mlx5 internal flex parser profile structure. */
1482 : : struct mlx5_internal_flex_parser_profile {
1483 : : RTE_ATOMIC(uint32_t) refcnt;
1484 : : struct mlx5_flex_item flex; /* Hold map info for modify field. */
1485 : : };
1486 : :
1487 : : struct mlx5_send_to_kernel_action {
1488 : : void *action;
1489 : : void *tbl;
1490 : : };
1491 : :
1492 : : #define HWS_CNT_ASO_SQ_NUM 4
1493 : :
1494 : : struct mlx5_hws_aso_mng {
1495 : : uint16_t sq_num;
1496 : : struct mlx5_aso_sq sqs[HWS_CNT_ASO_SQ_NUM];
1497 : : };
1498 : :
1499 : : struct mlx5_hws_cnt_svc_mng {
1500 : : uint32_t refcnt;
1501 : : uint32_t service_core;
1502 : : uint32_t query_interval;
1503 : : rte_thread_t service_thread;
1504 : : uint8_t svc_running;
1505 : : alignas(RTE_CACHE_LINE_SIZE) struct mlx5_hws_aso_mng aso_mng;
1506 : : };
1507 : :
1508 : : #define MLX5_FLOW_HW_TAGS_MAX 12
1509 : : #define MLX5_FLOW_NAT64_REGS_MAX 3
1510 : :
1511 : : struct mlx5_dev_registers {
1512 : : enum modify_reg aso_reg;
1513 : : enum modify_reg hw_avl_tags[MLX5_FLOW_HW_TAGS_MAX];
1514 : : enum modify_reg nat64_regs[MLX5_FLOW_NAT64_REGS_MAX];
1515 : : };
1516 : :
1517 : : #if defined(HAVE_MLX5DV_DR) && \
1518 : : (defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER) || \
1519 : : defined(HAVE_MLX5_DR_CREATE_ACTION_ASO))
1520 : : #define HAVE_MLX5_DR_CREATE_ACTION_ASO_EXT
1521 : : #endif
1522 : :
1523 : : struct mlx5_geneve_tlv_options;
1524 : :
1525 : : enum mlx5_ipv6_tc_support {
1526 : : MLX5_IPV6_TC_UNKNOWN = 0,
1527 : : MLX5_IPV6_TC_FALLBACK,
1528 : : MLX5_IPV6_TC_OK,
1529 : : };
1530 : :
1531 : : struct mlx5_common_nic_config {
1532 : : enum mlx5_ipv6_tc_support ipv6_tc_fallback;
1533 : : /* Whether ipv6 traffic class should use old value. */
1534 : : };
1535 : :
1536 : : /**
1537 : : * Physical device structure.
1538 : : * This device is created once per NIC to manage recourses shared by all ports
1539 : : * under same physical device.
1540 : : */
1541 : : struct mlx5_physical_device {
1542 : : LIST_ENTRY(mlx5_physical_device) next;
1543 : : void *ctx; /* CTX for creation of options. */
1544 : : uint64_t guid; /* System image guid, the uniq ID of physical device. */
1545 : : struct mlx5_geneve_tlv_options *tlv_options;
1546 : : struct mlx5_common_nic_config config;
1547 : : uint32_t refcnt;
1548 : : };
1549 : :
1550 : : /*
1551 : : * Shared Infiniband device context for Master/Representors
1552 : : * which belong to same IB device with multiple IB ports.
1553 : : **/
1554 : : struct mlx5_dev_ctx_shared {
1555 : : LIST_ENTRY(mlx5_dev_ctx_shared) next;
1556 : : uint32_t refcnt;
1557 : : uint32_t esw_mode:1; /* Whether is E-Switch mode. */
1558 : : uint32_t flow_hit_aso_en:1; /* Flow Hit ASO is supported. */
1559 : : uint32_t steering_format_version:4;
1560 : : /* Indicates the device steering logic format. */
1561 : : uint32_t meter_aso_en:1; /* Flow Meter ASO is supported. */
1562 : : uint32_t ct_aso_en:1; /* Connection Tracking ASO is supported. */
1563 : : uint32_t tunnel_header_0_1:1; /* tunnel_header_0_1 is supported. */
1564 : : uint32_t tunnel_header_2_3:1; /* tunnel_header_2_3 is supported. */
1565 : : uint32_t misc5_cap:1; /* misc5 matcher parameter is supported. */
1566 : : uint32_t dr_root_drop_action_en:1; /* DR drop action is usable on root tables. */
1567 : : uint32_t drop_action_check_flag:1; /* Check Flag for drop action. */
1568 : : uint32_t flow_priority_check_flag:1; /* Check Flag for flow priority. */
1569 : : uint32_t metadata_regc_check_flag:1; /* Check Flag for metadata REGC. */
1570 : : uint32_t shared_mark_enabled:1;
1571 : : /* If mark action is enabled on Rxqs (shared E-Switch domain). */
1572 : : uint32_t lag_rx_port_affinity_en:1;
1573 : : /* lag_rx_port_affinity is supported. */
1574 : : uint32_t hws_max_log_bulk_sz:5;
1575 : : uint32_t rdma_monitor_supp:1;
1576 : : /* Log of minimal HWS counters created hard coded. */
1577 : : uint32_t hws_max_nb_counters; /* Maximal number for HWS counters. */
1578 : : uint32_t max_port; /* Maximal IB device port index. */
1579 : : struct mlx5_bond_info bond; /* Bonding information. */
1580 : : struct mlx5_common_device *cdev; /* Backend mlx5 device. */
1581 : : struct mlx5_physical_device *phdev; /* Backend physical device. */
1582 : : uint32_t tdn; /* Transport Domain number. */
1583 : : char ibdev_name[MLX5_FS_NAME_MAX]; /* SYSFS dev name. */
1584 : : char ibdev_path[MLX5_FS_PATH_MAX]; /* SYSFS dev path for secondary */
1585 : : struct mlx5_dev_cap dev_cap; /* Device capabilities. */
1586 : : struct mlx5_sh_config config; /* Device configuration. */
1587 : : int numa_node; /* Numa node of backing physical device. */
1588 : : /* Packet pacing related structure. */
1589 : : struct mlx5_dev_txpp txpp;
1590 : : /* Shared DV/DR flow data section. */
1591 : : uint32_t dv_meta_mask; /* flow META metadata supported mask. */
1592 : : uint32_t dv_mark_mask; /* flow MARK metadata supported mask. */
1593 : : uint32_t dv_regc0_mask; /* available bits of metadata reg_c[0]. */
1594 : : void *fdb_domain; /* FDB Direct Rules name space handle. */
1595 : : void *rx_domain; /* RX Direct Rules name space handle. */
1596 : : void *tx_domain; /* TX Direct Rules name space handle. */
1597 : : #ifndef RTE_ARCH_64
1598 : : rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR. */
1599 : : rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];
1600 : : /* UAR same-page access control required in 32bit implementations. */
1601 : : #endif
1602 : : union {
1603 : : struct mlx5_hlist *flow_tbls; /* SWS flow table. */
1604 : : struct mlx5_hlist *groups; /* HWS flow group. */
1605 : : };
1606 : : struct mlx5_hlist *mreg_cp_tbl;
1607 : : /* Hash table of Rx metadata register copy table. */
1608 : : struct mlx5_flow_tunnel_hub *tunnel_hub;
1609 : : /* Direct Rules tables for FDB, NIC TX+RX */
1610 : : void *dr_drop_action; /* Pointer to DR drop action, any domain. */
1611 : : void *pop_vlan_action; /* Pointer to DR pop VLAN action. */
1612 : : #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1613 : : struct mlx5_send_to_kernel_action send_to_kernel_action[MLX5DR_TABLE_TYPE_MAX];
1614 : : #endif
1615 : : RTE_ATOMIC(struct mlx5_hlist *) encaps_decaps; /* Encap/decap action hash list. */
1616 : : RTE_ATOMIC(struct mlx5_hlist *) modify_cmds;
1617 : : RTE_ATOMIC(struct mlx5_hlist *) tag_table;
1618 : : struct mlx5_list *port_id_action_list; /* Port ID action list. */
1619 : : struct mlx5_list *push_vlan_action_list; /* Push VLAN actions. */
1620 : : struct mlx5_list *sample_action_list; /* List of sample actions. */
1621 : : struct mlx5_list *dest_array_list;
1622 : : struct mlx5_list *flex_parsers_dv; /* Flex Item parsers. */
1623 : : /* List of destination array actions. */
1624 : : struct mlx5_flow_counter_mng sws_cmng;
1625 : : /* SW steering counters management structure. */
1626 : : void *default_miss_action; /* Default miss action. */
1627 : : struct mlx5_indexed_pool *ipool[MLX5_IPOOL_MAX];
1628 : : RTE_ATOMIC(struct mlx5_indexed_pool *) mdh_ipools[MLX5_MAX_MODIFY_NUM];
1629 : : /* Shared interrupt handler section. */
1630 : : struct rte_intr_handle *intr_handle; /* Interrupt handler for device. */
1631 : : struct rte_intr_handle *intr_handle_devx; /* DEVX interrupt handler. */
1632 : : struct rte_intr_handle *intr_handle_nl; /* Netlink interrupt handler. */
1633 : : struct rte_intr_handle *intr_handle_ib; /* Interrupt handler for IB device. */
1634 : : void *devx_comp; /* DEVX async comp obj. */
1635 : : struct mlx5_devx_obj *tis[16]; /* TIS object. */
1636 : : struct mlx5_devx_obj *td; /* Transport domain. */
1637 : : struct mlx5_lag lag; /* LAG attributes */
1638 : : struct mlx5_uar tx_uar; /* DevX UAR for Tx and Txpp and ASO SQs. */
1639 : : struct mlx5_uar rx_uar; /* DevX UAR for Rx. */
1640 : : struct mlx5_proc_priv *pppriv; /* Pointer to primary private process. */
1641 : : struct mlx5_ecpri_parser_profile ecpri_parser;
1642 : : struct mlx5_internal_flex_parser_profile srh_flex_parser; /* srh flex parser structure. */
1643 : : /* Flex parser profiles information. */
1644 : : LIST_HEAD(shared_rxqs, mlx5_rxq_ctrl) shared_rxqs; /* Shared RXQs. */
1645 : : struct mlx5_aso_age_mng *aso_age_mng;
1646 : : /* Management data for aging mechanism using ASO Flow Hit. */
1647 : : struct mlx5_geneve_tlv_option_resource *geneve_tlv_option_resource;
1648 : : /* Management structure for geneve tlv option */
1649 : : rte_spinlock_t geneve_tlv_opt_sl; /* Lock for geneve tlv resource */
1650 : : struct mlx5_flow_mtr_mng *mtrmng;
1651 : : /* Meter management structure. */
1652 : : struct mlx5_aso_ct_pools_mng *ct_mng; /* Management data for ASO CT in HWS only. */
1653 : : struct mlx5_lb_ctx self_lb; /* QP to enable self loopback for Devx. */
1654 : : unsigned int flow_max_priority;
1655 : : enum modify_reg flow_mreg_c[MLX5_MREG_C_NUM];
1656 : : /* Availability of mreg_c's. */
1657 : : void *devx_channel_lwm;
1658 : : struct rte_intr_handle *intr_handle_lwm;
1659 : : pthread_mutex_t lwm_config_lock;
1660 : : uint32_t host_shaper_rate:8;
1661 : : uint32_t lwm_triggered:1;
1662 : : struct mlx5_hws_cnt_svc_mng *cnt_svc;
1663 : : rte_spinlock_t cpool_lock;
1664 : : LIST_HEAD(hws_cpool_list, mlx5_hws_cnt_pool) hws_cpool_list; /* Count pool list. */
1665 : : struct mlx5_dev_registers registers;
1666 : : struct mlx5_dev_shared_port port[]; /* per device port data array. */
1667 : : };
1668 : :
1669 : : /*
1670 : : * Per-process private structure.
1671 : : * Caution, secondary process may rebuild the struct during port start.
1672 : : */
1673 : : struct mlx5_proc_priv {
1674 : : RTE_ATOMIC(void *) hca_bar;
1675 : : /* Mapped HCA PCI BAR area. */
1676 : : size_t uar_table_sz;
1677 : : /* Size of UAR register table. */
1678 : : struct mlx5_uar_data uar_table[];
1679 : : /* Table of UAR registers for each process. */
1680 : : };
1681 : :
1682 : : /* MTR profile list. */
1683 : : TAILQ_HEAD(mlx5_mtr_profiles, mlx5_flow_meter_profile);
1684 : : /* MTR list. */
1685 : : TAILQ_HEAD(mlx5_legacy_flow_meters, mlx5_legacy_flow_meter);
1686 : :
1687 : : struct mlx5_mtr_config {
1688 : : uint32_t nb_meters; /**< Number of configured meters */
1689 : : uint32_t nb_meter_profiles; /**< Number of configured meter profiles */
1690 : : uint32_t nb_meter_policies; /**< Number of configured meter policies */
1691 : : };
1692 : :
1693 : : /* RSS description. */
1694 : : struct mlx5_flow_rss_desc {
1695 : : bool symmetric_hash_function; /**< Symmetric hash function */
1696 : : uint32_t level;
1697 : : uint32_t queue_num; /**< Number of entries in @p queue. */
1698 : : uint64_t types; /**< Specific RSS hash types (see RTE_ETH_RSS_*). */
1699 : : uint64_t hash_fields; /* Verbs Hash fields. */
1700 : : uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
1701 : : uint32_t key_len; /**< RSS hash key len. */
1702 : : uint32_t hws_flags; /**< HW steering action. */
1703 : : uint32_t tunnel; /**< Queue in tunnel. */
1704 : : uint32_t shared_rss; /**< Shared RSS index. */
1705 : : struct mlx5_ind_table_obj *ind_tbl;
1706 : : /**< Indirection table for shared RSS hash RX queues. */
1707 : : union {
1708 : : uint16_t *queue; /**< Destination queues. */
1709 : : const uint16_t *const_q; /**< Const pointer convert. */
1710 : : };
1711 : : };
1712 : :
1713 : : #define MLX5_PROC_PRIV(port_id) \
1714 : : ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private)
1715 : :
1716 : : /* Verbs/DevX Rx queue elements. */
1717 : : struct mlx5_rxq_obj {
1718 : : LIST_ENTRY(mlx5_rxq_obj) next; /* Pointer to the next element. */
1719 : : struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */
1720 : : int fd; /* File descriptor for event channel */
1721 : : union {
1722 : : struct {
1723 : : void *wq; /* Work Queue. */
1724 : : void *ibv_cq; /* Completion Queue. */
1725 : : void *ibv_channel;
1726 : : };
1727 : : struct mlx5_devx_obj *rq; /* DevX RQ object for hairpin. */
1728 : : struct {
1729 : : struct mlx5_devx_rmp devx_rmp; /* RMP for shared RQ. */
1730 : : struct mlx5_devx_cq cq_obj; /* DevX CQ object. */
1731 : : void *devx_channel;
1732 : : };
1733 : : };
1734 : : };
1735 : :
1736 : : /* Indirection table. */
1737 : : struct mlx5_ind_table_obj {
1738 : : LIST_ENTRY(mlx5_ind_table_obj) next; /* Pointer to the next element. */
1739 : : RTE_ATOMIC(uint32_t) refcnt; /* Reference counter. */
1740 : : union {
1741 : : void *ind_table; /**< Indirection table. */
1742 : : struct mlx5_devx_obj *rqt; /* DevX RQT object. */
1743 : : };
1744 : : uint32_t queues_n; /**< Number of queues in the list. */
1745 : : uint16_t *queues; /**< Queue list. */
1746 : : };
1747 : :
1748 : : /* Hash Rx queue. */
1749 : : __extension__
1750 : : struct mlx5_hrxq {
1751 : : struct mlx5_list_entry entry; /* List entry. */
1752 : : uint32_t standalone:1; /* This object used in shared action. */
1753 : : struct mlx5_ind_table_obj *ind_table; /* Indirection table. */
1754 : : union {
1755 : : void *qp; /* Verbs queue pair. */
1756 : : struct mlx5_devx_obj *tir; /* DevX TIR object. */
1757 : : };
1758 : : #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1759 : : void *action; /* DV QP action pointer. */
1760 : : #endif
1761 : : bool symmetric_hash_function; /* Symmetric hash function */
1762 : : uint32_t hws_flags; /* Hw steering flags. */
1763 : : uint64_t hash_fields; /* Verbs Hash fields. */
1764 : : uint32_t rss_key_len; /* Hash key length in bytes. */
1765 : : uint32_t idx; /* Hash Rx queue index. */
1766 : : uint8_t rss_key[]; /* Hash key. */
1767 : : };
1768 : :
1769 : : /* Verbs/DevX Tx queue elements. */
1770 : : struct mlx5_txq_obj {
1771 : : LIST_ENTRY(mlx5_txq_obj) next; /* Pointer to the next element. */
1772 : : struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */
1773 : : union {
1774 : : struct {
1775 : : void *cq; /* Completion Queue. */
1776 : : void *qp; /* Queue Pair. */
1777 : : };
1778 : : struct {
1779 : : struct mlx5_devx_obj *sq;
1780 : : /* DevX object for Sx queue. */
1781 : : struct mlx5_devx_obj *tis; /* The TIS object. */
1782 : : void *umem_buf_wq_buffer;
1783 : : void *umem_obj_wq_buffer;
1784 : : };
1785 : : struct {
1786 : : struct rte_eth_dev *dev;
1787 : : struct mlx5_devx_cq cq_obj;
1788 : : /* DevX CQ object and its resources. */
1789 : : struct mlx5_devx_sq sq_obj;
1790 : : /* DevX SQ object and its resources. */
1791 : : };
1792 : : };
1793 : : };
1794 : :
1795 : : enum mlx5_rxq_modify_type {
1796 : : MLX5_RXQ_MOD_ERR2RST, /* modify state from error to reset. */
1797 : : MLX5_RXQ_MOD_RST2RDY, /* modify state from reset to ready. */
1798 : : MLX5_RXQ_MOD_RDY2ERR, /* modify state from ready to error. */
1799 : : MLX5_RXQ_MOD_RDY2RST, /* modify state from ready to reset. */
1800 : : MLX5_RXQ_MOD_RDY2RDY, /* modify state from ready to ready. */
1801 : : };
1802 : :
1803 : : enum mlx5_txq_modify_type {
1804 : : MLX5_TXQ_MOD_RST2RDY, /* modify state from reset to ready. */
1805 : : MLX5_TXQ_MOD_RDY2RST, /* modify state from ready to reset. */
1806 : : MLX5_TXQ_MOD_ERR2RDY, /* modify state from error to ready. */
1807 : : };
1808 : :
1809 : : struct mlx5_rxq_priv;
1810 : : struct mlx5_priv;
1811 : :
1812 : : /* HW objects operations structure. */
1813 : : struct mlx5_obj_ops {
1814 : : int (*rxq_obj_modify_vlan_strip)(struct mlx5_rxq_priv *rxq, int on);
1815 : : int (*rxq_obj_modify_counter_set_id)(struct mlx5_rxq_priv *rxq, uint32_t counter_set_id);
1816 : : int (*rxq_obj_new)(struct mlx5_rxq_priv *rxq);
1817 : : int (*rxq_event_get)(struct mlx5_rxq_obj *rxq_obj);
1818 : : int (*rxq_obj_modify)(struct mlx5_rxq_priv *rxq, uint8_t type);
1819 : : void (*rxq_obj_release)(struct mlx5_rxq_priv *rxq);
1820 : : int (*rxq_event_get_lwm)(struct mlx5_priv *priv, int *rxq_idx, int *port_id);
1821 : : int (*ind_table_new)(struct rte_eth_dev *dev, const unsigned int log_n,
1822 : : struct mlx5_ind_table_obj *ind_tbl);
1823 : : int (*ind_table_modify)(struct rte_eth_dev *dev,
1824 : : const unsigned int log_n,
1825 : : const uint16_t *queues, const uint32_t queues_n,
1826 : : struct mlx5_ind_table_obj *ind_tbl);
1827 : : void (*ind_table_destroy)(struct mlx5_ind_table_obj *ind_tbl);
1828 : : int (*hrxq_new)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,
1829 : : int tunnel __rte_unused);
1830 : : int (*hrxq_modify)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,
1831 : : const uint8_t *rss_key,
1832 : : uint64_t hash_fields,
1833 : : bool symmetric_hash_function,
1834 : : const struct mlx5_ind_table_obj *ind_tbl);
1835 : : void (*hrxq_destroy)(struct mlx5_hrxq *hrxq);
1836 : : int (*drop_action_create)(struct rte_eth_dev *dev);
1837 : : void (*drop_action_destroy)(struct rte_eth_dev *dev);
1838 : : int (*txq_obj_new)(struct rte_eth_dev *dev, uint16_t idx);
1839 : : int (*txq_obj_modify)(struct mlx5_txq_obj *obj,
1840 : : enum mlx5_txq_modify_type type, uint8_t dev_port);
1841 : : void (*txq_obj_release)(struct mlx5_txq_obj *txq_obj);
1842 : : int (*lb_dummy_queue_create)(struct rte_eth_dev *dev);
1843 : : void (*lb_dummy_queue_release)(struct rte_eth_dev *dev);
1844 : : };
1845 : :
1846 : : enum mlx5_ctrl_flow_type {
1847 : : MLX5_CTRL_FLOW_TYPE_GENERAL,
1848 : : MLX5_CTRL_FLOW_TYPE_SQ_MISS_ROOT,
1849 : : MLX5_CTRL_FLOW_TYPE_SQ_MISS,
1850 : : MLX5_CTRL_FLOW_TYPE_DEFAULT_JUMP,
1851 : : MLX5_CTRL_FLOW_TYPE_TX_META_COPY,
1852 : : MLX5_CTRL_FLOW_TYPE_TX_REPR_MATCH,
1853 : : MLX5_CTRL_FLOW_TYPE_LACP_RX,
1854 : : MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS,
1855 : : MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC,
1856 : : MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC_VLAN,
1857 : : };
1858 : :
1859 : : /** Additional info about control flow rule. */
1860 : : struct mlx5_ctrl_flow_info {
1861 : : /** Determines the kind of control flow rule. */
1862 : : enum mlx5_ctrl_flow_type type;
1863 : : union {
1864 : : /**
1865 : : * If control flow is a SQ miss flow (root or not),
1866 : : * then fields contains matching SQ number.
1867 : : */
1868 : : uint32_t esw_mgr_sq;
1869 : : /**
1870 : : * If control flow is a Tx representor matching,
1871 : : * then fields contains matching SQ number.
1872 : : */
1873 : : uint32_t tx_repr_sq;
1874 : : /** Contains data relevant for unicast control flow rules. */
1875 : : struct {
1876 : : /**
1877 : : * If control flow is a unicast DMAC (or with VLAN) flow rule,
1878 : : * then this field contains DMAC.
1879 : : */
1880 : : struct rte_ether_addr dmac;
1881 : : /**
1882 : : * If control flow is a unicast DMAC with VLAN flow rule,
1883 : : * then this field contains VLAN ID.
1884 : : */
1885 : : uint16_t vlan;
1886 : : } uc;
1887 : : };
1888 : : };
1889 : :
1890 : : /** Returns true if a control flow rule with unicast DMAC match on given address was created. */
1891 : : bool mlx5_ctrl_flow_uc_dmac_exists(struct rte_eth_dev *dev, const struct rte_ether_addr *addr);
1892 : :
1893 : : /**
1894 : : * Returns true if a control flow rule with unicast DMAC and VLAN match
1895 : : * on given values was created.
1896 : : */
1897 : : bool mlx5_ctrl_flow_uc_dmac_vlan_exists(struct rte_eth_dev *dev,
1898 : : const struct rte_ether_addr *addr,
1899 : : const uint16_t vid);
1900 : :
1901 : : /** Entry for tracking control flow rules in HWS. */
1902 : : struct mlx5_ctrl_flow_entry {
1903 : : LIST_ENTRY(mlx5_ctrl_flow_entry) next;
1904 : : /**
1905 : : * Owner device is a port on behalf of which flow rule was created.
1906 : : *
1907 : : * It's different from the port which really created the flow rule
1908 : : * if and only if flow rule is created on transfer proxy port
1909 : : * on behalf of representor port.
1910 : : */
1911 : : struct rte_eth_dev *owner_dev;
1912 : : /** Pointer to flow rule handle. */
1913 : : struct rte_flow *flow;
1914 : : /** Additional information about the control flow rule. */
1915 : : struct mlx5_ctrl_flow_info info;
1916 : : };
1917 : :
1918 : : /* HW Steering port configuration passed to rte_flow_configure(). */
1919 : : struct mlx5_flow_hw_attr {
1920 : : struct rte_flow_port_attr port_attr;
1921 : : uint16_t nb_queue;
1922 : : struct rte_flow_queue_attr *queue_attr;
1923 : : bool nt_mode;
1924 : : };
1925 : :
1926 : : /*
1927 : : * Flow rule structure for flow engine mode control, focus on group 0.
1928 : : * Apply to all supported domains.
1929 : : */
1930 : : struct mlx5_dv_flow_info {
1931 : : LIST_ENTRY(mlx5_dv_flow_info) next;
1932 : : uint32_t orig_prio; /* prio set by user */
1933 : : uint32_t flow_idx_high_prio;
1934 : : /* flow index owned by standby mode. priority is lower unless DUP flags. */
1935 : : uint32_t flow_idx_low_prio;
1936 : : struct rte_flow_item *items;
1937 : : struct rte_flow_action *actions;
1938 : : struct rte_flow_attr attr;
1939 : : };
1940 : :
1941 : : struct rte_pmd_mlx5_flow_engine_mode_info {
1942 : : enum rte_pmd_mlx5_flow_engine_mode mode;
1943 : : uint32_t mode_flag;
1944 : : /* The list is maintained in insertion order. */
1945 : : LIST_HEAD(hot_up_info, mlx5_dv_flow_info) hot_upgrade;
1946 : : };
1947 : :
1948 : : struct mlx5_flow_hw_ctrl_rx;
1949 : :
1950 : : enum mlx5_quota_state {
1951 : : MLX5_QUOTA_STATE_FREE, /* quota not in use */
1952 : : MLX5_QUOTA_STATE_READY, /* quota is ready */
1953 : : MLX5_QUOTA_STATE_WAIT /* quota waits WR completion */
1954 : : };
1955 : :
1956 : : struct mlx5_quota {
1957 : : RTE_ATOMIC(uint8_t) state; /* object state */
1958 : : uint8_t mode; /* metering mode */
1959 : : /**
1960 : : * Keep track of application update types.
1961 : : * PMD does not allow 2 consecutive ADD updates.
1962 : : */
1963 : : enum rte_flow_update_quota_op last_update;
1964 : : };
1965 : :
1966 : : /* Bulk management structure for flow quota. */
1967 : : struct mlx5_quota_ctx {
1968 : : struct mlx5dr_action *dr_action; /* HWS action */
1969 : : struct mlx5_devx_obj *devx_obj; /* DEVX ranged object. */
1970 : : struct mlx5_pmd_mr mr; /* MR for READ from MTR ASO */
1971 : : struct mlx5_aso_mtr_dseg **read_buf; /* Buffers for READ */
1972 : : struct mlx5_aso_sq *sq; /* SQs for sync/async ACCESS_ASO WRs */
1973 : : struct mlx5_indexed_pool *quota_ipool; /* Manage quota objects */
1974 : : };
1975 : :
1976 : : struct mlx5_nta_sample_ctx;
1977 : : struct mlx5_priv {
1978 : : struct rte_eth_dev_data *dev_data; /* Pointer to device data. */
1979 : : struct mlx5_dev_ctx_shared *sh; /* Shared device context. */
1980 : : uint32_t dev_port; /* Device port number. */
1981 : : struct rte_pci_device *pci_dev; /* Backend PCI device. */
1982 : : struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
1983 : : BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES);
1984 : : /* Bit-field of MAC addresses owned by the PMD. */
1985 : : uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
1986 : : unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
1987 : : /* Device properties. */
1988 : : uint16_t min_mtu; /* Minimum MTU allowed on the NIC. */
1989 : : uint16_t max_mtu; /* Maximum MTU allowed on the NIC. */
1990 : : unsigned int isolated:1; /* Whether isolated mode is enabled. */
1991 : : unsigned int representor:1; /* Device is a port representor. */
1992 : : unsigned int master:1; /* Device is a E-Switch master. */
1993 : : unsigned int txpp_en:1; /* Tx packet pacing enabled. */
1994 : : unsigned int sampler_en:1; /* Whether support sampler. */
1995 : : unsigned int mtr_en:1; /* Whether support meter. */
1996 : : unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */
1997 : : unsigned int lb_used:1; /* Loopback queue is referred to. */
1998 : : unsigned int rmv_notified:1; /* Notified about removal event */
1999 : : uint32_t mark_enabled:1; /* If mark action is enabled on rxqs. */
2000 : : uint32_t num_lag_ports:4; /* Number of ports can be bonded. */
2001 : : uint32_t tunnel_enabled:1; /* If tunnel offloading is enabled on rxqs. */
2002 : : uint32_t unified_fdb_en:1; /* Unified FDB flag per port. */
2003 : : uint32_t jump_fdb_rx_en:1; /* Jump from FDB Tx to FDB Rx flag per port. */
2004 : : uint16_t domain_id; /* Switch domain identifier. */
2005 : : uint16_t vport_id; /* Associated VF vport index (if any). */
2006 : : uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */
2007 : : uint32_t vport_meta_mask; /* Used for vport index field match mask. */
2008 : : uint16_t representor_id; /* UINT16_MAX if not a representor. */
2009 : : int32_t pf_bond; /* >=0, representor owner PF index in bonding. */
2010 : : int32_t mpesw_owner; /* >=0, representor owner PF index in MPESW. */
2011 : : int32_t mpesw_port; /* Related port index of MPESW device. < 0 - no MPESW. */
2012 : : bool mpesw_uplink; /* If true, port is an uplink port. */
2013 : : unsigned int if_index; /* Associated kernel network device index. */
2014 : : /* RX/TX queues. */
2015 : : unsigned int rxqs_n; /* RX queues array size. */
2016 : : unsigned int txqs_n; /* TX queues array size. */
2017 : : struct mlx5_external_q *ext_rxqs; /* External RX queues array. */
2018 : : struct mlx5_external_q *ext_txqs; /* External TX queues array. */
2019 : : struct mlx5_rxq_priv *(*rxq_privs)[]; /* RX queue non-shared data. */
2020 : : struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
2021 : : struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
2022 : : struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
2023 : : unsigned int (*reta_idx)[]; /* RETA index table. */
2024 : : unsigned int reta_idx_n; /* RETA index size. */
2025 : : struct mlx5_drop drop_queue; /* Flow drop queues. */
2026 : : void *root_drop_action; /* Pointer to root drop action. */
2027 : : rte_spinlock_t hw_ctrl_lock;
2028 : : LIST_HEAD(hw_ctrl_flow, mlx5_ctrl_flow_entry) hw_ctrl_flows;
2029 : : LIST_HEAD(hw_ext_ctrl_flow, mlx5_ctrl_flow_entry) hw_ext_ctrl_flows;
2030 : : struct mlx5_flow_hw_ctrl_fdb *hw_ctrl_fdb; /* FDB control flow context */
2031 : : struct mlx5_flow_hw_ctrl_nic *hw_ctrl_nic; /* NIC control flow context */
2032 : : struct rte_flow_pattern_template *hw_tx_repr_tagging_pt;
2033 : : struct rte_flow_actions_template *hw_tx_repr_tagging_at;
2034 : : struct rte_flow_template_table *hw_tx_repr_tagging_tbl;
2035 : : struct mlx5_indexed_pool *flows[MLX5_FLOW_TYPE_MAXI];
2036 : : /* RTE Flow rules. */
2037 : : uint32_t ctrl_flows; /* Control flow rules. */
2038 : : rte_spinlock_t flow_list_lock;
2039 : : struct mlx5_obj_ops obj_ops; /* HW objects operations. */
2040 : : LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
2041 : : LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */
2042 : : struct mlx5_list *hrxqs; /* Hash Rx queues. */
2043 : : LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
2044 : : LIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */
2045 : : /* Indirection tables. */
2046 : : LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls;
2047 : : /* Standalone indirect tables. */
2048 : : LIST_HEAD(stdl_ind_tables, mlx5_ind_table_obj) standalone_ind_tbls;
2049 : : /* Objects created with indirect list action */
2050 : : LIST_HEAD(indirect_list, mlx5_indirect_list) indirect_list_head;
2051 : : /* Pointer to next element. */
2052 : : rte_rwlock_t ind_tbls_lock;
2053 : : uint32_t refcnt; /**< Reference counter. */
2054 : : /**< Verbs modify header action object. */
2055 : : uint8_t ft_type; /**< Flow table type, Rx or Tx. */
2056 : : uint32_t max_lro_msg_size;
2057 : : uint32_t link_speed_capa; /* Link speed capabilities. */
2058 : : struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
2059 : : struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */
2060 : : struct mlx5_port_config config; /* Port configuration. */
2061 : : /* Context for Verbs allocator. */
2062 : : int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */
2063 : : int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
2064 : : struct mlx5_nl_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */
2065 : : struct mlx5_mtr_config mtr_config; /* Meter configuration */
2066 : : uint8_t mtr_sfx_reg; /* Meter prefix-suffix flow match REG_C. */
2067 : : struct mlx5_legacy_flow_meters flow_meters; /* MTR list. */
2068 : : struct mlx5_l3t_tbl *mtr_profile_tbl; /* Meter index lookup table. */
2069 : : struct mlx5_flow_meter_profile *mtr_profile_arr; /* Profile array. */
2070 : : struct mlx5_l3t_tbl *policy_idx_tbl; /* Policy index lookup table. */
2071 : : struct mlx5_flow_meter_policy *mtr_policy_arr; /* Policy array. */
2072 : : struct mlx5_l3t_tbl *mtr_idx_tbl; /* Meter index lookup table. */
2073 : : struct mlx5_mtr_bulk mtr_bulk; /* Meter index mapping for HWS */
2074 : : struct mlx5_quota_ctx quota_ctx; /* Quota index mapping for HWS */
2075 : : uint8_t skip_default_rss_reta; /* Skip configuration of default reta. */
2076 : : uint8_t fdb_def_rule; /* Whether fdb jump to table 1 is configured. */
2077 : : struct mlx5_mp_id mp_id; /* ID of a multi-process process */
2078 : : LIST_HEAD(fdir, mlx5_fdir_flow) fdir_flows; /* fdir flows. */
2079 : : rte_spinlock_t shared_act_sl; /* Shared actions spinlock. */
2080 : : uint32_t rss_shared_actions; /* RSS shared actions. */
2081 : : /**< Total number of hairpin queues attach to q counters. */
2082 : : uint64_t num_of_hairpin_q_counter_enabled;
2083 : : struct mlx5_devx_obj *q_counters; /* DevX queue counter object. */
2084 : : uint32_t counter_set_id; /* Queue counter ID to set in DevX objects. */
2085 : : /* DevX queue counter object for all hairpin queues of the port. */
2086 : : struct mlx5_devx_obj *q_counter_hairpin;
2087 : : uint32_t lag_affinity_idx; /* LAG mode queue 0 affinity starting. */
2088 : : rte_spinlock_t flex_item_sl; /* Flex item list spinlock. */
2089 : : struct mlx5_flex_item flex_item[MLX5_PORT_FLEX_ITEM_NUM];
2090 : : /* Flex items have been created on the port. */
2091 : : uint32_t flex_item_map; /* Map of allocated flex item elements. */
2092 : : uint32_t nb_queue; /* HW steering queue number. */
2093 : : struct mlx5_hws_cnt_pool *hws_cpool; /* HW steering's counter pool. */
2094 : : RTE_ATOMIC(uint32_t) hws_mark_refcnt; /* HWS mark action reference counter. */
2095 : : struct rte_pmd_mlx5_flow_engine_mode_info mode_info; /* Process set flow engine info. */
2096 : : struct mlx5_flow_hw_attr *hw_attr; /* HW Steering port configuration. */
2097 : : bool hws_rule_flushing; /**< Whether this port is in rules flushing stage. */
2098 : : #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
2099 : : /* Item template list. */
2100 : : LIST_HEAD(flow_hw_itt, rte_flow_pattern_template) flow_hw_itt;
2101 : : /* Action template list. */
2102 : : LIST_HEAD(flow_hw_at, rte_flow_actions_template) flow_hw_at;
2103 : : struct mlx5dr_context *dr_ctx; /**< HW steering DR context. */
2104 : : /* Pointer to the GENEVE TLV options. */
2105 : : struct mlx5_geneve_tlv_options *tlv_options;
2106 : : /* HW steering queue polling mechanism job descriptor LIFO. */
2107 : : uint32_t hws_strict_queue:1;
2108 : : /**< Whether all operations strictly happen on the same HWS queue. */
2109 : : uint32_t hws_age_req:1; /**< Whether this port has AGE indexed pool. */
2110 : : struct mlx5_hw_q *hw_q;
2111 : : /* HW steering rte flow table list header. */
2112 : : LIST_HEAD(flow_hw_tbl, rte_flow_template_table) flow_hw_tbl;
2113 : : /* HW steering rte flow group list header */
2114 : : LIST_HEAD(flow_hw_grp, mlx5_flow_group) flow_hw_grp;
2115 : : struct mlx5dr_action **hw_vport;
2116 : : /* HWS global actions. */
2117 : : struct mlx5_hws_global_actions hw_global_actions;
2118 : : /* HW steering create ongoing rte flow table list header. */
2119 : : LIST_HEAD(flow_hw_tbl_ongo, rte_flow_template_table) flow_hw_tbl_ongo;
2120 : : struct mlx5_indexed_pool *acts_ipool; /* Action data indexed pool. */
2121 : : struct mlx5_aso_ct_pools_mng *ct_mng;
2122 : : /* Management data for ASO connection tracking. */
2123 : : struct mlx5_aso_ct_pool *hws_ctpool; /* HW steering's CT pool. */
2124 : : struct mlx5_aso_mtr_pool *hws_mpool; /* HW steering's Meter pool. */
2125 : : struct mlx5_flow_hw_ctrl_rx *hw_ctrl_rx;
2126 : : /**< HW steering templates used to create control flow rules. */
2127 : :
2128 : : struct rte_flow_actions_template *action_template_drop[MLX5DR_TABLE_TYPE_MAX];
2129 : :
2130 : : struct mlx5_indexed_pool *ptype_rss_groups;
2131 : : struct mlx5_nta_sample_ctx *nta_sample_ctx;
2132 : : #endif
2133 : : struct rte_eth_dev *shared_host; /* Host device for HW steering. */
2134 : : struct {
2135 : : uint32_t sq_total_size;
2136 : : uint32_t cq_total_size;
2137 : : void *umem;
2138 : : void *umem_obj;
2139 : : uint32_t sq_cur_off;
2140 : : uint32_t cq_cur_off;
2141 : : } consec_tx_mem;
2142 : : RTE_ATOMIC(uint16_t) shared_refcnt; /* HW steering host reference counter. */
2143 : : };
2144 : :
2145 : : static __rte_always_inline bool
2146 : : mlx5_hws_active(const struct rte_eth_dev *dev)
2147 : : {
2148 : : #if defined(HAVE_MLX5_HWS_SUPPORT)
2149 : 0 : const struct mlx5_priv *priv = dev->data->dev_private;
2150 : :
2151 [ # # # # : 0 : return priv->sh->config.dv_flow_en == 2;
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
2152 : : #else
2153 : : RTE_SET_USED(dev);
2154 : : return false;
2155 : : #endif
2156 : : }
2157 : :
2158 : : #define PORT_ID(priv) ((priv)->dev_data->port_id)
2159 : : #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)])
2160 : : #define CTRL_QUEUE_ID(priv) ((priv)->nb_queue - 1)
2161 : :
2162 : : struct rte_hairpin_peer_info {
2163 : : uint32_t qp_id;
2164 : : uint32_t vhca_id;
2165 : : uint16_t peer_q;
2166 : : uint16_t tx_explicit;
2167 : : uint16_t manual_bind;
2168 : : };
2169 : :
2170 : : #define BUF_SIZE 1024
2171 : : enum dr_dump_rec_type {
2172 : : DR_DUMP_REC_TYPE_PMD_PKT_REFORMAT = 4410,
2173 : : DR_DUMP_REC_TYPE_PMD_MODIFY_HDR = 4420,
2174 : : DR_DUMP_REC_TYPE_PMD_COUNTER = 4430,
2175 : : };
2176 : :
2177 : : #if defined(HAVE_MLX5_HWS_SUPPORT)
2178 : : static __rte_always_inline struct mlx5_hw_q_job *
2179 : : flow_hw_job_get(struct mlx5_priv *priv, uint32_t queue)
2180 : : {
2181 : : MLX5_ASSERT(priv->hw_q[queue].job_idx <= priv->hw_q[queue].size);
2182 : 0 : return priv->hw_q[queue].job_idx ?
2183 [ # # # # : 0 : priv->hw_q[queue].job[--priv->hw_q[queue].job_idx] : NULL;
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
2184 : : }
2185 : :
2186 : : static __rte_always_inline void
2187 : : flow_hw_job_put(struct mlx5_priv *priv, struct mlx5_hw_q_job *job, uint32_t queue)
2188 : : {
2189 : : MLX5_ASSERT(priv->hw_q[queue].job_idx < priv->hw_q[queue].size);
2190 : 0 : priv->hw_q[queue].job[priv->hw_q[queue].job_idx++] = job;
2191 : 0 : }
2192 : :
2193 : : struct mlx5_hw_q_job *
2194 : : mlx5_flow_action_job_init(struct mlx5_priv *priv, uint32_t queue,
2195 : : const struct rte_flow_action_handle *handle,
2196 : : void *user_data, void *query_data,
2197 : : enum mlx5_hw_job_type type,
2198 : : struct rte_flow_error *error);
2199 : : #endif
2200 : :
2201 : : /**
2202 : : * Indicates whether HW objects operations can be created by DevX.
2203 : : *
2204 : : * This function is used for both:
2205 : : * Before creation - deciding whether to create HW objects operations by DevX.
2206 : : * After creation - indicator if HW objects operations were created by DevX.
2207 : : *
2208 : : * @param sh
2209 : : * Pointer to shared device context.
2210 : : *
2211 : : * @return
2212 : : * True if HW objects were created by DevX, False otherwise.
2213 : : */
2214 : : static inline bool
2215 : : mlx5_devx_obj_ops_en(struct mlx5_dev_ctx_shared *sh)
2216 : : {
2217 : : /*
2218 : : * When advanced DR API is available and DV flow is supported and
2219 : : * DevX is supported, HW objects operations are created by DevX.
2220 : : */
2221 [ # # # # : 0 : return (sh->cdev->config.devx && sh->config.dv_flow_en &&
# # # # #
# # # # #
# # ]
2222 : : sh->dev_cap.dest_tir);
2223 : : }
2224 : :
2225 : : /**
2226 : : * Check if the port is either MPESW physical device or a representor port.
2227 : : *
2228 : : * @param priv
2229 : : * Pointer to port's private data.
2230 : : *
2231 : : * @return
2232 : : * True if the port is a physical device or representor in MPESW setup.
2233 : : * False otherwise or MPESW was not configured.
2234 : : */
2235 : : static inline bool
2236 : : mlx5_is_port_on_mpesw_device(struct mlx5_priv *priv)
2237 : : {
2238 [ # # ]: 0 : return priv->mpesw_port >= 0;
2239 : : }
2240 : :
2241 : : static inline bool
2242 : : is_unified_fdb(const struct mlx5_priv *priv)
2243 : : {
2244 : : /* Only needed on proxy port in E-Switch mode. */
2245 [ # # # # : 0 : return priv->unified_fdb_en;
# # # # #
# # # # #
# # # # #
# ]
2246 : : }
2247 : :
2248 : : /* mlx5.c */
2249 : :
2250 : : int mlx5_getenv_int(const char *);
2251 : : int mlx5_proc_priv_init(struct rte_eth_dev *dev);
2252 : : void mlx5_proc_priv_uninit(struct rte_eth_dev *dev);
2253 : : int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev,
2254 : : struct rte_eth_udp_tunnel *udp_tunnel);
2255 : : uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_device *odev);
2256 : : int mlx5_dev_close(struct rte_eth_dev *dev);
2257 : : int mlx5_net_remove(struct mlx5_common_device *cdev);
2258 : : bool mlx5_is_hpf(struct rte_eth_dev *dev);
2259 : : bool mlx5_is_sf_repr(struct rte_eth_dev *dev);
2260 : : void mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh);
2261 : : int mlx5_lwm_setup(struct mlx5_priv *priv);
2262 : : void mlx5_lwm_unset(struct mlx5_dev_ctx_shared *sh);
2263 : : int mlx5_enable_port_level_hairpin_counter(struct rte_eth_dev *dev, uint64_t id);
2264 : : int mlx5_disable_port_level_hairpin_counter(struct rte_eth_dev *dev, uint64_t id);
2265 : : int mlx5_enable_per_queue_hairpin_counter(struct rte_eth_dev *dev, uint64_t id);
2266 : : int mlx5_disable_per_queue_hairpin_counter(struct rte_eth_dev *dev, uint64_t id);
2267 : :
2268 : : /* Macro to iterate over all valid ports for mlx5 driver. */
2269 : : #define MLX5_ETH_FOREACH_DEV(port_id, dev) \
2270 : : for (port_id = mlx5_eth_find_next(0, dev); \
2271 : : port_id < RTE_MAX_ETHPORTS; \
2272 : : port_id = mlx5_eth_find_next(port_id + 1, dev))
2273 : : void mlx5_rt_timestamp_config(struct mlx5_dev_ctx_shared *sh,
2274 : : struct mlx5_hca_attr *hca_attr);
2275 : : struct mlx5_dev_ctx_shared *
2276 : : mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
2277 : : struct mlx5_kvargs_ctrl *mkvlist);
2278 : : void mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh);
2279 : : int mlx5_dev_ctx_shared_mempool_subscribe(struct rte_eth_dev *dev);
2280 : : void mlx5_free_table_hash_list(struct mlx5_priv *priv);
2281 : : int mlx5_alloc_table_hash_list(struct mlx5_priv *priv);
2282 : : void mlx5_set_min_inline(struct mlx5_priv *priv);
2283 : : void mlx5_set_metadata_mask(struct rte_eth_dev *dev);
2284 : : int mlx5_probe_again_args_validate(struct mlx5_common_device *cdev,
2285 : : struct mlx5_kvargs_ctrl *mkvlist);
2286 : : int mlx5_port_args_config(struct mlx5_priv *priv,
2287 : : struct mlx5_kvargs_ctrl *mkvlist,
2288 : : struct mlx5_port_config *config);
2289 : : void mlx5_port_args_set_used(const char *name, uint16_t port_id,
2290 : : struct mlx5_kvargs_ctrl *mkvlist);
2291 : : bool mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev);
2292 : : int mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev);
2293 : : void mlx5_flow_counter_mode_config(struct rte_eth_dev *dev);
2294 : : int mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh);
2295 : : int mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh);
2296 : : int mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh);
2297 : : struct mlx5_physical_device *
2298 : : mlx5_get_locked_physical_device(struct mlx5_priv *priv);
2299 : : void mlx5_unlock_physical_device(void);
2300 : : int mlx5_read_queue_counter(struct mlx5_devx_obj *q_counter, const char *ctr_name, uint64_t *stat);
2301 : : void mlx5_fixup_flow_config(struct mlx5_sh_config *config,
2302 : : struct mlx5_dev_ctx_shared *sh,
2303 : : struct mlx5_kvargs_ctrl *mkvlist);
2304 : :
2305 : : /* mlx5_ethdev.c */
2306 : :
2307 : : int mlx5_dev_configure(struct rte_eth_dev *dev);
2308 : : int mlx5_representor_info_get(struct rte_eth_dev *dev,
2309 : : struct rte_eth_representor_info *info);
2310 : : #define MLX5_REPRESENTOR_ID(pf, type, repr) \
2311 : : (((pf) << 14) + ((type) << 12) + ((repr) & 0xfff))
2312 : : #define MLX5_REPRESENTOR_REPR(repr_id) \
2313 : : ((repr_id) & 0xfff)
2314 : : #define MLX5_REPRESENTOR_TYPE(repr_id) \
2315 : : (((repr_id) >> 12) & 3)
2316 : : uint16_t mlx5_representor_id_encode(const struct mlx5_switch_info *info,
2317 : : enum rte_eth_representor_type hpf_type);
2318 : : uint16_t mlx5_dev_get_max_wq_size(struct mlx5_dev_ctx_shared *sh);
2319 : : int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
2320 : : int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size);
2321 : : const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev,
2322 : : size_t *no_of_elements);
2323 : : int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
2324 : : int mlx5_hairpin_cap_get(struct rte_eth_dev *dev,
2325 : : struct rte_eth_hairpin_cap *cap);
2326 : : eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev);
2327 : : struct mlx5_priv *mlx5_port_to_eswitch_info(uint16_t port, bool valid);
2328 : : struct mlx5_priv *mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev);
2329 : : int mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev);
2330 : : uint64_t mlx5_get_restore_flags(struct rte_eth_dev *dev,
2331 : : enum rte_eth_dev_operation op);
2332 : : void mlx5_get_mtu_bounds(struct rte_eth_dev *dev, uint16_t *min_mtu, uint16_t *max_mtu);
2333 : :
2334 : : /* mlx5_ethdev_os.c */
2335 : :
2336 : : int mlx5_get_ifname(const struct rte_eth_dev *dev, char ifname[MLX5_NAMESIZE]);
2337 : : unsigned int mlx5_ifindex(const struct rte_eth_dev *dev);
2338 : : int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]);
2339 : : int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu);
2340 : : int mlx5_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
2341 : : int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock);
2342 : : int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete);
2343 : : int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev,
2344 : : struct rte_eth_fc_conf *fc_conf);
2345 : : int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev,
2346 : : struct rte_eth_fc_conf *fc_conf);
2347 : : void mlx5_dev_interrupt_handler(void *arg);
2348 : : void mlx5_dev_interrupt_handler_devx(void *arg);
2349 : : void mlx5_dev_interrupt_handler_nl(void *arg);
2350 : : void mlx5_dev_interrupt_handler_ib(void *arg);
2351 : : int mlx5_set_link_down(struct rte_eth_dev *dev);
2352 : : int mlx5_set_link_up(struct rte_eth_dev *dev);
2353 : : int mlx5_is_removed(struct rte_eth_dev *dev);
2354 : : int mlx5_sysfs_switch_info(unsigned int ifindex,
2355 : : struct mlx5_switch_info *info);
2356 : : void mlx5_translate_port_name(const char *port_name_in,
2357 : : struct mlx5_switch_info *port_info_out);
2358 : : int mlx5_sysfs_bond_info(unsigned int pf_ifindex, unsigned int *ifindex,
2359 : : char *ifname);
2360 : : int mlx5_get_module_info(struct rte_eth_dev *dev,
2361 : : struct rte_eth_dev_module_info *modinfo);
2362 : : int mlx5_get_module_eeprom(struct rte_eth_dev *dev,
2363 : : struct rte_dev_eeprom_info *info);
2364 : : int mlx5_os_read_dev_stat(struct mlx5_priv *priv,
2365 : : const char *ctr_name, uint64_t *stat);
2366 : : int mlx5_os_read_dev_counters(struct rte_eth_dev *dev, bool bond_master, uint64_t *stats);
2367 : : int mlx5_os_get_stats_n(struct rte_eth_dev *dev, bool bond_master,
2368 : : uint16_t *n_stats, uint16_t *n_stats_sec);
2369 : : void mlx5_os_stats_init(struct rte_eth_dev *dev);
2370 : : int mlx5_get_flag_dropless_rq(struct rte_eth_dev *dev);
2371 : : int mlx5_os_get_mtu_bounds(struct rte_eth_dev *dev, uint16_t *min_mtu, uint16_t *max_mtu);
2372 : :
2373 : : /* mlx5_mac.c */
2374 : :
2375 : : void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
2376 : : int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
2377 : : uint32_t index, uint32_t vmdq);
2378 : : int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr);
2379 : : int mlx5_set_mc_addr_list(struct rte_eth_dev *dev,
2380 : : struct rte_ether_addr *mc_addr_set,
2381 : : uint32_t nb_mc_addr);
2382 : :
2383 : : /* mlx5_rss.c */
2384 : :
2385 : : int mlx5_rss_hash_update(struct rte_eth_dev *dev,
2386 : : struct rte_eth_rss_conf *rss_conf);
2387 : : int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev,
2388 : : struct rte_eth_rss_conf *rss_conf);
2389 : : int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size);
2390 : : int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev,
2391 : : struct rte_eth_rss_reta_entry64 *reta_conf,
2392 : : uint16_t reta_size);
2393 : : int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev,
2394 : : struct rte_eth_rss_reta_entry64 *reta_conf,
2395 : : uint16_t reta_size);
2396 : :
2397 : : /* mlx5_rxmode.c */
2398 : :
2399 : : int mlx5_promiscuous_enable(struct rte_eth_dev *dev);
2400 : : int mlx5_promiscuous_disable(struct rte_eth_dev *dev);
2401 : : int mlx5_allmulticast_enable(struct rte_eth_dev *dev);
2402 : : int mlx5_allmulticast_disable(struct rte_eth_dev *dev);
2403 : :
2404 : : /* mlx5_stats.c */
2405 : :
2406 : : int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats,
2407 : : struct eth_queue_stats *qstats);
2408 : : int mlx5_stats_reset(struct rte_eth_dev *dev);
2409 : : int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
2410 : : unsigned int n);
2411 : : int mlx5_xstats_reset(struct rte_eth_dev *dev);
2412 : : int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
2413 : : struct rte_eth_xstat_name *xstats_names,
2414 : : unsigned int n);
2415 : : void mlx5_reset_xstats_by_name(struct mlx5_priv *priv, const char *ctr_name);
2416 : : void mlx5_reset_xstats_rq(struct rte_eth_dev *dev);
2417 : :
2418 : : /* mlx5_vlan.c */
2419 : :
2420 : : int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
2421 : : void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on);
2422 : : int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask);
2423 : :
2424 : : /* mlx5_vlan_os.c */
2425 : :
2426 : : void mlx5_vlan_vmwa_exit(void *ctx);
2427 : : void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev,
2428 : : struct mlx5_vf_vlan *vf_vlan);
2429 : : void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev,
2430 : : struct mlx5_vf_vlan *vf_vlan);
2431 : : void *mlx5_vlan_vmwa_init(struct rte_eth_dev *dev, uint32_t ifindex);
2432 : :
2433 : : /* mlx5_trigger.c */
2434 : :
2435 : : int mlx5_dev_start(struct rte_eth_dev *dev);
2436 : : int mlx5_dev_stop(struct rte_eth_dev *dev);
2437 : : int mlx5_traffic_enable(struct rte_eth_dev *dev);
2438 : : void mlx5_traffic_disable(struct rte_eth_dev *dev);
2439 : : int mlx5_traffic_restart(struct rte_eth_dev *dev);
2440 : : int mlx5_hairpin_queue_peer_update(struct rte_eth_dev *dev, uint16_t peer_queue,
2441 : : struct rte_hairpin_peer_info *current_info,
2442 : : struct rte_hairpin_peer_info *peer_info,
2443 : : uint32_t direction);
2444 : : int mlx5_hairpin_queue_peer_bind(struct rte_eth_dev *dev, uint16_t cur_queue,
2445 : : struct rte_hairpin_peer_info *peer_info,
2446 : : uint32_t direction);
2447 : : int mlx5_hairpin_queue_peer_unbind(struct rte_eth_dev *dev, uint16_t cur_queue,
2448 : : uint32_t direction);
2449 : : int mlx5_hairpin_bind(struct rte_eth_dev *dev, uint16_t rx_port);
2450 : : int mlx5_hairpin_unbind(struct rte_eth_dev *dev, uint16_t rx_port);
2451 : : int mlx5_hairpin_get_peer_ports(struct rte_eth_dev *dev, uint16_t *peer_ports,
2452 : : size_t len, uint32_t direction);
2453 : : int mlx5_traffic_mac_add(struct rte_eth_dev *dev, const struct rte_ether_addr *addr);
2454 : : int mlx5_traffic_mac_remove(struct rte_eth_dev *dev, const struct rte_ether_addr *addr);
2455 : : int mlx5_traffic_vlan_add(struct rte_eth_dev *dev, const uint16_t vid);
2456 : : int mlx5_traffic_vlan_remove(struct rte_eth_dev *dev, const uint16_t vid);
2457 : :
2458 : : /* mlx5_flow.c */
2459 : :
2460 : : int mlx5_flow_discover_mreg_c(struct rte_eth_dev *eth_dev);
2461 : : bool mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev);
2462 : : void mlx5_flow_print(struct rte_flow *flow);
2463 : : int mlx5_flow_validate(struct rte_eth_dev *dev,
2464 : : const struct rte_flow_attr *attr,
2465 : : const struct rte_flow_item items[],
2466 : : const struct rte_flow_action actions[],
2467 : : struct rte_flow_error *error);
2468 : : uintptr_t
2469 : : mlx5_flow_list_create(struct rte_eth_dev *dev, enum mlx5_flow_type type,
2470 : : const struct rte_flow_attr *attr,
2471 : : const struct rte_flow_item items[],
2472 : : const struct rte_flow_action actions[],
2473 : : bool external, struct rte_flow_error *error);
2474 : : void
2475 : : mlx5_flow_list_destroy(struct rte_eth_dev *dev, enum mlx5_flow_type type,
2476 : : uintptr_t flow_idx);
2477 : : struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev,
2478 : : const struct rte_flow_attr *attr,
2479 : : const struct rte_flow_item items[],
2480 : : const struct rte_flow_action actions[],
2481 : : struct rte_flow_error *error);
2482 : : int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
2483 : : struct rte_flow_error *error);
2484 : : void mlx5_flow_list_flush(struct rte_eth_dev *dev, enum mlx5_flow_type type,
2485 : : bool active);
2486 : : int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error);
2487 : : int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
2488 : : const struct rte_flow_action *action, void *data,
2489 : : struct rte_flow_error *error);
2490 : : int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable,
2491 : : struct rte_flow_error *error);
2492 : : int mlx5_flow_ops_get(struct rte_eth_dev *dev, const struct rte_flow_ops **ops);
2493 : : int mlx5_flow_start_default(struct rte_eth_dev *dev);
2494 : : void mlx5_flow_stop_default(struct rte_eth_dev *dev);
2495 : : int mlx5_flow_verify(struct rte_eth_dev *dev);
2496 : : int mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, uint32_t sq_num);
2497 : : int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,
2498 : : struct rte_flow_item_eth *eth_spec,
2499 : : struct rte_flow_item_eth *eth_mask,
2500 : : struct rte_flow_item_vlan *vlan_spec,
2501 : : struct rte_flow_item_vlan *vlan_mask);
2502 : : int mlx5_ctrl_flow(struct rte_eth_dev *dev,
2503 : : struct rte_flow_item_eth *eth_spec,
2504 : : struct rte_flow_item_eth *eth_mask);
2505 : : int mlx5_flow_lacp_miss(struct rte_eth_dev *dev);
2506 : : struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev);
2507 : : uint32_t mlx5_flow_create_devx_sq_miss_flow(struct rte_eth_dev *dev,
2508 : : uint32_t sq_num);
2509 : : void mlx5_flow_async_pool_query_handle(struct mlx5_dev_ctx_shared *sh,
2510 : : uint64_t async_id, int status);
2511 : : void mlx5_set_query_alarm(struct mlx5_dev_ctx_shared *sh);
2512 : : void mlx5_flow_query_alarm(void *arg);
2513 : : uint32_t mlx5_counter_alloc(struct rte_eth_dev *dev);
2514 : : void mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt);
2515 : : int mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt,
2516 : : bool clear, uint64_t *pkts, uint64_t *bytes, void **action);
2517 : : int mlx5_flow_dev_dump(struct rte_eth_dev *dev, struct rte_flow *flow,
2518 : : FILE *file, struct rte_flow_error *error);
2519 : : int mlx5_save_dump_file(const unsigned char *data, uint32_t size,
2520 : : uint32_t type, uint64_t id, void *arg, FILE *file);
2521 : : int mlx5_flow_query_counter(struct rte_eth_dev *dev, struct rte_flow *flow,
2522 : : struct rte_flow_query_count *count, struct rte_flow_error *error);
2523 : : #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2524 : : int mlx5_flow_dev_dump_ipool(struct rte_eth_dev *dev, struct rte_flow *flow,
2525 : : FILE *file, struct rte_flow_error *error);
2526 : : #endif
2527 : : int mlx5_flow_rx_metadata_negotiate(struct rte_eth_dev *dev,
2528 : : uint64_t *features);
2529 : : void mlx5_flow_rxq_dynf_set(struct rte_eth_dev *dev);
2530 : : int mlx5_flow_get_aged_flows(struct rte_eth_dev *dev, void **contexts,
2531 : : uint32_t nb_contexts, struct rte_flow_error *error);
2532 : : int mlx5_validate_action_ct(struct rte_eth_dev *dev,
2533 : : const struct rte_flow_action_conntrack *conntrack,
2534 : : struct rte_flow_error *error);
2535 : :
2536 : : int mlx5_flow_get_q_aged_flows(struct rte_eth_dev *dev, uint32_t queue_id,
2537 : : void **contexts, uint32_t nb_contexts,
2538 : : struct rte_flow_error *error);
2539 : :
2540 : : /* mlx5_mp_os.c */
2541 : :
2542 : : int mlx5_mp_os_primary_handle(const struct rte_mp_msg *mp_msg,
2543 : : const void *peer);
2544 : : int mlx5_mp_os_secondary_handle(const struct rte_mp_msg *mp_msg,
2545 : : const void *peer);
2546 : : void mlx5_mp_os_req_start_rxtx(struct rte_eth_dev *dev);
2547 : : void mlx5_mp_os_req_stop_rxtx(struct rte_eth_dev *dev);
2548 : : int mlx5_mp_os_req_queue_control(struct rte_eth_dev *dev, uint16_t queue_id,
2549 : : enum mlx5_mp_req_type req_type);
2550 : :
2551 : : /* mlx5_socket.c */
2552 : :
2553 : : int mlx5_pmd_socket_init(void);
2554 : : void mlx5_pmd_socket_uninit(void);
2555 : :
2556 : : /* mlx5_flow_meter.c */
2557 : :
2558 : : int mlx5_flow_meter_init(struct rte_eth_dev *dev,
2559 : : uint32_t nb_meters,
2560 : : uint32_t nb_meter_profiles,
2561 : : uint32_t nb_meter_policies,
2562 : : uint32_t nb_queues);
2563 : : void mlx5_flow_meter_uninit(struct rte_eth_dev *dev);
2564 : : int mlx5_flow_meter_ops_get(struct rte_eth_dev *dev, void *arg);
2565 : : struct mlx5_flow_meter_info *mlx5_flow_meter_find(struct mlx5_priv *priv,
2566 : : uint32_t meter_id, uint32_t *mtr_idx);
2567 : : struct mlx5_flow_meter_info *
2568 : : mlx5_flow_dv_meter_find_by_idx(struct mlx5_priv *priv, uint32_t idx);
2569 : : int mlx5_flow_meter_attach(struct mlx5_priv *priv,
2570 : : struct mlx5_flow_meter_info *fm,
2571 : : const struct rte_flow_attr *attr,
2572 : : struct rte_flow_error *error);
2573 : : void mlx5_flow_meter_detach(struct mlx5_priv *priv,
2574 : : struct mlx5_flow_meter_info *fm);
2575 : : struct mlx5_flow_meter_policy *mlx5_flow_meter_policy_find
2576 : : (struct rte_eth_dev *dev,
2577 : : uint32_t policy_id,
2578 : : uint32_t *policy_idx);
2579 : : struct mlx5_flow_meter_info *
2580 : : mlx5_flow_meter_hierarchy_next_meter(struct mlx5_priv *priv,
2581 : : struct mlx5_flow_meter_policy *policy,
2582 : : uint32_t *mtr_idx);
2583 : : struct mlx5_flow_meter_policy *
2584 : : mlx5_flow_meter_hierarchy_get_final_policy(struct rte_eth_dev *dev,
2585 : : struct mlx5_flow_meter_policy *policy);
2586 : : int mlx5_flow_meter_flush(struct rte_eth_dev *dev,
2587 : : struct rte_mtr_error *error);
2588 : : void mlx5_flow_meter_rxq_flush(struct rte_eth_dev *dev);
2589 : : uint32_t mlx5_flow_mtr_max_get(struct mlx5_priv *priv);
2590 : :
2591 : : /* mlx5_os.c */
2592 : :
2593 : : struct rte_pci_driver;
2594 : : int mlx5_os_capabilities_prepare(struct mlx5_dev_ctx_shared *sh);
2595 : : void mlx5_os_free_shared_dr(struct mlx5_priv *priv);
2596 : : int mlx5_os_net_probe(struct mlx5_common_device *cdev,
2597 : : struct mlx5_kvargs_ctrl *mkvlist);
2598 : : void mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh);
2599 : : void mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh);
2600 : : void mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
2601 : : int mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
2602 : : uint32_t index);
2603 : : int mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, unsigned int iface_idx,
2604 : : struct rte_ether_addr *mac_addr,
2605 : : int vf_index);
2606 : : int mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable);
2607 : : int mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable);
2608 : : int mlx5_os_set_nonblock_channel_fd(int fd);
2609 : : void mlx5_os_mac_addr_flush(struct rte_eth_dev *dev);
2610 : : void mlx5_os_net_cleanup(void);
2611 : : void mlx5_os_default_flow_config(struct mlx5_sh_config *config, struct mlx5_dev_ctx_shared *sh);
2612 : : void mlx5_os_fixup_flow_en(struct mlx5_sh_config *config,
2613 : : struct mlx5_dev_ctx_shared *sh);
2614 : : void mlx5_os_fixup_duplicate_pattern(struct mlx5_sh_config *config,
2615 : : struct mlx5_kvargs_ctrl *mkvlist,
2616 : : const char *key);
2617 : :
2618 : : /* mlx5_txpp.c */
2619 : :
2620 : : int mlx5_txpp_start(struct rte_eth_dev *dev);
2621 : : void mlx5_txpp_stop(struct rte_eth_dev *dev);
2622 : : int mlx5_txpp_read_clock(struct rte_eth_dev *dev, uint64_t *timestamp);
2623 : : int mlx5_txpp_xstats_get(struct rte_eth_dev *dev,
2624 : : struct rte_eth_xstat *stats,
2625 : : unsigned int n, unsigned int n_used);
2626 : : int mlx5_txpp_xstats_reset(struct rte_eth_dev *dev);
2627 : : int mlx5_txpp_xstats_get_names(struct rte_eth_dev *dev,
2628 : : struct rte_eth_xstat_name *xstats_names,
2629 : : unsigned int n, unsigned int n_used);
2630 : : void mlx5_txpp_interrupt_handler(void *cb_arg);
2631 : : int mlx5_txpp_map_hca_bar(struct rte_eth_dev *dev);
2632 : : void mlx5_txpp_unmap_hca_bar(struct rte_eth_dev *dev);
2633 : :
2634 : : /* mlx5_rxtx.c */
2635 : :
2636 : : eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev);
2637 : :
2638 : : /* mlx5_flow_aso.c */
2639 : :
2640 : : int mlx5_aso_mtr_queue_init(struct mlx5_dev_ctx_shared *sh,
2641 : : struct mlx5_aso_mtr_pool *hws_pool,
2642 : : struct mlx5_aso_mtr_pools_mng *pool_mng,
2643 : : uint32_t nb_queues);
2644 : : void mlx5_aso_mtr_queue_uninit(struct mlx5_dev_ctx_shared *sh,
2645 : : struct mlx5_aso_mtr_pool *hws_pool,
2646 : : struct mlx5_aso_mtr_pools_mng *pool_mng);
2647 : : int mlx5_aso_queue_init(struct mlx5_dev_ctx_shared *sh,
2648 : : enum mlx5_access_aso_opc_mod aso_opc_mode,
2649 : : uint32_t nb_queues);
2650 : : int mlx5_aso_flow_hit_queue_poll_start(struct mlx5_dev_ctx_shared *sh);
2651 : : int mlx5_aso_flow_hit_queue_poll_stop(struct mlx5_dev_ctx_shared *sh);
2652 : : void mlx5_aso_queue_uninit(struct mlx5_dev_ctx_shared *sh,
2653 : : enum mlx5_access_aso_opc_mod aso_opc_mod);
2654 : : int mlx5_aso_meter_update_by_wqe(struct mlx5_priv *priv, uint32_t queue,
2655 : : struct mlx5_aso_mtr *mtr,
2656 : : struct mlx5_mtr_bulk *bulk,
2657 : : struct mlx5_hw_q_job *job, bool push);
2658 : : int mlx5_aso_mtr_wait(struct mlx5_priv *priv,
2659 : : struct mlx5_aso_mtr *mtr, bool is_tmpl_api);
2660 : : int mlx5_aso_ct_update_by_wqe(struct mlx5_dev_ctx_shared *sh, uint32_t queue,
2661 : : struct mlx5_aso_ct_action *ct,
2662 : : const struct rte_flow_action_conntrack *profile,
2663 : : void *user_data,
2664 : : bool push);
2665 : : int mlx5_aso_ct_wait_ready(struct mlx5_dev_ctx_shared *sh, uint32_t queue,
2666 : : struct mlx5_aso_ct_action *ct);
2667 : : int mlx5_aso_ct_query_by_wqe(struct mlx5_dev_ctx_shared *sh, uint32_t queue,
2668 : : struct mlx5_aso_ct_action *ct,
2669 : : struct rte_flow_action_conntrack *profile,
2670 : : void *user_data, bool push);
2671 : : int mlx5_aso_ct_available(struct mlx5_dev_ctx_shared *sh, uint32_t queue,
2672 : : struct mlx5_aso_ct_action *ct);
2673 : : uint32_t
2674 : : mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr);
2675 : : uint32_t
2676 : : mlx5_get_supported_tunneling_offloads(const struct mlx5_hca_attr *attr);
2677 : :
2678 : : void mlx5_aso_ct_obj_analyze(struct rte_flow_action_conntrack *profile,
2679 : : char *wdata);
2680 : : void mlx5_aso_push_wqe(struct mlx5_dev_ctx_shared *sh,
2681 : : struct mlx5_aso_sq *sq);
2682 : : int mlx5_aso_pull_completion(struct mlx5_aso_sq *sq,
2683 : : struct rte_flow_op_result res[],
2684 : : uint16_t n_res);
2685 : : int mlx5_aso_cnt_queue_init(struct mlx5_dev_ctx_shared *sh);
2686 : : void mlx5_aso_cnt_queue_uninit(struct mlx5_dev_ctx_shared *sh);
2687 : : int mlx5_aso_cnt_query(struct mlx5_dev_ctx_shared *sh,
2688 : : struct mlx5_hws_cnt_pool *cpool);
2689 : : int mlx5_aso_ct_queue_init(struct mlx5_dev_ctx_shared *sh,
2690 : : struct mlx5_aso_ct_pools_mng *ct_mng,
2691 : : uint32_t nb_queues);
2692 : : int mlx5_aso_ct_queue_uninit(struct mlx5_dev_ctx_shared *sh,
2693 : : struct mlx5_aso_ct_pools_mng *ct_mng);
2694 : : int
2695 : : mlx5_aso_sq_create(struct mlx5_common_device *cdev, struct mlx5_aso_sq *sq,
2696 : : void *uar, uint16_t log_desc_n);
2697 : : void
2698 : : mlx5_aso_destroy_sq(struct mlx5_aso_sq *sq);
2699 : : void
2700 : : mlx5_aso_mtr_init_sq(struct mlx5_aso_sq *sq);
2701 : : void
2702 : : mlx5_aso_cqe_err_handle(struct mlx5_aso_sq *sq);
2703 : :
2704 : : /* mlx5_flow_flex.c */
2705 : :
2706 : : struct rte_flow_item_flex_handle *
2707 : : mlx5_flow_dv_item_create(struct rte_eth_dev *dev,
2708 : : const struct rte_flow_item_flex_conf *conf,
2709 : : struct rte_flow_error *error);
2710 : : int mlx5_flow_dv_item_release(struct rte_eth_dev *dev,
2711 : : const struct rte_flow_item_flex_handle *flex_handle,
2712 : : struct rte_flow_error *error);
2713 : : int mlx5_flex_item_port_init(struct rte_eth_dev *dev);
2714 : : void mlx5_flex_item_port_cleanup(struct rte_eth_dev *dev);
2715 : : void mlx5_flex_flow_translate_item(struct rte_eth_dev *dev, void *matcher,
2716 : : void *key, const struct rte_flow_item *item,
2717 : : bool is_inner);
2718 : : int mlx5_flex_get_sample_id(const struct mlx5_flex_item *tp,
2719 : : uint32_t idx, uint32_t *pos, bool is_inner);
2720 : : int mlx5_flex_get_parser_value_per_byte_off(const struct rte_flow_item_flex *item,
2721 : : void *flex, uint32_t byte_off,
2722 : : bool tunnel, uint32_t *value);
2723 : : int mlx5_flex_get_tunnel_mode(const struct rte_flow_item *item,
2724 : : enum rte_flow_item_flex_tunnel_mode *tunnel_mode);
2725 : : int mlx5_flex_acquire_index(struct rte_eth_dev *dev,
2726 : : struct rte_flow_item_flex_handle *handle,
2727 : : bool acquire);
2728 : : int mlx5_flex_release_index(struct rte_eth_dev *dev, int index);
2729 : : void mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev);
2730 : :
2731 : : /* Flex parser list callbacks. */
2732 : : struct mlx5_list_entry *mlx5_flex_parser_create_cb(void *list_ctx, void *ctx);
2733 : : int mlx5_flex_parser_match_cb(void *list_ctx,
2734 : : struct mlx5_list_entry *iter, void *ctx);
2735 : : void mlx5_flex_parser_remove_cb(void *list_ctx, struct mlx5_list_entry *entry);
2736 : : struct mlx5_list_entry *mlx5_flex_parser_clone_cb(void *list_ctx,
2737 : : struct mlx5_list_entry *entry,
2738 : : void *ctx);
2739 : : void mlx5_flex_parser_clone_free_cb(void *tool_ctx,
2740 : : struct mlx5_list_entry *entry);
2741 : :
2742 : : int
2743 : : mlx5_flow_quota_destroy(struct rte_eth_dev *dev);
2744 : : int
2745 : : mlx5_flow_quota_init(struct rte_eth_dev *dev, uint32_t nb_quotas);
2746 : : struct rte_flow_action_handle *
2747 : : mlx5_quota_alloc(struct rte_eth_dev *dev, uint32_t queue,
2748 : : const struct rte_flow_action_quota *conf,
2749 : : struct mlx5_hw_q_job *job, bool push,
2750 : : struct rte_flow_error *error);
2751 : : void
2752 : : mlx5_quota_async_completion(struct rte_eth_dev *dev, uint32_t queue,
2753 : : struct mlx5_hw_q_job *job);
2754 : : int
2755 : : mlx5_quota_query_update(struct rte_eth_dev *dev, uint32_t queue,
2756 : : struct rte_flow_action_handle *handle,
2757 : : const struct rte_flow_action *update,
2758 : : struct rte_flow_query_quota *query,
2759 : : struct mlx5_hw_q_job *async_job, bool push,
2760 : : struct rte_flow_error *error);
2761 : : int mlx5_quota_query(struct rte_eth_dev *dev, uint32_t queue,
2762 : : const struct rte_flow_action_handle *handle,
2763 : : struct rte_flow_query_quota *query,
2764 : : struct mlx5_hw_q_job *async_job, bool push,
2765 : : struct rte_flow_error *error);
2766 : :
2767 : : int mlx5_alloc_srh_flex_parser(struct rte_eth_dev *dev);
2768 : :
2769 : : void mlx5_free_srh_flex_parser(struct rte_eth_dev *dev);
2770 : :
2771 : : /* mlx5_flow_hw.c */
2772 : : struct rte_pmd_mlx5_host_action;
2773 : :
2774 : : struct mlx5dr_action *
2775 : : mlx5_flow_hw_get_dr_action(struct rte_eth_dev *dev,
2776 : : struct rte_pmd_mlx5_host_action *action,
2777 : : void **release_data);
2778 : :
2779 : : void
2780 : : mlx5_flow_hw_put_dr_action(struct rte_eth_dev *dev,
2781 : : enum rte_flow_action_type type,
2782 : : void *release_data);
2783 : :
2784 : : bool
2785 : : mlx5_hw_ctx_validate(const struct rte_eth_dev *dev,
2786 : : struct rte_flow_error *error);
2787 : :
2788 : : #endif /* RTE_PMD_MLX5_H_ */
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