Branch data Line data Source code
1 : : /* SPDX-License-Identifier: BSD-3-Clause
2 : : * Copyright 2018 Mellanox Technologies, Ltd
3 : : */
4 : :
5 : : #include <unistd.h>
6 : :
7 : : #include <eal_export.h>
8 : : #include <rte_errno.h>
9 : : #include <rte_malloc.h>
10 : : #include <rte_eal_paging.h>
11 : :
12 : : #include "mlx5_prm.h"
13 : : #include "mlx5_devx_cmds.h"
14 : : #include "mlx5_common_log.h"
15 : : #include "mlx5_malloc.h"
16 : :
17 : : /* FW writes status value to the OUT buffer at offset 00H */
18 : : #define MLX5_FW_STATUS(o) MLX5_GET(general_obj_out_cmd_hdr, (o), status)
19 : : /* FW writes syndrome value to the OUT buffer at offset 04H */
20 : : #define MLX5_FW_SYNDROME(o) MLX5_GET(general_obj_out_cmd_hdr, (o), syndrome)
21 : :
22 : : #define MLX5_DEVX_ERR_RC(x) ((x) > 0 ? -(x) : ((x) < 0 ? (x) : -1))
23 : :
24 : : #define DEVX_DRV_LOG(level, out, reason, param, value) \
25 : : do { \
26 : : /* \
27 : : * Some (old) GCC compilers like 7.5.0 and aarch64 GCC 7.1-2017.08 \
28 : : * do not expand correctly when the macro invoked when the `param` \
29 : : * is `NULL`. \
30 : : * Use `local_param` to avoid direct `NULL` expansion. \
31 : : */ \
32 : : const char *local_param = (const char *)param; \
33 : : \
34 : : rte_errno = errno; \
35 : : if (!local_param) { \
36 : : DRV_LOG(level, \
37 : : "DevX %s failed errno=%d status=%#x syndrome=%#x", \
38 : : (reason), errno, MLX5_FW_STATUS((out)), \
39 : : MLX5_FW_SYNDROME((out))); \
40 : : } else { \
41 : : DRV_LOG(level, \
42 : : "DevX %s %s=%#X failed errno=%d status=%#x syndrome=%#x",\
43 : : (reason), local_param, (value), errno, \
44 : : MLX5_FW_STATUS((out)), MLX5_FW_SYNDROME((out))); \
45 : : } \
46 : : } while (0)
47 : :
48 : : static void *
49 [ # # ]: 0 : mlx5_devx_get_hca_cap(void *ctx, uint32_t *in, uint32_t *out,
50 : : int *err, uint32_t flags)
51 : : {
52 : : const size_t size_in = MLX5_ST_SZ_DW(query_hca_cap_in) * sizeof(int);
53 : : const size_t size_out = MLX5_ST_SZ_DW(query_hca_cap_out) * sizeof(int);
54 : : int rc;
55 : :
56 : : memset(in, 0, size_in);
57 : : memset(out, 0, size_out);
58 [ # # ]: 0 : MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
59 [ # # ]: 0 : MLX5_SET(query_hca_cap_in, in, op_mod, flags);
60 : 0 : rc = mlx5_glue->devx_general_cmd(ctx, in, size_in, out, size_out);
61 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
62 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "HCA capabilities", "func", flags >> 1);
63 [ # # ]: 0 : if (err)
64 [ # # ]: 0 : *err = MLX5_DEVX_ERR_RC(rc);
65 : 0 : return NULL;
66 : : }
67 [ # # ]: 0 : if (err)
68 : 0 : *err = 0;
69 : 0 : return MLX5_ADDR_OF(query_hca_cap_out, out, capability);
70 : : }
71 : :
72 : : /**
73 : : * Perform read access to the registers. Reads data from register
74 : : * and writes ones to the specified buffer.
75 : : *
76 : : * @param[in] ctx
77 : : * Context returned from mlx5 open_device() glue function.
78 : : * @param[in] reg_id
79 : : * Register identifier according to the PRM.
80 : : * @param[in] arg
81 : : * Register access auxiliary parameter according to the PRM.
82 : : * @param[out] data
83 : : * Pointer to the buffer to store read data.
84 : : * @param[in] dw_cnt
85 : : * Buffer size in double words.
86 : : *
87 : : * @return
88 : : * 0 on success, a negative value otherwise.
89 : : */
90 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_register_read)
91 : : int
92 : 0 : mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg,
93 : : uint32_t *data, uint32_t dw_cnt)
94 : : {
95 : 0 : uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0};
96 : 0 : uint32_t out[MLX5_ST_SZ_DW(access_register_out) +
97 : : MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0};
98 : : int rc;
99 : :
100 : : MLX5_ASSERT(data && dw_cnt);
101 : : MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX);
102 [ # # ]: 0 : if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) {
103 : 0 : DRV_LOG(ERR, "Not enough buffer for register read data");
104 : 0 : return -1;
105 : : }
106 : 0 : MLX5_SET(access_register_in, in, opcode,
107 : : MLX5_CMD_OP_ACCESS_REGISTER_USER);
108 : 0 : MLX5_SET(access_register_in, in, op_mod,
109 : : MLX5_ACCESS_REGISTER_IN_OP_MOD_READ);
110 : 0 : MLX5_SET(access_register_in, in, register_id, reg_id);
111 : 0 : MLX5_SET(access_register_in, in, argument, arg);
112 : 0 : rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,
113 : 0 : MLX5_ST_SZ_BYTES(access_register_out) +
114 : : sizeof(uint32_t) * dw_cnt);
115 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
116 [ # # # # ]: 0 : DEVX_DRV_LOG(DEBUG, out, "read access", "NIC register", reg_id);
117 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
118 : : }
119 : 0 : memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)],
120 : : dw_cnt * sizeof(uint32_t));
121 : 0 : return 0;
122 : : }
123 : :
124 : : /**
125 : : * Perform write access to the registers.
126 : : *
127 : : * @param[in] ctx
128 : : * Context returned from mlx5 open_device() glue function.
129 : : * @param[in] reg_id
130 : : * Register identifier according to the PRM.
131 : : * @param[in] arg
132 : : * Register access auxiliary parameter according to the PRM.
133 : : * @param[out] data
134 : : * Pointer to the buffer containing data to write.
135 : : * @param[in] dw_cnt
136 : : * Buffer size in double words (32bit units).
137 : : *
138 : : * @return
139 : : * 0 on success, a negative value otherwise.
140 : : */
141 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_register_write)
142 : : int
143 : 0 : mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, uint32_t arg,
144 : : uint32_t *data, uint32_t dw_cnt)
145 : : {
146 : 0 : uint32_t in[MLX5_ST_SZ_DW(access_register_in) +
147 : : MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0};
148 : 0 : uint32_t out[MLX5_ST_SZ_DW(access_register_out)] = {0};
149 : : int rc;
150 : : void *ptr;
151 : :
152 : : MLX5_ASSERT(data && dw_cnt);
153 : : MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX);
154 [ # # ]: 0 : if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) {
155 : 0 : DRV_LOG(ERR, "Data to write exceeds max size");
156 : 0 : return -1;
157 : : }
158 : 0 : MLX5_SET(access_register_in, in, opcode,
159 : : MLX5_CMD_OP_ACCESS_REGISTER_USER);
160 : 0 : MLX5_SET(access_register_in, in, op_mod,
161 : : MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE);
162 : 0 : MLX5_SET(access_register_in, in, register_id, reg_id);
163 : 0 : MLX5_SET(access_register_in, in, argument, arg);
164 : : ptr = MLX5_ADDR_OF(access_register_in, in, register_data);
165 : 0 : memcpy(ptr, data, dw_cnt * sizeof(uint32_t));
166 : 0 : rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
167 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
168 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "write access", "NIC register", reg_id);
169 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
170 : : }
171 : 0 : rc = mlx5_glue->devx_general_cmd(ctx, in,
172 : 0 : MLX5_ST_SZ_BYTES(access_register_in) +
173 : : dw_cnt * sizeof(uint32_t),
174 : : out, sizeof(out));
175 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
176 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "write access", "NIC register", reg_id);
177 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
178 : : }
179 : : return 0;
180 : : }
181 : :
182 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_flow_counter_alloc_general)
183 : : struct mlx5_devx_obj *
184 : 0 : mlx5_devx_cmd_flow_counter_alloc_general(void *ctx,
185 : : struct mlx5_devx_counter_attr *attr)
186 : : {
187 : 0 : struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs),
188 : : 0, SOCKET_ID_ANY);
189 : 0 : uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0};
190 : 0 : uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0};
191 : :
192 [ # # ]: 0 : if (!dcs) {
193 : 0 : rte_errno = ENOMEM;
194 : 0 : return NULL;
195 : : }
196 : 0 : MLX5_SET(alloc_flow_counter_in, in, opcode,
197 : : MLX5_CMD_OP_ALLOC_FLOW_COUNTER);
198 [ # # ]: 0 : if (attr->bulk_log_max_alloc)
199 : 0 : MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk_log_size,
200 : : attr->flow_counter_bulk_log_size);
201 : : else
202 : 0 : MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk,
203 : : attr->bulk_n_128);
204 [ # # ]: 0 : if (attr->pd_valid)
205 : 0 : MLX5_SET(alloc_flow_counter_in, in, pd, attr->pd);
206 : 0 : dcs->obj = mlx5_glue->devx_obj_create(ctx, in,
207 : : sizeof(in), out, sizeof(out));
208 [ # # ]: 0 : if (!dcs->obj) {
209 : 0 : DRV_LOG(ERR, "Can't allocate counters - error %d", errno);
210 : 0 : rte_errno = errno;
211 : 0 : mlx5_free(dcs);
212 : 0 : return NULL;
213 : : }
214 [ # # ]: 0 : dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id);
215 : 0 : return dcs;
216 : : }
217 : :
218 : : /**
219 : : * Allocate flow counters via devx interface.
220 : : *
221 : : * @param[in] ctx
222 : : * Context returned from mlx5 open_device() glue function.
223 : : * @param dcs
224 : : * Pointer to counters properties structure to be filled by the routine.
225 : : * @param bulk_n_128
226 : : * Bulk counter numbers in 128 counters units.
227 : : *
228 : : * @return
229 : : * Pointer to counter object on success, a negative value otherwise and
230 : : * rte_errno is set.
231 : : */
232 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_flow_counter_alloc)
233 : : struct mlx5_devx_obj *
234 : 0 : mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128)
235 : : {
236 : 0 : struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs),
237 : : 0, SOCKET_ID_ANY);
238 : 0 : uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0};
239 : 0 : uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0};
240 : :
241 [ # # ]: 0 : if (!dcs) {
242 : 0 : rte_errno = ENOMEM;
243 : 0 : return NULL;
244 : : }
245 : 0 : MLX5_SET(alloc_flow_counter_in, in, opcode,
246 : : MLX5_CMD_OP_ALLOC_FLOW_COUNTER);
247 : 0 : MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128);
248 : 0 : dcs->obj = mlx5_glue->devx_obj_create(ctx, in,
249 : : sizeof(in), out, sizeof(out));
250 [ # # ]: 0 : if (!dcs->obj) {
251 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "allocate counters", NULL, 0);
252 : 0 : mlx5_free(dcs);
253 : 0 : return NULL;
254 : : }
255 [ # # ]: 0 : dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id);
256 : 0 : return dcs;
257 : : }
258 : :
259 : : /**
260 : : * Query flow counters values.
261 : : *
262 : : * @param[in] dcs
263 : : * devx object that was obtained from mlx5_devx_cmd_fc_alloc.
264 : : * @param[in] clear
265 : : * Whether hardware should clear the counters after the query or not.
266 : : * @param[in] n_counters
267 : : * 0 in case of 1 counter to read, otherwise the counter number to read.
268 : : * @param pkts
269 : : * The number of packets that matched the flow.
270 : : * @param bytes
271 : : * The number of bytes that matched the flow.
272 : : * @param mkey
273 : : * The mkey key for batch query.
274 : : * @param addr
275 : : * The address in the mkey range for batch query.
276 : : * @param cmd_comp
277 : : * The completion object for asynchronous batch query.
278 : : * @param async_id
279 : : * The ID to be returned in the asynchronous batch query response.
280 : : *
281 : : * @return
282 : : * 0 on success, a negative value otherwise.
283 : : */
284 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_flow_counter_query)
285 : : int
286 : 0 : mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
287 : : int clear, uint32_t n_counters,
288 : : uint64_t *pkts, uint64_t *bytes,
289 : : uint32_t mkey, void *addr,
290 : : void *cmd_comp,
291 : : uint64_t async_id)
292 : : {
293 : : uint32_t out[MLX5_ST_SZ_BYTES(query_flow_counter_out) + MLX5_ST_SZ_BYTES(traffic_counter)];
294 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0};
295 : : const int out_len = RTE_DIM(out);
296 : : void *stats;
297 : : int rc;
298 : :
299 : 0 : MLX5_SET(query_flow_counter_in, in, opcode,
300 : : MLX5_CMD_OP_QUERY_FLOW_COUNTER);
301 : 0 : MLX5_SET(query_flow_counter_in, in, op_mod, 0);
302 : 0 : MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id);
303 : 0 : MLX5_SET(query_flow_counter_in, in, clear, !!clear);
304 : :
305 [ # # ]: 0 : if (n_counters) {
306 [ # # ]: 0 : MLX5_SET(query_flow_counter_in, in, num_of_counters,
307 : : n_counters);
308 [ # # ]: 0 : MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1);
309 : 0 : MLX5_SET(query_flow_counter_in, in, mkey, mkey);
310 : 0 : MLX5_SET64(query_flow_counter_in, in, address,
311 : : (uint64_t)(uintptr_t)addr);
312 : : }
313 [ # # ]: 0 : if (!cmd_comp)
314 : 0 : rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
315 : : out_len);
316 : : else
317 : 0 : rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in),
318 : : out_len, async_id,
319 : : cmd_comp);
320 [ # # ]: 0 : if (rc) {
321 : 0 : DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc);
322 : 0 : rte_errno = rc;
323 : 0 : return -rc;
324 : : }
325 [ # # ]: 0 : if (!n_counters) {
326 : : stats = MLX5_ADDR_OF(query_flow_counter_out,
327 : : out, flow_statistics);
328 [ # # ]: 0 : *pkts = MLX5_GET64(traffic_counter, stats, packets);
329 [ # # ]: 0 : *bytes = MLX5_GET64(traffic_counter, stats, octets);
330 : : }
331 : : return 0;
332 : : }
333 : :
334 : : /**
335 : : * Create a new mkey.
336 : : *
337 : : * @param[in] ctx
338 : : * Context returned from mlx5 open_device() glue function.
339 : : * @param[in] attr
340 : : * Attributes of the requested mkey.
341 : : *
342 : : * @return
343 : : * Pointer to Devx mkey on success, a negative value otherwise and rte_errno
344 : : * is set.
345 : : */
346 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_mkey_create)
347 : : struct mlx5_devx_obj *
348 : 0 : mlx5_devx_cmd_mkey_create(void *ctx,
349 : : struct mlx5_devx_mkey_attr *attr)
350 : : {
351 : 0 : struct mlx5_klm *klm_array = attr->klm_array;
352 : 0 : int klm_num = attr->klm_num;
353 [ # # ]: 0 : int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) +
354 : 0 : (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm);
355 : 0 : uint32_t *in = alloca(sizeof(uint32_t) * in_size_dw);
356 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0};
357 : : void *mkc;
358 : 0 : struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey),
359 : : 0, SOCKET_ID_ANY);
360 : : size_t pgsize;
361 : : uint32_t translation_size;
362 : :
363 [ # # ]: 0 : if (!mkey) {
364 : 0 : rte_errno = ENOMEM;
365 : 0 : return NULL;
366 : : }
367 : : memset(in, 0, in_size_dw * 4);
368 : 0 : pgsize = rte_mem_page_size();
369 [ # # ]: 0 : if (pgsize == (size_t)-1) {
370 : 0 : mlx5_free(mkey);
371 : 0 : DRV_LOG(ERR, "Failed to get page size");
372 : 0 : rte_errno = ENOMEM;
373 : 0 : return NULL;
374 : : }
375 [ # # ]: 0 : MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY);
376 : : mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
377 [ # # ]: 0 : if (klm_num > 0) {
378 : : int i;
379 : 0 : uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in,
380 : : klm_pas_mtt);
381 : 0 : translation_size = RTE_ALIGN(klm_num, 4);
382 [ # # ]: 0 : for (i = 0; i < klm_num; i++) {
383 [ # # ]: 0 : MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count);
384 [ # # ]: 0 : MLX5_SET(klm, klm, mkey, klm_array[i].mkey);
385 [ # # ]: 0 : MLX5_SET64(klm, klm, address, klm_array[i].address);
386 : 0 : klm += MLX5_ST_SZ_BYTES(klm);
387 : : }
388 [ # # ]: 0 : for (; i < (int)translation_size; i++) {
389 [ # # ]: 0 : MLX5_SET(klm, klm, mkey, 0x0);
390 : 0 : MLX5_SET64(klm, klm, address, 0x0);
391 : 0 : klm += MLX5_ST_SZ_BYTES(klm);
392 : : }
393 [ # # # # ]: 0 : MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ?
394 : : MLX5_MKC_ACCESS_MODE_KLM_FBS :
395 : : MLX5_MKC_ACCESS_MODE_KLM);
396 [ # # ]: 0 : MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size);
397 : : } else {
398 : 0 : translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16;
399 [ # # ]: 0 : MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
400 [ # # # # ]: 0 : MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize));
401 : : }
402 [ # # ]: 0 : MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
403 : : translation_size);
404 [ # # ]: 0 : MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id);
405 [ # # ]: 0 : MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access);
406 [ # # ]: 0 : MLX5_SET(mkc, mkc, lw, 0x1);
407 [ # # ]: 0 : MLX5_SET(mkc, mkc, lr, 0x1);
408 [ # # ]: 0 : if (attr->set_remote_rw) {
409 [ # # ]: 0 : MLX5_SET(mkc, mkc, rw, 0x1);
410 [ # # ]: 0 : MLX5_SET(mkc, mkc, rr, 0x1);
411 : : }
412 [ # # ]: 0 : MLX5_SET(mkc, mkc, qpn, 0xffffff);
413 [ # # ]: 0 : MLX5_SET(mkc, mkc, pd, attr->pd);
414 [ # # ]: 0 : MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF);
415 [ # # ]: 0 : MLX5_SET(mkc, mkc, umr_en, attr->umr_en);
416 [ # # ]: 0 : MLX5_SET(mkc, mkc, translations_octword_size, translation_size);
417 [ # # ]: 0 : MLX5_SET(mkc, mkc, relaxed_ordering_write,
418 : : attr->relaxed_ordering_write);
419 [ # # ]: 0 : MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read);
420 [ # # ]: 0 : MLX5_SET64(mkc, mkc, start_addr, attr->addr);
421 [ # # ]: 0 : MLX5_SET64(mkc, mkc, len, attr->size);
422 [ # # ]: 0 : MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en);
423 [ # # ]: 0 : if (attr->crypto_en) {
424 [ # # ]: 0 : MLX5_SET(mkc, mkc, bsf_en, attr->crypto_en);
425 [ # # ]: 0 : MLX5_SET(mkc, mkc, bsf_octword_size, 4);
426 : : }
427 : 0 : mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out,
428 : : sizeof(out));
429 [ # # ]: 0 : if (!mkey->obj) {
430 [ # # # # : 0 : DEVX_DRV_LOG(ERR, out, klm_num ? "create indirect mkey"
# # ]
431 : : : "create direct key", NULL, 0);
432 : 0 : mlx5_free(mkey);
433 : 0 : return NULL;
434 : : }
435 [ # # ]: 0 : mkey->id = MLX5_GET(create_mkey_out, out, mkey_index);
436 : 0 : mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF);
437 : 0 : return mkey;
438 : : }
439 : :
440 : : /**
441 : : * Get status of devx command response.
442 : : * Mainly used for asynchronous commands.
443 : : *
444 : : * @param[in] out
445 : : * The out response buffer.
446 : : *
447 : : * @return
448 : : * 0 on success, non-zero value otherwise.
449 : : */
450 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_get_out_command_status)
451 : : int
452 : 0 : mlx5_devx_get_out_command_status(void *out)
453 : : {
454 : : int status;
455 : :
456 [ # # ]: 0 : if (!out)
457 : : return -EINVAL;
458 [ # # ]: 0 : status = MLX5_GET(query_flow_counter_out, out, status);
459 [ # # ]: 0 : if (status) {
460 [ # # ]: 0 : int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome);
461 : :
462 : 0 : DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status,
463 : : syndrome);
464 : : }
465 : : return status;
466 : : }
467 : :
468 : : /**
469 : : * Destroy any object allocated by a Devx API.
470 : : *
471 : : * @param[in] obj
472 : : * Pointer to a general object.
473 : : *
474 : : * @return
475 : : * 0 on success, a negative value otherwise.
476 : : */
477 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_destroy)
478 : : int
479 : 0 : mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj)
480 : : {
481 : : int ret;
482 : :
483 [ # # ]: 0 : if (!obj)
484 : : return 0;
485 : 0 : ret = mlx5_glue->devx_obj_destroy(obj->obj);
486 : 0 : mlx5_free(obj);
487 : 0 : return ret;
488 : : }
489 : :
490 : : static int
491 : 0 : mlx5_devx_cmd_query_esw_vport_context(void *ctx,
492 : : struct mlx5_hca_attr *attr)
493 : : {
494 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_esw_vport_context_in)] = {0};
495 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_esw_vport_context_out)] = {0};
496 : : void *vctx;
497 : : int rc;
498 : :
499 : 0 : MLX5_SET(query_esw_vport_context_in, in, opcode, MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT);
500 : 0 : rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
501 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
502 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "query ESW vport context", NULL, 0);
503 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
504 : : }
505 : : vctx = MLX5_ADDR_OF(query_esw_vport_context_out, out, esw_vport_context);
506 [ # # ]: 0 : attr->fdb_to_vport_reg_c = MLX5_GET(esw_vport_context, vctx, fdb_to_vport_reg_c);
507 [ # # ]: 0 : if (attr->fdb_to_vport_reg_c != 0) {
508 : 0 : attr->vport_to_fdb_metadata =
509 [ # # ]: 0 : MLX5_GET(esw_vport_context, vctx, vport_to_fdb_metadata);
510 : 0 : attr->fdb_to_vport_metadata =
511 [ # # ]: 0 : MLX5_GET(esw_vport_context, vctx, fdb_to_vport_metadata);
512 [ # # ]: 0 : attr->fdb_to_vport_reg_c_id =
513 : 0 : MLX5_GET(esw_vport_context, vctx, fdb_to_vport_reg_c_id);
514 : : }
515 : : return 0;
516 : : }
517 : :
518 : : /**
519 : : * Query NIC vport context.
520 : : * Fills minimal inline attribute.
521 : : *
522 : : * @param[in] ctx
523 : : * ibv contexts returned from mlx5dv_open_device.
524 : : * @param[in] vport
525 : : * vport index
526 : : * @param[out] attr
527 : : * Attributes device values.
528 : : *
529 : : * @return
530 : : * 0 on success, a negative value otherwise.
531 : : */
532 : : static int
533 : 0 : mlx5_devx_cmd_query_nic_vport_context(void *ctx,
534 : : unsigned int vport,
535 : : struct mlx5_hca_attr *attr)
536 : : {
537 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0};
538 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0};
539 : : void *vctx;
540 : : int rc;
541 : :
542 : : /* Query NIC vport context to determine inline mode. */
543 : 0 : MLX5_SET(query_nic_vport_context_in, in, opcode,
544 : : MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT);
545 : 0 : MLX5_SET(query_nic_vport_context_in, in, vport_number, vport);
546 [ # # ]: 0 : if (vport)
547 [ # # ]: 0 : MLX5_SET(query_nic_vport_context_in, in, other_vport, 1);
548 : 0 : rc = mlx5_glue->devx_general_cmd(ctx,
549 : : in, sizeof(in),
550 : : out, sizeof(out));
551 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
552 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "query NIC vport context", NULL, 0);
553 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
554 : : }
555 : : vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out,
556 : : nic_vport_context);
557 [ # # ]: 0 : if (attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
558 [ # # ]: 0 : attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx,
559 : : min_wqe_inline_mode);
560 [ # # ]: 0 : attr->system_image_guid = MLX5_GET64(nic_vport_context, vctx,
561 : : system_image_guid);
562 [ # # ]: 0 : attr->vport_to_fdb_metadata = MLX5_GET(nic_vport_context, vctx, vport_to_fdb_metadata);
563 [ # # ]: 0 : attr->fdb_to_vport_metadata = MLX5_GET(nic_vport_context, vctx, fdb_to_vport_metadata);
564 : 0 : return 0;
565 : : }
566 : :
567 : : /**
568 : : * Query NIC vDPA attributes.
569 : : *
570 : : * @param[in] ctx
571 : : * Context returned from mlx5 open_device() glue function.
572 : : * @param[out] vdpa_attr
573 : : * vDPA Attributes structure to fill.
574 : : */
575 : : static void
576 : 0 : mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx,
577 : : struct mlx5_hca_vdpa_attr *vdpa_attr)
578 : : {
579 : : uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)];
580 : : uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)];
581 : : void *hcattr;
582 : :
583 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, NULL,
584 : : MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION |
585 : : (uint32_t)MLX5_HCA_CAP_OPMOD_GET_CUR);
586 [ # # ]: 0 : if (!hcattr) {
587 : 0 : DRV_LOG(DEBUG, "Failed to query devx VDPA capabilities");
588 : 0 : vdpa_attr->valid = 0;
589 : : } else {
590 : 0 : vdpa_attr->valid = 1;
591 : 0 : vdpa_attr->desc_tunnel_offload_type =
592 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
593 : : desc_tunnel_offload_type);
594 : 0 : vdpa_attr->eth_frame_offload_type =
595 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
596 : : eth_frame_offload_type);
597 : 0 : vdpa_attr->virtio_version_1_0 =
598 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
599 : : virtio_version_1_0);
600 [ # # ]: 0 : vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr,
601 : : tso_ipv4);
602 [ # # ]: 0 : vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr,
603 : : tso_ipv6);
604 [ # # ]: 0 : vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
605 : : tx_csum);
606 [ # # ]: 0 : vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
607 : : rx_csum);
608 [ # # ]: 0 : vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr,
609 : : event_mode);
610 : 0 : vdpa_attr->virtio_queue_type =
611 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
612 : : virtio_queue_type);
613 : 0 : vdpa_attr->log_doorbell_stride =
614 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
615 : : log_doorbell_stride);
616 : 0 : vdpa_attr->vnet_modify_ext =
617 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
618 : : vnet_modify_ext);
619 : 0 : vdpa_attr->virtio_net_q_addr_modify =
620 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
621 : : virtio_net_q_addr_modify);
622 : 0 : vdpa_attr->virtio_q_index_modify =
623 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
624 : : virtio_q_index_modify);
625 : 0 : vdpa_attr->log_doorbell_bar_size =
626 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
627 : : log_doorbell_bar_size);
628 : 0 : vdpa_attr->doorbell_bar_offset =
629 [ # # ]: 0 : MLX5_GET64(virtio_emulation_cap, hcattr,
630 : : doorbell_bar_offset);
631 : 0 : vdpa_attr->max_num_virtio_queues =
632 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
633 : : max_num_virtio_queues);
634 [ # # ]: 0 : vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr,
635 : : umem_1_buffer_param_a);
636 [ # # ]: 0 : vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr,
637 : : umem_1_buffer_param_b);
638 [ # # ]: 0 : vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr,
639 : : umem_2_buffer_param_a);
640 [ # # ]: 0 : vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr,
641 : : umem_2_buffer_param_b);
642 [ # # ]: 0 : vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr,
643 : : umem_3_buffer_param_a);
644 [ # # ]: 0 : vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr,
645 : : umem_3_buffer_param_b);
646 : : }
647 : 0 : }
648 : :
649 : : /**
650 : : * Query match sample handle parameters.
651 : : *
652 : : * This command allows translating a field sample handle returned by either
653 : : * PARSE_GRAPH_FLOW_MATCH_SAMPLE or by GENEVE TLV OPTION object into values
654 : : * used for header modification or header matching/hashing.
655 : : *
656 : : * @param[in] ctx
657 : : * Context used to create either GENEVE TLV option or FLEX PARSE GRAPH object.
658 : : * @param[in] sample_field_id
659 : : * Field sample handle returned by either PARSE_GRAPH_FLOW_MATCH_SAMPLE
660 : : * or by GENEVE TLV OPTION object.
661 : : * @param[out] attr
662 : : * Pointer to match sample info attributes structure.
663 : : *
664 : : * @return
665 : : * 0 on success, a negative errno otherwise and rte_errno is set.
666 : : */
667 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_match_sample_info_query)
668 : : int
669 : 0 : mlx5_devx_cmd_match_sample_info_query(void *ctx, uint32_t sample_field_id,
670 : : struct mlx5_devx_match_sample_info_query_attr *attr)
671 : : {
672 : : #ifdef HAVE_IBV_FLOW_DV_SUPPORT
673 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_match_sample_info_out)] = {0};
674 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_match_sample_info_in)] = {0};
675 : : int rc;
676 : :
677 : 0 : MLX5_SET(query_match_sample_info_in, in, opcode,
678 : : MLX5_CMD_OP_QUERY_MATCH_SAMPLE_INFO);
679 : 0 : MLX5_SET(query_match_sample_info_in, in, op_mod, 0);
680 : 0 : MLX5_SET(query_match_sample_info_in, in, sample_field_id,
681 : : sample_field_id);
682 : 0 : rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
683 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
684 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "query match sample info",
685 : : "sample_field_id", sample_field_id);
686 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
687 : : }
688 [ # # ]: 0 : attr->modify_field_id = MLX5_GET(query_match_sample_info_out, out,
689 : : modify_field_id);
690 [ # # ]: 0 : attr->sample_dw_data = MLX5_GET(query_match_sample_info_out, out,
691 : : field_format_select_dw);
692 [ # # ]: 0 : attr->sample_dw_ok_bit = MLX5_GET(query_match_sample_info_out, out,
693 : : ok_bit_format_select_dw);
694 [ # # ]: 0 : attr->sample_dw_ok_bit_offset = MLX5_GET(query_match_sample_info_out,
695 : : out, ok_bit_offset);
696 : 0 : return 0;
697 : : #else
698 : : (void)ctx;
699 : : (void)sample_field_id;
700 : : (void)attr;
701 : : return -ENOTSUP;
702 : : #endif
703 : : }
704 : :
705 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_query_parse_samples)
706 : : int
707 : 0 : mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,
708 : : uint32_t *ids,
709 : : uint32_t num, uint8_t *anchor)
710 : : {
711 : 0 : uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
712 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0};
713 : : void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr);
714 : : void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex);
715 : : void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
716 : : int ret;
717 : : uint32_t idx = 0;
718 : : uint32_t i;
719 : :
720 [ # # ]: 0 : if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) {
721 : 0 : rte_errno = EINVAL;
722 : 0 : DRV_LOG(ERR, "Too many sample IDs to be fetched.");
723 : 0 : return -rte_errno;
724 : : }
725 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
726 : : MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
727 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
728 : : MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
729 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id);
730 : 0 : ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in),
731 : : out, sizeof(out));
732 [ # # ]: 0 : if (ret) {
733 : 0 : rte_errno = ret;
734 : 0 : DRV_LOG(ERR, "Failed to query sample IDs with object %p.",
735 : : (void *)flex_obj);
736 : 0 : return -rte_errno;
737 : : }
738 [ # # ]: 0 : if (anchor)
739 [ # # ]: 0 : *anchor = MLX5_GET(parse_graph_flex, flex, head_anchor_id);
740 [ # # ]: 0 : for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM && idx < num; i++) {
741 : 0 : void *s_off = (void *)((char *)sample + i *
742 : : MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
743 : : uint32_t en;
744 : :
745 [ # # ]: 0 : en = MLX5_GET(parse_graph_flow_match_sample, s_off,
746 : : flow_match_sample_en);
747 [ # # ]: 0 : if (!en)
748 : 0 : continue;
749 [ # # ]: 0 : ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off,
750 : : flow_match_sample_field_id);
751 : : }
752 [ # # ]: 0 : if (num != idx) {
753 : 0 : rte_errno = EINVAL;
754 : 0 : DRV_LOG(ERR, "Number of sample IDs are not as expected.");
755 : 0 : return -rte_errno;
756 : : }
757 : : return ret;
758 : : }
759 : :
760 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_flex_parser)
761 : : struct mlx5_devx_obj *
762 : 0 : mlx5_devx_cmd_create_flex_parser(void *ctx,
763 : : struct mlx5_devx_graph_node_attr *data)
764 : : {
765 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0};
766 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
767 : : void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr);
768 : : void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex);
769 : : void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
770 : : void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc);
771 : : void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc);
772 : 0 : struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc
773 : : (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY);
774 : : uint32_t i;
775 : :
776 [ # # ]: 0 : if (!parse_flex_obj) {
777 : 0 : DRV_LOG(ERR, "Failed to allocate flex parser data.");
778 : 0 : rte_errno = ENOMEM;
779 : 0 : return NULL;
780 : : }
781 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
782 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
783 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
784 : : MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
785 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, header_length_mode,
786 : : data->header_length_mode);
787 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, header_length_field_offset_mode,
788 : : data->header_length_field_offset_mode);
789 [ # # ]: 0 : MLX5_SET64(parse_graph_flex, flex, modify_field_select,
790 : : data->modify_field_select);
791 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, header_length_base_value,
792 : : data->header_length_base_value);
793 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, header_length_field_offset,
794 : : data->header_length_field_offset);
795 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, header_length_field_shift,
796 : : data->header_length_field_shift);
797 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, next_header_field_offset,
798 : : data->next_header_field_offset);
799 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, next_header_field_size,
800 : : data->next_header_field_size);
801 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, header_length_field_mask,
802 : : data->header_length_field_mask);
803 [ # # ]: 0 : for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {
804 : : struct mlx5_devx_match_sample_attr *s = &data->sample[i];
805 : 0 : void *s_off = (void *)((char *)sample + i *
806 : : MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
807 : :
808 [ # # ]: 0 : if (!s->flow_match_sample_en)
809 : 0 : continue;
810 [ # # ]: 0 : MLX5_SET(parse_graph_flow_match_sample, s_off,
811 : : flow_match_sample_en, !!s->flow_match_sample_en);
812 [ # # ]: 0 : MLX5_SET(parse_graph_flow_match_sample, s_off,
813 : : flow_match_sample_field_offset,
814 : : s->flow_match_sample_field_offset);
815 [ # # ]: 0 : MLX5_SET(parse_graph_flow_match_sample, s_off,
816 : : flow_match_sample_offset_mode,
817 : : s->flow_match_sample_offset_mode);
818 [ # # ]: 0 : MLX5_SET(parse_graph_flow_match_sample, s_off,
819 : : flow_match_sample_field_offset_mask,
820 : : s->flow_match_sample_field_offset_mask);
821 [ # # ]: 0 : MLX5_SET(parse_graph_flow_match_sample, s_off,
822 : : flow_match_sample_field_offset_shift,
823 : : s->flow_match_sample_field_offset_shift);
824 [ # # ]: 0 : MLX5_SET(parse_graph_flow_match_sample, s_off,
825 : : flow_match_sample_field_base_offset,
826 : : s->flow_match_sample_field_base_offset);
827 [ # # ]: 0 : MLX5_SET(parse_graph_flow_match_sample, s_off,
828 : : flow_match_sample_tunnel_mode,
829 : : s->flow_match_sample_tunnel_mode);
830 : : }
831 [ # # ]: 0 : for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) {
832 : : struct mlx5_devx_graph_arc_attr *ia = &data->in[i];
833 : : struct mlx5_devx_graph_arc_attr *oa = &data->out[i];
834 : 0 : void *in_off = (void *)((char *)in_arc + i *
835 : : MLX5_ST_SZ_BYTES(parse_graph_arc));
836 : 0 : void *out_off = (void *)((char *)out_arc + i *
837 : : MLX5_ST_SZ_BYTES(parse_graph_arc));
838 : :
839 [ # # ]: 0 : if (ia->arc_parse_graph_node != 0) {
840 [ # # ]: 0 : MLX5_SET(parse_graph_arc, in_off,
841 : : compare_condition_value,
842 : : ia->compare_condition_value);
843 [ # # ]: 0 : MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel,
844 : : ia->start_inner_tunnel);
845 [ # # ]: 0 : MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node,
846 : : ia->arc_parse_graph_node);
847 [ # # ]: 0 : MLX5_SET(parse_graph_arc, in_off,
848 : : parse_graph_node_handle,
849 : : ia->parse_graph_node_handle);
850 : : }
851 [ # # ]: 0 : if (oa->arc_parse_graph_node != 0) {
852 [ # # ]: 0 : MLX5_SET(parse_graph_arc, out_off,
853 : : compare_condition_value,
854 : : oa->compare_condition_value);
855 [ # # ]: 0 : MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel,
856 : : oa->start_inner_tunnel);
857 [ # # ]: 0 : MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node,
858 : : oa->arc_parse_graph_node);
859 [ # # ]: 0 : MLX5_SET(parse_graph_arc, out_off,
860 : : parse_graph_node_handle,
861 : : oa->parse_graph_node_handle);
862 : : }
863 : : }
864 : 0 : parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
865 : : out, sizeof(out));
866 [ # # ]: 0 : if (!parse_flex_obj->obj) {
867 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create FLEX PARSE GRAPH", NULL, 0);
868 : 0 : mlx5_free(parse_flex_obj);
869 : 0 : return NULL;
870 : : }
871 [ # # ]: 0 : parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
872 : 0 : return parse_flex_obj;
873 : : }
874 : :
875 : : static int
876 : 0 : mlx5_devx_cmd_query_hca_parse_graph_node_cap
877 : : (void *ctx, struct mlx5_hca_flex_attr *attr)
878 : : {
879 : : uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)];
880 : : uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)];
881 : : void *hcattr;
882 : : int rc;
883 : :
884 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
885 : : MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP |
886 : : (uint32_t)MLX5_HCA_CAP_OPMOD_GET_CUR);
887 [ # # ]: 0 : if (!hcattr)
888 : 0 : return rc;
889 [ # # ]: 0 : attr->node_in = MLX5_GET(parse_graph_node_cap, hcattr, node_in);
890 [ # # ]: 0 : attr->node_out = MLX5_GET(parse_graph_node_cap, hcattr, node_out);
891 [ # # ]: 0 : attr->header_length_mode = MLX5_GET(parse_graph_node_cap, hcattr,
892 : : header_length_mode);
893 [ # # ]: 0 : attr->sample_offset_mode = MLX5_GET(parse_graph_node_cap, hcattr,
894 : : sample_offset_mode);
895 [ # # ]: 0 : attr->max_num_arc_in = MLX5_GET(parse_graph_node_cap, hcattr,
896 : : max_num_arc_in);
897 [ # # ]: 0 : attr->max_num_arc_out = MLX5_GET(parse_graph_node_cap, hcattr,
898 : : max_num_arc_out);
899 [ # # ]: 0 : attr->max_num_sample = MLX5_GET(parse_graph_node_cap, hcattr,
900 : : max_num_sample);
901 [ # # ]: 0 : attr->parse_graph_anchor = MLX5_GET(parse_graph_node_cap, hcattr, parse_graph_anchor);
902 [ # # ]: 0 : attr->sample_tunnel_inner2 = MLX5_GET(parse_graph_node_cap, hcattr,
903 : : sample_tunnel_inner2);
904 [ # # ]: 0 : attr->zero_size_supported = MLX5_GET(parse_graph_node_cap, hcattr,
905 : : zero_size_supported);
906 [ # # ]: 0 : attr->sample_id_in_out = MLX5_GET(parse_graph_node_cap, hcattr,
907 : : sample_id_in_out);
908 [ # # ]: 0 : attr->max_base_header_length = MLX5_GET(parse_graph_node_cap, hcattr,
909 : : max_base_header_length);
910 [ # # ]: 0 : attr->max_sample_base_offset = MLX5_GET(parse_graph_node_cap, hcattr,
911 : : max_sample_base_offset);
912 [ # # ]: 0 : attr->max_next_header_offset = MLX5_GET(parse_graph_node_cap, hcattr,
913 : : max_next_header_offset);
914 [ # # ]: 0 : attr->header_length_mask_width = MLX5_GET(parse_graph_node_cap, hcattr,
915 : : header_length_mask_width);
916 [ # # ]: 0 : attr->header_length_field_mode_wa = !MLX5_GET(parse_graph_node_cap, hcattr,
917 : : header_length_field_offset_mode);
918 : : /* Get the max supported samples from HCA CAP 2 */
919 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
920 : : MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 |
921 : : (uint32_t)MLX5_HCA_CAP_OPMOD_GET_CUR);
922 [ # # ]: 0 : if (!hcattr)
923 : 0 : return rc;
924 : 0 : attr->max_num_prog_sample =
925 [ # # ]: 0 : MLX5_GET(cmd_hca_cap_2, hcattr, max_num_prog_sample_field);
926 : 0 : return 0;
927 : : }
928 : :
929 : : static int
930 : 0 : mlx5_devx_query_pkt_integrity_match(void *hcattr)
931 : : {
932 [ # # ]: 0 : return MLX5_GET(flow_table_nic_cap, hcattr,
933 [ # # # # ]: 0 : ft_field_support_2_nic_receive.inner_l3_ok) &&
934 : : MLX5_GET(flow_table_nic_cap, hcattr,
935 [ # # # # ]: 0 : ft_field_support_2_nic_receive.inner_l4_ok) &&
936 : : MLX5_GET(flow_table_nic_cap, hcattr,
937 [ # # # # ]: 0 : ft_field_support_2_nic_receive.outer_l3_ok) &&
938 : : MLX5_GET(flow_table_nic_cap, hcattr,
939 [ # # # # ]: 0 : ft_field_support_2_nic_receive.outer_l4_ok) &&
940 : : MLX5_GET(flow_table_nic_cap, hcattr,
941 : : ft_field_support_2_nic_receive
942 [ # # # # ]: 0 : .inner_ipv4_checksum_ok) &&
943 : : MLX5_GET(flow_table_nic_cap, hcattr,
944 [ # # # # ]: 0 : ft_field_support_2_nic_receive.inner_l4_checksum_ok) &&
945 : : MLX5_GET(flow_table_nic_cap, hcattr,
946 : : ft_field_support_2_nic_receive
947 [ # # # # : 0 : .outer_ipv4_checksum_ok) &&
# # # # #
# # # # #
# # # # ]
948 [ # # # # ]: 0 : MLX5_GET(flow_table_nic_cap, hcattr,
949 : : ft_field_support_2_nic_receive.outer_l4_checksum_ok);
950 : : }
951 : :
952 : : /**
953 : : * Query HCA attributes.
954 : : * Using those attributes we can check on run time if the device
955 : : * is having the required capabilities.
956 : : *
957 : : * @param[in] ctx
958 : : * Context returned from mlx5 open_device() glue function.
959 : : * @param[out] attr
960 : : * Attributes device values.
961 : : *
962 : : * @return
963 : : * 0 on success, a negative value otherwise.
964 : : */
965 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_query_hca_attr)
966 : : int
967 : 0 : mlx5_devx_cmd_query_hca_attr(void *ctx,
968 : : struct mlx5_hca_attr *attr)
969 : : {
970 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
971 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
972 : : bool hca_cap_2_sup;
973 : : uint64_t general_obj_types_supported = 0;
974 : : uint64_t stc_action_type_127_64;
975 : : void *hcattr;
976 : : int rc, i;
977 : :
978 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
979 : : MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE |
980 : : (uint32_t)MLX5_HCA_CAP_OPMOD_GET_CUR);
981 [ # # ]: 0 : if (!hcattr)
982 : 0 : return rc;
983 [ # # ]: 0 : hca_cap_2_sup = MLX5_GET(cmd_hca_cap, hcattr, hca_cap_2);
984 [ # # ]: 0 : attr->max_wqe_sz_sq = MLX5_GET(cmd_hca_cap, hcattr, max_wqe_sz_sq);
985 : 0 : attr->flow_counter_bulk_alloc_bitmap =
986 [ # # ]: 0 : MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc);
987 [ # # ]: 0 : attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr,
988 : : flow_counters_dump);
989 [ # # ]: 0 : attr->log_max_rmp = MLX5_GET(cmd_hca_cap, hcattr, log_max_rmp);
990 [ # # ]: 0 : attr->mem_rq_rmp = MLX5_GET(cmd_hca_cap, hcattr, mem_rq_rmp);
991 [ # # ]: 0 : attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr,
992 : : log_max_rqt_size);
993 [ # # ]: 0 : attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager);
994 [ # # ]: 0 : attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin);
995 [ # # ]: 0 : attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr,
996 : : log_max_hairpin_queues);
997 [ # # ]: 0 : attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr,
998 : : log_max_hairpin_wq_data_sz);
999 [ # # ]: 0 : attr->log_max_hairpin_num_packets = MLX5_GET
1000 : : (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz);
1001 [ # # ]: 0 : attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id);
1002 [ # # ]: 0 : attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr,
1003 : : relaxed_ordering_write);
1004 [ # # ]: 0 : attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr,
1005 : : relaxed_ordering_read);
1006 [ # # ]: 0 : attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr,
1007 : : access_register_user);
1008 [ # # ]: 0 : attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr,
1009 : : eth_net_offloads);
1010 [ # # ]: 0 : attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);
1011 [ # # ]: 0 : attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr,
1012 : : flex_parser_protocols);
1013 [ # # ]: 0 : attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr,
1014 : : max_geneve_tlv_options);
1015 [ # # ]: 0 : attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr,
1016 : : max_geneve_tlv_option_data_len);
1017 [ # # ]: 0 : attr->geneve_tlv_option_offset = MLX5_GET(cmd_hca_cap, hcattr,
1018 : : geneve_tlv_option_offset);
1019 [ # # ]: 0 : attr->geneve_tlv_sample = MLX5_GET(cmd_hca_cap, hcattr,
1020 : : geneve_tlv_sample);
1021 [ # # ]: 0 : attr->query_match_sample_info = MLX5_GET(cmd_hca_cap, hcattr,
1022 : : query_match_sample_info);
1023 [ # # ]: 0 : attr->geneve_tlv_option_sample_id = MLX5_GET(cmd_hca_cap, hcattr,
1024 : : flex_parser_id_geneve_opt_0);
1025 [ # # ]: 0 : attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos);
1026 [ # # ]: 0 : attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr,
1027 : : wqe_index_ignore_cap);
1028 [ # # ]: 0 : attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd);
1029 [ # # ]: 0 : attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq);
1030 [ # # ]: 0 : attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr,
1031 : : log_max_static_sq_wq);
1032 [ # # ]: 0 : attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports);
1033 [ # # ]: 0 : attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr,
1034 : : device_frequency_khz);
1035 : 0 : attr->scatter_fcs_w_decap_disable =
1036 [ # # ]: 0 : MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable);
1037 [ # # ]: 0 : attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce);
1038 [ # # ]: 0 : attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format);
1039 [ # # ]: 0 : attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format);
1040 : 0 : attr->steering_format_version =
1041 [ # # ]: 0 : MLX5_GET(cmd_hca_cap, hcattr, steering_format_version);
1042 [ # # ]: 0 : attr->regexp_params = MLX5_GET(cmd_hca_cap, hcattr, regexp_params);
1043 [ # # ]: 0 : attr->regexp_version = MLX5_GET(cmd_hca_cap, hcattr, regexp_version);
1044 [ # # ]: 0 : attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr,
1045 : : regexp_num_of_engines);
1046 : : /* Read the general_obj_types bitmap and extract the relevant bits. */
1047 [ # # ]: 0 : general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr,
1048 : : general_obj_types);
1049 : 0 : attr->qos.flow_meter_aso_sup =
1050 : 0 : !!(general_obj_types_supported &
1051 : : MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO);
1052 : 0 : attr->vdpa.valid = !!(general_obj_types_supported &
1053 : : MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q);
1054 : 0 : attr->vdpa.queue_counters_valid =
1055 : 0 : !!(general_obj_types_supported &
1056 : : MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS);
1057 : 0 : attr->parse_graph_flex_node =
1058 : 0 : !!(general_obj_types_supported &
1059 : : MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE);
1060 : 0 : attr->flow_hit_aso = !!(general_obj_types_supported &
1061 : : MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO);
1062 : 0 : attr->geneve_tlv_opt = !!(general_obj_types_supported &
1063 : : MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT);
1064 : 0 : attr->dek = !!(general_obj_types_supported &
1065 : : MLX5_GENERAL_OBJ_TYPES_CAP_DEK);
1066 : 0 : attr->import_kek = !!(general_obj_types_supported &
1067 : : MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK);
1068 : 0 : attr->credential = !!(general_obj_types_supported &
1069 : : MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL);
1070 : 0 : attr->crypto_login = !!(general_obj_types_supported &
1071 : : MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN);
1072 : : /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */
1073 [ # # ]: 0 : attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq);
1074 [ # # ]: 0 : attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp);
1075 [ # # ]: 0 : attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz);
1076 [ # # ]: 0 : attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz);
1077 [ # # ]: 0 : attr->log_max_wq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_wq_sz);
1078 [ # # ]: 0 : attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz);
1079 [ # # ]: 0 : attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd);
1080 [ # # ]: 0 : attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq);
1081 [ # # ]: 0 : attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz);
1082 : 0 : attr->reg_c_preserve =
1083 [ # # ]: 0 : MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve);
1084 [ # # ]: 0 : attr->mmo_regex_qp_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_qp);
1085 [ # # ]: 0 : attr->mmo_regex_sq_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_sq);
1086 [ # # ]: 0 : attr->mmo_dma_sq_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_sq);
1087 [ # # ]: 0 : attr->mmo_compress_sq_en = MLX5_GET(cmd_hca_cap, hcattr,
1088 : : compress_mmo_sq);
1089 [ # # ]: 0 : attr->mmo_decompress_sq_en = MLX5_GET(cmd_hca_cap, hcattr,
1090 : : decompress_mmo_sq);
1091 [ # # ]: 0 : attr->mmo_dma_qp_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_qp);
1092 [ # # ]: 0 : attr->mmo_compress_qp_en = MLX5_GET(cmd_hca_cap, hcattr,
1093 : : compress_mmo_qp);
1094 [ # # ]: 0 : attr->decomp_deflate_v1_en = MLX5_GET(cmd_hca_cap, hcattr,
1095 : : decompress_deflate_v1);
1096 [ # # ]: 0 : attr->decomp_deflate_v2_en = MLX5_GET(cmd_hca_cap, hcattr,
1097 : : decompress_deflate_v2);
1098 [ # # ]: 0 : attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr,
1099 : : compress_min_block_size);
1100 [ # # ]: 0 : attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size);
1101 [ # # ]: 0 : attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr,
1102 : : log_compress_mmo_size);
1103 [ # # ]: 0 : attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr,
1104 : : log_decompress_mmo_size);
1105 [ # # ]: 0 : attr->decomp_lz4_data_only_en = MLX5_GET(cmd_hca_cap, hcattr,
1106 : : decompress_lz4_data_only_v2);
1107 [ # # ]: 0 : attr->decomp_lz4_no_checksum_en = MLX5_GET(cmd_hca_cap, hcattr,
1108 : : decompress_lz4_no_checksum_v2);
1109 [ # # ]: 0 : attr->decomp_lz4_checksum_en = MLX5_GET(cmd_hca_cap, hcattr,
1110 : : decompress_lz4_checksum_v2);
1111 [ # # ]: 0 : attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression);
1112 [ # # ]: 0 : attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr,
1113 : : mini_cqe_resp_flow_tag);
1114 [ # # ]: 0 : attr->cqe_compression_128 = MLX5_GET(cmd_hca_cap, hcattr,
1115 : : cqe_compression_128);
1116 [ # # ]: 0 : attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr,
1117 : : mini_cqe_resp_l3_l4_tag);
1118 [ # # ]: 0 : attr->enhanced_cqe_compression = MLX5_GET(cmd_hca_cap, hcattr,
1119 : : enhanced_cqe_compression);
1120 : 0 : attr->umr_indirect_mkey_disabled =
1121 [ # # ]: 0 : MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled);
1122 : 0 : attr->umr_modify_entity_size_disabled =
1123 [ # # ]: 0 : MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled);
1124 [ # # ]: 0 : attr->wait_on_time = MLX5_GET(cmd_hca_cap, hcattr, wait_on_time);
1125 [ # # ]: 0 : attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto);
1126 : 0 : attr->ct_offload = !!(general_obj_types_supported &
1127 : : MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD);
1128 [ # # ]: 0 : attr->rq_delay_drop = MLX5_GET(cmd_hca_cap, hcattr, rq_delay_drop);
1129 [ # # ]: 0 : attr->nic_flow_table = MLX5_GET(cmd_hca_cap, hcattr, nic_flow_table);
1130 [ # # ]: 0 : attr->striding_rq = MLX5_GET(cmd_hca_cap, hcattr, striding_rq);
1131 : 0 : attr->ext_stride_num_range =
1132 [ # # ]: 0 : MLX5_GET(cmd_hca_cap, hcattr, ext_stride_num_range);
1133 [ # # ]: 0 : attr->nic_flow_table = MLX5_GET(cmd_hca_cap, hcattr, nic_flow_table);
1134 [ # # ]: 0 : attr->max_flow_counter_15_0 = MLX5_GET(cmd_hca_cap, hcattr,
1135 : : max_flow_counter_15_0);
1136 [ # # ]: 0 : attr->max_flow_counter_31_16 = MLX5_GET(cmd_hca_cap, hcattr,
1137 : : max_flow_counter_31_16);
1138 [ # # ]: 0 : attr->alloc_flow_counter_pd = MLX5_GET(cmd_hca_cap, hcattr,
1139 : : alloc_flow_counter_pd);
1140 [ # # ]: 0 : attr->flow_counter_access_aso = MLX5_GET(cmd_hca_cap, hcattr,
1141 : : flow_counter_access_aso);
1142 [ # # ]: 0 : attr->flow_access_aso_opc_mod = MLX5_GET(cmd_hca_cap, hcattr,
1143 : : flow_access_aso_opc_mod);
1144 [ # # ]: 0 : attr->wqe_based_flow_table_sup = MLX5_GET(cmd_hca_cap, hcattr,
1145 : : wqe_based_flow_table_update_cap);
1146 : : /*
1147 : : * Flex item support needs max_num_prog_sample_field
1148 : : * from the Capabilities 2 table for PARSE_GRAPH_NODE
1149 : : */
1150 [ # # ]: 0 : if (attr->parse_graph_flex_node) {
1151 : 0 : rc = mlx5_devx_cmd_query_hca_parse_graph_node_cap
1152 : : (ctx, &attr->flex);
1153 [ # # ]: 0 : if (rc)
1154 : : return -1;
1155 : 0 : attr->flex.query_match_sample_info =
1156 : 0 : attr->query_match_sample_info;
1157 : : }
1158 [ # # ]: 0 : if (attr->crypto) {
1159 [ # # # # : 0 : attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts) ||
# # ]
1160 [ # # # # : 0 : MLX5_GET(cmd_hca_cap, hcattr, aes_xts_multi_block_be_tweak) ||
# # # # #
# # # ]
1161 : : MLX5_GET(cmd_hca_cap, hcattr, aes_xts_single_block_le_tweak);
1162 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1163 : : MLX5_GET_HCA_CAP_OP_MOD_CRYPTO |
1164 : : (uint32_t)MLX5_HCA_CAP_OPMOD_GET_CUR);
1165 [ # # ]: 0 : if (!hcattr)
1166 : : return -1;
1167 [ # # ]: 0 : attr->crypto_wrapped_import_method = !!(MLX5_GET(crypto_caps,
1168 : : hcattr, wrapped_import_method)
1169 : 0 : & 1 << 2);
1170 [ # # ]: 0 : attr->crypto_mmo.crypto_mmo_qp = MLX5_GET(crypto_caps, hcattr, crypto_mmo_qp);
1171 : 0 : attr->crypto_mmo.gcm_256_encrypt =
1172 [ # # ]: 0 : MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_256_encrypt);
1173 : 0 : attr->crypto_mmo.gcm_128_encrypt =
1174 [ # # ]: 0 : MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_128_encrypt);
1175 : 0 : attr->crypto_mmo.gcm_256_decrypt =
1176 [ # # ]: 0 : MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_256_decrypt);
1177 : 0 : attr->crypto_mmo.gcm_128_decrypt =
1178 [ # # ]: 0 : MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_128_decrypt);
1179 : 0 : attr->crypto_mmo.gcm_auth_tag_128 =
1180 [ # # ]: 0 : MLX5_GET(crypto_caps, hcattr, gcm_auth_tag_128);
1181 : 0 : attr->crypto_mmo.gcm_auth_tag_96 =
1182 [ # # ]: 0 : MLX5_GET(crypto_caps, hcattr, gcm_auth_tag_96);
1183 : 0 : attr->crypto_mmo.log_crypto_mmo_max_size =
1184 [ # # ]: 0 : MLX5_GET(crypto_caps, hcattr, log_crypto_mmo_max_size);
1185 : : }
1186 [ # # ]: 0 : if (hca_cap_2_sup) {
1187 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1188 : : MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 |
1189 : : (uint32_t)MLX5_HCA_CAP_OPMOD_GET_CUR);
1190 [ # # ]: 0 : if (!hcattr) {
1191 : 0 : DRV_LOG(DEBUG,
1192 : : "Failed to query DevX HCA capabilities 2.");
1193 : 0 : return rc;
1194 : : }
1195 [ # # ]: 0 : attr->log_min_stride_wqe_sz = MLX5_GET(cmd_hca_cap_2, hcattr,
1196 : : log_min_stride_wqe_sz);
1197 [ # # ]: 0 : attr->hairpin_sq_wqe_bb_size = MLX5_GET(cmd_hca_cap_2, hcattr,
1198 : : hairpin_sq_wqe_bb_size);
1199 [ # # ]: 0 : attr->hairpin_sq_wq_in_host_mem = MLX5_GET(cmd_hca_cap_2, hcattr,
1200 : : hairpin_sq_wq_in_host_mem);
1201 [ # # ]: 0 : attr->hairpin_data_buffer_locked = MLX5_GET(cmd_hca_cap_2, hcattr,
1202 : : hairpin_data_buffer_locked);
1203 [ # # ]: 0 : attr->flow_counter_bulk_log_max_alloc = MLX5_GET(cmd_hca_cap_2,
1204 : : hcattr, flow_counter_bulk_log_max_alloc);
1205 : 0 : attr->flow_counter_bulk_log_granularity =
1206 [ # # ]: 0 : MLX5_GET(cmd_hca_cap_2, hcattr,
1207 : : flow_counter_bulk_log_granularity);
1208 [ # # ]: 0 : rc = MLX5_GET(cmd_hca_cap_2, hcattr,
1209 : : cross_vhca_object_to_object_supported);
1210 : 0 : attr->cross_vhca =
1211 : : (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_STC_TO_TIR) &&
1212 : : (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_STC_TO_FT) &&
1213 : 0 : (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_FT_TO_FT) &&
1214 : : (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_FT_TO_RTC);
1215 [ # # ]: 0 : rc = MLX5_GET(cmd_hca_cap_2, hcattr,
1216 : : allowed_object_for_other_vhca_access);
1217 : 0 : attr->cross_vhca = attr->cross_vhca &&
1218 : : (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_TIR) &&
1219 [ # # # # ]: 0 : (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_FT) &&
1220 : : (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_RTC);
1221 [ # # ]: 0 : if (attr->ct_offload)
1222 [ # # ]: 0 : attr->log_max_conn_track_offload = MLX5_GET(cmd_hca_cap_2, hcattr,
1223 : : log_max_conn_track_offload);
1224 : : }
1225 [ # # ]: 0 : if (attr->log_min_stride_wqe_sz == 0)
1226 : 0 : attr->log_min_stride_wqe_sz = MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE;
1227 [ # # ]: 0 : if (attr->qos.sup) {
1228 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1229 : : MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |
1230 : : (uint32_t)MLX5_HCA_CAP_OPMOD_GET_CUR);
1231 [ # # ]: 0 : if (!hcattr) {
1232 : 0 : DRV_LOG(DEBUG, "Failed to query devx QOS capabilities");
1233 : 0 : return rc;
1234 : : }
1235 : 0 : attr->qos.flow_meter_old =
1236 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr, flow_meter_old);
1237 [ # # ]: 0 : attr->qos.log_max_flow_meter =
1238 : 0 : MLX5_GET(qos_cap, hcattr, log_max_flow_meter);
1239 [ # # ]: 0 : attr->qos.flow_meter_reg_c_ids =
1240 : : MLX5_GET(qos_cap, hcattr, flow_meter_reg_id);
1241 : 0 : attr->qos.flow_meter =
1242 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr, flow_meter);
1243 : 0 : attr->qos.packet_pacing =
1244 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr, packet_pacing);
1245 : 0 : attr->qos.wqe_rate_pp =
1246 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr, wqe_rate_pp);
1247 [ # # ]: 0 : if (attr->qos.flow_meter_aso_sup) {
1248 : 0 : attr->qos.log_meter_aso_granularity =
1249 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr,
1250 : : log_meter_aso_granularity);
1251 : 0 : attr->qos.log_meter_aso_max_alloc =
1252 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr,
1253 : : log_meter_aso_max_alloc);
1254 : 0 : attr->qos.log_max_num_meter_aso =
1255 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr,
1256 : : log_max_num_meter_aso);
1257 : : }
1258 : : }
1259 [ # # ]: 0 : if (attr->vdpa.valid)
1260 : 0 : mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa);
1261 [ # # ]: 0 : if (!attr->eth_net_offloads)
1262 : : return 0;
1263 : : /* Query Flow Sampler Capability From FLow Table Properties Layout. */
1264 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1265 : : MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE |
1266 : : (uint32_t)MLX5_HCA_CAP_OPMOD_GET_CUR);
1267 [ # # ]: 0 : if (!hcattr) {
1268 : 0 : attr->log_max_ft_sampler_num = 0;
1269 : 0 : return rc;
1270 : : }
1271 [ # # ]: 0 : attr->log_max_ft_sampler_num = MLX5_GET
1272 : : (flow_table_nic_cap, hcattr,
1273 : : flow_table_properties_nic_receive.log_max_ft_sampler_num);
1274 [ # # ]: 0 : attr->flow.tunnel_header_0_1 = MLX5_GET
1275 : : (flow_table_nic_cap, hcattr,
1276 : : ft_field_support_2_nic_receive.tunnel_header_0_1);
1277 [ # # ]: 0 : attr->flow.tunnel_header_2_3 = MLX5_GET
1278 : : (flow_table_nic_cap, hcattr,
1279 : : ft_field_support_2_nic_receive.tunnel_header_2_3);
1280 [ # # ]: 0 : attr->modify_outer_ip_ecn = MLX5_GET
1281 : : (flow_table_nic_cap, hcattr,
1282 : : ft_header_modify_nic_receive.outer_ip_ecn);
1283 [ # # ]: 0 : attr->modify_outer_ipv6_traffic_class = MLX5_GET
1284 : : (flow_table_nic_cap, hcattr,
1285 : : ft_header_modify_nic_receive.outer_ipv6_traffic_class);
1286 : 0 : attr->set_reg_c = 0xffff;
1287 [ # # ]: 0 : if (attr->nic_flow_table) {
1288 : : #define GET_RX_REG_X_BITS \
1289 : : MLX5_GET(flow_table_nic_cap, hcattr, \
1290 : : ft_header_modify_nic_receive.metadata_reg_c_x)
1291 : : #define GET_TX_REG_X_BITS \
1292 : : MLX5_GET(flow_table_nic_cap, hcattr, \
1293 : : ft_header_modify_nic_transmit.metadata_reg_c_x)
1294 : :
1295 : : uint32_t tx_reg, rx_reg, reg_c_8_15;
1296 : :
1297 [ # # ]: 0 : tx_reg = GET_TX_REG_X_BITS;
1298 [ # # ]: 0 : reg_c_8_15 = MLX5_GET(flow_table_nic_cap, hcattr,
1299 : : ft_field_support_2_nic_transmit.metadata_reg_c_8_15);
1300 : 0 : tx_reg |= ((0xff & reg_c_8_15) << 8);
1301 [ # # ]: 0 : rx_reg = GET_RX_REG_X_BITS;
1302 [ # # ]: 0 : reg_c_8_15 = MLX5_GET(flow_table_nic_cap, hcattr,
1303 : : ft_field_support_2_nic_receive.metadata_reg_c_8_15);
1304 : 0 : rx_reg |= ((0xff & reg_c_8_15) << 8);
1305 : 0 : attr->set_reg_c &= (rx_reg & tx_reg);
1306 : :
1307 [ # # ]: 0 : attr->rx_sw_owner_v2 = MLX5_GET(flow_table_nic_cap, hcattr,
1308 : : flow_table_properties_nic_receive.sw_owner_v2);
1309 [ # # ]: 0 : if (!attr->rx_sw_owner_v2)
1310 [ # # ]: 0 : attr->rx_sw_owner = MLX5_GET(flow_table_nic_cap, hcattr,
1311 : : flow_table_properties_nic_receive.sw_owner);
1312 : :
1313 [ # # ]: 0 : attr->tx_sw_owner_v2 = MLX5_GET(flow_table_nic_cap, hcattr,
1314 : : flow_table_properties_nic_transmit.sw_owner_v2);
1315 [ # # ]: 0 : if (!attr->tx_sw_owner_v2)
1316 [ # # ]: 0 : attr->tx_sw_owner = MLX5_GET(flow_table_nic_cap, hcattr,
1317 : : flow_table_properties_nic_transmit.sw_owner);
1318 : :
1319 : : #undef GET_RX_REG_X_BITS
1320 : : #undef GET_TX_REG_X_BITS
1321 : : }
1322 : 0 : attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr);
1323 [ # # ]: 0 : attr->inner_ipv4_ihl = MLX5_GET
1324 : : (flow_table_nic_cap, hcattr,
1325 : : ft_field_support_2_nic_receive.inner_ipv4_ihl);
1326 [ # # ]: 0 : attr->outer_ipv4_ihl = MLX5_GET
1327 : : (flow_table_nic_cap, hcattr,
1328 : : ft_field_support_2_nic_receive.outer_ipv4_ihl);
1329 [ # # ]: 0 : attr->lag_rx_port_affinity = MLX5_GET
1330 : : (flow_table_nic_cap, hcattr,
1331 : : ft_field_support_2_nic_receive.lag_rx_port_affinity);
1332 : : /* Query HCA offloads for Ethernet protocol. */
1333 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1334 : : MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS |
1335 : : (uint32_t)MLX5_HCA_CAP_OPMOD_GET_CUR);
1336 [ # # ]: 0 : if (!hcattr) {
1337 : 0 : attr->eth_net_offloads = 0;
1338 : 0 : return rc;
1339 : : }
1340 [ # # ]: 0 : attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps,
1341 : : hcattr, wqe_vlan_insert);
1342 [ # # ]: 0 : attr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps,
1343 : : hcattr, csum_cap);
1344 [ # # ]: 0 : attr->vlan_cap = MLX5_GET(per_protocol_networking_offload_caps,
1345 : : hcattr, vlan_cap);
1346 [ # # ]: 0 : attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr,
1347 : : lro_cap);
1348 [ # # ]: 0 : attr->max_lso_cap = MLX5_GET(per_protocol_networking_offload_caps,
1349 : : hcattr, max_lso_cap);
1350 [ # # ]: 0 : attr->scatter_fcs = MLX5_GET(per_protocol_networking_offload_caps,
1351 : : hcattr, scatter_fcs);
1352 [ # # ]: 0 : attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps,
1353 : : hcattr, tunnel_lro_gre);
1354 [ # # ]: 0 : attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps,
1355 : : hcattr, tunnel_lro_vxlan);
1356 [ # # ]: 0 : attr->swp = MLX5_GET(per_protocol_networking_offload_caps,
1357 : : hcattr, swp);
1358 : 0 : attr->tunnel_stateless_gre =
1359 [ # # ]: 0 : MLX5_GET(per_protocol_networking_offload_caps,
1360 : : hcattr, tunnel_stateless_gre);
1361 : 0 : attr->tunnel_stateless_vxlan =
1362 [ # # ]: 0 : MLX5_GET(per_protocol_networking_offload_caps,
1363 : : hcattr, tunnel_stateless_vxlan);
1364 [ # # ]: 0 : attr->swp_csum = MLX5_GET(per_protocol_networking_offload_caps,
1365 : : hcattr, swp_csum);
1366 [ # # ]: 0 : attr->swp_lso = MLX5_GET(per_protocol_networking_offload_caps,
1367 : : hcattr, swp_lso);
1368 [ # # ]: 0 : attr->lro_max_msg_sz_mode = MLX5_GET
1369 : : (per_protocol_networking_offload_caps,
1370 : : hcattr, lro_max_msg_sz_mode);
1371 [ # # ]: 0 : for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) {
1372 : 0 : attr->lro_timer_supported_periods[i] =
1373 [ # # ]: 0 : MLX5_GET(per_protocol_networking_offload_caps, hcattr,
1374 : : lro_timer_supported_periods[i]);
1375 : : }
1376 [ # # ]: 0 : attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps,
1377 : : hcattr, lro_min_mss_size);
1378 : 0 : attr->tunnel_stateless_geneve_rx =
1379 [ # # ]: 0 : MLX5_GET(per_protocol_networking_offload_caps,
1380 : : hcattr, tunnel_stateless_geneve_rx);
1381 : 0 : attr->geneve_max_opt_len =
1382 [ # # ]: 0 : MLX5_GET(per_protocol_networking_offload_caps,
1383 : : hcattr, max_geneve_opt_len);
1384 [ # # ]: 0 : attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps,
1385 : : hcattr, wqe_inline_mode);
1386 [ # # ]: 0 : attr->tunnel_stateless_gtp = MLX5_GET
1387 : : (per_protocol_networking_offload_caps,
1388 : : hcattr, tunnel_stateless_gtp);
1389 [ # # ]: 0 : attr->tunnel_stateless_vxlan_gpe_nsh = MLX5_GET
1390 : : (per_protocol_networking_offload_caps,
1391 : : hcattr, tunnel_stateless_vxlan_gpe_nsh);
1392 [ # # ]: 0 : attr->rss_ind_tbl_cap = MLX5_GET
1393 : : (per_protocol_networking_offload_caps,
1394 : : hcattr, rss_ind_tbl_cap);
1395 [ # # ]: 0 : attr->multi_pkt_send_wqe = MLX5_GET
1396 : : (per_protocol_networking_offload_caps,
1397 : : hcattr, multi_pkt_send_wqe);
1398 [ # # ]: 0 : attr->enhanced_multi_pkt_send_wqe = MLX5_GET
1399 : : (per_protocol_networking_offload_caps,
1400 : : hcattr, enhanced_multi_pkt_send_wqe);
1401 [ # # ]: 0 : if (attr->wqe_based_flow_table_sup) {
1402 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1403 : : MLX5_GET_HCA_CAP_OP_MOD_WQE_BASED_FLOW_TABLE |
1404 : : (uint32_t)MLX5_HCA_CAP_OPMOD_GET_CUR);
1405 [ # # ]: 0 : if (!hcattr) {
1406 : 0 : DRV_LOG(DEBUG, "Failed to query WQE Based Flow table capabilities");
1407 : 0 : return rc;
1408 : : }
1409 [ # # ]: 0 : attr->max_header_modify_pattern_length = MLX5_GET(wqe_based_flow_table_cap,
1410 : : hcattr,
1411 : : max_header_modify_pattern_length);
1412 [ # # ]: 0 : attr->fdb_unified_en = MLX5_GET(wqe_based_flow_table_cap,
1413 : : hcattr,
1414 : : fdb_unified_en);
1415 [ # # ]: 0 : attr->fdb_rx_set_flow_tag_stc = MLX5_GET(wqe_based_flow_table_cap,
1416 : : hcattr,
1417 : : fdb_rx_set_flow_tag_stc);
1418 [ # # ]: 0 : stc_action_type_127_64 = MLX5_GET64(wqe_based_flow_table_cap,
1419 : : hcattr,
1420 : : stc_action_type_127_64);
1421 [ # # ]: 0 : if (stc_action_type_127_64 &
1422 : : (1 << (MLX5_IFC_STC_ACTION_TYPE_JUMP_FLOW_TABLE_FDB_RX_BIT_INDEX -
1423 : : MLX5_IFC_STC_ACTION_TYPE_BIT_64_INDEX)))
1424 : 0 : attr->jump_fdb_rx_en = 1;
1425 : : }
1426 : : /* Query HCA attribute for ROCE. */
1427 [ # # ]: 0 : if (attr->roce) {
1428 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1429 : : MLX5_GET_HCA_CAP_OP_MOD_ROCE |
1430 : : (uint32_t)MLX5_HCA_CAP_OPMOD_GET_CUR);
1431 [ # # ]: 0 : if (!hcattr) {
1432 : 0 : DRV_LOG(DEBUG,
1433 : : "Failed to query devx HCA ROCE capabilities");
1434 : 0 : return rc;
1435 : : }
1436 [ # # ]: 0 : attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format);
1437 : : }
1438 [ # # ]: 0 : if (attr->eth_virt) {
1439 : 0 : rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr);
1440 [ # # ]: 0 : if (rc) {
1441 : 0 : attr->eth_virt = 0;
1442 : 0 : goto error;
1443 : : }
1444 : : }
1445 [ # # ]: 0 : if (attr->eswitch_manager) {
1446 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1447 : : MLX5_SET_HCA_CAP_OP_MOD_ESW |
1448 : : (uint32_t)MLX5_HCA_CAP_OPMOD_GET_CUR);
1449 [ # # ]: 0 : if (!hcattr)
1450 : 0 : return rc;
1451 : 0 : attr->esw_mgr_vport_id_valid =
1452 [ # # ]: 0 : MLX5_GET(esw_cap, hcattr,
1453 : : esw_manager_vport_number_valid);
1454 : 0 : attr->esw_mgr_vport_id =
1455 [ # # ]: 0 : MLX5_GET(esw_cap, hcattr, esw_manager_vport_number);
1456 : 0 : mlx5_devx_cmd_query_esw_vport_context(ctx, attr);
1457 : : }
1458 [ # # ]: 0 : if (attr->eswitch_manager) {
1459 : : uint32_t esw_reg, reg_c_8_15;
1460 : :
1461 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1462 : : MLX5_GET_HCA_CAP_OP_MOD_ESW_FLOW_TABLE |
1463 : : (uint32_t)MLX5_HCA_CAP_OPMOD_GET_CUR);
1464 [ # # ]: 0 : if (!hcattr)
1465 : 0 : return rc;
1466 [ # # ]: 0 : esw_reg = MLX5_GET(flow_table_esw_cap, hcattr,
1467 : : ft_header_modify_esw_fdb.metadata_reg_c_x);
1468 [ # # ]: 0 : reg_c_8_15 = MLX5_GET(flow_table_esw_cap, hcattr,
1469 : : ft_field_support_2_esw_fdb.metadata_reg_c_8_15);
1470 : 0 : attr->set_reg_c &= ((0xff & reg_c_8_15) << 8) | esw_reg;
1471 : :
1472 [ # # ]: 0 : attr->esw_sw_owner_v2 = MLX5_GET(flow_table_esw_cap, hcattr,
1473 : : flow_table_properties_nic_esw_fdb.sw_owner_v2);
1474 [ # # ]: 0 : if (!attr->esw_sw_owner_v2)
1475 [ # # ]: 0 : attr->esw_sw_owner = MLX5_GET(flow_table_esw_cap, hcattr,
1476 : : flow_table_properties_nic_esw_fdb.sw_owner);
1477 : : }
1478 : : return 0;
1479 : : error:
1480 : 0 : rc = (rc > 0) ? -rc : rc;
1481 : 0 : return rc;
1482 : : }
1483 : :
1484 : : /**
1485 : : * Query TIS transport domain from QP verbs object using DevX API.
1486 : : *
1487 : : * @param[in] qp
1488 : : * Pointer to verbs QP returned by ibv_create_qp .
1489 : : * @param[in] tis_num
1490 : : * TIS number of TIS to query.
1491 : : * @param[out] tis_td
1492 : : * Pointer to TIS transport domain variable, to be set by the routine.
1493 : : *
1494 : : * @return
1495 : : * 0 on success, a negative value otherwise.
1496 : : */
1497 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_qp_query_tis_td)
1498 : : int
1499 : 0 : mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num,
1500 : : uint32_t *tis_td)
1501 : : {
1502 : : #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1503 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0};
1504 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0};
1505 : : int rc;
1506 : : void *tis_ctx;
1507 : :
1508 : 0 : MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS);
1509 : 0 : MLX5_SET(query_tis_in, in, tisn, tis_num);
1510 : 0 : rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out));
1511 [ # # ]: 0 : if (rc) {
1512 : 0 : DRV_LOG(ERR, "Failed to query QP using DevX");
1513 : 0 : return -rc;
1514 : : };
1515 : : tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context);
1516 [ # # ]: 0 : *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain);
1517 : 0 : return 0;
1518 : : #else
1519 : : (void)qp;
1520 : : (void)tis_num;
1521 : : (void)tis_td;
1522 : : return -ENOTSUP;
1523 : : #endif
1524 : : }
1525 : :
1526 : : /**
1527 : : * Fill WQ data for DevX API command.
1528 : : * Utility function for use when creating DevX objects containing a WQ.
1529 : : *
1530 : : * @param[in] wq_ctx
1531 : : * Pointer to WQ context to fill with data.
1532 : : * @param [in] wq_attr
1533 : : * Pointer to WQ attributes structure to fill in WQ context.
1534 : : */
1535 : : static void
1536 : 0 : devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr)
1537 : : {
1538 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type);
1539 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature);
1540 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode);
1541 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave);
1542 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge);
1543 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size);
1544 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset);
1545 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm);
1546 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, pd, wq_attr->pd);
1547 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page);
1548 [ # # ]: 0 : MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr);
1549 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter);
1550 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter);
1551 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride);
1552 [ # # ]: 0 : if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT)
1553 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, log_wq_pg_sz,
1554 : : wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT);
1555 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz);
1556 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid);
1557 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid);
1558 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, log_hairpin_num_packets,
1559 : : wq_attr->log_hairpin_num_packets);
1560 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz);
1561 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides,
1562 : : wq_attr->single_wqe_log_num_of_strides);
1563 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en);
1564 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes,
1565 : : wq_attr->single_stride_log_num_of_bytes);
1566 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id);
1567 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id);
1568 [ # # ]: 0 : MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset);
1569 : 0 : }
1570 : :
1571 : : /**
1572 : : * Create RQ using DevX API.
1573 : : *
1574 : : * @param[in] ctx
1575 : : * Context returned from mlx5 open_device() glue function.
1576 : : * @param [in] rq_attr
1577 : : * Pointer to create RQ attributes structure.
1578 : : * @param [in] socket
1579 : : * CPU socket ID for allocations.
1580 : : *
1581 : : * @return
1582 : : * The DevX object created, NULL otherwise and rte_errno is set.
1583 : : */
1584 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_rq)
1585 : : struct mlx5_devx_obj *
1586 : 0 : mlx5_devx_cmd_create_rq(void *ctx,
1587 : : struct mlx5_devx_create_rq_attr *rq_attr,
1588 : : int socket)
1589 : : {
1590 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0};
1591 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0};
1592 : : void *rq_ctx, *wq_ctx;
1593 : : struct mlx5_devx_wq_attr *wq_attr;
1594 : : struct mlx5_devx_obj *rq = NULL;
1595 : :
1596 [ # # # # ]: 0 : rq = mlx5_malloc_numa_tolerant(MLX5_MEM_ZERO, sizeof(*rq), 0, socket);
1597 [ # # ]: 0 : if (!rq) {
1598 : 0 : DRV_LOG(ERR, "Failed to allocate RQ data");
1599 : 0 : rte_errno = ENOMEM;
1600 : 0 : return NULL;
1601 : : }
1602 [ # # ]: 0 : MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ);
1603 : : rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx);
1604 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky);
1605 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en);
1606 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
1607 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
1608 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type);
1609 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
1610 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en);
1611 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin);
1612 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, hairpin_data_buffer_type, rq_attr->hairpin_data_buffer_type);
1613 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index);
1614 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn);
1615 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
1616 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn);
1617 [ # # ]: 0 : MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format);
1618 : : wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
1619 : 0 : wq_attr = &rq_attr->wq_attr;
1620 : 0 : devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1621 : 0 : rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1622 : : out, sizeof(out));
1623 [ # # ]: 0 : if (!rq->obj) {
1624 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create RQ", NULL, 0);
1625 : 0 : mlx5_free(rq);
1626 : 0 : return NULL;
1627 : : }
1628 [ # # ]: 0 : rq->id = MLX5_GET(create_rq_out, out, rqn);
1629 : 0 : return rq;
1630 : : }
1631 : :
1632 : : /**
1633 : : * Modify RQ using DevX API.
1634 : : *
1635 : : * @param[in] rq
1636 : : * Pointer to RQ object structure.
1637 : : * @param [in] rq_attr
1638 : : * Pointer to modify RQ attributes structure.
1639 : : *
1640 : : * @return
1641 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
1642 : : */
1643 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_modify_rq)
1644 : : int
1645 : 0 : mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
1646 : : struct mlx5_devx_modify_rq_attr *rq_attr)
1647 : : {
1648 : 0 : uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0};
1649 : 0 : uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0};
1650 : : void *rq_ctx, *wq_ctx;
1651 : : int ret;
1652 : :
1653 : 0 : MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ);
1654 : 0 : MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state);
1655 [ # # ]: 0 : MLX5_SET(modify_rq_in, in, rqn, rq->id);
1656 [ # # ]: 0 : MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask);
1657 : : rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1658 : 0 : MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
1659 [ # # ]: 0 : if (rq_attr->modify_bitmask &
1660 : : MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS)
1661 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
1662 [ # # ]: 0 : if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD)
1663 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
1664 [ # # ]: 0 : if (rq_attr->modify_bitmask &
1665 : : MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID)
1666 : 0 : MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
1667 : 0 : MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq);
1668 : 0 : MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca);
1669 [ # # ]: 0 : if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) {
1670 : : wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
1671 : 0 : MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm);
1672 : : }
1673 : 0 : ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in),
1674 : : out, sizeof(out));
1675 [ # # # # : 0 : if (ret || MLX5_FW_STATUS(out)) {
# # # # ]
1676 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "RQ modify", "rq_id", rq->id);
1677 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(ret);
1678 : : }
1679 : : return 0;
1680 : : }
1681 : :
1682 : : /*
1683 : : * Query RQ using DevX API.
1684 : : *
1685 : : * @param[in] rq_obj
1686 : : * RQ Devx Object
1687 : : * @param[out] out
1688 : : * RQ Query Output
1689 : : * @param[in] outlen
1690 : : * RQ Query Output Length
1691 : : *
1692 : : * @return
1693 : : * 0 if Query successful, else non-zero return value from devx_obj_query API
1694 : : */
1695 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_query_rq)
1696 : : int
1697 : 0 : mlx5_devx_cmd_query_rq(struct mlx5_devx_obj *rq_obj, void *out, size_t outlen)
1698 : : {
1699 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0};
1700 : : int rc;
1701 : :
1702 : 0 : MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ);
1703 : 0 : MLX5_SET(query_rq_in, in, rqn, rq_obj->id);
1704 : 0 : rc = mlx5_glue->devx_obj_query(rq_obj->obj, in, sizeof(in), out, outlen);
1705 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
1706 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "RQ query", "rq_id", rq_obj->id);
1707 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
1708 : : }
1709 : : return 0;
1710 : : }
1711 : :
1712 : : /**
1713 : : * Create RMP using DevX API.
1714 : : *
1715 : : * @param[in] ctx
1716 : : * Context returned from mlx5 open_device() glue function.
1717 : : * @param [in] rmp_attr
1718 : : * Pointer to create RMP attributes structure.
1719 : : * @param [in] socket
1720 : : * CPU socket ID for allocations.
1721 : : *
1722 : : * @return
1723 : : * The DevX object created, NULL otherwise and rte_errno is set.
1724 : : */
1725 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_rmp)
1726 : : struct mlx5_devx_obj *
1727 : 0 : mlx5_devx_cmd_create_rmp(void *ctx,
1728 : : struct mlx5_devx_create_rmp_attr *rmp_attr,
1729 : : int socket)
1730 : : {
1731 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_rmp_in)] = {0};
1732 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_rmp_out)] = {0};
1733 : : void *rmp_ctx, *wq_ctx;
1734 : : struct mlx5_devx_wq_attr *wq_attr;
1735 : : struct mlx5_devx_obj *rmp = NULL;
1736 : :
1737 [ # # # # ]: 0 : rmp = mlx5_malloc_numa_tolerant(MLX5_MEM_ZERO, sizeof(*rmp), 0, socket);
1738 [ # # ]: 0 : if (!rmp) {
1739 : 0 : DRV_LOG(ERR, "Failed to allocate RMP data");
1740 : 0 : rte_errno = ENOMEM;
1741 : 0 : return NULL;
1742 : : }
1743 [ # # ]: 0 : MLX5_SET(create_rmp_in, in, opcode, MLX5_CMD_OP_CREATE_RMP);
1744 : : rmp_ctx = MLX5_ADDR_OF(create_rmp_in, in, ctx);
1745 [ # # ]: 0 : MLX5_SET(rmpc, rmp_ctx, state, rmp_attr->state);
1746 [ # # ]: 0 : MLX5_SET(rmpc, rmp_ctx, basic_cyclic_rcv_wqe,
1747 : : rmp_attr->basic_cyclic_rcv_wqe);
1748 : : wq_ctx = MLX5_ADDR_OF(rmpc, rmp_ctx, wq);
1749 : 0 : wq_attr = &rmp_attr->wq_attr;
1750 : 0 : devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1751 : 0 : rmp->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1752 : : sizeof(out));
1753 [ # # ]: 0 : if (!rmp->obj) {
1754 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create RMP", NULL, 0);
1755 : 0 : mlx5_free(rmp);
1756 : 0 : return NULL;
1757 : : }
1758 [ # # ]: 0 : rmp->id = MLX5_GET(create_rmp_out, out, rmpn);
1759 : 0 : return rmp;
1760 : : }
1761 : :
1762 : : /*
1763 : : * Create TIR using DevX API.
1764 : : *
1765 : : * @param[in] ctx
1766 : : * Context returned from mlx5 open_device() glue function.
1767 : : * @param [in] tir_attr
1768 : : * Pointer to TIR attributes structure.
1769 : : *
1770 : : * @return
1771 : : * The DevX object created, NULL otherwise and rte_errno is set.
1772 : : */
1773 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_tir)
1774 : : struct mlx5_devx_obj *
1775 : 0 : mlx5_devx_cmd_create_tir(void *ctx,
1776 : : struct mlx5_devx_tir_attr *tir_attr)
1777 : : {
1778 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
1779 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0};
1780 : : void *tir_ctx, *outer, *inner, *rss_key;
1781 : : struct mlx5_devx_obj *tir = NULL;
1782 : :
1783 : 0 : tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY);
1784 [ # # ]: 0 : if (!tir) {
1785 : 0 : DRV_LOG(ERR, "Failed to allocate TIR data");
1786 : 0 : rte_errno = ENOMEM;
1787 : 0 : return NULL;
1788 : : }
1789 [ # # ]: 0 : MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1790 : : tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx);
1791 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type);
1792 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1793 : : tir_attr->lro_timeout_period_usecs);
1794 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask);
1795 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz);
1796 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn);
1797 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric);
1798 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, tunneled_offload_en,
1799 : : tir_attr->tunneled_offload_en);
1800 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table);
1801 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1802 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1803 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain);
1804 : : rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key);
1805 [ # # ]: 0 : memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN);
1806 : : outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer);
1807 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1808 : : tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1809 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1810 : : tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1811 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, outer, selected_fields,
1812 : : tir_attr->rx_hash_field_selector_outer.selected_fields);
1813 : : inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner);
1814 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1815 : : tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1816 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1817 : : tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1818 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, inner, selected_fields,
1819 : : tir_attr->rx_hash_field_selector_inner.selected_fields);
1820 : 0 : tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1821 : : out, sizeof(out));
1822 [ # # ]: 0 : if (!tir->obj) {
1823 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create TIR", NULL, 0);
1824 : 0 : mlx5_free(tir);
1825 : 0 : return NULL;
1826 : : }
1827 [ # # ]: 0 : tir->id = MLX5_GET(create_tir_out, out, tirn);
1828 : 0 : return tir;
1829 : : }
1830 : :
1831 : : /**
1832 : : * Modify TIR using DevX API.
1833 : : *
1834 : : * @param[in] tir
1835 : : * Pointer to TIR DevX object structure.
1836 : : * @param [in] modify_tir_attr
1837 : : * Pointer to TIR modification attributes structure.
1838 : : *
1839 : : * @return
1840 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
1841 : : */
1842 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_modify_tir)
1843 : : int
1844 : 0 : mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir,
1845 : : struct mlx5_devx_modify_tir_attr *modify_tir_attr)
1846 : : {
1847 : : struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir;
1848 : 0 : uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0};
1849 : 0 : uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0};
1850 : : void *tir_ctx;
1851 : : int ret;
1852 : :
1853 : 0 : MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR);
1854 : 0 : MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn);
1855 [ # # ]: 0 : MLX5_SET64(modify_tir_in, in, modify_bitmask,
1856 : : modify_tir_attr->modify_bitmask);
1857 : : tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1858 [ # # ]: 0 : if (modify_tir_attr->modify_bitmask &
1859 : : MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) {
1860 : 0 : MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1861 : : tir_attr->lro_timeout_period_usecs);
1862 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, lro_enable_mask,
1863 : : tir_attr->lro_enable_mask);
1864 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, lro_max_msg_sz,
1865 : : tir_attr->lro_max_msg_sz);
1866 : : }
1867 [ # # ]: 0 : if (modify_tir_attr->modify_bitmask &
1868 : : MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE)
1869 : 0 : MLX5_SET(tirc, tir_ctx, indirect_table,
1870 : : tir_attr->indirect_table);
1871 [ # # ]: 0 : if (modify_tir_attr->modify_bitmask &
1872 : : MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) {
1873 : : int i;
1874 : : void *outer, *inner;
1875 : :
1876 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, rx_hash_symmetric,
1877 : : tir_attr->rx_hash_symmetric);
1878 : 0 : MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1879 [ # # ]: 0 : for (i = 0; i < 10; i++) {
1880 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i],
1881 : : tir_attr->rx_hash_toeplitz_key[i]);
1882 : : }
1883 : : outer = MLX5_ADDR_OF(tirc, tir_ctx,
1884 : : rx_hash_field_selector_outer);
1885 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1886 : : tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1887 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1888 : : tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1889 [ # # ]: 0 : MLX5_SET
1890 : : (rx_hash_field_select, outer, selected_fields,
1891 : : tir_attr->rx_hash_field_selector_outer.selected_fields);
1892 : : inner = MLX5_ADDR_OF(tirc, tir_ctx,
1893 : : rx_hash_field_selector_inner);
1894 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1895 : : tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1896 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1897 : : tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1898 [ # # ]: 0 : MLX5_SET
1899 : : (rx_hash_field_select, inner, selected_fields,
1900 : : tir_attr->rx_hash_field_selector_inner.selected_fields);
1901 : : }
1902 [ # # ]: 0 : if (modify_tir_attr->modify_bitmask &
1903 : : MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) {
1904 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1905 : : }
1906 : 0 : ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in),
1907 : : out, sizeof(out));
1908 [ # # ]: 0 : if (ret) {
1909 : 0 : DRV_LOG(ERR, "Failed to modify TIR using DevX");
1910 : 0 : rte_errno = errno;
1911 : 0 : return -errno;
1912 : : }
1913 : : return ret;
1914 : : }
1915 : :
1916 : : /**
1917 : : * Create RQT using DevX API.
1918 : : *
1919 : : * @param[in] ctx
1920 : : * Context returned from mlx5 open_device() glue function.
1921 : : * @param [in] rqt_attr
1922 : : * Pointer to RQT attributes structure.
1923 : : *
1924 : : * @return
1925 : : * The DevX object created, NULL otherwise and rte_errno is set.
1926 : : */
1927 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_rqt)
1928 : : struct mlx5_devx_obj *
1929 : 0 : mlx5_devx_cmd_create_rqt(void *ctx,
1930 : : struct mlx5_devx_rqt_attr *rqt_attr)
1931 : : {
1932 : : uint32_t *in = NULL;
1933 : 0 : uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) +
1934 : 0 : rqt_attr->rqt_actual_size * sizeof(uint32_t);
1935 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
1936 : : void *rqt_ctx;
1937 : : struct mlx5_devx_obj *rqt = NULL;
1938 : : unsigned int i;
1939 : :
1940 : 0 : in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1941 [ # # ]: 0 : if (!in) {
1942 : 0 : DRV_LOG(ERR, "Failed to allocate RQT IN data");
1943 : 0 : rte_errno = ENOMEM;
1944 : 0 : return NULL;
1945 : : }
1946 : 0 : rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY);
1947 [ # # ]: 0 : if (!rqt) {
1948 : 0 : DRV_LOG(ERR, "Failed to allocate RQT data");
1949 : 0 : rte_errno = ENOMEM;
1950 : 0 : mlx5_free(in);
1951 : 0 : return NULL;
1952 : : }
1953 [ # # ]: 0 : MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
1954 : 0 : rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1955 [ # # ]: 0 : MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1956 [ # # ]: 0 : MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
1957 [ # # ]: 0 : MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1958 [ # # ]: 0 : for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1959 [ # # ]: 0 : MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1960 : 0 : rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out));
1961 : 0 : mlx5_free(in);
1962 [ # # ]: 0 : if (!rqt->obj) {
1963 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create RQT", NULL, 0);
1964 : 0 : mlx5_free(rqt);
1965 : 0 : return NULL;
1966 : : }
1967 [ # # ]: 0 : rqt->id = MLX5_GET(create_rqt_out, out, rqtn);
1968 : 0 : return rqt;
1969 : : }
1970 : :
1971 : : /**
1972 : : * Modify RQT using DevX API.
1973 : : *
1974 : : * @param[in] rqt
1975 : : * Pointer to RQT DevX object structure.
1976 : : * @param [in] rqt_attr
1977 : : * Pointer to RQT attributes structure.
1978 : : *
1979 : : * @return
1980 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
1981 : : */
1982 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_modify_rqt)
1983 : : int
1984 : 0 : mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
1985 : : struct mlx5_devx_rqt_attr *rqt_attr)
1986 : : {
1987 : 0 : uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) +
1988 : 0 : rqt_attr->rqt_actual_size * sizeof(uint32_t);
1989 : 0 : uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0};
1990 : 0 : uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1991 : : void *rqt_ctx;
1992 : : unsigned int i;
1993 : : int ret;
1994 : :
1995 [ # # ]: 0 : if (!in) {
1996 : 0 : DRV_LOG(ERR, "Failed to allocate RQT modify IN data.");
1997 : 0 : rte_errno = ENOMEM;
1998 : 0 : return -ENOMEM;
1999 : : }
2000 [ # # ]: 0 : MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT);
2001 [ # # ]: 0 : MLX5_SET(modify_rqt_in, in, rqtn, rqt->id);
2002 : 0 : MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1);
2003 : 0 : rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context);
2004 [ # # ]: 0 : MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
2005 [ # # ]: 0 : MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
2006 [ # # ]: 0 : for (i = 0; i < rqt_attr->rqt_actual_size; i++)
2007 [ # # ]: 0 : MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
2008 : 0 : ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out));
2009 : 0 : mlx5_free(in);
2010 [ # # ]: 0 : if (ret) {
2011 : 0 : DRV_LOG(ERR, "Failed to modify RQT using DevX.");
2012 : 0 : rte_errno = errno;
2013 : 0 : return -rte_errno;
2014 : : }
2015 : : return ret;
2016 : : }
2017 : :
2018 : : /**
2019 : : * Create SQ using DevX API.
2020 : : *
2021 : : * @param[in] ctx
2022 : : * Context returned from mlx5 open_device() glue function.
2023 : : * @param [in] sq_attr
2024 : : * Pointer to SQ attributes structure.
2025 : : * @param [in] socket
2026 : : * CPU socket ID for allocations.
2027 : : *
2028 : : * @return
2029 : : * The DevX object created, NULL otherwise and rte_errno is set.
2030 : : **/
2031 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_sq)
2032 : : struct mlx5_devx_obj *
2033 : 0 : mlx5_devx_cmd_create_sq(void *ctx,
2034 : : struct mlx5_devx_create_sq_attr *sq_attr)
2035 : : {
2036 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0};
2037 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0};
2038 : : void *sq_ctx;
2039 : : void *wq_ctx;
2040 : : struct mlx5_devx_wq_attr *wq_attr;
2041 : : struct mlx5_devx_obj *sq = NULL;
2042 : :
2043 : 0 : sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY);
2044 [ # # ]: 0 : if (!sq) {
2045 : 0 : DRV_LOG(ERR, "Failed to allocate SQ data");
2046 : 0 : rte_errno = ENOMEM;
2047 : 0 : return NULL;
2048 : : }
2049 [ # # ]: 0 : MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ);
2050 : : sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx);
2051 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky);
2052 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master);
2053 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre);
2054 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en);
2055 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe,
2056 : : sq_attr->allow_multi_pkt_send_wqe);
2057 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode,
2058 : : sq_attr->min_wqe_inline_mode);
2059 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
2060 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr);
2061 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp);
2062 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin);
2063 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire);
2064 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq);
2065 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, hairpin_wq_buffer_type, sq_attr->hairpin_wq_buffer_type);
2066 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index);
2067 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn);
2068 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index,
2069 : : sq_attr->packet_pacing_rate_limit_index);
2070 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz);
2071 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num);
2072 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format);
2073 : : wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq);
2074 : 0 : wq_attr = &sq_attr->wq_attr;
2075 : 0 : devx_cmd_fill_wq_data(wq_ctx, wq_attr);
2076 : 0 : sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2077 : : out, sizeof(out));
2078 [ # # ]: 0 : if (!sq->obj) {
2079 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create SQ", NULL, 0);
2080 : 0 : mlx5_free(sq);
2081 : 0 : return NULL;
2082 : : }
2083 [ # # ]: 0 : sq->id = MLX5_GET(create_sq_out, out, sqn);
2084 : 0 : return sq;
2085 : : }
2086 : :
2087 : : /**
2088 : : * Modify SQ using DevX API.
2089 : : *
2090 : : * @param[in] sq
2091 : : * Pointer to SQ object structure.
2092 : : * @param [in] sq_attr
2093 : : * Pointer to SQ attributes structure.
2094 : : *
2095 : : * @return
2096 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
2097 : : */
2098 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_modify_sq)
2099 : : int
2100 : 0 : mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
2101 : : struct mlx5_devx_modify_sq_attr *sq_attr)
2102 : : {
2103 : 0 : uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0};
2104 : 0 : uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0};
2105 : : void *sq_ctx;
2106 : : int ret;
2107 : :
2108 : 0 : MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ);
2109 : 0 : MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state);
2110 [ # # ]: 0 : MLX5_SET(modify_sq_in, in, sqn, sq->id);
2111 : : sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2112 : 0 : MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
2113 : 0 : MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq);
2114 : 0 : MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca);
2115 : 0 : ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in),
2116 : : out, sizeof(out));
2117 [ # # # # : 0 : if (ret || MLX5_FW_STATUS(out)) {
# # # # ]
2118 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "SQ modify", "sq_id", sq->id);
2119 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(ret);
2120 : : }
2121 : : return 0;
2122 : : }
2123 : :
2124 : : /*
2125 : : * Query SQ using DevX API.
2126 : : *
2127 : : * @param[in] sq_obj
2128 : : * SQ Devx Object
2129 : : * @param[out] out
2130 : : * SQ Query Output
2131 : : * @param[in] outlen
2132 : : * SQ Query Output Length
2133 : : *
2134 : : * @return
2135 : : * 0 if Query successful, else non-zero return value from devx_obj_query API
2136 : : */
2137 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_query_sq)
2138 : : int
2139 : 0 : mlx5_devx_cmd_query_sq(struct mlx5_devx_obj *sq_obj, void *out, size_t outlen)
2140 : : {
2141 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_sq_in)] = {0};
2142 : : int rc;
2143 : :
2144 : 0 : MLX5_SET(query_sq_in, in, opcode, MLX5_CMD_OP_QUERY_SQ);
2145 : 0 : MLX5_SET(query_sq_in, in, sqn, sq_obj->id);
2146 : 0 : rc = mlx5_glue->devx_obj_query(sq_obj->obj, in, sizeof(in), out, outlen);
2147 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
2148 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "SQ query", "sq_id", sq_obj->id);
2149 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
2150 : : }
2151 : : return 0;
2152 : : }
2153 : :
2154 : : /**
2155 : : * Create TIS using DevX API.
2156 : : *
2157 : : * @param[in] ctx
2158 : : * Context returned from mlx5 open_device() glue function.
2159 : : * @param [in] tis_attr
2160 : : * Pointer to TIS attributes structure.
2161 : : *
2162 : : * @return
2163 : : * The DevX object created, NULL otherwise and rte_errno is set.
2164 : : */
2165 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_tis)
2166 : : struct mlx5_devx_obj *
2167 : 0 : mlx5_devx_cmd_create_tis(void *ctx,
2168 : : struct mlx5_devx_tis_attr *tis_attr)
2169 : : {
2170 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2171 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0};
2172 : : struct mlx5_devx_obj *tis = NULL;
2173 : : void *tis_ctx;
2174 : :
2175 : 0 : tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY);
2176 [ # # ]: 0 : if (!tis) {
2177 : 0 : DRV_LOG(ERR, "Failed to allocate TIS object");
2178 : 0 : rte_errno = ENOMEM;
2179 : 0 : return NULL;
2180 : : }
2181 [ # # ]: 0 : MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS);
2182 : : tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx);
2183 [ # # ]: 0 : MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,
2184 : : tis_attr->strict_lag_tx_port_affinity);
2185 [ # # ]: 0 : MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity,
2186 : : tis_attr->lag_tx_port_affinity);
2187 [ # # ]: 0 : MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio);
2188 [ # # ]: 0 : MLX5_SET(tisc, tis_ctx, transport_domain,
2189 : : tis_attr->transport_domain);
2190 : 0 : tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2191 : : out, sizeof(out));
2192 [ # # ]: 0 : if (!tis->obj) {
2193 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create TIS", NULL, 0);
2194 : 0 : mlx5_free(tis);
2195 : 0 : return NULL;
2196 : : }
2197 [ # # ]: 0 : tis->id = MLX5_GET(create_tis_out, out, tisn);
2198 : 0 : return tis;
2199 : : }
2200 : :
2201 : : /**
2202 : : * Create transport domain using DevX API.
2203 : : *
2204 : : * @param[in] ctx
2205 : : * Context returned from mlx5 open_device() glue function.
2206 : : * @return
2207 : : * The DevX object created, NULL otherwise and rte_errno is set.
2208 : : */
2209 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_td)
2210 : : struct mlx5_devx_obj *
2211 : 0 : mlx5_devx_cmd_create_td(void *ctx)
2212 : : {
2213 : 0 : uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0};
2214 : 0 : uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0};
2215 : : struct mlx5_devx_obj *td = NULL;
2216 : :
2217 : 0 : td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY);
2218 [ # # ]: 0 : if (!td) {
2219 : 0 : DRV_LOG(ERR, "Failed to allocate TD object");
2220 : 0 : rte_errno = ENOMEM;
2221 : 0 : return NULL;
2222 : : }
2223 [ # # ]: 0 : MLX5_SET(alloc_transport_domain_in, in, opcode,
2224 : : MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN);
2225 : 0 : td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2226 : : out, sizeof(out));
2227 [ # # ]: 0 : if (!td->obj) {
2228 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create TIS", NULL, 0);
2229 : 0 : mlx5_free(td);
2230 : 0 : return NULL;
2231 : : }
2232 [ # # ]: 0 : td->id = MLX5_GET(alloc_transport_domain_out, out,
2233 : : transport_domain);
2234 : 0 : return td;
2235 : : }
2236 : :
2237 : : /**
2238 : : * Dump all flows to file.
2239 : : *
2240 : : * @param[in] fdb_domain
2241 : : * FDB domain.
2242 : : * @param[in] rx_domain
2243 : : * RX domain.
2244 : : * @param[in] tx_domain
2245 : : * TX domain.
2246 : : * @param[out] file
2247 : : * Pointer to file stream.
2248 : : *
2249 : : * @return
2250 : : * 0 on success, a negative value otherwise.
2251 : : */
2252 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_flow_dump)
2253 : : int
2254 : 0 : mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused,
2255 : : void *rx_domain __rte_unused,
2256 : : void *tx_domain __rte_unused, FILE *file __rte_unused)
2257 : : {
2258 : : int ret = 0;
2259 : :
2260 : : #ifdef HAVE_MLX5_DR_FLOW_DUMP
2261 [ # # ]: 0 : if (fdb_domain) {
2262 : 0 : ret = mlx5_glue->dr_dump_domain(file, fdb_domain);
2263 [ # # ]: 0 : if (ret)
2264 : : return ret;
2265 : : }
2266 : : MLX5_ASSERT(rx_domain);
2267 : 0 : ret = mlx5_glue->dr_dump_domain(file, rx_domain);
2268 [ # # ]: 0 : if (ret)
2269 : : return ret;
2270 : : MLX5_ASSERT(tx_domain);
2271 : 0 : ret = mlx5_glue->dr_dump_domain(file, tx_domain);
2272 : : #else
2273 : : ret = ENOTSUP;
2274 : : #endif
2275 : 0 : return -ret;
2276 : : }
2277 : :
2278 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_flow_single_dump)
2279 : : int
2280 : 0 : mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused,
2281 : : FILE *file __rte_unused)
2282 : : {
2283 : : int ret = 0;
2284 : : #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE
2285 [ # # ]: 0 : if (rule_info)
2286 : 0 : ret = mlx5_glue->dr_dump_rule(file, rule_info);
2287 : : #else
2288 : : ret = ENOTSUP;
2289 : : #endif
2290 : 0 : return -ret;
2291 : : }
2292 : :
2293 : : /*
2294 : : * Create CQ using DevX API.
2295 : : *
2296 : : * @param[in] ctx
2297 : : * Context returned from mlx5 open_device() glue function.
2298 : : * @param [in] attr
2299 : : * Pointer to CQ attributes structure.
2300 : : *
2301 : : * @return
2302 : : * The DevX object created, NULL otherwise and rte_errno is set.
2303 : : */
2304 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_cq)
2305 : : struct mlx5_devx_obj *
2306 : 0 : mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr)
2307 : : {
2308 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0};
2309 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0};
2310 : 0 : struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO,
2311 : : sizeof(*cq_obj),
2312 : : 0, SOCKET_ID_ANY);
2313 : : void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context);
2314 : :
2315 [ # # ]: 0 : if (!cq_obj) {
2316 : 0 : DRV_LOG(ERR, "Failed to allocate CQ object memory.");
2317 : 0 : rte_errno = ENOMEM;
2318 : 0 : return NULL;
2319 : : }
2320 [ # # ]: 0 : MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ);
2321 [ # # ]: 0 : if (attr->db_umem_valid) {
2322 [ # # ]: 0 : MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid);
2323 [ # # ]: 0 : MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id);
2324 [ # # ]: 0 : MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset);
2325 : : } else {
2326 [ # # ]: 0 : MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr);
2327 : : }
2328 [ # # ]: 0 : MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ?
2329 : : MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B);
2330 [ # # ]: 0 : MLX5_SET(cqc, cqctx, cc, attr->use_first_only);
2331 [ # # ]: 0 : MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore);
2332 [ # # ]: 0 : MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size);
2333 [ # # ]: 0 : if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)
2334 [ # # ]: 0 : MLX5_SET(cqc, cqctx, log_page_size,
2335 : : attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT);
2336 [ # # ]: 0 : MLX5_SET(cqc, cqctx, c_eqn, attr->eqn);
2337 [ # # ]: 0 : MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id);
2338 [ # # ]: 0 : MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en);
2339 [ # # ]: 0 : MLX5_SET(cqc, cqctx, cqe_comp_layout, !!attr->cqe_comp_layout);
2340 [ # # ]: 0 : MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format);
2341 [ # # ]: 0 : MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext,
2342 : : attr->mini_cqe_res_format_ext);
2343 [ # # ]: 0 : if (attr->q_umem_valid) {
2344 [ # # ]: 0 : MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid);
2345 [ # # ]: 0 : MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id);
2346 [ # # ]: 0 : MLX5_SET64(create_cq_in, in, cq_umem_offset,
2347 : : attr->q_umem_offset);
2348 : : }
2349 : 0 : cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2350 : : sizeof(out));
2351 [ # # ]: 0 : if (!cq_obj->obj) {
2352 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create CQ", NULL, 0);
2353 : 0 : mlx5_free(cq_obj);
2354 : 0 : return NULL;
2355 : : }
2356 [ # # ]: 0 : cq_obj->id = MLX5_GET(create_cq_out, out, cqn);
2357 : 0 : return cq_obj;
2358 : : }
2359 : :
2360 : : /*
2361 : : * Query CQ using DevX API.
2362 : : *
2363 : : * @param[in] cq_obj
2364 : : * CQ Devx Object
2365 : : * @param[out] out
2366 : : * CQ Query Output
2367 : : * @param[in] outlen
2368 : : * CQ Query Output Length
2369 : : *
2370 : : * @return
2371 : : * 0 if Query successful, else non-zero return value from devx_obj_query API
2372 : : */
2373 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_query_cq)
2374 : : int
2375 : 0 : mlx5_devx_cmd_query_cq(struct mlx5_devx_obj *cq_obj, void *out, size_t outlen)
2376 : : {
2377 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_cq_in)] = {0};
2378 : : int rc;
2379 : :
2380 : 0 : MLX5_SET(query_cq_in, in, opcode, MLX5_CMD_OP_QUERY_CQ);
2381 : 0 : MLX5_SET(query_cq_in, in, cqn, cq_obj->id);
2382 : 0 : rc = mlx5_glue->devx_obj_query(cq_obj->obj, in, sizeof(in), out, outlen);
2383 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
2384 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "CQ query", "cq_id", cq_obj->id);
2385 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
2386 : : }
2387 : : return 0;
2388 : : }
2389 : :
2390 : : /**
2391 : : * Create VIRTQ using DevX API.
2392 : : *
2393 : : * @param[in] ctx
2394 : : * Context returned from mlx5 open_device() glue function.
2395 : : * @param [in] attr
2396 : : * Pointer to VIRTQ attributes structure.
2397 : : *
2398 : : * @return
2399 : : * The DevX object created, NULL otherwise and rte_errno is set.
2400 : : */
2401 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_virtq)
2402 : : struct mlx5_devx_obj *
2403 : 0 : mlx5_devx_cmd_create_virtq(void *ctx,
2404 : : struct mlx5_devx_virtq_attr *attr)
2405 : : {
2406 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
2407 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2408 : 0 : struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO,
2409 : : sizeof(*virtq_obj),
2410 : : 0, SOCKET_ID_ANY);
2411 : : void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
2412 : : void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
2413 : : void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
2414 : :
2415 [ # # ]: 0 : if (!virtq_obj) {
2416 : 0 : DRV_LOG(ERR, "Failed to allocate virtq data.");
2417 : 0 : rte_errno = ENOMEM;
2418 : 0 : return NULL;
2419 : : }
2420 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2421 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2422 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2423 : : MLX5_GENERAL_OBJ_TYPE_VIRTQ);
2424 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, hw_available_index,
2425 : : attr->hw_available_index);
2426 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index);
2427 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4);
2428 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6);
2429 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum);
2430 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum);
2431 [ # # ]: 0 : MLX5_SET16(virtio_q, virtctx, virtio_version_1_0,
2432 : : attr->virtio_version_1_0);
2433 [ # # ]: 0 : MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode);
2434 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id);
2435 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr);
2436 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr);
2437 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr);
2438 [ # # ]: 0 : MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
2439 [ # # ]: 0 : MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size);
2440 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey);
2441 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id);
2442 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size);
2443 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset);
2444 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id);
2445 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size);
2446 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset);
2447 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id);
2448 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size);
2449 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset);
2450 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id);
2451 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, pd, attr->pd);
2452 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode);
2453 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us);
2454 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp);
2455 [ # # ]: 0 : MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id);
2456 : 0 : virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2457 : : sizeof(out));
2458 [ # # ]: 0 : if (!virtq_obj->obj) {
2459 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create VIRTQ", NULL, 0);
2460 : 0 : mlx5_free(virtq_obj);
2461 : 0 : return NULL;
2462 : : }
2463 [ # # ]: 0 : virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2464 : 0 : return virtq_obj;
2465 : : }
2466 : :
2467 : : /**
2468 : : * Modify VIRTQ using DevX API.
2469 : : *
2470 : : * @param[in] virtq_obj
2471 : : * Pointer to virtq object structure.
2472 : : * @param [in] attr
2473 : : * Pointer to modify virtq attributes structure.
2474 : : *
2475 : : * @return
2476 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
2477 : : */
2478 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_modify_virtq)
2479 : : int
2480 : 0 : mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,
2481 : : struct mlx5_devx_virtq_attr *attr)
2482 : : {
2483 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
2484 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2485 : : void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
2486 : : void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
2487 : : void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
2488 : : int ret;
2489 : :
2490 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2491 : : MLX5_CMD_OP_MODIFY_GENERAL_OBJECT);
2492 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2493 : : MLX5_GENERAL_OBJ_TYPE_VIRTQ);
2494 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
2495 [ # # ]: 0 : MLX5_SET64(virtio_net_q, virtq, modify_field_select,
2496 : : attr->mod_fields_bitmap);
2497 : 0 : MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
2498 [ # # ]: 0 : if (!attr->mod_fields_bitmap) {
2499 : 0 : DRV_LOG(ERR, "Failed to modify VIRTQ for no type set.");
2500 : 0 : rte_errno = EINVAL;
2501 : 0 : return -rte_errno;
2502 : : }
2503 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_STATE)
2504 : 0 : MLX5_SET16(virtio_net_q, virtq, state, attr->state);
2505 [ # # ]: 0 : if (attr->mod_fields_bitmap &
2506 : : MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS) {
2507 : 0 : MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey,
2508 : : attr->dirty_bitmap_mkey);
2509 [ # # ]: 0 : MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr,
2510 : : attr->dirty_bitmap_addr);
2511 : 0 : MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size,
2512 : : attr->dirty_bitmap_size);
2513 : : }
2514 [ # # ]: 0 : if (attr->mod_fields_bitmap &
2515 : : MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE)
2516 [ # # ]: 0 : MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable,
2517 : : attr->dirty_bitmap_dump_enable);
2518 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_QUEUE_PERIOD) {
2519 : 0 : MLX5_SET(virtio_q, virtctx, queue_period_mode,
2520 : : attr->hw_latency_mode);
2521 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, queue_period_us,
2522 : : attr->hw_max_latency_us);
2523 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, queue_max_count,
2524 : : attr->hw_max_pending_comp);
2525 : : }
2526 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_ADDR) {
2527 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr);
2528 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr);
2529 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, available_addr,
2530 : : attr->available_addr);
2531 : : }
2532 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_AVAILABLE_INDEX)
2533 : 0 : MLX5_SET16(virtio_net_q, virtq, hw_available_index,
2534 : : attr->hw_available_index);
2535 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_USED_INDEX)
2536 : 0 : MLX5_SET16(virtio_net_q, virtq, hw_used_index,
2537 : : attr->hw_used_index);
2538 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_TYPE)
2539 : 0 : MLX5_SET16(virtio_q, virtctx, virtio_q_type, attr->q_type);
2540 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_VERSION_1_0)
2541 : 0 : MLX5_SET16(virtio_q, virtctx, virtio_version_1_0,
2542 : : attr->virtio_version_1_0);
2543 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_MKEY)
2544 : 0 : MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey);
2545 [ # # ]: 0 : if (attr->mod_fields_bitmap &
2546 : : MLX5_VIRTQ_MODIFY_TYPE_QUEUE_FEATURE_BIT_MASK) {
2547 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4);
2548 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6);
2549 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum);
2550 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum);
2551 : : }
2552 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_EVENT_MODE) {
2553 [ # # ]: 0 : MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode);
2554 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id);
2555 : : }
2556 : 0 : ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in),
2557 : : out, sizeof(out));
2558 [ # # ]: 0 : if (ret) {
2559 : 0 : DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
2560 : 0 : rte_errno = errno;
2561 : 0 : return -rte_errno;
2562 : : }
2563 : : return ret;
2564 : : }
2565 : :
2566 : : /**
2567 : : * Query VIRTQ using DevX API.
2568 : : *
2569 : : * @param[in] virtq_obj
2570 : : * Pointer to virtq object structure.
2571 : : * @param [in/out] attr
2572 : : * Pointer to virtq attributes structure.
2573 : : *
2574 : : * @return
2575 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
2576 : : */
2577 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_query_virtq)
2578 : : int
2579 : 0 : mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,
2580 : : struct mlx5_devx_virtq_attr *attr)
2581 : : {
2582 : 0 : uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
2583 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0};
2584 : : void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr);
2585 : : void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq);
2586 : : int ret;
2587 : :
2588 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2589 : : MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
2590 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2591 : : MLX5_GENERAL_OBJ_TYPE_VIRTQ);
2592 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
2593 : 0 : ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in),
2594 : : out, sizeof(out));
2595 [ # # ]: 0 : if (ret) {
2596 : 0 : DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
2597 : 0 : rte_errno = errno;
2598 : 0 : return -errno;
2599 : : }
2600 [ # # ]: 0 : attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq,
2601 : : hw_available_index);
2602 [ # # ]: 0 : attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index);
2603 [ # # ]: 0 : attr->state = MLX5_GET16(virtio_net_q, virtq, state);
2604 [ # # ]: 0 : attr->error_type = MLX5_GET16(virtio_net_q, virtq,
2605 : : virtio_q_context.error_type);
2606 : 0 : return ret;
2607 : : }
2608 : :
2609 : : /**
2610 : : * Create QP using DevX API.
2611 : : *
2612 : : * @param[in] ctx
2613 : : * Context returned from mlx5 open_device() glue function.
2614 : : * @param [in] attr
2615 : : * Pointer to QP attributes structure.
2616 : : *
2617 : : * @return
2618 : : * The DevX object created, NULL otherwise and rte_errno is set.
2619 : : */
2620 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_qp)
2621 : : struct mlx5_devx_obj *
2622 : 0 : mlx5_devx_cmd_create_qp(void *ctx,
2623 : : struct mlx5_devx_qp_attr *attr)
2624 : : {
2625 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0};
2626 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0};
2627 : 0 : struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO,
2628 : : sizeof(*qp_obj),
2629 : : 0, SOCKET_ID_ANY);
2630 : : void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
2631 : :
2632 [ # # ]: 0 : if (!qp_obj) {
2633 : 0 : DRV_LOG(ERR, "Failed to allocate QP data.");
2634 : 0 : rte_errno = ENOMEM;
2635 : 0 : return NULL;
2636 : : }
2637 [ # # ]: 0 : MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP);
2638 [ # # ]: 0 : MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC);
2639 [ # # ]: 0 : MLX5_SET(qpc, qpc, pd, attr->pd);
2640 [ # # ]: 0 : MLX5_SET(qpc, qpc, ts_format, attr->ts_format);
2641 [ # # ]: 0 : MLX5_SET(qpc, qpc, user_index, attr->user_index);
2642 [ # # ]: 0 : if (attr->uar_index) {
2643 [ # # ]: 0 : if (attr->mmo) {
2644 : : void *qpc_ext_and_pas_list = MLX5_ADDR_OF(create_qp_in,
2645 : : in, qpc_extension_and_pas_list);
2646 : : void *qpc_ext = MLX5_ADDR_OF(qpc_extension_and_pas_list,
2647 : : qpc_ext_and_pas_list, qpc_data_extension);
2648 : :
2649 [ # # ]: 0 : MLX5_SET(create_qp_in, in, qpc_ext, 1);
2650 [ # # ]: 0 : MLX5_SET(qpc_extension, qpc_ext, mmo, 1);
2651 : : }
2652 [ # # ]: 0 : MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2653 [ # # ]: 0 : MLX5_SET(qpc, qpc, uar_page, attr->uar_index);
2654 [ # # ]: 0 : if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)
2655 [ # # ]: 0 : MLX5_SET(qpc, qpc, log_page_size,
2656 : : attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT);
2657 [ # # ]: 0 : if (attr->num_of_send_wqbbs) {
2658 : : MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->num_of_send_wqbbs));
2659 [ # # ]: 0 : MLX5_SET(qpc, qpc, cqn_snd, attr->cqn);
2660 [ # # ]: 0 : MLX5_SET(qpc, qpc, log_sq_size,
2661 : : rte_log2_u32(attr->num_of_send_wqbbs));
2662 : : } else {
2663 [ # # ]: 0 : MLX5_SET(qpc, qpc, no_sq, 1);
2664 : : }
2665 [ # # ]: 0 : if (attr->num_of_receive_wqes) {
2666 : : MLX5_ASSERT(RTE_IS_POWER_OF_2(
2667 : : attr->num_of_receive_wqes));
2668 [ # # ]: 0 : MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn);
2669 [ # # ]: 0 : MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride -
2670 : : MLX5_LOG_RQ_STRIDE_SHIFT);
2671 [ # # # # ]: 0 : MLX5_SET(qpc, qpc, log_rq_size,
2672 : : rte_log2_u32(attr->num_of_receive_wqes));
2673 [ # # ]: 0 : MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ);
2674 : : } else {
2675 [ # # ]: 0 : MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
2676 : : }
2677 [ # # ]: 0 : if (attr->dbr_umem_valid) {
2678 [ # # ]: 0 : MLX5_SET(qpc, qpc, dbr_umem_valid,
2679 : : attr->dbr_umem_valid);
2680 [ # # ]: 0 : MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id);
2681 : : }
2682 [ # # ]: 0 : if (attr->cd_master)
2683 [ # # ]: 0 : MLX5_SET(qpc, qpc, cd_master, attr->cd_master);
2684 [ # # ]: 0 : if (attr->cd_slave_send)
2685 [ # # ]: 0 : MLX5_SET(qpc, qpc, cd_slave_send, attr->cd_slave_send);
2686 [ # # ]: 0 : if (attr->cd_slave_recv)
2687 [ # # ]: 0 : MLX5_SET(qpc, qpc, cd_slave_receive, attr->cd_slave_recv);
2688 [ # # ]: 0 : MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address);
2689 [ # # ]: 0 : MLX5_SET64(create_qp_in, in, wq_umem_offset,
2690 : : attr->wq_umem_offset);
2691 [ # # ]: 0 : MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id);
2692 [ # # ]: 0 : MLX5_SET(create_qp_in, in, wq_umem_valid, 1);
2693 : : } else {
2694 : : /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */
2695 [ # # ]: 0 : MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
2696 [ # # ]: 0 : MLX5_SET(qpc, qpc, no_sq, 1);
2697 : : }
2698 : 0 : qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2699 : : sizeof(out));
2700 [ # # ]: 0 : if (!qp_obj->obj) {
2701 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create QP", NULL, 0);
2702 : 0 : mlx5_free(qp_obj);
2703 : 0 : return NULL;
2704 : : }
2705 [ # # ]: 0 : qp_obj->id = MLX5_GET(create_qp_out, out, qpn);
2706 : 0 : return qp_obj;
2707 : : }
2708 : :
2709 : : /**
2710 : : * Modify QP using DevX API.
2711 : : * Currently supports only force loop-back QP.
2712 : : *
2713 : : * @param[in] qp
2714 : : * Pointer to QP object structure.
2715 : : * @param [in] qp_st_mod_op
2716 : : * The QP state modification operation.
2717 : : * @param [in] remote_qp_id
2718 : : * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation.
2719 : : *
2720 : : * @return
2721 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
2722 : : */
2723 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_modify_qp_state)
2724 : : int
2725 : 0 : mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op,
2726 : : uint32_t remote_qp_id)
2727 : : {
2728 : : union {
2729 : : uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)];
2730 : : uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)];
2731 : : uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)];
2732 : : uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_in)];
2733 : : } in;
2734 : : union {
2735 : : uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)];
2736 : : uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)];
2737 : : uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)];
2738 : : uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_out)];
2739 : : } out;
2740 : : void *qpc;
2741 : : int ret;
2742 : : unsigned int inlen;
2743 : : unsigned int outlen;
2744 : :
2745 : : memset(&in, 0, sizeof(in));
2746 : : memset(&out, 0, sizeof(out));
2747 : 0 : MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op);
2748 [ # # # # : 0 : switch (qp_st_mod_op) {
# ]
2749 : 0 : case MLX5_CMD_OP_RST2INIT_QP:
2750 : 0 : MLX5_SET(rst2init_qp_in, &in, qpn, qp->id);
2751 : : qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc);
2752 : 0 : MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
2753 : : MLX5_SET(qpc, qpc, rre, 1);
2754 [ # # ]: 0 : MLX5_SET(qpc, qpc, rwe, 1);
2755 : 0 : MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2756 : : inlen = sizeof(in.rst2init);
2757 : : outlen = sizeof(out.rst2init);
2758 : 0 : break;
2759 : 0 : case MLX5_CMD_OP_INIT2RTR_QP:
2760 : 0 : MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id);
2761 : : qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc);
2762 : 0 : MLX5_SET(qpc, qpc, primary_address_path.fl, 1);
2763 : 0 : MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
2764 : : MLX5_SET(qpc, qpc, mtu, 1);
2765 [ # # ]: 0 : MLX5_SET(qpc, qpc, log_msg_max, 30);
2766 : 0 : MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id);
2767 : 0 : MLX5_SET(qpc, qpc, min_rnr_nak, 0);
2768 : : inlen = sizeof(in.init2rtr);
2769 : : outlen = sizeof(out.init2rtr);
2770 : 0 : break;
2771 : 0 : case MLX5_CMD_OP_RTR2RTS_QP:
2772 : : qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc);
2773 : 0 : MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id);
2774 : 0 : MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 16);
2775 : : MLX5_SET(qpc, qpc, log_ack_req_freq, 0);
2776 [ # # ]: 0 : MLX5_SET(qpc, qpc, retry_count, 7);
2777 [ # # ]: 0 : MLX5_SET(qpc, qpc, rnr_retry, 7);
2778 : : inlen = sizeof(in.rtr2rts);
2779 : : outlen = sizeof(out.rtr2rts);
2780 : 0 : break;
2781 : 0 : case MLX5_CMD_OP_QP_2RST:
2782 : 0 : MLX5_SET(2rst_qp_in, &in, qpn, qp->id);
2783 : : inlen = sizeof(in.qp2rst);
2784 : : outlen = sizeof(out.qp2rst);
2785 : 0 : break;
2786 : 0 : default:
2787 : 0 : DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.",
2788 : : qp_st_mod_op);
2789 : 0 : rte_errno = EINVAL;
2790 : 0 : return -rte_errno;
2791 : : }
2792 : 0 : ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen);
2793 [ # # ]: 0 : if (ret) {
2794 : 0 : DRV_LOG(ERR, "Failed to modify QP using DevX.");
2795 : 0 : rte_errno = errno;
2796 : 0 : return -rte_errno;
2797 : : }
2798 : : return ret;
2799 : : }
2800 : :
2801 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_virtio_q_counters)
2802 : : struct mlx5_devx_obj *
2803 : 0 : mlx5_devx_cmd_create_virtio_q_counters(void *ctx)
2804 : : {
2805 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0};
2806 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2807 : 0 : struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO,
2808 : : sizeof(*couners_obj), 0,
2809 : : SOCKET_ID_ANY);
2810 : : void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr);
2811 : :
2812 [ # # ]: 0 : if (!couners_obj) {
2813 : 0 : DRV_LOG(ERR, "Failed to allocate virtio queue counters data.");
2814 : 0 : rte_errno = ENOMEM;
2815 : 0 : return NULL;
2816 : : }
2817 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2818 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2819 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2820 : : MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
2821 : 0 : couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2822 : : sizeof(out));
2823 [ # # ]: 0 : if (!couners_obj->obj) {
2824 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create virtio queue counters Obj", NULL,
2825 : : 0);
2826 : 0 : mlx5_free(couners_obj);
2827 : 0 : return NULL;
2828 : : }
2829 [ # # ]: 0 : couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2830 : 0 : return couners_obj;
2831 : : }
2832 : :
2833 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_query_virtio_q_counters)
2834 : : int
2835 : 0 : mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,
2836 : : struct mlx5_devx_virtio_q_couners_attr *attr)
2837 : : {
2838 : 0 : uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
2839 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0};
2840 : : void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr);
2841 : : void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out,
2842 : : virtio_q_counters);
2843 : : int ret;
2844 : :
2845 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2846 : : MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
2847 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2848 : : MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
2849 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id);
2850 : 0 : ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out,
2851 : : sizeof(out));
2852 [ # # ]: 0 : if (ret) {
2853 : 0 : DRV_LOG(ERR, "Failed to query virtio q counters using DevX.");
2854 : 0 : rte_errno = errno;
2855 : 0 : return -errno;
2856 : : }
2857 [ # # ]: 0 : attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
2858 : : received_desc);
2859 [ # # ]: 0 : attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
2860 : : completed_desc);
2861 [ # # ]: 0 : attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters,
2862 : : error_cqes);
2863 [ # # ]: 0 : attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters,
2864 : : bad_desc_errors);
2865 [ # # ]: 0 : attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters,
2866 : : exceed_max_chain);
2867 [ # # ]: 0 : attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters,
2868 : : invalid_buffer);
2869 : 0 : return ret;
2870 : : }
2871 : :
2872 : : /**
2873 : : * Create general object of type FLOW_HIT_ASO using DevX API.
2874 : : *
2875 : : * @param[in] ctx
2876 : : * Context returned from mlx5 open_device() glue function.
2877 : : * @param [in] pd
2878 : : * PD value to associate the FLOW_HIT_ASO object with.
2879 : : *
2880 : : * @return
2881 : : * The DevX object created, NULL otherwise and rte_errno is set.
2882 : : */
2883 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_flow_hit_aso_obj)
2884 : : struct mlx5_devx_obj *
2885 : 0 : mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd)
2886 : : {
2887 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0};
2888 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2889 : : struct mlx5_devx_obj *flow_hit_aso_obj = NULL;
2890 : : void *ptr = NULL;
2891 : :
2892 : 0 : flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj),
2893 : : 0, SOCKET_ID_ANY);
2894 [ # # ]: 0 : if (!flow_hit_aso_obj) {
2895 : 0 : DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data");
2896 : 0 : rte_errno = ENOMEM;
2897 : 0 : return NULL;
2898 : : }
2899 : : ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr);
2900 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2901 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2902 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2903 : : MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO);
2904 : : ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso);
2905 [ # # ]: 0 : MLX5_SET(flow_hit_aso, ptr, access_pd, pd);
2906 : 0 : flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2907 : : out, sizeof(out));
2908 [ # # ]: 0 : if (!flow_hit_aso_obj->obj) {
2909 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create FLOW_HIT_ASO", NULL, 0);
2910 : 0 : mlx5_free(flow_hit_aso_obj);
2911 : 0 : return NULL;
2912 : : }
2913 [ # # ]: 0 : flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2914 : 0 : return flow_hit_aso_obj;
2915 : : }
2916 : :
2917 : : /*
2918 : : * Create PD using DevX API.
2919 : : *
2920 : : * @param[in] ctx
2921 : : * Context returned from mlx5 open_device() glue function.
2922 : : *
2923 : : * @return
2924 : : * The DevX object created, NULL otherwise and rte_errno is set.
2925 : : */
2926 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_alloc_pd)
2927 : : struct mlx5_devx_obj *
2928 : 0 : mlx5_devx_cmd_alloc_pd(void *ctx)
2929 : : {
2930 : : struct mlx5_devx_obj *ppd =
2931 : 0 : mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY);
2932 : 0 : u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0};
2933 : 0 : u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0};
2934 : :
2935 [ # # ]: 0 : if (!ppd) {
2936 : 0 : DRV_LOG(ERR, "Failed to allocate PD data.");
2937 : 0 : rte_errno = ENOMEM;
2938 : 0 : return NULL;
2939 : : }
2940 : 0 : MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2941 : 0 : ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2942 : : out, sizeof(out));
2943 [ # # ]: 0 : if (!ppd->obj) {
2944 : 0 : mlx5_free(ppd);
2945 : 0 : DRV_LOG(ERR, "Failed to allocate PD Obj using DevX.");
2946 : 0 : rte_errno = errno;
2947 : 0 : return NULL;
2948 : : }
2949 [ # # ]: 0 : ppd->id = MLX5_GET(alloc_pd_out, out, pd);
2950 : 0 : return ppd;
2951 : : }
2952 : :
2953 : : /**
2954 : : * Create general object of type FLOW_METER_ASO using DevX API.
2955 : : *
2956 : : * @param[in] ctx
2957 : : * Context returned from mlx5 open_device() glue function.
2958 : : * @param [in] pd
2959 : : * PD value to associate the FLOW_METER_ASO object with.
2960 : : * @param [in] log_obj_size
2961 : : * log_obj_size define to allocate number of 2 * meters
2962 : : * in one FLOW_METER_ASO object.
2963 : : *
2964 : : * @return
2965 : : * The DevX object created, NULL otherwise and rte_errno is set.
2966 : : */
2967 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_flow_meter_aso_obj)
2968 : : struct mlx5_devx_obj *
2969 : 0 : mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd,
2970 : : uint32_t log_obj_size)
2971 : : {
2972 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0};
2973 : : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
2974 : : struct mlx5_devx_obj *flow_meter_aso_obj;
2975 : : void *ptr;
2976 : :
2977 : 0 : flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO,
2978 : : sizeof(*flow_meter_aso_obj),
2979 : : 0, SOCKET_ID_ANY);
2980 [ # # ]: 0 : if (!flow_meter_aso_obj) {
2981 : 0 : DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data");
2982 : 0 : rte_errno = ENOMEM;
2983 : 0 : return NULL;
2984 : : }
2985 : : ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr);
2986 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2987 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2988 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2989 : : MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO);
2990 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range,
2991 : : log_obj_size);
2992 : : ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso);
2993 [ # # ]: 0 : MLX5_SET(flow_meter_aso, ptr, access_pd, pd);
2994 : 0 : flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create(
2995 : : ctx, in, sizeof(in),
2996 : : out, sizeof(out));
2997 [ # # ]: 0 : if (!flow_meter_aso_obj->obj) {
2998 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create FLOW_METTER_ASO", NULL, 0);
2999 : 0 : mlx5_free(flow_meter_aso_obj);
3000 : 0 : return NULL;
3001 : : }
3002 [ # # ]: 0 : flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr,
3003 : : out, obj_id);
3004 : 0 : return flow_meter_aso_obj;
3005 : : }
3006 : :
3007 : : /*
3008 : : * Create general object of type CONN_TRACK_OFFLOAD using DevX API.
3009 : : *
3010 : : * @param[in] ctx
3011 : : * Context returned from mlx5 open_device() glue function.
3012 : : * @param [in] pd
3013 : : * PD value to associate the CONN_TRACK_OFFLOAD ASO object with.
3014 : : * @param [in] log_obj_size
3015 : : * log_obj_size to allocate its power of 2 * objects
3016 : : * in one CONN_TRACK_OFFLOAD bulk allocation.
3017 : : *
3018 : : * @return
3019 : : * The DevX object created, NULL otherwise and rte_errno is set.
3020 : : */
3021 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_conn_track_offload_obj)
3022 : : struct mlx5_devx_obj *
3023 : 0 : mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, uint32_t pd,
3024 : : uint32_t log_obj_size)
3025 : : {
3026 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_conn_track_aso_in)] = {0};
3027 : : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
3028 : : struct mlx5_devx_obj *ct_aso_obj;
3029 : : void *ptr;
3030 : :
3031 : 0 : ct_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ct_aso_obj),
3032 : : 0, SOCKET_ID_ANY);
3033 [ # # ]: 0 : if (!ct_aso_obj) {
3034 : 0 : DRV_LOG(ERR, "Failed to allocate CONN_TRACK_OFFLOAD object.");
3035 : 0 : rte_errno = ENOMEM;
3036 : 0 : return NULL;
3037 : : }
3038 : : ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, hdr);
3039 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
3040 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
3041 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
3042 : : MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD);
3043 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, log_obj_size);
3044 : : ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, conn_track_offload);
3045 [ # # ]: 0 : MLX5_SET(conn_track_offload, ptr, conn_track_aso_access_pd, pd);
3046 : 0 : ct_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
3047 : : out, sizeof(out));
3048 [ # # ]: 0 : if (!ct_aso_obj->obj) {
3049 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create CONN_TRACK_OFFLOAD", NULL, 0);
3050 : 0 : mlx5_free(ct_aso_obj);
3051 : 0 : return NULL;
3052 : : }
3053 [ # # ]: 0 : ct_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
3054 : 0 : return ct_aso_obj;
3055 : : }
3056 : :
3057 : : /**
3058 : : * Create general object of type GENEVE TLV option using DevX API.
3059 : : *
3060 : : * @param[in] ctx
3061 : : * Context returned from mlx5 open_device() glue function.
3062 : : * @param[in] attr
3063 : : * Pointer to GENEVE TLV option attributes structure.
3064 : : *
3065 : : * @return
3066 : : * The DevX object created, NULL otherwise and rte_errno is set.
3067 : : */
3068 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_geneve_tlv_option)
3069 : : struct mlx5_devx_obj *
3070 : 0 : mlx5_devx_cmd_create_geneve_tlv_option(void *ctx,
3071 : : struct mlx5_devx_geneve_tlv_option_attr *attr)
3072 : : {
3073 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0};
3074 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
3075 : 0 : struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO,
3076 : : sizeof(*geneve_tlv_opt_obj),
3077 : : 0, SOCKET_ID_ANY);
3078 : :
3079 [ # # ]: 0 : if (!geneve_tlv_opt_obj) {
3080 : 0 : DRV_LOG(ERR, "Failed to allocate GENEVE TLV option object.");
3081 : 0 : rte_errno = ENOMEM;
3082 : 0 : return NULL;
3083 : : }
3084 : : void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr);
3085 : : void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in,
3086 : : geneve_tlv_opt);
3087 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
3088 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
3089 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
3090 : : MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT);
3091 [ # # ]: 0 : MLX5_SET(geneve_tlv_option, opt, option_type, attr->option_type);
3092 [ # # ]: 0 : MLX5_SET(geneve_tlv_option, opt, option_data_length,
3093 : : attr->option_data_len);
3094 [ # # ]: 0 : if (attr->option_class_ignore)
3095 [ # # ]: 0 : MLX5_SET(geneve_tlv_option, opt, option_class_ignore,
3096 : : attr->option_class_ignore);
3097 : : else
3098 [ # # # # ]: 0 : MLX5_SET(geneve_tlv_option, opt, option_class,
3099 : : rte_be_to_cpu_16(attr->option_class));
3100 [ # # ]: 0 : if (attr->offset_valid) {
3101 [ # # ]: 0 : MLX5_SET(geneve_tlv_option, opt, sample_offset_valid,
3102 : : attr->offset_valid);
3103 [ # # ]: 0 : MLX5_SET(geneve_tlv_option, opt, sample_offset,
3104 : : attr->sample_offset);
3105 : : }
3106 : 0 : geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in,
3107 : : sizeof(in), out,
3108 : : sizeof(out));
3109 [ # # ]: 0 : if (!geneve_tlv_opt_obj->obj) {
3110 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create GENEVE TLV option", NULL, 0);
3111 : 0 : mlx5_free(geneve_tlv_opt_obj);
3112 : 0 : return NULL;
3113 : : }
3114 [ # # ]: 0 : geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
3115 : 0 : return geneve_tlv_opt_obj;
3116 : : }
3117 : :
3118 : : /**
3119 : : * Query GENEVE TLV option using DevX API.
3120 : : *
3121 : : * @param[in] ctx
3122 : : * Context used to create GENEVE TLV option object.
3123 : : * @param[in] geneve_tlv_opt_obj
3124 : : * DevX object of the GENEVE TLV option.
3125 : : * @param[out] attr
3126 : : * Pointer to match sample info attributes structure.
3127 : : *
3128 : : * @return
3129 : : * 0 on success, a negative errno otherwise and rte_errno is set.
3130 : : */
3131 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_query_geneve_tlv_option)
3132 : : int
3133 : 0 : mlx5_devx_cmd_query_geneve_tlv_option(void *ctx,
3134 : : struct mlx5_devx_obj *geneve_tlv_opt_obj,
3135 : : struct mlx5_devx_match_sample_info_query_attr *attr)
3136 : : {
3137 : 0 : uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
3138 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_geneve_tlv_option_out)] = {0};
3139 : : void *hdr = MLX5_ADDR_OF(query_geneve_tlv_option_out, in, hdr);
3140 : : void *opt = MLX5_ADDR_OF(query_geneve_tlv_option_out, out,
3141 : : geneve_tlv_opt);
3142 : : int ret;
3143 : :
3144 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
3145 : : MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
3146 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
3147 : : MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT);
3148 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, geneve_tlv_opt_obj->id);
3149 : : /* Call first query to get sample handle. */
3150 : 0 : ret = mlx5_glue->devx_obj_query(geneve_tlv_opt_obj->obj, in, sizeof(in),
3151 : : out, sizeof(out));
3152 [ # # ]: 0 : if (ret) {
3153 : 0 : DRV_LOG(ERR, "Failed to query GENEVE TLV option using DevX.");
3154 : 0 : rte_errno = errno;
3155 : 0 : return -errno;
3156 : : }
3157 : : /* Call second query to get sample information. */
3158 [ # # # # ]: 0 : if (MLX5_GET(geneve_tlv_option, opt, sample_id_valid)) {
3159 [ # # ]: 0 : uint32_t sample_id = MLX5_GET(geneve_tlv_option, opt,
3160 : : geneve_sample_field_id);
3161 : :
3162 : 0 : return mlx5_devx_cmd_match_sample_info_query(ctx, sample_id,
3163 : : attr);
3164 : : }
3165 : 0 : DRV_LOG(DEBUG, "GENEVE TLV option sample isn't valid.");
3166 : 0 : return 0;
3167 : : }
3168 : :
3169 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_wq_query)
3170 : : int
3171 : 0 : mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id)
3172 : : {
3173 : : #ifdef HAVE_IBV_FLOW_DV_SUPPORT
3174 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0};
3175 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0};
3176 : : int rc;
3177 : : void *rq_ctx;
3178 : :
3179 : 0 : MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ);
3180 : 0 : MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num);
3181 : 0 : rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out));
3182 [ # # ]: 0 : if (rc) {
3183 : 0 : rte_errno = errno;
3184 : 0 : DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - "
3185 : : "rc = %d, errno = %d.", rc, errno);
3186 : 0 : return -rc;
3187 : : };
3188 : : rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context);
3189 [ # # ]: 0 : *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id);
3190 : 0 : return 0;
3191 : : #else
3192 : : (void)wq;
3193 : : (void)counter_set_id;
3194 : : return -ENOTSUP;
3195 : : #endif
3196 : : }
3197 : :
3198 : : /*
3199 : : * Allocate queue counters via devx interface.
3200 : : *
3201 : : * @param[in] ctx
3202 : : * Context returned from mlx5 open_device() glue function.
3203 : : * @param[out] syndrome
3204 : : * Get syndrome of devx command response.
3205 : : *
3206 : : * @return
3207 : : * Pointer to counter object on success, a NULL value otherwise and
3208 : : * rte_errno is set.
3209 : : */
3210 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_queue_counter_alloc)
3211 : : struct mlx5_devx_obj *
3212 : 0 : mlx5_devx_cmd_queue_counter_alloc(void *ctx, int *syndrome)
3213 : : {
3214 : : int status;
3215 : 0 : struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0,
3216 : : SOCKET_ID_ANY);
3217 : 0 : uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {0};
3218 : 0 : uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0};
3219 : :
3220 [ # # ]: 0 : if (!dcs) {
3221 : 0 : rte_errno = ENOMEM;
3222 : 0 : return NULL;
3223 : : }
3224 : 0 : MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
3225 : 0 : dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
3226 : : sizeof(out));
3227 [ # # ]: 0 : if (!dcs->obj) {
3228 [ # # # # ]: 0 : DEVX_DRV_LOG(DEBUG, out, "create q counter set", NULL, 0);
3229 [ # # ]: 0 : status = MLX5_GET(alloc_q_counter_out, out, status);
3230 [ # # ]: 0 : if (status && syndrome)
3231 [ # # ]: 0 : *syndrome = MLX5_GET(alloc_q_counter_out, out, syndrome);
3232 : 0 : mlx5_free(dcs);
3233 : 0 : return NULL;
3234 : : }
3235 [ # # ]: 0 : dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id);
3236 : 0 : return dcs;
3237 : : }
3238 : :
3239 : : /**
3240 : : * Query queue counters values.
3241 : : *
3242 : : * @param[in] dcs
3243 : : * devx object of the queue counter set.
3244 : : * @param[in] clear
3245 : : * Whether hardware should clear the counters after the query or not.
3246 : : * @param[out] out_of_buffers
3247 : : * Number of dropped occurred due to lack of WQE for the associated QPs/RQs.
3248 : : *
3249 : : * @return
3250 : : * 0 on success, a negative value otherwise.
3251 : : */
3252 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_queue_counter_query)
3253 : : int
3254 : 0 : mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear,
3255 : : uint32_t *out_of_buffers)
3256 : : {
3257 : 0 : uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0};
3258 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0};
3259 : : int rc;
3260 : :
3261 : 0 : MLX5_SET(query_q_counter_in, in, opcode,
3262 : : MLX5_CMD_OP_QUERY_Q_COUNTER);
3263 : 0 : MLX5_SET(query_q_counter_in, in, op_mod, 0);
3264 : 0 : MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id);
3265 : 0 : MLX5_SET(query_q_counter_in, in, clear, !!clear);
3266 : 0 : rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
3267 : : sizeof(out));
3268 [ # # ]: 0 : if (rc) {
3269 : 0 : DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc);
3270 : 0 : rte_errno = rc;
3271 : 0 : return -rc;
3272 : : }
3273 [ # # ]: 0 : *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer);
3274 : 0 : return 0;
3275 : : }
3276 : :
3277 : : /**
3278 : : * Create general object of type DEK using DevX API.
3279 : : *
3280 : : * @param[in] ctx
3281 : : * Context returned from mlx5 open_device() glue function.
3282 : : * @param [in] attr
3283 : : * Pointer to DEK attributes structure.
3284 : : *
3285 : : * @return
3286 : : * The DevX object created, NULL otherwise and rte_errno is set.
3287 : : */
3288 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_dek_obj)
3289 : : struct mlx5_devx_obj *
3290 : 0 : mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr)
3291 : : {
3292 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0};
3293 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
3294 : : struct mlx5_devx_obj *dek_obj = NULL;
3295 : : void *ptr = NULL, *key_addr = NULL;
3296 : :
3297 : 0 : dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj),
3298 : : 0, SOCKET_ID_ANY);
3299 [ # # ]: 0 : if (dek_obj == NULL) {
3300 : 0 : DRV_LOG(ERR, "Failed to allocate DEK object data");
3301 : 0 : rte_errno = ENOMEM;
3302 : 0 : return NULL;
3303 : : }
3304 : : ptr = MLX5_ADDR_OF(create_dek_in, in, hdr);
3305 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
3306 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
3307 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
3308 : : MLX5_GENERAL_OBJ_TYPE_DEK);
3309 : : ptr = MLX5_ADDR_OF(create_dek_in, in, dek);
3310 [ # # ]: 0 : MLX5_SET(dek, ptr, key_size, attr->key_size);
3311 [ # # ]: 0 : MLX5_SET(dek, ptr, has_keytag, attr->has_keytag);
3312 [ # # ]: 0 : MLX5_SET(dek, ptr, key_purpose, attr->key_purpose);
3313 [ # # ]: 0 : MLX5_SET(dek, ptr, pd, attr->pd);
3314 [ # # ]: 0 : MLX5_SET64(dek, ptr, opaque, attr->opaque);
3315 : : key_addr = MLX5_ADDR_OF(dek, ptr, key);
3316 : 0 : memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE);
3317 : 0 : dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
3318 : : out, sizeof(out));
3319 [ # # ]: 0 : if (dek_obj->obj == NULL) {
3320 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create DEK", NULL, 0);
3321 : 0 : mlx5_free(dek_obj);
3322 : 0 : return NULL;
3323 : : }
3324 [ # # ]: 0 : dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
3325 : 0 : return dek_obj;
3326 : : }
3327 : :
3328 : : /**
3329 : : * Create general object of type IMPORT_KEK using DevX API.
3330 : : *
3331 : : * @param[in] ctx
3332 : : * Context returned from mlx5 open_device() glue function.
3333 : : * @param [in] attr
3334 : : * Pointer to IMPORT_KEK attributes structure.
3335 : : *
3336 : : * @return
3337 : : * The DevX object created, NULL otherwise and rte_errno is set.
3338 : : */
3339 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_import_kek_obj)
3340 : : struct mlx5_devx_obj *
3341 : 0 : mlx5_devx_cmd_create_import_kek_obj(void *ctx,
3342 : : struct mlx5_devx_import_kek_attr *attr)
3343 : : {
3344 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_import_kek_in)] = {0};
3345 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
3346 : : struct mlx5_devx_obj *import_kek_obj = NULL;
3347 : : void *ptr = NULL, *key_addr = NULL;
3348 : :
3349 : 0 : import_kek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*import_kek_obj),
3350 : : 0, SOCKET_ID_ANY);
3351 [ # # ]: 0 : if (import_kek_obj == NULL) {
3352 : 0 : DRV_LOG(ERR, "Failed to allocate IMPORT_KEK object data");
3353 : 0 : rte_errno = ENOMEM;
3354 : 0 : return NULL;
3355 : : }
3356 : : ptr = MLX5_ADDR_OF(create_import_kek_in, in, hdr);
3357 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
3358 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
3359 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
3360 : : MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK);
3361 : : ptr = MLX5_ADDR_OF(create_import_kek_in, in, import_kek);
3362 [ # # ]: 0 : MLX5_SET(import_kek, ptr, key_size, attr->key_size);
3363 : : key_addr = MLX5_ADDR_OF(import_kek, ptr, key);
3364 : 0 : memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE);
3365 : 0 : import_kek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
3366 : : out, sizeof(out));
3367 [ # # ]: 0 : if (import_kek_obj->obj == NULL) {
3368 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create IMPORT_KEK", NULL, 0);
3369 : 0 : mlx5_free(import_kek_obj);
3370 : 0 : return NULL;
3371 : : }
3372 [ # # ]: 0 : import_kek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
3373 : 0 : return import_kek_obj;
3374 : : }
3375 : :
3376 : : /**
3377 : : * Create general object of type CREDENTIAL using DevX API.
3378 : : *
3379 : : * @param[in] ctx
3380 : : * Context returned from mlx5 open_device() glue function.
3381 : : * @param [in] attr
3382 : : * Pointer to CREDENTIAL attributes structure.
3383 : : *
3384 : : * @return
3385 : : * The DevX object created, NULL otherwise and rte_errno is set.
3386 : : */
3387 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_credential_obj)
3388 : : struct mlx5_devx_obj *
3389 : 0 : mlx5_devx_cmd_create_credential_obj(void *ctx,
3390 : : struct mlx5_devx_credential_attr *attr)
3391 : : {
3392 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_credential_in)] = {0};
3393 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
3394 : : struct mlx5_devx_obj *credential_obj = NULL;
3395 : : void *ptr = NULL, *credential_addr = NULL;
3396 : :
3397 : 0 : credential_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*credential_obj),
3398 : : 0, SOCKET_ID_ANY);
3399 [ # # ]: 0 : if (credential_obj == NULL) {
3400 : 0 : DRV_LOG(ERR, "Failed to allocate CREDENTIAL object data");
3401 : 0 : rte_errno = ENOMEM;
3402 : 0 : return NULL;
3403 : : }
3404 : : ptr = MLX5_ADDR_OF(create_credential_in, in, hdr);
3405 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
3406 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
3407 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
3408 : : MLX5_GENERAL_OBJ_TYPE_CREDENTIAL);
3409 : : ptr = MLX5_ADDR_OF(create_credential_in, in, credential);
3410 [ # # ]: 0 : MLX5_SET(credential, ptr, credential_role, attr->credential_role);
3411 : : credential_addr = MLX5_ADDR_OF(credential, ptr, credential);
3412 : 0 : memcpy(credential_addr, (void *)(attr->credential),
3413 : : MLX5_CRYPTO_CREDENTIAL_SIZE);
3414 : 0 : credential_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
3415 : : out, sizeof(out));
3416 [ # # ]: 0 : if (credential_obj->obj == NULL) {
3417 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create CREDENTIAL", NULL, 0);
3418 : 0 : mlx5_free(credential_obj);
3419 : 0 : return NULL;
3420 : : }
3421 [ # # ]: 0 : credential_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
3422 : 0 : return credential_obj;
3423 : : }
3424 : :
3425 : : /**
3426 : : * Create general object of type CRYPTO_LOGIN using DevX API.
3427 : : *
3428 : : * @param[in] ctx
3429 : : * Context returned from mlx5 open_device() glue function.
3430 : : * @param [in] attr
3431 : : * Pointer to CRYPTO_LOGIN attributes structure.
3432 : : *
3433 : : * @return
3434 : : * The DevX object created, NULL otherwise and rte_errno is set.
3435 : : */
3436 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_create_crypto_login_obj)
3437 : : struct mlx5_devx_obj *
3438 : 0 : mlx5_devx_cmd_create_crypto_login_obj(void *ctx,
3439 : : struct mlx5_devx_crypto_login_attr *attr)
3440 : : {
3441 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_crypto_login_in)] = {0};
3442 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
3443 : : struct mlx5_devx_obj *crypto_login_obj = NULL;
3444 : : void *ptr = NULL, *credential_addr = NULL;
3445 : :
3446 : 0 : crypto_login_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*crypto_login_obj),
3447 : : 0, SOCKET_ID_ANY);
3448 [ # # ]: 0 : if (crypto_login_obj == NULL) {
3449 : 0 : DRV_LOG(ERR, "Failed to allocate CRYPTO_LOGIN object data");
3450 : 0 : rte_errno = ENOMEM;
3451 : 0 : return NULL;
3452 : : }
3453 : : ptr = MLX5_ADDR_OF(create_crypto_login_in, in, hdr);
3454 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
3455 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
3456 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
3457 : : MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN);
3458 : : ptr = MLX5_ADDR_OF(create_crypto_login_in, in, crypto_login);
3459 [ # # ]: 0 : MLX5_SET(crypto_login, ptr, credential_pointer,
3460 : : attr->credential_pointer);
3461 [ # # ]: 0 : MLX5_SET(crypto_login, ptr, session_import_kek_ptr,
3462 : : attr->session_import_kek_ptr);
3463 : : credential_addr = MLX5_ADDR_OF(crypto_login, ptr, credential);
3464 : 0 : memcpy(credential_addr, (void *)(attr->credential),
3465 : : MLX5_CRYPTO_CREDENTIAL_SIZE);
3466 : 0 : crypto_login_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
3467 : : out, sizeof(out));
3468 [ # # ]: 0 : if (crypto_login_obj->obj == NULL) {
3469 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create CRYPTO_LOGIN", NULL, 0);
3470 : 0 : mlx5_free(crypto_login_obj);
3471 : 0 : return NULL;
3472 : : }
3473 [ # # ]: 0 : crypto_login_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
3474 : 0 : return crypto_login_obj;
3475 : : }
3476 : :
3477 : : /**
3478 : : * Query LAG context.
3479 : : *
3480 : : * @param[in] ctx
3481 : : * Pointer to ibv_context, returned from mlx5dv_open_device.
3482 : : * @param[out] lag_ctx
3483 : : * Pointer to struct mlx5_devx_lag_context, to be set by the routine.
3484 : : *
3485 : : * @return
3486 : : * 0 on success, a negative value otherwise.
3487 : : */
3488 : : RTE_EXPORT_INTERNAL_SYMBOL(mlx5_devx_cmd_query_lag)
3489 : : int
3490 : 0 : mlx5_devx_cmd_query_lag(void *ctx,
3491 : : struct mlx5_devx_lag_context *lag_ctx)
3492 : : {
3493 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_lag_in)] = {0};
3494 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_lag_out)] = {0};
3495 : : void *lctx;
3496 : : int rc;
3497 : :
3498 : 0 : MLX5_SET(query_lag_in, in, opcode, MLX5_CMD_OP_QUERY_LAG);
3499 : 0 : rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
3500 [ # # ]: 0 : if (rc)
3501 : 0 : goto error;
3502 : : lctx = MLX5_ADDR_OF(query_lag_out, out, context);
3503 [ # # ]: 0 : lag_ctx->fdb_selection_mode = MLX5_GET(lag_context, lctx,
3504 : : fdb_selection_mode);
3505 [ # # ]: 0 : lag_ctx->port_select_mode = MLX5_GET(lag_context, lctx,
3506 : : port_select_mode);
3507 [ # # ]: 0 : lag_ctx->lag_state = MLX5_GET(lag_context, lctx, lag_state);
3508 [ # # ]: 0 : lag_ctx->tx_remap_affinity_2 = MLX5_GET(lag_context, lctx,
3509 : : tx_remap_affinity_2);
3510 [ # # ]: 0 : lag_ctx->tx_remap_affinity_1 = MLX5_GET(lag_context, lctx,
3511 : : tx_remap_affinity_1);
3512 : 0 : return 0;
3513 : : error:
3514 : 0 : rc = (rc > 0) ? -rc : rc;
3515 : 0 : return rc;
3516 : : }
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