Branch data Line data Source code
1 : : /* SPDX-License-Identifier: BSD-3-Clause
2 : : * Copyright(c) 2023 Napatech A/S
3 : : */
4 : :
5 : : #include "nt_service.h"
6 : : #include "ntlog.h"
7 : : #include "nthw_fpga.h"
8 : : #include "ntnic_mod_reg.h"
9 : :
10 : : /*
11 : : * Global variables shared by NT adapter types
12 : : */
13 : :
14 : 0 : static int nt4ga_adapter_show_info(struct adapter_info_s *p_adapter_info, FILE *pfh)
15 : : {
16 : 0 : const char *const p_dev_name = p_adapter_info->p_dev_name;
17 : 0 : const char *const p_adapter_id_str = p_adapter_info->mp_adapter_id_str;
18 : : fpga_info_t *p_fpga_info = &p_adapter_info->fpga_info;
19 : : hw_info_t *p_hw_info = &p_adapter_info->hw_info;
20 : : mcu_info_t *mcu_info = &p_adapter_info->fpga_info.mcu_info;
21 : : char a_pci_ident_str[32];
22 : :
23 : 0 : snprintf(a_pci_ident_str, sizeof(a_pci_ident_str), PCIIDENT_PRINT_STR,
24 : 0 : PCIIDENT_TO_DOMAIN(p_fpga_info->pciident),
25 : 0 : PCIIDENT_TO_BUSNR(p_fpga_info->pciident),
26 : 0 : PCIIDENT_TO_DEVNR(p_fpga_info->pciident),
27 [ # # ]: 0 : PCIIDENT_TO_FUNCNR(p_fpga_info->pciident));
28 : :
29 [ # # ]: 0 : fprintf(pfh, "%s: DeviceName: %s\n", p_adapter_id_str, (p_dev_name ? p_dev_name : "NA"));
30 : : fprintf(pfh, "%s: PCI Details:\n", p_adapter_id_str);
31 : 0 : fprintf(pfh, "%s: %s: %08X: %04X:%04X %04X:%04X\n", p_adapter_id_str, a_pci_ident_str,
32 : 0 : p_fpga_info->pciident, p_hw_info->pci_vendor_id, p_hw_info->pci_device_id,
33 : 0 : p_hw_info->pci_sub_vendor_id, p_hw_info->pci_sub_device_id);
34 : : fprintf(pfh, "%s: FPGA Details:\n", p_adapter_id_str);
35 : 0 : fprintf(pfh, "%s: %03d-%04d-%02d-%02d [%016" PRIX64 "] (%08X)\n", p_adapter_id_str,
36 : : p_fpga_info->n_fpga_type_id, p_fpga_info->n_fpga_prod_id,
37 : : p_fpga_info->n_fpga_ver_id, p_fpga_info->n_fpga_rev_id, p_fpga_info->n_fpga_ident,
38 : : p_fpga_info->n_fpga_build_time);
39 : 0 : fprintf(pfh, "%s: FpgaDebugMode=0x%x\n", p_adapter_id_str, p_fpga_info->n_fpga_debug_mode);
40 : 0 : fprintf(pfh, "%s: Nims=%d PhyPorts=%d PhyQuads=%d RxPorts=%d TxPorts=%d\n",
41 : : p_adapter_id_str, p_fpga_info->n_nims, p_fpga_info->n_phy_ports,
42 : : p_fpga_info->n_phy_quads, p_fpga_info->n_rx_ports, p_fpga_info->n_tx_ports);
43 : 0 : fprintf(pfh, "%s: Hw=0x%02X_rev%d: %s\n", p_adapter_id_str, p_hw_info->hw_platform_id,
44 : 0 : p_fpga_info->nthw_hw_info.hw_id, p_fpga_info->nthw_hw_info.hw_plat_id_str);
45 : : fprintf(pfh, "%s: MCU Details:\n", p_adapter_id_str);
46 : 0 : fprintf(pfh, "%s: HasMcu=%d McuType=%d McuDramSize=%d\n", p_adapter_id_str,
47 : 0 : mcu_info->mb_has_mcu, mcu_info->mn_mcu_type, mcu_info->mn_mcu_dram_size);
48 : :
49 : 0 : return 0;
50 : : }
51 : :
52 : 0 : static int nt4ga_adapter_init(struct adapter_info_s *p_adapter_info)
53 : : {
54 : 0 : const struct flow_filter_ops *flow_filter_ops = nthw_get_flow_filter_ops();
55 : :
56 [ # # ]: 0 : if (flow_filter_ops == NULL)
57 : 0 : NT_LOG(ERR, NTNIC, "%s: flow_filter module uninitialized", __func__);
58 : :
59 : 0 : char *const p_dev_name = malloc(24);
60 : 0 : char *const p_adapter_id_str = malloc(24);
61 : 0 : fpga_info_t *fpga_info = &p_adapter_info->fpga_info;
62 : : hw_info_t *p_hw_info = &p_adapter_info->hw_info;
63 : :
64 : : RTE_ASSERT(fpga_info);
65 : :
66 : : /*
67 : : * IMPORTANT: Most variables cannot be determined before nthw fpga model is instantiated
68 : : * (nthw_fpga_init())
69 : : */
70 : : int res = -1;
71 : : nthw_fpga_t *p_fpga = NULL;
72 : :
73 : 0 : p_hw_info->n_nthw_adapter_id = nthw_platform_get_adapter_id(p_hw_info->pci_device_id);
74 : :
75 : 0 : fpga_info->n_nthw_adapter_id = p_hw_info->n_nthw_adapter_id;
76 : : /* ref: DN-0060 section 9 */
77 : 0 : p_hw_info->hw_product_type = p_hw_info->pci_device_id & 0x000f;
78 : : /* ref: DN-0060 section 9 */
79 : 0 : p_hw_info->hw_platform_id = (p_hw_info->pci_device_id >> 4) & 0x00ff;
80 : : /* ref: DN-0060 section 9 */
81 : 0 : p_hw_info->hw_reserved1 = (p_hw_info->pci_device_id >> 12) & 0x000f;
82 : :
83 : 0 : p_adapter_info->p_dev_name = p_dev_name;
84 : :
85 [ # # ]: 0 : if (p_dev_name) {
86 : 0 : snprintf(p_dev_name, 24, PCIIDENT_PRINT_STR,
87 : 0 : PCIIDENT_TO_DOMAIN(p_adapter_info->fpga_info.pciident),
88 : 0 : PCIIDENT_TO_BUSNR(p_adapter_info->fpga_info.pciident),
89 : 0 : PCIIDENT_TO_DEVNR(p_adapter_info->fpga_info.pciident),
90 : 0 : PCIIDENT_TO_FUNCNR(p_adapter_info->fpga_info.pciident));
91 : 0 : NT_LOG(DBG, NTNIC, "%s: (0x%08X)", p_dev_name,
92 : : p_adapter_info->fpga_info.pciident);
93 : : }
94 : :
95 : 0 : p_adapter_info->mp_adapter_id_str = p_adapter_id_str;
96 : :
97 : 0 : p_adapter_info->fpga_info.mp_adapter_id_str = p_adapter_id_str;
98 : :
99 [ # # ]: 0 : if (p_adapter_id_str) {
100 : 0 : snprintf(p_adapter_id_str, 24, "PCI:" PCIIDENT_PRINT_STR,
101 : 0 : PCIIDENT_TO_DOMAIN(p_adapter_info->fpga_info.pciident),
102 : 0 : PCIIDENT_TO_BUSNR(p_adapter_info->fpga_info.pciident),
103 : 0 : PCIIDENT_TO_DEVNR(p_adapter_info->fpga_info.pciident),
104 [ # # ]: 0 : PCIIDENT_TO_FUNCNR(p_adapter_info->fpga_info.pciident));
105 [ # # ]: 0 : NT_LOG(DBG, NTNIC, "%s: %s", p_adapter_id_str, p_dev_name ? p_dev_name : "NA");
106 : : }
107 : :
108 : : {
109 : : int i;
110 : :
111 [ # # ]: 0 : for (i = 0; i < (int)ARRAY_SIZE(p_adapter_info->mp_port_id_str); i++) {
112 : 0 : char *p = malloc(32);
113 : :
114 [ # # ]: 0 : if (p) {
115 [ # # ]: 0 : snprintf(p, 32, "%s:intf_%d",
116 : : (p_adapter_id_str ? p_adapter_id_str : "NA"), i);
117 : : }
118 : :
119 : 0 : p_adapter_info->mp_port_id_str[i] = p;
120 : : }
121 : : }
122 : :
123 : 0 : res = nthw_fpga_init(&p_adapter_info->fpga_info);
124 : :
125 [ # # ]: 0 : if (res) {
126 [ # # # # ]: 0 : NT_LOG_DBGX(ERR, NTNIC, "%s: %s: FPGA=%04d res=x%08X",
127 : : p_adapter_id_str ? p_adapter_id_str : "NA",
128 : : p_dev_name ? p_dev_name : "NA", fpga_info->n_fpga_prod_id, res);
129 : 0 : return res;
130 : : }
131 : :
132 : : RTE_ASSERT(fpga_info->n_phy_ports >= 1);
133 : : RTE_ASSERT(fpga_info->n_nims >= 1);
134 : :
135 : 0 : p_fpga = fpga_info->mp_fpga;
136 : : RTE_ASSERT(p_fpga);
137 : :
138 : : /* Nt4ga Init Filter */
139 : : nt4ga_filter_t *p_filter = &p_adapter_info->nt4ga_filter;
140 : :
141 [ # # ]: 0 : if (flow_filter_ops != NULL) {
142 : 0 : res = flow_filter_ops->nthw_flow_filter_init(p_fpga, &p_filter->mp_flow_device,
143 : : p_adapter_info->adapter_no);
144 : :
145 [ # # ]: 0 : if (res != 0) {
146 : 0 : NT_LOG(ERR, NTNIC, "%s: Cannot initialize filter", p_adapter_id_str);
147 : 0 : return res;
148 : : }
149 : : }
150 : :
151 : : {
152 : : int i;
153 : : const struct link_ops_s *link_ops = NULL;
154 : : RTE_ASSERT(fpga_info->n_fpga_prod_id > 0);
155 : :
156 [ # # ]: 0 : for (i = 0; i < NUM_ADAPTER_PORTS_MAX; i++) {
157 : : /* Disable all ports. Must be enabled later */
158 : 0 : p_adapter_info->nt4ga_link.port_action[i].port_disable = true;
159 : : }
160 : :
161 [ # # # ]: 0 : switch (fpga_info->n_fpga_prod_id) {
162 : : /* NT200A01: 2x100G (Xilinx) */
163 : 0 : case 9563: /* NT200A02 (Cap) */
164 : 0 : link_ops = nthw_get_100g_link_ops();
165 : :
166 [ # # ]: 0 : if (link_ops == NULL) {
167 : 0 : NT_LOG(ERR, NTNIC, "NT200A02 100G link module uninitialized");
168 : : res = -1;
169 : : break;
170 : : }
171 : :
172 : 0 : res = link_ops->link_init(p_adapter_info, p_fpga);
173 : 0 : break;
174 : 0 : case 9569: /* NT400D11 (Intel Agilex FPGA) */
175 : : case 9574: /* NT400D13 (Intel Agilex FPGA) */
176 : 0 : link_ops = nthw_get_agx_100g_link_ops();
177 [ # # ]: 0 : if (link_ops == NULL) {
178 : 0 : NT_LOG(ERR, NTNIC, "NT400Dxx 100G link module uninitialized");
179 : : res = -1;
180 : : break;
181 : : }
182 : 0 : res = link_ops->link_init(p_adapter_info, p_fpga);
183 : 0 : break;
184 : :
185 : 0 : default:
186 : 0 : NT_LOG(ERR, NTNIC, "Unsupported FPGA product: %04d",
187 : : fpga_info->n_fpga_prod_id);
188 : : res = -1;
189 : : break;
190 : : }
191 : :
192 [ # # ]: 0 : if (res) {
193 : 0 : NT_LOG_DBGX(ERR, NTNIC, "%s: %s: FPGA=%04d res=x%08X",
194 : : p_adapter_id_str, p_dev_name,
195 : : fpga_info->n_fpga_prod_id, res);
196 : 0 : return res;
197 : : }
198 : : }
199 : :
200 : 0 : const struct nt4ga_stat_ops *nt4ga_stat_ops = nthw_get_nt4ga_stat_ops();
201 : :
202 [ # # ]: 0 : if (nt4ga_stat_ops != NULL) {
203 : : /* Nt4ga Stat init/setup */
204 : 0 : res = nt4ga_stat_ops->nt4ga_stat_init(p_adapter_info);
205 : :
206 [ # # ]: 0 : if (res != 0) {
207 : 0 : NT_LOG(ERR, NTNIC, "%s: Cannot initialize the statistics module",
208 : : p_adapter_id_str);
209 : 0 : return res;
210 : : }
211 : :
212 : 0 : res = nt4ga_stat_ops->nt4ga_stat_setup(p_adapter_info);
213 : :
214 [ # # ]: 0 : if (res != 0) {
215 : 0 : NT_LOG(ERR, NTNIC, "%s: Cannot setup the statistics module",
216 : : p_adapter_id_str);
217 : 0 : return res;
218 : : }
219 : : }
220 : :
221 : : return 0;
222 : : }
223 : :
224 : 0 : static int nt4ga_adapter_deinit(struct adapter_info_s *p_adapter_info)
225 : : {
226 : 0 : const struct flow_filter_ops *flow_filter_ops = nthw_get_flow_filter_ops();
227 : :
228 [ # # ]: 0 : if (flow_filter_ops == NULL)
229 : 0 : NT_LOG(ERR, NTNIC, "%s: flow_filter module uninitialized", __func__);
230 : :
231 : : fpga_info_t *fpga_info = &p_adapter_info->fpga_info;
232 : : int i;
233 : : int res = -1;
234 : :
235 : 0 : nthw_service_del(RTE_NTNIC_SERVICE_ADAPTER_MON);
236 : :
237 : : /* Nt4ga Deinit Filter */
238 : : nt4ga_filter_t *p_filter = &p_adapter_info->nt4ga_filter;
239 : :
240 [ # # ]: 0 : if (flow_filter_ops != NULL) {
241 : 0 : res = flow_filter_ops->nthw_flow_filter_done(p_filter->mp_flow_device);
242 : :
243 [ # # ]: 0 : if (res != 0) {
244 : 0 : NT_LOG(ERR, NTNIC, "Cannot deinitialize filter");
245 : 0 : return res;
246 : : }
247 : : }
248 : :
249 : 0 : nthw_fpga_shutdown(&p_adapter_info->fpga_info);
250 : :
251 : : /* Rac rab reset flip flop */
252 : 0 : res = nthw_rac_rab_reset(fpga_info->mp_nthw_rac);
253 : :
254 : : /* Free adapter port ident strings */
255 [ # # ]: 0 : for (i = 0; i < fpga_info->n_phy_ports; i++) {
256 [ # # ]: 0 : if (p_adapter_info->mp_port_id_str[i]) {
257 : 0 : free(p_adapter_info->mp_port_id_str[i]);
258 : 0 : p_adapter_info->mp_port_id_str[i] = NULL;
259 : : }
260 : : }
261 : :
262 : : /* Free adapter ident string */
263 [ # # ]: 0 : if (p_adapter_info->mp_adapter_id_str) {
264 : 0 : free(p_adapter_info->mp_adapter_id_str);
265 : 0 : p_adapter_info->mp_adapter_id_str = NULL;
266 : : }
267 : :
268 : : /* Free devname ident string */
269 [ # # ]: 0 : if (p_adapter_info->p_dev_name) {
270 : 0 : free(p_adapter_info->p_dev_name);
271 : 0 : p_adapter_info->p_dev_name = NULL;
272 : : }
273 : :
274 : : return res;
275 : : }
276 : :
277 : : static const struct adapter_ops ops = {
278 : : .init = nt4ga_adapter_init,
279 : : .deinit = nt4ga_adapter_deinit,
280 : :
281 : : .show_info = nt4ga_adapter_show_info,
282 : : };
283 : :
284 : 0 : void nthw_adapter_init(void)
285 : : {
286 : 0 : nthw_reg_adapter_ops(&ops);
287 : 0 : }
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