Branch data Line data Source code
1 : : /* SPDX-License-Identifier: BSD-3-Clause
2 : : * Copyright (c) 2022 NVIDIA Corporation & Affiliates
3 : : */
4 : :
5 : : #include <rte_flow.h>
6 : : #include <rte_flow_driver.h>
7 : : #include <rte_stdatomic.h>
8 : :
9 : : #include <mlx5_malloc.h>
10 : :
11 : : #include "mlx5.h"
12 : : #include "mlx5_common.h"
13 : : #include "mlx5_defs.h"
14 : : #include "mlx5_flow.h"
15 : : #include "mlx5_flow_os.h"
16 : : #include "mlx5_rx.h"
17 : :
18 : : #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
19 : : #include "mlx5_hws_cnt.h"
20 : :
21 : : /** Fast path async flow API functions. */
22 : : static struct rte_flow_fp_ops mlx5_flow_hw_fp_ops;
23 : :
24 : : /*
25 : : * The default ipool threshold value indicates which per_core_cache
26 : : * value to set.
27 : : */
28 : : #define MLX5_HW_IPOOL_SIZE_THRESHOLD (1 << 19)
29 : : /* The default min local cache size. */
30 : : #define MLX5_HW_IPOOL_CACHE_MIN (1 << 9)
31 : :
32 : : /* Default push burst threshold. */
33 : : #define BURST_THR 32u
34 : :
35 : : /* Default queue to flush the flows. */
36 : : #define MLX5_DEFAULT_FLUSH_QUEUE 0
37 : :
38 : : /* Maximum number of rules in control flow tables. */
39 : : #define MLX5_HW_CTRL_FLOW_NB_RULES (4096)
40 : :
41 : : /* Lowest flow group usable by an application if group translation is done. */
42 : : #define MLX5_HW_LOWEST_USABLE_GROUP (1)
43 : :
44 : : /* Maximum group index usable by user applications for transfer flows. */
45 : : #define MLX5_HW_MAX_TRANSFER_GROUP (UINT32_MAX - 1)
46 : :
47 : : /* Maximum group index usable by user applications for egress flows. */
48 : : #define MLX5_HW_MAX_EGRESS_GROUP (UINT32_MAX - 1)
49 : :
50 : : /* Lowest priority for HW root table. */
51 : : #define MLX5_HW_LOWEST_PRIO_ROOT 15
52 : :
53 : : /* Lowest priority for HW non-root table. */
54 : : #define MLX5_HW_LOWEST_PRIO_NON_ROOT (UINT32_MAX)
55 : :
56 : : /* Priorities for Rx control flow rules. */
57 : : #define MLX5_HW_CTRL_RX_PRIO_L2 (MLX5_HW_LOWEST_PRIO_ROOT)
58 : : #define MLX5_HW_CTRL_RX_PRIO_L3 (MLX5_HW_LOWEST_PRIO_ROOT - 1)
59 : : #define MLX5_HW_CTRL_RX_PRIO_L4 (MLX5_HW_LOWEST_PRIO_ROOT - 2)
60 : :
61 : : #define MLX5_HW_VLAN_PUSH_TYPE_IDX 0
62 : : #define MLX5_HW_VLAN_PUSH_VID_IDX 1
63 : : #define MLX5_HW_VLAN_PUSH_PCP_IDX 2
64 : :
65 : : #define MLX5_HW_PORT_IS_PROXY(priv) \
66 : : (!!((priv)->sh->esw_mode && (priv)->master))
67 : :
68 : :
69 : : struct mlx5_indlst_legacy {
70 : : struct mlx5_indirect_list indirect;
71 : : struct rte_flow_action_handle *handle;
72 : : enum rte_flow_action_type legacy_type;
73 : : };
74 : :
75 : : #define MLX5_CONST_ENCAP_ITEM(encap_type, ptr) \
76 : : (((const struct encap_type *)(ptr))->definition)
77 : :
78 : : /**
79 : : * Returns the size of a struct with a following layout:
80 : : *
81 : : * @code{.c}
82 : : * struct rte_flow_hw {
83 : : * // rte_flow_hw fields
84 : : * uint8_t rule[mlx5dr_rule_get_handle_size()];
85 : : * };
86 : : * @endcode
87 : : *
88 : : * Such struct is used as a basic container for HW Steering flow rule.
89 : : */
90 : : static size_t
91 : : mlx5_flow_hw_entry_size(void)
92 : : {
93 : 0 : return sizeof(struct rte_flow_hw) + mlx5dr_rule_get_handle_size();
94 : : }
95 : :
96 : : /**
97 : : * Returns the size of "auxed" rte_flow_hw structure which is assumed to be laid out as follows:
98 : : *
99 : : * @code{.c}
100 : : * struct {
101 : : * struct rte_flow_hw {
102 : : * // rte_flow_hw fields
103 : : * uint8_t rule[mlx5dr_rule_get_handle_size()];
104 : : * } flow;
105 : : * struct rte_flow_hw_aux aux;
106 : : * };
107 : : * @endcode
108 : : *
109 : : * Such struct is used whenever rte_flow_hw_aux cannot be allocated separately from the rte_flow_hw
110 : : * e.g., when table is resizable.
111 : : */
112 : : static size_t
113 : : mlx5_flow_hw_auxed_entry_size(void)
114 : : {
115 : 0 : size_t rule_size = mlx5dr_rule_get_handle_size();
116 : :
117 : 0 : return sizeof(struct rte_flow_hw) + rule_size + sizeof(struct rte_flow_hw_aux);
118 : : }
119 : :
120 : : /**
121 : : * Returns a valid pointer to rte_flow_hw_aux associated with given rte_flow_hw
122 : : * depending on template table configuration.
123 : : */
124 : : static __rte_always_inline struct rte_flow_hw_aux *
125 : : mlx5_flow_hw_aux(uint16_t port_id, struct rte_flow_hw *flow)
126 : : {
127 : 0 : struct rte_flow_template_table *table = flow->table;
128 : :
129 : 0 : if (!flow->nt_rule) {
130 [ # # # # : 0 : if (rte_flow_template_table_resizable(port_id, &table->cfg.attr)) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # #
# ]
131 : 0 : size_t offset = sizeof(struct rte_flow_hw) + mlx5dr_rule_get_handle_size();
132 : :
133 : 0 : return RTE_PTR_ADD(flow, offset);
134 : : } else {
135 : 0 : return &table->flow_aux[flow->idx - 1];
136 : : }
137 : : } else {
138 : 0 : return flow->nt2hws->flow_aux;
139 : : }
140 : : }
141 : :
142 : : static __rte_always_inline void
143 : : mlx5_flow_hw_aux_set_age_idx(struct rte_flow_hw *flow,
144 : : struct rte_flow_hw_aux *aux,
145 : : uint32_t age_idx)
146 : : {
147 : : /*
148 : : * Only when creating a flow rule, the type will be set explicitly.
149 : : * Or else, it should be none in the rule update case.
150 : : */
151 [ # # # # : 0 : if (unlikely(flow->operation_type == MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE))
# # # # #
# # # # #
# # # # #
# ]
152 : 0 : aux->upd.age_idx = age_idx;
153 : : else
154 : 0 : aux->orig.age_idx = age_idx;
155 : : }
156 : :
157 : : static __rte_always_inline uint32_t
158 : : mlx5_flow_hw_aux_get_age_idx(struct rte_flow_hw *flow, struct rte_flow_hw_aux *aux)
159 : : {
160 [ # # # # : 0 : if (unlikely(flow->operation_type == MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE))
# # # # #
# # # ]
161 : 0 : return aux->upd.age_idx;
162 : : else
163 : 0 : return aux->orig.age_idx;
164 : : }
165 : :
166 : : static __rte_always_inline void
167 : : mlx5_flow_hw_aux_set_mtr_id(struct rte_flow_hw *flow,
168 : : struct rte_flow_hw_aux *aux,
169 : : uint32_t mtr_id)
170 : : {
171 [ # # # # : 0 : if (unlikely(flow->operation_type == MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE))
# # # # #
# ]
172 : 0 : aux->upd.mtr_id = mtr_id;
173 : : else
174 : 0 : aux->orig.mtr_id = mtr_id;
175 : : }
176 : :
177 : : static __rte_always_inline uint32_t
178 : : mlx5_flow_hw_aux_get_mtr_id(struct rte_flow_hw *flow, struct rte_flow_hw_aux *aux)
179 : : {
180 [ # # ]: 0 : if (unlikely(flow->operation_type == MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE))
181 : 0 : return aux->upd.mtr_id;
182 : : else
183 : 0 : return aux->orig.mtr_id;
184 : : }
185 : :
186 : : static __rte_always_inline struct mlx5_hw_q_job *
187 : : flow_hw_action_job_init(struct mlx5_priv *priv, uint32_t queue,
188 : : const struct rte_flow_action_handle *handle,
189 : : void *user_data, void *query_data,
190 : : enum mlx5_hw_job_type type,
191 : : enum mlx5_hw_indirect_type indirect_type,
192 : : struct rte_flow_error *error);
193 : : static void
194 : : flow_hw_age_count_release(struct mlx5_priv *priv, uint32_t queue, struct rte_flow_hw *flow,
195 : : struct rte_flow_error *error);
196 : :
197 : : static int
198 : : mlx5_tbl_multi_pattern_process(struct rte_eth_dev *dev,
199 : : struct rte_flow_template_table *tbl,
200 : : struct mlx5_multi_pattern_segment *segment,
201 : : uint32_t bulk_size,
202 : : struct rte_flow_error *error);
203 : : static void
204 : : mlx5_destroy_multi_pattern_segment(struct mlx5_multi_pattern_segment *segment);
205 : :
206 : : static __rte_always_inline enum mlx5_indirect_list_type
207 : : flow_hw_inlist_type_get(const struct rte_flow_action *actions);
208 : :
209 : : static int
210 : : flow_hw_allocate_actions(struct rte_eth_dev *dev,
211 : : uint64_t action_flags,
212 : : struct rte_flow_error *error);
213 : :
214 : : static int
215 : : flow_hw_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
216 : : const struct rte_flow_item items[],
217 : : const struct rte_flow_action actions[],
218 : : bool external __rte_unused, int hairpin __rte_unused,
219 : : struct rte_flow_error *error);
220 : :
221 : : bool
222 : 0 : mlx5_hw_ctx_validate(const struct rte_eth_dev *dev, struct rte_flow_error *error)
223 : : {
224 : 0 : const struct mlx5_priv *priv = dev->data->dev_private;
225 : :
226 [ # # ]: 0 : if (!priv->dr_ctx) {
227 : 0 : rte_flow_error_set(error, EINVAL,
228 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
229 : : "non-template flow engine was not configured");
230 : 0 : return false;
231 : : }
232 : : return true;
233 : : }
234 : :
235 : : static int
236 : : flow_hw_allocate_actions(struct rte_eth_dev *dev,
237 : : uint64_t action_flags,
238 : : struct rte_flow_error *error);
239 : :
240 : : static __rte_always_inline int
241 : : mlx5_multi_pattern_reformat_to_index(enum mlx5dr_action_type type)
242 : : {
243 : : switch (type) {
244 : : case MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2:
245 : : return 0;
246 : : case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2:
247 : : return 1;
248 : : case MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2:
249 : : return 2;
250 : : case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3:
251 : : return 3;
252 : : default:
253 : : break;
254 : : }
255 : : return -1;
256 : : }
257 : :
258 : : /* Include only supported reformat actions for BWC non template API. */
259 : : static __rte_always_inline int
260 : : mlx5_bwc_multi_pattern_reformat_to_index(enum mlx5dr_action_type type)
261 : : {
262 : 0 : switch (type) {
263 : : case MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2:
264 : : case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2:
265 : : case MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2:
266 : : case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3:
267 : : return mlx5_multi_pattern_reformat_to_index(type);
268 : : default:
269 : : break;
270 : : }
271 : : return -1;
272 : : }
273 : :
274 : : static __rte_always_inline enum mlx5dr_action_type
275 : : mlx5_multi_pattern_reformat_index_to_type(uint32_t ix)
276 : : {
277 : : switch (ix) {
278 : : case 0:
279 : : return MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2;
280 : : case 1:
281 : : return MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;
282 : : case 2:
283 : : return MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2;
284 : : case 3:
285 : : return MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3;
286 : : default:
287 : : break;
288 : : }
289 : : return MLX5DR_ACTION_TYP_MAX;
290 : : }
291 : :
292 : : static inline enum mlx5dr_table_type
293 : : get_mlx5dr_fdb_table_type(const struct rte_flow_attr *attr,
294 : : uint32_t specialize, bool fdb_unified_en)
295 : : {
296 [ # # # # ]: 0 : if (fdb_unified_en && !!attr->group) {
297 [ # # ]: 0 : if ((specialize & (RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_WIRE_ORIG |
298 : : RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_VPORT_ORIG)) == 0)
299 : : return MLX5DR_TABLE_TYPE_FDB_UNIFIED;
300 : : MLX5_ASSERT((specialize & (RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_WIRE_ORIG |
301 : : RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_VPORT_ORIG)) !=
302 : : (RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_WIRE_ORIG |
303 : : RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_VPORT_ORIG));
304 [ # # ]: 0 : if (specialize & RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_WIRE_ORIG)
305 : : return MLX5DR_TABLE_TYPE_FDB_RX;
306 [ # # ]: 0 : if (specialize & RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_VPORT_ORIG)
307 : 0 : return MLX5DR_TABLE_TYPE_FDB_TX;
308 : : }
309 : :
310 : : return MLX5DR_TABLE_TYPE_FDB;
311 : : }
312 : :
313 : : static inline enum mlx5dr_table_type
314 : 0 : get_mlx5dr_table_type(const struct rte_flow_attr *attr, uint32_t specialize,
315 : : bool fdb_unified_en)
316 : : {
317 : : enum mlx5dr_table_type type;
318 : :
319 [ # # ]: 0 : if (attr->transfer)
320 : : type = get_mlx5dr_fdb_table_type(attr, specialize, fdb_unified_en);
321 [ # # ]: 0 : else if (attr->egress)
322 : : type = MLX5DR_TABLE_TYPE_NIC_TX;
323 : : else
324 : : type = MLX5DR_TABLE_TYPE_NIC_RX;
325 : 0 : return type;
326 : : }
327 : :
328 : : /* Non template default queue size used for inner ctrl queue. */
329 : : #define MLX5_NT_DEFAULT_QUEUE_SIZE 32
330 : :
331 : : static int flow_hw_flush_all_ctrl_flows(struct rte_eth_dev *dev);
332 : : static int flow_hw_translate_group(struct rte_eth_dev *dev,
333 : : const struct mlx5_flow_template_table_cfg *cfg,
334 : : uint32_t group,
335 : : uint32_t *table_group,
336 : : struct rte_flow_error *error);
337 : : static __rte_always_inline int
338 : : flow_hw_set_vlan_vid_construct(struct rte_eth_dev *dev,
339 : : struct mlx5_modification_cmd *mhdr_cmd,
340 : : struct mlx5_action_construct_data *act_data,
341 : : const struct mlx5_hw_actions *hw_acts,
342 : : const struct rte_flow_action *action);
343 : : static void
344 : : flow_hw_construct_quota(struct mlx5_priv *priv,
345 : : struct mlx5dr_rule_action *rule_act, uint32_t qid);
346 : :
347 : : static int
348 : : mlx5_flow_ct_init(struct rte_eth_dev *dev,
349 : : uint32_t nb_conn_tracks,
350 : : uint16_t nb_queue);
351 : :
352 : : static __rte_always_inline uint32_t flow_hw_tx_tag_regc_mask(struct rte_eth_dev *dev);
353 : : static __rte_always_inline uint32_t flow_hw_tx_tag_regc_value(struct rte_eth_dev *dev);
354 : :
355 : : static int flow_hw_async_create_validate(struct rte_eth_dev *dev,
356 : : const uint32_t queue,
357 : : const struct rte_flow_template_table *table,
358 : : enum rte_flow_table_insertion_type insertion_type,
359 : : const uint32_t rule_index,
360 : : const struct rte_flow_item items[],
361 : : const uint8_t pattern_template_index,
362 : : const struct rte_flow_action actions[],
363 : : const uint8_t action_template_index,
364 : : struct rte_flow_error *error);
365 : : static int flow_hw_async_update_validate(struct rte_eth_dev *dev,
366 : : const uint32_t queue,
367 : : const struct rte_flow_hw *flow,
368 : : const struct rte_flow_action actions[],
369 : : const uint8_t action_template_index,
370 : : struct rte_flow_error *error);
371 : : static int flow_hw_async_destroy_validate(struct rte_eth_dev *dev,
372 : : const uint32_t queue,
373 : : const struct rte_flow_hw *flow,
374 : : struct rte_flow_error *error);
375 : :
376 : : const struct mlx5_flow_driver_ops mlx5_flow_hw_drv_ops;
377 : :
378 : : /* DR action flags with different table. */
379 : : static uint32_t mlx5_hw_act_flag[MLX5_HW_ACTION_FLAG_MAX]
380 : : [MLX5DR_TABLE_TYPE_MAX] = {
381 : : {
382 : : MLX5DR_ACTION_FLAG_ROOT_RX,
383 : : MLX5DR_ACTION_FLAG_ROOT_TX,
384 : : MLX5DR_ACTION_FLAG_ROOT_FDB,
385 : : MLX5DR_ACTION_FLAG_ROOT_FDB,
386 : : MLX5DR_ACTION_FLAG_ROOT_FDB,
387 : : MLX5DR_ACTION_FLAG_ROOT_FDB,
388 : : },
389 : : {
390 : : MLX5DR_ACTION_FLAG_HWS_RX,
391 : : MLX5DR_ACTION_FLAG_HWS_TX,
392 : : MLX5DR_ACTION_FLAG_HWS_FDB,
393 : : MLX5DR_ACTION_FLAG_HWS_FDB_RX,
394 : : MLX5DR_ACTION_FLAG_HWS_FDB_TX,
395 : : MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED,
396 : : },
397 : : };
398 : :
399 : : /**
400 : : * Jump table flags.
401 : : * Can jump to FDB_RX table from FDB_RX or UNIFIED tables.
402 : : * Can jump to FDB_TX table from FDB_TX or UNIFIED tables.
403 : : * Can jump to UNIFIED table from all tables.
404 : : */
405 : : static uint32_t mlx5_hw_act_dest_table_flag[MLX5DR_TABLE_TYPE_MAX] = {
406 : : MLX5DR_ACTION_FLAG_HWS_RX,
407 : : MLX5DR_ACTION_FLAG_HWS_TX,
408 : : MLX5DR_ACTION_FLAG_HWS_FDB,
409 : : (MLX5DR_ACTION_FLAG_HWS_FDB_RX | MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED),
410 : : (MLX5DR_ACTION_FLAG_HWS_FDB_TX | MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED),
411 : : (MLX5DR_ACTION_FLAG_HWS_FDB_RX | MLX5DR_ACTION_FLAG_HWS_FDB_TX |
412 : : MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED),
413 : : };
414 : :
415 : : /* Ethernet item spec for promiscuous mode. */
416 : : static const struct rte_flow_item_eth ctrl_rx_eth_promisc_spec = {
417 : : .hdr.dst_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
418 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
419 : : .hdr.ether_type = 0,
420 : : };
421 : : /* Ethernet item mask for promiscuous mode. */
422 : : static const struct rte_flow_item_eth ctrl_rx_eth_promisc_mask = {
423 : : .hdr.dst_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
424 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
425 : : .hdr.ether_type = 0,
426 : : };
427 : :
428 : : /* Ethernet item spec for all multicast mode. */
429 : : static const struct rte_flow_item_eth ctrl_rx_eth_mcast_spec = {
430 : : .hdr.dst_addr.addr_bytes = { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 },
431 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
432 : : .hdr.ether_type = 0,
433 : : };
434 : : /* Ethernet item mask for all multicast mode. */
435 : : static const struct rte_flow_item_eth ctrl_rx_eth_mcast_mask = {
436 : : .hdr.dst_addr.addr_bytes = { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 },
437 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
438 : : .hdr.ether_type = 0,
439 : : };
440 : :
441 : : /* Ethernet item spec for IPv4 multicast traffic. */
442 : : static const struct rte_flow_item_eth ctrl_rx_eth_ipv4_mcast_spec = {
443 : : .hdr.dst_addr.addr_bytes = { 0x01, 0x00, 0x5e, 0x00, 0x00, 0x00 },
444 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
445 : : .hdr.ether_type = 0,
446 : : };
447 : : /* Ethernet item mask for IPv4 multicast traffic. */
448 : : static const struct rte_flow_item_eth ctrl_rx_eth_ipv4_mcast_mask = {
449 : : .hdr.dst_addr.addr_bytes = { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 },
450 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
451 : : .hdr.ether_type = 0,
452 : : };
453 : :
454 : : /* Ethernet item spec for IPv6 multicast traffic. */
455 : : static const struct rte_flow_item_eth ctrl_rx_eth_ipv6_mcast_spec = {
456 : : .hdr.dst_addr.addr_bytes = { 0x33, 0x33, 0x00, 0x00, 0x00, 0x00 },
457 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
458 : : .hdr.ether_type = 0,
459 : : };
460 : : /* Ethernet item mask for IPv6 multicast traffic. */
461 : : static const struct rte_flow_item_eth ctrl_rx_eth_ipv6_mcast_mask = {
462 : : .hdr.dst_addr.addr_bytes = { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 },
463 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
464 : : .hdr.ether_type = 0,
465 : : };
466 : :
467 : : /* Ethernet item mask for unicast traffic. */
468 : : static const struct rte_flow_item_eth ctrl_rx_eth_dmac_mask = {
469 : : .hdr.dst_addr.addr_bytes = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
470 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
471 : : .hdr.ether_type = 0,
472 : : };
473 : :
474 : : /* Ethernet item spec for broadcast. */
475 : : static const struct rte_flow_item_eth ctrl_rx_eth_bcast_spec = {
476 : : .hdr.dst_addr.addr_bytes = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
477 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
478 : : .hdr.ether_type = 0,
479 : : };
480 : :
481 : : static inline uint32_t
482 : : flow_hw_q_pending(struct mlx5_priv *priv, uint32_t queue)
483 : : {
484 : 0 : struct mlx5_hw_q *q = &priv->hw_q[queue];
485 : :
486 : : MLX5_ASSERT(q->size >= q->job_idx);
487 : 0 : return (q->size - q->job_idx) + q->ongoing_flow_ops;
488 : : }
489 : :
490 : : static inline void
491 : 0 : flow_hw_q_inc_flow_ops(struct mlx5_priv *priv, uint32_t queue)
492 : : {
493 : 0 : struct mlx5_hw_q *q = &priv->hw_q[queue];
494 : :
495 : 0 : q->ongoing_flow_ops++;
496 : 0 : }
497 : :
498 : : static inline void
499 : : flow_hw_q_dec_flow_ops(struct mlx5_priv *priv, uint32_t queue)
500 : : {
501 : 0 : struct mlx5_hw_q *q = &priv->hw_q[queue];
502 : :
503 : 0 : q->ongoing_flow_ops--;
504 : : }
505 : :
506 : : static inline enum mlx5dr_matcher_insert_mode
507 : : flow_hw_matcher_insert_mode_get(enum rte_flow_table_insertion_type insert_type)
508 : : {
509 : 0 : if (insert_type == RTE_FLOW_TABLE_INSERTION_TYPE_PATTERN)
510 : : return MLX5DR_MATCHER_INSERT_BY_HASH;
511 : : else
512 : 0 : return MLX5DR_MATCHER_INSERT_BY_INDEX;
513 : : }
514 : :
515 : : static inline enum mlx5dr_matcher_distribute_mode
516 : : flow_hw_matcher_distribute_mode_get(enum rte_flow_table_hash_func hash_func)
517 : : {
518 [ # # ]: 0 : if (hash_func == RTE_FLOW_TABLE_HASH_FUNC_LINEAR)
519 : : return MLX5DR_MATCHER_DISTRIBUTE_BY_LINEAR;
520 : : else
521 : 0 : return MLX5DR_MATCHER_DISTRIBUTE_BY_HASH;
522 : : }
523 : :
524 : : /**
525 : : * Set the hash fields according to the @p rss_desc information.
526 : : *
527 : : * @param[in] rss_desc
528 : : * Pointer to the mlx5_flow_rss_desc.
529 : : * @param[out] hash_fields
530 : : * Pointer to the RSS hash fields.
531 : : */
532 : : static void
533 : 0 : flow_hw_hashfields_set(struct mlx5_flow_rss_desc *rss_desc,
534 : : uint64_t *hash_fields)
535 : : {
536 : : uint64_t fields = 0;
537 : : int rss_inner = 0;
538 [ # # ]: 0 : uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
539 : :
540 : : #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
541 [ # # ]: 0 : if (rss_desc->level >= 2)
542 : : rss_inner = 1;
543 : : #endif
544 [ # # ]: 0 : if (rss_types & MLX5_IPV4_LAYER_TYPES) {
545 [ # # ]: 0 : if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
546 : : fields |= IBV_RX_HASH_SRC_IPV4;
547 [ # # ]: 0 : else if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
548 : : fields |= IBV_RX_HASH_DST_IPV4;
549 : : else
550 : : fields |= MLX5_IPV4_IBV_RX_HASH;
551 [ # # ]: 0 : } else if (rss_types & MLX5_IPV6_LAYER_TYPES) {
552 [ # # ]: 0 : if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
553 : : fields |= IBV_RX_HASH_SRC_IPV6;
554 [ # # ]: 0 : else if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
555 : : fields |= IBV_RX_HASH_DST_IPV6;
556 : : else
557 : : fields |= MLX5_IPV6_IBV_RX_HASH;
558 : : }
559 [ # # ]: 0 : if (rss_types & RTE_ETH_RSS_UDP) {
560 [ # # ]: 0 : if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
561 : 0 : fields |= IBV_RX_HASH_SRC_PORT_UDP;
562 [ # # ]: 0 : else if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
563 : 0 : fields |= IBV_RX_HASH_DST_PORT_UDP;
564 : : else
565 : 0 : fields |= MLX5_UDP_IBV_RX_HASH;
566 [ # # ]: 0 : } else if (rss_types & RTE_ETH_RSS_TCP) {
567 [ # # ]: 0 : if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
568 : 0 : fields |= IBV_RX_HASH_SRC_PORT_TCP;
569 [ # # ]: 0 : else if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
570 : 0 : fields |= IBV_RX_HASH_DST_PORT_TCP;
571 : : else
572 : 0 : fields |= MLX5_TCP_IBV_RX_HASH;
573 : : }
574 [ # # ]: 0 : if (rss_types & RTE_ETH_RSS_ESP)
575 : 0 : fields |= IBV_RX_HASH_IPSEC_SPI;
576 [ # # ]: 0 : if (rss_inner)
577 : 0 : fields |= IBV_RX_HASH_INNER;
578 : 0 : *hash_fields |= fields;
579 : 0 : }
580 : :
581 : : uint64_t
582 : 0 : mlx5_flow_hw_action_flags_get(const struct rte_flow_action actions[],
583 : : const struct rte_flow_action **qrss,
584 : : const struct rte_flow_action **mark,
585 : : int *encap_idx,
586 : : int *act_cnt,
587 : : struct rte_flow_error *error)
588 : : {
589 : : uint64_t action_flags = 0;
590 : : const struct rte_flow_action *action;
591 : : const struct rte_flow_action_raw_encap *raw_encap;
592 : : int raw_decap_idx = -1;
593 : : int action_idx;
594 : :
595 : 0 : *encap_idx = -1;
596 : : action_idx = 0;
597 [ # # ]: 0 : for (action = actions; action->type != RTE_FLOW_ACTION_TYPE_END; action++) {
598 : 0 : int type = (int)action->type;
599 [ # # # # : 0 : switch (type) {
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
600 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT:
601 [ # # # # : 0 : switch (MLX5_INDIRECT_ACTION_TYPE_GET(action->conf)) {
# # ]
602 : 0 : case MLX5_INDIRECT_ACTION_TYPE_RSS:
603 : 0 : goto rss;
604 : 0 : case MLX5_INDIRECT_ACTION_TYPE_AGE:
605 : 0 : goto age;
606 : 0 : case MLX5_INDIRECT_ACTION_TYPE_COUNT:
607 : 0 : goto count;
608 : 0 : case MLX5_INDIRECT_ACTION_TYPE_CT:
609 : 0 : goto ct;
610 : 0 : case MLX5_INDIRECT_ACTION_TYPE_METER_MARK:
611 : 0 : goto meter;
612 : 0 : default:
613 : 0 : goto error;
614 : : }
615 : : break;
616 : 0 : case RTE_FLOW_ACTION_TYPE_DROP:
617 : 0 : action_flags |= MLX5_FLOW_ACTION_DROP;
618 : 0 : break;
619 : 0 : case RTE_FLOW_ACTION_TYPE_FLAG:
620 : 0 : action_flags |= MLX5_FLOW_ACTION_FLAG;
621 : 0 : break;
622 : 0 : case RTE_FLOW_ACTION_TYPE_MARK:
623 : 0 : action_flags |= MLX5_FLOW_ACTION_MARK;
624 : 0 : *mark = action;
625 : 0 : break;
626 : 0 : case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
627 : 0 : action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
628 : 0 : break;
629 : 0 : case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
630 : 0 : action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
631 : 0 : break;
632 : 0 : case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
633 : 0 : action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
634 : 0 : break;
635 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP:
636 : 0 : action_flags |= MLX5_FLOW_ACTION_JUMP;
637 : 0 : break;
638 : 0 : case RTE_FLOW_ACTION_TYPE_QUEUE:
639 : 0 : action_flags |= MLX5_FLOW_ACTION_QUEUE;
640 : 0 : *qrss = action;
641 : 0 : break;
642 : : case RTE_FLOW_ACTION_TYPE_RSS:
643 : 0 : rss:
644 : 0 : action_flags |= MLX5_FLOW_ACTION_RSS;
645 : 0 : *qrss = action;
646 : 0 : break;
647 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
648 : : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
649 : 0 : action_flags |= MLX5_FLOW_ACTION_ENCAP;
650 : 0 : *encap_idx = action_idx;
651 : 0 : break;
652 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
653 : 0 : action_flags |= MLX5_FLOW_ACTION_ENCAP;
654 : 0 : raw_encap = action->conf;
655 [ # # ]: 0 : if (raw_encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
656 : 0 : *encap_idx = raw_decap_idx != -1 ?
657 [ # # ]: 0 : raw_decap_idx : action_idx;
658 : : break;
659 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
660 : : case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
661 : 0 : action_flags |= MLX5_FLOW_ACTION_DECAP;
662 : 0 : break;
663 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
664 : 0 : action_flags |= MLX5_FLOW_ACTION_DECAP;
665 : : raw_decap_idx = action_idx;
666 : 0 : break;
667 : 0 : case RTE_FLOW_ACTION_TYPE_SEND_TO_KERNEL:
668 : 0 : action_flags |= MLX5_FLOW_ACTION_SEND_TO_KERNEL;
669 : 0 : break;
670 : 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
671 : 0 : action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
672 : 0 : break;
673 : 0 : case RTE_FLOW_ACTION_TYPE_PORT_ID:
674 : : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
675 : 0 : action_flags |= MLX5_FLOW_ACTION_PORT_ID;
676 : 0 : break;
677 : : case RTE_FLOW_ACTION_TYPE_AGE:
678 : 0 : age:
679 : 0 : action_flags |= MLX5_FLOW_ACTION_AGE;
680 : 0 : break;
681 : : case RTE_FLOW_ACTION_TYPE_COUNT:
682 : 0 : count:
683 : 0 : action_flags |= MLX5_FLOW_ACTION_COUNT;
684 : 0 : break;
685 : : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
686 : 0 : ct:
687 : 0 : action_flags |= MLX5_FLOW_ACTION_CT;
688 : 0 : break;
689 : : case RTE_FLOW_ACTION_TYPE_METER_MARK:
690 : 0 : meter:
691 : 0 : action_flags |= MLX5_FLOW_ACTION_METER;
692 : 0 : break;
693 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
694 : 0 : action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
695 : 0 : break;
696 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
697 : 0 : action_flags |= MLX5_FLOW_ACTION_JUMP_TO_TABLE_INDEX;
698 : 0 : break;
699 : 0 : case RTE_FLOW_ACTION_TYPE_SAMPLE:
700 : 0 : action_flags |= MLX5_FLOW_ACTION_SAMPLE;
701 : 0 : break;
702 : : case RTE_FLOW_ACTION_TYPE_VOID:
703 : : case RTE_FLOW_ACTION_TYPE_END:
704 : : break;
705 : 0 : default:
706 : 0 : goto error;
707 : : }
708 : 0 : action_idx++;
709 : : }
710 [ # # ]: 0 : if (*encap_idx == -1)
711 : 0 : *encap_idx = action_idx;
712 : 0 : action_idx++; /* The END action. */
713 : 0 : *act_cnt = action_idx;
714 : 0 : return action_flags;
715 : 0 : error:
716 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
717 : : action, "invalid flow action");
718 : 0 : return 0;
719 : : }
720 : :
721 : : /**
722 : : * Register destination table DR jump action.
723 : : *
724 : : * @param[in] dev
725 : : * Pointer to the rte_eth_dev structure.
726 : : * @param[in] table_attr
727 : : * Pointer to the flow attributes.
728 : : * @param[in] dest_group
729 : : * The destination group ID.
730 : : * @param[out] error
731 : : * Pointer to error structure.
732 : : *
733 : : * @return
734 : : * Table on success, NULL otherwise and rte_errno is set.
735 : : */
736 : : static struct mlx5_hw_jump_action *
737 : 0 : flow_hw_jump_action_register(struct rte_eth_dev *dev,
738 : : const struct mlx5_flow_template_table_cfg *cfg,
739 : : uint32_t dest_group,
740 : : struct rte_flow_error *error)
741 : : {
742 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
743 : 0 : struct rte_flow_attr jattr = cfg->attr.flow_attr;
744 : 0 : uint32_t specialize = cfg->attr.specialize;
745 : : struct mlx5_flow_group *grp;
746 : 0 : struct mlx5_flow_cb_ctx ctx = {
747 : : .dev = dev,
748 : : .error = error,
749 : : .data = &jattr,
750 : : .data2 = &specialize,
751 : : };
752 : : struct mlx5_list_entry *ge;
753 : : uint32_t target_group;
754 : :
755 : 0 : target_group = dest_group;
756 [ # # ]: 0 : if (flow_hw_translate_group(dev, cfg, dest_group, &target_group, error))
757 : : return NULL;
758 : 0 : jattr.group = target_group;
759 : 0 : ge = mlx5_hlist_register(priv->sh->flow_tbls, target_group, &ctx);
760 [ # # ]: 0 : if (!ge)
761 : : return NULL;
762 : : grp = container_of(ge, struct mlx5_flow_group, entry);
763 : 0 : return &grp->jump;
764 : : }
765 : :
766 : : /**
767 : : * Release jump action.
768 : : *
769 : : * @param[in] dev
770 : : * Pointer to the rte_eth_dev structure.
771 : : * @param[in] jump
772 : : * Pointer to the jump action.
773 : : */
774 : :
775 : : static void
776 : : flow_hw_jump_release(struct rte_eth_dev *dev, struct mlx5_hw_jump_action *jump)
777 : : {
778 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
779 : : struct mlx5_flow_group *grp;
780 : :
781 : 0 : grp = container_of(jump, struct mlx5_flow_group, jump);
782 : 0 : mlx5_hlist_unregister(priv->sh->flow_tbls, &grp->entry);
783 : 0 : }
784 : :
785 : : /**
786 : : * Register queue/RSS action.
787 : : *
788 : : * @param[in] dev
789 : : * Pointer to the rte_eth_dev structure.
790 : : * @param[in] hws_flags
791 : : * DR action flags.
792 : : * @param[in] action
793 : : * rte flow action.
794 : : * @param[in] item_flags
795 : : * Item flags for non template rule.
796 : : * @param[in] is_template
797 : : * True if it is a template rule.
798 : : *
799 : : * @return
800 : : * Table on success, NULL otherwise and rte_errno is set.
801 : : */
802 : : static inline struct mlx5_hrxq*
803 : 0 : flow_hw_tir_action_register(struct rte_eth_dev *dev,
804 : : uint32_t hws_flags,
805 : : const struct rte_flow_action *action)
806 : : {
807 : 0 : struct mlx5_flow_rss_desc rss_desc = {
808 : : .hws_flags = hws_flags,
809 : : };
810 : : struct mlx5_hrxq *hrxq;
811 : :
812 [ # # ]: 0 : if (action->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
813 : 0 : const struct rte_flow_action_queue *queue = action->conf;
814 : :
815 : 0 : rss_desc.const_q = &queue->index;
816 : 0 : rss_desc.queue_num = 1;
817 : : } else {
818 : 0 : const struct rte_flow_action_rss *rss = action->conf;
819 : :
820 : 0 : rss_desc.queue_num = rss->queue_num;
821 : 0 : rss_desc.const_q = rss->queue;
822 : 0 : memcpy(rss_desc.key,
823 [ # # ]: 0 : !rss->key ? rss_hash_default_key : rss->key,
824 : : MLX5_RSS_HASH_KEY_LEN);
825 : 0 : rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
826 [ # # ]: 0 : rss_desc.types = !rss->types ? RTE_ETH_RSS_IP : rss->types;
827 : 0 : rss_desc.symmetric_hash_function = MLX5_RSS_IS_SYMM(rss->func);
828 : 0 : flow_hw_hashfields_set(&rss_desc, &rss_desc.hash_fields);
829 : 0 : flow_dv_action_rss_l34_hash_adjust(rss->types,
830 : : &rss_desc.hash_fields);
831 [ # # ]: 0 : if (rss->level > 1) {
832 : 0 : rss_desc.hash_fields |= IBV_RX_HASH_INNER;
833 : 0 : rss_desc.tunnel = 1;
834 : : }
835 : : }
836 : 0 : hrxq = mlx5_hrxq_get(dev, &rss_desc);
837 : 0 : return hrxq;
838 : : }
839 : :
840 : : static __rte_always_inline int
841 : : flow_hw_ct_compile(struct rte_eth_dev *dev,
842 : : uint32_t queue, uint32_t idx,
843 : : struct mlx5dr_rule_action *rule_act)
844 : : {
845 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
846 : : struct mlx5_aso_ct_action *ct;
847 : :
848 : 0 : ct = mlx5_ipool_get(priv->hws_ctpool->cts, idx);
849 [ # # # # : 0 : if (!ct || (!priv->shared_host && mlx5_aso_ct_available(priv->sh, queue, ct)))
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # ]
850 : : return -1;
851 : 0 : rule_act->action = priv->hws_ctpool->dr_action;
852 : 0 : rule_act->aso_ct.offset = ct->offset;
853 : 0 : rule_act->aso_ct.direction = ct->is_original ?
854 : 0 : MLX5DR_ACTION_ASO_CT_DIRECTION_INITIATOR :
855 : : MLX5DR_ACTION_ASO_CT_DIRECTION_RESPONDER;
856 : : return 0;
857 : : }
858 : :
859 : : static void
860 : : flow_hw_template_destroy_reformat_action(struct mlx5_hw_encap_decap_action *encap_decap)
861 : : {
862 [ # # # # ]: 0 : if (encap_decap->action && !encap_decap->multi_pattern)
863 : 0 : mlx5dr_action_destroy(encap_decap->action);
864 : : }
865 : :
866 : : static void
867 : : flow_hw_template_destroy_mhdr_action(struct mlx5_hw_modify_header_action *mhdr)
868 : : {
869 [ # # # # ]: 0 : if (mhdr->action && !mhdr->multi_pattern)
870 : 0 : mlx5dr_action_destroy(mhdr->action);
871 : : }
872 : :
873 : : /**
874 : : * Destroy DR actions created by action template.
875 : : *
876 : : * For DR actions created during table creation's action translate.
877 : : * Need to destroy the DR action when destroying the table.
878 : : *
879 : : * @param[in] dev
880 : : * Pointer to the rte_eth_dev structure.
881 : : * @param[in] acts
882 : : * Pointer to the template HW steering DR actions.
883 : : */
884 : : static void
885 : 0 : __flow_hw_actions_release(struct rte_eth_dev *dev, struct mlx5_hw_actions *acts)
886 : : {
887 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
888 : :
889 [ # # ]: 0 : if (acts->mark)
890 [ # # ]: 0 : if (!(rte_atomic_fetch_sub_explicit(&priv->hws_mark_refcnt, 1,
891 : : rte_memory_order_relaxed) - 1))
892 : 0 : flow_hw_rxq_flag_set(dev, false);
893 : :
894 [ # # ]: 0 : if (acts->jump) {
895 : : struct mlx5_flow_group *grp;
896 : :
897 : 0 : grp = container_of
898 : : (acts->jump, struct mlx5_flow_group, jump);
899 : 0 : mlx5_hlist_unregister(priv->sh->flow_tbls, &grp->entry);
900 : 0 : acts->jump = NULL;
901 : : }
902 [ # # ]: 0 : if (acts->tir) {
903 : 0 : mlx5_hrxq_release(dev, acts->tir->idx);
904 : 0 : acts->tir = NULL;
905 : : }
906 [ # # ]: 0 : if (acts->encap_decap) {
907 : : flow_hw_template_destroy_reformat_action(acts->encap_decap);
908 : 0 : mlx5_free(acts->encap_decap);
909 : 0 : acts->encap_decap = NULL;
910 : : }
911 [ # # ]: 0 : if (acts->push_remove) {
912 [ # # ]: 0 : if (acts->push_remove->action)
913 : 0 : mlx5dr_action_destroy(acts->push_remove->action);
914 : 0 : mlx5_free(acts->push_remove);
915 : 0 : acts->push_remove = NULL;
916 : : }
917 [ # # ]: 0 : if (acts->mhdr) {
918 : : flow_hw_template_destroy_mhdr_action(acts->mhdr);
919 : 0 : mlx5_free(acts->mhdr);
920 : 0 : acts->mhdr = NULL;
921 : : }
922 [ # # ]: 0 : if (mlx5_hws_cnt_id_valid(acts->cnt_id)) {
923 [ # # ]: 0 : mlx5_hws_cnt_shared_put(priv->hws_cpool, &acts->cnt_id);
924 : 0 : acts->cnt_id = 0;
925 : : }
926 [ # # ]: 0 : if (acts->mtr_id) {
927 : 0 : mlx5_ipool_free(priv->hws_mpool->idx_pool, acts->mtr_id);
928 : 0 : acts->mtr_id = 0;
929 : : }
930 : 0 : }
931 : :
932 : : /**
933 : : * Release the action data back into the pool without destroy any action.
934 : : *
935 : : * @param[in] dev
936 : : * Pointer to the rte_eth_dev structure.
937 : : * @param[in] acts
938 : : * Pointer to the template HW steering DR actions.
939 : : */
940 : : static inline void
941 : 0 : __flow_hw_act_data_flush(struct rte_eth_dev *dev, struct mlx5_hw_actions *acts)
942 : : {
943 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
944 : : struct mlx5_action_construct_data *data;
945 : :
946 [ # # ]: 0 : while (!LIST_EMPTY(&acts->act_list)) {
947 : : data = LIST_FIRST(&acts->act_list);
948 [ # # ]: 0 : LIST_REMOVE(data, next);
949 : 0 : mlx5_ipool_free(priv->acts_ipool, data->idx);
950 : : }
951 : 0 : }
952 : :
953 : : /*
954 : : * Destroy DR actions created by action template.
955 : : *
956 : : * For DR actions created during table creation's action translate.
957 : : * Need to destroy the DR action when destroying the table.
958 : : *
959 : : * @param[in] dev
960 : : * Pointer to the rte_eth_dev structure.
961 : : * @param[in] acts
962 : : * Pointer to the template HW steering DR actions.
963 : : */
964 : : static void
965 : 0 : __flow_hw_action_template_destroy(struct rte_eth_dev *dev, struct mlx5_hw_actions *acts)
966 : : {
967 : 0 : __flow_hw_act_data_flush(dev, acts);
968 : 0 : __flow_hw_actions_release(dev, acts);
969 : 0 : }
970 : :
971 : : /**
972 : : * Append dynamic action to the dynamic action list.
973 : : *
974 : : * @param[in] priv
975 : : * Pointer to the port private data structure.
976 : : * @param[in] acts
977 : : * Pointer to the template HW steering DR actions.
978 : : * @param[in] type
979 : : * Action type.
980 : : * @param[in] action_src
981 : : * Offset of source rte flow action.
982 : : * @param[in] action_dst
983 : : * Offset of destination DR action.
984 : : *
985 : : * @return
986 : : * 0 on success, negative value otherwise and rte_errno is set.
987 : : */
988 : : static __rte_always_inline struct mlx5_action_construct_data *
989 : : __flow_hw_act_data_alloc(struct mlx5_priv *priv,
990 : : enum rte_flow_action_type type,
991 : : uint16_t action_src,
992 : : uint16_t action_dst)
993 : : {
994 : : struct mlx5_action_construct_data *act_data;
995 : 0 : uint32_t idx = 0;
996 : :
997 : 0 : act_data = mlx5_ipool_zmalloc(priv->acts_ipool, &idx);
998 [ # # # # : 0 : if (!act_data)
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
999 : : return NULL;
1000 : 0 : act_data->idx = idx;
1001 : 0 : act_data->type = type;
1002 : 0 : act_data->action_src = action_src;
1003 : 0 : act_data->action_dst = action_dst;
1004 : : return act_data;
1005 : : }
1006 : :
1007 : : /**
1008 : : * Append dynamic action to the dynamic action list.
1009 : : *
1010 : : * @param[in] priv
1011 : : * Pointer to the port private data structure.
1012 : : * @param[in] acts
1013 : : * Pointer to the template HW steering DR actions.
1014 : : * @param[in] type
1015 : : * Action type.
1016 : : * @param[in] action_src
1017 : : * Offset of source rte flow action.
1018 : : * @param[in] action_dst
1019 : : * Offset of destination DR action.
1020 : : *
1021 : : * @return
1022 : : * 0 on success, negative value otherwise and rte_errno is set.
1023 : : */
1024 : : static __rte_always_inline int
1025 : : __flow_hw_act_data_general_append(struct mlx5_priv *priv,
1026 : : struct mlx5_hw_actions *acts,
1027 : : enum rte_flow_action_type type,
1028 : : uint16_t action_src,
1029 : : uint16_t action_dst)
1030 : : {
1031 : : struct mlx5_action_construct_data *act_data;
1032 : :
1033 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1034 : : if (!act_data)
1035 : : return -1;
1036 [ # # # # : 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
1037 : : return 0;
1038 : : }
1039 : :
1040 : : static __rte_always_inline int
1041 : : __flow_hw_act_data_indirect_append(struct mlx5_priv *priv,
1042 : : struct mlx5_hw_actions *acts,
1043 : : enum rte_flow_action_type type,
1044 : : enum rte_flow_action_type mask_type,
1045 : : uint16_t action_src,
1046 : : uint16_t action_dst)
1047 : : {
1048 : : struct mlx5_action_construct_data *act_data;
1049 : :
1050 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1051 : : if (!act_data)
1052 : : return -1;
1053 : 0 : act_data->indirect.expected_type = mask_type;
1054 [ # # ]: 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
1055 : : return 0;
1056 : : }
1057 : :
1058 : : static __rte_always_inline int
1059 : : flow_hw_act_data_indirect_list_append(struct mlx5_priv *priv,
1060 : : struct mlx5_hw_actions *acts,
1061 : : enum rte_flow_action_type type,
1062 : : uint16_t action_src, uint16_t action_dst,
1063 : : indirect_list_callback_t cb)
1064 : : {
1065 : : struct mlx5_action_construct_data *act_data;
1066 : :
1067 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1068 : : if (!act_data)
1069 : 0 : return -1;
1070 : 0 : act_data->indirect_list_cb = cb;
1071 [ # # # # : 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
# # ]
1072 : 0 : return 0;
1073 : : }
1074 : : /**
1075 : : * Append dynamic encap action to the dynamic action list.
1076 : : *
1077 : : * @param[in] priv
1078 : : * Pointer to the port private data structure.
1079 : : * @param[in] acts
1080 : : * Pointer to the template HW steering DR actions.
1081 : : * @param[in] type
1082 : : * Action type.
1083 : : * @param[in] action_src
1084 : : * Offset of source rte flow action.
1085 : : * @param[in] action_dst
1086 : : * Offset of destination DR action.
1087 : : * @param[in] len
1088 : : * Length of the data to be updated.
1089 : : *
1090 : : * @return
1091 : : * 0 on success, negative value otherwise and rte_errno is set.
1092 : : */
1093 : : static __rte_always_inline int
1094 : : __flow_hw_act_data_encap_append(struct mlx5_priv *priv,
1095 : : struct mlx5_hw_actions *acts,
1096 : : enum rte_flow_action_type type,
1097 : : uint16_t action_src,
1098 : : uint16_t action_dst,
1099 : : uint16_t len)
1100 : : {
1101 : : struct mlx5_action_construct_data *act_data;
1102 : :
1103 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1104 : : if (!act_data)
1105 : : return -1;
1106 : 0 : act_data->encap.len = len;
1107 [ # # ]: 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
1108 : : return 0;
1109 : : }
1110 : :
1111 : : /**
1112 : : * Append dynamic push action to the dynamic action list.
1113 : : *
1114 : : * @param[in] dev
1115 : : * Pointer to the port.
1116 : : * @param[in] acts
1117 : : * Pointer to the template HW steering DR actions.
1118 : : * @param[in] type
1119 : : * Action type.
1120 : : * @param[in] action_src
1121 : : * Offset of source rte flow action.
1122 : : * @param[in] action_dst
1123 : : * Offset of destination DR action.
1124 : : * @param[in] len
1125 : : * Length of the data to be updated.
1126 : : *
1127 : : * @return
1128 : : * Data pointer on success, NULL otherwise and rte_errno is set.
1129 : : */
1130 : : static __rte_always_inline void *
1131 : : __flow_hw_act_data_push_append(struct rte_eth_dev *dev,
1132 : : struct mlx5_hw_actions *acts,
1133 : : enum rte_flow_action_type type,
1134 : : uint16_t action_src,
1135 : : uint16_t action_dst,
1136 : : uint16_t len)
1137 : : {
1138 : : struct mlx5_action_construct_data *act_data;
1139 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1140 : :
1141 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1142 : : if (!act_data)
1143 : : return NULL;
1144 : 0 : act_data->ipv6_ext.len = len;
1145 [ # # ]: 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
1146 : : return act_data;
1147 : : }
1148 : :
1149 : : static __rte_always_inline int
1150 : : __flow_hw_act_data_hdr_modify_append(struct mlx5_priv *priv,
1151 : : struct mlx5_hw_actions *acts,
1152 : : enum rte_flow_action_type type,
1153 : : uint16_t action_src,
1154 : : uint16_t action_dst,
1155 : : const struct rte_flow_action_modify_field *mf,
1156 : : uint16_t mhdr_cmds_off,
1157 : : uint16_t mhdr_cmds_end,
1158 : : bool shared,
1159 : : struct field_modify_info *field,
1160 : : struct field_modify_info *dcopy,
1161 : : uint32_t *mask)
1162 : : {
1163 : : struct mlx5_action_construct_data *act_data;
1164 : :
1165 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1166 : : if (!act_data)
1167 : : return -1;
1168 : 0 : act_data->modify_header.action = *mf;
1169 : 0 : act_data->modify_header.mhdr_cmds_off = mhdr_cmds_off;
1170 : 0 : act_data->modify_header.mhdr_cmds_end = mhdr_cmds_end;
1171 : 0 : act_data->modify_header.shared = shared;
1172 [ # # ]: 0 : rte_memcpy(act_data->modify_header.field, field,
1173 : : sizeof(*field) * MLX5_ACT_MAX_MOD_FIELDS);
1174 [ # # ]: 0 : rte_memcpy(act_data->modify_header.dcopy, dcopy,
1175 : : sizeof(*dcopy) * MLX5_ACT_MAX_MOD_FIELDS);
1176 [ # # ]: 0 : rte_memcpy(act_data->modify_header.mask, mask,
1177 : : sizeof(*mask) * MLX5_ACT_MAX_MOD_FIELDS);
1178 [ # # ]: 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
1179 : : return 0;
1180 : : }
1181 : :
1182 : : /**
1183 : : * Append shared RSS action to the dynamic action list.
1184 : : *
1185 : : * @param[in] priv
1186 : : * Pointer to the port private data structure.
1187 : : * @param[in] acts
1188 : : * Pointer to the template HW steering DR actions.
1189 : : * @param[in] type
1190 : : * Action type.
1191 : : * @param[in] action_src
1192 : : * Offset of source rte flow action.
1193 : : * @param[in] action_dst
1194 : : * Offset of destination DR action.
1195 : : * @param[in] idx
1196 : : * Shared RSS index.
1197 : : * @param[in] rss
1198 : : * Pointer to the shared RSS info.
1199 : : *
1200 : : * @return
1201 : : * 0 on success, negative value otherwise and rte_errno is set.
1202 : : */
1203 : : static __rte_always_inline int
1204 : : __flow_hw_act_data_shared_rss_append(struct mlx5_priv *priv,
1205 : : struct mlx5_hw_actions *acts,
1206 : : enum rte_flow_action_type type,
1207 : : uint16_t action_src,
1208 : : uint16_t action_dst,
1209 : : uint32_t idx,
1210 : : struct mlx5_shared_action_rss *rss)
1211 : : {
1212 : : struct mlx5_action_construct_data *act_data;
1213 : :
1214 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1215 : : if (!act_data)
1216 : : return -1;
1217 : 0 : act_data->shared_rss.level = rss->origin.level;
1218 [ # # ]: 0 : act_data->shared_rss.types = !rss->origin.types ? RTE_ETH_RSS_IP :
1219 : : rss->origin.types;
1220 : 0 : act_data->shared_rss.idx = idx;
1221 : 0 : act_data->shared_rss.symmetric_hash_function =
1222 : 0 : MLX5_RSS_IS_SYMM(rss->origin.func);
1223 [ # # ]: 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
1224 : : return 0;
1225 : : }
1226 : :
1227 : : /**
1228 : : * Append shared counter action to the dynamic action list.
1229 : : *
1230 : : * @param[in] priv
1231 : : * Pointer to the port private data structure.
1232 : : * @param[in] acts
1233 : : * Pointer to the template HW steering DR actions.
1234 : : * @param[in] type
1235 : : * Action type.
1236 : : * @param[in] action_src
1237 : : * Offset of source rte flow action.
1238 : : * @param[in] action_dst
1239 : : * Offset of destination DR action.
1240 : : * @param[in] cnt_id
1241 : : * Shared counter id.
1242 : : *
1243 : : * @return
1244 : : * 0 on success, negative value otherwise and rte_errno is set.
1245 : : */
1246 : : static __rte_always_inline int
1247 : : __flow_hw_act_data_shared_cnt_append(struct mlx5_priv *priv,
1248 : : struct mlx5_hw_actions *acts,
1249 : : enum rte_flow_action_type type,
1250 : : uint16_t action_src,
1251 : : uint16_t action_dst,
1252 : : cnt_id_t cnt_id)
1253 : : {
1254 : : struct mlx5_action_construct_data *act_data;
1255 : :
1256 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1257 : : if (!act_data)
1258 : : return -1;
1259 : : act_data->type = type;
1260 : 0 : act_data->shared_counter.id = cnt_id;
1261 [ # # ]: 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
1262 : : return 0;
1263 : : }
1264 : :
1265 : : /**
1266 : : * Append shared meter_mark action to the dynamic action list.
1267 : : *
1268 : : * @param[in] priv
1269 : : * Pointer to the port private data structure.
1270 : : * @param[in] acts
1271 : : * Pointer to the template HW steering DR actions.
1272 : : * @param[in] type
1273 : : * Action type.
1274 : : * @param[in] action_src
1275 : : * Offset of source rte flow action.
1276 : : * @param[in] action_dst
1277 : : * Offset of destination DR action.
1278 : : * @param[in] mtr_id
1279 : : * Shared meter id.
1280 : : *
1281 : : * @return
1282 : : * 0 on success, negative value otherwise and rte_errno is set.
1283 : : */
1284 : : static __rte_always_inline int
1285 : : __flow_hw_act_data_shared_mtr_append(struct mlx5_priv *priv,
1286 : : struct mlx5_hw_actions *acts,
1287 : : enum rte_flow_action_type type,
1288 : : uint16_t action_src,
1289 : : uint16_t action_dst,
1290 : : cnt_id_t mtr_id)
1291 : : { struct mlx5_action_construct_data *act_data;
1292 : :
1293 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1294 : : if (!act_data)
1295 : : return -1;
1296 : : act_data->type = type;
1297 : 0 : act_data->shared_meter.id = mtr_id;
1298 [ # # ]: 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
1299 : : return 0;
1300 : : }
1301 : :
1302 : : /**
1303 : : * Translate shared indirect action.
1304 : : *
1305 : : * @param[in] dev
1306 : : * Pointer to the rte_eth_dev data structure.
1307 : : * @param[in] action
1308 : : * Pointer to the shared indirect rte_flow action.
1309 : : * @param[in] acts
1310 : : * Pointer to the template HW steering DR actions.
1311 : : * @param[in] action_src
1312 : : * Offset of source rte flow action.
1313 : : * @param[in] action_dst
1314 : : * Offset of destination DR action.
1315 : : *
1316 : : * @return
1317 : : * 0 on success, negative value otherwise and rte_errno is set.
1318 : : */
1319 : : static __rte_always_inline int
1320 : : flow_hw_shared_action_translate(struct rte_eth_dev *dev,
1321 : : const struct rte_flow_action *action,
1322 : : struct mlx5_hw_actions *acts,
1323 : : uint16_t action_src,
1324 : : uint16_t action_dst)
1325 : : {
1326 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1327 : : struct mlx5_shared_action_rss *shared_rss;
1328 : 0 : uint32_t act_idx = (uint32_t)(uintptr_t)action->conf;
1329 : 0 : uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
1330 : 0 : uint32_t idx = act_idx &
1331 : : ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
1332 : :
1333 : 0 : switch (type) {
1334 : 0 : case MLX5_INDIRECT_ACTION_TYPE_RSS:
1335 : 0 : shared_rss = mlx5_ipool_get
1336 : 0 : (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
1337 [ # # ]: 0 : if (!shared_rss || __flow_hw_act_data_shared_rss_append
1338 : : (priv, acts,
1339 : : (enum rte_flow_action_type)MLX5_RTE_FLOW_ACTION_TYPE_RSS,
1340 : : action_src, action_dst, idx, shared_rss)) {
1341 : 0 : DRV_LOG(WARNING, "Indirect RSS action index %d translate failed", act_idx);
1342 : : return -1;
1343 : : }
1344 : : break;
1345 : 0 : case MLX5_INDIRECT_ACTION_TYPE_COUNT:
1346 : : if (__flow_hw_act_data_shared_cnt_append(priv, acts,
1347 : : (enum rte_flow_action_type)
1348 : : MLX5_RTE_FLOW_ACTION_TYPE_COUNT,
1349 : : action_src, action_dst, act_idx)) {
1350 : 0 : DRV_LOG(WARNING, "Indirect count action translate failed");
1351 : : return -1;
1352 : : }
1353 : : break;
1354 : 0 : case MLX5_INDIRECT_ACTION_TYPE_CT:
1355 : : if (flow_hw_ct_compile(dev, MLX5_HW_INV_QUEUE,
1356 : : idx, &acts->rule_acts[action_dst])) {
1357 : 0 : DRV_LOG(WARNING, "Indirect CT action translate failed");
1358 : : return -1;
1359 : : }
1360 : : break;
1361 : 0 : case MLX5_INDIRECT_ACTION_TYPE_METER_MARK:
1362 : : if (__flow_hw_act_data_shared_mtr_append(priv, acts,
1363 : : (enum rte_flow_action_type)
1364 : : MLX5_RTE_FLOW_ACTION_TYPE_METER_MARK,
1365 : : action_src, action_dst, idx)) {
1366 : 0 : DRV_LOG(WARNING, "Indirect meter mark action translate failed");
1367 : : return -1;
1368 : : }
1369 : : break;
1370 : 0 : case MLX5_INDIRECT_ACTION_TYPE_QUOTA:
1371 : : flow_hw_construct_quota(priv, &acts->rule_acts[action_dst], idx);
1372 : : break;
1373 : 0 : default:
1374 : 0 : DRV_LOG(WARNING, "Unsupported shared action type:%d", type);
1375 : : break;
1376 : : }
1377 : : return 0;
1378 : : }
1379 : :
1380 : : static __rte_always_inline bool
1381 : : flow_hw_action_modify_field_is_shared(const struct rte_flow_action *action,
1382 : : const struct rte_flow_action *mask)
1383 : : {
1384 : : const struct rte_flow_action_modify_field *v = action->conf;
1385 : 0 : const struct rte_flow_action_modify_field *m = mask->conf;
1386 : :
1387 : 0 : if (v->src.field == RTE_FLOW_FIELD_VALUE) {
1388 : : uint32_t j;
1389 : :
1390 [ # # ]: 0 : for (j = 0; j < RTE_DIM(m->src.value); ++j) {
1391 : : /*
1392 : : * Immediate value is considered to be masked
1393 : : * (and thus shared by all flow rules), if mask
1394 : : * is non-zero. Partial mask over immediate value
1395 : : * is not allowed.
1396 : : */
1397 [ # # ]: 0 : if (m->src.value[j])
1398 : : return true;
1399 : : }
1400 : : return false;
1401 : : }
1402 [ # # ]: 0 : if (v->src.field == RTE_FLOW_FIELD_POINTER)
1403 : 0 : return m->src.pvalue != NULL;
1404 : : /*
1405 : : * Source field types other than VALUE and
1406 : : * POINTER are always shared.
1407 : : */
1408 : : return true;
1409 : : }
1410 : :
1411 : : static __rte_always_inline bool
1412 : : flow_hw_should_insert_nop(const struct mlx5_hw_modify_header_action *mhdr,
1413 : : const struct mlx5_modification_cmd *cmd,
1414 : : const struct rte_flow_attr *attr)
1415 : : {
1416 : : struct mlx5_modification_cmd last_cmd = { { 0 } };
1417 : : struct mlx5_modification_cmd new_cmd = { { 0 } };
1418 : 0 : const uint32_t cmds_num = mhdr->mhdr_cmds_num;
1419 : : unsigned int last_type;
1420 : : bool should_insert = false;
1421 : :
1422 : : /*
1423 : : * Modify header action list does not require NOPs in root table,
1424 : : * because different type of underlying object is used:
1425 : : * - in root table - MODIFY_HEADER_CONTEXT (does not require NOPs),
1426 : : * - in non-root - either inline modify action or based on Modify Header Pattern
1427 : : * (which requires NOPs).
1428 : : */
1429 [ # # # # ]: 0 : if (attr->group == 0)
1430 : : return false;
1431 [ # # # # ]: 0 : if (cmds_num == 0)
1432 : : return false;
1433 : 0 : last_cmd = *(&mhdr->mhdr_cmds[cmds_num - 1]);
1434 [ # # # # ]: 0 : last_cmd.data0 = rte_be_to_cpu_32(last_cmd.data0);
1435 [ # # # # ]: 0 : last_cmd.data1 = rte_be_to_cpu_32(last_cmd.data1);
1436 : 0 : last_type = last_cmd.action_type;
1437 : 0 : new_cmd = *cmd;
1438 [ # # # # ]: 0 : new_cmd.data0 = rte_be_to_cpu_32(new_cmd.data0);
1439 [ # # # # ]: 0 : new_cmd.data1 = rte_be_to_cpu_32(new_cmd.data1);
1440 [ # # # # : 0 : switch (new_cmd.action_type) {
# # ]
1441 : 0 : case MLX5_MODIFICATION_TYPE_SET:
1442 : : case MLX5_MODIFICATION_TYPE_ADD:
1443 [ # # # # ]: 0 : if (last_type == MLX5_MODIFICATION_TYPE_SET ||
1444 : : last_type == MLX5_MODIFICATION_TYPE_ADD)
1445 : 0 : should_insert = new_cmd.field == last_cmd.field;
1446 : 0 : else if (last_type == MLX5_MODIFICATION_TYPE_COPY ||
1447 [ # # # # ]: 0 : last_type == MLX5_MODIFICATION_TYPE_ADD_FIELD)
1448 : 0 : should_insert = new_cmd.field == last_cmd.dst_field;
1449 : : else if (last_type == MLX5_MODIFICATION_TYPE_NOP)
1450 : : should_insert = false;
1451 : : else
1452 : : MLX5_ASSERT(false); /* Other types are not supported. */
1453 : : break;
1454 : 0 : case MLX5_MODIFICATION_TYPE_COPY:
1455 : : case MLX5_MODIFICATION_TYPE_ADD_FIELD:
1456 [ # # # # ]: 0 : if (last_type == MLX5_MODIFICATION_TYPE_SET ||
1457 : : last_type == MLX5_MODIFICATION_TYPE_ADD)
1458 [ # # # # ]: 0 : should_insert = (new_cmd.field == last_cmd.field ||
1459 [ # # # # ]: 0 : new_cmd.dst_field == last_cmd.field);
1460 : 0 : else if (last_type == MLX5_MODIFICATION_TYPE_COPY ||
1461 [ # # # # ]: 0 : last_type == MLX5_MODIFICATION_TYPE_ADD_FIELD)
1462 [ # # # # ]: 0 : should_insert = (new_cmd.field == last_cmd.dst_field ||
1463 [ # # # # ]: 0 : new_cmd.dst_field == last_cmd.dst_field);
1464 : : else if (last_type == MLX5_MODIFICATION_TYPE_NOP)
1465 : : should_insert = false;
1466 : : else
1467 : : MLX5_ASSERT(false); /* Other types are not supported. */
1468 : : break;
1469 : : default:
1470 : : /* Other action types should be rejected on AT validation. */
1471 : : MLX5_ASSERT(false);
1472 : : break;
1473 : : }
1474 : : return should_insert;
1475 : : }
1476 : :
1477 : : static __rte_always_inline int
1478 : : flow_hw_mhdr_cmd_nop_append(struct mlx5_hw_modify_header_action *mhdr)
1479 : : {
1480 : : struct mlx5_modification_cmd *nop;
1481 : : uint32_t num = mhdr->mhdr_cmds_num;
1482 : :
1483 [ # # # # ]: 0 : if (num + 1 >= MLX5_MHDR_MAX_CMD)
1484 : : return -ENOMEM;
1485 : 0 : nop = mhdr->mhdr_cmds + num;
1486 : : nop->data0 = 0;
1487 : : nop->action_type = MLX5_MODIFICATION_TYPE_NOP;
1488 : 0 : nop->data0 = rte_cpu_to_be_32(nop->data0);
1489 : 0 : nop->data1 = 0;
1490 : 0 : mhdr->mhdr_cmds_num = num + 1;
1491 : : return 0;
1492 : : }
1493 : :
1494 : : static __rte_always_inline int
1495 : : flow_hw_mhdr_cmd_append(struct mlx5_hw_modify_header_action *mhdr,
1496 : : struct mlx5_modification_cmd *cmd)
1497 : : {
1498 : 0 : uint32_t num = mhdr->mhdr_cmds_num;
1499 : :
1500 [ # # ]: 0 : if (num + 1 >= MLX5_MHDR_MAX_CMD)
1501 : : return -ENOMEM;
1502 : 0 : mhdr->mhdr_cmds[num] = *cmd;
1503 : 0 : mhdr->mhdr_cmds_num = num + 1;
1504 : : return 0;
1505 : : }
1506 : :
1507 : : static __rte_always_inline int
1508 : : flow_hw_converted_mhdr_cmds_append(struct mlx5_hw_modify_header_action *mhdr,
1509 : : struct mlx5_flow_dv_modify_hdr_resource *resource,
1510 : : const struct rte_flow_attr *attr)
1511 : : {
1512 : : uint32_t idx;
1513 : : int ret;
1514 : :
1515 [ # # ]: 0 : for (idx = 0; idx < resource->actions_num; ++idx) {
1516 : : struct mlx5_modification_cmd *src = &resource->actions[idx];
1517 : :
1518 [ # # ]: 0 : if (flow_hw_should_insert_nop(mhdr, src, attr)) {
1519 : : ret = flow_hw_mhdr_cmd_nop_append(mhdr);
1520 : : if (ret)
1521 : : return ret;
1522 : : }
1523 : : ret = flow_hw_mhdr_cmd_append(mhdr, src);
1524 : : if (ret)
1525 : : return ret;
1526 : : }
1527 : : return 0;
1528 : : }
1529 : :
1530 : : static __rte_always_inline void
1531 : : flow_hw_modify_field_init(struct mlx5_hw_modify_header_action *mhdr,
1532 : : struct rte_flow_actions_template *at)
1533 : : {
1534 : : memset(mhdr, 0, sizeof(*mhdr));
1535 : : /* Modify header action without any commands is shared by default. */
1536 : 0 : mhdr->shared = true;
1537 : 0 : mhdr->pos = at->mhdr_off;
1538 : : }
1539 : :
1540 : : static __rte_always_inline int
1541 : : flow_hw_modify_field_compile(struct rte_eth_dev *dev,
1542 : : const struct rte_flow_attr *attr,
1543 : : const struct rte_flow_action *action, /* Current action from AT. */
1544 : : const struct rte_flow_action *action_mask, /* Current mask from AT. */
1545 : : struct mlx5_hw_actions *acts,
1546 : : struct mlx5_hw_modify_header_action *mhdr,
1547 : : uint16_t src_pos,
1548 : : struct rte_flow_error *error)
1549 : : {
1550 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1551 : 0 : const struct rte_flow_action_modify_field *conf = action->conf;
1552 : : union {
1553 : : struct mlx5_flow_dv_modify_hdr_resource resource;
1554 : : uint8_t data[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
1555 : : sizeof(struct mlx5_modification_cmd) * MLX5_MHDR_MAX_CMD];
1556 : : } dummy;
1557 : : struct mlx5_flow_dv_modify_hdr_resource *resource;
1558 : 0 : struct rte_flow_item item = {
1559 : : .spec = NULL,
1560 : : .mask = NULL
1561 : : };
1562 : 0 : struct field_modify_info field[MLX5_ACT_MAX_MOD_FIELDS] = {
1563 : : {0, 0, MLX5_MODI_OUT_NONE} };
1564 : 0 : struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {
1565 : : {0, 0, MLX5_MODI_OUT_NONE} };
1566 : 0 : uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = { 0 };
1567 : 0 : uint32_t type, value = 0;
1568 : : uint16_t cmds_start, cmds_end;
1569 : : bool shared;
1570 : : int ret;
1571 : :
1572 : : /*
1573 : : * Modify header action is shared if previous modify_field actions
1574 : : * are shared and currently compiled action is shared.
1575 : : */
1576 : : shared = flow_hw_action_modify_field_is_shared(action, action_mask);
1577 : 0 : mhdr->shared &= shared;
1578 [ # # ]: 0 : if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
1579 : : conf->src.field == RTE_FLOW_FIELD_VALUE) {
1580 [ # # ]: 0 : type = conf->operation == RTE_FLOW_MODIFY_SET ? MLX5_MODIFICATION_TYPE_SET :
1581 : : MLX5_MODIFICATION_TYPE_ADD;
1582 : : /* For SET/ADD fill the destination field (field) first. */
1583 : 0 : mlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,
1584 : 0 : conf->width, dev,
1585 : : attr, error);
1586 : 0 : item.spec = conf->src.field == RTE_FLOW_FIELD_POINTER ?
1587 [ # # ]: 0 : (void *)(uintptr_t)conf->src.pvalue :
1588 : : (void *)(uintptr_t)&conf->src.value;
1589 [ # # ]: 0 : if (conf->dst.field == RTE_FLOW_FIELD_META ||
1590 [ # # ]: 0 : conf->dst.field == RTE_FLOW_FIELD_TAG ||
1591 [ # # ]: 0 : conf->dst.field == RTE_FLOW_FIELD_METER_COLOR ||
1592 : 0 : conf->dst.field == (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG) {
1593 : : uint8_t tag_index = flow_tag_index_get(&conf->dst);
1594 : :
1595 : 0 : value = *(const unaligned_uint32_t *)item.spec;
1596 [ # # # # ]: 0 : if (conf->dst.field == RTE_FLOW_FIELD_TAG &&
1597 : : tag_index == RTE_PMD_MLX5_LINEAR_HASH_TAG_INDEX)
1598 [ # # ]: 0 : value = rte_cpu_to_be_32(value << 16);
1599 : : else
1600 [ # # ]: 0 : value = rte_cpu_to_be_32(value);
1601 : 0 : item.spec = &value;
1602 [ # # ]: 0 : } else if (conf->dst.field == RTE_FLOW_FIELD_GTP_PSC_QFI ||
1603 : : conf->dst.field == RTE_FLOW_FIELD_GENEVE_OPT_TYPE) {
1604 : : /*
1605 : : * Both QFI and Geneve option type are passed as an uint8_t integer,
1606 : : * but it is accessed through a 2nd least significant byte of a 32-bit
1607 : : * field in modify header command.
1608 : : */
1609 : 0 : value = *(const uint8_t *)item.spec;
1610 [ # # ]: 0 : value = rte_cpu_to_be_32(value << 8);
1611 : 0 : item.spec = &value;
1612 [ # # ]: 0 : } else if (conf->dst.field == RTE_FLOW_FIELD_VXLAN_LAST_RSVD) {
1613 : 0 : value = *(const uint8_t *)item.spec << 24;
1614 [ # # ]: 0 : value = rte_cpu_to_be_32(value);
1615 : 0 : item.spec = &value;
1616 : : }
1617 : : } else {
1618 : 0 : type = conf->operation == RTE_FLOW_MODIFY_SET ?
1619 [ # # ]: 0 : MLX5_MODIFICATION_TYPE_COPY : MLX5_MODIFICATION_TYPE_ADD_FIELD;
1620 : : /* For COPY fill the destination field (dcopy) without mask. */
1621 : 0 : mlx5_flow_field_id_to_modify_info(&conf->dst, dcopy, NULL,
1622 : 0 : conf->width, dev,
1623 : : attr, error);
1624 : : /* Then construct the source field (field) with mask. */
1625 : 0 : mlx5_flow_field_id_to_modify_info(&conf->src, field, mask,
1626 : 0 : conf->width, dev,
1627 : : attr, error);
1628 : : }
1629 : 0 : item.mask = &mask;
1630 : : memset(&dummy, 0, sizeof(dummy));
1631 : : resource = &dummy.resource;
1632 : 0 : ret = flow_dv_convert_modify_action(&item, field, dcopy, resource, type, error);
1633 [ # # ]: 0 : if (ret)
1634 : : return ret;
1635 : : MLX5_ASSERT(resource->actions_num > 0);
1636 : : /*
1637 : : * If previous modify field action collide with this one, then insert NOP command.
1638 : : * This NOP command will not be a part of action's command range used to update commands
1639 : : * on rule creation.
1640 : : */
1641 [ # # ]: 0 : if (flow_hw_should_insert_nop(mhdr, &resource->actions[0], attr)) {
1642 : : ret = flow_hw_mhdr_cmd_nop_append(mhdr);
1643 : : if (ret)
1644 : 0 : return rte_flow_error_set(error, ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1645 : : NULL, "too many modify field operations specified");
1646 : : }
1647 : 0 : cmds_start = mhdr->mhdr_cmds_num;
1648 : : ret = flow_hw_converted_mhdr_cmds_append(mhdr, resource, attr);
1649 [ # # ]: 0 : if (ret)
1650 : 0 : return rte_flow_error_set(error, ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1651 : : NULL, "too many modify field operations specified");
1652 : :
1653 : 0 : cmds_end = mhdr->mhdr_cmds_num;
1654 [ # # ]: 0 : if (shared)
1655 : : return 0;
1656 : : ret = __flow_hw_act_data_hdr_modify_append(priv, acts, RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
1657 : 0 : src_pos, mhdr->pos, conf,
1658 : : cmds_start, cmds_end, shared,
1659 : : field, dcopy, mask);
1660 : : if (ret)
1661 : 0 : return rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1662 : : NULL, "not enough memory to store modify field metadata");
1663 : : return 0;
1664 : : }
1665 : :
1666 : : static uint32_t
1667 : 0 : flow_hw_count_nop_modify_field(struct mlx5_hw_modify_header_action *mhdr)
1668 : : {
1669 : : uint32_t i;
1670 : : uint32_t nops = 0;
1671 : :
1672 [ # # ]: 0 : for (i = 0; i < mhdr->mhdr_cmds_num; ++i) {
1673 : 0 : struct mlx5_modification_cmd cmd = mhdr->mhdr_cmds[i];
1674 : :
1675 [ # # ]: 0 : cmd.data0 = rte_be_to_cpu_32(cmd.data0);
1676 [ # # ]: 0 : if (cmd.action_type == MLX5_MODIFICATION_TYPE_NOP)
1677 : 0 : ++nops;
1678 : : }
1679 : 0 : return nops;
1680 : : }
1681 : :
1682 : : static int
1683 : 0 : flow_hw_validate_compiled_modify_field(struct rte_eth_dev *dev,
1684 : : const struct mlx5_flow_template_table_cfg *cfg,
1685 : : struct mlx5_hw_modify_header_action *mhdr,
1686 : : struct rte_flow_error *error)
1687 : : {
1688 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1689 : 0 : struct mlx5_hca_attr *hca_attr = &priv->sh->cdev->config.hca_attr;
1690 : :
1691 : : /*
1692 : : * Header modify pattern length limitation is only valid for HWS groups, i.e. groups > 0.
1693 : : * In group 0, MODIFY_FIELD actions are handled with header modify actions
1694 : : * managed by rdma-core.
1695 : : */
1696 [ # # ]: 0 : if (cfg->attr.flow_attr.group != 0 &&
1697 [ # # ]: 0 : mhdr->mhdr_cmds_num > hca_attr->max_header_modify_pattern_length) {
1698 : 0 : uint32_t nops = flow_hw_count_nop_modify_field(mhdr);
1699 : :
1700 : 0 : DRV_LOG(ERR, "Too many modify header commands generated from "
1701 : : "MODIFY_FIELD actions. "
1702 : : "Generated HW commands = %u (amount of NOP commands = %u). "
1703 : : "Maximum supported = %u.",
1704 : : mhdr->mhdr_cmds_num, nops,
1705 : : hca_attr->max_header_modify_pattern_length);
1706 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1707 : : "Number of MODIFY_FIELD actions exceeds maximum "
1708 : : "supported limit of actions");
1709 : : }
1710 : : return 0;
1711 : : }
1712 : :
1713 : : static int
1714 : 0 : flow_hw_represented_port_compile(struct rte_eth_dev *dev,
1715 : : const struct rte_flow_attr *attr,
1716 : : const struct rte_flow_action *action,
1717 : : const struct rte_flow_action *action_mask,
1718 : : struct mlx5_hw_actions *acts,
1719 : : uint16_t action_src, uint16_t action_dst,
1720 : : struct rte_flow_error *error)
1721 : : {
1722 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1723 : 0 : const struct rte_flow_action_ethdev *v = action->conf;
1724 : 0 : const struct rte_flow_action_ethdev *m = action_mask->conf;
1725 : : int ret;
1726 : :
1727 [ # # ]: 0 : if (!attr->group)
1728 : 0 : return rte_flow_error_set(error, EINVAL,
1729 : : RTE_FLOW_ERROR_TYPE_ATTR, NULL,
1730 : : "represented_port action cannot"
1731 : : " be used on group 0");
1732 [ # # ]: 0 : if (!attr->transfer)
1733 : 0 : return rte_flow_error_set(error, EINVAL,
1734 : : RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER,
1735 : : NULL,
1736 : : "represented_port action requires"
1737 : : " transfer attribute");
1738 [ # # ]: 0 : if (attr->ingress || attr->egress)
1739 : 0 : return rte_flow_error_set(error, EINVAL,
1740 : : RTE_FLOW_ERROR_TYPE_ATTR, NULL,
1741 : : "represented_port action cannot"
1742 : : " be used with direction attributes");
1743 [ # # ]: 0 : if (!priv->master)
1744 : 0 : return rte_flow_error_set(error, EINVAL,
1745 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1746 : : "represented_port action must"
1747 : : " be used on proxy port");
1748 [ # # # # ]: 0 : if (m && !!m->port_id) {
1749 : : struct mlx5_priv *port_priv;
1750 : :
1751 [ # # ]: 0 : if (!v)
1752 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
1753 : : action, "port index was not provided");
1754 : 0 : port_priv = mlx5_port_to_eswitch_info(v->port_id, false);
1755 [ # # ]: 0 : if (port_priv == NULL)
1756 : 0 : return rte_flow_error_set
1757 : : (error, EINVAL,
1758 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1759 : : "port does not exist or unable to"
1760 : : " obtain E-Switch info for port");
1761 : : MLX5_ASSERT(priv->hw_vport != NULL);
1762 [ # # ]: 0 : if (priv->hw_vport[v->port_id]) {
1763 : 0 : acts->rule_acts[action_dst].action =
1764 : : priv->hw_vport[v->port_id];
1765 : : } else {
1766 : 0 : return rte_flow_error_set
1767 : : (error, EINVAL,
1768 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1769 : : "cannot use represented_port action"
1770 : : " with this port");
1771 : : }
1772 : : } else {
1773 : : ret = __flow_hw_act_data_general_append
1774 : 0 : (priv, acts, action->type,
1775 : : action_src, action_dst);
1776 : : if (ret)
1777 : 0 : return rte_flow_error_set
1778 : : (error, ENOMEM,
1779 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1780 : : "not enough memory to store"
1781 : : " vport action");
1782 : : }
1783 : : return 0;
1784 : : }
1785 : :
1786 : : static __rte_always_inline int
1787 : : flow_hw_cnt_compile(struct rte_eth_dev *dev, uint32_t start_pos,
1788 : : struct mlx5_hw_actions *acts)
1789 : : {
1790 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1791 : : uint32_t pos = start_pos;
1792 : : cnt_id_t cnt_id;
1793 : : int ret;
1794 : :
1795 : 0 : ret = mlx5_hws_cnt_shared_get(priv->hws_cpool, &cnt_id, 0);
1796 : : if (ret != 0)
1797 : : return ret;
1798 : 0 : ret = mlx5_hws_cnt_pool_get_action_offset
1799 : : (priv->hws_cpool,
1800 : : cnt_id,
1801 : : &acts->rule_acts[pos].action,
1802 : : &acts->rule_acts[pos].counter.offset);
1803 : : if (ret != 0)
1804 : : return ret;
1805 : 0 : acts->cnt_id = cnt_id;
1806 : : return 0;
1807 : : }
1808 : :
1809 : : static __rte_always_inline bool
1810 : : is_of_vlan_pcp_present(const struct rte_flow_action *actions)
1811 : : {
1812 : : /*
1813 : : * Order of RTE VLAN push actions is
1814 : : * OF_PUSH_VLAN / OF_SET_VLAN_VID [ / OF_SET_VLAN_PCP ]
1815 : : */
1816 : 0 : return actions[MLX5_HW_VLAN_PUSH_PCP_IDX].type ==
1817 : : RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP;
1818 : : }
1819 : :
1820 : : static __rte_always_inline bool
1821 : : is_template_masked_push_vlan(const struct rte_flow_action_of_push_vlan *mask)
1822 : : {
1823 : : /*
1824 : : * In masked push VLAN template all RTE push actions are masked.
1825 : : */
1826 [ # # ]: 0 : return mask && mask->ethertype != 0;
1827 : : }
1828 : :
1829 : 0 : static rte_be32_t vlan_hdr_to_be32(const struct rte_flow_action *actions)
1830 : : {
1831 : : /*
1832 : : * OpenFlow Switch Specification defines 801.1q VID as 12+1 bits.
1833 : : */
1834 : : rte_be32_t type, vid, pcp;
1835 : : #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
1836 : : rte_be32_t vid_lo, vid_hi;
1837 : : #endif
1838 : :
1839 : 0 : type = ((const struct rte_flow_action_of_push_vlan *)
1840 : 0 : actions[MLX5_HW_VLAN_PUSH_TYPE_IDX].conf)->ethertype;
1841 : 0 : vid = ((const struct rte_flow_action_of_set_vlan_vid *)
1842 : 0 : actions[MLX5_HW_VLAN_PUSH_VID_IDX].conf)->vlan_vid;
1843 : : pcp = is_of_vlan_pcp_present(actions) ?
1844 : : ((const struct rte_flow_action_of_set_vlan_pcp *)
1845 [ # # # # ]: 0 : actions[MLX5_HW_VLAN_PUSH_PCP_IDX].conf)->vlan_pcp : 0;
1846 : : #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
1847 : 0 : vid_hi = vid & 0xff;
1848 : : vid_lo = vid >> 8;
1849 : 0 : return (((vid_lo << 8) | (pcp << 5) | vid_hi) << 16) | type;
1850 : : #else
1851 : : return (type << 16) | (pcp << 13) | vid;
1852 : : #endif
1853 : : }
1854 : :
1855 : : static __rte_always_inline struct mlx5_aso_mtr *
1856 : : flow_hw_meter_mark_alloc(struct rte_eth_dev *dev, uint32_t queue,
1857 : : const struct rte_flow_action *action,
1858 : : struct mlx5_hw_q_job *job, bool push,
1859 : : struct rte_flow_error *error)
1860 : : {
1861 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1862 : 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
1863 : 0 : const struct rte_flow_action_meter_mark *meter_mark = action->conf;
1864 : : struct mlx5_aso_mtr *aso_mtr;
1865 : : struct mlx5_flow_meter_info *fm;
1866 : 0 : uint32_t mtr_id = 0;
1867 : : uintptr_t handle = (uintptr_t)MLX5_INDIRECT_ACTION_TYPE_METER_MARK <<
1868 : : MLX5_INDIRECT_ACTION_TYPE_OFFSET;
1869 : :
1870 : 0 : if (priv->shared_host) {
1871 : 0 : rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1872 : : "Meter mark actions can only be created on the host port");
1873 : : return NULL;
1874 : : }
1875 [ # # # # : 0 : if (meter_mark->profile == NULL)
# # # # #
# # # #
# ]
1876 : : return NULL;
1877 : 0 : aso_mtr = mlx5_ipool_malloc(pool->idx_pool, &mtr_id);
1878 [ # # # # : 0 : if (!aso_mtr) {
# # # # #
# # # #
# ]
1879 : 0 : rte_flow_error_set(error, ENOMEM,
1880 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1881 : : NULL,
1882 : : "failed to allocate aso meter entry");
1883 [ # # # # : 0 : if (mtr_id)
# # # # #
# # # #
# ]
1884 : 0 : mlx5_ipool_free(pool->idx_pool, mtr_id);
1885 : : return NULL;
1886 : : }
1887 : : /* Fill the flow meter parameters. */
1888 : 0 : aso_mtr->type = ASO_METER_INDIRECT;
1889 : : fm = &aso_mtr->fm;
1890 : 0 : fm->meter_id = mtr_id;
1891 : 0 : fm->profile = (struct mlx5_flow_meter_profile *)(meter_mark->profile);
1892 : 0 : fm->is_enable = meter_mark->state;
1893 : 0 : fm->color_aware = meter_mark->color_mode;
1894 : 0 : aso_mtr->pool = pool;
1895 [ # # ]: 0 : aso_mtr->state = (queue == MLX5_HW_INV_QUEUE) ?
1896 : : ASO_METER_WAIT : ASO_METER_WAIT_ASYNC;
1897 : 0 : aso_mtr->offset = mtr_id - 1;
1898 [ # # # # : 0 : aso_mtr->init_color = fm->color_aware ? RTE_COLORS : RTE_COLOR_GREEN;
# # # # #
# # # #
# ]
1899 : 0 : job->action = (void *)(handle | mtr_id);
1900 : : /* Update ASO flow meter by wqe. */
1901 [ # # # # : 0 : if (mlx5_aso_meter_update_by_wqe(priv, queue, aso_mtr,
# # # # #
# # # #
# ]
1902 : : &priv->mtr_bulk, job, push)) {
1903 : 0 : mlx5_ipool_free(pool->idx_pool, mtr_id);
1904 : : return NULL;
1905 : : }
1906 : : /* Wait for ASO object completion. */
1907 [ # # # # : 0 : if (queue == MLX5_HW_INV_QUEUE &&
# # # # #
# # # # #
# # ]
1908 : 0 : mlx5_aso_mtr_wait(priv, aso_mtr, true)) {
1909 : 0 : mlx5_ipool_free(pool->idx_pool, mtr_id);
1910 : : return NULL;
1911 : : }
1912 : : return aso_mtr;
1913 : : }
1914 : :
1915 : : static __rte_always_inline int
1916 : : flow_hw_meter_mark_compile(struct rte_eth_dev *dev,
1917 : : uint16_t aso_mtr_pos,
1918 : : const struct rte_flow_action *action,
1919 : : struct mlx5dr_rule_action *acts,
1920 : : uint32_t *index,
1921 : : uint32_t queue,
1922 : : struct rte_flow_error *error)
1923 : : {
1924 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1925 : 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
1926 : : struct mlx5_aso_mtr *aso_mtr;
1927 : : struct mlx5_hw_q_job *job =
1928 : : flow_hw_action_job_init(priv, queue, NULL, NULL, NULL,
1929 : : MLX5_HW_Q_JOB_TYPE_CREATE,
1930 : : MLX5_HW_INDIRECT_TYPE_LEGACY, NULL);
1931 : :
1932 : : if (!job)
1933 : : return -1;
1934 : : aso_mtr = flow_hw_meter_mark_alloc(dev, queue, action, job,
1935 : : true, error);
1936 : : if (!aso_mtr) {
1937 : : flow_hw_job_put(priv, job, queue);
1938 : : return -1;
1939 : : }
1940 : :
1941 : : /* Compile METER_MARK action */
1942 : 0 : acts[aso_mtr_pos].action = pool->action;
1943 : 0 : acts[aso_mtr_pos].aso_meter.offset = aso_mtr->offset;
1944 : 0 : *index = aso_mtr->fm.meter_id;
1945 : : return 0;
1946 : : }
1947 : :
1948 : : static int
1949 : 0 : flow_hw_translate_indirect_mirror(__rte_unused struct rte_eth_dev *dev,
1950 : : __rte_unused const struct mlx5_action_construct_data *act_data,
1951 : : const struct rte_flow_action *action,
1952 : : struct mlx5dr_rule_action *dr_rule)
1953 : : {
1954 : 0 : const struct rte_flow_action_indirect_list *list_conf = action->conf;
1955 : 0 : const struct mlx5_mirror *mirror = (typeof(mirror))list_conf->handle;
1956 : :
1957 : 0 : dr_rule->action = mirror->mirror_action;
1958 : 0 : return 0;
1959 : : }
1960 : :
1961 : : /**
1962 : : * HWS mirror implemented as FW island.
1963 : : * The action does not support indirect list flow configuration.
1964 : : * If template handle was masked, use handle mirror action in flow rules.
1965 : : * Otherwise let flow rule specify mirror handle.
1966 : : */
1967 : : static int
1968 : 0 : hws_table_tmpl_translate_indirect_mirror(struct rte_eth_dev *dev,
1969 : : const struct rte_flow_action *action,
1970 : : const struct rte_flow_action *mask,
1971 : : struct mlx5_hw_actions *acts,
1972 : : uint16_t action_src, uint16_t action_dst)
1973 : : {
1974 : : int ret = 0;
1975 : 0 : const struct rte_flow_action_indirect_list *mask_conf = mask->conf;
1976 : :
1977 [ # # # # ]: 0 : if (mask_conf && mask_conf->handle) {
1978 : : /**
1979 : : * If mirror handle was masked, assign fixed DR5 mirror action.
1980 : : */
1981 : : flow_hw_translate_indirect_mirror(dev, NULL, action,
1982 : 0 : &acts->rule_acts[action_dst]);
1983 : : } else {
1984 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1985 : : ret = flow_hw_act_data_indirect_list_append
1986 : : (priv, acts, RTE_FLOW_ACTION_TYPE_INDIRECT_LIST,
1987 : : action_src, action_dst,
1988 : : flow_hw_translate_indirect_mirror);
1989 : : }
1990 : :
1991 : 0 : return ret;
1992 : : }
1993 : :
1994 : : static int
1995 : 0 : flow_hw_reformat_action(__rte_unused struct rte_eth_dev *dev,
1996 : : __rte_unused const struct mlx5_action_construct_data *data,
1997 : : const struct rte_flow_action *action,
1998 : : struct mlx5dr_rule_action *dr_rule)
1999 : : {
2000 : 0 : const struct rte_flow_action_indirect_list *indlst_conf = action->conf;
2001 : :
2002 : 0 : dr_rule->action = ((struct mlx5_hw_encap_decap_action *)
2003 : 0 : (indlst_conf->handle))->action;
2004 [ # # ]: 0 : if (!dr_rule->action)
2005 : 0 : return -EINVAL;
2006 : : return 0;
2007 : : }
2008 : :
2009 : : /**
2010 : : * Template conf must not be masked. If handle is masked, use the one in template,
2011 : : * otherwise update per flow rule.
2012 : : */
2013 : : static int
2014 : 0 : hws_table_tmpl_translate_indirect_reformat(struct rte_eth_dev *dev,
2015 : : const struct rte_flow_action *action,
2016 : : const struct rte_flow_action *mask,
2017 : : struct mlx5_hw_actions *acts,
2018 : : uint16_t action_src, uint16_t action_dst)
2019 : : {
2020 : : int ret = -1;
2021 : 0 : const struct rte_flow_action_indirect_list *mask_conf = mask->conf;
2022 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
2023 : :
2024 [ # # # # : 0 : if (mask_conf && mask_conf->handle && !mask_conf->conf)
# # ]
2025 : : /**
2026 : : * If handle was masked, assign fixed DR action.
2027 : : */
2028 : : ret = flow_hw_reformat_action(dev, NULL, action,
2029 [ # # ]: 0 : &acts->rule_acts[action_dst]);
2030 [ # # # # : 0 : else if (mask_conf && !mask_conf->handle && !mask_conf->conf)
# # ]
2031 : : ret = flow_hw_act_data_indirect_list_append
2032 : : (priv, acts, RTE_FLOW_ACTION_TYPE_INDIRECT_LIST,
2033 : : action_src, action_dst, flow_hw_reformat_action);
2034 : 0 : return ret;
2035 : : }
2036 : :
2037 : : static int
2038 : 0 : flow_dr_set_meter(struct mlx5_priv *priv,
2039 : : struct mlx5dr_rule_action *dr_rule,
2040 : : const struct rte_flow_action_indirect_list *action_conf)
2041 : : {
2042 : 0 : const struct mlx5_indlst_legacy *legacy_obj =
2043 : : (typeof(legacy_obj))action_conf->handle;
2044 : 0 : struct mlx5_aso_mtr_pool *mtr_pool = priv->hws_mpool;
2045 : 0 : uint32_t act_idx = (uint32_t)(uintptr_t)legacy_obj->handle;
2046 : 0 : uint32_t mtr_id = act_idx & (RTE_BIT32(MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
2047 : 0 : struct mlx5_aso_mtr *aso_mtr = mlx5_ipool_get(mtr_pool->idx_pool, mtr_id);
2048 : :
2049 [ # # ]: 0 : if (!aso_mtr)
2050 : : return -EINVAL;
2051 : 0 : dr_rule->action = mtr_pool->action;
2052 : 0 : dr_rule->aso_meter.offset = aso_mtr->offset;
2053 : 0 : return 0;
2054 : : }
2055 : :
2056 : : __rte_always_inline static void
2057 : : flow_dr_mtr_flow_color(struct mlx5dr_rule_action *dr_rule, enum rte_color init_color)
2058 : : {
2059 : 0 : dr_rule->aso_meter.init_color =
2060 : 0 : (enum mlx5dr_action_aso_meter_color)rte_col_2_mlx5_col(init_color);
2061 : 0 : }
2062 : :
2063 : : static int
2064 : 0 : flow_hw_translate_indirect_meter(struct rte_eth_dev *dev,
2065 : : const struct mlx5_action_construct_data *act_data,
2066 : : const struct rte_flow_action *action,
2067 : : struct mlx5dr_rule_action *dr_rule)
2068 : : {
2069 : : int ret;
2070 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
2071 : 0 : const struct rte_flow_action_indirect_list *action_conf = action->conf;
2072 : 0 : const struct rte_flow_indirect_update_flow_meter_mark **flow_conf =
2073 : : (typeof(flow_conf))action_conf->conf;
2074 : :
2075 : 0 : ret = flow_dr_set_meter(priv, dr_rule, action_conf);
2076 [ # # ]: 0 : if (ret)
2077 : : return ret;
2078 [ # # ]: 0 : if (!act_data->shared_meter.conf_masked) {
2079 [ # # # # : 0 : if (flow_conf && flow_conf[0] && flow_conf[0]->init_color < RTE_COLORS)
# # ]
2080 : : flow_dr_mtr_flow_color(dr_rule, flow_conf[0]->init_color);
2081 : : }
2082 : : return 0;
2083 : : }
2084 : :
2085 : : static int
2086 : 0 : hws_table_tmpl_translate_indirect_meter(struct rte_eth_dev *dev,
2087 : : const struct rte_flow_action *action,
2088 : : const struct rte_flow_action *mask,
2089 : : struct mlx5_hw_actions *acts,
2090 : : uint16_t action_src, uint16_t action_dst)
2091 : : {
2092 : : int ret;
2093 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
2094 : 0 : const struct rte_flow_action_indirect_list *action_conf = action->conf;
2095 : 0 : const struct rte_flow_action_indirect_list *mask_conf = mask->conf;
2096 [ # # # # ]: 0 : bool is_handle_masked = mask_conf && mask_conf->handle;
2097 [ # # # # : 0 : bool is_conf_masked = mask_conf && mask_conf->conf && mask_conf->conf[0];
# # ]
2098 : 0 : struct mlx5dr_rule_action *dr_rule = &acts->rule_acts[action_dst];
2099 : :
2100 [ # # ]: 0 : if (is_handle_masked) {
2101 : 0 : ret = flow_dr_set_meter(priv, dr_rule, action->conf);
2102 [ # # ]: 0 : if (ret)
2103 : : return ret;
2104 : : }
2105 [ # # ]: 0 : if (is_conf_masked) {
2106 : : const struct
2107 : 0 : rte_flow_indirect_update_flow_meter_mark **flow_conf =
2108 : : (typeof(flow_conf))action_conf->conf;
2109 : : flow_dr_mtr_flow_color(dr_rule,
2110 [ # # ]: 0 : flow_conf[0]->init_color);
2111 : : }
2112 [ # # ]: 0 : if (!is_handle_masked || !is_conf_masked) {
2113 : : struct mlx5_action_construct_data *act_data;
2114 : :
2115 : : ret = flow_hw_act_data_indirect_list_append
2116 : : (priv, acts, RTE_FLOW_ACTION_TYPE_INDIRECT_LIST,
2117 : : action_src, action_dst, flow_hw_translate_indirect_meter);
2118 : : if (ret)
2119 : 0 : return ret;
2120 : : act_data = LIST_FIRST(&acts->act_list);
2121 : 0 : act_data->shared_meter.conf_masked = is_conf_masked;
2122 : : }
2123 : : return 0;
2124 : : }
2125 : :
2126 : : static int
2127 : : hws_table_tmpl_translate_indirect_legacy(struct rte_eth_dev *dev,
2128 : : const struct rte_flow_action *action,
2129 : : const struct rte_flow_action *mask,
2130 : : struct mlx5_hw_actions *acts,
2131 : : uint16_t action_src, uint16_t action_dst)
2132 : : {
2133 : : int ret;
2134 : : const struct rte_flow_action_indirect_list *indlst_conf = action->conf;
2135 : : struct mlx5_indlst_legacy *indlst_obj = (typeof(indlst_obj))indlst_conf->handle;
2136 : 0 : uint32_t act_idx = (uint32_t)(uintptr_t)indlst_obj->handle;
2137 : 0 : uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
2138 : :
2139 : 0 : switch (type) {
2140 : 0 : case MLX5_INDIRECT_ACTION_TYPE_METER_MARK:
2141 : 0 : ret = hws_table_tmpl_translate_indirect_meter(dev, action, mask,
2142 : : acts, action_src,
2143 : : action_dst);
2144 : 0 : break;
2145 : : default:
2146 : : ret = -EINVAL;
2147 : : break;
2148 : : }
2149 : : return ret;
2150 : : }
2151 : :
2152 : : /*
2153 : : * template .. indirect_list handle Ht conf Ct ..
2154 : : * mask .. indirect_list handle Hm conf Cm ..
2155 : : *
2156 : : * PMD requires Ht != 0 to resolve handle type.
2157 : : * If Ht was masked (Hm != 0) DR5 action will be set according to Ht and will
2158 : : * not change. Otherwise, DR5 action will be resolved during flow rule build.
2159 : : * If Ct was masked (Cm != 0), table template processing updates base
2160 : : * indirect action configuration with Ct parameters.
2161 : : */
2162 : : static int
2163 : 0 : table_template_translate_indirect_list(struct rte_eth_dev *dev,
2164 : : const struct rte_flow_action *action,
2165 : : const struct rte_flow_action *mask,
2166 : : struct mlx5_hw_actions *acts,
2167 : : uint16_t action_src, uint16_t action_dst)
2168 : : {
2169 : : int ret = 0;
2170 : : enum mlx5_indirect_list_type type;
2171 : 0 : const struct rte_flow_action_indirect_list *list_conf = action->conf;
2172 : :
2173 [ # # # # ]: 0 : if (!list_conf || !list_conf->handle)
2174 : : return -EINVAL;
2175 : : type = mlx5_get_indirect_list_type(list_conf->handle);
2176 [ # # # # ]: 0 : switch (type) {
2177 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY:
2178 [ # # ]: 0 : ret = hws_table_tmpl_translate_indirect_legacy(dev, action, mask,
2179 : : acts, action_src,
2180 : : action_dst);
2181 : : break;
2182 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR:
2183 : 0 : ret = hws_table_tmpl_translate_indirect_mirror(dev, action, mask,
2184 : : acts, action_src,
2185 : : action_dst);
2186 : 0 : break;
2187 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT:
2188 [ # # ]: 0 : if (list_conf->conf)
2189 : : return -EINVAL;
2190 : 0 : ret = hws_table_tmpl_translate_indirect_reformat(dev, action, mask,
2191 : : acts, action_src,
2192 : : action_dst);
2193 : 0 : break;
2194 : : default:
2195 : : return -EINVAL;
2196 : : }
2197 : : return ret;
2198 : : }
2199 : :
2200 : : static void
2201 : : mlx5_set_reformat_header(struct mlx5dr_action_reformat_header *hdr,
2202 : : uint8_t *encap_data,
2203 : : size_t data_size)
2204 : : {
2205 : 0 : hdr->sz = data_size;
2206 : 0 : hdr->data = encap_data;
2207 : : }
2208 : :
2209 : : static int
2210 [ # # ]: 0 : mlx5_tbl_translate_reformat(struct mlx5_priv *priv,
2211 : : struct mlx5_hw_actions *acts,
2212 : : struct rte_flow_actions_template *at,
2213 : : const struct rte_flow_item *enc_item,
2214 : : const struct rte_flow_item *enc_item_m,
2215 : : uint8_t *encap_data, uint8_t *encap_data_m,
2216 : : struct mlx5_tbl_multi_pattern_ctx *mp_ctx,
2217 : : size_t data_size, uint16_t reformat_src,
2218 : : enum mlx5dr_action_type refmt_type,
2219 : : struct rte_flow_error *error)
2220 : : {
2221 : : int mp_reformat_ix = mlx5_multi_pattern_reformat_to_index(refmt_type);
2222 : : struct mlx5dr_action_reformat_header hdr;
2223 : : uint8_t buf[MLX5_ENCAP_MAX_LEN];
2224 : : bool shared_rfmt = false;
2225 : : int ret;
2226 : :
2227 : : MLX5_ASSERT(at->reformat_off != UINT16_MAX);
2228 [ # # ]: 0 : if (enc_item) {
2229 : : MLX5_ASSERT(!encap_data);
2230 : 0 : ret = flow_dv_convert_encap_data(enc_item, buf, &data_size, error);
2231 [ # # ]: 0 : if (ret)
2232 : : return ret;
2233 : : encap_data = buf;
2234 [ # # ]: 0 : if (enc_item_m)
2235 : : shared_rfmt = true;
2236 [ # # ]: 0 : } else if (encap_data && encap_data_m) {
2237 : : shared_rfmt = true;
2238 : : }
2239 : 0 : acts->encap_decap = mlx5_malloc(MLX5_MEM_ZERO,
2240 : : sizeof(*acts->encap_decap) + data_size,
2241 : : 0, SOCKET_ID_ANY);
2242 [ # # ]: 0 : if (!acts->encap_decap)
2243 : 0 : return rte_flow_error_set(error, ENOMEM,
2244 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2245 : : NULL, "no memory for reformat context");
2246 : 0 : acts->encap_decap_pos = at->reformat_off;
2247 : 0 : acts->encap_decap->data_size = data_size;
2248 : 0 : acts->encap_decap->action_type = refmt_type;
2249 [ # # ]: 0 : if (shared_rfmt || mp_reformat_ix < 0) {
2250 : : uint16_t reformat_ix = at->reformat_off;
2251 : : /*
2252 : : * This copy is only needed in non template mode.
2253 : : * In order to create the action later.
2254 : : */
2255 : 0 : memcpy(acts->encap_decap->data, encap_data, data_size);
2256 : 0 : acts->rule_acts[reformat_ix].reformat.data = acts->encap_decap->data;
2257 : 0 : acts->rule_acts[reformat_ix].reformat.offset = 0;
2258 : 0 : acts->encap_decap->shared = true;
2259 : : } else {
2260 : : uint32_t ix;
2261 : 0 : typeof(mp_ctx->reformat[0]) *reformat = mp_ctx->reformat +
2262 : : mp_reformat_ix;
2263 : : mlx5_set_reformat_header(&hdr, encap_data, data_size);
2264 : 0 : ix = reformat->elements_num++;
2265 : 0 : reformat->reformat_hdr[ix] = hdr;
2266 : 0 : acts->rule_acts[at->reformat_off].reformat.hdr_idx = ix;
2267 : 0 : acts->encap_decap->multi_pattern = 1;
2268 : 0 : ret = __flow_hw_act_data_encap_append
2269 : 0 : (priv, acts, (at->actions + reformat_src)->type,
2270 : : reformat_src, at->reformat_off, data_size);
2271 : : if (ret)
2272 : 0 : return -rte_errno;
2273 : : mlx5_multi_pattern_activate(mp_ctx);
2274 : : }
2275 : : return 0;
2276 : : }
2277 : :
2278 : : static int
2279 : 0 : mlx5_tbl_create_reformat_action(struct mlx5_priv *priv,
2280 : : const struct rte_flow_template_table_attr *table_attr,
2281 : : struct mlx5_hw_actions *acts,
2282 : : struct rte_flow_actions_template *at,
2283 : : uint8_t *encap_data,
2284 : : size_t data_size,
2285 : : enum mlx5dr_action_type refmt_type)
2286 : : {
2287 : 0 : const struct rte_flow_attr *attr = &table_attr->flow_attr;
2288 : : bool unified_fdb = is_unified_fdb(priv);
2289 : 0 : enum mlx5dr_table_type tbl_type = get_mlx5dr_table_type(attr, table_attr->specialize,
2290 : : unified_fdb);
2291 : : struct mlx5dr_action_reformat_header hdr;
2292 : :
2293 : : mlx5_set_reformat_header(&hdr, encap_data, data_size);
2294 : 0 : uint16_t reformat_ix = at->reformat_off;
2295 : 0 : uint32_t flags = mlx5_hw_act_flag[!!attr->group][tbl_type] |
2296 : : MLX5DR_ACTION_FLAG_SHARED;
2297 : :
2298 : 0 : acts->encap_decap->action = mlx5dr_action_create_reformat(priv->dr_ctx, refmt_type,
2299 : : 1, &hdr, 0, flags);
2300 [ # # ]: 0 : if (!acts->encap_decap->action)
2301 : 0 : return -rte_errno;
2302 : 0 : acts->rule_acts[reformat_ix].action = acts->encap_decap->action;
2303 : 0 : return 0;
2304 : : }
2305 : :
2306 : : static int
2307 : 0 : mlx5_tbl_translate_modify_header(struct rte_eth_dev *dev,
2308 : : const struct mlx5_flow_template_table_cfg *cfg,
2309 : : struct mlx5_hw_actions *acts,
2310 : : struct mlx5_tbl_multi_pattern_ctx *mp_ctx,
2311 : : struct mlx5_hw_modify_header_action *mhdr,
2312 : : struct rte_flow_error *error)
2313 : : {
2314 : 0 : uint16_t mhdr_ix = mhdr->pos;
2315 : : struct mlx5dr_action_mh_pattern pattern = {
2316 : 0 : .sz = sizeof(struct mlx5_modification_cmd) * mhdr->mhdr_cmds_num
2317 : : };
2318 : :
2319 [ # # ]: 0 : if (flow_hw_validate_compiled_modify_field(dev, cfg, mhdr, error)) {
2320 : : __flow_hw_action_template_destroy(dev, acts);
2321 : 0 : return -rte_errno;
2322 : : }
2323 : 0 : acts->mhdr = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*acts->mhdr),
2324 : : 0, SOCKET_ID_ANY);
2325 [ # # ]: 0 : if (!acts->mhdr)
2326 : 0 : return rte_flow_error_set(error, ENOMEM,
2327 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2328 : : NULL, "translate modify_header: no memory for modify header context");
2329 : : rte_memcpy(acts->mhdr, mhdr, sizeof(*mhdr));
2330 [ # # ]: 0 : if (!mhdr->shared) {
2331 : 0 : pattern.data = (__be64 *)acts->mhdr->mhdr_cmds;
2332 : : typeof(mp_ctx->mh) *mh = &mp_ctx->mh;
2333 : 0 : uint32_t idx = mh->elements_num;
2334 : 0 : mh->pattern[mh->elements_num++] = pattern;
2335 : 0 : acts->mhdr->multi_pattern = 1;
2336 : 0 : acts->rule_acts[mhdr_ix].modify_header.pattern_idx = idx;
2337 : : mlx5_multi_pattern_activate(mp_ctx);
2338 : : }
2339 : : return 0;
2340 : : }
2341 : :
2342 : : static int
2343 : 0 : mlx5_tbl_ensure_shared_modify_header(struct rte_eth_dev *dev,
2344 : : const struct mlx5_flow_template_table_cfg *cfg,
2345 : : struct mlx5_hw_actions *acts,
2346 : : struct rte_flow_error *error)
2347 : : {
2348 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
2349 : : bool unified_fdb = is_unified_fdb(priv);
2350 : : const struct rte_flow_template_table_attr *table_attr = &cfg->attr;
2351 : 0 : const struct rte_flow_attr *attr = &table_attr->flow_attr;
2352 : 0 : enum mlx5dr_table_type tbl_type = get_mlx5dr_table_type(attr, table_attr->specialize,
2353 : : unified_fdb);
2354 : 0 : struct mlx5dr_action_mh_pattern pattern = {
2355 : 0 : .sz = sizeof(struct mlx5_modification_cmd) * acts->mhdr->mhdr_cmds_num
2356 : : };
2357 : 0 : uint16_t mhdr_ix = acts->mhdr->pos;
2358 : 0 : uint32_t flags = mlx5_hw_act_flag[!!attr->group][tbl_type] | MLX5DR_ACTION_FLAG_SHARED;
2359 : :
2360 : 0 : pattern.data = (__be64 *)acts->mhdr->mhdr_cmds;
2361 : 0 : acts->mhdr->action = mlx5dr_action_create_modify_header(priv->dr_ctx, 1,
2362 : : &pattern, 0, flags);
2363 [ # # ]: 0 : if (!acts->mhdr->action)
2364 : 0 : return rte_flow_error_set(error, rte_errno,
2365 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2366 : : "translate modify_header: failed to create DR action");
2367 : 0 : acts->rule_acts[mhdr_ix].action = acts->mhdr->action;
2368 : 0 : return 0;
2369 : : }
2370 : :
2371 : : static int
2372 : 0 : mlx5_create_ipv6_ext_reformat(struct rte_eth_dev *dev,
2373 : : const struct mlx5_flow_template_table_cfg *cfg,
2374 : : struct mlx5_hw_actions *acts,
2375 : : struct rte_flow_actions_template *at,
2376 : : uint8_t *push_data, uint8_t *push_data_m,
2377 : : size_t push_size, uint16_t recom_src,
2378 : : enum mlx5dr_action_type recom_type)
2379 : : {
2380 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
2381 : : bool unified_fdb = is_unified_fdb(priv);
2382 : : const struct rte_flow_template_table_attr *table_attr = &cfg->attr;
2383 : 0 : const struct rte_flow_attr *attr = &table_attr->flow_attr;
2384 : : enum mlx5dr_table_type type =
2385 : 0 : get_mlx5dr_table_type(attr, table_attr->specialize, unified_fdb);
2386 : : struct mlx5_action_construct_data *act_data;
2387 : 0 : struct mlx5dr_action_reformat_header hdr = {0};
2388 : : uint32_t flag, bulk = 0;
2389 : :
2390 : 0 : flag = mlx5_hw_act_flag[!!attr->group][type];
2391 : 0 : acts->push_remove = mlx5_malloc(MLX5_MEM_ZERO,
2392 : : sizeof(*acts->push_remove) + push_size,
2393 : : 0, SOCKET_ID_ANY);
2394 [ # # ]: 0 : if (!acts->push_remove)
2395 : : return -ENOMEM;
2396 : :
2397 [ # # # ]: 0 : switch (recom_type) {
2398 : 0 : case MLX5DR_ACTION_TYP_PUSH_IPV6_ROUTE_EXT:
2399 [ # # ]: 0 : if (!push_data || !push_size)
2400 : 0 : goto err1;
2401 [ # # ]: 0 : if (!push_data_m) {
2402 [ # # ]: 0 : bulk = rte_log2_u32(table_attr->nb_flows);
2403 : : } else {
2404 : 0 : flag |= MLX5DR_ACTION_FLAG_SHARED;
2405 : 0 : acts->push_remove->shared = 1;
2406 : : }
2407 : 0 : acts->push_remove->data_size = push_size;
2408 : 0 : memcpy(acts->push_remove->data, push_data, push_size);
2409 : 0 : hdr.data = push_data;
2410 : 0 : hdr.sz = push_size;
2411 : 0 : break;
2412 : 0 : case MLX5DR_ACTION_TYP_POP_IPV6_ROUTE_EXT:
2413 : 0 : flag |= MLX5DR_ACTION_FLAG_SHARED;
2414 : 0 : acts->push_remove->shared = 1;
2415 : 0 : break;
2416 : : default:
2417 : : break;
2418 : : }
2419 : :
2420 : 0 : acts->push_remove->action =
2421 : 0 : mlx5dr_action_create_reformat_ipv6_ext(priv->dr_ctx,
2422 : : recom_type, &hdr, bulk, flag);
2423 [ # # ]: 0 : if (!acts->push_remove->action)
2424 : 0 : goto err1;
2425 : 0 : acts->rule_acts[at->recom_off].action = acts->push_remove->action;
2426 : 0 : acts->rule_acts[at->recom_off].ipv6_ext.header = acts->push_remove->data;
2427 : 0 : acts->rule_acts[at->recom_off].ipv6_ext.offset = 0;
2428 : 0 : acts->push_remove_pos = at->recom_off;
2429 [ # # ]: 0 : if (!acts->push_remove->shared) {
2430 : 0 : act_data = __flow_hw_act_data_push_append(dev, acts,
2431 : : RTE_FLOW_ACTION_TYPE_IPV6_EXT_PUSH,
2432 : : recom_src, at->recom_off, push_size);
2433 : : if (!act_data)
2434 : 0 : goto err;
2435 : : }
2436 : : return 0;
2437 : : err:
2438 [ # # ]: 0 : if (acts->push_remove->action)
2439 : 0 : mlx5dr_action_destroy(acts->push_remove->action);
2440 : 0 : err1:
2441 [ # # ]: 0 : if (acts->push_remove) {
2442 : 0 : mlx5_free(acts->push_remove);
2443 : 0 : acts->push_remove = NULL;
2444 : : }
2445 : : return -EINVAL;
2446 : : }
2447 : :
2448 : : /**
2449 : : * Translate rte_flow actions to DR action.
2450 : : *
2451 : : * As the action template has already indicated the actions. Translate
2452 : : * the rte_flow actions to DR action if possbile. So in flow create
2453 : : * stage we will save cycles from handing the actions' organizing.
2454 : : * For the actions with limited information, need to add these to a
2455 : : * list.
2456 : : *
2457 : : * @param[in] dev
2458 : : * Pointer to the rte_eth_dev structure.
2459 : : * @param[in] cfg
2460 : : * Pointer to the table configuration.
2461 : : * @param[in/out] acts
2462 : : * Pointer to the template HW steering DR actions.
2463 : : * @param[in] at
2464 : : * Action template.
2465 : : * @param[in] nt_mode
2466 : : * Non template rule translate.
2467 : : * @param[out] error
2468 : : * Pointer to error structure.
2469 : : *
2470 : : * @return
2471 : : * 0 on success, a negative errno otherwise and rte_errno is set.
2472 : : */
2473 : : static int
2474 : 0 : __flow_hw_translate_actions_template(struct rte_eth_dev *dev,
2475 : : const struct mlx5_flow_template_table_cfg *cfg,
2476 : : struct mlx5_hw_actions *acts,
2477 : : struct rte_flow_actions_template *at,
2478 : : struct mlx5_tbl_multi_pattern_ctx *mp_ctx,
2479 : : bool nt_mode,
2480 : : struct rte_flow_error *error)
2481 : : {
2482 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
2483 : 0 : struct mlx5_hca_attr *hca_attr = &priv->sh->cdev->config.hca_attr;
2484 : 0 : const struct rte_flow_template_table_attr *table_attr = &cfg->attr;
2485 : 0 : const struct rte_flow_attr *attr = &table_attr->flow_attr;
2486 : 0 : struct rte_flow_action *actions = at->actions;
2487 : 0 : struct rte_flow_action *masks = at->masks;
2488 : : enum mlx5dr_action_type refmt_type = MLX5DR_ACTION_TYP_LAST;
2489 : : enum mlx5dr_action_type recom_type = MLX5DR_ACTION_TYP_LAST;
2490 : : const struct rte_flow_action_raw_encap *raw_encap_data;
2491 : : const struct rte_flow_action_ipv6_ext_push *ipv6_ext_data;
2492 : : const struct rte_flow_item *enc_item = NULL, *enc_item_m = NULL;
2493 : : uint16_t reformat_src = 0, recom_src = 0;
2494 : : uint8_t *encap_data = NULL, *encap_data_m = NULL;
2495 : : uint8_t *push_data = NULL, *push_data_m = NULL;
2496 : : size_t data_size = 0, push_size = 0;
2497 : : struct mlx5_hw_modify_header_action mhdr = { 0 };
2498 : 0 : struct rte_flow_error sub_error = {
2499 : : .type = RTE_FLOW_ERROR_TYPE_NONE,
2500 : : .cause = NULL,
2501 : : .message = NULL,
2502 : : };
2503 : : bool actions_end = false;
2504 : : uint32_t type;
2505 : : bool reformat_used = false;
2506 : : bool recom_used = false;
2507 : : unsigned int of_vlan_offset;
2508 : : uint32_t ct_idx;
2509 : : int ret, err;
2510 : 0 : uint32_t target_grp = 0;
2511 : : bool unified_fdb = is_unified_fdb(priv);
2512 : :
2513 : : flow_hw_modify_field_init(&mhdr, at);
2514 : 0 : type = get_mlx5dr_table_type(attr, cfg->attr.specialize, unified_fdb);
2515 [ # # ]: 0 : for (; !actions_end; actions++, masks++) {
2516 : 0 : uint64_t pos = actions - at->actions;
2517 : 0 : uint16_t src_pos = pos - at->src_off[pos];
2518 : 0 : uint16_t dr_pos = at->dr_off[pos];
2519 : :
2520 [ # # # # : 0 : switch ((int)actions->type) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # ]
2521 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT_LIST:
2522 [ # # ]: 0 : if (!attr->group) {
2523 : 0 : DRV_LOG(ERR, "Indirect action is not supported in root table.");
2524 : 0 : goto err;
2525 : : }
2526 : 0 : ret = table_template_translate_indirect_list
2527 : : (dev, actions, masks, acts, src_pos, dr_pos);
2528 [ # # ]: 0 : if (ret)
2529 : 0 : goto err;
2530 : : break;
2531 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT:
2532 [ # # ]: 0 : if (!attr->group) {
2533 : 0 : DRV_LOG(ERR, "Indirect action is not supported in root table.");
2534 : 0 : goto err;
2535 : : }
2536 [ # # # # ]: 0 : if (actions->conf && masks->conf) {
2537 [ # # # # : 0 : if (flow_hw_shared_action_translate
# # ]
2538 : : (dev, actions, acts, src_pos, dr_pos))
2539 : 0 : goto err;
2540 : 0 : } else if (__flow_hw_act_data_indirect_append
2541 : : (priv, acts, RTE_FLOW_ACTION_TYPE_INDIRECT,
2542 : : masks->type, src_pos, dr_pos)){
2543 : 0 : goto err;
2544 : : }
2545 : : break;
2546 : : case RTE_FLOW_ACTION_TYPE_VOID:
2547 : : break;
2548 : 0 : case RTE_FLOW_ACTION_TYPE_DROP:
2549 : 0 : acts->rule_acts[dr_pos].action =
2550 : 0 : priv->hw_drop[!!attr->group];
2551 : 0 : break;
2552 : 0 : case RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:
2553 [ # # ]: 0 : if (!attr->group) {
2554 : 0 : DRV_LOG(ERR, "Port representor is not supported in root table.");
2555 : 0 : goto err;
2556 : : }
2557 : 0 : acts->rule_acts[dr_pos].action = priv->hw_def_miss;
2558 : 0 : break;
2559 : 0 : case RTE_FLOW_ACTION_TYPE_FLAG:
2560 : 0 : acts->mark = true;
2561 : 0 : acts->rule_acts[dr_pos].tag.value =
2562 : : mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
2563 : 0 : acts->rule_acts[dr_pos].action =
2564 : 0 : priv->hw_tag[!!attr->group];
2565 : 0 : rte_atomic_fetch_add_explicit(&priv->hws_mark_refcnt, 1,
2566 : : rte_memory_order_relaxed);
2567 : 0 : flow_hw_rxq_flag_set(dev, true);
2568 : 0 : break;
2569 : 0 : case RTE_FLOW_ACTION_TYPE_MARK:
2570 : 0 : acts->mark = true;
2571 [ # # ]: 0 : if (masks->conf &&
2572 : : ((const struct rte_flow_action_mark *)
2573 [ # # ]: 0 : masks->conf)->id)
2574 : 0 : acts->rule_acts[dr_pos].tag.value =
2575 : : mlx5_flow_mark_set
2576 : : (((const struct rte_flow_action_mark *)
2577 [ # # ]: 0 : (actions->conf))->id);
2578 : : else if (__flow_hw_act_data_general_append(priv, acts,
2579 : : actions->type,
2580 : : src_pos, dr_pos))
2581 : 0 : goto err;
2582 : 0 : acts->rule_acts[dr_pos].action =
2583 : 0 : priv->hw_tag[!!attr->group];
2584 : 0 : rte_atomic_fetch_add_explicit(&priv->hws_mark_refcnt, 1,
2585 : : rte_memory_order_relaxed);
2586 : 0 : flow_hw_rxq_flag_set(dev, true);
2587 : 0 : break;
2588 : 0 : case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
2589 : 0 : acts->rule_acts[dr_pos].action =
2590 : 0 : priv->hw_push_vlan[type];
2591 [ # # # # ]: 0 : if (is_template_masked_push_vlan(masks->conf))
2592 : 0 : acts->rule_acts[dr_pos].push_vlan.vlan_hdr =
2593 : : vlan_hdr_to_be32(actions);
2594 : : else if (__flow_hw_act_data_general_append
2595 : : (priv, acts, actions->type,
2596 : : src_pos, dr_pos))
2597 : 0 : goto err;
2598 : : of_vlan_offset = is_of_vlan_pcp_present(actions) ?
2599 [ # # ]: 0 : MLX5_HW_VLAN_PUSH_PCP_IDX :
2600 : : MLX5_HW_VLAN_PUSH_VID_IDX;
2601 : 0 : actions += of_vlan_offset;
2602 : 0 : masks += of_vlan_offset;
2603 : 0 : break;
2604 : 0 : case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
2605 : 0 : acts->rule_acts[dr_pos].action =
2606 : 0 : priv->hw_pop_vlan[type];
2607 : 0 : break;
2608 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP:
2609 [ # # ]: 0 : if (masks->conf &&
2610 : : ((const struct rte_flow_action_jump *)
2611 [ # # ]: 0 : masks->conf)->group) {
2612 : 0 : uint32_t jump_group =
2613 : : ((const struct rte_flow_action_jump *)
2614 : 0 : actions->conf)->group;
2615 : 0 : acts->jump = flow_hw_jump_action_register
2616 : : (dev, cfg, jump_group, &sub_error);
2617 [ # # ]: 0 : if (!acts->jump)
2618 : 0 : goto err;
2619 : 0 : acts->rule_acts[dr_pos].action = (!!attr->group) ?
2620 [ # # ]: 0 : acts->jump->hws_action :
2621 : : acts->jump->root_action;
2622 : : } else if (__flow_hw_act_data_general_append
2623 : : (priv, acts, actions->type,
2624 : : src_pos, dr_pos)){
2625 : 0 : goto err;
2626 : : }
2627 : : break;
2628 : 0 : case RTE_FLOW_ACTION_TYPE_QUEUE:
2629 [ # # ]: 0 : if (masks->conf &&
2630 : : ((const struct rte_flow_action_queue *)
2631 [ # # ]: 0 : masks->conf)->index) {
2632 : 0 : acts->tir = flow_hw_tir_action_register
2633 : 0 : (dev, mlx5_hw_act_flag[!!attr->group][type],
2634 : : actions);
2635 [ # # ]: 0 : if (!acts->tir)
2636 : 0 : goto err;
2637 : 0 : acts->rule_acts[dr_pos].action =
2638 : 0 : acts->tir->action;
2639 : : } else if (__flow_hw_act_data_general_append
2640 : : (priv, acts, actions->type,
2641 : : src_pos, dr_pos)) {
2642 : 0 : goto err;
2643 : : }
2644 : : break;
2645 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
2646 [ # # # # ]: 0 : if (actions->conf && masks->conf) {
2647 : 0 : acts->tir = flow_hw_tir_action_register
2648 : 0 : (dev, mlx5_hw_act_flag[!!attr->group][type],
2649 : : actions);
2650 [ # # ]: 0 : if (!acts->tir)
2651 : 0 : goto err;
2652 : 0 : acts->rule_acts[dr_pos].action =
2653 : 0 : acts->tir->action;
2654 : : } else if (__flow_hw_act_data_general_append
2655 : : (priv, acts, actions->type,
2656 : : src_pos, dr_pos)) {
2657 : 0 : goto err;
2658 : : }
2659 : : break;
2660 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
2661 : : MLX5_ASSERT(!reformat_used);
2662 : 0 : enc_item = MLX5_CONST_ENCAP_ITEM(rte_flow_action_vxlan_encap,
2663 : : actions->conf);
2664 [ # # ]: 0 : if (masks->conf)
2665 : 0 : enc_item_m = MLX5_CONST_ENCAP_ITEM(rte_flow_action_vxlan_encap,
2666 : : masks->conf);
2667 : : reformat_used = true;
2668 : : reformat_src = src_pos;
2669 : : refmt_type = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;
2670 : : break;
2671 : 0 : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
2672 : : MLX5_ASSERT(!reformat_used);
2673 : 0 : enc_item = MLX5_CONST_ENCAP_ITEM(rte_flow_action_nvgre_encap,
2674 : : actions->conf);
2675 [ # # ]: 0 : if (masks->conf)
2676 : 0 : enc_item_m = MLX5_CONST_ENCAP_ITEM(rte_flow_action_nvgre_encap,
2677 : : masks->conf);
2678 : : reformat_used = true;
2679 : : reformat_src = src_pos;
2680 : : refmt_type = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;
2681 : : break;
2682 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
2683 : 0 : raw_encap_data =
2684 : : (const struct rte_flow_action_raw_encap *)
2685 : : masks->conf;
2686 [ # # ]: 0 : if (raw_encap_data)
2687 : 0 : encap_data_m = raw_encap_data->data;
2688 : 0 : raw_encap_data =
2689 : : (const struct rte_flow_action_raw_encap *)
2690 : : actions->conf;
2691 : 0 : encap_data = raw_encap_data->data;
2692 : 0 : data_size = raw_encap_data->size;
2693 [ # # ]: 0 : if (reformat_used) {
2694 : : refmt_type = data_size <
2695 : : MLX5_ENCAPSULATION_DECISION_SIZE ?
2696 [ # # ]: 0 : MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2 :
2697 : : MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3;
2698 : : } else {
2699 : : reformat_used = true;
2700 : : refmt_type =
2701 : : MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;
2702 : : }
2703 : : reformat_src = src_pos;
2704 : : break;
2705 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
2706 : : case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
2707 : : MLX5_ASSERT(!reformat_used);
2708 : : reformat_used = true;
2709 : : refmt_type = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2;
2710 : 0 : break;
2711 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
2712 : : reformat_used = true;
2713 : : refmt_type = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2;
2714 : 0 : break;
2715 : 0 : case RTE_FLOW_ACTION_TYPE_IPV6_EXT_PUSH:
2716 [ # # ]: 0 : if (!hca_attr->flex.query_match_sample_info ||
2717 : 0 : !hca_attr->flex.parse_graph_anchor ||
2718 [ # # ]: 0 : !priv->sh->srh_flex_parser.flex.mapnum) {
2719 : 0 : DRV_LOG(ERR, "SRv6 anchor is not supported.");
2720 : 0 : goto err;
2721 : : }
2722 : : MLX5_ASSERT(!recom_used && !recom_type);
2723 : : recom_used = true;
2724 : : recom_type = MLX5DR_ACTION_TYP_PUSH_IPV6_ROUTE_EXT;
2725 : 0 : ipv6_ext_data =
2726 : : (const struct rte_flow_action_ipv6_ext_push *)masks->conf;
2727 [ # # ]: 0 : if (ipv6_ext_data)
2728 : 0 : push_data_m = ipv6_ext_data->data;
2729 : 0 : ipv6_ext_data =
2730 : : (const struct rte_flow_action_ipv6_ext_push *)actions->conf;
2731 [ # # ]: 0 : if (ipv6_ext_data) {
2732 : 0 : push_data = ipv6_ext_data->data;
2733 : 0 : push_size = ipv6_ext_data->size;
2734 : : }
2735 : : recom_src = src_pos;
2736 : : break;
2737 : 0 : case RTE_FLOW_ACTION_TYPE_IPV6_EXT_REMOVE:
2738 [ # # ]: 0 : if (!hca_attr->flex.query_match_sample_info ||
2739 : 0 : !hca_attr->flex.parse_graph_anchor ||
2740 [ # # ]: 0 : !priv->sh->srh_flex_parser.flex.mapnum) {
2741 : 0 : DRV_LOG(ERR, "SRv6 anchor is not supported.");
2742 : 0 : goto err;
2743 : : }
2744 : : recom_used = true;
2745 : : recom_type = MLX5DR_ACTION_TYP_POP_IPV6_ROUTE_EXT;
2746 : : break;
2747 : 0 : case RTE_FLOW_ACTION_TYPE_SEND_TO_KERNEL:
2748 : 0 : ret = flow_hw_translate_group(dev, cfg, attr->group,
2749 : : &target_grp, &sub_error);
2750 [ # # ]: 0 : if (ret)
2751 : 0 : goto err;
2752 [ # # ]: 0 : if (target_grp == 0) {
2753 : : __flow_hw_action_template_destroy(dev, acts);
2754 : 0 : rte_flow_error_set(&sub_error, ENOTSUP,
2755 : : RTE_FLOW_ERROR_TYPE_ACTION,
2756 : : NULL,
2757 : : "Send to kernel action on root table is not supported in HW steering mode");
2758 : 0 : goto err;
2759 : : }
2760 : 0 : acts->rule_acts[dr_pos].action = priv->hw_send_to_kernel[type];
2761 : 0 : break;
2762 [ # # ]: 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
2763 : : err = flow_hw_modify_field_compile(dev, attr, actions,
2764 : : masks, acts, &mhdr,
2765 : : src_pos, &sub_error);
2766 [ # # ]: 0 : if (err)
2767 : 0 : goto err;
2768 : : break;
2769 : 0 : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
2770 [ # # ]: 0 : if (flow_hw_represented_port_compile
2771 : : (dev, attr, actions,
2772 : : masks, acts, src_pos, dr_pos, &sub_error))
2773 : 0 : goto err;
2774 : : break;
2775 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
2776 : 0 : ret = flow_hw_translate_group(dev, cfg, attr->group,
2777 : : &target_grp, &sub_error);
2778 [ # # ]: 0 : if (ret)
2779 : 0 : goto err;
2780 [ # # ]: 0 : if (target_grp == 0) {
2781 : : __flow_hw_action_template_destroy(dev, acts);
2782 : 0 : rte_flow_error_set(&sub_error, ENOTSUP,
2783 : : RTE_FLOW_ERROR_TYPE_ACTION,
2784 : : NULL,
2785 : : "Age action on root table is not supported in HW steering mode");
2786 : 0 : goto err;
2787 : : }
2788 : 0 : if (__flow_hw_act_data_general_append(priv, acts,
2789 : : actions->type,
2790 : : src_pos,
2791 : : dr_pos))
2792 : 0 : goto err;
2793 : : break;
2794 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
2795 : 0 : ret = flow_hw_translate_group(dev, cfg, attr->group,
2796 : : &target_grp, &sub_error);
2797 [ # # ]: 0 : if (ret)
2798 : 0 : goto err;
2799 [ # # ]: 0 : if (target_grp == 0) {
2800 : : __flow_hw_action_template_destroy(dev, acts);
2801 : 0 : rte_flow_error_set(&sub_error, ENOTSUP,
2802 : : RTE_FLOW_ERROR_TYPE_ACTION,
2803 : : NULL,
2804 : : "Counter action on root table is not supported in HW steering mode");
2805 : 0 : goto err;
2806 : : }
2807 [ # # ]: 0 : if ((at->action_flags & MLX5_FLOW_ACTION_AGE) ||
2808 : : (at->action_flags & MLX5_FLOW_ACTION_INDIRECT_AGE))
2809 : : /*
2810 : : * When both COUNT and AGE are requested, it is
2811 : : * saved as AGE action which creates also the
2812 : : * counter.
2813 : : */
2814 : : break;
2815 [ # # ]: 0 : if (masks->conf &&
2816 : : ((const struct rte_flow_action_count *)
2817 [ # # ]: 0 : masks->conf)->id) {
2818 [ # # ]: 0 : err = flow_hw_cnt_compile(dev, dr_pos, acts);
2819 : : if (err)
2820 : 0 : goto err;
2821 : 0 : } else if (__flow_hw_act_data_general_append
2822 : : (priv, acts, actions->type,
2823 : : src_pos, dr_pos)) {
2824 : 0 : goto err;
2825 : : }
2826 : : break;
2827 : 0 : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
2828 [ # # ]: 0 : if (masks->conf) {
2829 : 0 : ct_idx = MLX5_INDIRECT_ACTION_IDX_GET(actions->conf);
2830 : : if (flow_hw_ct_compile(dev, MLX5_HW_INV_QUEUE, ct_idx,
2831 : 0 : &acts->rule_acts[dr_pos]))
2832 : 0 : goto err;
2833 : : } else if (__flow_hw_act_data_general_append
2834 : : (priv, acts, actions->type,
2835 : : src_pos, dr_pos)) {
2836 : 0 : goto err;
2837 : : }
2838 : : break;
2839 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
2840 [ # # # # ]: 0 : if (actions->conf && masks->conf &&
2841 : : ((const struct rte_flow_action_meter_mark *)
2842 [ # # ]: 0 : masks->conf)->profile) {
2843 : : err = flow_hw_meter_mark_compile(dev,
2844 : : dr_pos, actions,
2845 : 0 : acts->rule_acts,
2846 : : &acts->mtr_id,
2847 : : MLX5_HW_INV_QUEUE,
2848 : : &sub_error);
2849 : : if (err)
2850 : 0 : goto err;
2851 : : } else if (__flow_hw_act_data_general_append(priv, acts,
2852 : : actions->type,
2853 : : src_pos,
2854 : : dr_pos))
2855 : 0 : goto err;
2856 : : break;
2857 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
2858 : : /* Internal, can be skipped. */
2859 [ # # ]: 0 : if (!!attr->group) {
2860 : 0 : DRV_LOG(ERR, "DEFAULT MISS action is only"
2861 : : " supported in root table.");
2862 : 0 : goto err;
2863 : : }
2864 : 0 : acts->rule_acts[dr_pos].action = priv->hw_def_miss;
2865 : 0 : break;
2866 : 0 : case RTE_FLOW_ACTION_TYPE_NAT64:
2867 [ # # ]: 0 : if (masks->conf &&
2868 [ # # ]: 0 : ((const struct rte_flow_action_nat64 *)masks->conf)->type) {
2869 : 0 : const struct rte_flow_action_nat64 *nat64_c =
2870 : : (const struct rte_flow_action_nat64 *)actions->conf;
2871 : :
2872 : 0 : acts->rule_acts[dr_pos].action =
2873 : 0 : priv->action_nat64[type][nat64_c->type];
2874 : : } else if (__flow_hw_act_data_general_append(priv, acts,
2875 : : actions->type,
2876 : : src_pos, dr_pos))
2877 : 0 : goto err;
2878 : : break;
2879 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
2880 [ # # ]: 0 : if (masks->conf &&
2881 : : ((const struct rte_flow_action_jump_to_table_index *)
2882 [ # # ]: 0 : masks->conf)->table) {
2883 : 0 : struct rte_flow_template_table *jump_table =
2884 : : ((const struct rte_flow_action_jump_to_table_index *)
2885 : 0 : actions->conf)->table;
2886 : 0 : acts->rule_acts[dr_pos].jump_to_matcher.offset =
2887 : : ((const struct rte_flow_action_jump_to_table_index *)
2888 : 0 : actions->conf)->index;
2889 [ # # ]: 0 : if (likely(!rte_flow_template_table_resizable(dev->data->port_id,
2890 : : &jump_table->cfg.attr))) {
2891 : 0 : acts->rule_acts[dr_pos].action =
2892 : 0 : jump_table->matcher_info[0].jump;
2893 : : } else {
2894 : : uint32_t selector;
2895 : 0 : rte_rwlock_read_lock(&jump_table->matcher_replace_rwlk);
2896 : 0 : selector = jump_table->matcher_selector;
2897 : 0 : acts->rule_acts[dr_pos].action =
2898 : 0 : jump_table->matcher_info[selector].jump;
2899 : : rte_rwlock_read_unlock(&jump_table->matcher_replace_rwlk);
2900 : : }
2901 : : } else if (__flow_hw_act_data_general_append
2902 : : (priv, acts, actions->type,
2903 : : src_pos, dr_pos)){
2904 : 0 : goto err;
2905 : : }
2906 : : break;
2907 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_MIRROR:
2908 : : if (__flow_hw_act_data_general_append(priv, acts,
2909 : : actions->type,
2910 : : src_pos, dr_pos))
2911 : 0 : goto err;
2912 : : break;
2913 : 0 : case RTE_FLOW_ACTION_TYPE_END:
2914 : : actions_end = true;
2915 : 0 : break;
2916 : 0 : case RTE_FLOW_ACTION_TYPE_PORT_ID:
2917 : 0 : DRV_LOG(ERR, "RTE_FLOW_ACTION_TYPE_PORT_ID action is not supported. "
2918 : : "Use RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT instead.");
2919 : 0 : goto err;
2920 : : default:
2921 : : break;
2922 : : }
2923 : : }
2924 [ # # ]: 0 : if (mhdr.pos != UINT16_MAX) {
2925 : 0 : ret = mlx5_tbl_translate_modify_header(dev, cfg, acts, mp_ctx, &mhdr, &sub_error);
2926 [ # # ]: 0 : if (ret)
2927 : 0 : goto err;
2928 [ # # # # ]: 0 : if (!nt_mode && mhdr.shared) {
2929 : 0 : ret = mlx5_tbl_ensure_shared_modify_header(dev, cfg, acts, &sub_error);
2930 [ # # ]: 0 : if (ret)
2931 : 0 : goto err;
2932 : : }
2933 : : }
2934 [ # # ]: 0 : if (reformat_used) {
2935 : 0 : ret = mlx5_tbl_translate_reformat(priv, acts, at,
2936 : : enc_item, enc_item_m,
2937 : : encap_data, encap_data_m,
2938 : : mp_ctx, data_size,
2939 : : reformat_src,
2940 : : refmt_type, &sub_error);
2941 [ # # ]: 0 : if (ret)
2942 : 0 : goto err;
2943 [ # # # # ]: 0 : if (!nt_mode && acts->encap_decap->shared) {
2944 : 0 : ret = mlx5_tbl_create_reformat_action(priv, table_attr, acts, at,
2945 : : encap_data, data_size,
2946 : : refmt_type);
2947 [ # # ]: 0 : if (ret)
2948 : 0 : goto err;
2949 : : }
2950 : : }
2951 [ # # ]: 0 : if (recom_used) {
2952 : : MLX5_ASSERT(at->recom_off != UINT16_MAX);
2953 : 0 : ret = mlx5_create_ipv6_ext_reformat(dev, cfg, acts, at, push_data,
2954 : : push_data_m, push_size, recom_src,
2955 : : recom_type);
2956 [ # # ]: 0 : if (ret)
2957 : 0 : goto err;
2958 : : }
2959 : : return 0;
2960 : 0 : err:
2961 : : /* If rte_errno was not initialized and reached error state. */
2962 [ # # ]: 0 : if (!rte_errno)
2963 : 0 : rte_errno = EINVAL;
2964 : 0 : err = rte_errno;
2965 : : __flow_hw_action_template_destroy(dev, acts);
2966 [ # # # # ]: 0 : if (error != NULL && sub_error.type != RTE_FLOW_ERROR_TYPE_NONE) {
2967 : : rte_memcpy(error, &sub_error, sizeof(sub_error));
2968 : 0 : return -EINVAL;
2969 : : }
2970 : 0 : return rte_flow_error_set(error, err,
2971 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2972 : : "fail to create rte table");
2973 : : }
2974 : :
2975 : : /**
2976 : : * Translate rte_flow actions to DR action.
2977 : : *
2978 : : * As the action template has already indicated the actions. Translate
2979 : : * the rte_flow actions to DR action if possible. So in flow create
2980 : : * stage we will save cycles from handing the actions' organizing.
2981 : : * For the actions with limited information, need to add these to a
2982 : : * list.
2983 : : *
2984 : : * @param[in] dev
2985 : : * Pointer to the rte_eth_dev structure.
2986 : : * @param[in] cfg
2987 : : * Pointer to the table configuration.
2988 : : * @param[in/out] acts
2989 : : * Pointer to the template HW steering DR actions.
2990 : : * @param[in] at
2991 : : * Action template.
2992 : : * @param[out] error
2993 : : * Pointer to error structure.
2994 : : *
2995 : : * @return
2996 : : * 0 on success, a negative errno otherwise and rte_errno is set.
2997 : : */
2998 : : static int
2999 : : flow_hw_translate_actions_template(struct rte_eth_dev *dev,
3000 : : const struct mlx5_flow_template_table_cfg *cfg,
3001 : : struct mlx5_hw_actions *acts,
3002 : : struct rte_flow_actions_template *at,
3003 : : struct mlx5_tbl_multi_pattern_ctx *mp_ctx,
3004 : : struct rte_flow_error *error)
3005 : : {
3006 : 0 : return __flow_hw_translate_actions_template(dev, cfg, acts, at, mp_ctx, false, error);
3007 : : }
3008 : :
3009 : : static __rte_always_inline struct mlx5dr_rule_action *
3010 : : flow_hw_get_dr_action_buffer(struct mlx5_priv *priv,
3011 : : struct rte_flow_template_table *table,
3012 : : uint8_t action_template_index,
3013 : : uint32_t queue)
3014 : : {
3015 : 0 : uint32_t offset = action_template_index * priv->nb_queue + queue;
3016 : :
3017 : 0 : return &table->rule_acts[offset].acts[0];
3018 : : }
3019 : :
3020 : : static void
3021 : 0 : flow_hw_populate_rule_acts_caches(struct rte_eth_dev *dev,
3022 : : struct rte_flow_template_table *table,
3023 : : uint8_t at_idx)
3024 : : {
3025 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
3026 : : uint32_t q;
3027 : :
3028 [ # # ]: 0 : for (q = 0; q < priv->nb_queue; ++q) {
3029 : : struct mlx5dr_rule_action *rule_acts =
3030 : 0 : flow_hw_get_dr_action_buffer(priv, table, at_idx, q);
3031 : :
3032 [ # # ]: 0 : rte_memcpy(rule_acts, table->ats[at_idx].acts.rule_acts,
3033 : : sizeof(table->ats[at_idx].acts.rule_acts));
3034 : : }
3035 : 0 : }
3036 : :
3037 : : /**
3038 : : * Translate rte_flow actions to DR action.
3039 : : *
3040 : : * @param[in] dev
3041 : : * Pointer to the rte_eth_dev structure.
3042 : : * @param[in] tbl
3043 : : * Pointer to the flow template table.
3044 : : * @param[out] error
3045 : : * Pointer to error structure.
3046 : : *
3047 : : * @return
3048 : : * 0 on success, negative value otherwise and rte_errno is set.
3049 : : */
3050 : : static int
3051 : 0 : flow_hw_translate_all_actions_templates(struct rte_eth_dev *dev,
3052 : : struct rte_flow_template_table *tbl,
3053 : : struct rte_flow_error *error)
3054 : : {
3055 : : int ret;
3056 : : uint32_t i;
3057 : :
3058 [ # # ]: 0 : for (i = 0; i < tbl->nb_action_templates; i++) {
3059 [ # # ]: 0 : if (flow_hw_translate_actions_template(dev, &tbl->cfg,
3060 : : &tbl->ats[i].acts,
3061 : : tbl->ats[i].action_template,
3062 : : &tbl->mpctx, error))
3063 : 0 : goto err;
3064 : 0 : flow_hw_populate_rule_acts_caches(dev, tbl, i);
3065 : : }
3066 [ # # ]: 0 : ret = mlx5_tbl_multi_pattern_process(dev, tbl, &tbl->mpctx.segments[0],
3067 : : rte_log2_u32(tbl->cfg.attr.nb_flows),
3068 : : error);
3069 [ # # ]: 0 : if (ret)
3070 : 0 : goto err;
3071 : : return 0;
3072 : : err:
3073 [ # # ]: 0 : while (i--)
3074 : 0 : __flow_hw_action_template_destroy(dev, &tbl->ats[i].acts);
3075 : : return -1;
3076 : : }
3077 : :
3078 : : /**
3079 : : * Get shared indirect action.
3080 : : *
3081 : : * @param[in] dev
3082 : : * Pointer to the rte_eth_dev data structure.
3083 : : * @param[in] act_data
3084 : : * Pointer to the recorded action construct data.
3085 : : * @param[in] item_flags
3086 : : * The matcher itme_flags used for RSS lookup.
3087 : : * @param[in] rule_act
3088 : : * Pointer to the shared action's destination rule DR action.
3089 : : *
3090 : : * @return
3091 : : * 0 on success, negative value otherwise and rte_errno is set.
3092 : : */
3093 : : static __rte_always_inline int
3094 : : flow_hw_shared_action_get(struct rte_eth_dev *dev,
3095 : : struct mlx5_action_construct_data *act_data,
3096 : : const uint64_t item_flags,
3097 : : struct mlx5dr_rule_action *rule_act)
3098 : : {
3099 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
3100 : 0 : struct mlx5_flow_rss_desc rss_desc = { 0 };
3101 : 0 : uint64_t hash_fields = 0;
3102 : : uint32_t hrxq_idx = 0;
3103 : : struct mlx5_hrxq *hrxq = NULL;
3104 : : int act_type = act_data->type;
3105 : :
3106 : : switch (act_type) {
3107 : : case MLX5_RTE_FLOW_ACTION_TYPE_RSS:
3108 : 0 : rss_desc.level = act_data->shared_rss.level;
3109 : 0 : rss_desc.types = act_data->shared_rss.types;
3110 : 0 : rss_desc.symmetric_hash_function = act_data->shared_rss.symmetric_hash_function;
3111 : 0 : flow_dv_hashfields_set(item_flags, &rss_desc, &hash_fields);
3112 : 0 : hrxq_idx = flow_dv_action_rss_hrxq_lookup
3113 : : (dev, act_data->shared_rss.idx, hash_fields);
3114 [ # # # # : 0 : if (hrxq_idx)
# # # # #
# # # # #
# # # # #
# ]
3115 : 0 : hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
3116 : : hrxq_idx);
3117 [ # # # # : 0 : if (hrxq) {
# # # # #
# # # # #
# # # # #
# ]
3118 : 0 : rule_act->action = hrxq->action;
3119 : : return 0;
3120 : : }
3121 : : break;
3122 : : default:
3123 : : DRV_LOG(WARNING, "Unsupported shared action type:%d",
3124 : : act_data->type);
3125 : : break;
3126 : : }
3127 : : return -1;
3128 : : }
3129 : :
3130 : : static void
3131 : 0 : flow_hw_construct_quota(struct mlx5_priv *priv,
3132 : : struct mlx5dr_rule_action *rule_act, uint32_t qid)
3133 : : {
3134 : 0 : rule_act->action = priv->quota_ctx.dr_action;
3135 : 0 : rule_act->aso_meter.offset = qid - 1;
3136 : 0 : rule_act->aso_meter.init_color =
3137 : : MLX5DR_ACTION_ASO_METER_COLOR_GREEN;
3138 : 0 : }
3139 : :
3140 : : /**
3141 : : * Construct shared indirect action.
3142 : : *
3143 : : * @param[in] dev
3144 : : * Pointer to the rte_eth_dev data structure.
3145 : : * @param[in] queue
3146 : : * The flow creation queue index.
3147 : : * @param[in] action
3148 : : * Pointer to the shared indirect rte_flow action.
3149 : : * @param[in] table
3150 : : * Pointer to the flow table.
3151 : : * @param[in] item_flags
3152 : : * Item flags.
3153 : : * @param[in] action_flags
3154 : : * Actions bit-map detected in this template.
3155 : : * @param[in, out] flow
3156 : : * Pointer to the flow containing the counter.
3157 : : * @param[in] rule_act
3158 : : * Pointer to the shared action's destination rule DR action.
3159 : : *
3160 : : * @return
3161 : : * 0 on success, negative value otherwise and rte_errno is set.
3162 : : */
3163 : : static __rte_always_inline int
3164 : : flow_hw_shared_action_construct(struct rte_eth_dev *dev, uint32_t queue,
3165 : : const struct rte_flow_action *action,
3166 : : struct rte_flow_template_table *table __rte_unused,
3167 : : const uint64_t item_flags, uint64_t action_flags,
3168 : : struct rte_flow_hw *flow,
3169 : : struct mlx5dr_rule_action *rule_act)
3170 : : {
3171 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
3172 : 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
3173 : : struct mlx5_action_construct_data act_data;
3174 : : struct mlx5_shared_action_rss *shared_rss;
3175 : : struct mlx5_aso_mtr *aso_mtr;
3176 : : struct mlx5_age_info *age_info;
3177 : : struct mlx5_hws_age_param *param;
3178 : : struct rte_flow_hw_aux *aux;
3179 : 0 : uint32_t act_idx = (uint32_t)(uintptr_t)action->conf;
3180 : 0 : uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
3181 : 0 : uint32_t idx = act_idx &
3182 : : ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
3183 : : uint32_t *cnt_queue;
3184 : : cnt_id_t age_cnt;
3185 : :
3186 : : memset(&act_data, 0, sizeof(act_data));
3187 [ # # # # : 0 : switch (type) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3188 : 0 : case MLX5_INDIRECT_ACTION_TYPE_RSS:
3189 : 0 : act_data.type = MLX5_RTE_FLOW_ACTION_TYPE_RSS;
3190 : 0 : shared_rss = mlx5_ipool_get
3191 : 0 : (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
3192 [ # # # # : 0 : if (!shared_rss)
# # # # #
# ]
3193 : : return -1;
3194 : 0 : act_data.shared_rss.idx = idx;
3195 : 0 : act_data.shared_rss.level = shared_rss->origin.level;
3196 : 0 : act_data.shared_rss.types = !shared_rss->origin.types ?
3197 [ # # # # : 0 : RTE_ETH_RSS_IP :
# # # # #
# ]
3198 : : shared_rss->origin.types;
3199 : 0 : act_data.shared_rss.symmetric_hash_function =
3200 : 0 : MLX5_RSS_IS_SYMM(shared_rss->origin.func);
3201 : :
3202 : : if (flow_hw_shared_action_get
3203 : : (dev, &act_data, item_flags, rule_act))
3204 : : return -1;
3205 : : break;
3206 : 0 : case MLX5_INDIRECT_ACTION_TYPE_COUNT:
3207 : 0 : if (mlx5_hws_cnt_pool_get_action_offset(priv->hws_cpool,
3208 : : act_idx,
3209 : : &rule_act->action,
3210 : : &rule_act->counter.offset))
3211 : : return -1;
3212 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_CNT_ID;
3213 : 0 : flow->cnt_id = act_idx;
3214 : : break;
3215 : 0 : case MLX5_INDIRECT_ACTION_TYPE_AGE:
3216 [ # # # # : 0 : aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
# # # # #
# ]
3217 : : /*
3218 : : * Save the index with the indirect type, to recognize
3219 : : * it in flow destroy.
3220 : : */
3221 : : mlx5_flow_hw_aux_set_age_idx(flow, aux, act_idx);
3222 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_AGE_IDX;
3223 [ # # # # : 0 : if (action_flags & MLX5_FLOW_ACTION_INDIRECT_COUNT)
# # # # #
# ]
3224 : : /*
3225 : : * The mutual update for idirect AGE & COUNT will be
3226 : : * performed later after we have ID for both of them.
3227 : : */
3228 : : break;
3229 : 0 : age_info = GET_PORT_AGE_INFO(priv);
3230 : 0 : param = mlx5_ipool_get(age_info->ages_ipool, idx);
3231 [ # # # # : 0 : if (param == NULL)
# # # # #
# ]
3232 : : return -1;
3233 [ # # # # : 0 : if (action_flags & MLX5_FLOW_ACTION_COUNT) {
# # # # #
# ]
3234 : : cnt_queue = mlx5_hws_cnt_get_queue(priv, &queue);
3235 [ # # # # : 0 : if (mlx5_hws_cnt_pool_get(priv->hws_cpool, cnt_queue, &age_cnt, idx) < 0)
# # # # #
# ]
3236 : : return -1;
3237 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_CNT_ID;
3238 : 0 : flow->cnt_id = age_cnt;
3239 : 0 : param->nb_cnts++;
3240 : : } else {
3241 : : /*
3242 : : * Get the counter of this indirect AGE or create one
3243 : : * if doesn't exist.
3244 : : */
3245 : : age_cnt = mlx5_hws_age_cnt_get(priv, param, idx);
3246 [ # # # # : 0 : if (age_cnt == 0)
# # # # #
# ]
3247 : : return -1;
3248 : : }
3249 : 0 : if (mlx5_hws_cnt_pool_get_action_offset(priv->hws_cpool,
3250 : : age_cnt, &rule_act->action,
3251 : : &rule_act->counter.offset))
3252 : : return -1;
3253 : : break;
3254 : 0 : case MLX5_INDIRECT_ACTION_TYPE_CT:
3255 : : if (flow_hw_ct_compile(dev, queue, idx, rule_act))
3256 : : return -1;
3257 : : break;
3258 : 0 : case MLX5_INDIRECT_ACTION_TYPE_METER_MARK:
3259 : : /* Find ASO object. */
3260 : 0 : aso_mtr = mlx5_ipool_get(pool->idx_pool, idx);
3261 [ # # # # : 0 : if (!aso_mtr)
# # # # #
# ]
3262 : : return -1;
3263 : 0 : rule_act->action = pool->action;
3264 : 0 : rule_act->aso_meter.offset = aso_mtr->offset;
3265 : : break;
3266 : 0 : case MLX5_INDIRECT_ACTION_TYPE_QUOTA:
3267 : 0 : flow_hw_construct_quota(priv, rule_act, idx);
3268 : : break;
3269 : 0 : default:
3270 : 0 : DRV_LOG(WARNING, "Unsupported shared action type:%d", type);
3271 : : break;
3272 : : }
3273 : : return 0;
3274 : : }
3275 : :
3276 : : static __rte_always_inline int
3277 : : flow_hw_mhdr_cmd_is_nop(const struct mlx5_modification_cmd *cmd)
3278 : : {
3279 : : struct mlx5_modification_cmd cmd_he = {
3280 : 0 : .data0 = rte_be_to_cpu_32(cmd->data0),
3281 : : .data1 = 0,
3282 : : };
3283 : :
3284 : 0 : return cmd_he.action_type == MLX5_MODIFICATION_TYPE_NOP;
3285 : : }
3286 : :
3287 : : /**
3288 : : * Construct flow action array.
3289 : : *
3290 : : * For action template contains dynamic actions, these actions need to
3291 : : * be updated according to the rte_flow action during flow creation.
3292 : : *
3293 : : * @param[in] dev
3294 : : * Pointer to the rte_eth_dev structure.
3295 : : * @param[in] job
3296 : : * Pointer to job descriptor.
3297 : : * @param[in] hw_acts
3298 : : * Pointer to translated actions from template.
3299 : : * @param[in] it_idx
3300 : : * Item template index the action template refer to.
3301 : : * @param[in] actions
3302 : : * Array of rte_flow action need to be checked.
3303 : : * @param[in] rule_acts
3304 : : * Array of DR rule actions to be used during flow creation..
3305 : : * @param[in] acts_num
3306 : : * Pointer to the real acts_num flow has.
3307 : : *
3308 : : * @return
3309 : : * 0 on success, negative value otherwise and rte_errno is set.
3310 : : */
3311 : : static __rte_always_inline int
3312 : : flow_hw_modify_field_construct(struct mlx5_modification_cmd *mhdr_cmd,
3313 : : struct mlx5_action_construct_data *act_data,
3314 : : const struct mlx5_hw_actions *hw_acts,
3315 : : const struct rte_flow_action *action)
3316 : : {
3317 : 0 : const struct rte_flow_action_modify_field *mhdr_action = action->conf;
3318 : 0 : uint8_t values[16] = { 0 };
3319 : : unaligned_uint32_t *value_p;
3320 : : uint32_t i;
3321 : : struct field_modify_info *field;
3322 : :
3323 [ # # # # : 0 : if (!hw_acts->mhdr)
# # # # #
# ]
3324 : : return -1;
3325 [ # # # # : 0 : if (hw_acts->mhdr->shared || act_data->modify_header.shared)
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3326 : : return 0;
3327 : : MLX5_ASSERT(mhdr_action->operation == RTE_FLOW_MODIFY_SET ||
3328 : : mhdr_action->operation == RTE_FLOW_MODIFY_ADD);
3329 [ # # # # : 0 : if (mhdr_action->src.field != RTE_FLOW_FIELD_VALUE &&
# # # # #
# ]
3330 : : mhdr_action->src.field != RTE_FLOW_FIELD_POINTER)
3331 : : return 0;
3332 [ # # # # : 0 : if (mhdr_action->src.field == RTE_FLOW_FIELD_VALUE)
# # # # #
# ]
3333 [ # # # # : 0 : rte_memcpy(values, &mhdr_action->src.value, sizeof(values));
# # # # #
# ]
3334 : : else
3335 [ # # # # : 0 : rte_memcpy(values, mhdr_action->src.pvalue, sizeof(values));
# # # # #
# ]
3336 [ # # # # : 0 : if (mhdr_action->dst.field == RTE_FLOW_FIELD_META ||
# # # # #
# ]
3337 [ # # # # : 0 : mhdr_action->dst.field == RTE_FLOW_FIELD_TAG ||
# # # # #
# ]
3338 [ # # # # : 0 : mhdr_action->dst.field == RTE_FLOW_FIELD_METER_COLOR ||
# # # # #
# ]
3339 : : mhdr_action->dst.field == (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG) {
3340 : 0 : uint8_t tag_index = flow_tag_index_get(&mhdr_action->dst);
3341 : :
3342 : : value_p = (unaligned_uint32_t *)values;
3343 [ # # # # : 0 : if (mhdr_action->dst.field == RTE_FLOW_FIELD_TAG &&
# # # # #
# # # # #
# # # # #
# ]
3344 : : tag_index == RTE_PMD_MLX5_LINEAR_HASH_TAG_INDEX)
3345 [ # # # # : 0 : *value_p = rte_cpu_to_be_32(*value_p << 16);
# # # # #
# ]
3346 : : else
3347 [ # # # # : 0 : *value_p = rte_cpu_to_be_32(*value_p);
# # # # #
# ]
3348 [ # # # # : 0 : } else if (mhdr_action->dst.field == RTE_FLOW_FIELD_GTP_PSC_QFI ||
# # # # #
# ]
3349 : : mhdr_action->dst.field == RTE_FLOW_FIELD_GENEVE_OPT_TYPE) {
3350 : : uint32_t tmp;
3351 : :
3352 : : /*
3353 : : * Both QFI and Geneve option type are passed as an uint8_t integer,
3354 : : * but it is accessed through a 2nd least significant byte of a 32-bit
3355 : : * field in modify header command.
3356 : : */
3357 : 0 : tmp = values[0];
3358 : : value_p = (unaligned_uint32_t *)values;
3359 [ # # # # : 0 : *value_p = rte_cpu_to_be_32(tmp << 8);
# # # # #
# ]
3360 : : }
3361 : 0 : i = act_data->modify_header.mhdr_cmds_off;
3362 : 0 : field = act_data->modify_header.field;
3363 : : do {
3364 : : uint32_t off_b;
3365 : : uint32_t mask;
3366 : : uint32_t data;
3367 : : const uint8_t *mask_src;
3368 : :
3369 [ # # # # : 0 : if (i >= act_data->modify_header.mhdr_cmds_end)
# # # # #
# # # # #
# # # # #
# ]
3370 : : return -1;
3371 [ # # # # : 0 : if (flow_hw_mhdr_cmd_is_nop(&mhdr_cmd[i])) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3372 : 0 : ++i;
3373 : 0 : continue;
3374 : : }
3375 : 0 : mask_src = (const uint8_t *)act_data->modify_header.mask;
3376 : 0 : mask = flow_dv_fetch_field(mask_src + field->offset, field->size);
3377 [ # # # # : 0 : if (!mask) {
# # # # #
# # # # #
# # # # #
# ]
3378 : 0 : ++field;
3379 : 0 : continue;
3380 : : }
3381 : 0 : off_b = rte_bsf32(mask);
3382 : 0 : data = flow_dv_fetch_field(values + field->offset, field->size);
3383 : : /*
3384 : : * IPv6 DSCP uses OUT_IPV6_TRAFFIC_CLASS as ID but it starts from 2
3385 : : * bits left. Shift the data left for IPv6 DSCP
3386 : : */
3387 [ # # # # : 0 : if (field->id == MLX5_MODI_OUT_IPV6_TRAFFIC_CLASS &&
# # # # #
# # # #
# ]
3388 [ # # # # : 0 : mhdr_action->dst.field == RTE_FLOW_FIELD_IPV6_DSCP)
# # ]
3389 : 0 : data <<= MLX5_IPV6_HDR_DSCP_SHIFT;
3390 : 0 : data = (data & mask) >> off_b;
3391 [ # # # # : 0 : mhdr_cmd[i++].data1 = rte_cpu_to_be_32(data);
# # # # #
# # # # #
# # # # #
# ]
3392 : 0 : ++field;
3393 [ # # # # : 0 : } while (field->size);
# # # # #
# # # # #
# # # # #
# ]
3394 : : return 0;
3395 : : }
3396 : :
3397 : : /**
3398 : : * Release any actions allocated for the flow rule during actions construction.
3399 : : *
3400 : : * @param[in] flow
3401 : : * Pointer to flow structure.
3402 : : */
3403 : : static void
3404 : 0 : flow_hw_release_actions(struct rte_eth_dev *dev,
3405 : : uint32_t queue,
3406 : : struct rte_flow_hw *flow)
3407 : : {
3408 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
3409 : 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
3410 [ # # ]: 0 : struct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
3411 : :
3412 [ # # ]: 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_FATE_JUMP)
3413 : 0 : flow_hw_jump_release(dev, flow->jump);
3414 [ # # ]: 0 : else if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_FATE_HRXQ)
3415 : 0 : mlx5_hrxq_obj_release(dev, flow->hrxq);
3416 [ # # ]: 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_CNT_ID)
3417 : 0 : flow_hw_age_count_release(priv, queue, flow, NULL);
3418 [ # # ]: 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_MTR_ID)
3419 : 0 : mlx5_ipool_free(pool->idx_pool, mlx5_flow_hw_aux_get_mtr_id(flow, aux));
3420 : 0 : }
3421 : :
3422 : : /**
3423 : : * Construct flow action array.
3424 : : *
3425 : : * For action template contains dynamic actions, these actions need to
3426 : : * be updated according to the rte_flow action during flow creation.
3427 : : *
3428 : : * @param[in] dev
3429 : : * Pointer to the rte_eth_dev structure.
3430 : : * @param[in] flow
3431 : : * Pointer to flow structure.
3432 : : * @param[in] ap
3433 : : * Pointer to container for temporarily constructed actions' parameters.
3434 : : * @param[in] hw_acts
3435 : : * Pointer to translated actions from template.
3436 : : * @param[in] items_flags
3437 : : * Item flags.
3438 : : * @param[in] table
3439 : : * Pointer to the template table.
3440 : : * @param[in] actions
3441 : : * Array of rte_flow action need to be checked.
3442 : : * @param[in] rule_acts
3443 : : * Array of DR rule actions to be used during flow creation..
3444 : : * @param[in] acts_num
3445 : : * Pointer to the real acts_num flow has.
3446 : : *
3447 : : * @return
3448 : : * 0 on success, negative value otherwise and rte_errno is set.
3449 : : */
3450 : : static __rte_always_inline int
3451 : : flow_hw_actions_construct(struct rte_eth_dev *dev,
3452 : : struct rte_flow_hw *flow,
3453 : : struct mlx5_flow_hw_action_params *ap,
3454 : : const struct mlx5_hw_action_template *hw_at,
3455 : : uint64_t item_flags,
3456 : : struct rte_flow_template_table *table,
3457 : : const struct rte_flow_action actions[],
3458 : : struct mlx5dr_rule_action *rule_acts,
3459 : : uint32_t queue,
3460 : : struct rte_flow_error *error)
3461 : : {
3462 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
3463 : 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
3464 : : struct mlx5_action_construct_data *act_data;
3465 : 0 : const struct rte_flow_actions_template *at = hw_at->action_template;
3466 : : const struct mlx5_hw_actions *hw_acts = &hw_at->acts;
3467 : : const struct rte_flow_action *action;
3468 : : const struct rte_flow_action_raw_encap *raw_encap_data;
3469 : : const struct rte_flow_action_ipv6_ext_push *ipv6_push;
3470 : : const struct rte_flow_item *enc_item = NULL;
3471 : : const struct rte_flow_action_ethdev *port_action = NULL;
3472 : : const struct rte_flow_action_age *age = NULL;
3473 : : const struct rte_flow_action_nat64 *nat64_c = NULL;
3474 : 0 : struct rte_flow_attr attr = {
3475 : : .ingress = 1,
3476 : : };
3477 : : uint32_t ft_flag;
3478 : : int ret;
3479 : 0 : size_t encap_len = 0;
3480 : : uint32_t age_idx = 0;
3481 : : uint32_t mtr_idx = 0;
3482 : : struct mlx5_aso_mtr *aso_mtr;
3483 : : struct mlx5_multi_pattern_segment *mp_segment = NULL;
3484 : : struct rte_flow_hw_aux *aux;
3485 : :
3486 : 0 : attr.group = table->grp->group_id;
3487 : 0 : ft_flag = mlx5_hw_act_flag[!!table->grp->group_id][table->type];
3488 : 0 : if (table->type >= MLX5DR_TABLE_TYPE_FDB && table->type < MLX5DR_TABLE_TYPE_MAX) {
3489 : 0 : attr.transfer = 1;
3490 : : attr.ingress = 1;
3491 [ # # # # : 0 : } else if (table->type == MLX5DR_TABLE_TYPE_NIC_TX) {
# # # # #
# ]
3492 : 0 : attr.egress = 1;
3493 : 0 : attr.ingress = 0;
3494 : : } else {
3495 : : attr.ingress = 1;
3496 : : }
3497 [ # # # # : 0 : if (hw_acts->mhdr && hw_acts->mhdr->mhdr_cmds_num > 0 && !hw_acts->mhdr->shared) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3498 : 0 : uint16_t pos = hw_acts->mhdr->pos;
3499 : :
3500 : 0 : mp_segment = mlx5_multi_pattern_segment_find(table, flow->res_idx);
3501 [ # # # # : 0 : if (!mp_segment || !mp_segment->mhdr_action)
# # # # #
# # # # #
# # # # #
# ]
3502 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3503 : : NULL, "No modify header action found");
3504 : 0 : rule_acts[pos].action = mp_segment->mhdr_action;
3505 : : /* offset is relative to DR action */
3506 : 0 : rule_acts[pos].modify_header.offset =
3507 : 0 : flow->res_idx - mp_segment->head_index;
3508 : 0 : rule_acts[pos].modify_header.data =
3509 : 0 : (uint8_t *)ap->mhdr_cmd;
3510 : : MLX5_ASSERT(hw_acts->mhdr->mhdr_cmds_num <= MLX5_MHDR_MAX_CMD);
3511 : 0 : rte_memcpy(ap->mhdr_cmd, hw_acts->mhdr->mhdr_cmds,
3512 [ # # # # : 0 : sizeof(*ap->mhdr_cmd) * hw_acts->mhdr->mhdr_cmds_num);
# # # # #
# ]
3513 : : }
3514 [ # # # # : 0 : LIST_FOREACH(act_data, &hw_acts->act_list, next) {
# # # # #
# ]
3515 : : uint32_t jump_group;
3516 : : uint32_t tag;
3517 : : struct mlx5_hw_jump_action *jump;
3518 : : struct mlx5_hrxq *hrxq;
3519 : : uint32_t ct_idx;
3520 : : cnt_id_t cnt_id;
3521 : : uint32_t *cnt_queue;
3522 : : uint32_t mtr_id;
3523 : : struct rte_flow_template_table *jump_table;
3524 : :
3525 : 0 : action = &actions[act_data->action_src];
3526 : : /*
3527 : : * action template construction replaces
3528 : : * OF_SET_VLAN_VID with MODIFY_FIELD
3529 : : */
3530 : 0 : if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)
3531 : : MLX5_ASSERT(act_data->type ==
3532 : : RTE_FLOW_ACTION_TYPE_MODIFY_FIELD);
3533 : : else
3534 : : MLX5_ASSERT(action->type ==
3535 : : RTE_FLOW_ACTION_TYPE_INDIRECT ||
3536 : : (int)action->type == act_data->type);
3537 [ # # # # : 0 : switch ((int)act_data->type) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3538 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT_LIST:
3539 : 0 : act_data->indirect_list_cb(dev, act_data, action,
3540 : 0 : &rule_acts[act_data->action_dst]);
3541 : 0 : break;
3542 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT:
3543 : 0 : if (flow_hw_shared_action_construct
3544 : : (dev, queue, action, table,
3545 : 0 : item_flags, at->action_flags, flow,
3546 [ # # # # : 0 : &rule_acts[act_data->action_dst]))
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3547 : 0 : goto error;
3548 : : break;
3549 : : case RTE_FLOW_ACTION_TYPE_VOID:
3550 : : break;
3551 : 0 : case RTE_FLOW_ACTION_TYPE_MARK:
3552 : 0 : tag = mlx5_flow_mark_set
3553 : : (((const struct rte_flow_action_mark *)
3554 : 0 : (action->conf))->id);
3555 : 0 : rule_acts[act_data->action_dst].tag.value = tag;
3556 : 0 : break;
3557 : 0 : case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
3558 : 0 : rule_acts[act_data->action_dst].push_vlan.vlan_hdr =
3559 : 0 : vlan_hdr_to_be32(action);
3560 : 0 : break;
3561 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP:
3562 : 0 : jump_group = ((const struct rte_flow_action_jump *)
3563 : 0 : action->conf)->group;
3564 : 0 : jump = flow_hw_jump_action_register
3565 : 0 : (dev, &table->cfg, jump_group, NULL);
3566 [ # # # # : 0 : if (!jump)
# # # # #
# ]
3567 : 0 : goto error;
3568 : 0 : rule_acts[act_data->action_dst].action =
3569 [ # # # # : 0 : (!!attr.group) ? jump->hws_action : jump->root_action;
# # # # #
# ]
3570 : 0 : flow->jump = jump;
3571 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_FATE_JUMP;
3572 : 0 : break;
3573 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
3574 : : case RTE_FLOW_ACTION_TYPE_QUEUE:
3575 : 0 : hrxq = flow_hw_tir_action_register(dev, ft_flag, action);
3576 [ # # # # : 0 : if (!hrxq)
# # # # #
# ]
3577 : 0 : goto error;
3578 : 0 : rule_acts[act_data->action_dst].action = hrxq->action;
3579 : 0 : flow->hrxq = hrxq;
3580 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_FATE_HRXQ;
3581 : 0 : break;
3582 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_RSS:
3583 : 0 : if (flow_hw_shared_action_get
3584 : : (dev, act_data, item_flags,
3585 : 0 : &rule_acts[act_data->action_dst]))
3586 : 0 : goto error;
3587 : : break;
3588 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
3589 : 0 : enc_item = ((const struct rte_flow_action_vxlan_encap *)
3590 : 0 : action->conf)->definition;
3591 [ # # # # : 0 : if (flow_dv_convert_encap_data(enc_item, ap->encap_data, &encap_len, NULL))
# # # # #
# ]
3592 : 0 : goto error;
3593 : : break;
3594 : 0 : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
3595 : 0 : enc_item = ((const struct rte_flow_action_nvgre_encap *)
3596 : 0 : action->conf)->definition;
3597 [ # # # # : 0 : if (flow_dv_convert_encap_data(enc_item, ap->encap_data, &encap_len, NULL))
# # # # #
# ]
3598 : 0 : goto error;
3599 : : break;
3600 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
3601 : 0 : raw_encap_data =
3602 : : (const struct rte_flow_action_raw_encap *)
3603 : : action->conf;
3604 : : MLX5_ASSERT(raw_encap_data->size == act_data->encap.len);
3605 [ # # # # : 0 : if (unlikely(act_data->encap.len > MLX5_ENCAP_MAX_LEN))
# # # # #
# ]
3606 : : return -1;
3607 [ # # # # : 0 : rte_memcpy(ap->encap_data, raw_encap_data->data, act_data->encap.len);
# # # # #
# ]
3608 : : break;
3609 : 0 : case RTE_FLOW_ACTION_TYPE_IPV6_EXT_PUSH:
3610 : 0 : ipv6_push =
3611 : : (const struct rte_flow_action_ipv6_ext_push *)action->conf;
3612 : : MLX5_ASSERT(ipv6_push->size == act_data->ipv6_ext.len);
3613 [ # # # # : 0 : if (unlikely(act_data->ipv6_ext.len > MLX5_PUSH_MAX_LEN))
# # # # #
# ]
3614 : : return -1;
3615 [ # # # # : 0 : rte_memcpy(ap->ipv6_push_data, ipv6_push->data,
# # # # #
# ]
3616 : : act_data->ipv6_ext.len);
3617 : : break;
3618 : 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
3619 [ # # # # : 0 : if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)
# # # # #
# ]
3620 : 0 : ret = flow_hw_set_vlan_vid_construct(dev, ap->mhdr_cmd,
3621 : : act_data,
3622 : : hw_acts,
3623 : : action);
3624 : : else
3625 [ # # # # : 0 : ret = flow_hw_modify_field_construct(ap->mhdr_cmd,
# # # # #
# ]
3626 : : act_data,
3627 : : hw_acts,
3628 : : action);
3629 [ # # # # : 0 : if (ret)
# # # # #
# ]
3630 : 0 : goto error;
3631 : : break;
3632 : 0 : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
3633 : 0 : port_action = action->conf;
3634 [ # # # # : 0 : if (!priv->hw_vport[port_action->port_id])
# # # # #
# ]
3635 : 0 : goto error;
3636 : 0 : rule_acts[act_data->action_dst].action =
3637 : : priv->hw_vport[port_action->port_id];
3638 : 0 : break;
3639 : 0 : case RTE_FLOW_ACTION_TYPE_QUOTA:
3640 : 0 : flow_hw_construct_quota(priv,
3641 : 0 : rule_acts + act_data->action_dst,
3642 : : act_data->shared_meter.id);
3643 : 0 : break;
3644 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
3645 [ # # # # : 0 : aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
# # # # #
# ]
3646 : 0 : age = action->conf;
3647 : : /*
3648 : : * First, create the AGE parameter, then create its
3649 : : * counter later:
3650 : : * Regular counter - in next case.
3651 : : * Indirect counter - update it after the loop.
3652 : : */
3653 : 0 : age_idx = mlx5_hws_age_action_create(priv, queue, 0,
3654 : : age,
3655 : : flow->res_idx,
3656 : : error);
3657 [ # # # # : 0 : if (age_idx == 0)
# # # # #
# ]
3658 : 0 : goto error;
3659 : : mlx5_flow_hw_aux_set_age_idx(flow, aux, age_idx);
3660 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_AGE_IDX;
3661 [ # # # # : 0 : if (at->action_flags & MLX5_FLOW_ACTION_INDIRECT_COUNT)
# # # # #
# ]
3662 : : /*
3663 : : * When AGE uses indirect counter, no need to
3664 : : * create counter but need to update it with the
3665 : : * AGE parameter, will be done after the loop.
3666 : : */
3667 : : break;
3668 : : /* Fall-through. */
3669 : : case RTE_FLOW_ACTION_TYPE_COUNT:
3670 : : cnt_queue = mlx5_hws_cnt_get_queue(priv, &queue);
3671 : : ret = mlx5_hws_cnt_pool_get(priv->hws_cpool, cnt_queue, &cnt_id, age_idx);
3672 [ # # # # : 0 : if (ret != 0) {
# # # # #
# ]
3673 : 0 : rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_ACTION,
3674 : : action, "Failed to allocate flow counter");
3675 : 0 : goto error;
3676 : : }
3677 : 0 : ret = mlx5_hws_cnt_pool_get_action_offset
3678 : : (priv->hws_cpool,
3679 : : cnt_id,
3680 : : &rule_acts[act_data->action_dst].action,
3681 : 0 : &rule_acts[act_data->action_dst].counter.offset
3682 : : );
3683 : : if (ret != 0)
3684 : : goto error;
3685 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_CNT_ID;
3686 : 0 : flow->cnt_id = cnt_id;
3687 : 0 : break;
3688 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
3689 : 0 : ret = mlx5_hws_cnt_pool_get_action_offset
3690 : : (priv->hws_cpool,
3691 : : act_data->shared_counter.id,
3692 : : &rule_acts[act_data->action_dst].action,
3693 : 0 : &rule_acts[act_data->action_dst].counter.offset
3694 : : );
3695 : : if (ret != 0)
3696 : : goto error;
3697 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_CNT_ID;
3698 : 0 : flow->cnt_id = act_data->shared_counter.id;
3699 : 0 : break;
3700 : 0 : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
3701 : 0 : ct_idx = MLX5_INDIRECT_ACTION_IDX_GET(action->conf);
3702 : 0 : if (flow_hw_ct_compile(dev, queue, ct_idx,
3703 : 0 : &rule_acts[act_data->action_dst]))
3704 : 0 : goto error;
3705 : : break;
3706 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_METER_MARK:
3707 : 0 : mtr_id = act_data->shared_meter.id &
3708 : : ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
3709 : : /* Find ASO object. */
3710 : 0 : aso_mtr = mlx5_ipool_get(pool->idx_pool, mtr_id);
3711 [ # # # # : 0 : if (!aso_mtr)
# # # # #
# ]
3712 : 0 : goto error;
3713 : 0 : rule_acts[act_data->action_dst].action =
3714 : 0 : pool->action;
3715 : 0 : rule_acts[act_data->action_dst].aso_meter.offset =
3716 : 0 : aso_mtr->offset;
3717 : 0 : break;
3718 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
3719 : : /*
3720 : : * Allocate meter directly will slow down flow
3721 : : * insertion rate.
3722 : : */
3723 : : ret = flow_hw_meter_mark_compile(dev,
3724 : 0 : act_data->action_dst, action,
3725 : : rule_acts, &mtr_idx, MLX5_HW_INV_QUEUE, error);
3726 : : if (ret != 0)
3727 : 0 : goto error;
3728 [ # # # # : 0 : aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
# # # # #
# ]
3729 : : mlx5_flow_hw_aux_set_mtr_id(flow, aux, mtr_idx);
3730 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_MTR_ID;
3731 : 0 : break;
3732 : 0 : case RTE_FLOW_ACTION_TYPE_NAT64:
3733 : 0 : nat64_c = action->conf;
3734 : : MLX5_ASSERT(table->type < MLX5DR_TABLE_TYPE_MAX);
3735 : 0 : rule_acts[act_data->action_dst].action =
3736 : 0 : priv->action_nat64[table->type][nat64_c->type];
3737 : 0 : break;
3738 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
3739 : 0 : jump_table = ((const struct rte_flow_action_jump_to_table_index *)
3740 : 0 : action->conf)->table;
3741 [ # # # # : 0 : if (likely(!rte_flow_template_table_resizable(dev->data->port_id,
# # # # #
# ]
3742 : : &table->cfg.attr))) {
3743 : 0 : rule_acts[act_data->action_dst].action =
3744 : 0 : jump_table->matcher_info[0].jump;
3745 : : } else {
3746 : : uint32_t selector;
3747 : 0 : rte_rwlock_read_lock(&table->matcher_replace_rwlk);
3748 : 0 : selector = table->matcher_selector;
3749 : 0 : rule_acts[act_data->action_dst].action =
3750 : 0 : jump_table->matcher_info[selector].jump;
3751 : 0 : rte_rwlock_read_unlock(&table->matcher_replace_rwlk);
3752 : : }
3753 : 0 : rule_acts[act_data->action_dst].jump_to_matcher.offset =
3754 : : ((const struct rte_flow_action_jump_to_table_index *)
3755 : 0 : action->conf)->index;
3756 : 0 : break;
3757 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_MIRROR: {
3758 : 0 : const struct mlx5_mirror *mirror = action->conf;
3759 : :
3760 : 0 : rule_acts[act_data->action_dst].action = mirror->mirror_action;
3761 : 0 : break;
3762 : : }
3763 : : default:
3764 : : break;
3765 : : }
3766 : : }
3767 [ # # # # : 0 : if (at->action_flags & MLX5_FLOW_ACTION_INDIRECT_COUNT) {
# # # # #
# ]
3768 : : /* If indirect count is used, then CNT_ID flag should be set. */
3769 : : MLX5_ASSERT(flow->flags & MLX5_FLOW_HW_FLOW_FLAG_CNT_ID);
3770 [ # # # # : 0 : if (at->action_flags & MLX5_FLOW_ACTION_INDIRECT_AGE) {
# # # # #
# ]
3771 : : /* If indirect AGE is used, then AGE_IDX flag should be set. */
3772 : : MLX5_ASSERT(flow->flags & MLX5_FLOW_HW_FLOW_FLAG_AGE_IDX);
3773 [ # # # # : 0 : aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
# # # # #
# ]
3774 : 0 : age_idx = mlx5_flow_hw_aux_get_age_idx(flow, aux) &
3775 : : MLX5_HWS_AGE_IDX_MASK;
3776 [ # # # # : 0 : if (mlx5_hws_cnt_age_get(priv->hws_cpool, flow->cnt_id) != age_idx)
# # # # #
# # # # #
# # # # #
# ]
3777 : : /*
3778 : : * This is first use of this indirect counter
3779 : : * for this indirect AGE, need to increase the
3780 : : * number of counters.
3781 : : */
3782 : : mlx5_hws_age_nb_cnt_increase(priv, age_idx);
3783 : : }
3784 : : /*
3785 : : * Update this indirect counter the indirect/direct AGE in which
3786 : : * using it.
3787 : : */
3788 [ # # # # : 0 : mlx5_hws_cnt_age_set(priv->hws_cpool, flow->cnt_id, age_idx);
# # # # #
# ]
3789 : : }
3790 [ # # # # : 0 : if (hw_acts->encap_decap && !hw_acts->encap_decap->shared) {
# # # # #
# # # # #
# # # # #
# ]
3791 [ # # # # : 0 : int ix = mlx5_multi_pattern_reformat_to_index(hw_acts->encap_decap->action_type);
# # # # #
# ]
3792 : 0 : struct mlx5dr_rule_action *ra = &rule_acts[hw_acts->encap_decap_pos];
3793 : :
3794 [ # # # # : 0 : if (ix < 0)
# # # # #
# ]
3795 : 0 : goto error;
3796 [ # # # # : 0 : if (!mp_segment)
# # # # #
# ]
3797 : 0 : mp_segment = mlx5_multi_pattern_segment_find(table, flow->res_idx);
3798 [ # # # # : 0 : if (!mp_segment || !mp_segment->reformat_action[ix])
# # # # #
# # # # #
# # # # #
# ]
3799 : 0 : goto error;
3800 : 0 : ra->action = mp_segment->reformat_action[ix];
3801 : : /* reformat offset is relative to selected DR action */
3802 : 0 : ra->reformat.offset = flow->res_idx - mp_segment->head_index;
3803 : 0 : ra->reformat.data = ap->encap_data;
3804 : : }
3805 [ # # # # : 0 : if (hw_acts->push_remove && !hw_acts->push_remove->shared) {
# # # # #
# # # # #
# # # # #
# ]
3806 : 0 : rule_acts[hw_acts->push_remove_pos].ipv6_ext.offset =
3807 : 0 : flow->res_idx - 1;
3808 : 0 : rule_acts[hw_acts->push_remove_pos].ipv6_ext.header = ap->ipv6_push_data;
3809 : : }
3810 [ # # # # : 0 : if (mlx5_hws_cnt_id_valid(hw_acts->cnt_id)) {
# # # # #
# ]
3811 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_CNT_ID;
3812 : 0 : flow->cnt_id = hw_acts->cnt_id;
3813 : : }
3814 : : return 0;
3815 : :
3816 : 0 : error:
3817 : 0 : flow_hw_release_actions(dev, queue, flow);
3818 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3819 : : NULL, "Action construction failed");
3820 : : }
3821 : :
3822 : : static const struct rte_flow_item *
3823 : 0 : flow_hw_get_rule_items(struct rte_eth_dev *dev,
3824 : : const struct rte_flow_template_table *table,
3825 : : const struct rte_flow_item items[],
3826 : : uint8_t pattern_template_index,
3827 : : struct mlx5_flow_hw_pattern_params *pp)
3828 : : {
3829 : 0 : struct rte_flow_pattern_template *pt = table->its[pattern_template_index];
3830 : :
3831 : : /* Only one implicit item can be added to flow rule pattern. */
3832 : : MLX5_ASSERT(!pt->implicit_port || !pt->implicit_tag);
3833 : : /* At least one item was allocated in pattern params for items. */
3834 : : MLX5_ASSERT(MLX5_HW_MAX_ITEMS >= 1);
3835 [ # # ]: 0 : if (pt->implicit_port) {
3836 [ # # ]: 0 : if (pt->orig_item_nb + 1 > MLX5_HW_MAX_ITEMS) {
3837 : 0 : rte_errno = ENOMEM;
3838 : 0 : return NULL;
3839 : : }
3840 : : /* Set up represented port item in pattern params. */
3841 : 0 : pp->port_spec = (struct rte_flow_item_ethdev){
3842 : 0 : .port_id = dev->data->port_id,
3843 : : };
3844 : 0 : pp->items[0] = (struct rte_flow_item){
3845 : : .type = RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT,
3846 : 0 : .spec = &pp->port_spec,
3847 : : };
3848 [ # # ]: 0 : rte_memcpy(&pp->items[1], items, sizeof(*items) * pt->orig_item_nb);
3849 : 0 : return pp->items;
3850 [ # # ]: 0 : } else if (pt->implicit_tag) {
3851 [ # # ]: 0 : if (pt->orig_item_nb + 1 > MLX5_HW_MAX_ITEMS) {
3852 : 0 : rte_errno = ENOMEM;
3853 : 0 : return NULL;
3854 : : }
3855 : : /* Set up tag item in pattern params. */
3856 : 0 : pp->tag_spec = (struct rte_flow_item_tag){
3857 : : .data = flow_hw_tx_tag_regc_value(dev),
3858 : : };
3859 : 0 : pp->items[0] = (struct rte_flow_item){
3860 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_TAG,
3861 : 0 : .spec = &pp->tag_spec,
3862 : : };
3863 : 0 : rte_memcpy(&pp->items[1], items, sizeof(*items) * pt->orig_item_nb);
3864 : 0 : return pp->items;
3865 : : } else {
3866 : : return items;
3867 : : }
3868 : : }
3869 : :
3870 : : /**
3871 : : * Enqueue HW steering flow creation.
3872 : : *
3873 : : * The flow will be applied to the HW only if the postpone bit is not set or
3874 : : * the extra push function is called.
3875 : : * The flow creation status should be checked from dequeue result.
3876 : : *
3877 : : * @param[in] dev
3878 : : * Pointer to the rte_eth_dev structure.
3879 : : * @param[in] queue
3880 : : * The queue to create the flow.
3881 : : * @param[in] attr
3882 : : * Pointer to the flow operation attributes.
3883 : : * @param[in] table
3884 : : * Pointer to the template table.
3885 : : * @param[in] insertion_type
3886 : : * Insertion type for flow rules.
3887 : : * @param[in] rule_index
3888 : : * The item pattern flow follows from the table.
3889 : : * @param[in] items
3890 : : * Items with flow spec value.
3891 : : * @param[in] pattern_template_index
3892 : : * The item pattern flow follows from the table.
3893 : : * @param[in] actions
3894 : : * Action with flow spec value.
3895 : : * @param[in] action_template_index
3896 : : * The action pattern flow follows from the table.
3897 : : * @param[in] user_data
3898 : : * Pointer to the user_data.
3899 : : * @param[out] error
3900 : : * Pointer to error structure.
3901 : : *
3902 : : * @return
3903 : : * Flow pointer on success, NULL otherwise and rte_errno is set.
3904 : : */
3905 : : static __rte_always_inline struct rte_flow *
3906 : : flow_hw_async_flow_create_generic(struct rte_eth_dev *dev,
3907 : : uint32_t queue,
3908 : : const struct rte_flow_op_attr *attr,
3909 : : struct rte_flow_template_table *table,
3910 : : enum rte_flow_table_insertion_type insertion_type,
3911 : : uint32_t rule_index,
3912 : : const struct rte_flow_item items[],
3913 : : uint8_t pattern_template_index,
3914 : : const struct rte_flow_action actions[],
3915 : : uint8_t action_template_index,
3916 : : void *user_data,
3917 : : struct rte_flow_error *error)
3918 : : {
3919 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
3920 : 0 : struct mlx5dr_rule_attr rule_attr = {
3921 : : .queue_id = queue,
3922 : : .user_data = user_data,
3923 : 0 : .burst = attr->postpone,
3924 : : };
3925 : : struct mlx5dr_rule_action *rule_acts;
3926 : : struct rte_flow_hw *flow = NULL;
3927 : : const struct rte_flow_item *rule_items;
3928 : 0 : struct rte_flow_error sub_error = { 0 };
3929 : 0 : uint32_t flow_idx = 0;
3930 : 0 : uint32_t res_idx = 0;
3931 : : int ret;
3932 : :
3933 : 0 : if (mlx5_fp_debug_enabled()) {
3934 [ # # # # : 0 : if (flow_hw_async_create_validate(dev, queue, table, insertion_type, rule_index,
# # ]
3935 : : items, pattern_template_index, actions, action_template_index, error))
3936 : : return NULL;
3937 : : }
3938 : 0 : flow = mlx5_ipool_malloc(table->flow, &flow_idx);
3939 [ # # # # : 0 : if (!flow) {
# # ]
3940 : 0 : rte_errno = ENOMEM;
3941 : 0 : goto error;
3942 : : }
3943 : 0 : flow->nt_rule = false;
3944 : : rule_acts = flow_hw_get_dr_action_buffer(priv, table, action_template_index, queue);
3945 : : /*
3946 : : * Set the table here in order to know the destination table
3947 : : * when free the flow afterward.
3948 : : */
3949 : 0 : flow->table = table;
3950 : 0 : flow->mt_idx = pattern_template_index;
3951 : 0 : flow->idx = flow_idx;
3952 [ # # # # : 0 : if (table->resource) {
# # ]
3953 : 0 : mlx5_ipool_malloc(table->resource, &res_idx);
3954 [ # # # # : 0 : if (!res_idx) {
# # ]
3955 : 0 : rte_errno = ENOMEM;
3956 : 0 : goto error;
3957 : : }
3958 : 0 : flow->res_idx = res_idx;
3959 : : } else {
3960 : 0 : flow->res_idx = flow_idx;
3961 : : }
3962 : 0 : flow->flags = 0;
3963 : : /*
3964 : : * Set the flow operation type here in order to know if the flow memory
3965 : : * should be freed or not when get the result from dequeue.
3966 : : */
3967 : 0 : flow->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_CREATE;
3968 : 0 : flow->user_data = user_data;
3969 : 0 : rule_attr.user_data = flow;
3970 : : /*
3971 : : * Indexed pool returns 1-based indices, but mlx5dr expects 0-based indices
3972 : : * for rule insertion hints.
3973 : : */
3974 [ # # # # ]: 0 : flow->rule_idx = (rule_index == UINT32_MAX) ? flow->res_idx - 1 : rule_index;
3975 : 0 : rule_attr.rule_idx = flow->rule_idx;
3976 : : /*
3977 : : * Construct the flow actions based on the input actions.
3978 : : * The implicitly appended action is always fixed, like metadata
3979 : : * copy action from FDB to NIC Rx.
3980 : : * No need to copy and contrust a new "actions" list based on the
3981 : : * user's input, in order to save the cost.
3982 : : */
3983 [ # # # # : 0 : if (flow_hw_actions_construct(dev, flow, &priv->hw_q[queue].ap,
# # ]
3984 : 0 : &table->ats[action_template_index],
3985 [ # # # # : 0 : table->its[pattern_template_index]->item_flags,
# # ]
3986 : : flow->table, actions,
3987 : : rule_acts, queue, &sub_error))
3988 : 0 : goto error;
3989 : : if (insertion_type == RTE_FLOW_TABLE_INSERTION_TYPE_INDEX) {
3990 : : rule_items = items;
3991 : : } else {
3992 : 0 : rule_items = flow_hw_get_rule_items(dev, table, items,
3993 : 0 : pattern_template_index, &priv->hw_q[queue].pp);
3994 [ # # # # ]: 0 : if (!rule_items)
3995 : 0 : goto error;
3996 : : }
3997 [ # # # # : 0 : if (likely(!rte_flow_template_table_resizable(dev->data->port_id, &table->cfg.attr))) {
# # ]
3998 : 0 : ret = mlx5dr_rule_create(table->matcher_info[0].matcher,
3999 : : pattern_template_index, rule_items,
4000 : : action_template_index, rule_acts,
4001 : : &rule_attr,
4002 : 0 : (struct mlx5dr_rule *)flow->rule);
4003 : : } else {
4004 [ # # # # : 0 : struct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
# # ]
4005 : : uint32_t selector;
4006 : :
4007 : 0 : flow->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_CREATE;
4008 : 0 : rte_rwlock_read_lock(&table->matcher_replace_rwlk);
4009 : 0 : selector = table->matcher_selector;
4010 : 0 : ret = mlx5dr_rule_create(table->matcher_info[selector].matcher,
4011 : : pattern_template_index, rule_items,
4012 : : action_template_index, rule_acts,
4013 : : &rule_attr,
4014 : 0 : (struct mlx5dr_rule *)flow->rule);
4015 : 0 : rte_rwlock_read_unlock(&table->matcher_replace_rwlk);
4016 : 0 : aux->matcher_selector = selector;
4017 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_MATCHER_SELECTOR;
4018 : : }
4019 : :
4020 [ # # # # : 0 : if (likely(!ret)) {
# # ]
4021 : 0 : flow_hw_q_inc_flow_ops(priv, queue);
4022 : 0 : return (struct rte_flow *)flow;
4023 : : }
4024 : 0 : error:
4025 [ # # # # : 0 : if (table->resource && res_idx)
# # # # #
# # # ]
4026 : 0 : mlx5_ipool_free(table->resource, res_idx);
4027 [ # # # # : 0 : if (flow_idx)
# # ]
4028 : 0 : mlx5_ipool_free(table->flow, flow_idx);
4029 [ # # # # : 0 : if (sub_error.cause != RTE_FLOW_ERROR_TYPE_NONE && error != NULL)
# # # # #
# # # ]
4030 : 0 : *error = sub_error;
4031 : : else
4032 : 0 : rte_flow_error_set(error, rte_errno,
4033 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4034 : : "fail to create rte flow");
4035 : : return NULL;
4036 : : }
4037 : :
4038 : : static struct rte_flow *
4039 : 0 : flow_hw_async_flow_create(struct rte_eth_dev *dev,
4040 : : uint32_t queue,
4041 : : const struct rte_flow_op_attr *attr,
4042 : : struct rte_flow_template_table *table,
4043 : : const struct rte_flow_item items[],
4044 : : uint8_t pattern_template_index,
4045 : : const struct rte_flow_action actions[],
4046 : : uint8_t action_template_index,
4047 : : void *user_data,
4048 : : struct rte_flow_error *error)
4049 : : {
4050 : : uint32_t rule_index = UINT32_MAX;
4051 : :
4052 [ # # ]: 0 : return flow_hw_async_flow_create_generic(dev, queue, attr, table,
4053 : : RTE_FLOW_TABLE_INSERTION_TYPE_PATTERN, rule_index,
4054 : : items, pattern_template_index, actions, action_template_index,
4055 : : user_data, error);
4056 : : }
4057 : :
4058 : : static struct rte_flow *
4059 : 0 : flow_hw_async_flow_create_by_index(struct rte_eth_dev *dev,
4060 : : uint32_t queue,
4061 : : const struct rte_flow_op_attr *attr,
4062 : : struct rte_flow_template_table *table,
4063 : : uint32_t rule_index,
4064 : : const struct rte_flow_action actions[],
4065 : : uint8_t action_template_index,
4066 : : void *user_data,
4067 : : struct rte_flow_error *error)
4068 : : {
4069 : 0 : struct rte_flow_item items[] = {{.type = RTE_FLOW_ITEM_TYPE_END,}};
4070 : : uint8_t pattern_template_index = 0;
4071 : :
4072 [ # # ]: 0 : return flow_hw_async_flow_create_generic(dev, queue, attr, table,
4073 : : RTE_FLOW_TABLE_INSERTION_TYPE_INDEX, rule_index,
4074 : : items, pattern_template_index, actions, action_template_index,
4075 : : user_data, error);
4076 : : }
4077 : :
4078 : : static struct rte_flow *
4079 : 0 : flow_hw_async_flow_create_by_index_with_pattern(struct rte_eth_dev *dev,
4080 : : uint32_t queue,
4081 : : const struct rte_flow_op_attr *attr,
4082 : : struct rte_flow_template_table *table,
4083 : : uint32_t rule_index,
4084 : : const struct rte_flow_item items[],
4085 : : uint8_t pattern_template_index,
4086 : : const struct rte_flow_action actions[],
4087 : : uint8_t action_template_index,
4088 : : void *user_data,
4089 : : struct rte_flow_error *error)
4090 : : {
4091 [ # # ]: 0 : return flow_hw_async_flow_create_generic(dev, queue, attr, table,
4092 : : RTE_FLOW_TABLE_INSERTION_TYPE_INDEX_WITH_PATTERN, rule_index,
4093 : : items, pattern_template_index, actions, action_template_index,
4094 : : user_data, error);
4095 : : }
4096 : :
4097 : : /**
4098 : : * Enqueue HW steering flow update.
4099 : : *
4100 : : * The flow will be applied to the HW only if the postpone bit is not set or
4101 : : * the extra push function is called.
4102 : : * The flow destruction status should be checked from dequeue result.
4103 : : *
4104 : : * @param[in] dev
4105 : : * Pointer to the rte_eth_dev structure.
4106 : : * @param[in] queue
4107 : : * The queue to destroy the flow.
4108 : : * @param[in] attr
4109 : : * Pointer to the flow operation attributes.
4110 : : * @param[in] flow
4111 : : * Pointer to the flow to be destroyed.
4112 : : * @param[in] actions
4113 : : * Action with flow spec value.
4114 : : * @param[in] action_template_index
4115 : : * The action pattern flow follows from the table.
4116 : : * @param[in] user_data
4117 : : * Pointer to the user_data.
4118 : : * @param[out] error
4119 : : * Pointer to error structure.
4120 : : *
4121 : : * @return
4122 : : * 0 on success, negative value otherwise and rte_errno is set.
4123 : : */
4124 : : static int
4125 : 0 : flow_hw_async_flow_update(struct rte_eth_dev *dev,
4126 : : uint32_t queue,
4127 : : const struct rte_flow_op_attr *attr,
4128 : : struct rte_flow *flow,
4129 : : const struct rte_flow_action actions[],
4130 : : uint8_t action_template_index,
4131 : : void *user_data,
4132 : : struct rte_flow_error *error)
4133 : : {
4134 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4135 : 0 : struct mlx5dr_rule_attr rule_attr = {
4136 : : .queue_id = queue,
4137 : : .user_data = user_data,
4138 : 0 : .burst = attr->postpone,
4139 : : };
4140 : : struct mlx5dr_rule_action *rule_acts;
4141 : : struct rte_flow_hw *of = (struct rte_flow_hw *)flow;
4142 : : struct rte_flow_hw *nf;
4143 : : struct rte_flow_hw_aux *aux;
4144 : 0 : struct rte_flow_template_table *table = of->table;
4145 : 0 : uint32_t res_idx = 0;
4146 : : int ret;
4147 : :
4148 [ # # ]: 0 : if (mlx5_fp_debug_enabled()) {
4149 [ # # ]: 0 : if (flow_hw_async_update_validate(dev, queue, of, actions, action_template_index,
4150 : : error))
4151 : 0 : return -rte_errno;
4152 : : }
4153 [ # # ]: 0 : aux = mlx5_flow_hw_aux(dev->data->port_id, of);
4154 : 0 : nf = &aux->upd_flow;
4155 : 0 : nf->nt_rule = false;
4156 : 0 : rule_acts = flow_hw_get_dr_action_buffer(priv, table, action_template_index, queue);
4157 : : /*
4158 : : * Set the table here in order to know the destination table
4159 : : * when free the flow afterwards.
4160 : : */
4161 : 0 : nf->table = table;
4162 : 0 : nf->mt_idx = of->mt_idx;
4163 : 0 : nf->idx = of->idx;
4164 [ # # ]: 0 : if (table->resource) {
4165 : 0 : mlx5_ipool_malloc(table->resource, &res_idx);
4166 [ # # ]: 0 : if (!res_idx) {
4167 : 0 : rte_errno = ENOMEM;
4168 : 0 : goto error;
4169 : : }
4170 : 0 : nf->res_idx = res_idx;
4171 : : } else {
4172 : 0 : nf->res_idx = of->res_idx;
4173 : : }
4174 : 0 : nf->flags = 0;
4175 : : /* Indicate the construction function to set the proper fields. */
4176 : 0 : nf->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE;
4177 : : /*
4178 : : * Indexed pool returns 1-based indices, but mlx5dr expects 0-based indices
4179 : : * for rule insertion hints.
4180 : : * If there is only one STE, the update will be atomic by nature.
4181 : : */
4182 : 0 : nf->rule_idx = nf->res_idx - 1;
4183 : 0 : rule_attr.rule_idx = nf->rule_idx;
4184 : : /*
4185 : : * Construct the flow actions based on the input actions.
4186 : : * The implicitly appended action is always fixed, like metadata
4187 : : * copy action from FDB to NIC Rx.
4188 : : * No need to copy and contrust a new "actions" list based on the
4189 : : * user's input, in order to save the cost.
4190 : : */
4191 [ # # ]: 0 : if (flow_hw_actions_construct(dev, nf, &priv->hw_q[queue].ap,
4192 : 0 : &table->ats[action_template_index],
4193 [ # # ]: 0 : table->its[nf->mt_idx]->item_flags,
4194 : : table, actions,
4195 : : rule_acts, queue, error)) {
4196 : 0 : rte_errno = EINVAL;
4197 : 0 : goto error;
4198 : : }
4199 : : /*
4200 : : * Set the flow operation type here in order to know if the flow memory
4201 : : * should be freed or not when get the result from dequeue.
4202 : : */
4203 : 0 : of->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE;
4204 : 0 : of->user_data = user_data;
4205 : 0 : of->flags |= MLX5_FLOW_HW_FLOW_FLAG_UPD_FLOW;
4206 : 0 : rule_attr.user_data = of;
4207 : 0 : ret = mlx5dr_rule_action_update((struct mlx5dr_rule *)of->rule,
4208 : : action_template_index, rule_acts, &rule_attr);
4209 [ # # ]: 0 : if (likely(!ret)) {
4210 : 0 : flow_hw_q_inc_flow_ops(priv, queue);
4211 : 0 : return 0;
4212 : : }
4213 : 0 : error:
4214 [ # # # # ]: 0 : if (table->resource && res_idx)
4215 : 0 : mlx5_ipool_free(table->resource, res_idx);
4216 : 0 : return rte_flow_error_set(error, rte_errno,
4217 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4218 : : "fail to update rte flow");
4219 : : }
4220 : :
4221 : : /**
4222 : : * Enqueue HW steering flow destruction.
4223 : : *
4224 : : * The flow will be applied to the HW only if the postpone bit is not set or
4225 : : * the extra push function is called.
4226 : : * The flow destruction status should be checked from dequeue result.
4227 : : *
4228 : : * @param[in] dev
4229 : : * Pointer to the rte_eth_dev structure.
4230 : : * @param[in] queue
4231 : : * The queue to destroy the flow.
4232 : : * @param[in] attr
4233 : : * Pointer to the flow operation attributes.
4234 : : * @param[in] flow
4235 : : * Pointer to the flow to be destroyed.
4236 : : * @param[in] user_data
4237 : : * Pointer to the user_data.
4238 : : * @param[out] error
4239 : : * Pointer to error structure.
4240 : : *
4241 : : * @return
4242 : : * 0 on success, negative value otherwise and rte_errno is set.
4243 : : */
4244 : : static int
4245 : 0 : flow_hw_async_flow_destroy(struct rte_eth_dev *dev,
4246 : : uint32_t queue,
4247 : : const struct rte_flow_op_attr *attr,
4248 : : struct rte_flow *flow,
4249 : : void *user_data,
4250 : : struct rte_flow_error *error)
4251 : : {
4252 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4253 : 0 : struct mlx5dr_rule_attr rule_attr = {
4254 : : .queue_id = queue,
4255 : : .user_data = user_data,
4256 : 0 : .burst = attr->postpone,
4257 : : };
4258 : : struct rte_flow_hw *fh = (struct rte_flow_hw *)flow;
4259 : 0 : bool resizable = rte_flow_template_table_resizable(dev->data->port_id,
4260 : 0 : &fh->table->cfg.attr);
4261 : : int ret;
4262 : :
4263 : : if (mlx5_fp_debug_enabled()) {
4264 : : if (flow_hw_async_destroy_validate(dev, queue, fh, error))
4265 : : return -rte_errno;
4266 : : }
4267 [ # # ]: 0 : fh->operation_type = !resizable ?
4268 : : MLX5_FLOW_HW_FLOW_OP_TYPE_DESTROY :
4269 : : MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_DESTROY;
4270 : 0 : fh->user_data = user_data;
4271 : 0 : rule_attr.user_data = fh;
4272 : 0 : rule_attr.rule_idx = fh->rule_idx;
4273 : 0 : ret = mlx5dr_rule_destroy((struct mlx5dr_rule *)fh->rule, &rule_attr);
4274 [ # # ]: 0 : if (ret) {
4275 : 0 : return rte_flow_error_set(error, rte_errno,
4276 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4277 : : "fail to destroy rte flow");
4278 : : }
4279 : : flow_hw_q_inc_flow_ops(priv, queue);
4280 : 0 : return 0;
4281 : : }
4282 : :
4283 : : /**
4284 : : * Release the AGE and counter for given flow.
4285 : : *
4286 : : * @param[in] priv
4287 : : * Pointer to the port private data structure.
4288 : : * @param[in] queue
4289 : : * The queue to release the counter.
4290 : : * @param[in, out] flow
4291 : : * Pointer to the flow containing the counter.
4292 : : * @param[out] error
4293 : : * Pointer to error structure.
4294 : : */
4295 : : static void
4296 : 0 : flow_hw_age_count_release(struct mlx5_priv *priv, uint32_t queue,
4297 : : struct rte_flow_hw *flow,
4298 : : struct rte_flow_error *error)
4299 : : {
4300 [ # # ]: 0 : struct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(priv->dev_data->port_id, flow);
4301 : : uint32_t *cnt_queue;
4302 : 0 : uint32_t age_idx = aux->orig.age_idx;
4303 : :
4304 : : MLX5_ASSERT(flow->flags & MLX5_FLOW_HW_FLOW_FLAG_CNT_ID);
4305 [ # # # # ]: 0 : if (mlx5_hws_cnt_is_shared(priv->hws_cpool, flow->cnt_id)) {
4306 [ # # # # ]: 0 : if ((flow->flags & MLX5_FLOW_HW_FLOW_FLAG_AGE_IDX) &&
4307 : : !mlx5_hws_age_is_indirect(age_idx)) {
4308 : : /* Remove this AGE parameter from indirect counter. */
4309 : : mlx5_hws_cnt_age_set(priv->hws_cpool, flow->cnt_id, 0);
4310 : : /* Release the AGE parameter. */
4311 : 0 : mlx5_hws_age_action_destroy(priv, age_idx, error);
4312 : : }
4313 : 0 : return;
4314 : : }
4315 : : cnt_queue = mlx5_hws_cnt_get_queue(priv, &queue);
4316 : : /* Put the counter first to reduce the race risk in BG thread. */
4317 [ # # ]: 0 : mlx5_hws_cnt_pool_put(priv->hws_cpool, cnt_queue, &flow->cnt_id);
4318 [ # # ]: 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_AGE_IDX) {
4319 [ # # ]: 0 : if (mlx5_hws_age_is_indirect(age_idx)) {
4320 : 0 : uint32_t idx = age_idx & MLX5_HWS_AGE_IDX_MASK;
4321 : :
4322 : : mlx5_hws_age_nb_cnt_decrease(priv, idx);
4323 : : } else {
4324 : : /* Release the AGE parameter. */
4325 : 0 : mlx5_hws_age_action_destroy(priv, age_idx, error);
4326 : : }
4327 : : }
4328 : : }
4329 : :
4330 : : static __rte_always_inline void
4331 : : flow_hw_pull_legacy_indirect_comp(struct rte_eth_dev *dev, struct mlx5_hw_q_job *job,
4332 : : uint32_t queue)
4333 : : {
4334 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4335 : : struct mlx5_aso_ct_action *aso_ct;
4336 : : struct mlx5_aso_mtr *aso_mtr;
4337 : : uint32_t type, idx;
4338 : :
4339 [ # # ]: 0 : if (MLX5_INDIRECT_ACTION_TYPE_GET(job->action) ==
4340 : : MLX5_INDIRECT_ACTION_TYPE_QUOTA) {
4341 : 0 : mlx5_quota_async_completion(dev, queue, job);
4342 [ # # ]: 0 : } else if (job->type == MLX5_HW_Q_JOB_TYPE_DESTROY) {
4343 : : type = MLX5_INDIRECT_ACTION_TYPE_GET(job->action);
4344 [ # # ]: 0 : if (type == MLX5_INDIRECT_ACTION_TYPE_METER_MARK) {
4345 : 0 : idx = MLX5_INDIRECT_ACTION_IDX_GET(job->action);
4346 : 0 : mlx5_ipool_free(priv->hws_mpool->idx_pool, idx);
4347 : : }
4348 [ # # ]: 0 : } else if (job->type == MLX5_HW_Q_JOB_TYPE_CREATE) {
4349 : : type = MLX5_INDIRECT_ACTION_TYPE_GET(job->action);
4350 [ # # ]: 0 : if (type == MLX5_INDIRECT_ACTION_TYPE_METER_MARK) {
4351 : 0 : idx = MLX5_INDIRECT_ACTION_IDX_GET(job->action);
4352 : 0 : aso_mtr = mlx5_ipool_get(priv->hws_mpool->idx_pool, idx);
4353 : 0 : aso_mtr->state = ASO_METER_READY;
4354 [ # # ]: 0 : } else if (type == MLX5_INDIRECT_ACTION_TYPE_CT) {
4355 : 0 : idx = MLX5_INDIRECT_ACTION_IDX_GET(job->action);
4356 : 0 : aso_ct = mlx5_ipool_get(priv->hws_ctpool->cts, idx);
4357 : 0 : aso_ct->state = ASO_CONNTRACK_READY;
4358 : : }
4359 [ # # ]: 0 : } else if (job->type == MLX5_HW_Q_JOB_TYPE_QUERY) {
4360 : : type = MLX5_INDIRECT_ACTION_TYPE_GET(job->action);
4361 [ # # ]: 0 : if (type == MLX5_INDIRECT_ACTION_TYPE_CT) {
4362 : 0 : idx = MLX5_INDIRECT_ACTION_IDX_GET(job->action);
4363 : 0 : aso_ct = mlx5_ipool_get(priv->hws_ctpool->cts, idx);
4364 : 0 : mlx5_aso_ct_obj_analyze(job->query.user,
4365 : 0 : job->query.hw);
4366 : 0 : aso_ct->state = ASO_CONNTRACK_READY;
4367 : : }
4368 : : }
4369 : : }
4370 : :
4371 : : static __rte_always_inline int
4372 : : mlx5_hw_pull_flow_transfer_comp(struct rte_eth_dev *dev,
4373 : : uint32_t queue, struct rte_flow_op_result res[],
4374 : : uint16_t n_res)
4375 : : {
4376 : : uint32_t size, i;
4377 : 0 : struct rte_flow_hw *flow = NULL;
4378 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4379 : 0 : struct rte_ring *ring = priv->hw_q[queue].flow_transfer_completed;
4380 : :
4381 : 0 : size = RTE_MIN(rte_ring_count(ring), n_res);
4382 [ # # ]: 0 : for (i = 0; i < size; i++) {
4383 [ # # # # : 0 : res[i].status = RTE_FLOW_OP_SUCCESS;
# ]
4384 : : rte_ring_dequeue(ring, (void **)&flow);
4385 : 0 : res[i].user_data = flow->user_data;
4386 : : flow_hw_q_dec_flow_ops(priv, queue);
4387 : : }
4388 : 0 : return (int)size;
4389 : : }
4390 : :
4391 : : static inline int
4392 : 0 : __flow_hw_pull_indir_action_comp(struct rte_eth_dev *dev,
4393 : : uint32_t queue,
4394 : : struct rte_flow_op_result res[],
4395 : : uint16_t n_res)
4396 : :
4397 : : {
4398 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4399 : 0 : struct rte_ring *r = priv->hw_q[queue].indir_cq;
4400 : 0 : void *user_data = NULL;
4401 : : int ret_comp, i;
4402 : :
4403 : 0 : ret_comp = (int)rte_ring_count(r);
4404 : 0 : if (ret_comp > n_res)
4405 : : ret_comp = n_res;
4406 [ # # ]: 0 : for (i = 0; i < ret_comp; i++) {
4407 : : rte_ring_dequeue(r, &user_data);
4408 : 0 : res[i].user_data = user_data;
4409 : 0 : res[i].status = RTE_FLOW_OP_SUCCESS;
4410 : : }
4411 [ # # ]: 0 : if (!priv->shared_host) {
4412 [ # # # # ]: 0 : if (ret_comp < n_res && priv->hws_mpool)
4413 : 0 : ret_comp += mlx5_aso_pull_completion(&priv->hws_mpool->sq[queue],
4414 : 0 : &res[ret_comp], n_res - ret_comp);
4415 [ # # # # ]: 0 : if (ret_comp < n_res && priv->hws_ctpool)
4416 : 0 : ret_comp += mlx5_aso_pull_completion(&priv->ct_mng->aso_sqs[queue],
4417 : 0 : &res[ret_comp], n_res - ret_comp);
4418 : : }
4419 [ # # # # ]: 0 : if (ret_comp < n_res && priv->quota_ctx.sq)
4420 : 0 : ret_comp += mlx5_aso_pull_completion(&priv->quota_ctx.sq[queue],
4421 : 0 : &res[ret_comp],
4422 : 0 : n_res - ret_comp);
4423 [ # # ]: 0 : for (i = 0; i < ret_comp; i++) {
4424 : 0 : struct mlx5_hw_q_job *job = (struct mlx5_hw_q_job *)res[i].user_data;
4425 : :
4426 : : /* Restore user data. */
4427 : 0 : res[i].user_data = job->user_data;
4428 [ # # ]: 0 : if (job->indirect_type == MLX5_HW_INDIRECT_TYPE_LEGACY)
4429 : : flow_hw_pull_legacy_indirect_comp(dev, job, queue);
4430 : : /*
4431 : : * Current PMD supports 2 indirect action list types - MIRROR and REFORMAT.
4432 : : * These indirect list types do not post WQE to create action.
4433 : : * Future indirect list types that do post WQE will add
4434 : : * completion handlers here.
4435 : : */
4436 : : flow_hw_job_put(priv, job, queue);
4437 : : }
4438 : 0 : return ret_comp;
4439 : : }
4440 : :
4441 : : static __rte_always_inline void
4442 : : hw_cmpl_flow_update_or_destroy(struct rte_eth_dev *dev,
4443 : : struct rte_flow_hw *flow,
4444 : : uint32_t queue, struct rte_flow_error *error)
4445 : : {
4446 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4447 : 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
4448 : 0 : struct rte_flow_template_table *table = flow->table;
4449 : : /* Release the original resource index in case of update. */
4450 : 0 : uint32_t res_idx = flow->res_idx;
4451 : :
4452 [ # # ]: 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAGS_ALL) {
4453 [ # # # # : 0 : struct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
# # ]
4454 : :
4455 [ # # # # : 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_FATE_JUMP)
# # ]
4456 : 0 : flow_hw_jump_release(dev, flow->jump);
4457 [ # # # # : 0 : else if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_FATE_HRXQ)
# # ]
4458 : 0 : mlx5_hrxq_obj_release(dev, flow->hrxq);
4459 [ # # # # : 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_CNT_ID)
# # ]
4460 : 0 : flow_hw_age_count_release(priv, queue, flow, error);
4461 [ # # # # : 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_MTR_ID)
# # ]
4462 : 0 : mlx5_ipool_free(pool->idx_pool, aux->orig.mtr_id);
4463 [ # # # # : 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_UPD_FLOW) {
# # ]
4464 [ # # # # : 0 : struct rte_flow_hw *upd_flow = &aux->upd_flow;
# # ]
4465 : :
4466 : : rte_memcpy(flow, upd_flow, offsetof(struct rte_flow_hw, rule));
4467 : 0 : aux->orig = aux->upd;
4468 : 0 : flow->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_CREATE;
4469 [ # # # # : 0 : if (!flow->nt_rule && table->resource)
# # # # #
# # # ]
4470 : 0 : mlx5_ipool_free(table->resource, res_idx);
4471 : : }
4472 : : }
4473 [ # # # # : 0 : if (flow->operation_type == MLX5_FLOW_HW_FLOW_OP_TYPE_DESTROY ||
# # ]
4474 : : flow->operation_type == MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_DESTROY) {
4475 [ # # # # : 0 : if (!flow->nt_rule) {
# # ]
4476 [ # # # # : 0 : if (table->resource)
# # ]
4477 : 0 : mlx5_ipool_free(table->resource, res_idx);
4478 : 0 : mlx5_ipool_free(table->flow, flow->idx);
4479 : : }
4480 : : }
4481 : : }
4482 : :
4483 : : static __rte_always_inline void
4484 : : hw_cmpl_resizable_tbl(struct rte_eth_dev *dev,
4485 : : struct rte_flow_hw *flow,
4486 : : uint32_t queue, enum rte_flow_op_status status,
4487 : : struct rte_flow_error *error)
4488 : : {
4489 : 0 : struct rte_flow_template_table *table = flow->table;
4490 : 0 : struct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
4491 : 0 : uint32_t selector = aux->matcher_selector;
4492 : 0 : uint32_t other_selector = (selector + 1) & 1;
4493 : :
4494 : : MLX5_ASSERT(flow->flags & MLX5_FLOW_HW_FLOW_FLAG_MATCHER_SELECTOR);
4495 [ # # # # ]: 0 : switch (flow->operation_type) {
4496 : 0 : case MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_CREATE:
4497 : 0 : rte_atomic_fetch_add_explicit
4498 : : (&table->matcher_info[selector].refcnt, 1,
4499 : : rte_memory_order_relaxed);
4500 : 0 : break;
4501 : 0 : case MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_DESTROY:
4502 [ # # ]: 0 : rte_atomic_fetch_sub_explicit
4503 : : (&table->matcher_info[selector].refcnt, 1,
4504 : : rte_memory_order_relaxed);
4505 : : hw_cmpl_flow_update_or_destroy(dev, flow, queue, error);
4506 : : break;
4507 : 0 : case MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_MOVE:
4508 [ # # ]: 0 : if (status == RTE_FLOW_OP_SUCCESS) {
4509 : 0 : rte_atomic_fetch_sub_explicit
4510 : : (&table->matcher_info[selector].refcnt, 1,
4511 : : rte_memory_order_relaxed);
4512 : 0 : rte_atomic_fetch_add_explicit
4513 : : (&table->matcher_info[other_selector].refcnt, 1,
4514 : : rte_memory_order_relaxed);
4515 : 0 : aux->matcher_selector = other_selector;
4516 : : }
4517 : : break;
4518 : : default:
4519 : : break;
4520 : : }
4521 : : }
4522 : :
4523 : : /**
4524 : : * Pull the enqueued flows.
4525 : : *
4526 : : * For flows enqueued from creation/destruction, the status should be
4527 : : * checked from the dequeue result.
4528 : : *
4529 : : * @param[in] dev
4530 : : * Pointer to the rte_eth_dev structure.
4531 : : * @param[in] queue
4532 : : * The queue to pull the result.
4533 : : * @param[in/out] res
4534 : : * Array to save the results.
4535 : : * @param[in] n_res
4536 : : * Available result with the array.
4537 : : * @param[out] error
4538 : : * Pointer to error structure.
4539 : : *
4540 : : * @return
4541 : : * Result number on success, negative value otherwise and rte_errno is set.
4542 : : */
4543 : : static int
4544 : 0 : flow_hw_pull(struct rte_eth_dev *dev,
4545 : : uint32_t queue,
4546 : : struct rte_flow_op_result res[],
4547 : : uint16_t n_res,
4548 : : struct rte_flow_error *error)
4549 : : {
4550 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4551 : : int ret, i;
4552 : :
4553 : : /* 1. Pull the flow completion. */
4554 : 0 : ret = mlx5dr_send_queue_poll(priv->dr_ctx, queue, res, n_res);
4555 [ # # ]: 0 : if (ret < 0)
4556 : 0 : return rte_flow_error_set(error, rte_errno,
4557 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4558 : : "fail to query flow queue");
4559 [ # # ]: 0 : for (i = 0; i < ret; i++) {
4560 : 0 : struct rte_flow_hw *flow = res[i].user_data;
4561 : :
4562 : : /* Restore user data. */
4563 : 0 : res[i].user_data = flow->user_data;
4564 [ # # # ]: 0 : switch (flow->operation_type) {
4565 : : case MLX5_FLOW_HW_FLOW_OP_TYPE_DESTROY:
4566 : : case MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE:
4567 : : hw_cmpl_flow_update_or_destroy(dev, flow, queue, error);
4568 : : break;
4569 : 0 : case MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_CREATE:
4570 : : case MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_DESTROY:
4571 : : case MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_MOVE:
4572 [ # # ]: 0 : hw_cmpl_resizable_tbl(dev, flow, queue, res[i].status, error);
4573 : : break;
4574 : : default:
4575 : : break;
4576 : : }
4577 : : flow_hw_q_dec_flow_ops(priv, queue);
4578 : : }
4579 : : /* 2. Pull indirect action comp. */
4580 [ # # ]: 0 : if (ret < n_res)
4581 : 0 : ret += __flow_hw_pull_indir_action_comp(dev, queue, &res[ret],
4582 : 0 : n_res - ret);
4583 [ # # ]: 0 : if (ret < n_res)
4584 : 0 : ret += mlx5_hw_pull_flow_transfer_comp(dev, queue, &res[ret],
4585 : 0 : n_res - ret);
4586 : :
4587 : : return ret;
4588 : : }
4589 : :
4590 : : static uint32_t
4591 : 0 : mlx5_hw_push_queue(struct rte_ring *pending_q, struct rte_ring *cmpl_q)
4592 : : {
4593 : 0 : void *job = NULL;
4594 : : uint32_t i, size = rte_ring_count(pending_q);
4595 : :
4596 [ # # ]: 0 : for (i = 0; i < size; i++) {
4597 : : rte_ring_dequeue(pending_q, &job);
4598 [ # # # # : 0 : rte_ring_enqueue(cmpl_q, job);
# ]
4599 : : }
4600 : 0 : return size;
4601 : : }
4602 : :
4603 : : static inline uint32_t
4604 : 0 : __flow_hw_push_action(struct rte_eth_dev *dev,
4605 : : uint32_t queue)
4606 : : {
4607 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4608 : 0 : struct mlx5_hw_q *hw_q = &priv->hw_q[queue];
4609 : :
4610 : 0 : mlx5_hw_push_queue(hw_q->indir_iq, hw_q->indir_cq);
4611 : 0 : mlx5_hw_push_queue(hw_q->flow_transfer_pending,
4612 : : hw_q->flow_transfer_completed);
4613 [ # # ]: 0 : if (!priv->shared_host) {
4614 [ # # ]: 0 : if (priv->hws_ctpool)
4615 : 0 : mlx5_aso_push_wqe(priv->sh,
4616 : 0 : &priv->ct_mng->aso_sqs[queue]);
4617 [ # # ]: 0 : if (priv->hws_mpool)
4618 : 0 : mlx5_aso_push_wqe(priv->sh,
4619 : 0 : &priv->hws_mpool->sq[queue]);
4620 : : }
4621 : 0 : return flow_hw_q_pending(priv, queue);
4622 : : }
4623 : :
4624 : : static int
4625 : 0 : __flow_hw_push(struct rte_eth_dev *dev,
4626 : : uint32_t queue,
4627 : : struct rte_flow_error *error)
4628 : : {
4629 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4630 : : int ret, num;
4631 : :
4632 : 0 : num = __flow_hw_push_action(dev, queue);
4633 : 0 : ret = mlx5dr_send_queue_action(priv->dr_ctx, queue,
4634 : : MLX5DR_SEND_QUEUE_ACTION_DRAIN_ASYNC);
4635 [ # # ]: 0 : if (ret) {
4636 : 0 : rte_flow_error_set(error, rte_errno,
4637 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4638 : : "fail to push flows");
4639 : 0 : return ret;
4640 : : }
4641 : : return num;
4642 : : }
4643 : :
4644 : : /**
4645 : : * Push the enqueued flows to HW.
4646 : : *
4647 : : * Force apply all the enqueued flows to the HW.
4648 : : *
4649 : : * @param[in] dev
4650 : : * Pointer to the rte_eth_dev structure.
4651 : : * @param[in] queue
4652 : : * The queue to push the flow.
4653 : : * @param[out] error
4654 : : * Pointer to error structure.
4655 : : *
4656 : : * @return
4657 : : * 0 on success, negative value otherwise and rte_errno is set.
4658 : : */
4659 : : static int
4660 : 0 : flow_hw_push(struct rte_eth_dev *dev,
4661 : : uint32_t queue, struct rte_flow_error *error)
4662 : : {
4663 : 0 : int ret = __flow_hw_push(dev, queue, error);
4664 : :
4665 : 0 : return ret >= 0 ? 0 : ret;
4666 : : }
4667 : :
4668 : : /**
4669 : : * Drain the enqueued flows' completion.
4670 : : *
4671 : : * @param[in] dev
4672 : : * Pointer to the rte_eth_dev structure.
4673 : : * @param[in] queue
4674 : : * The queue to pull the flow.
4675 : : * @param[out] error
4676 : : * Pointer to error structure.
4677 : : *
4678 : : * @return
4679 : : * 0 on success, negative value otherwise and rte_errno is set.
4680 : : */
4681 : : static int
4682 : 0 : __flow_hw_pull_comp(struct rte_eth_dev *dev,
4683 : : uint32_t queue, struct rte_flow_error *error)
4684 : : {
4685 : : struct rte_flow_op_result comp[BURST_THR];
4686 : : int ret, i, empty_loop = 0;
4687 : : uint32_t pending_rules;
4688 : :
4689 : 0 : ret = __flow_hw_push(dev, queue, error);
4690 [ # # ]: 0 : if (ret < 0)
4691 : : return ret;
4692 : 0 : pending_rules = ret;
4693 [ # # ]: 0 : while (pending_rules) {
4694 : 0 : ret = flow_hw_pull(dev, queue, comp, BURST_THR, error);
4695 [ # # ]: 0 : if (ret < 0)
4696 : : return -1;
4697 [ # # ]: 0 : if (!ret) {
4698 : 0 : rte_delay_us_sleep(MLX5_ASO_WQE_CQE_RESPONSE_DELAY);
4699 [ # # ]: 0 : if (++empty_loop > 5) {
4700 : 0 : DRV_LOG(WARNING, "No available dequeue %u, quit.", pending_rules);
4701 : 0 : break;
4702 : : }
4703 : 0 : continue;
4704 : : }
4705 [ # # ]: 0 : for (i = 0; i < ret; i++) {
4706 [ # # ]: 0 : if (comp[i].status == RTE_FLOW_OP_ERROR)
4707 : 0 : DRV_LOG(WARNING, "Flow flush get error CQE.");
4708 : : }
4709 : : /*
4710 : : * Indirect **SYNC** METER_MARK and CT actions do not
4711 : : * remove completion after WQE post.
4712 : : * That implementation avoids HW timeout.
4713 : : * The completion is removed before the following WQE post.
4714 : : * However, HWS queue updates do not reflect that behaviour.
4715 : : * Therefore, during port destruction sync queue may have
4716 : : * pending completions.
4717 : : */
4718 : 0 : pending_rules -= RTE_MIN(pending_rules, (uint32_t)ret);
4719 : : empty_loop = 0;
4720 : : }
4721 : : return 0;
4722 : : }
4723 : :
4724 : : /**
4725 : : * Flush created flows.
4726 : : *
4727 : : * @param[in] dev
4728 : : * Pointer to the rte_eth_dev structure.
4729 : : * @param[out] error
4730 : : * Pointer to error structure.
4731 : : *
4732 : : * @return
4733 : : * 0 on success, negative value otherwise and rte_errno is set.
4734 : : */
4735 : : int
4736 : 0 : flow_hw_q_flow_flush(struct rte_eth_dev *dev,
4737 : : struct rte_flow_error *error)
4738 : : {
4739 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4740 : 0 : struct mlx5_hw_q *hw_q = &priv->hw_q[MLX5_DEFAULT_FLUSH_QUEUE];
4741 : : struct rte_flow_template_table *tbl;
4742 : : struct rte_flow_hw *flow;
4743 : 0 : struct rte_flow_op_attr attr = {
4744 : : .postpone = 0,
4745 : : };
4746 : : uint32_t pending_rules = 0;
4747 : : uint32_t queue;
4748 : : uint32_t fidx;
4749 : :
4750 : : /*
4751 : : * Ensure to push and dequeue all the enqueued flow
4752 : : * creation/destruction jobs in case user forgot to
4753 : : * dequeue. Or the enqueued created flows will be
4754 : : * leaked. The forgotten dequeues would also cause
4755 : : * flow flush get extra CQEs as expected and pending_rules
4756 : : * be minus value.
4757 : : */
4758 [ # # ]: 0 : for (queue = 0; queue < priv->nb_queue; queue++) {
4759 [ # # ]: 0 : if (__flow_hw_pull_comp(dev, queue, error))
4760 : : return -1;
4761 : : }
4762 : : /* Flush flow per-table from MLX5_DEFAULT_FLUSH_QUEUE. */
4763 [ # # ]: 0 : LIST_FOREACH(tbl, &priv->flow_hw_tbl, next) {
4764 [ # # ]: 0 : if (!tbl->cfg.external)
4765 : 0 : continue;
4766 [ # # ]: 0 : MLX5_IPOOL_FOREACH(tbl->flow, fidx, flow) {
4767 [ # # ]: 0 : if (flow_hw_async_flow_destroy(dev,
4768 : : MLX5_DEFAULT_FLUSH_QUEUE,
4769 : : &attr,
4770 : : (struct rte_flow *)flow,
4771 : : NULL,
4772 : : error))
4773 : : return -1;
4774 : 0 : pending_rules++;
4775 : : /* Drain completion with queue size. */
4776 [ # # ]: 0 : if (pending_rules >= hw_q->size) {
4777 [ # # ]: 0 : if (__flow_hw_pull_comp(dev,
4778 : : MLX5_DEFAULT_FLUSH_QUEUE,
4779 : : error))
4780 : : return -1;
4781 : : pending_rules = 0;
4782 : : }
4783 : : }
4784 : : }
4785 : : /* Drain left completion. */
4786 [ # # # # ]: 0 : if (pending_rules &&
4787 : 0 : __flow_hw_pull_comp(dev, MLX5_DEFAULT_FLUSH_QUEUE, error))
4788 : 0 : return -1;
4789 : : return 0;
4790 : : }
4791 : :
4792 : : static int
4793 : 0 : mlx5_tbl_multi_pattern_process(struct rte_eth_dev *dev,
4794 : : struct rte_flow_template_table *tbl,
4795 : : struct mlx5_multi_pattern_segment *segment,
4796 : : uint32_t bulk_size,
4797 : : struct rte_flow_error *error)
4798 : : {
4799 : : int ret = 0;
4800 : : uint32_t i;
4801 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4802 : : bool unified_fdb = is_unified_fdb(priv);
4803 : : struct mlx5_tbl_multi_pattern_ctx *mpctx = &tbl->mpctx;
4804 : : const struct rte_flow_template_table_attr *table_attr = &tbl->cfg.attr;
4805 : 0 : const struct rte_flow_attr *attr = &table_attr->flow_attr;
4806 : : enum mlx5dr_table_type type =
4807 : 0 : get_mlx5dr_table_type(attr, table_attr->specialize, unified_fdb);
4808 : 0 : uint32_t flags = mlx5_hw_act_flag[!!attr->group][type];
4809 : : struct mlx5dr_action *dr_action = NULL;
4810 : :
4811 [ # # ]: 0 : for (i = 0; i < MLX5_MULTIPATTERN_ENCAP_NUM; i++) {
4812 [ # # ]: 0 : typeof(mpctx->reformat[0]) *reformat = mpctx->reformat + i;
4813 : : enum mlx5dr_action_type reformat_type =
4814 : : mlx5_multi_pattern_reformat_index_to_type(i);
4815 : :
4816 [ # # ]: 0 : if (!reformat->elements_num)
4817 : 0 : continue;
4818 : : dr_action = reformat_type == MLX5DR_ACTION_TYP_INSERT_HEADER ?
4819 : : mlx5dr_action_create_insert_header
4820 : : (priv->dr_ctx, reformat->elements_num,
4821 : : reformat->insert_hdr, bulk_size, flags) :
4822 : 0 : mlx5dr_action_create_reformat
4823 : : (priv->dr_ctx, reformat_type, reformat->elements_num,
4824 : 0 : reformat->reformat_hdr, bulk_size, flags);
4825 [ # # ]: 0 : if (!dr_action) {
4826 : 0 : ret = rte_flow_error_set(error, rte_errno,
4827 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4828 : : NULL,
4829 : : "failed to create multi-pattern encap action");
4830 : 0 : goto error;
4831 : : }
4832 : 0 : segment->reformat_action[i] = dr_action;
4833 : : }
4834 [ # # ]: 0 : if (mpctx->mh.elements_num) {
4835 : : typeof(mpctx->mh) *mh = &mpctx->mh;
4836 : 0 : dr_action = mlx5dr_action_create_modify_header
4837 : 0 : (priv->dr_ctx, mpctx->mh.elements_num, mh->pattern,
4838 : : bulk_size, flags);
4839 [ # # ]: 0 : if (!dr_action) {
4840 : 0 : ret = rte_flow_error_set(error, rte_errno,
4841 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4842 : : NULL, "failed to create multi-pattern header modify action");
4843 : 0 : goto error;
4844 : : }
4845 : 0 : segment->mhdr_action = dr_action;
4846 : : }
4847 [ # # ]: 0 : if (dr_action) {
4848 : 0 : segment->capacity = RTE_BIT32(bulk_size);
4849 [ # # ]: 0 : if (segment != &mpctx->segments[MLX5_MAX_TABLE_RESIZE_NUM - 1])
4850 : 0 : segment[1].head_index = segment->head_index + segment->capacity;
4851 : : }
4852 : : return 0;
4853 : 0 : error:
4854 : 0 : mlx5_destroy_multi_pattern_segment(segment);
4855 : 0 : return ret;
4856 : : }
4857 : :
4858 : : static int
4859 : 0 : mlx5_hw_build_template_table(struct rte_eth_dev *dev,
4860 : : uint8_t nb_action_templates,
4861 : : struct rte_flow_actions_template *action_templates[],
4862 : : struct mlx5dr_action_template *at[],
4863 : : struct rte_flow_template_table *tbl,
4864 : : struct rte_flow_error *error)
4865 : : {
4866 : : int ret;
4867 : : uint8_t i;
4868 : :
4869 [ # # ]: 0 : for (i = 0; i < nb_action_templates; i++) {
4870 : 0 : uint32_t refcnt = rte_atomic_fetch_add_explicit(&action_templates[i]->refcnt, 1,
4871 : : rte_memory_order_relaxed) + 1;
4872 : :
4873 [ # # ]: 0 : if (refcnt <= 1) {
4874 : 0 : rte_flow_error_set(error, EINVAL,
4875 : : RTE_FLOW_ERROR_TYPE_ACTION,
4876 : : &action_templates[i], "invalid AT refcount");
4877 : 0 : goto at_error;
4878 : : }
4879 : 0 : at[i] = action_templates[i]->tmpl;
4880 : 0 : tbl->ats[i].action_template = action_templates[i];
4881 : 0 : LIST_INIT(&tbl->ats[i].acts.act_list);
4882 : : /* do NOT translate table action if `dev` was not started */
4883 [ # # ]: 0 : if (!dev->data->dev_started)
4884 : 0 : continue;
4885 : 0 : ret = flow_hw_translate_actions_template(dev, &tbl->cfg,
4886 : : &tbl->ats[i].acts,
4887 : : action_templates[i],
4888 : : &tbl->mpctx, error);
4889 [ # # ]: 0 : if (ret) {
4890 : 0 : i++;
4891 : 0 : goto at_error;
4892 : : }
4893 : 0 : flow_hw_populate_rule_acts_caches(dev, tbl, i);
4894 : : }
4895 [ # # ]: 0 : tbl->nb_action_templates = nb_action_templates;
4896 [ # # ]: 0 : if (mlx5_is_multi_pattern_active(&tbl->mpctx)) {
4897 [ # # ]: 0 : ret = mlx5_tbl_multi_pattern_process(dev, tbl,
4898 : : &tbl->mpctx.segments[0],
4899 : : rte_log2_u32(tbl->cfg.attr.nb_flows),
4900 : : error);
4901 [ # # ]: 0 : if (ret)
4902 : 0 : goto at_error;
4903 : : }
4904 : : return 0;
4905 : :
4906 : : at_error:
4907 [ # # ]: 0 : while (i--) {
4908 : 0 : __flow_hw_action_template_destroy(dev, &tbl->ats[i].acts);
4909 : 0 : rte_atomic_fetch_sub_explicit(&action_templates[i]->refcnt,
4910 : : 1, rte_memory_order_relaxed);
4911 : : }
4912 : 0 : return rte_errno;
4913 : : }
4914 : :
4915 : : static bool
4916 : : flow_hw_validate_template_domain(const struct rte_flow_attr *table_attr,
4917 : : uint32_t ingress, uint32_t egress, uint32_t transfer)
4918 : : {
4919 : 0 : if (table_attr->ingress)
4920 : : return ingress != 0;
4921 [ # # # # ]: 0 : else if (table_attr->egress)
4922 : : return egress != 0;
4923 : : else
4924 : 0 : return transfer;
4925 : : }
4926 : :
4927 : : static bool
4928 : : flow_hw_validate_table_domain(const struct rte_flow_attr *table_attr)
4929 : : {
4930 : 0 : return table_attr->ingress + table_attr->egress + table_attr->transfer
4931 : : == 1;
4932 : : }
4933 : :
4934 : : /**
4935 : : * Create flow table.
4936 : : *
4937 : : * The input item and action templates will be binded to the table.
4938 : : * Flow memory will also be allocated. Matcher will be created based
4939 : : * on the item template. Action will be translated to the dedicated
4940 : : * DR action if possible.
4941 : : *
4942 : : * @param[in] dev
4943 : : * Pointer to the rte_eth_dev structure.
4944 : : * @param[in] table_cfg
4945 : : * Pointer to the table configuration.
4946 : : * @param[in] item_templates
4947 : : * Item template array to be binded to the table.
4948 : : * @param[in] nb_item_templates
4949 : : * Number of item template.
4950 : : * @param[in] action_templates
4951 : : * Action template array to be binded to the table.
4952 : : * @param[in] nb_action_templates
4953 : : * Number of action template.
4954 : : * @param[out] error
4955 : : * Pointer to error structure.
4956 : : *
4957 : : * @return
4958 : : * Table on success, NULL otherwise and rte_errno is set.
4959 : : */
4960 : : static struct rte_flow_template_table *
4961 : 0 : flow_hw_table_create(struct rte_eth_dev *dev,
4962 : : const struct mlx5_flow_template_table_cfg *table_cfg,
4963 : : struct rte_flow_pattern_template *item_templates[],
4964 : : uint8_t nb_item_templates,
4965 : : struct rte_flow_actions_template *action_templates[],
4966 : : uint8_t nb_action_templates,
4967 : : struct rte_flow_error *error)
4968 : : {
4969 : 0 : struct rte_flow_error sub_error = {
4970 : : .type = RTE_FLOW_ERROR_TYPE_NONE,
4971 : : .cause = NULL,
4972 : : .message = NULL,
4973 : : };
4974 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
4975 : : bool unified_fdb = is_unified_fdb(priv);
4976 : 0 : struct mlx5dr_matcher_attr matcher_attr = {0};
4977 : 0 : struct mlx5dr_action_jump_to_matcher_attr jump_attr = {
4978 : : .type = MLX5DR_ACTION_JUMP_TO_MATCHER_BY_INDEX,
4979 : : .matcher = NULL,
4980 : : };
4981 : : struct rte_flow_template_table *tbl = NULL;
4982 : : struct mlx5_flow_group *grp;
4983 : : struct mlx5dr_match_template *mt[MLX5_HW_TBL_MAX_ITEM_TEMPLATE];
4984 : : struct mlx5dr_action_template *at[MLX5_HW_TBL_MAX_ACTION_TEMPLATE];
4985 : 0 : const struct rte_flow_template_table_attr *attr = &table_cfg->attr;
4986 : 0 : struct rte_flow_attr flow_attr = attr->flow_attr;
4987 : 0 : uint32_t specialize = table_cfg->attr.specialize;
4988 : 0 : struct mlx5_flow_cb_ctx ctx = {
4989 : : .dev = dev,
4990 : : .error = &sub_error,
4991 : : .data = &flow_attr,
4992 : : .data2 = &specialize,
4993 : : };
4994 : 0 : struct mlx5_indexed_pool_config cfg = {
4995 : : .trunk_size = 1 << 12,
4996 : : .per_core_cache = 1 << 13,
4997 : : .need_lock = 1,
4998 : 0 : .release_mem_en = !!priv->sh->config.reclaim_mode,
4999 : : .malloc = mlx5_malloc,
5000 : : .free = mlx5_free,
5001 : : .type = "mlx5_hw_table_flow",
5002 : : };
5003 : : struct mlx5_list_entry *ge;
5004 : : uint32_t i = 0, max_tpl = MLX5_HW_TBL_MAX_ITEM_TEMPLATE;
5005 [ # # ]: 0 : uint32_t nb_flows = rte_align32pow2(attr->nb_flows);
5006 : 0 : bool port_started = !!dev->data->dev_started;
5007 : : bool rpool_needed;
5008 : : size_t tbl_mem_size;
5009 : : enum mlx5dr_table_type table_type;
5010 : : int err;
5011 : :
5012 [ # # ]: 0 : if (!flow_hw_validate_table_domain(&attr->flow_attr)) {
5013 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ATTR,
5014 : : NULL, "invalid table domain attributes");
5015 : 0 : return NULL;
5016 : : }
5017 [ # # ]: 0 : for (i = 0; i < nb_item_templates; i++) {
5018 : : const struct rte_flow_pattern_template_attr *pt_attr =
5019 : 0 : &item_templates[i]->attr;
5020 : : bool match = flow_hw_validate_template_domain(&attr->flow_attr,
5021 : 0 : pt_attr->ingress,
5022 : 0 : pt_attr->egress,
5023 [ # # ]: 0 : pt_attr->transfer);
5024 [ # # ]: 0 : if (!match) {
5025 : 0 : rte_flow_error_set(error, EINVAL,
5026 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5027 : : NULL, "pattern template domain does not match table");
5028 : 0 : return NULL;
5029 : : }
5030 [ # # # # ]: 0 : if (item_templates[i]->item_flags & MLX5_FLOW_LAYER_ECPRI &&
5031 : 0 : !mlx5_flex_parser_ecpri_exist(dev))
5032 [ # # ]: 0 : if (mlx5_flex_parser_ecpri_alloc(dev)) {
5033 : 0 : rte_flow_error_set(error, EIO,
5034 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5035 : : NULL,
5036 : : "failed to create Flex parser "
5037 : : "profile for ECPRI");
5038 : 0 : goto error;
5039 : : }
5040 : : }
5041 [ # # ]: 0 : for (i = 0; i < nb_action_templates; i++) {
5042 : 0 : const struct rte_flow_actions_template *at = action_templates[i];
5043 : : bool match = flow_hw_validate_template_domain(&attr->flow_attr,
5044 : 0 : at->attr.ingress,
5045 : 0 : at->attr.egress,
5046 [ # # ]: 0 : at->attr.transfer);
5047 [ # # ]: 0 : if (!match) {
5048 : 0 : rte_flow_error_set(error, EINVAL,
5049 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5050 : : NULL, "action template domain does not match table");
5051 : 0 : return NULL;
5052 : : }
5053 : : }
5054 : : /* HWS layer accepts only 1 item template with root table. */
5055 [ # # ]: 0 : if (!attr->flow_attr.group)
5056 : : max_tpl = 1;
5057 : 0 : cfg.max_idx = nb_flows;
5058 [ # # ]: 0 : cfg.size = !rte_flow_template_table_resizable(dev->data->port_id, attr) ?
5059 : : mlx5_flow_hw_entry_size() :
5060 : : mlx5_flow_hw_auxed_entry_size();
5061 : : /* For table has very limited flows, disable cache. */
5062 [ # # ]: 0 : if (nb_flows < cfg.trunk_size) {
5063 : 0 : cfg.per_core_cache = 0;
5064 : 0 : cfg.trunk_size = nb_flows;
5065 [ # # ]: 0 : } else if (nb_flows <= MLX5_HW_IPOOL_SIZE_THRESHOLD) {
5066 : 0 : cfg.per_core_cache = MLX5_HW_IPOOL_CACHE_MIN;
5067 : : }
5068 : : /* Check if we requires too many templates. */
5069 [ # # # # ]: 0 : if (nb_item_templates > max_tpl ||
5070 : : nb_action_templates > MLX5_HW_TBL_MAX_ACTION_TEMPLATE) {
5071 : 0 : rte_errno = EINVAL;
5072 : 0 : goto error;
5073 : : }
5074 : : /*
5075 : : * Amount of memory required for rte_flow_template_table struct:
5076 : : * - Size of the struct itself.
5077 : : * - VLA of DR rule action containers at the end =
5078 : : * number of actions templates * number of queues * size of DR rule actions container.
5079 : : */
5080 : : tbl_mem_size = sizeof(*tbl);
5081 : 0 : tbl_mem_size += nb_action_templates * priv->nb_queue * sizeof(tbl->rule_acts[0]);
5082 : : /* Allocate the table memory. */
5083 : 0 : tbl = mlx5_malloc(MLX5_MEM_ZERO, tbl_mem_size, RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
5084 [ # # ]: 0 : if (!tbl)
5085 : 0 : goto error;
5086 : 0 : tbl->cfg = *table_cfg;
5087 : : /* Allocate flow indexed pool. */
5088 : 0 : tbl->flow = mlx5_ipool_create(&cfg);
5089 [ # # ]: 0 : if (!tbl->flow)
5090 : 0 : goto error;
5091 : : /* Allocate table of auxiliary flow rule structs. */
5092 : 0 : tbl->flow_aux = mlx5_malloc(MLX5_MEM_ZERO, sizeof(struct rte_flow_hw_aux) * nb_flows,
5093 : : RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
5094 [ # # ]: 0 : if (!tbl->flow_aux)
5095 : 0 : goto error;
5096 : : /* Register the flow group. */
5097 : 0 : ge = mlx5_hlist_register(priv->sh->groups, attr->flow_attr.group, &ctx);
5098 [ # # ]: 0 : if (!ge)
5099 : 0 : goto error;
5100 : : grp = container_of(ge, struct mlx5_flow_group, entry);
5101 : : /* Verify unified fdb sub domains consistency */
5102 : 0 : table_type = get_mlx5dr_table_type(&flow_attr, specialize, unified_fdb);
5103 [ # # ]: 0 : if (table_type != grp->type) {
5104 : 0 : DRV_LOG(ERR, "Table type (%u) does not match group id (%u) type (%u)",
5105 : : table_type, grp->group_id, grp->type);
5106 : 0 : rte_errno = EINVAL;
5107 : 0 : goto error;
5108 : : }
5109 : 0 : tbl->grp = grp;
5110 : : /* Prepare matcher information. */
5111 : 0 : matcher_attr.resizable = !!rte_flow_template_table_resizable
5112 : 0 : (dev->data->port_id, &table_cfg->attr);
5113 : 0 : matcher_attr.optimize_flow_src = MLX5DR_MATCHER_FLOW_SRC_ANY;
5114 : 0 : matcher_attr.priority = attr->flow_attr.priority;
5115 : 0 : matcher_attr.optimize_using_rule_idx = true;
5116 : 0 : matcher_attr.mode = MLX5DR_MATCHER_RESOURCE_MODE_RULE;
5117 [ # # ]: 0 : matcher_attr.insert_mode = flow_hw_matcher_insert_mode_get(attr->insertion_type);
5118 [ # # ]: 0 : if (matcher_attr.insert_mode == MLX5DR_MATCHER_INSERT_BY_INDEX) {
5119 [ # # ]: 0 : if (attr->insertion_type == RTE_FLOW_TABLE_INSERTION_TYPE_INDEX_WITH_PATTERN) {
5120 : 0 : matcher_attr.isolated = true;
5121 : 0 : matcher_attr.match_mode = MLX5DR_MATCHER_MATCH_MODE_DEFAULT;
5122 : : } else {
5123 : 0 : matcher_attr.isolated = false;
5124 : 0 : matcher_attr.match_mode = MLX5DR_MATCHER_MATCH_MODE_ALWAYS_HIT;
5125 : : }
5126 : : }
5127 [ # # ]: 0 : if (attr->hash_func == RTE_FLOW_TABLE_HASH_FUNC_CRC16) {
5128 : 0 : DRV_LOG(ERR, "16-bit checksum hash type is not supported");
5129 : 0 : rte_errno = ENOTSUP;
5130 : 0 : goto it_error;
5131 : : }
5132 [ # # ]: 0 : matcher_attr.distribute_mode = flow_hw_matcher_distribute_mode_get(attr->hash_func);
5133 : 0 : matcher_attr.rule.num_log = rte_log2_u32(nb_flows);
5134 : : /* Parse hints information. */
5135 [ # # ]: 0 : if (attr->specialize) {
5136 : : uint32_t val = RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_WIRE_ORIG |
5137 : : RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_VPORT_ORIG;
5138 : :
5139 [ # # ]: 0 : if ((attr->specialize & val) == val) {
5140 : 0 : DRV_LOG(ERR, "Invalid hint value %x",
5141 : : attr->specialize);
5142 : 0 : rte_errno = EINVAL;
5143 : 0 : goto it_error;
5144 : : }
5145 [ # # ]: 0 : if (attr->specialize &
5146 : : RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_WIRE_ORIG) {
5147 : 0 : matcher_attr.optimize_flow_src =
5148 : : MLX5DR_MATCHER_FLOW_SRC_WIRE;
5149 [ # # ]: 0 : } else if (attr->specialize &
5150 : : RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_VPORT_ORIG) {
5151 : 0 : matcher_attr.optimize_flow_src =
5152 : : MLX5DR_MATCHER_FLOW_SRC_VPORT;
5153 : : }
5154 : : }
5155 : : /* Build the item template. */
5156 [ # # ]: 0 : for (i = 0; i < nb_item_templates; i++) {
5157 : : uint32_t ret;
5158 : :
5159 [ # # # # ]: 0 : if ((flow_attr.ingress && !item_templates[i]->attr.ingress) ||
5160 [ # # # # ]: 0 : (flow_attr.egress && !item_templates[i]->attr.egress) ||
5161 [ # # # # ]: 0 : (flow_attr.transfer && !item_templates[i]->attr.transfer)) {
5162 : 0 : DRV_LOG(ERR, "pattern template and template table attribute mismatch");
5163 : 0 : rte_errno = EINVAL;
5164 : 0 : goto it_error;
5165 : : }
5166 [ # # ]: 0 : if (item_templates[i]->item_flags & MLX5_FLOW_ITEM_COMPARE)
5167 : 0 : matcher_attr.mode = MLX5DR_MATCHER_RESOURCE_MODE_HTABLE;
5168 : 0 : ret = rte_atomic_fetch_add_explicit(&item_templates[i]->refcnt, 1,
5169 : : rte_memory_order_relaxed) + 1;
5170 [ # # ]: 0 : if (ret <= 1) {
5171 : 0 : rte_errno = EINVAL;
5172 : 0 : goto it_error;
5173 : : }
5174 : 0 : mt[i] = item_templates[i]->mt;
5175 : 0 : tbl->its[i] = item_templates[i];
5176 : : }
5177 : 0 : tbl->nb_item_templates = nb_item_templates;
5178 : : /* Build the action template. */
5179 : 0 : err = mlx5_hw_build_template_table(dev, nb_action_templates,
5180 : : action_templates, at, tbl, &sub_error);
5181 [ # # ]: 0 : if (err) {
5182 : : i = nb_item_templates;
5183 : 0 : goto it_error;
5184 : : }
5185 : 0 : tbl->matcher_info[0].matcher = mlx5dr_matcher_create
5186 : 0 : (tbl->grp->tbl, mt, nb_item_templates, at, nb_action_templates, &matcher_attr);
5187 [ # # ]: 0 : if (!tbl->matcher_info[0].matcher)
5188 : 0 : goto at_error;
5189 : 0 : tbl->matcher_attr = matcher_attr;
5190 : 0 : tbl->type = table_type;
5191 [ # # ]: 0 : if (matcher_attr.isolated) {
5192 : 0 : jump_attr.matcher = tbl->matcher_info[0].matcher;
5193 : 0 : tbl->matcher_info[0].jump = mlx5dr_action_create_jump_to_matcher(priv->dr_ctx,
5194 : 0 : &jump_attr, mlx5_hw_act_flag[!!attr->flow_attr.group][tbl->type]);
5195 [ # # ]: 0 : if (!tbl->matcher_info[0].jump)
5196 : 0 : goto jtm_error;
5197 : : }
5198 : : /*
5199 : : * Only the matcher supports update and needs more than 1 WQE, an additional
5200 : : * index is needed. Or else the flow index can be reused.
5201 : : */
5202 [ # # # # ]: 0 : rpool_needed = mlx5dr_matcher_is_updatable(tbl->matcher_info[0].matcher) &&
5203 : 0 : mlx5dr_matcher_is_dependent(tbl->matcher_info[0].matcher);
5204 [ # # ]: 0 : if (rpool_needed) {
5205 : : /* Allocate rule indexed pool. */
5206 : 0 : cfg.size = 0;
5207 : 0 : cfg.type = "mlx5_hw_table_rule";
5208 : 0 : cfg.max_idx += priv->hw_q[0].size;
5209 : 0 : tbl->resource = mlx5_ipool_create(&cfg);
5210 [ # # ]: 0 : if (!tbl->resource)
5211 : 0 : goto res_error;
5212 : : }
5213 [ # # ]: 0 : if (port_started)
5214 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->flow_hw_tbl, tbl, next);
5215 : : else
5216 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->flow_hw_tbl_ongo, tbl, next);
5217 : : rte_rwlock_init(&tbl->matcher_replace_rwlk);
5218 : 0 : return tbl;
5219 : : res_error:
5220 [ # # ]: 0 : if (tbl->matcher_info[0].jump)
5221 : 0 : mlx5dr_action_destroy(tbl->matcher_info[0].jump);
5222 : 0 : jtm_error:
5223 [ # # ]: 0 : if (tbl->matcher_info[0].matcher)
5224 : 0 : (void)mlx5dr_matcher_destroy(tbl->matcher_info[0].matcher);
5225 : 0 : at_error:
5226 [ # # ]: 0 : for (i = 0; i < nb_action_templates; i++) {
5227 : 0 : __flow_hw_action_template_destroy(dev, &tbl->ats[i].acts);
5228 : 0 : rte_atomic_fetch_sub_explicit(&action_templates[i]->refcnt,
5229 : : 1, rte_memory_order_relaxed);
5230 : : }
5231 : : i = nb_item_templates;
5232 : : it_error:
5233 [ # # ]: 0 : while (i--)
5234 : 0 : rte_atomic_fetch_sub_explicit(&item_templates[i]->refcnt,
5235 : : 1, rte_memory_order_relaxed);
5236 : 0 : error:
5237 : 0 : err = rte_errno;
5238 [ # # ]: 0 : if (tbl) {
5239 [ # # ]: 0 : if (tbl->grp)
5240 : 0 : mlx5_hlist_unregister(priv->sh->groups,
5241 : : &tbl->grp->entry);
5242 [ # # ]: 0 : if (tbl->flow_aux)
5243 : 0 : mlx5_free(tbl->flow_aux);
5244 [ # # ]: 0 : if (tbl->flow)
5245 : 0 : mlx5_ipool_destroy(tbl->flow);
5246 : 0 : mlx5_free(tbl);
5247 : : }
5248 [ # # ]: 0 : if (error != NULL) {
5249 [ # # ]: 0 : if (sub_error.type == RTE_FLOW_ERROR_TYPE_NONE)
5250 : 0 : rte_flow_error_set(error, err, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5251 : : "Failed to create template table");
5252 : : else
5253 : : rte_memcpy(error, &sub_error, sizeof(sub_error));
5254 : : }
5255 : : return NULL;
5256 : : }
5257 : :
5258 : : /**
5259 : : * Update flow template table.
5260 : : *
5261 : : * @param[in] dev
5262 : : * Pointer to the rte_eth_dev structure.
5263 : : * @param[out] error
5264 : : * Pointer to error structure.
5265 : : *
5266 : : * @return
5267 : : * 0 on success, negative value otherwise and rte_errno is set.
5268 : : */
5269 : : int
5270 : 0 : flow_hw_table_update(struct rte_eth_dev *dev,
5271 : : struct rte_flow_error *error)
5272 : : {
5273 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
5274 : : struct rte_flow_template_table *tbl;
5275 : :
5276 [ # # ]: 0 : while ((tbl = LIST_FIRST(&priv->flow_hw_tbl_ongo)) != NULL) {
5277 [ # # ]: 0 : if (flow_hw_translate_all_actions_templates(dev, tbl, error))
5278 : : return -1;
5279 [ # # ]: 0 : LIST_REMOVE(tbl, next);
5280 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->flow_hw_tbl, tbl, next);
5281 : : }
5282 : : return 0;
5283 : : }
5284 : :
5285 : : static inline int
5286 : 0 : __translate_group(struct rte_eth_dev *dev,
5287 : : const struct rte_flow_attr *flow_attr,
5288 : : bool external,
5289 : : uint32_t group,
5290 : : uint32_t *table_group,
5291 : : struct rte_flow_error *error)
5292 : : {
5293 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
5294 : 0 : struct mlx5_sh_config *config = &priv->sh->config;
5295 : :
5296 [ # # ]: 0 : if (config->dv_esw_en &&
5297 [ # # # # ]: 0 : priv->fdb_def_rule &&
5298 [ # # ]: 0 : external &&
5299 : : flow_attr->transfer) {
5300 [ # # ]: 0 : if (group > MLX5_HW_MAX_TRANSFER_GROUP)
5301 : 0 : return rte_flow_error_set(error, EINVAL,
5302 : : RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5303 : : NULL,
5304 : : "group index not supported");
5305 : 0 : *table_group = group + 1;
5306 [ # # ]: 0 : } else if (config->dv_esw_en &&
5307 [ # # # # : 0 : (config->repr_matching || config->dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS) &&
# # ]
5308 [ # # ]: 0 : external &&
5309 : : flow_attr->egress) {
5310 : : /*
5311 : : * On E-Switch setups, default egress flow rules are inserted to allow
5312 : : * representor matching and/or preserving metadata across steering domains.
5313 : : * These flow rules are inserted in group 0 and this group is reserved by PMD
5314 : : * for these purposes.
5315 : : *
5316 : : * As a result, if representor matching or extended metadata mode is enabled,
5317 : : * group provided by the user must be incremented to avoid inserting flow rules
5318 : : * in group 0.
5319 : : */
5320 [ # # ]: 0 : if (group > MLX5_HW_MAX_EGRESS_GROUP)
5321 : 0 : return rte_flow_error_set(error, EINVAL,
5322 : : RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5323 : : NULL,
5324 : : "group index not supported");
5325 : 0 : *table_group = group + 1;
5326 : : } else {
5327 : 0 : *table_group = group;
5328 : : }
5329 : : return 0;
5330 : : }
5331 : :
5332 : : /**
5333 : : * Translates group index specified by the user in @p attr to internal
5334 : : * group index.
5335 : : *
5336 : : * Translation is done by incrementing group index, so group n becomes n + 1.
5337 : : *
5338 : : * @param[in] dev
5339 : : * Pointer to Ethernet device.
5340 : : * @param[in] cfg
5341 : : * Pointer to the template table configuration.
5342 : : * @param[in] group
5343 : : * Currently used group index (table group or jump destination).
5344 : : * @param[out] table_group
5345 : : * Pointer to output group index.
5346 : : * @param[out] error
5347 : : * Pointer to error structure.
5348 : : *
5349 : : * @return
5350 : : * 0 on success. Otherwise, returns negative error code, rte_errno is set
5351 : : * and error structure is filled.
5352 : : */
5353 : : static int
5354 : : flow_hw_translate_group(struct rte_eth_dev *dev,
5355 : : const struct mlx5_flow_template_table_cfg *cfg,
5356 : : uint32_t group,
5357 : : uint32_t *table_group,
5358 : : struct rte_flow_error *error)
5359 : : {
5360 : 0 : const struct rte_flow_attr *flow_attr = &cfg->attr.flow_attr;
5361 : :
5362 : 0 : return __translate_group(dev, flow_attr, cfg->external, group, table_group, error);
5363 : : }
5364 : :
5365 : : /**
5366 : : * Create flow table.
5367 : : *
5368 : : * This function is a wrapper over @ref flow_hw_table_create(), which translates parameters
5369 : : * provided by user to proper internal values.
5370 : : *
5371 : : * @param[in] dev
5372 : : * Pointer to Ethernet device.
5373 : : * @param[in] attr
5374 : : * Pointer to the table attributes.
5375 : : * @param[in] item_templates
5376 : : * Item template array to be binded to the table.
5377 : : * @param[in] nb_item_templates
5378 : : * Number of item templates.
5379 : : * @param[in] action_templates
5380 : : * Action template array to be binded to the table.
5381 : : * @param[in] nb_action_templates
5382 : : * Number of action templates.
5383 : : * @param[out] error
5384 : : * Pointer to error structure.
5385 : : *
5386 : : * @return
5387 : : * Table on success, Otherwise, returns negative error code, rte_errno is set
5388 : : * and error structure is filled.
5389 : : */
5390 : : static struct rte_flow_template_table *
5391 : 0 : flow_hw_template_table_create(struct rte_eth_dev *dev,
5392 : : const struct rte_flow_template_table_attr *attr,
5393 : : struct rte_flow_pattern_template *item_templates[],
5394 : : uint8_t nb_item_templates,
5395 : : struct rte_flow_actions_template *action_templates[],
5396 : : uint8_t nb_action_templates,
5397 : : struct rte_flow_error *error)
5398 : : {
5399 : 0 : struct mlx5_flow_template_table_cfg cfg = {
5400 : : .attr = *attr,
5401 : : .external = true,
5402 : : };
5403 : 0 : uint32_t group = attr->flow_attr.group;
5404 : :
5405 [ # # ]: 0 : if (flow_hw_translate_group(dev, &cfg, group, &cfg.attr.flow_attr.group, error))
5406 : : return NULL;
5407 [ # # # # ]: 0 : if (!cfg.attr.flow_attr.group &&
5408 : 0 : rte_flow_template_table_resizable(dev->data->port_id, attr)) {
5409 : 0 : rte_flow_error_set(error, EINVAL,
5410 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5411 : : "table cannot be resized: invalid group");
5412 : 0 : return NULL;
5413 : : }
5414 : 0 : return flow_hw_table_create(dev, &cfg, item_templates, nb_item_templates,
5415 : : action_templates, nb_action_templates, error);
5416 : : }
5417 : :
5418 : : static void
5419 : 0 : mlx5_destroy_multi_pattern_segment(struct mlx5_multi_pattern_segment *segment)
5420 : : {
5421 : : int i;
5422 : :
5423 [ # # ]: 0 : if (segment->mhdr_action)
5424 : 0 : mlx5dr_action_destroy(segment->mhdr_action);
5425 [ # # ]: 0 : for (i = 0; i < MLX5_MULTIPATTERN_ENCAP_NUM; i++) {
5426 [ # # ]: 0 : if (segment->reformat_action[i])
5427 : 0 : mlx5dr_action_destroy(segment->reformat_action[i]);
5428 : : }
5429 : 0 : segment->capacity = 0;
5430 : 0 : }
5431 : :
5432 : : static void
5433 : : flow_hw_destroy_table_multi_pattern_ctx(struct rte_flow_template_table *table)
5434 : : {
5435 : : int sx;
5436 : :
5437 [ # # ]: 0 : for (sx = 0; sx < MLX5_MAX_TABLE_RESIZE_NUM; sx++)
5438 : 0 : mlx5_destroy_multi_pattern_segment(table->mpctx.segments + sx);
5439 : : }
5440 : : /**
5441 : : * Destroy flow table.
5442 : : *
5443 : : * @param[in] dev
5444 : : * Pointer to the rte_eth_dev structure.
5445 : : * @param[in] table
5446 : : * Pointer to the table to be destroyed.
5447 : : * @param[out] error
5448 : : * Pointer to error structure.
5449 : : *
5450 : : * @return
5451 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
5452 : : */
5453 : : static int
5454 : 0 : flow_hw_table_destroy(struct rte_eth_dev *dev,
5455 : : struct rte_flow_template_table *table,
5456 : : struct rte_flow_error *error)
5457 : : {
5458 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
5459 : : int i;
5460 : 0 : uint32_t fidx = 1;
5461 : 0 : uint32_t ridx = 1;
5462 : :
5463 : : /* Build ipool allocated object bitmap. */
5464 [ # # ]: 0 : if (table->resource)
5465 : 0 : mlx5_ipool_flush_cache(table->resource);
5466 : 0 : mlx5_ipool_flush_cache(table->flow);
5467 : : /* Check if ipool has allocated objects. */
5468 [ # # # # ]: 0 : if (table->refcnt ||
5469 : 0 : mlx5_ipool_get_next(table->flow, &fidx) ||
5470 [ # # # # ]: 0 : (table->resource && mlx5_ipool_get_next(table->resource, &ridx))) {
5471 : 0 : DRV_LOG(WARNING, "Table %p is still in use.", (void *)table);
5472 : 0 : return rte_flow_error_set(error, EBUSY,
5473 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5474 : : NULL,
5475 : : "table is in use");
5476 : : }
5477 [ # # ]: 0 : LIST_REMOVE(table, next);
5478 [ # # ]: 0 : for (i = 0; i < table->nb_item_templates; i++)
5479 : 0 : rte_atomic_fetch_sub_explicit(&table->its[i]->refcnt,
5480 : : 1, rte_memory_order_relaxed);
5481 [ # # ]: 0 : for (i = 0; i < table->nb_action_templates; i++) {
5482 : 0 : __flow_hw_action_template_destroy(dev, &table->ats[i].acts);
5483 : 0 : rte_atomic_fetch_sub_explicit(&table->ats[i].action_template->refcnt,
5484 : : 1, rte_memory_order_relaxed);
5485 : : }
5486 : : flow_hw_destroy_table_multi_pattern_ctx(table);
5487 [ # # ]: 0 : if (table->matcher_info[0].jump)
5488 : 0 : mlx5dr_action_destroy(table->matcher_info[0].jump);
5489 [ # # ]: 0 : if (table->matcher_info[0].matcher)
5490 : 0 : mlx5dr_matcher_destroy(table->matcher_info[0].matcher);
5491 [ # # ]: 0 : if (table->matcher_info[1].jump)
5492 : 0 : mlx5dr_action_destroy(table->matcher_info[1].jump);
5493 [ # # ]: 0 : if (table->matcher_info[1].matcher)
5494 : 0 : mlx5dr_matcher_destroy(table->matcher_info[1].matcher);
5495 : 0 : mlx5_hlist_unregister(priv->sh->groups, &table->grp->entry);
5496 [ # # ]: 0 : if (table->resource)
5497 : 0 : mlx5_ipool_destroy(table->resource);
5498 : 0 : mlx5_free(table->flow_aux);
5499 : 0 : mlx5_ipool_destroy(table->flow);
5500 : 0 : mlx5_free(table);
5501 : 0 : return 0;
5502 : : }
5503 : :
5504 : : /**
5505 : : * Parse group's miss actions.
5506 : : *
5507 : : * @param[in] dev
5508 : : * Pointer to the rte_eth_dev structure.
5509 : : * @param[in] cfg
5510 : : * Pointer to the table_cfg structure.
5511 : : * @param[in] actions
5512 : : * Array of actions to perform on group miss. Supported types:
5513 : : * RTE_FLOW_ACTION_TYPE_JUMP, RTE_FLOW_ACTION_TYPE_VOID, RTE_FLOW_ACTION_TYPE_END.
5514 : : * @param[out] dst_group_id
5515 : : * Pointer to destination group id output. will be set to 0 if actions is END,
5516 : : * otherwise will be set to destination group id.
5517 : : * @param[out] error
5518 : : * Pointer to error structure.
5519 : : *
5520 : : * @return
5521 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
5522 : : */
5523 : :
5524 : : static int
5525 : 0 : flow_hw_group_parse_miss_actions(struct rte_eth_dev *dev,
5526 : : struct mlx5_flow_template_table_cfg *cfg,
5527 : : const struct rte_flow_action actions[],
5528 : : uint32_t *dst_group_id,
5529 : : struct rte_flow_error *error)
5530 : : {
5531 : : const struct rte_flow_action_jump *jump_conf;
5532 : 0 : uint32_t temp = 0;
5533 : : uint32_t i;
5534 : :
5535 [ # # ]: 0 : for (i = 0; actions[i].type != RTE_FLOW_ACTION_TYPE_END; i++) {
5536 [ # # # ]: 0 : switch (actions[i].type) {
5537 : 0 : case RTE_FLOW_ACTION_TYPE_VOID:
5538 : 0 : continue;
5539 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP:
5540 [ # # ]: 0 : if (temp)
5541 : 0 : return rte_flow_error_set(error, ENOTSUP,
5542 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, actions,
5543 : : "Miss actions can contain only a single JUMP");
5544 : :
5545 : 0 : jump_conf = (const struct rte_flow_action_jump *)actions[i].conf;
5546 [ # # ]: 0 : if (!jump_conf)
5547 : 0 : return rte_flow_error_set(error, EINVAL,
5548 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5549 : : jump_conf, "Jump conf must not be NULL");
5550 : :
5551 [ # # ]: 0 : if (flow_hw_translate_group(dev, cfg, jump_conf->group, &temp, error))
5552 : 0 : return -rte_errno;
5553 : :
5554 [ # # ]: 0 : if (!temp)
5555 : 0 : return rte_flow_error_set(error, EINVAL,
5556 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5557 : : "Failed to set group miss actions - Invalid target group");
5558 : : break;
5559 : 0 : default:
5560 : 0 : return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
5561 : : &actions[i], "Unsupported default miss action type");
5562 : : }
5563 : : }
5564 : :
5565 : 0 : *dst_group_id = temp;
5566 : 0 : return 0;
5567 : : }
5568 : :
5569 : : /**
5570 : : * Set group's miss group.
5571 : : *
5572 : : * @param[in] dev
5573 : : * Pointer to the rte_eth_dev structure.
5574 : : * @param[in] cfg
5575 : : * Pointer to the table_cfg structure.
5576 : : * @param[in] src_grp
5577 : : * Pointer to source group structure.
5578 : : * if NULL, a new group will be created based on group id from cfg->attr.flow_attr.group.
5579 : : * @param[in] dst_grp
5580 : : * Pointer to destination group structure.
5581 : : * @param[out] error
5582 : : * Pointer to error structure.
5583 : : *
5584 : : * @return
5585 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
5586 : : */
5587 : :
5588 : : static int
5589 : 0 : flow_hw_group_set_miss_group(struct rte_eth_dev *dev,
5590 : : struct mlx5_flow_template_table_cfg *cfg,
5591 : : struct mlx5_flow_group *src_grp,
5592 : : struct mlx5_flow_group *dst_grp,
5593 : : struct rte_flow_error *error)
5594 : : {
5595 : 0 : struct rte_flow_error sub_error = {
5596 : : .type = RTE_FLOW_ERROR_TYPE_NONE,
5597 : : .cause = NULL,
5598 : : .message = NULL,
5599 : : };
5600 : 0 : struct mlx5_flow_cb_ctx ctx = {
5601 : : .dev = dev,
5602 : : .error = &sub_error,
5603 : 0 : .data = &cfg->attr.flow_attr,
5604 : 0 : .data2 = &cfg->attr.specialize,
5605 : : };
5606 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
5607 : : struct mlx5_list_entry *ge;
5608 : : bool ref = false;
5609 : : int ret;
5610 : :
5611 [ # # ]: 0 : if (!dst_grp)
5612 : : return -EINVAL;
5613 : :
5614 : : /* If group doesn't exist - needs to be created. */
5615 [ # # ]: 0 : if (!src_grp) {
5616 : 0 : ge = mlx5_hlist_register(priv->sh->groups, cfg->attr.flow_attr.group, &ctx);
5617 [ # # ]: 0 : if (!ge)
5618 : 0 : return -rte_errno;
5619 : :
5620 : : src_grp = container_of(ge, struct mlx5_flow_group, entry);
5621 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->flow_hw_grp, src_grp, next);
5622 : : ref = true;
5623 [ # # ]: 0 : } else if (!src_grp->miss_group) {
5624 : : /* If group exists, but has no miss actions - need to increase ref_cnt. */
5625 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->flow_hw_grp, src_grp, next);
5626 : 0 : src_grp->entry.ref_cnt++;
5627 : : ref = true;
5628 : : }
5629 : :
5630 : 0 : ret = mlx5dr_table_set_default_miss(src_grp->tbl, dst_grp->tbl);
5631 [ # # ]: 0 : if (ret)
5632 : 0 : goto mlx5dr_error;
5633 : :
5634 : : /* If group existed and had old miss actions - ref_cnt is already correct.
5635 : : * However, need to reduce ref counter for old miss group.
5636 : : */
5637 [ # # ]: 0 : if (src_grp->miss_group)
5638 : 0 : mlx5_hlist_unregister(priv->sh->groups, &src_grp->miss_group->entry);
5639 : :
5640 : 0 : src_grp->miss_group = dst_grp;
5641 : 0 : return 0;
5642 : :
5643 : : mlx5dr_error:
5644 : : /* Reduce src_grp ref_cnt back & remove from grp list in case of mlx5dr error */
5645 [ # # ]: 0 : if (ref) {
5646 : 0 : mlx5_hlist_unregister(priv->sh->groups, &src_grp->entry);
5647 [ # # ]: 0 : LIST_REMOVE(src_grp, next);
5648 : : }
5649 : :
5650 : 0 : return rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5651 : : "Failed to set group miss actions");
5652 : : }
5653 : :
5654 : : /**
5655 : : * Unset group's miss group.
5656 : : *
5657 : : * @param[in] dev
5658 : : * Pointer to the rte_eth_dev structure.
5659 : : * @param[in] grp
5660 : : * Pointer to group structure.
5661 : : * @param[out] error
5662 : : * Pointer to error structure.
5663 : : *
5664 : : * @return
5665 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
5666 : : */
5667 : :
5668 : : static int
5669 : 0 : flow_hw_group_unset_miss_group(struct rte_eth_dev *dev,
5670 : : struct mlx5_flow_group *grp,
5671 : : struct rte_flow_error *error)
5672 : : {
5673 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
5674 : : int ret;
5675 : :
5676 : : /* If group doesn't exist - no need to change anything. */
5677 [ # # ]: 0 : if (!grp)
5678 : : return 0;
5679 : :
5680 : : /* If group exists, but miss actions is already default behavior -
5681 : : * no need to change anything.
5682 : : */
5683 [ # # ]: 0 : if (!grp->miss_group)
5684 : : return 0;
5685 : :
5686 : 0 : ret = mlx5dr_table_set_default_miss(grp->tbl, NULL);
5687 [ # # ]: 0 : if (ret)
5688 : 0 : return rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5689 : : "Failed to unset group miss actions");
5690 : :
5691 : 0 : mlx5_hlist_unregister(priv->sh->groups, &grp->miss_group->entry);
5692 : 0 : grp->miss_group = NULL;
5693 : :
5694 [ # # ]: 0 : LIST_REMOVE(grp, next);
5695 : 0 : mlx5_hlist_unregister(priv->sh->groups, &grp->entry);
5696 : :
5697 : 0 : return 0;
5698 : : }
5699 : :
5700 : : /**
5701 : : * Set group miss actions.
5702 : : *
5703 : : * @param[in] dev
5704 : : * Pointer to the rte_eth_dev structure.
5705 : : * @param[in] group_id
5706 : : * Group id.
5707 : : * @param[in] attr
5708 : : * Pointer to group attributes structure.
5709 : : * @param[in] actions
5710 : : * Array of actions to perform on group miss. Supported types:
5711 : : * RTE_FLOW_ACTION_TYPE_JUMP, RTE_FLOW_ACTION_TYPE_VOID, RTE_FLOW_ACTION_TYPE_END.
5712 : : * @param[out] error
5713 : : * Pointer to error structure.
5714 : : *
5715 : : * @return
5716 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
5717 : : */
5718 : :
5719 : : int
5720 : 0 : mlx5_flow_hw_group_set_miss_actions(struct rte_eth_dev *dev,
5721 : : uint32_t group_id,
5722 : : const struct rte_flow_group_attr *attr,
5723 : : const struct rte_flow_action actions[],
5724 : : struct rte_flow_error *error)
5725 : : {
5726 : 0 : struct rte_flow_error sub_error = {
5727 : : .type = RTE_FLOW_ERROR_TYPE_NONE,
5728 : : .cause = NULL,
5729 : : .message = NULL,
5730 : : };
5731 : 0 : struct mlx5_flow_template_table_cfg cfg = {
5732 : : .external = true,
5733 : : .attr = {
5734 : : .flow_attr = {
5735 : : .group = group_id,
5736 : 0 : .ingress = attr->ingress,
5737 : 0 : .egress = attr->egress,
5738 : 0 : .transfer = attr->transfer,
5739 : : },
5740 : : },
5741 : : };
5742 : 0 : struct mlx5_flow_cb_ctx ctx = {
5743 : : .dev = dev,
5744 : : .error = &sub_error,
5745 : : .data = &cfg.attr.flow_attr,
5746 : : .data2 = &cfg.attr.specialize,
5747 : : };
5748 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
5749 : : struct mlx5_flow_group *src_grp = NULL;
5750 : : struct mlx5_flow_group *dst_grp = NULL;
5751 : : struct mlx5_list_entry *ge;
5752 : 0 : uint32_t dst_group_id = 0;
5753 : : int ret;
5754 : :
5755 [ # # ]: 0 : if (flow_hw_translate_group(dev, &cfg, group_id, &group_id, error))
5756 : 0 : return -rte_errno;
5757 : :
5758 [ # # ]: 0 : if (!group_id)
5759 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5760 : : NULL, "Failed to set group miss actions - invalid group id");
5761 : :
5762 : 0 : ret = flow_hw_group_parse_miss_actions(dev, &cfg, actions, &dst_group_id, error);
5763 [ # # ]: 0 : if (ret)
5764 : 0 : return -rte_errno;
5765 : :
5766 [ # # ]: 0 : if (dst_group_id == group_id) {
5767 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5768 : : NULL, "Failed to set group miss actions - target group id must differ from group_id");
5769 : : }
5770 : :
5771 : 0 : cfg.attr.flow_attr.group = group_id;
5772 : 0 : ge = mlx5_hlist_lookup(priv->sh->groups, group_id, &ctx);
5773 [ # # ]: 0 : if (ge)
5774 : : src_grp = container_of(ge, struct mlx5_flow_group, entry);
5775 : :
5776 [ # # ]: 0 : if (dst_group_id) {
5777 : : /* Increase ref_cnt for new miss group. */
5778 : 0 : cfg.attr.flow_attr.group = dst_group_id;
5779 : 0 : ge = mlx5_hlist_register(priv->sh->groups, dst_group_id, &ctx);
5780 [ # # ]: 0 : if (!ge)
5781 : 0 : return -rte_errno;
5782 : :
5783 : : dst_grp = container_of(ge, struct mlx5_flow_group, entry);
5784 : :
5785 : 0 : cfg.attr.flow_attr.group = group_id;
5786 : 0 : ret = flow_hw_group_set_miss_group(dev, &cfg, src_grp, dst_grp, error);
5787 [ # # ]: 0 : if (ret)
5788 : 0 : goto error;
5789 : : } else {
5790 : 0 : return flow_hw_group_unset_miss_group(dev, src_grp, error);
5791 : : }
5792 : :
5793 : : return 0;
5794 : :
5795 : : error:
5796 : : if (dst_grp)
5797 : 0 : mlx5_hlist_unregister(priv->sh->groups, &dst_grp->entry);
5798 : 0 : return -rte_errno;
5799 : : }
5800 : :
5801 : : static bool
5802 : : flow_hw_modify_field_is_used(const struct rte_flow_action_modify_field *action,
5803 : : enum rte_flow_field_id field)
5804 : : {
5805 [ # # # # : 0 : return action->src.field == field || action->dst.field == field;
# # # # #
# # # # #
# # # # #
# # # # #
# # # # ]
5806 : : }
5807 : :
5808 : : static bool
5809 : : flow_hw_modify_field_is_geneve_opt(enum rte_flow_field_id field)
5810 : : {
5811 : : return field == RTE_FLOW_FIELD_GENEVE_OPT_TYPE ||
5812 : 0 : field == RTE_FLOW_FIELD_GENEVE_OPT_CLASS ||
5813 : : field == RTE_FLOW_FIELD_GENEVE_OPT_DATA;
5814 : : }
5815 : :
5816 : : static bool
5817 : 0 : flow_hw_modify_field_is_add_dst_valid(const struct rte_flow_action_modify_field *conf)
5818 : : {
5819 [ # # ]: 0 : if (conf->operation != RTE_FLOW_MODIFY_ADD)
5820 : : return true;
5821 [ # # ]: 0 : if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
5822 : : conf->src.field == RTE_FLOW_FIELD_VALUE)
5823 : : return true;
5824 [ # # ]: 0 : switch (conf->dst.field) {
5825 : : case RTE_FLOW_FIELD_IPV4_TTL:
5826 : : case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
5827 : : case RTE_FLOW_FIELD_TCP_SEQ_NUM:
5828 : : case RTE_FLOW_FIELD_TCP_ACK_NUM:
5829 : : case RTE_FLOW_FIELD_TAG:
5830 : : case RTE_FLOW_FIELD_META:
5831 : : case RTE_FLOW_FIELD_FLEX_ITEM:
5832 : : case RTE_FLOW_FIELD_TCP_DATA_OFFSET:
5833 : : case RTE_FLOW_FIELD_IPV4_IHL:
5834 : : case RTE_FLOW_FIELD_IPV4_TOTAL_LEN:
5835 : : case RTE_FLOW_FIELD_IPV6_PAYLOAD_LEN:
5836 : : return true;
5837 : : default:
5838 : : break;
5839 : : }
5840 : 0 : return false;
5841 : : }
5842 : :
5843 : : /**
5844 : : * Validate the level value for modify field action.
5845 : : *
5846 : : * @param[in] data
5847 : : * Pointer to the rte_flow_field_data structure either src or dst.
5848 : : * @param[in] inner_supported
5849 : : * Indicator whether inner should be supported.
5850 : : * @param[out] error
5851 : : * Pointer to error structure.
5852 : : *
5853 : : * @return
5854 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
5855 : : */
5856 : : static int
5857 : 0 : flow_hw_validate_modify_field_level(const struct rte_flow_field_data *data,
5858 : : bool inner_supported,
5859 : : struct rte_flow_error *error)
5860 : : {
5861 [ # # # # : 0 : switch ((int)data->field) {
# ]
5862 : : case RTE_FLOW_FIELD_START:
5863 : : case RTE_FLOW_FIELD_VLAN_TYPE:
5864 : : case RTE_FLOW_FIELD_RANDOM:
5865 : : case RTE_FLOW_FIELD_FLEX_ITEM:
5866 : : /*
5867 : : * Level shouldn't be valid since field isn't supported or
5868 : : * doesn't use 'level'.
5869 : : */
5870 : : break;
5871 : : case RTE_FLOW_FIELD_MARK:
5872 : : case RTE_FLOW_FIELD_META:
5873 : : case RTE_FLOW_FIELD_METER_COLOR:
5874 : : case RTE_FLOW_FIELD_HASH_RESULT:
5875 : : /* For meta data fields encapsulation level is don't-care. */
5876 : : break;
5877 : 0 : case RTE_FLOW_FIELD_TAG:
5878 : : case MLX5_RTE_FLOW_FIELD_META_REG:
5879 : : /*
5880 : : * The tag array for RTE_FLOW_FIELD_TAG type is provided using
5881 : : * 'tag_index' field. In old API, it was provided using 'level'
5882 : : * field and it is still supported for backwards compatibility.
5883 : : * Therefore, for meta tag field only, level is matter. It is
5884 : : * taken as tag index when 'tag_index' field isn't set, and
5885 : : * return error otherwise.
5886 : : */
5887 [ # # ]: 0 : if (data->level > 0) {
5888 [ # # ]: 0 : if (data->tag_index > 0)
5889 : 0 : return rte_flow_error_set(error, EINVAL,
5890 : : RTE_FLOW_ERROR_TYPE_ACTION,
5891 : : data,
5892 : : "tag array can be provided using 'level' or 'tag_index' fields, not both");
5893 : 0 : DRV_LOG(WARNING,
5894 : : "tag array provided in 'level' field instead of 'tag_index' field.");
5895 : : }
5896 : : break;
5897 : 0 : case RTE_FLOW_FIELD_MAC_DST:
5898 : : case RTE_FLOW_FIELD_MAC_SRC:
5899 : : case RTE_FLOW_FIELD_MAC_TYPE:
5900 : : case RTE_FLOW_FIELD_IPV4_IHL:
5901 : : case RTE_FLOW_FIELD_IPV4_TOTAL_LEN:
5902 : : case RTE_FLOW_FIELD_IPV4_DSCP:
5903 : : case RTE_FLOW_FIELD_IPV4_ECN:
5904 : : case RTE_FLOW_FIELD_IPV4_TTL:
5905 : : case RTE_FLOW_FIELD_IPV4_SRC:
5906 : : case RTE_FLOW_FIELD_IPV4_DST:
5907 : : case RTE_FLOW_FIELD_IPV6_TRAFFIC_CLASS:
5908 : : case RTE_FLOW_FIELD_IPV6_FLOW_LABEL:
5909 : : case RTE_FLOW_FIELD_IPV6_PAYLOAD_LEN:
5910 : : case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
5911 : : case RTE_FLOW_FIELD_IPV6_SRC:
5912 : : case RTE_FLOW_FIELD_IPV6_DST:
5913 : : case RTE_FLOW_FIELD_TCP_PORT_SRC:
5914 : : case RTE_FLOW_FIELD_TCP_PORT_DST:
5915 : : case RTE_FLOW_FIELD_TCP_FLAGS:
5916 : : case RTE_FLOW_FIELD_TCP_DATA_OFFSET:
5917 : : case RTE_FLOW_FIELD_UDP_PORT_SRC:
5918 : : case RTE_FLOW_FIELD_UDP_PORT_DST:
5919 [ # # ]: 0 : if (data->level > 2)
5920 : 0 : return rte_flow_error_set(error, ENOTSUP,
5921 : : RTE_FLOW_ERROR_TYPE_ACTION,
5922 : : data,
5923 : : "second inner header fields modification is not supported");
5924 [ # # ]: 0 : if (inner_supported)
5925 : : break;
5926 : : /* Fallthrough */
5927 : : case RTE_FLOW_FIELD_VLAN_ID:
5928 : : case RTE_FLOW_FIELD_IPV4_PROTO:
5929 : : case RTE_FLOW_FIELD_IPV6_PROTO:
5930 : : case RTE_FLOW_FIELD_IPV6_DSCP:
5931 : : case RTE_FLOW_FIELD_IPV6_ECN:
5932 : : case RTE_FLOW_FIELD_TCP_SEQ_NUM:
5933 : : case RTE_FLOW_FIELD_TCP_ACK_NUM:
5934 : : case RTE_FLOW_FIELD_ESP_PROTO:
5935 : : case RTE_FLOW_FIELD_ESP_SPI:
5936 : : case RTE_FLOW_FIELD_ESP_SEQ_NUM:
5937 : : case RTE_FLOW_FIELD_VXLAN_VNI:
5938 : : case RTE_FLOW_FIELD_VXLAN_LAST_RSVD:
5939 : : case RTE_FLOW_FIELD_GENEVE_VNI:
5940 : : case RTE_FLOW_FIELD_GENEVE_OPT_TYPE:
5941 : : case RTE_FLOW_FIELD_GENEVE_OPT_CLASS:
5942 : : case RTE_FLOW_FIELD_GENEVE_OPT_DATA:
5943 : : case RTE_FLOW_FIELD_GTP_TEID:
5944 : : case RTE_FLOW_FIELD_GTP_PSC_QFI:
5945 [ # # ]: 0 : if (data->level > 1)
5946 : 0 : return rte_flow_error_set(error, ENOTSUP,
5947 : : RTE_FLOW_ERROR_TYPE_ACTION,
5948 : : data,
5949 : : "inner header fields modification is not supported");
5950 : : break;
5951 : 0 : case RTE_FLOW_FIELD_MPLS:
5952 [ # # ]: 0 : if (data->level == 1)
5953 : 0 : return rte_flow_error_set(error, ENOTSUP,
5954 : : RTE_FLOW_ERROR_TYPE_ACTION,
5955 : : data,
5956 : : "outer MPLS header modification is not supported");
5957 [ # # ]: 0 : if (data->level > 2)
5958 : 0 : return rte_flow_error_set(error, ENOTSUP,
5959 : : RTE_FLOW_ERROR_TYPE_ACTION,
5960 : : data,
5961 : : "inner MPLS header modification is not supported");
5962 : : break;
5963 : 0 : case RTE_FLOW_FIELD_POINTER:
5964 : : case RTE_FLOW_FIELD_VALUE:
5965 : : default:
5966 : : MLX5_ASSERT(false);
5967 : : }
5968 : : return 0;
5969 : : }
5970 : :
5971 : : static int
5972 : 0 : flow_hw_validate_action_modify_field(struct rte_eth_dev *dev,
5973 : : const struct rte_flow_action *action,
5974 : : const struct rte_flow_action *mask,
5975 : : struct rte_flow_error *error)
5976 : : {
5977 : 0 : const struct rte_flow_action_modify_field *action_conf = action->conf;
5978 : 0 : const struct rte_flow_action_modify_field *mask_conf = mask->conf;
5979 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
5980 : 0 : struct mlx5_hca_attr *attr = &priv->sh->cdev->config.hca_attr;
5981 : : int ret;
5982 : :
5983 [ # # ]: 0 : if (!mask_conf)
5984 : 0 : return rte_flow_error_set(error, EINVAL,
5985 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
5986 : : "modify_field mask conf is missing");
5987 [ # # ]: 0 : if (action_conf->operation != mask_conf->operation)
5988 : 0 : return rte_flow_error_set(error, EINVAL,
5989 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
5990 : : "modify_field operation mask and template are not equal");
5991 [ # # ]: 0 : if (action_conf->dst.field != mask_conf->dst.field)
5992 : 0 : return rte_flow_error_set(error, EINVAL,
5993 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
5994 : : "destination field mask and template are not equal");
5995 : 0 : if (action_conf->dst.field == RTE_FLOW_FIELD_POINTER ||
5996 [ # # ]: 0 : action_conf->dst.field == RTE_FLOW_FIELD_VALUE ||
5997 : : action_conf->dst.field == RTE_FLOW_FIELD_HASH_RESULT)
5998 : 0 : return rte_flow_error_set(error, EINVAL,
5999 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6000 : : "immediate value, pointer and hash result cannot be used as destination");
6001 : 0 : ret = flow_hw_validate_modify_field_level(&action_conf->dst, false, error);
6002 [ # # ]: 0 : if (ret)
6003 : : return ret;
6004 [ # # # # ]: 0 : if (action_conf->dst.field != RTE_FLOW_FIELD_FLEX_ITEM &&
6005 : : !flow_hw_modify_field_is_geneve_opt(action_conf->dst.field)) {
6006 [ # # ]: 0 : if (action_conf->dst.tag_index &&
6007 : : !flow_modify_field_support_tag_array(action_conf->dst.field))
6008 : 0 : return rte_flow_error_set(error, EINVAL,
6009 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6010 : : "destination tag index is not supported");
6011 [ # # ]: 0 : if (action_conf->dst.class_id)
6012 : 0 : return rte_flow_error_set(error, EINVAL,
6013 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6014 : : "destination class id is not supported");
6015 : : }
6016 [ # # ]: 0 : if (mask_conf->dst.level != UINT8_MAX)
6017 : 0 : return rte_flow_error_set(error, EINVAL,
6018 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6019 : : "destination encapsulation level must be fully masked");
6020 [ # # ]: 0 : if (mask_conf->dst.offset != UINT32_MAX)
6021 : 0 : return rte_flow_error_set(error, EINVAL,
6022 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6023 : : "destination offset level must be fully masked");
6024 [ # # ]: 0 : if (action_conf->src.field != mask_conf->src.field)
6025 : 0 : return rte_flow_error_set(error, EINVAL,
6026 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6027 : : "destination field mask and template are not equal");
6028 [ # # ]: 0 : if (action_conf->src.field != RTE_FLOW_FIELD_POINTER &&
6029 : : action_conf->src.field != RTE_FLOW_FIELD_VALUE) {
6030 [ # # # # ]: 0 : if (action_conf->src.field != RTE_FLOW_FIELD_FLEX_ITEM &&
6031 : : !flow_hw_modify_field_is_geneve_opt(action_conf->src.field)) {
6032 [ # # ]: 0 : if (action_conf->src.tag_index &&
6033 : : !flow_modify_field_support_tag_array(action_conf->src.field))
6034 : 0 : return rte_flow_error_set(error, EINVAL,
6035 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6036 : : "source tag index is not supported");
6037 [ # # ]: 0 : if (action_conf->src.class_id)
6038 : 0 : return rte_flow_error_set(error, EINVAL,
6039 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6040 : : "source class id is not supported");
6041 : : }
6042 [ # # ]: 0 : if (mask_conf->src.level != UINT8_MAX)
6043 : 0 : return rte_flow_error_set(error, EINVAL,
6044 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6045 : : "source encapsulation level must be fully masked");
6046 [ # # ]: 0 : if (mask_conf->src.offset != UINT32_MAX)
6047 : 0 : return rte_flow_error_set(error, EINVAL,
6048 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6049 : : "source offset level must be fully masked");
6050 : 0 : ret = flow_hw_validate_modify_field_level(&action_conf->src, true, error);
6051 [ # # ]: 0 : if (ret)
6052 : : return ret;
6053 : : }
6054 [ # # ]: 0 : if ((action_conf->dst.field == RTE_FLOW_FIELD_TAG &&
6055 [ # # # # ]: 0 : action_conf->dst.tag_index >= MLX5_FLOW_HW_TAGS_MAX &&
6056 : 0 : action_conf->dst.tag_index != RTE_PMD_MLX5_LINEAR_HASH_TAG_INDEX) ||
6057 [ # # ]: 0 : (action_conf->src.field == RTE_FLOW_FIELD_TAG &&
6058 [ # # # # ]: 0 : action_conf->src.tag_index >= MLX5_FLOW_HW_TAGS_MAX &&
6059 : : action_conf->src.tag_index != RTE_PMD_MLX5_LINEAR_HASH_TAG_INDEX))
6060 : 0 : return rte_flow_error_set(error, EINVAL,
6061 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6062 : : "tag index is out of range");
6063 [ # # # # ]: 0 : if ((action_conf->dst.field == RTE_FLOW_FIELD_TAG &&
6064 [ # # # # ]: 0 : flow_hw_get_reg_id(dev, RTE_FLOW_ITEM_TYPE_TAG, action_conf->dst.tag_index) == REG_NON) ||
6065 [ # # ]: 0 : (action_conf->src.field == RTE_FLOW_FIELD_TAG &&
6066 [ # # ]: 0 : flow_hw_get_reg_id(dev, RTE_FLOW_ITEM_TYPE_TAG, action_conf->src.tag_index) == REG_NON))
6067 : 0 : return rte_flow_error_set(error, EINVAL,
6068 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6069 : : "tag index is out of range");
6070 [ # # ]: 0 : if (mask_conf->width != UINT32_MAX)
6071 : 0 : return rte_flow_error_set(error, EINVAL,
6072 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6073 : : "modify_field width field must be fully masked");
6074 [ # # ]: 0 : if (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_START))
6075 : 0 : return rte_flow_error_set(error, EINVAL,
6076 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6077 : : "modifying arbitrary place in a packet is not supported");
6078 [ # # ]: 0 : if (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_VLAN_TYPE))
6079 : 0 : return rte_flow_error_set(error, EINVAL,
6080 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6081 : : "modifying vlan_type is not supported");
6082 [ # # ]: 0 : if (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_RANDOM))
6083 : 0 : return rte_flow_error_set(error, EINVAL,
6084 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6085 : : "modifying random value is not supported");
6086 : : /**
6087 : : * Geneve VNI modification is supported only when Geneve header is
6088 : : * parsed natively. When GENEVE options are supported, they both Geneve
6089 : : * and options headers are parsed as a flex parser.
6090 : : */
6091 [ # # ]: 0 : if (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_GENEVE_VNI) &&
6092 [ # # ]: 0 : attr->geneve_tlv_opt)
6093 : 0 : return rte_flow_error_set(error, EINVAL,
6094 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6095 : : "modifying Geneve VNI is not supported when GENEVE opt is supported");
6096 [ # # # # ]: 0 : if (priv->tlv_options == NULL &&
6097 [ # # ]: 0 : (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_GENEVE_OPT_TYPE) ||
6098 [ # # ]: 0 : flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_GENEVE_OPT_CLASS) ||
6099 : : flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_GENEVE_OPT_DATA)))
6100 : 0 : return rte_flow_error_set(error, EINVAL,
6101 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6102 : : "modifying Geneve TLV option is supported only after parser configuration");
6103 : : /* Due to HW bug, tunnel MPLS header is read only. */
6104 [ # # ]: 0 : if (action_conf->dst.field == RTE_FLOW_FIELD_MPLS)
6105 : 0 : return rte_flow_error_set(error, EINVAL,
6106 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6107 : : "MPLS cannot be used as destination");
6108 : : /* ADD_FIELD is not supported for all the fields. */
6109 [ # # ]: 0 : if (!flow_hw_modify_field_is_add_dst_valid(action_conf))
6110 : 0 : return rte_flow_error_set(error, EINVAL,
6111 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6112 : : "invalid add_field destination");
6113 : : return 0;
6114 : : }
6115 : :
6116 : : static int
6117 : 0 : flow_hw_validate_action_port_representor(struct rte_eth_dev *dev __rte_unused,
6118 : : const struct rte_flow_actions_template_attr *attr,
6119 : : const struct rte_flow_action *action,
6120 : : const struct rte_flow_action *mask,
6121 : : struct rte_flow_error *error)
6122 : : {
6123 : : const struct rte_flow_action_ethdev *action_conf = NULL;
6124 : : const struct rte_flow_action_ethdev *mask_conf = NULL;
6125 : :
6126 : : /* If transfer is set, port has been validated as proxy port. */
6127 [ # # ]: 0 : if (!attr->transfer)
6128 : 0 : return rte_flow_error_set(error, EINVAL,
6129 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6130 : : "cannot use port_representor actions"
6131 : : " without an E-Switch");
6132 [ # # ]: 0 : if (!action || !mask)
6133 : 0 : return rte_flow_error_set(error, EINVAL,
6134 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6135 : : "actiona and mask configuration must be set");
6136 : 0 : action_conf = action->conf;
6137 : 0 : mask_conf = mask->conf;
6138 [ # # # # : 0 : if (!mask_conf || mask_conf->port_id != MLX5_REPRESENTED_PORT_ESW_MGR ||
# # ]
6139 [ # # ]: 0 : !action_conf || action_conf->port_id != MLX5_REPRESENTED_PORT_ESW_MGR)
6140 : 0 : return rte_flow_error_set(error, EINVAL,
6141 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6142 : : "only eswitch manager port 0xffff is"
6143 : : " supported");
6144 : : return 0;
6145 : : }
6146 : :
6147 : : static int
6148 : 0 : flow_hw_validate_target_port_id(struct rte_eth_dev *dev,
6149 : : uint16_t target_port_id)
6150 : : {
6151 : : struct mlx5_priv *port_priv;
6152 : : struct mlx5_priv *dev_priv;
6153 : :
6154 [ # # ]: 0 : if (target_port_id == MLX5_REPRESENTED_PORT_ESW_MGR)
6155 : : return 0;
6156 : :
6157 : 0 : port_priv = mlx5_port_to_eswitch_info(target_port_id, false);
6158 [ # # ]: 0 : if (!port_priv) {
6159 : 0 : rte_errno = EINVAL;
6160 : 0 : DRV_LOG(ERR, "Port %u Failed to obtain E-Switch info for port %u",
6161 : : dev->data->port_id, target_port_id);
6162 : 0 : return -rte_errno;
6163 : : }
6164 : :
6165 : 0 : dev_priv = mlx5_dev_to_eswitch_info(dev);
6166 [ # # ]: 0 : if (!dev_priv) {
6167 : 0 : rte_errno = EINVAL;
6168 : 0 : DRV_LOG(ERR, "Port %u Failed to obtain E-Switch info for transfer proxy",
6169 : : dev->data->port_id);
6170 : 0 : return -rte_errno;
6171 : : }
6172 : :
6173 [ # # ]: 0 : if (port_priv->domain_id != dev_priv->domain_id) {
6174 : 0 : rte_errno = EINVAL;
6175 : 0 : DRV_LOG(ERR, "Port %u Failed to obtain E-Switch info for transfer proxy",
6176 : : dev->data->port_id);
6177 : 0 : return -rte_errno;
6178 : : }
6179 : :
6180 : : return 0;
6181 : : }
6182 : :
6183 : : static int
6184 : 0 : flow_hw_validate_action_represented_port(struct rte_eth_dev *dev,
6185 : : const struct rte_flow_action *action,
6186 : : const struct rte_flow_action *mask,
6187 : : struct rte_flow_error *error)
6188 : : {
6189 : 0 : const struct rte_flow_action_ethdev *action_conf = action->conf;
6190 : 0 : const struct rte_flow_action_ethdev *mask_conf = mask->conf;
6191 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6192 : :
6193 [ # # ]: 0 : if (!priv->sh->config.dv_esw_en)
6194 : 0 : return rte_flow_error_set(error, EINVAL,
6195 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6196 : : "cannot use represented_port actions"
6197 : : " without an E-Switch");
6198 [ # # # # ]: 0 : if (mask_conf && mask_conf->port_id) {
6199 [ # # ]: 0 : if (!action_conf)
6200 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
6201 : : action, "port index was not provided");
6202 : :
6203 [ # # ]: 0 : if (flow_hw_validate_target_port_id(dev, action_conf->port_id))
6204 : 0 : return rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
6205 : : action, "port index is invalid");
6206 : : }
6207 : : return 0;
6208 : : }
6209 : :
6210 : : /**
6211 : : * Validate AGE action.
6212 : : *
6213 : : * @param[in] dev
6214 : : * Pointer to rte_eth_dev structure.
6215 : : * @param[in] action
6216 : : * Pointer to the indirect action.
6217 : : * @param[in] action_flags
6218 : : * Holds the actions detected until now.
6219 : : * @param[in] fixed_cnt
6220 : : * Indicator if this list has a fixed COUNT action.
6221 : : * @param[out] error
6222 : : * Pointer to error structure.
6223 : : *
6224 : : * @return
6225 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
6226 : : */
6227 : : static int
6228 : 0 : flow_hw_validate_action_age(struct rte_eth_dev *dev,
6229 : : const struct rte_flow_action *action,
6230 : : uint64_t action_flags, bool fixed_cnt,
6231 : : struct rte_flow_error *error)
6232 : : {
6233 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6234 : 0 : struct mlx5_age_info *age_info = GET_PORT_AGE_INFO(priv);
6235 : :
6236 [ # # ]: 0 : if (!priv->sh->cdev->config.devx)
6237 : 0 : return rte_flow_error_set(error, ENOTSUP,
6238 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6239 : : NULL, "AGE action not supported");
6240 [ # # ]: 0 : if (age_info->ages_ipool == NULL)
6241 : 0 : return rte_flow_error_set(error, EINVAL,
6242 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6243 : : "aging pool not initialized");
6244 [ # # ]: 0 : if ((action_flags & MLX5_FLOW_ACTION_AGE) ||
6245 : : (action_flags & MLX5_FLOW_ACTION_INDIRECT_AGE))
6246 : 0 : return rte_flow_error_set(error, EINVAL,
6247 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6248 : : "duplicate AGE actions set");
6249 [ # # ]: 0 : if (fixed_cnt)
6250 : 0 : return rte_flow_error_set(error, EINVAL,
6251 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6252 : : "AGE and fixed COUNT combination is not supported");
6253 : : return 0;
6254 : : }
6255 : :
6256 : : /**
6257 : : * Validate count action.
6258 : : *
6259 : : * @param[in] dev
6260 : : * Pointer to rte_eth_dev structure.
6261 : : * @param[in] action
6262 : : * Pointer to the indirect action.
6263 : : * @param[in] mask
6264 : : * Pointer to the indirect action mask.
6265 : : * @param[in] action_flags
6266 : : * Holds the actions detected until now.
6267 : : * @param[out] error
6268 : : * Pointer to error structure.
6269 : : *
6270 : : * @return
6271 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
6272 : : */
6273 : : static int
6274 : 0 : flow_hw_validate_action_count(struct rte_eth_dev *dev,
6275 : : const struct rte_flow_action *action,
6276 : : const struct rte_flow_action *mask,
6277 : : uint64_t action_flags,
6278 : : struct rte_flow_error *error)
6279 : : {
6280 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6281 : 0 : const struct rte_flow_action_count *count = mask->conf;
6282 : :
6283 [ # # ]: 0 : if (!priv->sh->cdev->config.devx)
6284 : 0 : return rte_flow_error_set(error, ENOTSUP,
6285 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6286 : : "count action not supported");
6287 [ # # ]: 0 : if (!priv->hws_cpool)
6288 : 0 : return rte_flow_error_set(error, EINVAL,
6289 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6290 : : "counters pool not initialized");
6291 [ # # ]: 0 : if ((action_flags & MLX5_FLOW_ACTION_COUNT) ||
6292 : : (action_flags & MLX5_FLOW_ACTION_INDIRECT_COUNT))
6293 : 0 : return rte_flow_error_set(error, EINVAL,
6294 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6295 : : "duplicate count actions set");
6296 [ # # # # : 0 : if (count && count->id && (action_flags & MLX5_FLOW_ACTION_AGE))
# # ]
6297 : 0 : return rte_flow_error_set(error, EINVAL,
6298 : : RTE_FLOW_ERROR_TYPE_ACTION, mask,
6299 : : "AGE and COUNT action shared by mask combination is not supported");
6300 : : return 0;
6301 : : }
6302 : :
6303 : : /**
6304 : : * Validate meter_mark action.
6305 : : *
6306 : : * @param[in] dev
6307 : : * Pointer to rte_eth_dev structure.
6308 : : * @param[in] action
6309 : : * Pointer to the indirect action.
6310 : : * @param[in] indirect
6311 : : * If true, then provided action was passed using an indirect action.
6312 : : * @param[out] error
6313 : : * Pointer to error structure.
6314 : : *
6315 : : * @return
6316 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
6317 : : */
6318 : : static int
6319 : 0 : flow_hw_validate_action_meter_mark(struct rte_eth_dev *dev,
6320 : : const struct rte_flow_action *action,
6321 : : bool indirect,
6322 : : struct rte_flow_error *error)
6323 : : {
6324 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6325 : :
6326 : : RTE_SET_USED(action);
6327 : :
6328 [ # # ]: 0 : if (!priv->sh->cdev->config.devx)
6329 : 0 : return rte_flow_error_set(error, ENOTSUP,
6330 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6331 : : "meter_mark action not supported");
6332 [ # # # # ]: 0 : if (!indirect && priv->shared_host)
6333 : 0 : return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, action,
6334 : : "meter_mark action can only be used on host port");
6335 [ # # ]: 0 : if (!priv->hws_mpool)
6336 : 0 : return rte_flow_error_set(error, EINVAL,
6337 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6338 : : "meter_mark pool not initialized");
6339 : : return 0;
6340 : : }
6341 : :
6342 : : /**
6343 : : * Validate indirect action.
6344 : : *
6345 : : * @param[in] dev
6346 : : * Pointer to rte_eth_dev structure.
6347 : : * @param[in] action
6348 : : * Pointer to the indirect action.
6349 : : * @param[in] mask
6350 : : * Pointer to the indirect action mask.
6351 : : * @param[in, out] action_flags
6352 : : * Holds the actions detected until now.
6353 : : * @param[in, out] fixed_cnt
6354 : : * Pointer to indicator if this list has a fixed COUNT action.
6355 : : * @param[out] error
6356 : : * Pointer to error structure.
6357 : : *
6358 : : * @return
6359 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
6360 : : */
6361 : : static int
6362 : 0 : flow_hw_validate_action_indirect(struct rte_eth_dev *dev,
6363 : : const struct rte_flow_action *action,
6364 : : const struct rte_flow_action *mask,
6365 : : uint64_t *action_flags, bool *fixed_cnt,
6366 : : struct rte_flow_error *error)
6367 : : {
6368 : : uint32_t type;
6369 : : int ret;
6370 : :
6371 [ # # ]: 0 : if (!mask)
6372 : 0 : return rte_flow_error_set(error, EINVAL,
6373 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6374 : : "Unable to determine indirect action type without a mask specified");
6375 : 0 : type = mask->type;
6376 [ # # # # : 0 : switch (type) {
# # # ]
6377 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
6378 : 0 : ret = flow_hw_validate_action_meter_mark(dev, mask, true, error);
6379 [ # # ]: 0 : if (ret < 0)
6380 : : return ret;
6381 : 0 : *action_flags |= MLX5_FLOW_ACTION_METER;
6382 : 0 : break;
6383 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
6384 : : /* TODO: Validation logic (same as flow_hw_actions_validate) */
6385 : 0 : *action_flags |= MLX5_FLOW_ACTION_RSS;
6386 : 0 : break;
6387 : 0 : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
6388 : : /* TODO: Validation logic (same as flow_hw_actions_validate) */
6389 : 0 : *action_flags |= MLX5_FLOW_ACTION_CT;
6390 : 0 : break;
6391 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
6392 [ # # # # ]: 0 : if (action->conf && mask->conf) {
6393 [ # # ]: 0 : if ((*action_flags & MLX5_FLOW_ACTION_AGE) ||
6394 : : (*action_flags & MLX5_FLOW_ACTION_INDIRECT_AGE))
6395 : : /*
6396 : : * AGE cannot use indirect counter which is
6397 : : * shared with enother flow rules.
6398 : : */
6399 : 0 : return rte_flow_error_set(error, EINVAL,
6400 : : RTE_FLOW_ERROR_TYPE_ACTION,
6401 : : NULL,
6402 : : "AGE and fixed COUNT combination is not supported");
6403 : 0 : *fixed_cnt = true;
6404 : : }
6405 : 0 : ret = flow_hw_validate_action_count(dev, action, mask,
6406 : : *action_flags, error);
6407 [ # # ]: 0 : if (ret < 0)
6408 : : return ret;
6409 : 0 : *action_flags |= MLX5_FLOW_ACTION_INDIRECT_COUNT;
6410 : 0 : break;
6411 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
6412 [ # # # # ]: 0 : if (action->conf && mask->conf)
6413 : 0 : return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
6414 : : action,
6415 : : "Fixed indirect age action is not supported");
6416 : 0 : ret = flow_hw_validate_action_age(dev, action, *action_flags,
6417 : 0 : *fixed_cnt, error);
6418 [ # # ]: 0 : if (ret < 0)
6419 : : return ret;
6420 : 0 : *action_flags |= MLX5_FLOW_ACTION_INDIRECT_AGE;
6421 : 0 : break;
6422 : 0 : case RTE_FLOW_ACTION_TYPE_QUOTA:
6423 : : /* TODO: add proper quota verification */
6424 : 0 : *action_flags |= MLX5_FLOW_ACTION_QUOTA;
6425 : 0 : break;
6426 : 0 : default:
6427 : 0 : DRV_LOG(WARNING, "Unsupported shared action type: %d", type);
6428 : 0 : return rte_flow_error_set(error, ENOTSUP,
6429 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, mask,
6430 : : "Unsupported indirect action type");
6431 : : }
6432 : : return 0;
6433 : : }
6434 : :
6435 : : /**
6436 : : * Validate ipv6_ext_push action.
6437 : : *
6438 : : * @param[in] dev
6439 : : * Pointer to rte_eth_dev structure.
6440 : : * @param[in] action
6441 : : * Pointer to the indirect action.
6442 : : * @param[out] error
6443 : : * Pointer to error structure.
6444 : : *
6445 : : * @return
6446 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
6447 : : */
6448 : : static int
6449 : 0 : flow_hw_validate_action_ipv6_ext_push(struct rte_eth_dev *dev __rte_unused,
6450 : : const struct rte_flow_action *action,
6451 : : struct rte_flow_error *error)
6452 : : {
6453 : 0 : const struct rte_flow_action_ipv6_ext_push *raw_push_data = action->conf;
6454 : :
6455 [ # # # # : 0 : if (!raw_push_data || !raw_push_data->size || !raw_push_data->data)
# # ]
6456 : 0 : return rte_flow_error_set(error, EINVAL,
6457 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6458 : : "invalid ipv6_ext_push data");
6459 [ # # # # ]: 0 : if (raw_push_data->type != IPPROTO_ROUTING ||
6460 : : raw_push_data->size > MLX5_PUSH_MAX_LEN)
6461 : 0 : return rte_flow_error_set(error, EINVAL,
6462 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6463 : : "Unsupported ipv6_ext_push type or length");
6464 : : return 0;
6465 : : }
6466 : :
6467 : : /**
6468 : : * Process `... / raw_decap / raw_encap / ...` actions sequence.
6469 : : * The PMD handles the sequence as a single encap or decap reformat action,
6470 : : * depending on the raw_encap configuration.
6471 : : *
6472 : : * The function assumes that the raw_decap / raw_encap location
6473 : : * in actions template list complies with relative HWS actions order:
6474 : : * for the required reformat configuration:
6475 : : * ENCAP configuration must appear before [JUMP|DROP|PORT]
6476 : : * DECAP configuration must appear at the template head.
6477 : : */
6478 : : static uint64_t
6479 : : mlx5_decap_encap_reformat_type(const struct rte_flow_action *actions,
6480 : : uint32_t encap_ind, uint64_t flags)
6481 : : {
6482 : 0 : const struct rte_flow_action_raw_encap *encap = actions[encap_ind].conf;
6483 : :
6484 [ # # ]: 0 : if ((flags & MLX5_FLOW_ACTION_DECAP) == 0)
6485 : : return MLX5_FLOW_ACTION_ENCAP;
6486 [ # # ]: 0 : if (actions[encap_ind - 1].type != RTE_FLOW_ACTION_TYPE_RAW_DECAP)
6487 : : return MLX5_FLOW_ACTION_ENCAP;
6488 : 0 : return encap->size >= MLX5_ENCAPSULATION_DECISION_SIZE ?
6489 [ # # ]: 0 : MLX5_FLOW_ACTION_ENCAP : MLX5_FLOW_ACTION_DECAP;
6490 : : }
6491 : :
6492 : : enum mlx5_hw_indirect_list_relative_position {
6493 : : MLX5_INDIRECT_LIST_POSITION_UNKNOWN = -1,
6494 : : MLX5_INDIRECT_LIST_POSITION_BEFORE_MH = 0,
6495 : : MLX5_INDIRECT_LIST_POSITION_AFTER_MH,
6496 : : };
6497 : :
6498 : : static enum mlx5_hw_indirect_list_relative_position
6499 : 0 : mlx5_hw_indirect_list_mh_position(const struct rte_flow_action *action)
6500 : : {
6501 : 0 : const struct rte_flow_action_indirect_list *conf = action->conf;
6502 [ # # # # ]: 0 : enum mlx5_indirect_list_type list_type = mlx5_get_indirect_list_type(conf->handle);
6503 : : enum mlx5_hw_indirect_list_relative_position pos = MLX5_INDIRECT_LIST_POSITION_UNKNOWN;
6504 : : const union {
6505 : : struct mlx5_indlst_legacy *legacy;
6506 : : struct mlx5_hw_encap_decap_action *reformat;
6507 : : struct rte_flow_action_list_handle *handle;
6508 : : } h = { .handle = conf->handle};
6509 : :
6510 [ # # # # ]: 0 : switch (list_type) {
6511 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY:
6512 [ # # # ]: 0 : switch (h.legacy->legacy_type) {
6513 : : case RTE_FLOW_ACTION_TYPE_AGE:
6514 : : case RTE_FLOW_ACTION_TYPE_COUNT:
6515 : : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
6516 : : case RTE_FLOW_ACTION_TYPE_METER_MARK:
6517 : : case RTE_FLOW_ACTION_TYPE_QUOTA:
6518 : : pos = MLX5_INDIRECT_LIST_POSITION_BEFORE_MH;
6519 : : break;
6520 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
6521 : : pos = MLX5_INDIRECT_LIST_POSITION_AFTER_MH;
6522 : 0 : break;
6523 : 0 : default:
6524 : : pos = MLX5_INDIRECT_LIST_POSITION_UNKNOWN;
6525 : 0 : break;
6526 : : }
6527 : : break;
6528 : : case MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR:
6529 : : pos = MLX5_INDIRECT_LIST_POSITION_AFTER_MH;
6530 : : break;
6531 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT:
6532 [ # # # ]: 0 : switch (h.reformat->action_type) {
6533 : : case MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2:
6534 : : case MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2:
6535 : : pos = MLX5_INDIRECT_LIST_POSITION_BEFORE_MH;
6536 : : break;
6537 : 0 : case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2:
6538 : : case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3:
6539 : : pos = MLX5_INDIRECT_LIST_POSITION_AFTER_MH;
6540 : 0 : break;
6541 : 0 : default:
6542 : : pos = MLX5_INDIRECT_LIST_POSITION_UNKNOWN;
6543 : 0 : break;
6544 : : }
6545 : : break;
6546 : 0 : default:
6547 : : pos = MLX5_INDIRECT_LIST_POSITION_UNKNOWN;
6548 : 0 : break;
6549 : : }
6550 : 0 : return pos;
6551 : : }
6552 : :
6553 : : #define MLX5_HW_EXPAND_MH_FAILED 0xffff
6554 : :
6555 : : static inline uint16_t
6556 : 0 : flow_hw_template_expand_modify_field(struct rte_flow_action actions[],
6557 : : struct rte_flow_action masks[],
6558 : : const struct rte_flow_action *mf_actions,
6559 : : const struct rte_flow_action *mf_masks,
6560 : : uint64_t flags, uint32_t act_num,
6561 : : uint32_t mf_num)
6562 : : {
6563 : : uint32_t i, tail;
6564 : :
6565 : : MLX5_ASSERT(actions && masks);
6566 : : MLX5_ASSERT(mf_num > 0);
6567 [ # # ]: 0 : if (flags & MLX5_FLOW_ACTION_MODIFY_FIELD) {
6568 : : /*
6569 : : * Application action template already has Modify Field.
6570 : : * It's location will be used in DR.
6571 : : * Expanded MF action can be added before the END.
6572 : : */
6573 : 0 : i = act_num - 1;
6574 : 0 : goto insert;
6575 : : }
6576 : : /**
6577 : : * Locate the first action positioned BEFORE the new MF.
6578 : : *
6579 : : * Search for a place to insert modify header
6580 : : * from the END action backwards:
6581 : : * 1. END is always present in actions array
6582 : : * 2. END location is always at action[act_num - 1]
6583 : : * 3. END always positioned AFTER modify field location
6584 : : *
6585 : : * Relative actions order is the same for RX, TX and FDB.
6586 : : *
6587 : : * Current actions order (draft-3)
6588 : : * @see action_order_arr[]
6589 : : */
6590 [ # # ]: 0 : for (i = act_num - 2; (int)i >= 0; i--) {
6591 : : enum mlx5_hw_indirect_list_relative_position pos;
6592 : 0 : enum rte_flow_action_type type = actions[i].type;
6593 : : uint64_t reformat_type;
6594 : :
6595 [ # # ]: 0 : if (type == RTE_FLOW_ACTION_TYPE_INDIRECT)
6596 : 0 : type = masks[i].type;
6597 [ # # # # ]: 0 : switch (type) {
6598 : : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
6599 : : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
6600 : : case RTE_FLOW_ACTION_TYPE_DROP:
6601 : : case RTE_FLOW_ACTION_TYPE_SEND_TO_KERNEL:
6602 : : case RTE_FLOW_ACTION_TYPE_JUMP:
6603 : : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
6604 : : case RTE_FLOW_ACTION_TYPE_QUEUE:
6605 : : case RTE_FLOW_ACTION_TYPE_RSS:
6606 : : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
6607 : : case RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:
6608 : : case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
6609 : : case RTE_FLOW_ACTION_TYPE_VOID:
6610 : : case RTE_FLOW_ACTION_TYPE_END:
6611 : : break;
6612 : : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
6613 : : reformat_type =
6614 : : mlx5_decap_encap_reformat_type(actions, i,
6615 : : flags);
6616 : : if (reformat_type == MLX5_FLOW_ACTION_DECAP) {
6617 : 0 : i++;
6618 : 0 : goto insert;
6619 : : }
6620 [ # # ]: 0 : if (actions[i - 1].type == RTE_FLOW_ACTION_TYPE_RAW_DECAP)
6621 : : i--;
6622 : : break;
6623 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT_LIST:
6624 : 0 : pos = mlx5_hw_indirect_list_mh_position(&actions[i]);
6625 [ # # ]: 0 : if (pos == MLX5_INDIRECT_LIST_POSITION_UNKNOWN)
6626 : : return MLX5_HW_EXPAND_MH_FAILED;
6627 [ # # ]: 0 : if (pos == MLX5_INDIRECT_LIST_POSITION_BEFORE_MH)
6628 : 0 : goto insert;
6629 : : break;
6630 : 0 : default:
6631 : 0 : i++; /* new MF inserted AFTER actions[i] */
6632 : 0 : goto insert;
6633 : : }
6634 : : }
6635 : : i = 0;
6636 : 0 : insert:
6637 : 0 : tail = act_num - i; /* num action to move */
6638 : 0 : memmove(actions + i + mf_num, actions + i, sizeof(actions[0]) * tail);
6639 : 0 : memcpy(actions + i, mf_actions, sizeof(actions[0]) * mf_num);
6640 : 0 : memmove(masks + i + mf_num, masks + i, sizeof(masks[0]) * tail);
6641 : : memcpy(masks + i, mf_masks, sizeof(masks[0]) * mf_num);
6642 : 0 : return i;
6643 : : }
6644 : :
6645 : : static int
6646 : 0 : flow_hw_validate_action_push_vlan(struct rte_eth_dev *dev,
6647 : : const
6648 : : struct rte_flow_actions_template_attr *attr,
6649 : : const struct rte_flow_action *action,
6650 : : const struct rte_flow_action *mask,
6651 : : struct rte_flow_error *error)
6652 : : {
6653 : : #define X_FIELD(ptr, t, f) (((ptr)->conf) && ((t *)((ptr)->conf))->f)
6654 : :
6655 : 0 : const bool masked_push =
6656 [ # # # # ]: 0 : X_FIELD(mask + MLX5_HW_VLAN_PUSH_TYPE_IDX,
6657 : : const struct rte_flow_action_of_push_vlan, ethertype);
6658 : : bool masked_param;
6659 : :
6660 : : /*
6661 : : * Mandatory actions order:
6662 : : * OF_PUSH_VLAN / OF_SET_VLAN_VID [ / OF_SET_VLAN_PCP ]
6663 : : */
6664 : : RTE_SET_USED(dev);
6665 : : RTE_SET_USED(attr);
6666 : : /* Check that mark matches OF_PUSH_VLAN */
6667 [ # # ]: 0 : if (mask[MLX5_HW_VLAN_PUSH_TYPE_IDX].type !=
6668 : : RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN)
6669 : 0 : return rte_flow_error_set(error, EINVAL,
6670 : : RTE_FLOW_ERROR_TYPE_ACTION,
6671 : : action, "OF_PUSH_VLAN: mask does not match");
6672 : : /* Check that the second template and mask items are SET_VLAN_VID */
6673 [ # # ]: 0 : if (action[MLX5_HW_VLAN_PUSH_VID_IDX].type !=
6674 : 0 : RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID ||
6675 [ # # ]: 0 : mask[MLX5_HW_VLAN_PUSH_VID_IDX].type !=
6676 : : RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)
6677 : 0 : return rte_flow_error_set(error, EINVAL,
6678 : : RTE_FLOW_ERROR_TYPE_ACTION,
6679 : : action, "OF_PUSH_VLAN: invalid actions order");
6680 [ # # # # ]: 0 : masked_param = X_FIELD(mask + MLX5_HW_VLAN_PUSH_VID_IDX,
6681 : : const struct rte_flow_action_of_set_vlan_vid,
6682 : : vlan_vid);
6683 : : /*
6684 : : * PMD requires OF_SET_VLAN_VID mask to must match OF_PUSH_VLAN
6685 : : */
6686 [ # # ]: 0 : if (masked_push ^ masked_param)
6687 : 0 : return rte_flow_error_set(error, EINVAL,
6688 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6689 : : "OF_SET_VLAN_VID: mask does not match OF_PUSH_VLAN");
6690 [ # # ]: 0 : if (is_of_vlan_pcp_present(action)) {
6691 [ # # ]: 0 : if (mask[MLX5_HW_VLAN_PUSH_PCP_IDX].type !=
6692 : : RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)
6693 : 0 : return rte_flow_error_set(error, EINVAL,
6694 : : RTE_FLOW_ERROR_TYPE_ACTION,
6695 : : action, "OF_SET_VLAN_PCP: missing mask configuration");
6696 [ # # # # ]: 0 : masked_param = X_FIELD(mask + MLX5_HW_VLAN_PUSH_PCP_IDX,
6697 : : const struct
6698 : : rte_flow_action_of_set_vlan_pcp,
6699 : : vlan_pcp);
6700 : : /*
6701 : : * PMD requires OF_SET_VLAN_PCP mask to must match OF_PUSH_VLAN
6702 : : */
6703 [ # # ]: 0 : if (masked_push ^ masked_param)
6704 : 0 : return rte_flow_error_set(error, EINVAL,
6705 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6706 : : "OF_SET_VLAN_PCP: mask does not match OF_PUSH_VLAN");
6707 : : }
6708 : : return 0;
6709 : : #undef X_FIELD
6710 : : }
6711 : :
6712 : : static int
6713 : 0 : flow_hw_validate_action_default_miss(struct rte_eth_dev *dev,
6714 : : const struct rte_flow_actions_template_attr *attr,
6715 : : uint64_t action_flags,
6716 : : struct rte_flow_error *error)
6717 : : {
6718 : : /*
6719 : : * The private DEFAULT_MISS action is used internally for LACP in control
6720 : : * flows. So this validation can be ignored. It can be kept right now since
6721 : : * the validation will be done only once.
6722 : : */
6723 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6724 : :
6725 [ # # ]: 0 : if (!attr->ingress || attr->egress || attr->transfer)
6726 : 0 : return rte_flow_error_set(error, EINVAL,
6727 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6728 : : "DEFAULT MISS is only supported in ingress.");
6729 [ # # ]: 0 : if (!priv->hw_def_miss)
6730 : 0 : return rte_flow_error_set(error, EINVAL,
6731 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6732 : : "DEFAULT MISS action does not exist.");
6733 [ # # ]: 0 : if (action_flags & MLX5_FLOW_FATE_ACTIONS)
6734 : 0 : return rte_flow_error_set(error, EINVAL,
6735 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6736 : : "DEFAULT MISS should be the only termination.");
6737 : : return 0;
6738 : : }
6739 : :
6740 : : static int
6741 : 0 : flow_hw_validate_action_nat64(struct rte_eth_dev *dev,
6742 : : const struct rte_flow_actions_template_attr *attr,
6743 : : const struct rte_flow_action *action,
6744 : : const struct rte_flow_action *mask,
6745 : : uint64_t action_flags,
6746 : : struct rte_flow_error *error)
6747 : : {
6748 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6749 : : const struct rte_flow_action_nat64 *nat64_c;
6750 : : enum rte_flow_nat64_type cov_type;
6751 : :
6752 : : RTE_SET_USED(action_flags);
6753 [ # # # # ]: 0 : if (mask->conf && ((const struct rte_flow_action_nat64 *)mask->conf)->type) {
6754 : 0 : nat64_c = (const struct rte_flow_action_nat64 *)action->conf;
6755 : 0 : cov_type = nat64_c->type;
6756 [ # # # # ]: 0 : if ((attr->ingress && !priv->action_nat64[MLX5DR_TABLE_TYPE_NIC_RX][cov_type]) ||
6757 [ # # # # ]: 0 : (attr->egress && !priv->action_nat64[MLX5DR_TABLE_TYPE_NIC_TX][cov_type]))
6758 : 0 : goto err_out;
6759 [ # # ]: 0 : if (attr->transfer) {
6760 [ # # ]: 0 : if (!is_unified_fdb(priv)) {
6761 [ # # ]: 0 : if (!priv->action_nat64[MLX5DR_TABLE_TYPE_FDB][cov_type])
6762 : 0 : goto err_out;
6763 : : } else {
6764 [ # # ]: 0 : if (!priv->action_nat64[MLX5DR_TABLE_TYPE_FDB_RX][cov_type] ||
6765 [ # # ]: 0 : !priv->action_nat64[MLX5DR_TABLE_TYPE_FDB_TX][cov_type] ||
6766 [ # # ]: 0 : !priv->action_nat64[MLX5DR_TABLE_TYPE_FDB_UNIFIED][cov_type])
6767 : 0 : goto err_out;
6768 : : }
6769 : : }
6770 : : } else {
6771 : : /*
6772 : : * Usually, the actions will be used on both directions. For non-masked actions,
6773 : : * both directions' actions will be checked.
6774 : : */
6775 [ # # ]: 0 : if (attr->ingress)
6776 [ # # ]: 0 : if (!priv->action_nat64[MLX5DR_TABLE_TYPE_NIC_RX][RTE_FLOW_NAT64_6TO4] ||
6777 [ # # ]: 0 : !priv->action_nat64[MLX5DR_TABLE_TYPE_NIC_RX][RTE_FLOW_NAT64_4TO6])
6778 : 0 : goto err_out;
6779 [ # # ]: 0 : if (attr->egress)
6780 [ # # ]: 0 : if (!priv->action_nat64[MLX5DR_TABLE_TYPE_NIC_TX][RTE_FLOW_NAT64_6TO4] ||
6781 [ # # ]: 0 : !priv->action_nat64[MLX5DR_TABLE_TYPE_NIC_TX][RTE_FLOW_NAT64_4TO6])
6782 : 0 : goto err_out;
6783 [ # # ]: 0 : if (attr->transfer) {
6784 [ # # ]: 0 : if (!is_unified_fdb(priv)) {
6785 : 0 : if (!priv->action_nat64[MLX5DR_TABLE_TYPE_FDB]
6786 [ # # ]: 0 : [RTE_FLOW_NAT64_6TO4] ||
6787 : : !priv->action_nat64[MLX5DR_TABLE_TYPE_FDB]
6788 [ # # ]: 0 : [RTE_FLOW_NAT64_4TO6])
6789 : 0 : goto err_out;
6790 : : } else {
6791 : 0 : if (!priv->action_nat64[MLX5DR_TABLE_TYPE_FDB_RX]
6792 [ # # ]: 0 : [RTE_FLOW_NAT64_6TO4] ||
6793 : : !priv->action_nat64[MLX5DR_TABLE_TYPE_FDB_RX]
6794 [ # # ]: 0 : [RTE_FLOW_NAT64_4TO6] ||
6795 : : !priv->action_nat64[MLX5DR_TABLE_TYPE_FDB_TX]
6796 [ # # ]: 0 : [RTE_FLOW_NAT64_6TO4] ||
6797 : : !priv->action_nat64[MLX5DR_TABLE_TYPE_FDB_TX]
6798 [ # # ]: 0 : [RTE_FLOW_NAT64_4TO6] ||
6799 : : !priv->action_nat64[MLX5DR_TABLE_TYPE_FDB_UNIFIED]
6800 [ # # ]: 0 : [RTE_FLOW_NAT64_6TO4] ||
6801 : : !priv->action_nat64[MLX5DR_TABLE_TYPE_FDB_UNIFIED]
6802 [ # # ]: 0 : [RTE_FLOW_NAT64_4TO6])
6803 : 0 : goto err_out;
6804 : : }
6805 : : }
6806 : : }
6807 : : return 0;
6808 : 0 : err_out:
6809 : 0 : return rte_flow_error_set(error, EOPNOTSUPP, RTE_FLOW_ERROR_TYPE_ACTION,
6810 : : NULL, "NAT64 action is not supported.");
6811 : : }
6812 : :
6813 : : static int
6814 : 0 : flow_hw_validate_action_jump(struct rte_eth_dev *dev,
6815 : : const struct rte_flow_actions_template_attr *attr,
6816 : : const struct rte_flow_action *action,
6817 : : const struct rte_flow_action *mask,
6818 : : struct rte_flow_error *error)
6819 : : {
6820 : 0 : const struct rte_flow_action_jump *m = mask->conf;
6821 : 0 : const struct rte_flow_action_jump *v = action->conf;
6822 : 0 : struct mlx5_flow_template_table_cfg cfg = {
6823 : : .external = true,
6824 : : .attr = {
6825 : : .flow_attr = {
6826 : 0 : .ingress = attr->ingress,
6827 : 0 : .egress = attr->egress,
6828 : 0 : .transfer = attr->transfer,
6829 : : },
6830 : : },
6831 : : };
6832 : 0 : uint32_t t_group = 0;
6833 : :
6834 [ # # # # ]: 0 : if (!m || !m->group)
6835 : : return 0;
6836 [ # # ]: 0 : if (!v)
6837 : 0 : return rte_flow_error_set(error, EINVAL,
6838 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6839 : : "Invalid jump action configuration");
6840 [ # # ]: 0 : if (flow_hw_translate_group(dev, &cfg, v->group, &t_group, error))
6841 : 0 : return -rte_errno;
6842 [ # # ]: 0 : if (t_group == 0)
6843 : 0 : return rte_flow_error_set(error, EINVAL,
6844 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6845 : : "Unsupported action - jump to root table");
6846 : : return 0;
6847 : : }
6848 : :
6849 : : static int
6850 : 0 : mlx5_flow_validate_action_jump_to_table_index(const struct rte_flow_action *action,
6851 : : const struct rte_flow_action *mask,
6852 : : struct rte_flow_error *error)
6853 : : {
6854 : 0 : const struct rte_flow_action_jump_to_table_index *m = mask->conf;
6855 : 0 : const struct rte_flow_action_jump_to_table_index *v = action->conf;
6856 : : struct mlx5dr_action *jump_action;
6857 : : uint32_t t_group = 0;
6858 : :
6859 [ # # # # ]: 0 : if (!m || !m->table)
6860 : : return 0;
6861 [ # # ]: 0 : if (!v)
6862 : 0 : return rte_flow_error_set(error, EINVAL,
6863 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6864 : : "Invalid jump to matcher action configuration");
6865 : 0 : t_group = v->table->grp->group_id;
6866 [ # # ]: 0 : if (t_group == 0)
6867 : 0 : return rte_flow_error_set(error, EINVAL,
6868 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6869 : : "Unsupported action - jump to root table");
6870 [ # # ]: 0 : if (likely(!rte_flow_template_table_resizable(0, &v->table->cfg.attr))) {
6871 : 0 : jump_action = v->table->matcher_info[0].jump;
6872 : : } else {
6873 : : uint32_t selector;
6874 : 0 : rte_rwlock_read_lock(&v->table->matcher_replace_rwlk);
6875 : 0 : selector = v->table->matcher_selector;
6876 : 0 : jump_action = v->table->matcher_info[selector].jump;
6877 : : rte_rwlock_read_unlock(&v->table->matcher_replace_rwlk);
6878 : : }
6879 [ # # ]: 0 : if (jump_action == NULL)
6880 : 0 : return rte_flow_error_set(error, EINVAL,
6881 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6882 : : "Unsupported action - table is not an rule array");
6883 : : return 0;
6884 : : }
6885 : :
6886 : : static int
6887 : 0 : mlx5_hw_validate_action_mark(struct rte_eth_dev *dev,
6888 : : const struct rte_flow_action *template_action,
6889 : : const struct rte_flow_action *template_mask,
6890 : : uint64_t action_flags,
6891 : : const struct rte_flow_actions_template_attr *template_attr,
6892 : : struct rte_flow_error *error)
6893 : : {
6894 : 0 : const struct rte_flow_action_mark *mark_mask = template_mask->conf;
6895 : : const struct rte_flow_action *action =
6896 [ # # # # ]: 0 : mark_mask && mark_mask->id ? template_action :
6897 : 0 : &(const struct rte_flow_action) {
6898 : : .type = RTE_FLOW_ACTION_TYPE_MARK,
6899 : 0 : .conf = &(const struct rte_flow_action_mark) {
6900 : : .id = MLX5_FLOW_MARK_MAX - 1
6901 : : }
6902 : : };
6903 : 0 : const struct rte_flow_attr attr = {
6904 : 0 : .ingress = template_attr->ingress,
6905 : 0 : .egress = template_attr->egress,
6906 : 0 : .transfer = template_attr->transfer
6907 : : };
6908 : :
6909 [ # # ]: 0 : if (template_attr->transfer &&
6910 [ # # ]: 0 : !MLX5_SH(dev)->cdev->config.hca_attr.fdb_rx_set_flow_tag_stc)
6911 : 0 : return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
6912 : : action,
6913 : : "mark action not supported for transfer");
6914 : :
6915 : 0 : return mlx5_flow_validate_action_mark(dev, action, action_flags,
6916 : : &attr, error);
6917 : : }
6918 : :
6919 : : static int
6920 : 0 : mlx5_hw_validate_action_queue(struct rte_eth_dev *dev,
6921 : : const struct rte_flow_action *template_action,
6922 : : const struct rte_flow_action *template_mask,
6923 : : const struct rte_flow_actions_template_attr *template_attr,
6924 : : uint64_t action_flags,
6925 : : struct rte_flow_error *error)
6926 : : {
6927 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6928 : 0 : const struct rte_flow_action_queue *queue_mask = template_mask->conf;
6929 : 0 : const struct rte_flow_attr attr = {
6930 : 0 : .ingress = template_attr->ingress,
6931 : 0 : .egress = template_attr->egress,
6932 : 0 : .transfer = template_attr->transfer
6933 : : };
6934 [ # # # # ]: 0 : bool masked = queue_mask != NULL && queue_mask->index;
6935 : :
6936 [ # # # # : 0 : if (template_attr->egress || (template_attr->transfer && !priv->jump_fdb_rx_en))
# # ]
6937 : 0 : return rte_flow_error_set(error, EINVAL,
6938 : : RTE_FLOW_ERROR_TYPE_ATTR, NULL,
6939 : : "QUEUE action supported for ingress only");
6940 [ # # ]: 0 : if (masked)
6941 : 0 : return mlx5_flow_validate_action_queue(template_action, action_flags, dev,
6942 : : &attr, error);
6943 : : else
6944 : : return 0;
6945 : : }
6946 : :
6947 : : static int
6948 : 0 : mlx5_hw_validate_action_rss(struct rte_eth_dev *dev,
6949 : : const struct rte_flow_action *template_action,
6950 : : const struct rte_flow_action *template_mask,
6951 : : const struct rte_flow_actions_template_attr *template_attr,
6952 : : __rte_unused uint64_t action_flags,
6953 : : struct rte_flow_error *error)
6954 : : {
6955 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6956 : 0 : const struct rte_flow_action_rss *mask = template_mask->conf;
6957 : :
6958 [ # # # # : 0 : if (template_attr->egress || (template_attr->transfer && !priv->jump_fdb_rx_en))
# # ]
6959 : 0 : return rte_flow_error_set(error, EINVAL,
6960 : : RTE_FLOW_ERROR_TYPE_ATTR, NULL,
6961 : : "RSS action supported for ingress only");
6962 [ # # ]: 0 : if (mask != NULL)
6963 : 0 : return mlx5_validate_action_rss(dev, template_action, error);
6964 : : else
6965 : : return 0;
6966 : : }
6967 : :
6968 : : static int
6969 : 0 : mlx5_hw_validate_action_l2_encap(struct rte_eth_dev *dev,
6970 : : const struct rte_flow_action *template_action,
6971 : : const struct rte_flow_action *template_mask,
6972 : : const struct rte_flow_actions_template_attr *template_attr,
6973 : : uint64_t action_flags,
6974 : : struct rte_flow_error *error)
6975 : : {
6976 : 0 : const struct rte_flow_action_vxlan_encap default_action_conf = {
6977 : : .definition = (struct rte_flow_item *)
6978 : 0 : (struct rte_flow_item [1]) {
6979 : : [0] = { .type = RTE_FLOW_ITEM_TYPE_END }
6980 : : }
6981 : : };
6982 : 0 : const struct rte_flow_action *action = template_mask->conf ?
6983 [ # # ]: 0 : template_action : &(const struct rte_flow_action) {
6984 : 0 : .type = template_mask->type,
6985 : : .conf = &default_action_conf
6986 : : };
6987 : 0 : const struct rte_flow_attr attr = {
6988 : 0 : .ingress = template_attr->ingress,
6989 : 0 : .egress = template_attr->egress,
6990 : 0 : .transfer = template_attr->transfer
6991 : : };
6992 : :
6993 : 0 : return mlx5_flow_dv_validate_action_l2_encap(dev, action_flags, action,
6994 : : &attr, error);
6995 : : }
6996 : :
6997 : : static int
6998 : 0 : mlx5_hw_validate_action_l2_decap(struct rte_eth_dev *dev,
6999 : : const struct rte_flow_action *template_action,
7000 : : const struct rte_flow_action *template_mask,
7001 : : const struct rte_flow_actions_template_attr *template_attr,
7002 : : uint64_t action_flags,
7003 : : struct rte_flow_error *error)
7004 : : {
7005 : 0 : const struct rte_flow_action_vxlan_encap default_action_conf = {
7006 : : .definition = (struct rte_flow_item *)
7007 : 0 : (struct rte_flow_item [1]) {
7008 : : [0] = { .type = RTE_FLOW_ITEM_TYPE_END }
7009 : : }
7010 : : };
7011 : 0 : const struct rte_flow_action *action = template_mask->conf ?
7012 [ # # ]: 0 : template_action : &(const struct rte_flow_action) {
7013 : 0 : .type = template_mask->type,
7014 : : .conf = &default_action_conf
7015 : : };
7016 : 0 : const struct rte_flow_attr attr = {
7017 : 0 : .ingress = template_attr->ingress,
7018 : 0 : .egress = template_attr->egress,
7019 : 0 : .transfer = template_attr->transfer
7020 : : };
7021 : : uint64_t item_flags =
7022 : 0 : action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
7023 [ # # ]: 0 : MLX5_FLOW_LAYER_VXLAN : 0;
7024 : :
7025 : 0 : return mlx5_flow_dv_validate_action_decap(dev, action_flags, action,
7026 : : item_flags, &attr, error);
7027 : : }
7028 : :
7029 : : static int
7030 : : mlx5_hw_validate_action_conntrack(struct rte_eth_dev *dev,
7031 : : const struct rte_flow_action *template_action,
7032 : : const struct rte_flow_action *template_mask,
7033 : : const struct rte_flow_actions_template_attr *template_attr,
7034 : : uint64_t action_flags,
7035 : : struct rte_flow_error *error)
7036 : : {
7037 : : RTE_SET_USED(template_action);
7038 : : RTE_SET_USED(template_mask);
7039 : : RTE_SET_USED(template_attr);
7040 : 0 : return mlx5_flow_dv_validate_action_aso_ct(dev, action_flags,
7041 : : MLX5_FLOW_LAYER_OUTER_L4_TCP,
7042 : : false, error);
7043 : : }
7044 : :
7045 : : static int
7046 : 0 : flow_hw_validate_action_raw_encap(const struct rte_flow_action *action,
7047 : : const struct rte_flow_action *mask,
7048 : : struct rte_flow_error *error)
7049 : : {
7050 : 0 : const struct rte_flow_action_raw_encap *mask_conf = mask->conf;
7051 : 0 : const struct rte_flow_action_raw_encap *action_conf = action->conf;
7052 : :
7053 [ # # # # ]: 0 : if (!mask_conf || !mask_conf->size)
7054 : 0 : return rte_flow_error_set(error, EINVAL,
7055 : : RTE_FLOW_ERROR_TYPE_ACTION, mask,
7056 : : "raw_encap: size must be masked");
7057 [ # # # # ]: 0 : if (!action_conf || !action_conf->size)
7058 : 0 : return rte_flow_error_set(error, EINVAL,
7059 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
7060 : : "raw_encap: invalid action configuration");
7061 [ # # # # ]: 0 : if (mask_conf->data && !action_conf->data)
7062 : 0 : return rte_flow_error_set(error, EINVAL,
7063 : : RTE_FLOW_ERROR_TYPE_ACTION,
7064 : : action, "raw_encap: masked data is missing");
7065 : : return 0;
7066 : : }
7067 : :
7068 : :
7069 : : static int
7070 : 0 : flow_hw_validate_action_raw_reformat(struct rte_eth_dev *dev,
7071 : : const struct rte_flow_action *template_action,
7072 : : const struct rte_flow_action *template_mask,
7073 : : const struct
7074 : : rte_flow_actions_template_attr *template_attr,
7075 : : uint64_t *action_flags,
7076 : : struct rte_flow_error *error)
7077 : : {
7078 : : const struct rte_flow_action *encap_action = NULL;
7079 : : const struct rte_flow_action *encap_mask = NULL;
7080 : : const struct rte_flow_action_raw_decap *raw_decap = NULL;
7081 : : const struct rte_flow_action_raw_encap *raw_encap = NULL;
7082 : 0 : const struct rte_flow_attr attr = {
7083 : 0 : .ingress = template_attr->ingress,
7084 : 0 : .egress = template_attr->egress,
7085 : 0 : .transfer = template_attr->transfer
7086 : : };
7087 : : uint64_t item_flags = 0;
7088 : 0 : int ret, actions_n = 0;
7089 : :
7090 [ # # ]: 0 : if (template_action->type == RTE_FLOW_ACTION_TYPE_RAW_DECAP) {
7091 : 0 : raw_decap = template_mask->conf ?
7092 [ # # ]: 0 : template_action->conf : &empty_decap;
7093 [ # # ]: 0 : if ((template_action + 1)->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7094 [ # # ]: 0 : if ((template_mask + 1)->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP)
7095 : 0 : return rte_flow_error_set(error, EINVAL,
7096 : : RTE_FLOW_ERROR_TYPE_ACTION,
7097 : 0 : template_mask + 1, "invalid mask type");
7098 : 0 : encap_action = template_action + 1;
7099 : 0 : encap_mask = template_mask + 1;
7100 : : }
7101 : : } else {
7102 : : encap_action = template_action;
7103 : : encap_mask = template_mask;
7104 : : }
7105 [ # # ]: 0 : if (encap_action) {
7106 : 0 : raw_encap = encap_action->conf;
7107 : 0 : ret = flow_hw_validate_action_raw_encap(encap_action,
7108 : : encap_mask, error);
7109 [ # # ]: 0 : if (ret)
7110 : : return ret;
7111 : : }
7112 : 0 : return mlx5_flow_dv_validate_action_raw_encap_decap(dev, raw_decap,
7113 : : raw_encap, &attr,
7114 : : action_flags,
7115 : : &actions_n,
7116 : : template_action,
7117 : : item_flags, error);
7118 : : }
7119 : :
7120 : :
7121 : :
7122 : : static int
7123 : 0 : mlx5_flow_hw_actions_validate(struct rte_eth_dev *dev,
7124 : : const struct rte_flow_actions_template_attr *attr,
7125 : : const struct rte_flow_action actions[],
7126 : : const struct rte_flow_action masks[],
7127 : : uint64_t *act_flags,
7128 : : struct rte_flow_error *error)
7129 : : {
7130 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
7131 : : const struct rte_flow_action_count *count_mask = NULL;
7132 : 0 : bool fixed_cnt = false;
7133 : 0 : uint64_t action_flags = 0;
7134 : : bool actions_end = false;
7135 : : uint16_t i;
7136 : : int ret;
7137 : : const struct rte_flow_action_ipv6_ext_remove *remove_data;
7138 : :
7139 [ # # ]: 0 : if (!mlx5_hw_ctx_validate(dev, error))
7140 : 0 : return -rte_errno;
7141 : : /* FDB actions are only valid to proxy port. */
7142 [ # # # # : 0 : if (attr->transfer && (!priv->sh->config.dv_esw_en || !priv->master))
# # ]
7143 : 0 : return rte_flow_error_set(error, EINVAL,
7144 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7145 : : NULL,
7146 : : "transfer actions are only valid to proxy port");
7147 [ # # ]: 0 : for (i = 0; !actions_end; ++i) {
7148 : 0 : const struct rte_flow_action *action = &actions[i];
7149 : 0 : const struct rte_flow_action *mask = &masks[i];
7150 : :
7151 : : MLX5_ASSERT(i < MLX5_HW_MAX_ACTS);
7152 [ # # ]: 0 : if (action->type != RTE_FLOW_ACTION_TYPE_INDIRECT &&
7153 [ # # ]: 0 : action->type != mask->type)
7154 : 0 : return rte_flow_error_set(error, ENOTSUP,
7155 : : RTE_FLOW_ERROR_TYPE_ACTION,
7156 : : action,
7157 : : "mask type does not match action type");
7158 [ # # # # : 0 : switch ((int)action->type) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # ]
7159 : : case RTE_FLOW_ACTION_TYPE_VOID:
7160 : 0 : break;
7161 : : case RTE_FLOW_ACTION_TYPE_INDIRECT_LIST:
7162 : : break;
7163 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT:
7164 : 0 : ret = flow_hw_validate_action_indirect(dev, action,
7165 : : mask,
7166 : : &action_flags,
7167 : : &fixed_cnt,
7168 : : error);
7169 [ # # ]: 0 : if (ret < 0)
7170 : 0 : return ret;
7171 : : break;
7172 : 0 : case RTE_FLOW_ACTION_TYPE_FLAG:
7173 : : /* TODO: Validation logic */
7174 : 0 : action_flags |= MLX5_FLOW_ACTION_FLAG;
7175 : 0 : break;
7176 : 0 : case RTE_FLOW_ACTION_TYPE_MARK:
7177 : 0 : ret = mlx5_hw_validate_action_mark(dev, action, mask,
7178 : : action_flags,
7179 : : attr, error);
7180 [ # # ]: 0 : if (ret)
7181 : 0 : return ret;
7182 : 0 : action_flags |= MLX5_FLOW_ACTION_MARK;
7183 : 0 : break;
7184 : 0 : case RTE_FLOW_ACTION_TYPE_DROP:
7185 : 0 : ret = mlx5_flow_validate_action_drop
7186 : : (dev, action_flags,
7187 : 0 : &(struct rte_flow_attr){.egress = attr->egress},
7188 : : error);
7189 [ # # ]: 0 : if (ret)
7190 : 0 : return ret;
7191 : 0 : action_flags |= MLX5_FLOW_ACTION_DROP;
7192 : 0 : break;
7193 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP:
7194 : : /* Only validate the jump to root table in template stage. */
7195 : 0 : ret = flow_hw_validate_action_jump(dev, attr, action, mask, error);
7196 [ # # ]: 0 : if (ret)
7197 : 0 : return ret;
7198 : 0 : action_flags |= MLX5_FLOW_ACTION_JUMP;
7199 : 0 : break;
7200 : : #ifdef HAVE_MLX5DV_DR_ACTION_CREATE_DEST_ROOT_TABLE
7201 : : case RTE_FLOW_ACTION_TYPE_SEND_TO_KERNEL: {
7202 : : bool res;
7203 : :
7204 : : if (priv->shared_host)
7205 : : return rte_flow_error_set(error, ENOTSUP,
7206 : : RTE_FLOW_ERROR_TYPE_ACTION,
7207 : : action,
7208 : : "action not supported in guest port");
7209 : : if (attr->ingress) {
7210 : : res = priv->hw_send_to_kernel[MLX5DR_TABLE_TYPE_NIC_RX];
7211 : : } else if (attr->egress) {
7212 : : res = priv->hw_send_to_kernel[MLX5DR_TABLE_TYPE_NIC_TX];
7213 : : } else {
7214 : : if (!is_unified_fdb(priv))
7215 : : res = priv->hw_send_to_kernel[MLX5DR_TABLE_TYPE_FDB];
7216 : : else
7217 : : res =
7218 : : priv->hw_send_to_kernel[MLX5DR_TABLE_TYPE_FDB_RX] &&
7219 : : priv->hw_send_to_kernel[MLX5DR_TABLE_TYPE_FDB_TX] &&
7220 : : priv->hw_send_to_kernel[MLX5DR_TABLE_TYPE_FDB_UNIFIED];
7221 : : }
7222 : : if (!res)
7223 : : return rte_flow_error_set(error, ENOTSUP,
7224 : : RTE_FLOW_ERROR_TYPE_ACTION,
7225 : : action,
7226 : : "action is not available");
7227 : :
7228 : : action_flags |= MLX5_FLOW_ACTION_SEND_TO_KERNEL;
7229 : : break;
7230 : : }
7231 : : #endif
7232 : 0 : case RTE_FLOW_ACTION_TYPE_QUEUE:
7233 : 0 : ret = mlx5_hw_validate_action_queue(dev, action, mask,
7234 : : attr, action_flags,
7235 : : error);
7236 [ # # ]: 0 : if (ret)
7237 : 0 : return ret;
7238 : 0 : action_flags |= MLX5_FLOW_ACTION_QUEUE;
7239 : 0 : break;
7240 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
7241 : 0 : ret = mlx5_hw_validate_action_rss(dev, action, mask,
7242 : : attr, action_flags,
7243 : : error);
7244 [ # # ]: 0 : if (ret)
7245 : 0 : return ret;
7246 : 0 : action_flags |= MLX5_FLOW_ACTION_RSS;
7247 : 0 : break;
7248 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7249 : : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7250 : 0 : ret = mlx5_hw_validate_action_l2_encap(dev, action, mask,
7251 : : attr, action_flags,
7252 : : error);
7253 [ # # ]: 0 : if (ret)
7254 : 0 : return ret;
7255 : 0 : action_flags |= MLX5_FLOW_ACTION_ENCAP;
7256 : 0 : break;
7257 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7258 : : case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7259 : 0 : ret = mlx5_hw_validate_action_l2_decap(dev, action, mask,
7260 : : attr, action_flags,
7261 : : error);
7262 [ # # ]: 0 : if (ret)
7263 : 0 : return ret;
7264 : 0 : action_flags |= MLX5_FLOW_ACTION_DECAP;
7265 : 0 : break;
7266 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7267 : : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7268 : 0 : ret = flow_hw_validate_action_raw_reformat(dev, action,
7269 : : mask, attr,
7270 : : &action_flags,
7271 : : error);
7272 [ # # ]: 0 : if (ret)
7273 : 0 : return ret;
7274 [ # # ]: 0 : if (action->type == RTE_FLOW_ACTION_TYPE_RAW_DECAP &&
7275 [ # # ]: 0 : (action + 1)->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7276 : 0 : action_flags |= MLX5_FLOW_XCAP_ACTIONS;
7277 : 0 : i++;
7278 : : }
7279 : : break;
7280 : 0 : case RTE_FLOW_ACTION_TYPE_IPV6_EXT_PUSH:
7281 : 0 : ret = flow_hw_validate_action_ipv6_ext_push(dev, action, error);
7282 [ # # ]: 0 : if (ret < 0)
7283 : 0 : return ret;
7284 : 0 : action_flags |= MLX5_FLOW_ACTION_IPV6_ROUTING_PUSH;
7285 : 0 : break;
7286 : 0 : case RTE_FLOW_ACTION_TYPE_IPV6_EXT_REMOVE:
7287 : 0 : remove_data = action->conf;
7288 : : /* Remove action must be shared. */
7289 [ # # # # ]: 0 : if (remove_data->type != IPPROTO_ROUTING || !mask) {
7290 : 0 : DRV_LOG(ERR, "Only supports shared IPv6 routing remove");
7291 : 0 : return -EINVAL;
7292 : : }
7293 : 0 : action_flags |= MLX5_FLOW_ACTION_IPV6_ROUTING_REMOVE;
7294 : 0 : break;
7295 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
7296 : 0 : ret = flow_hw_validate_action_meter_mark(dev, action, false, error);
7297 [ # # ]: 0 : if (ret < 0)
7298 : 0 : return ret;
7299 : 0 : action_flags |= MLX5_FLOW_ACTION_METER;
7300 : 0 : break;
7301 : 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
7302 : 0 : ret = flow_hw_validate_action_modify_field(dev, action, mask,
7303 : : error);
7304 [ # # ]: 0 : if (ret < 0)
7305 : 0 : return ret;
7306 : 0 : action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
7307 : 0 : break;
7308 : 0 : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
7309 : 0 : ret = flow_hw_validate_action_represented_port
7310 : : (dev, action, mask, error);
7311 [ # # ]: 0 : if (ret < 0)
7312 : 0 : return ret;
7313 : 0 : action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7314 : 0 : break;
7315 : 0 : case RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:
7316 : 0 : ret = flow_hw_validate_action_port_representor
7317 : : (dev, attr, action, mask, error);
7318 [ # # ]: 0 : if (ret < 0)
7319 : 0 : return ret;
7320 : 0 : action_flags |= MLX5_FLOW_ACTION_PORT_REPRESENTOR;
7321 : 0 : break;
7322 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
7323 [ # # # # ]: 0 : if (count_mask && count_mask->id)
7324 : 0 : fixed_cnt = true;
7325 : 0 : ret = flow_hw_validate_action_age(dev, action,
7326 : : action_flags,
7327 : : fixed_cnt, error);
7328 [ # # ]: 0 : if (ret < 0)
7329 : 0 : return ret;
7330 : 0 : action_flags |= MLX5_FLOW_ACTION_AGE;
7331 : 0 : break;
7332 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
7333 : 0 : ret = flow_hw_validate_action_count(dev, action, mask,
7334 : : action_flags,
7335 : : error);
7336 [ # # ]: 0 : if (ret < 0)
7337 : 0 : return ret;
7338 : 0 : count_mask = mask->conf;
7339 : 0 : action_flags |= MLX5_FLOW_ACTION_COUNT;
7340 : 0 : break;
7341 : 0 : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
7342 : 0 : ret = mlx5_hw_validate_action_conntrack(dev, action, mask,
7343 : : attr, action_flags,
7344 : : error);
7345 [ # # ]: 0 : if (ret)
7346 : 0 : return ret;
7347 : 0 : action_flags |= MLX5_FLOW_ACTION_CT;
7348 : 0 : break;
7349 : 0 : case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7350 : 0 : action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7351 : 0 : break;
7352 : 0 : case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7353 : 0 : action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7354 : 0 : break;
7355 : 0 : case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7356 : 0 : ret = flow_hw_validate_action_push_vlan
7357 : : (dev, attr, action, mask, error);
7358 [ # # ]: 0 : if (ret != 0)
7359 : 0 : return ret;
7360 : 0 : i += is_of_vlan_pcp_present(action) ?
7361 [ # # ]: 0 : MLX5_HW_VLAN_PUSH_PCP_IDX :
7362 : : MLX5_HW_VLAN_PUSH_VID_IDX;
7363 : 0 : action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7364 : 0 : break;
7365 : 0 : case RTE_FLOW_ACTION_TYPE_NAT64:
7366 : 0 : ret = flow_hw_validate_action_nat64(dev, attr, action, mask,
7367 : : action_flags, error);
7368 [ # # ]: 0 : if (ret != 0)
7369 : 0 : return ret;
7370 : 0 : action_flags |= MLX5_FLOW_ACTION_NAT64;
7371 : 0 : break;
7372 : 0 : case RTE_FLOW_ACTION_TYPE_END:
7373 : : actions_end = true;
7374 : 0 : break;
7375 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
7376 : 0 : ret = flow_hw_validate_action_default_miss(dev, attr,
7377 : : action_flags, error);
7378 [ # # ]: 0 : if (ret < 0)
7379 : 0 : return ret;
7380 : 0 : action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
7381 : 0 : break;
7382 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
7383 : 0 : ret = mlx5_flow_validate_action_jump_to_table_index(action, mask, error);
7384 [ # # ]: 0 : if (ret < 0)
7385 : 0 : return ret;
7386 : 0 : action_flags |= MLX5_FLOW_ACTION_JUMP_TO_TABLE_INDEX;
7387 : 0 : break;
7388 : 0 : default:
7389 : 0 : return rte_flow_error_set(error, ENOTSUP,
7390 : : RTE_FLOW_ERROR_TYPE_ACTION,
7391 : : action,
7392 : : "action not supported in template API");
7393 : : }
7394 : : }
7395 [ # # ]: 0 : if (act_flags != NULL)
7396 : 0 : *act_flags = action_flags;
7397 : : return 0;
7398 : : }
7399 : :
7400 : : static int
7401 : 0 : flow_hw_actions_validate(struct rte_eth_dev *dev,
7402 : : const struct rte_flow_actions_template_attr *attr,
7403 : : const struct rte_flow_action actions[],
7404 : : const struct rte_flow_action masks[],
7405 : : struct rte_flow_error *error)
7406 : : {
7407 : 0 : return mlx5_flow_hw_actions_validate(dev, attr, actions, masks, NULL, error);
7408 : : }
7409 : :
7410 : :
7411 : : static enum mlx5dr_action_type mlx5_hw_dr_action_types[] = {
7412 : : [RTE_FLOW_ACTION_TYPE_MARK] = MLX5DR_ACTION_TYP_TAG,
7413 : : [RTE_FLOW_ACTION_TYPE_FLAG] = MLX5DR_ACTION_TYP_TAG,
7414 : : [RTE_FLOW_ACTION_TYPE_DROP] = MLX5DR_ACTION_TYP_DROP,
7415 : : [RTE_FLOW_ACTION_TYPE_JUMP] = MLX5DR_ACTION_TYP_TBL,
7416 : : [RTE_FLOW_ACTION_TYPE_QUEUE] = MLX5DR_ACTION_TYP_TIR,
7417 : : [RTE_FLOW_ACTION_TYPE_RSS] = MLX5DR_ACTION_TYP_TIR,
7418 : : [RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP] = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2,
7419 : : [RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP] = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2,
7420 : : [RTE_FLOW_ACTION_TYPE_VXLAN_DECAP] = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2,
7421 : : [RTE_FLOW_ACTION_TYPE_NVGRE_DECAP] = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2,
7422 : : [RTE_FLOW_ACTION_TYPE_MODIFY_FIELD] = MLX5DR_ACTION_TYP_MODIFY_HDR,
7423 : : [RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT] = MLX5DR_ACTION_TYP_VPORT,
7424 : : [RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR] = MLX5DR_ACTION_TYP_MISS,
7425 : : [RTE_FLOW_ACTION_TYPE_CONNTRACK] = MLX5DR_ACTION_TYP_ASO_CT,
7426 : : [RTE_FLOW_ACTION_TYPE_OF_POP_VLAN] = MLX5DR_ACTION_TYP_POP_VLAN,
7427 : : [RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN] = MLX5DR_ACTION_TYP_PUSH_VLAN,
7428 : : [RTE_FLOW_ACTION_TYPE_SEND_TO_KERNEL] = MLX5DR_ACTION_TYP_DEST_ROOT,
7429 : : [RTE_FLOW_ACTION_TYPE_IPV6_EXT_PUSH] = MLX5DR_ACTION_TYP_PUSH_IPV6_ROUTE_EXT,
7430 : : [RTE_FLOW_ACTION_TYPE_IPV6_EXT_REMOVE] = MLX5DR_ACTION_TYP_POP_IPV6_ROUTE_EXT,
7431 : : [RTE_FLOW_ACTION_TYPE_NAT64] = MLX5DR_ACTION_TYP_NAT64,
7432 : : [RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX] = MLX5DR_ACTION_TYP_JUMP_TO_MATCHER,
7433 : : };
7434 : :
7435 : : static inline void
7436 : : action_template_set_type(struct rte_flow_actions_template *at,
7437 : : enum mlx5dr_action_type *action_types,
7438 : : unsigned int action_src, uint16_t *curr_off,
7439 : : enum mlx5dr_action_type type)
7440 : : {
7441 : 0 : at->dr_off[action_src] = *curr_off;
7442 : 0 : action_types[*curr_off] = type;
7443 : 0 : *curr_off = *curr_off + 1;
7444 : 0 : }
7445 : :
7446 : : static int
7447 : 0 : flow_hw_dr_actions_template_handle_shared(int type, uint32_t action_src,
7448 : : enum mlx5dr_action_type *action_types,
7449 : : uint16_t *curr_off, uint16_t *cnt_off,
7450 : : struct rte_flow_actions_template *at)
7451 : : {
7452 [ # # # # : 0 : switch (type) {
# ]
7453 : : case RTE_FLOW_ACTION_TYPE_RSS:
7454 : : action_template_set_type(at, action_types, action_src, curr_off,
7455 : : MLX5DR_ACTION_TYP_TIR);
7456 : : break;
7457 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
7458 : : case RTE_FLOW_ACTION_TYPE_COUNT:
7459 : : /*
7460 : : * Both AGE and COUNT action need counter, the first one fills
7461 : : * the action_types array, and the second only saves the offset.
7462 : : */
7463 [ # # ]: 0 : if (*cnt_off == UINT16_MAX) {
7464 : 0 : *cnt_off = *curr_off;
7465 : : action_template_set_type(at, action_types,
7466 : : action_src, curr_off,
7467 : : MLX5DR_ACTION_TYP_CTR);
7468 : : }
7469 : 0 : at->dr_off[action_src] = *cnt_off;
7470 : 0 : break;
7471 : : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
7472 : : action_template_set_type(at, action_types, action_src, curr_off,
7473 : : MLX5DR_ACTION_TYP_ASO_CT);
7474 : : break;
7475 : : case RTE_FLOW_ACTION_TYPE_QUOTA:
7476 : : case RTE_FLOW_ACTION_TYPE_METER_MARK:
7477 : : action_template_set_type(at, action_types, action_src, curr_off,
7478 : : MLX5DR_ACTION_TYP_ASO_METER);
7479 : : break;
7480 : 0 : default:
7481 : 0 : DRV_LOG(WARNING, "Unsupported shared action type: %d", type);
7482 : 0 : return -EINVAL;
7483 : : }
7484 : : return 0;
7485 : : }
7486 : :
7487 : :
7488 : : static int
7489 : 0 : flow_hw_template_actions_list(struct rte_flow_actions_template *at,
7490 : : unsigned int action_src,
7491 : : enum mlx5dr_action_type *action_types,
7492 : : uint16_t *curr_off, uint16_t *cnt_off)
7493 : : {
7494 : : int ret;
7495 : 0 : const struct rte_flow_action_indirect_list *indlst_conf = at->actions[action_src].conf;
7496 [ # # # # ]: 0 : enum mlx5_indirect_list_type list_type = mlx5_get_indirect_list_type(indlst_conf->handle);
7497 : : const union {
7498 : : struct mlx5_indlst_legacy *legacy;
7499 : : struct rte_flow_action_list_handle *handle;
7500 : : } indlst_obj = { .handle = indlst_conf->handle };
7501 : : enum mlx5dr_action_type type;
7502 : :
7503 [ # # # # ]: 0 : switch (list_type) {
7504 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY:
7505 : 0 : ret = flow_hw_dr_actions_template_handle_shared
7506 : 0 : (indlst_obj.legacy->legacy_type, action_src,
7507 : : action_types, curr_off, cnt_off, at);
7508 [ # # ]: 0 : if (ret)
7509 : 0 : return ret;
7510 : : break;
7511 : : case MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR:
7512 : : action_template_set_type(at, action_types, action_src, curr_off,
7513 : : MLX5DR_ACTION_TYP_DEST_ARRAY);
7514 : : break;
7515 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT:
7516 : 0 : type = ((struct mlx5_hw_encap_decap_action *)
7517 : : (indlst_conf->handle))->action_type;
7518 : : action_template_set_type(at, action_types, action_src, curr_off, type);
7519 : : break;
7520 : 0 : default:
7521 : 0 : DRV_LOG(ERR, "Unsupported indirect list type");
7522 : 0 : return -EINVAL;
7523 : : }
7524 : : return 0;
7525 : : }
7526 : :
7527 : : /**
7528 : : * Create DR action template based on a provided sequence of flow actions.
7529 : : *
7530 : : * @param[in] dev
7531 : : * Pointer to the rte_eth_dev structure.
7532 : : * @param[in] at
7533 : : * Pointer to flow actions template to be updated.
7534 : : * @param[out] action_types
7535 : : * Action types array to be filled.
7536 : : * @param[out] tmpl_flags
7537 : : * Template DR flags to be filled.
7538 : : *
7539 : : * @return
7540 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
7541 : : */
7542 : : static int
7543 : 0 : flow_hw_parse_flow_actions_to_dr_actions(struct rte_eth_dev *dev,
7544 : : struct rte_flow_actions_template *at,
7545 : : enum mlx5dr_action_type action_types[MLX5_HW_MAX_ACTS],
7546 : : uint32_t *tmpl_flags __rte_unused)
7547 : : {
7548 : : unsigned int i;
7549 : : uint16_t curr_off;
7550 : : enum mlx5dr_action_type reformat_act_type = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2;
7551 : : uint16_t reformat_off = UINT16_MAX;
7552 : : uint16_t mhdr_off = UINT16_MAX;
7553 : : uint16_t recom_off = UINT16_MAX;
7554 : 0 : uint16_t cnt_off = UINT16_MAX;
7555 : : enum mlx5dr_action_type recom_type = MLX5DR_ACTION_TYP_LAST;
7556 : : int ret;
7557 : :
7558 [ # # ]: 0 : for (i = 0, curr_off = 0; at->actions[i].type != RTE_FLOW_ACTION_TYPE_END; ++i) {
7559 : : const struct rte_flow_action_raw_encap *raw_encap_data;
7560 : : size_t data_size;
7561 : : enum mlx5dr_action_type type;
7562 : :
7563 [ # # ]: 0 : if (curr_off >= MLX5_HW_MAX_ACTS)
7564 : 0 : goto err_actions_num;
7565 [ # # # # : 0 : switch ((int)at->actions[i].type) {
# # # # #
# # # # #
# # # ]
7566 : : case RTE_FLOW_ACTION_TYPE_VOID:
7567 : : break;
7568 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT_LIST:
7569 : 0 : ret = flow_hw_template_actions_list(at, i, action_types,
7570 : : &curr_off, &cnt_off);
7571 [ # # ]: 0 : if (ret)
7572 : 0 : return ret;
7573 : : break;
7574 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT:
7575 : 0 : ret = flow_hw_dr_actions_template_handle_shared
7576 : 0 : (at->masks[i].type, i, action_types,
7577 : : &curr_off, &cnt_off, at);
7578 [ # # ]: 0 : if (ret)
7579 : 0 : return ret;
7580 : : break;
7581 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7582 : : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7583 : : case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7584 : : case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7585 : : MLX5_ASSERT(reformat_off == UINT16_MAX);
7586 : 0 : reformat_off = curr_off++;
7587 : 0 : reformat_act_type = mlx5_hw_dr_action_types[at->actions[i].type];
7588 : 0 : break;
7589 : 0 : case RTE_FLOW_ACTION_TYPE_IPV6_EXT_PUSH:
7590 : : MLX5_ASSERT(recom_off == UINT16_MAX);
7591 : : recom_type = MLX5DR_ACTION_TYP_PUSH_IPV6_ROUTE_EXT;
7592 : 0 : recom_off = curr_off++;
7593 : 0 : break;
7594 : 0 : case RTE_FLOW_ACTION_TYPE_IPV6_EXT_REMOVE:
7595 : : MLX5_ASSERT(recom_off == UINT16_MAX);
7596 : : recom_type = MLX5DR_ACTION_TYP_POP_IPV6_ROUTE_EXT;
7597 : 0 : recom_off = curr_off++;
7598 : 0 : break;
7599 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7600 : 0 : raw_encap_data = at->actions[i].conf;
7601 : 0 : data_size = raw_encap_data->size;
7602 [ # # ]: 0 : if (reformat_off != UINT16_MAX) {
7603 : : reformat_act_type = data_size < MLX5_ENCAPSULATION_DECISION_SIZE ?
7604 [ # # ]: 0 : MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2 :
7605 : : MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3;
7606 : : } else {
7607 : 0 : reformat_off = curr_off++;
7608 : : reformat_act_type = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;
7609 : : }
7610 : : break;
7611 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7612 : 0 : reformat_off = curr_off++;
7613 : : reformat_act_type = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2;
7614 : 0 : break;
7615 : 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
7616 [ # # ]: 0 : if (mhdr_off == UINT16_MAX) {
7617 : 0 : mhdr_off = curr_off++;
7618 : 0 : type = mlx5_hw_dr_action_types[at->actions[i].type];
7619 : 0 : action_types[mhdr_off] = type;
7620 : : }
7621 : : break;
7622 : 0 : case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7623 : 0 : type = mlx5_hw_dr_action_types[at->actions[i].type];
7624 : 0 : at->dr_off[i] = curr_off;
7625 : 0 : action_types[curr_off++] = type;
7626 : 0 : i += is_of_vlan_pcp_present(at->actions + i) ?
7627 [ # # ]: 0 : MLX5_HW_VLAN_PUSH_PCP_IDX :
7628 : : MLX5_HW_VLAN_PUSH_VID_IDX;
7629 : 0 : break;
7630 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
7631 : 0 : at->dr_off[i] = curr_off;
7632 : 0 : action_types[curr_off++] = MLX5DR_ACTION_TYP_ASO_METER;
7633 [ # # ]: 0 : if (curr_off >= MLX5_HW_MAX_ACTS)
7634 : 0 : goto err_actions_num;
7635 : : break;
7636 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
7637 : : case RTE_FLOW_ACTION_TYPE_COUNT:
7638 : : /*
7639 : : * Both AGE and COUNT action need counter, the first
7640 : : * one fills the action_types array, and the second only
7641 : : * saves the offset.
7642 : : */
7643 [ # # ]: 0 : if (cnt_off == UINT16_MAX) {
7644 : 0 : cnt_off = curr_off++;
7645 : 0 : action_types[cnt_off] = MLX5DR_ACTION_TYP_CTR;
7646 : : }
7647 : 0 : at->dr_off[i] = cnt_off;
7648 : 0 : break;
7649 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
7650 : 0 : at->dr_off[i] = curr_off;
7651 : 0 : action_types[curr_off++] = MLX5DR_ACTION_TYP_MISS;
7652 : 0 : break;
7653 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
7654 : 0 : *tmpl_flags |= MLX5DR_ACTION_TEMPLATE_FLAG_RELAXED_ORDER;
7655 : 0 : at->dr_off[i] = curr_off;
7656 : 0 : action_types[curr_off++] = MLX5DR_ACTION_TYP_JUMP_TO_MATCHER;
7657 : 0 : break;
7658 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_MIRROR:
7659 : 0 : at->dr_off[i] = curr_off;
7660 : 0 : action_types[curr_off++] = MLX5DR_ACTION_TYP_DEST_ARRAY;
7661 : 0 : break;
7662 : 0 : case RTE_FLOW_ACTION_TYPE_PORT_ID:
7663 : 0 : DRV_LOG(ERR, "RTE_FLOW_ACTION_TYPE_PORT_ID action is not supported. "
7664 : : "Use RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT instead.");
7665 : 0 : return -EINVAL;
7666 : 0 : default:
7667 : 0 : type = mlx5_hw_dr_action_types[at->actions[i].type];
7668 : 0 : at->dr_off[i] = curr_off;
7669 : 0 : action_types[curr_off++] = type;
7670 : 0 : break;
7671 : : }
7672 : : }
7673 [ # # ]: 0 : if (curr_off >= MLX5_HW_MAX_ACTS)
7674 : 0 : goto err_actions_num;
7675 [ # # ]: 0 : if (mhdr_off != UINT16_MAX)
7676 : 0 : at->mhdr_off = mhdr_off;
7677 [ # # ]: 0 : if (reformat_off != UINT16_MAX) {
7678 : 0 : at->reformat_off = reformat_off;
7679 : 0 : action_types[reformat_off] = reformat_act_type;
7680 : : }
7681 [ # # ]: 0 : if (recom_off != UINT16_MAX) {
7682 : 0 : at->recom_off = recom_off;
7683 : 0 : action_types[recom_off] = recom_type;
7684 : : }
7685 : 0 : at->dr_actions_num = curr_off;
7686 : :
7687 : : /* Create srh flex parser for remove anchor. */
7688 [ # # ]: 0 : if ((recom_type == MLX5DR_ACTION_TYP_POP_IPV6_ROUTE_EXT ||
7689 [ # # ]: 0 : recom_type == MLX5DR_ACTION_TYP_PUSH_IPV6_ROUTE_EXT) &&
7690 : 0 : (ret = mlx5_alloc_srh_flex_parser(dev))) {
7691 : 0 : DRV_LOG(ERR, "Failed to create srv6 flex parser");
7692 : 0 : return ret;
7693 : : }
7694 : : return 0;
7695 : 0 : err_actions_num:
7696 : 0 : DRV_LOG(ERR, "Number of HW actions (%u) exceeded maximum (%u) allowed in template",
7697 : : curr_off, MLX5_HW_MAX_ACTS);
7698 : 0 : return -EINVAL;
7699 : : }
7700 : :
7701 : : static int
7702 : 0 : flow_hw_set_vlan_vid(struct rte_eth_dev *dev,
7703 : : struct rte_flow_action *ra,
7704 : : struct rte_flow_action *rm,
7705 : : struct rte_flow_action_modify_field *spec,
7706 : : struct rte_flow_action_modify_field *mask,
7707 : : int set_vlan_vid_ix,
7708 : : struct rte_flow_error *error)
7709 : : {
7710 [ # # ]: 0 : const bool masked = rm[set_vlan_vid_ix].conf &&
7711 : : (((const struct rte_flow_action_of_set_vlan_vid *)
7712 [ # # ]: 0 : rm[set_vlan_vid_ix].conf)->vlan_vid != 0);
7713 : 0 : const struct rte_flow_action_of_set_vlan_vid *conf =
7714 : 0 : ra[set_vlan_vid_ix].conf;
7715 : 0 : int width = mlx5_flow_item_field_width(dev, RTE_FLOW_FIELD_VLAN_ID, 0,
7716 : : NULL, error);
7717 : : MLX5_ASSERT(width);
7718 : 0 : *spec = (typeof(*spec)) {
7719 : : .operation = RTE_FLOW_MODIFY_SET,
7720 : : .dst = {
7721 : : .field = RTE_FLOW_FIELD_VLAN_ID,
7722 : : .level = 0, .offset = 0,
7723 : : },
7724 : : .src = {
7725 : : .field = RTE_FLOW_FIELD_VALUE,
7726 : : },
7727 : : .width = width,
7728 : : };
7729 : 0 : *mask = (typeof(*mask)) {
7730 : : .operation = RTE_FLOW_MODIFY_SET,
7731 : : .dst = {
7732 : : .field = RTE_FLOW_FIELD_VLAN_ID,
7733 : : .level = 0xff, .offset = 0xffffffff,
7734 : : },
7735 : : .src = {
7736 : : .field = RTE_FLOW_FIELD_VALUE,
7737 : : },
7738 : : .width = 0xffffffff,
7739 : : };
7740 [ # # ]: 0 : if (masked) {
7741 : 0 : uint32_t mask_val = 0xffffffff;
7742 : :
7743 [ # # ]: 0 : rte_memcpy(spec->src.value, &conf->vlan_vid, sizeof(conf->vlan_vid));
7744 [ # # ]: 0 : rte_memcpy(mask->src.value, &mask_val, sizeof(mask_val));
7745 : : }
7746 : 0 : ra[set_vlan_vid_ix].type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD;
7747 : 0 : ra[set_vlan_vid_ix].conf = spec;
7748 : 0 : rm[set_vlan_vid_ix].type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD;
7749 : 0 : rm[set_vlan_vid_ix].conf = mask;
7750 : 0 : return 0;
7751 : : }
7752 : :
7753 : : static __rte_always_inline int
7754 : : flow_hw_set_vlan_vid_construct(struct rte_eth_dev *dev,
7755 : : struct mlx5_modification_cmd *mhdr_cmd,
7756 : : struct mlx5_action_construct_data *act_data,
7757 : : const struct mlx5_hw_actions *hw_acts,
7758 : : const struct rte_flow_action *action)
7759 : : {
7760 : : struct rte_flow_error error;
7761 : 0 : rte_be16_t vid = ((const struct rte_flow_action_of_set_vlan_vid *)
7762 : 0 : action->conf)->vlan_vid;
7763 : 0 : int width = mlx5_flow_item_field_width(dev, RTE_FLOW_FIELD_VLAN_ID, 0,
7764 : : NULL, &error);
7765 [ # # # # : 0 : struct rte_flow_action_modify_field conf = {
# # # # #
# ]
7766 : : .operation = RTE_FLOW_MODIFY_SET,
7767 : : .dst = {
7768 : : .field = RTE_FLOW_FIELD_VLAN_ID,
7769 : : .level = 0, .offset = 0,
7770 : : },
7771 : : .src = {
7772 : : .field = RTE_FLOW_FIELD_VALUE,
7773 : : },
7774 : : .width = width,
7775 : : };
7776 : : struct rte_flow_action modify_action = {
7777 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
7778 : : .conf = &conf
7779 : : };
7780 : :
7781 : : rte_memcpy(conf.src.value, &vid, sizeof(vid));
7782 : : return flow_hw_modify_field_construct(mhdr_cmd, act_data, hw_acts, &modify_action);
7783 : : }
7784 : :
7785 : : static int
7786 : 0 : flow_hw_flex_item_acquire(struct rte_eth_dev *dev,
7787 : : struct rte_flow_item_flex_handle *handle,
7788 : : uint8_t *flex_item)
7789 : : {
7790 : 0 : int index = mlx5_flex_acquire_index(dev, handle, false);
7791 : :
7792 : : MLX5_ASSERT(index >= 0 && index < (int)(sizeof(uint32_t) * CHAR_BIT));
7793 [ # # ]: 0 : if (index < 0)
7794 : : return -1;
7795 [ # # ]: 0 : if (!(*flex_item & RTE_BIT32(index))) {
7796 : : /* Don't count same flex item again. */
7797 : 0 : if (mlx5_flex_acquire_index(dev, handle, true) != index)
7798 : : MLX5_ASSERT(false);
7799 : 0 : *flex_item |= (uint8_t)RTE_BIT32(index);
7800 : : }
7801 : : return 0;
7802 : : }
7803 : :
7804 : : static void
7805 : 0 : flow_hw_flex_item_release(struct rte_eth_dev *dev, uint8_t *flex_item)
7806 : : {
7807 [ # # ]: 0 : while (*flex_item) {
7808 : 0 : int index = rte_bsf32(*flex_item);
7809 : :
7810 : 0 : mlx5_flex_release_index(dev, index);
7811 : 0 : *flex_item &= ~(uint8_t)RTE_BIT32(index);
7812 : : }
7813 : 0 : }
7814 : : static __rte_always_inline void
7815 : : flow_hw_actions_template_replace_container(const
7816 : : struct rte_flow_action *actions,
7817 : : const
7818 : : struct rte_flow_action *masks,
7819 : : struct rte_flow_action *new_actions,
7820 : : struct rte_flow_action *new_masks,
7821 : : struct rte_flow_action **ra,
7822 : : struct rte_flow_action **rm,
7823 : : uint32_t act_num)
7824 : : {
7825 : 0 : memcpy(new_actions, actions, sizeof(actions[0]) * act_num);
7826 : : memcpy(new_masks, masks, sizeof(masks[0]) * act_num);
7827 : : *ra = (void *)(uintptr_t)new_actions;
7828 : : *rm = (void *)(uintptr_t)new_masks;
7829 : 0 : }
7830 : :
7831 : : /* Action template copies these actions in rte_flow_conv() */
7832 : :
7833 : : static const struct rte_flow_action rx_meta_copy_action = {
7834 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
7835 : : .conf = &(struct rte_flow_action_modify_field){
7836 : : .operation = RTE_FLOW_MODIFY_SET,
7837 : : .dst = {
7838 : : .field = (enum rte_flow_field_id)
7839 : : MLX5_RTE_FLOW_FIELD_META_REG,
7840 : : .tag_index = REG_B,
7841 : : },
7842 : : .src = {
7843 : : .field = (enum rte_flow_field_id)
7844 : : MLX5_RTE_FLOW_FIELD_META_REG,
7845 : : .tag_index = REG_C_1,
7846 : : },
7847 : : .width = 32,
7848 : : }
7849 : : };
7850 : :
7851 : : static const struct rte_flow_action rx_meta_copy_mask = {
7852 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
7853 : : .conf = &(struct rte_flow_action_modify_field){
7854 : : .operation = RTE_FLOW_MODIFY_SET,
7855 : : .dst = {
7856 : : .field = (enum rte_flow_field_id)
7857 : : MLX5_RTE_FLOW_FIELD_META_REG,
7858 : : .level = UINT8_MAX,
7859 : : .tag_index = UINT8_MAX,
7860 : : .offset = UINT32_MAX,
7861 : : },
7862 : : .src = {
7863 : : .field = (enum rte_flow_field_id)
7864 : : MLX5_RTE_FLOW_FIELD_META_REG,
7865 : : .level = UINT8_MAX,
7866 : : .tag_index = UINT8_MAX,
7867 : : .offset = UINT32_MAX,
7868 : : },
7869 : : .width = UINT32_MAX,
7870 : : }
7871 : : };
7872 : :
7873 : : static const struct rte_flow_action quota_color_inc_action = {
7874 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
7875 : : .conf = &(struct rte_flow_action_modify_field) {
7876 : : .operation = RTE_FLOW_MODIFY_ADD,
7877 : : .dst = {
7878 : : .field = RTE_FLOW_FIELD_METER_COLOR,
7879 : : .level = 0, .offset = 0
7880 : : },
7881 : : .src = {
7882 : : .field = RTE_FLOW_FIELD_VALUE,
7883 : : .level = 1,
7884 : : .offset = 0,
7885 : : },
7886 : : .width = 2
7887 : : }
7888 : : };
7889 : :
7890 : : static const struct rte_flow_action quota_color_inc_mask = {
7891 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
7892 : : .conf = &(struct rte_flow_action_modify_field) {
7893 : : .operation = RTE_FLOW_MODIFY_ADD,
7894 : : .dst = {
7895 : : .field = RTE_FLOW_FIELD_METER_COLOR,
7896 : : .level = UINT8_MAX,
7897 : : .tag_index = UINT8_MAX,
7898 : : .offset = UINT32_MAX,
7899 : : },
7900 : : .src = {
7901 : : .field = RTE_FLOW_FIELD_VALUE,
7902 : : .level = 3,
7903 : : .offset = 0
7904 : : },
7905 : : .width = UINT32_MAX
7906 : : }
7907 : : };
7908 : :
7909 : : /**
7910 : : * Create flow action template.
7911 : : *
7912 : : * @param[in] dev
7913 : : * Pointer to the rte_eth_dev structure.
7914 : : * @param[in] attr
7915 : : * Pointer to the action template attributes.
7916 : : * @param[in] actions
7917 : : * Associated actions (list terminated by the END action).
7918 : : * @param[in] masks
7919 : : * List of actions that marks which of the action's member is constant.
7920 : : * @param[in] nt_mode
7921 : : * Non template mode.
7922 : : * @param[out] error
7923 : : * Pointer to error structure.
7924 : : *
7925 : : * @return
7926 : : * Action template pointer on success, NULL otherwise and rte_errno is set.
7927 : : */
7928 : : static struct rte_flow_actions_template *
7929 : 0 : __flow_hw_actions_template_create(struct rte_eth_dev *dev,
7930 : : const struct rte_flow_actions_template_attr *attr,
7931 : : const struct rte_flow_action actions[],
7932 : : const struct rte_flow_action masks[],
7933 : : bool nt_mode,
7934 : : struct rte_flow_error *error)
7935 : : {
7936 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
7937 : : int len, act_len, mask_len;
7938 : : int orig_act_len;
7939 : : unsigned int act_num;
7940 : : unsigned int i;
7941 : : struct rte_flow_actions_template *at = NULL;
7942 : : uint16_t pos;
7943 : 0 : uint64_t action_flags = 0;
7944 : : struct rte_flow_action tmp_action[MLX5_HW_MAX_ACTS];
7945 : : struct rte_flow_action tmp_mask[MLX5_HW_MAX_ACTS];
7946 : : struct rte_flow_action *ra = (void *)(uintptr_t)actions;
7947 : : struct rte_flow_action *rm = (void *)(uintptr_t)masks;
7948 : : int set_vlan_vid_ix = -1;
7949 : 0 : struct rte_flow_action_modify_field set_vlan_vid_spec = {0, };
7950 : 0 : struct rte_flow_action_modify_field set_vlan_vid_mask = {0, };
7951 : : struct rte_flow_action mf_actions[MLX5_HW_MAX_ACTS];
7952 : : struct rte_flow_action mf_masks[MLX5_HW_MAX_ACTS];
7953 : : uint32_t expand_mf_num = 0;
7954 : 0 : uint16_t src_off[MLX5_HW_MAX_ACTS] = {0, };
7955 : 0 : enum mlx5dr_action_type action_types[MLX5_HW_MAX_ACTS] = { MLX5DR_ACTION_TYP_LAST };
7956 : 0 : uint32_t tmpl_flags = 0;
7957 : : int ret;
7958 : :
7959 [ # # # # ]: 0 : if (!nt_mode && mlx5_flow_hw_actions_validate(dev, attr, actions, masks,
7960 : : &action_flags, error))
7961 : : return NULL;
7962 [ # # ]: 0 : for (i = 0; ra[i].type != RTE_FLOW_ACTION_TYPE_END; ++i) {
7963 [ # # # ]: 0 : switch (ra[i].type) {
7964 : : /* OF_PUSH_VLAN *MUST* come before OF_SET_VLAN_VID */
7965 : 0 : case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7966 : 0 : i += is_of_vlan_pcp_present(ra + i) ?
7967 [ # # ]: 0 : MLX5_HW_VLAN_PUSH_PCP_IDX :
7968 : : MLX5_HW_VLAN_PUSH_VID_IDX;
7969 : 0 : break;
7970 : 0 : case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7971 : 0 : set_vlan_vid_ix = i;
7972 : 0 : break;
7973 : : default:
7974 : : break;
7975 : : }
7976 : : }
7977 : : /*
7978 : : * Count flow actions to allocate required space for storing DR offsets and to check
7979 : : * if temporary buffer would not be overrun.
7980 : : */
7981 : 0 : act_num = i + 1;
7982 [ # # ]: 0 : if (act_num >= MLX5_HW_MAX_ACTS) {
7983 : 0 : rte_flow_error_set(error, EINVAL,
7984 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL, "Too many actions");
7985 : 0 : return NULL;
7986 : : }
7987 [ # # ]: 0 : if (set_vlan_vid_ix != -1) {
7988 : : /* If temporary action buffer was not used, copy template actions to it */
7989 : : if (ra == actions)
7990 : : flow_hw_actions_template_replace_container(actions,
7991 : : masks,
7992 : : tmp_action,
7993 : : tmp_mask,
7994 : : &ra, &rm,
7995 : : act_num);
7996 : 0 : ret = flow_hw_set_vlan_vid(dev, ra, rm,
7997 : : &set_vlan_vid_spec, &set_vlan_vid_mask,
7998 : : set_vlan_vid_ix, error);
7999 [ # # ]: 0 : if (ret)
8000 : 0 : goto error;
8001 : 0 : action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
8002 : : }
8003 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_QUOTA) {
8004 : 0 : mf_actions[expand_mf_num] = quota_color_inc_action;
8005 : 0 : mf_masks[expand_mf_num] = quota_color_inc_mask;
8006 : : expand_mf_num++;
8007 : : }
8008 [ # # ]: 0 : if (priv->sh->config.dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS &&
8009 : 0 : priv->sh->config.dv_esw_en &&
8010 [ # # ]: 0 : !attr->transfer &&
8011 [ # # ]: 0 : (action_flags & (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS))) {
8012 : : /* Insert META copy */
8013 : 0 : mf_actions[expand_mf_num] = rx_meta_copy_action;
8014 : 0 : mf_masks[expand_mf_num] = rx_meta_copy_mask;
8015 : 0 : expand_mf_num++;
8016 : : }
8017 [ # # ]: 0 : if (expand_mf_num) {
8018 [ # # ]: 0 : if (act_num + expand_mf_num > MLX5_HW_MAX_ACTS) {
8019 : 0 : rte_flow_error_set(error, E2BIG,
8020 : : RTE_FLOW_ERROR_TYPE_ACTION,
8021 : : NULL, "cannot expand: too many actions");
8022 : 0 : return NULL;
8023 : : }
8024 [ # # ]: 0 : if (ra == actions)
8025 : : flow_hw_actions_template_replace_container(actions,
8026 : : masks,
8027 : : tmp_action,
8028 : : tmp_mask,
8029 : : &ra, &rm,
8030 : : act_num);
8031 : : /* Application should make sure only one Q/RSS exist in one rule. */
8032 : 0 : pos = flow_hw_template_expand_modify_field(ra, rm,
8033 : : mf_actions,
8034 : : mf_masks,
8035 : : action_flags,
8036 : : act_num,
8037 : : expand_mf_num);
8038 [ # # ]: 0 : if (pos == MLX5_HW_EXPAND_MH_FAILED) {
8039 : 0 : rte_flow_error_set(error, ENOMEM,
8040 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8041 : : NULL, "modify header expansion failed");
8042 : 0 : return NULL;
8043 : : }
8044 : : act_num += expand_mf_num;
8045 [ # # ]: 0 : for (i = pos + expand_mf_num; i < act_num; i++)
8046 : 0 : src_off[i] += expand_mf_num;
8047 : 0 : action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
8048 : : }
8049 : 0 : act_len = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, NULL, 0, ra, error);
8050 [ # # ]: 0 : if (act_len <= 0)
8051 : : return NULL;
8052 : 0 : len = RTE_ALIGN(act_len, 16);
8053 : 0 : mask_len = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, NULL, 0, rm, error);
8054 [ # # ]: 0 : if (mask_len <= 0)
8055 : : return NULL;
8056 : 0 : len += RTE_ALIGN(mask_len, 16);
8057 : 0 : len += RTE_ALIGN(act_num * sizeof(*at->dr_off), 16);
8058 : 0 : len += RTE_ALIGN(act_num * sizeof(*at->src_off), 16);
8059 : 0 : orig_act_len = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, NULL, 0, actions, error);
8060 [ # # ]: 0 : if (orig_act_len <= 0)
8061 : : return NULL;
8062 : 0 : len += RTE_ALIGN(orig_act_len, 16);
8063 : 0 : at = mlx5_malloc(MLX5_MEM_ZERO, len + sizeof(*at),
8064 : : RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
8065 [ # # ]: 0 : if (!at) {
8066 : 0 : rte_flow_error_set(error, ENOMEM,
8067 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8068 : : NULL,
8069 : : "cannot allocate action template");
8070 : 0 : return NULL;
8071 : : }
8072 : : /* Actions part is in the first part. */
8073 : 0 : at->attr = *attr;
8074 : 0 : at->actions = (struct rte_flow_action *)(at + 1);
8075 : 0 : act_len = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, at->actions,
8076 : : len, ra, error);
8077 [ # # ]: 0 : if (act_len <= 0)
8078 : 0 : goto error;
8079 : : /* Masks part is in the second part. */
8080 : 0 : at->masks = (struct rte_flow_action *)(((uint8_t *)at->actions) + act_len);
8081 : 0 : mask_len = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, at->masks,
8082 : 0 : len - act_len, rm, error);
8083 [ # # ]: 0 : if (mask_len <= 0)
8084 : 0 : goto error;
8085 : : /* DR actions offsets in the third part. */
8086 : 0 : at->dr_off = (uint16_t *)((uint8_t *)at->masks + mask_len);
8087 : 0 : at->src_off = RTE_PTR_ADD(at->dr_off,
8088 : : RTE_ALIGN(act_num * sizeof(*at->dr_off), 16));
8089 : : memcpy(at->src_off, src_off, act_num * sizeof(at->src_off[0]));
8090 : 0 : at->orig_actions = RTE_PTR_ADD(at->src_off,
8091 : : RTE_ALIGN(act_num * sizeof(*at->src_off), 16));
8092 : 0 : orig_act_len = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, at->orig_actions, orig_act_len,
8093 : : actions, error);
8094 [ # # ]: 0 : if (orig_act_len <= 0)
8095 : 0 : goto error;
8096 : 0 : at->actions_num = act_num;
8097 [ # # ]: 0 : for (i = 0; i < at->actions_num; ++i)
8098 : 0 : at->dr_off[i] = UINT16_MAX;
8099 : 0 : at->reformat_off = UINT16_MAX;
8100 : 0 : at->mhdr_off = UINT16_MAX;
8101 : 0 : at->recom_off = UINT16_MAX;
8102 [ # # ]: 0 : for (i = 0; actions->type != RTE_FLOW_ACTION_TYPE_END;
8103 : 0 : actions++, masks++, i++) {
8104 : : const struct rte_flow_action_modify_field *info;
8105 : :
8106 [ # # # ]: 0 : switch (actions->type) {
8107 : : /*
8108 : : * mlx5 PMD hacks indirect action index directly to the action conf.
8109 : : * The rte_flow_conv() function copies the content from conf pointer.
8110 : : * Need to restore the indirect action index from action conf here.
8111 : : */
8112 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT:
8113 : 0 : at->actions[i].conf = ra[i].conf;
8114 : 0 : at->masks[i].conf = rm[i].conf;
8115 : 0 : break;
8116 : 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
8117 : 0 : info = actions->conf;
8118 [ # # # # ]: 0 : if ((info->dst.field == RTE_FLOW_FIELD_FLEX_ITEM &&
8119 : 0 : flow_hw_flex_item_acquire(dev, info->dst.flex_handle,
8120 : 0 : &at->flex_item)) ||
8121 [ # # # # ]: 0 : (info->src.field == RTE_FLOW_FIELD_FLEX_ITEM &&
8122 : 0 : flow_hw_flex_item_acquire(dev, info->src.flex_handle,
8123 : : &at->flex_item)))
8124 : 0 : goto error;
8125 : : break;
8126 : : default:
8127 : : break;
8128 : : }
8129 : : }
8130 : 0 : ret = flow_hw_parse_flow_actions_to_dr_actions(dev, at, action_types, &tmpl_flags);
8131 [ # # ]: 0 : if (ret)
8132 : 0 : goto error;
8133 : 0 : at->action_flags = action_flags;
8134 : : /* In non template mode there is no need to create the dr template. */
8135 [ # # ]: 0 : if (nt_mode)
8136 : : return at;
8137 : 0 : at->tmpl = mlx5dr_action_template_create(action_types, tmpl_flags);
8138 [ # # ]: 0 : if (!at->tmpl) {
8139 : 0 : DRV_LOG(ERR, "Failed to create DR action template: %d", rte_errno);
8140 : 0 : goto error;
8141 : : }
8142 : 0 : rte_atomic_fetch_add_explicit(&at->refcnt, 1, rte_memory_order_relaxed);
8143 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->flow_hw_at, at, next);
8144 : 0 : return at;
8145 : 0 : error:
8146 : : if (at) {
8147 : 0 : mlx5_free(at);
8148 : : }
8149 : 0 : rte_flow_error_set(error, rte_errno,
8150 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8151 : : "Failed to create action template");
8152 : 0 : return NULL;
8153 : : }
8154 : :
8155 : : /**
8156 : : * Create flow action template.
8157 : : *
8158 : : * @param[in] dev
8159 : : * Pointer to the rte_eth_dev structure.
8160 : : * @param[in] attr
8161 : : * Pointer to the action template attributes.
8162 : : * @param[in] actions
8163 : : * Associated actions (list terminated by the END action).
8164 : : * @param[in] masks
8165 : : * List of actions that marks which of the action's member is constant.
8166 : : * @param[out] error
8167 : : * Pointer to error structure.
8168 : : *
8169 : : * @return
8170 : : * Action template pointer on success, NULL otherwise and rte_errno is set.
8171 : : */
8172 : : static struct rte_flow_actions_template *
8173 : 0 : flow_hw_actions_template_create(struct rte_eth_dev *dev,
8174 : : const struct rte_flow_actions_template_attr *attr,
8175 : : const struct rte_flow_action actions[],
8176 : : const struct rte_flow_action masks[],
8177 : : struct rte_flow_error *error)
8178 : : {
8179 : 0 : return __flow_hw_actions_template_create(dev, attr, actions, masks, false, error);
8180 : : }
8181 : :
8182 : : /**
8183 : : * Destroy flow action template.
8184 : : *
8185 : : * @param[in] dev
8186 : : * Pointer to the rte_eth_dev structure.
8187 : : * @param[in] template
8188 : : * Pointer to the action template to be destroyed.
8189 : : * @param[out] error
8190 : : * Pointer to error structure.
8191 : : *
8192 : : * @return
8193 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
8194 : : */
8195 : : static int
8196 : 0 : flow_hw_actions_template_destroy(struct rte_eth_dev *dev,
8197 : : struct rte_flow_actions_template *template,
8198 : : struct rte_flow_error *error __rte_unused)
8199 : : {
8200 : : uint64_t flag = MLX5_FLOW_ACTION_IPV6_ROUTING_REMOVE |
8201 : : MLX5_FLOW_ACTION_IPV6_ROUTING_PUSH;
8202 : :
8203 [ # # ]: 0 : if (rte_atomic_load_explicit(&template->refcnt, rte_memory_order_relaxed) > 1) {
8204 : 0 : DRV_LOG(WARNING, "Action template %p is still in use.",
8205 : : (void *)template);
8206 : 0 : return rte_flow_error_set(error, EBUSY,
8207 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8208 : : NULL,
8209 : : "action template is in use");
8210 : : }
8211 [ # # ]: 0 : if (template->action_flags & flag)
8212 : 0 : mlx5_free_srh_flex_parser(dev);
8213 [ # # ]: 0 : LIST_REMOVE(template, next);
8214 : 0 : flow_hw_flex_item_release(dev, &template->flex_item);
8215 [ # # ]: 0 : if (template->tmpl)
8216 : 0 : mlx5dr_action_template_destroy(template->tmpl);
8217 : 0 : mlx5_free(template);
8218 : 0 : return 0;
8219 : : }
8220 : :
8221 : : static struct rte_flow_item *
8222 : 0 : flow_hw_prepend_item(const struct rte_flow_item *items,
8223 : : const uint32_t nb_items,
8224 : : const struct rte_flow_item *new_item,
8225 : : struct rte_flow_error *error)
8226 : : {
8227 : : struct rte_flow_item *copied_items;
8228 : : size_t size;
8229 : :
8230 : : /* Allocate new array of items. */
8231 : 0 : size = sizeof(*copied_items) * (nb_items + 1);
8232 : 0 : copied_items = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
8233 [ # # ]: 0 : if (!copied_items) {
8234 : 0 : rte_flow_error_set(error, ENOMEM,
8235 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8236 : : NULL,
8237 : : "cannot allocate item template");
8238 : 0 : return NULL;
8239 : : }
8240 : : /* Put new item at the beginning and copy the rest. */
8241 : 0 : copied_items[0] = *new_item;
8242 [ # # ]: 0 : rte_memcpy(&copied_items[1], items, sizeof(*items) * nb_items);
8243 : : return copied_items;
8244 : : }
8245 : :
8246 : : static int
8247 : 0 : flow_hw_item_compare_field_validate(enum rte_flow_field_id arg_field,
8248 : : enum rte_flow_field_id base_field,
8249 : : struct rte_flow_error *error)
8250 : : {
8251 [ # # # ]: 0 : switch (arg_field) {
8252 : : case RTE_FLOW_FIELD_TAG:
8253 : : case RTE_FLOW_FIELD_META:
8254 : : case RTE_FLOW_FIELD_ESP_SEQ_NUM:
8255 : : break;
8256 : 0 : case RTE_FLOW_FIELD_RANDOM:
8257 [ # # ]: 0 : if (base_field == RTE_FLOW_FIELD_VALUE)
8258 : : return 0;
8259 : 0 : return rte_flow_error_set(error, EINVAL,
8260 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8261 : : NULL,
8262 : : "compare random is supported only with immediate value");
8263 : 0 : default:
8264 : 0 : return rte_flow_error_set(error, ENOTSUP,
8265 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8266 : : NULL,
8267 : : "compare item argument field is not supported");
8268 : : }
8269 [ # # ]: 0 : switch (base_field) {
8270 : : case RTE_FLOW_FIELD_TAG:
8271 : : case RTE_FLOW_FIELD_META:
8272 : : case RTE_FLOW_FIELD_VALUE:
8273 : : case RTE_FLOW_FIELD_ESP_SEQ_NUM:
8274 : : break;
8275 : 0 : default:
8276 : 0 : return rte_flow_error_set(error, ENOTSUP,
8277 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8278 : : NULL,
8279 : : "compare item base field is not supported");
8280 : : }
8281 : : return 0;
8282 : : }
8283 : :
8284 : : static inline uint32_t
8285 : : flow_hw_item_compare_width_supported(enum rte_flow_field_id field)
8286 : : {
8287 [ # # # ]: 0 : switch (field) {
8288 : : case RTE_FLOW_FIELD_TAG:
8289 : : case RTE_FLOW_FIELD_META:
8290 : : case RTE_FLOW_FIELD_ESP_SEQ_NUM:
8291 : : return 32;
8292 : 0 : case RTE_FLOW_FIELD_RANDOM:
8293 : 0 : return 16;
8294 : : default:
8295 : : break;
8296 : : }
8297 : 0 : return 0;
8298 : : }
8299 : :
8300 : : static int
8301 : 0 : flow_hw_validate_item_compare(const struct rte_flow_item *item,
8302 : : struct rte_flow_error *error)
8303 : : {
8304 : 0 : const struct rte_flow_item_compare *comp_m = item->mask;
8305 : 0 : const struct rte_flow_item_compare *comp_v = item->spec;
8306 : : int ret;
8307 : :
8308 [ # # ]: 0 : if (unlikely(!comp_m))
8309 : 0 : return rte_flow_error_set(error, EINVAL,
8310 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8311 : : NULL,
8312 : : "compare item mask is missing");
8313 [ # # ]: 0 : if (comp_m->width != UINT32_MAX)
8314 : 0 : return rte_flow_error_set(error, EINVAL,
8315 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8316 : : NULL,
8317 : : "compare item only support full mask");
8318 : 0 : ret = flow_hw_item_compare_field_validate(comp_m->a.field,
8319 : 0 : comp_m->b.field, error);
8320 [ # # ]: 0 : if (ret < 0)
8321 : : return ret;
8322 [ # # ]: 0 : if (comp_v) {
8323 : : uint32_t width;
8324 : :
8325 [ # # ]: 0 : if (comp_v->operation != comp_m->operation ||
8326 [ # # ]: 0 : comp_v->a.field != comp_m->a.field ||
8327 [ # # ]: 0 : comp_v->b.field != comp_m->b.field)
8328 : 0 : return rte_flow_error_set(error, EINVAL,
8329 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8330 : : NULL,
8331 : : "compare item spec/mask not matching");
8332 : : width = flow_hw_item_compare_width_supported(comp_v->a.field);
8333 : : MLX5_ASSERT(width > 0);
8334 [ # # ]: 0 : if ((comp_v->width & comp_m->width) != width)
8335 : 0 : return rte_flow_error_set(error, EINVAL,
8336 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8337 : : NULL,
8338 : : "compare item only support full mask");
8339 : : }
8340 : : return 0;
8341 : : }
8342 : :
8343 : : static inline int
8344 : : mlx5_hw_validate_item_nsh(struct rte_eth_dev *dev,
8345 : : const struct rte_flow_item *item,
8346 : : struct rte_flow_error *error)
8347 : : {
8348 : 0 : return mlx5_flow_validate_item_nsh(dev, item, error);
8349 : : }
8350 : :
8351 : : static bool
8352 : : mlx5_hw_flow_tunnel_ip_check(uint64_t last_item, uint64_t *item_flags)
8353 : : {
8354 : : bool tunnel;
8355 : :
8356 : 0 : if (last_item == MLX5_FLOW_LAYER_OUTER_L3_IPV4 ||
8357 [ # # # # ]: 0 : last_item == MLX5_FLOW_LAYER_OUTER_L3_IPV6) {
8358 : : tunnel = true;
8359 : 0 : *item_flags |= MLX5_FLOW_LAYER_IPIP;
8360 [ # # # # ]: 0 : } else if (last_item == MLX5_FLOW_LAYER_OUTER_L3_IPV6 ||
8361 : : last_item == MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT) {
8362 : : tunnel = true;
8363 : 0 : *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
8364 : : } else {
8365 : : tunnel = false;
8366 : : }
8367 : : return tunnel;
8368 : : }
8369 : :
8370 : : const struct rte_flow_item_ipv4 hws_nic_ipv4_mask = {
8371 : : .hdr = {
8372 : : .version = 0xf,
8373 : : .ihl = 0xf,
8374 : : .type_of_service = 0xff,
8375 : : .total_length = RTE_BE16(0xffff),
8376 : : .packet_id = RTE_BE16(0xffff),
8377 : : .fragment_offset = RTE_BE16(0xffff),
8378 : : .time_to_live = 0xff,
8379 : : .next_proto_id = 0xff,
8380 : : .src_addr = RTE_BE32(0xffffffff),
8381 : : .dst_addr = RTE_BE32(0xffffffff),
8382 : : },
8383 : : };
8384 : :
8385 : : const struct rte_flow_item_ipv6 hws_nic_ipv6_mask = {
8386 : : .hdr = {
8387 : : .vtc_flow = RTE_BE32(0xffffffff),
8388 : : .payload_len = RTE_BE16(0xffff),
8389 : : .proto = 0xff,
8390 : : .hop_limits = 0xff,
8391 : : .src_addr = RTE_IPV6_MASK_FULL,
8392 : : .dst_addr = RTE_IPV6_MASK_FULL,
8393 : : },
8394 : : .has_frag_ext = 1,
8395 : : };
8396 : :
8397 : : const struct rte_flow_item_ecpri hws_nic_ecpri_mask = {
8398 : : .hdr = {
8399 : : .common = {
8400 : : .u32 = RTE_BE32(0xffffffff),
8401 : : },
8402 : : .dummy[0] = 0xffffffff,
8403 : : },
8404 : : };
8405 : :
8406 : :
8407 : : static int
8408 : 0 : flow_hw_validate_item_ptype(const struct rte_flow_item *item,
8409 : : struct rte_flow_error *error)
8410 : : {
8411 : 0 : const struct rte_flow_item_ptype *ptype = item->mask;
8412 : :
8413 : : /* HWS does not allow empty PTYPE mask */
8414 [ # # ]: 0 : if (!ptype)
8415 : 0 : return rte_flow_error_set(error, EINVAL,
8416 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8417 : : NULL, "empty ptype mask");
8418 [ # # ]: 0 : if (!(ptype->packet_type &
8419 : : (RTE_PTYPE_L2_MASK | RTE_PTYPE_L3_MASK | RTE_PTYPE_L4_MASK |
8420 : : RTE_PTYPE_INNER_L2_MASK | RTE_PTYPE_INNER_L3_MASK |
8421 : : RTE_PTYPE_INNER_L4_MASK)))
8422 : 0 : return rte_flow_error_set(error, ENOTSUP,
8423 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8424 : : NULL, "ptype mask not supported");
8425 : : return 0;
8426 : : }
8427 : :
8428 : : struct mlx5_hw_pattern_validation_ctx {
8429 : : const struct rte_flow_item *geneve_item;
8430 : : const struct rte_flow_item *flex_item;
8431 : : };
8432 : :
8433 : : static int
8434 : 0 : __flow_hw_pattern_validate(struct rte_eth_dev *dev,
8435 : : const struct rte_flow_pattern_template_attr *attr,
8436 : : const struct rte_flow_item items[],
8437 : : uint64_t *item_flags,
8438 : : bool nt_flow,
8439 : : struct rte_flow_error *error)
8440 : : {
8441 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
8442 : : const struct rte_flow_item *item;
8443 : : const struct rte_flow_item *gtp_item = NULL;
8444 : : const struct rte_flow_item *gre_item = NULL;
8445 : 0 : const struct rte_flow_attr flow_attr = {
8446 : 0 : .ingress = attr->ingress,
8447 : 0 : .egress = attr->egress,
8448 : 0 : .transfer = attr->transfer
8449 : : };
8450 : : int ret, tag_idx;
8451 : : uint32_t tag_bitmap = 0;
8452 : : uint64_t last_item = 0;
8453 : :
8454 [ # # ]: 0 : if (!mlx5_hw_ctx_validate(dev, error))
8455 : 0 : return -rte_errno;
8456 [ # # ]: 0 : if (!attr->ingress && !attr->egress && !attr->transfer)
8457 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ATTR, NULL,
8458 : : "at least one of the direction attributes"
8459 : : " must be specified");
8460 [ # # ]: 0 : if (priv->sh->config.dv_esw_en) {
8461 : : MLX5_ASSERT(priv->master || priv->representor);
8462 [ # # ]: 0 : if (priv->master) {
8463 [ # # ]: 0 : if ((attr->ingress && attr->egress) ||
8464 [ # # ]: 0 : (attr->ingress && attr->transfer) ||
8465 [ # # ]: 0 : (attr->egress && attr->transfer))
8466 : 0 : return rte_flow_error_set(error, EINVAL,
8467 : : RTE_FLOW_ERROR_TYPE_ATTR, NULL,
8468 : : "only one direction attribute at once"
8469 : : " can be used on transfer proxy port");
8470 : : } else {
8471 [ # # ]: 0 : if (attr->transfer)
8472 : 0 : return rte_flow_error_set(error, EINVAL,
8473 : : RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER, NULL,
8474 : : "transfer attribute cannot be used with"
8475 : : " port representors");
8476 [ # # ]: 0 : if (attr->ingress && attr->egress)
8477 : 0 : return rte_flow_error_set(error, EINVAL,
8478 : : RTE_FLOW_ERROR_TYPE_ATTR, NULL,
8479 : : "ingress and egress direction attributes"
8480 : : " cannot be used at the same time on"
8481 : : " port representors");
8482 : : }
8483 : : } else {
8484 [ # # ]: 0 : if (attr->transfer)
8485 : 0 : return rte_flow_error_set(error, EINVAL,
8486 : : RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER, NULL,
8487 : : "transfer attribute cannot be used when"
8488 : : " E-Switch is disabled");
8489 : : }
8490 [ # # ]: 0 : for (item = items; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
8491 : 0 : bool tunnel = *item_flags & MLX5_FLOW_LAYER_TUNNEL;
8492 : :
8493 [ # # # # : 0 : switch ((int)item->type) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # #
# ]
8494 : 0 : case RTE_FLOW_ITEM_TYPE_PTYPE:
8495 : 0 : ret = flow_hw_validate_item_ptype(item, error);
8496 [ # # ]: 0 : if (ret)
8497 : 0 : return ret;
8498 : : last_item = MLX5_FLOW_ITEM_PTYPE;
8499 : : break;
8500 : 0 : case RTE_FLOW_ITEM_TYPE_TAG:
8501 : : {
8502 : 0 : const struct rte_flow_item_tag *tag =
8503 : : (const struct rte_flow_item_tag *)item->spec;
8504 : :
8505 [ # # ]: 0 : if (tag == NULL)
8506 : 0 : return rte_flow_error_set(error, EINVAL,
8507 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8508 : : NULL,
8509 : : "Tag spec is NULL");
8510 [ # # ]: 0 : if (tag->index >= MLX5_FLOW_HW_TAGS_MAX &&
8511 : : tag->index != RTE_PMD_MLX5_LINEAR_HASH_TAG_INDEX)
8512 : 0 : return rte_flow_error_set(error, EINVAL,
8513 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8514 : : NULL,
8515 : : "Invalid tag index");
8516 [ # # ]: 0 : tag_idx = flow_hw_get_reg_id(dev, RTE_FLOW_ITEM_TYPE_TAG, tag->index);
8517 [ # # ]: 0 : if (tag_idx == REG_NON)
8518 : 0 : return rte_flow_error_set(error, EINVAL,
8519 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8520 : : NULL,
8521 : : "Unsupported tag index");
8522 [ # # ]: 0 : if (tag_bitmap & (1 << tag_idx))
8523 : 0 : return rte_flow_error_set(error, EINVAL,
8524 : : RTE_FLOW_ERROR_TYPE_ITEM,
8525 : : NULL,
8526 : : "Duplicated tag index");
8527 : 0 : tag_bitmap |= 1 << tag_idx;
8528 : : last_item = MLX5_FLOW_ITEM_TAG;
8529 : 0 : break;
8530 : : }
8531 : 0 : case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
8532 : : {
8533 : 0 : const struct rte_flow_item_tag *tag =
8534 : : (const struct rte_flow_item_tag *)item->spec;
8535 : 0 : uint16_t regcs = (uint8_t)priv->sh->cdev->config.hca_attr.set_reg_c;
8536 : :
8537 [ # # ]: 0 : if (!((1 << (tag->index - REG_C_0)) & regcs))
8538 : 0 : return rte_flow_error_set(error, EINVAL,
8539 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8540 : : NULL,
8541 : : "Unsupported internal tag index");
8542 [ # # ]: 0 : if (tag_bitmap & (1 << tag->index))
8543 : 0 : return rte_flow_error_set(error, EINVAL,
8544 : : RTE_FLOW_ERROR_TYPE_ITEM,
8545 : : NULL,
8546 : : "Duplicated tag index");
8547 : 0 : tag_bitmap |= 1 << tag->index;
8548 : 0 : break;
8549 : : }
8550 : 0 : case RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT:
8551 [ # # # # ]: 0 : if (attr->ingress && priv->sh->config.repr_matching)
8552 : 0 : return rte_flow_error_set(error, EINVAL,
8553 : : RTE_FLOW_ERROR_TYPE_ITEM, NULL,
8554 : : "represented port item cannot be used"
8555 : : " when ingress attribute is set");
8556 [ # # ]: 0 : if (attr->egress)
8557 : 0 : return rte_flow_error_set(error, EINVAL,
8558 : : RTE_FLOW_ERROR_TYPE_ITEM, NULL,
8559 : : "represented port item cannot be used"
8560 : : " when egress attribute is set");
8561 : : last_item = MLX5_FLOW_ITEM_REPRESENTED_PORT;
8562 : : break;
8563 : 0 : case RTE_FLOW_ITEM_TYPE_META:
8564 : : /* ingress + group 0 is not supported */
8565 : 0 : *item_flags |= MLX5_FLOW_ITEM_METADATA;
8566 : 0 : break;
8567 : : case RTE_FLOW_ITEM_TYPE_METER_COLOR:
8568 : : {
8569 : : int reg = flow_hw_get_reg_id(dev,
8570 : : RTE_FLOW_ITEM_TYPE_METER_COLOR,
8571 : : 0);
8572 [ # # ]: 0 : if (reg == REG_NON)
8573 : 0 : return rte_flow_error_set(error, EINVAL,
8574 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8575 : : NULL,
8576 : : "Unsupported meter color register");
8577 [ # # ]: 0 : if (*item_flags &
8578 : : (MLX5_FLOW_ITEM_QUOTA | MLX5_FLOW_LAYER_ASO_CT))
8579 : 0 : return rte_flow_error_set
8580 : : (error, EINVAL,
8581 : : RTE_FLOW_ERROR_TYPE_ITEM, NULL, "Only one ASO item is supported");
8582 : : last_item = MLX5_FLOW_ITEM_METER_COLOR;
8583 : : break;
8584 : : }
8585 : 0 : case RTE_FLOW_ITEM_TYPE_AGGR_AFFINITY:
8586 : : {
8587 [ # # ]: 0 : if (!priv->sh->lag_rx_port_affinity_en)
8588 : 0 : return rte_flow_error_set(error, EINVAL,
8589 : : RTE_FLOW_ERROR_TYPE_ITEM, NULL,
8590 : : "Unsupported aggregated affinity with Older FW");
8591 [ # # # # : 0 : if ((attr->transfer && priv->fdb_def_rule) || attr->egress)
# # ]
8592 : 0 : return rte_flow_error_set(error, EINVAL,
8593 : : RTE_FLOW_ERROR_TYPE_ITEM, NULL,
8594 : : "Aggregated affinity item not supported"
8595 : : " with egress or transfer"
8596 : : " attribute");
8597 : : last_item = MLX5_FLOW_ITEM_AGGR_AFFINITY;
8598 : : break;
8599 : : }
8600 : 0 : case RTE_FLOW_ITEM_TYPE_GENEVE:
8601 : : last_item = MLX5_FLOW_LAYER_GENEVE;
8602 : 0 : break;
8603 : 0 : case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
8604 : : {
8605 : : last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
8606 : : /*
8607 : : * For non template the parser is internally created before
8608 : : * the flow creation.
8609 : : */
8610 [ # # ]: 0 : if (!nt_flow) {
8611 : 0 : ret = mlx5_flow_geneve_tlv_option_validate(priv, item,
8612 : : error);
8613 [ # # ]: 0 : if (ret < 0)
8614 : 0 : return ret;
8615 : : }
8616 : : break;
8617 : : }
8618 : 0 : case RTE_FLOW_ITEM_TYPE_COMPARE:
8619 : : {
8620 : : last_item = MLX5_FLOW_ITEM_COMPARE;
8621 : 0 : ret = flow_hw_validate_item_compare(item, error);
8622 [ # # ]: 0 : if (ret)
8623 : 0 : return ret;
8624 : : break;
8625 : : }
8626 : 0 : case RTE_FLOW_ITEM_TYPE_ETH:
8627 : 0 : ret = mlx5_flow_validate_item_eth(dev, item,
8628 : : *item_flags,
8629 : : true, error);
8630 [ # # ]: 0 : if (ret < 0)
8631 : 0 : return ret;
8632 [ # # ]: 0 : last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
8633 : : MLX5_FLOW_LAYER_OUTER_L2;
8634 : : break;
8635 : 0 : case RTE_FLOW_ITEM_TYPE_VLAN:
8636 : 0 : ret = mlx5_flow_dv_validate_item_vlan(item, *item_flags,
8637 : : dev, error);
8638 [ # # ]: 0 : if (ret < 0)
8639 : 0 : return ret;
8640 [ # # ]: 0 : last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
8641 : : MLX5_FLOW_LAYER_OUTER_VLAN;
8642 : : break;
8643 : : case RTE_FLOW_ITEM_TYPE_IPV4:
8644 : 0 : tunnel |= mlx5_hw_flow_tunnel_ip_check(last_item,
8645 : : item_flags);
8646 : 0 : ret = mlx5_flow_dv_validate_item_ipv4(dev, item,
8647 : : *item_flags,
8648 : : last_item, 0,
8649 : : &hws_nic_ipv4_mask,
8650 : : error);
8651 [ # # ]: 0 : if (ret)
8652 : 0 : return ret;
8653 [ # # ]: 0 : last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
8654 : : MLX5_FLOW_LAYER_OUTER_L3_IPV4;
8655 : : break;
8656 : : case RTE_FLOW_ITEM_TYPE_IPV6:
8657 : 0 : tunnel |= mlx5_hw_flow_tunnel_ip_check(last_item,
8658 : : item_flags);
8659 : 0 : ret = mlx5_flow_validate_item_ipv6(dev, item,
8660 : : *item_flags,
8661 : : last_item, 0,
8662 : : &hws_nic_ipv6_mask,
8663 : : error);
8664 [ # # ]: 0 : if (ret < 0)
8665 : 0 : return ret;
8666 [ # # ]: 0 : last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
8667 : : MLX5_FLOW_LAYER_OUTER_L3_IPV6;
8668 : : break;
8669 : 0 : case RTE_FLOW_ITEM_TYPE_UDP:
8670 : 0 : ret = mlx5_flow_validate_item_udp(dev, item,
8671 : : *item_flags,
8672 : : 0xff, error);
8673 [ # # ]: 0 : if (ret)
8674 : 0 : return ret;
8675 [ # # ]: 0 : last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
8676 : : MLX5_FLOW_LAYER_OUTER_L4_UDP;
8677 : : break;
8678 : 0 : case RTE_FLOW_ITEM_TYPE_TCP:
8679 : 0 : ret = mlx5_flow_validate_item_tcp
8680 : : (dev, item, *item_flags,
8681 : : 0xff, &nic_tcp_mask, error);
8682 [ # # ]: 0 : if (ret < 0)
8683 : 0 : return ret;
8684 [ # # ]: 0 : last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
8685 : : MLX5_FLOW_LAYER_OUTER_L4_TCP;
8686 : : break;
8687 : 0 : case RTE_FLOW_ITEM_TYPE_GTP:
8688 : : gtp_item = item;
8689 : 0 : ret = mlx5_flow_dv_validate_item_gtp(dev, gtp_item,
8690 : : *item_flags, error);
8691 [ # # ]: 0 : if (ret < 0)
8692 : 0 : return ret;
8693 : : last_item = MLX5_FLOW_LAYER_GTP;
8694 : : break;
8695 : 0 : case RTE_FLOW_ITEM_TYPE_GTP_PSC:
8696 : 0 : ret = mlx5_flow_dv_validate_item_gtp_psc(dev, item,
8697 : : last_item,
8698 : : gtp_item,
8699 : : false, error);
8700 [ # # ]: 0 : if (ret < 0)
8701 : 0 : return ret;
8702 : : last_item = MLX5_FLOW_LAYER_GTP_PSC;
8703 : : break;
8704 : 0 : case RTE_FLOW_ITEM_TYPE_VXLAN:
8705 : 0 : ret = mlx5_flow_validate_item_vxlan(dev, 0, item,
8706 : : *item_flags,
8707 : : false, error);
8708 [ # # ]: 0 : if (ret < 0)
8709 : 0 : return ret;
8710 : : last_item = MLX5_FLOW_LAYER_VXLAN;
8711 : : break;
8712 : 0 : case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
8713 : 0 : ret = mlx5_flow_validate_item_vxlan_gpe(item,
8714 : : *item_flags,
8715 : : dev, error);
8716 [ # # ]: 0 : if (ret < 0)
8717 : 0 : return ret;
8718 : : last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
8719 : : break;
8720 : 0 : case RTE_FLOW_ITEM_TYPE_MPLS:
8721 : 0 : ret = mlx5_flow_validate_item_mpls(dev, item,
8722 : : *item_flags,
8723 : : last_item, error);
8724 [ # # ]: 0 : if (ret < 0)
8725 : 0 : return ret;
8726 : : last_item = MLX5_FLOW_LAYER_MPLS;
8727 : : break;
8728 : 0 : case MLX5_RTE_FLOW_ITEM_TYPE_SQ:
8729 : : case RTE_FLOW_ITEM_TYPE_TX_QUEUE:
8730 : : last_item = MLX5_FLOW_ITEM_SQ;
8731 : 0 : break;
8732 : 0 : case RTE_FLOW_ITEM_TYPE_GRE:
8733 : 0 : ret = mlx5_flow_validate_item_gre(dev, item,
8734 : : *item_flags,
8735 : : 0xff, error);
8736 [ # # ]: 0 : if (ret < 0)
8737 : 0 : return ret;
8738 : : gre_item = item;
8739 : : last_item = MLX5_FLOW_LAYER_GRE;
8740 : : break;
8741 : 0 : case RTE_FLOW_ITEM_TYPE_GRE_KEY:
8742 [ # # ]: 0 : if (!(*item_flags & MLX5_FLOW_LAYER_GRE))
8743 : 0 : return rte_flow_error_set
8744 : : (error, EINVAL,
8745 : : RTE_FLOW_ERROR_TYPE_ITEM, item, "GRE item is missing");
8746 : 0 : ret = mlx5_flow_validate_item_gre_key
8747 : : (dev, item, *item_flags, gre_item, error);
8748 [ # # ]: 0 : if (ret < 0)
8749 : 0 : return ret;
8750 : : last_item = MLX5_FLOW_LAYER_GRE_KEY;
8751 : : break;
8752 : 0 : case RTE_FLOW_ITEM_TYPE_GRE_OPTION:
8753 [ # # ]: 0 : if (!(*item_flags & MLX5_FLOW_LAYER_GRE))
8754 : 0 : return rte_flow_error_set
8755 : : (error, EINVAL,
8756 : : RTE_FLOW_ERROR_TYPE_ITEM, item, "GRE item is missing");
8757 : 0 : ret = mlx5_flow_validate_item_gre_option(dev, item,
8758 : : *item_flags,
8759 : : &flow_attr,
8760 : : gre_item,
8761 : : error);
8762 [ # # ]: 0 : if (ret < 0)
8763 : 0 : return ret;
8764 : : last_item = MLX5_FLOW_LAYER_GRE;
8765 : : break;
8766 : 0 : case RTE_FLOW_ITEM_TYPE_NVGRE:
8767 : 0 : ret = mlx5_flow_validate_item_nvgre(dev, item,
8768 : : *item_flags, 0xff,
8769 : : error);
8770 [ # # ]: 0 : if (ret)
8771 : 0 : return ret;
8772 : : last_item = MLX5_FLOW_LAYER_NVGRE;
8773 : : break;
8774 : 0 : case RTE_FLOW_ITEM_TYPE_ICMP:
8775 : 0 : ret = mlx5_flow_validate_item_icmp(dev, item,
8776 : : *item_flags, 0xff,
8777 : : error);
8778 [ # # ]: 0 : if (ret < 0)
8779 : 0 : return ret;
8780 : : last_item = MLX5_FLOW_LAYER_ICMP;
8781 : : break;
8782 : 0 : case RTE_FLOW_ITEM_TYPE_ICMP6:
8783 : 0 : ret = mlx5_flow_validate_item_icmp6(dev, item,
8784 : : *item_flags, 0xff,
8785 : : error);
8786 [ # # ]: 0 : if (ret < 0)
8787 : 0 : return ret;
8788 : : last_item = MLX5_FLOW_LAYER_ICMP6;
8789 : : break;
8790 : 0 : case RTE_FLOW_ITEM_TYPE_ICMP6_ECHO_REQUEST:
8791 : : case RTE_FLOW_ITEM_TYPE_ICMP6_ECHO_REPLY:
8792 : 0 : ret = mlx5_flow_validate_item_icmp6_echo(dev, item,
8793 : : *item_flags,
8794 : : 0xff, error);
8795 [ # # ]: 0 : if (ret < 0)
8796 : 0 : return ret;
8797 : : last_item = MLX5_FLOW_LAYER_ICMP6;
8798 : : break;
8799 : 0 : case RTE_FLOW_ITEM_TYPE_CONNTRACK:
8800 [ # # ]: 0 : if (*item_flags &
8801 : : (MLX5_FLOW_ITEM_QUOTA | MLX5_FLOW_LAYER_ASO_CT))
8802 : 0 : return rte_flow_error_set
8803 : : (error, EINVAL,
8804 : : RTE_FLOW_ERROR_TYPE_ITEM, NULL, "Only one ASO item is supported");
8805 : 0 : ret = mlx5_flow_dv_validate_item_aso_ct(dev, item,
8806 : : item_flags,
8807 : : error);
8808 [ # # ]: 0 : if (ret < 0)
8809 : 0 : return ret;
8810 : : break;
8811 : 0 : case RTE_FLOW_ITEM_TYPE_QUOTA:
8812 [ # # ]: 0 : if (*item_flags &
8813 : : (MLX5_FLOW_ITEM_METER_COLOR |
8814 : : MLX5_FLOW_LAYER_ASO_CT))
8815 : 0 : return rte_flow_error_set
8816 : : (error, EINVAL,
8817 : : RTE_FLOW_ERROR_TYPE_ITEM, NULL, "Only one ASO item is supported");
8818 : : last_item = MLX5_FLOW_ITEM_QUOTA;
8819 : : break;
8820 : 0 : case RTE_FLOW_ITEM_TYPE_ESP:
8821 : 0 : ret = mlx5_flow_os_validate_item_esp(dev, item,
8822 : : *item_flags, 0xff,
8823 : : error);
8824 [ # # ]: 0 : if (ret < 0)
8825 : 0 : return ret;
8826 : : last_item = MLX5_FLOW_ITEM_ESP;
8827 : : break;
8828 : 0 : case RTE_FLOW_ITEM_TYPE_IPV6_ROUTING_EXT:
8829 : : last_item = tunnel ?
8830 [ # # ]: 0 : MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT :
8831 : : MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT;
8832 : : break;
8833 : 0 : case RTE_FLOW_ITEM_TYPE_FLEX: {
8834 : 0 : enum rte_flow_item_flex_tunnel_mode tunnel_mode = FLEX_TUNNEL_MODE_SINGLE;
8835 : :
8836 : 0 : ret = mlx5_flex_get_tunnel_mode(item, &tunnel_mode);
8837 [ # # ]: 0 : if (ret < 0)
8838 : 0 : return rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_ITEM,
8839 : : item, "Unable to get flex item mode");
8840 [ # # ]: 0 : if (tunnel_mode == FLEX_TUNNEL_MODE_TUNNEL)
8841 : : last_item = MLX5_FLOW_ITEM_FLEX_TUNNEL;
8842 : : else
8843 : : last_item = tunnel ?
8844 [ # # ]: 0 : MLX5_FLOW_ITEM_INNER_FLEX :
8845 : : MLX5_FLOW_ITEM_OUTER_FLEX;
8846 : 0 : break;
8847 : : }
8848 : 0 : case RTE_FLOW_ITEM_TYPE_RANDOM:
8849 : : last_item = MLX5_FLOW_ITEM_RANDOM;
8850 : 0 : break;
8851 : 0 : case RTE_FLOW_ITEM_TYPE_NSH:
8852 : : last_item = MLX5_FLOW_ITEM_NSH;
8853 : : ret = mlx5_hw_validate_item_nsh(dev, item, error);
8854 [ # # ]: 0 : if (ret < 0)
8855 : 0 : return ret;
8856 : : break;
8857 : : case RTE_FLOW_ITEM_TYPE_INTEGRITY:
8858 : : /*
8859 : : * Integrity flow item validation require access to
8860 : : * both item mask and spec.
8861 : : * Current HWS model allows item mask in pattern
8862 : : * template and item spec in flow rule.
8863 : : */
8864 : : break;
8865 : 0 : case RTE_FLOW_ITEM_TYPE_ECPRI:
8866 : 0 : ret = mlx5_flow_validate_item_ecpri(dev, item, *item_flags, last_item,
8867 : : RTE_ETHER_TYPE_ECPRI,
8868 : : &hws_nic_ecpri_mask, error);
8869 [ # # ]: 0 : if (ret < 0)
8870 : 0 : return ret;
8871 : 0 : *item_flags |= MLX5_FLOW_LAYER_ECPRI;
8872 : 0 : break;
8873 : : case RTE_FLOW_ITEM_TYPE_IB_BTH:
8874 : : case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
8875 : : case RTE_FLOW_ITEM_TYPE_VOID:
8876 : : case RTE_FLOW_ITEM_TYPE_END:
8877 : : break;
8878 : 0 : default:
8879 : 0 : return rte_flow_error_set(error, EINVAL,
8880 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8881 : : NULL,
8882 : : "Unsupported item type");
8883 : : }
8884 : 0 : *item_flags |= last_item;
8885 : : }
8886 : 0 : return 1 + RTE_PTR_DIFF(item, items) / sizeof(item[0]);
8887 : : }
8888 : :
8889 : : static int
8890 : 0 : flow_hw_pattern_validate(struct rte_eth_dev *dev,
8891 : : const struct rte_flow_pattern_template_attr *attr,
8892 : : const struct rte_flow_item items[],
8893 : : uint64_t *item_flags,
8894 : : struct rte_flow_error *error)
8895 : : {
8896 : 0 : return __flow_hw_pattern_validate(dev, attr, items, item_flags, false, error);
8897 : : }
8898 : :
8899 : : /*
8900 : : * Verify that the tested flow patterns fits STE size limit in HWS group.
8901 : : *
8902 : : *
8903 : : * Return values:
8904 : : * 0 : Tested patterns fit STE size limit
8905 : : * -EINVAL : Invalid parameters detected
8906 : : * -E2BIG : Tested patterns exceed STE size limit
8907 : : */
8908 : : static int
8909 : 0 : pattern_template_validate(struct rte_eth_dev *dev,
8910 : : struct rte_flow_pattern_template *pt[],
8911 : : uint32_t pt_num,
8912 : : struct rte_flow_error *error)
8913 : : {
8914 : 0 : struct mlx5_flow_template_table_cfg tbl_cfg = {
8915 : : .attr = {
8916 : : .nb_flows = 64,
8917 : : .insertion_type = RTE_FLOW_TABLE_INSERTION_TYPE_PATTERN,
8918 : : .hash_func = RTE_FLOW_TABLE_HASH_FUNC_DEFAULT,
8919 : : .flow_attr = {
8920 : : .group = 1,
8921 : 0 : .ingress = pt[0]->attr.ingress,
8922 : 0 : .egress = pt[0]->attr.egress,
8923 : 0 : .transfer = pt[0]->attr.transfer
8924 : : }
8925 : : }
8926 : : };
8927 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
8928 : : struct rte_flow_actions_template *action_template;
8929 : : struct rte_flow_template_table *tmpl_tbl;
8930 : : int ret;
8931 : :
8932 [ # # ]: 0 : if (pt[0]->attr.ingress) {
8933 : 0 : action_template =
8934 : 0 : priv->action_template_drop[MLX5DR_TABLE_TYPE_NIC_RX];
8935 [ # # ]: 0 : } else if (pt[0]->attr.egress) {
8936 : 0 : action_template =
8937 : 0 : priv->action_template_drop[MLX5DR_TABLE_TYPE_NIC_TX];
8938 [ # # ]: 0 : } else if (pt[0]->attr.transfer) {
8939 : 0 : action_template =
8940 : 0 : priv->action_template_drop[MLX5DR_TABLE_TYPE_FDB];
8941 : : } else {
8942 : : ret = EINVAL;
8943 : 0 : goto end;
8944 : : }
8945 : :
8946 [ # # ]: 0 : if (pt[0]->item_flags & MLX5_FLOW_ITEM_COMPARE)
8947 : 0 : tbl_cfg.attr.nb_flows = 1;
8948 : 0 : tmpl_tbl = flow_hw_table_create(dev, &tbl_cfg, pt, pt_num,
8949 : : &action_template, 1, error);
8950 [ # # ]: 0 : if (tmpl_tbl) {
8951 : : ret = 0;
8952 : 0 : flow_hw_table_destroy(dev, tmpl_tbl, error);
8953 : : } else {
8954 [ # # # ]: 0 : switch (rte_errno) {
8955 : : case E2BIG:
8956 : : ret = E2BIG;
8957 : : break;
8958 : : case ENOTSUP:
8959 : : ret = EINVAL;
8960 : : break;
8961 : : default:
8962 : : ret = 0;
8963 : : break;
8964 : : }
8965 : : }
8966 : : end:
8967 : : if (ret)
8968 : 0 : rte_flow_error_set(error, ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8969 : : NULL, "failed to validate pattern template");
8970 : 0 : return -ret;
8971 : : }
8972 : :
8973 : : /**
8974 : : * Create flow item template.
8975 : : *
8976 : : * @param[in] dev
8977 : : * Pointer to the rte_eth_dev structure.
8978 : : * @param[in] attr
8979 : : * Pointer to the item template attributes.
8980 : : * @param[in] items
8981 : : * The template item pattern.
8982 : : * @param[out] error
8983 : : * Pointer to error structure.
8984 : : *
8985 : : * @return
8986 : : * Item template pointer on success, NULL otherwise and rte_errno is set.
8987 : : */
8988 : : static struct rte_flow_pattern_template *
8989 : 0 : flow_hw_pattern_template_create(struct rte_eth_dev *dev,
8990 : : const struct rte_flow_pattern_template_attr *attr,
8991 : : const struct rte_flow_item items[],
8992 : : struct rte_flow_error *error)
8993 : : {
8994 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
8995 : : struct rte_flow_pattern_template *it;
8996 : : struct rte_flow_item *copied_items = NULL;
8997 : : const struct rte_flow_item *tmpl_items;
8998 : 0 : uint64_t orig_item_nb, item_flags = 0;
8999 : 0 : struct rte_flow_item port = {
9000 : : .type = RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT,
9001 : : .mask = &rte_flow_item_ethdev_mask,
9002 : : };
9003 : 0 : struct rte_flow_item_tag tag_v = {
9004 : : .data = 0,
9005 : : .index = REG_C_0,
9006 : : };
9007 : 0 : struct rte_flow_item_tag tag_m = {
9008 : : .data = flow_hw_tx_tag_regc_mask(dev),
9009 : : .index = 0xff,
9010 : : };
9011 : 0 : struct rte_flow_item tag = {
9012 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_TAG,
9013 : : .spec = &tag_v,
9014 : : .mask = &tag_m,
9015 : : .last = NULL
9016 : : };
9017 : : int it_items_size;
9018 : : unsigned int i = 0;
9019 : : int rc;
9020 : :
9021 : : /* Validate application items only */
9022 : : rc = flow_hw_pattern_validate(dev, attr, items, &item_flags, error);
9023 [ # # ]: 0 : if (rc < 0)
9024 : : return NULL;
9025 : 0 : orig_item_nb = rc;
9026 [ # # ]: 0 : if (priv->sh->config.dv_esw_en &&
9027 : : priv->sh->config.repr_matching &&
9028 [ # # ]: 0 : attr->ingress && !attr->egress && !attr->transfer) {
9029 : 0 : copied_items = flow_hw_prepend_item(items, orig_item_nb, &port, error);
9030 [ # # ]: 0 : if (!copied_items)
9031 : : return NULL;
9032 : : tmpl_items = copied_items;
9033 [ # # ]: 0 : } else if (priv->sh->config.dv_esw_en &&
9034 : : priv->sh->config.repr_matching &&
9035 [ # # ]: 0 : !attr->ingress && attr->egress && !attr->transfer) {
9036 [ # # ]: 0 : if (item_flags & MLX5_FLOW_ITEM_SQ) {
9037 : 0 : DRV_LOG(DEBUG, "Port %u omitting implicit REG_C_0 match for egress "
9038 : : "pattern template", dev->data->port_id);
9039 : : tmpl_items = items;
9040 : 0 : goto setup_pattern_template;
9041 : : }
9042 : 0 : copied_items = flow_hw_prepend_item(items, orig_item_nb, &tag, error);
9043 [ # # ]: 0 : if (!copied_items)
9044 : : return NULL;
9045 : : tmpl_items = copied_items;
9046 : : } else {
9047 : : tmpl_items = items;
9048 : : }
9049 : 0 : setup_pattern_template:
9050 : 0 : it = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*it), 0, SOCKET_ID_ANY);
9051 [ # # ]: 0 : if (!it) {
9052 : 0 : rte_flow_error_set(error, ENOMEM,
9053 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9054 : : NULL,
9055 : : "cannot allocate item template");
9056 : 0 : goto error;
9057 : : }
9058 : 0 : it->attr = *attr;
9059 : 0 : it->item_flags = item_flags;
9060 : 0 : it->orig_item_nb = orig_item_nb;
9061 : 0 : it_items_size = rte_flow_conv(RTE_FLOW_CONV_OP_PATTERN, NULL, 0, tmpl_items, error);
9062 [ # # ]: 0 : if (it_items_size <= 0) {
9063 : 0 : rte_flow_error_set(error, ENOMEM,
9064 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9065 : : NULL,
9066 : : "Failed to determine buffer size for pattern");
9067 : 0 : goto error;
9068 : : }
9069 : 0 : it_items_size = RTE_ALIGN(it_items_size, 16);
9070 : 0 : it->items = mlx5_malloc(MLX5_MEM_ZERO, it_items_size, 0, SOCKET_ID_ANY);
9071 [ # # ]: 0 : if (it->items == NULL) {
9072 : 0 : rte_flow_error_set(error, ENOMEM,
9073 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9074 : : NULL,
9075 : : "Cannot allocate memory for pattern");
9076 : 0 : goto error;
9077 : : }
9078 : 0 : rc = rte_flow_conv(RTE_FLOW_CONV_OP_PATTERN, it->items, it_items_size, tmpl_items, error);
9079 [ # # ]: 0 : if (rc <= 0) {
9080 : 0 : rte_flow_error_set(error, ENOMEM,
9081 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9082 : : NULL,
9083 : : "Failed to store pattern");
9084 : 0 : goto error;
9085 : : }
9086 : 0 : it->mt = mlx5dr_match_template_create(tmpl_items, attr->relaxed_matching);
9087 [ # # ]: 0 : if (!it->mt) {
9088 : 0 : rte_flow_error_set(error, rte_errno,
9089 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9090 : : NULL,
9091 : : "cannot create match template");
9092 : 0 : goto error;
9093 : : }
9094 [ # # ]: 0 : if (copied_items) {
9095 [ # # ]: 0 : if (attr->ingress)
9096 : 0 : it->implicit_port = true;
9097 [ # # ]: 0 : else if (attr->egress)
9098 : 0 : it->implicit_tag = true;
9099 : 0 : mlx5_free(copied_items);
9100 : : copied_items = NULL;
9101 : : }
9102 : : /* Either inner or outer, can't both. */
9103 [ # # ]: 0 : if (it->item_flags & (MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT |
9104 : : MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT)) {
9105 [ # # ]: 0 : if (((it->item_flags & MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT) &&
9106 [ # # ]: 0 : (it->item_flags & MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT)) ||
9107 : 0 : (mlx5_alloc_srh_flex_parser(dev))) {
9108 : 0 : rte_flow_error_set(error, rte_errno,
9109 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9110 : : "cannot create IPv6 routing extension support");
9111 : 0 : goto error;
9112 : : }
9113 : : }
9114 [ # # ]: 0 : if (it->item_flags & MLX5_FLOW_ITEM_FLEX) {
9115 [ # # ]: 0 : for (i = 0; items[i].type != RTE_FLOW_ITEM_TYPE_END; i++) {
9116 : 0 : const struct rte_flow_item_flex *spec = items[i].spec;
9117 : : struct rte_flow_item_flex_handle *handle;
9118 : :
9119 [ # # ]: 0 : if (items[i].type != RTE_FLOW_ITEM_TYPE_FLEX)
9120 : 0 : continue;
9121 : 0 : handle = spec->handle;
9122 [ # # ]: 0 : if (flow_hw_flex_item_acquire(dev, handle,
9123 : 0 : &it->flex_item)) {
9124 : 0 : rte_flow_error_set(error, EINVAL,
9125 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9126 : : NULL, "cannot create hw FLEX item");
9127 : 0 : goto error;
9128 : : }
9129 : : }
9130 : : }
9131 [ # # ]: 0 : if (it->item_flags & MLX5_FLOW_LAYER_GENEVE_OPT) {
9132 [ # # ]: 0 : for (i = 0; items[i].type != RTE_FLOW_ITEM_TYPE_END; i++) {
9133 : 0 : const struct rte_flow_item_geneve_opt *spec =
9134 : : items[i].spec;
9135 : :
9136 [ # # ]: 0 : if (items[i].type != RTE_FLOW_ITEM_TYPE_GENEVE_OPT)
9137 : 0 : continue;
9138 [ # # ]: 0 : if (mlx5_geneve_tlv_option_register(priv, spec,
9139 : 0 : &it->geneve_opt_mng)) {
9140 : 0 : rte_flow_error_set(error, EINVAL,
9141 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9142 : : NULL, "cannot register GENEVE TLV option");
9143 : 0 : goto error;
9144 : : }
9145 : : }
9146 : : }
9147 : 0 : rte_atomic_fetch_add_explicit(&it->refcnt, 1, rte_memory_order_relaxed);
9148 : 0 : rc = pattern_template_validate(dev, &it, 1, error);
9149 [ # # ]: 0 : if (rc)
9150 : 0 : goto error;
9151 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->flow_hw_itt, it, next);
9152 : 0 : return it;
9153 : 0 : error:
9154 [ # # ]: 0 : if (it) {
9155 [ # # ]: 0 : if (it->flex_item)
9156 : 0 : flow_hw_flex_item_release(dev, &it->flex_item);
9157 [ # # ]: 0 : if (it->geneve_opt_mng.nb_options)
9158 : 0 : mlx5_geneve_tlv_options_unregister(priv, &it->geneve_opt_mng);
9159 [ # # ]: 0 : if (it->mt)
9160 : 0 : claim_zero(mlx5dr_match_template_destroy(it->mt));
9161 : 0 : mlx5_free(it->items);
9162 : 0 : mlx5_free(it);
9163 : : }
9164 [ # # ]: 0 : if (copied_items)
9165 : 0 : mlx5_free(copied_items);
9166 : : return NULL;
9167 : : }
9168 : :
9169 : : /**
9170 : : * Destroy flow item template.
9171 : : *
9172 : : * @param[in] dev
9173 : : * Pointer to the rte_eth_dev structure.
9174 : : * @param[in] template
9175 : : * Pointer to the item template to be destroyed.
9176 : : * @param[out] error
9177 : : * Pointer to error structure.
9178 : : *
9179 : : * @return
9180 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
9181 : : */
9182 : : static int
9183 : 0 : flow_hw_pattern_template_destroy(struct rte_eth_dev *dev,
9184 : : struct rte_flow_pattern_template *template,
9185 : : struct rte_flow_error *error __rte_unused)
9186 : : {
9187 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
9188 : :
9189 [ # # ]: 0 : if (rte_atomic_load_explicit(&template->refcnt, rte_memory_order_relaxed) > 1) {
9190 : 0 : DRV_LOG(WARNING, "Item template %p is still in use.",
9191 : : (void *)template);
9192 : 0 : return rte_flow_error_set(error, EBUSY,
9193 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9194 : : NULL,
9195 : : "item template is in use");
9196 : : }
9197 [ # # ]: 0 : if (template->item_flags & (MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT |
9198 : : MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT))
9199 : 0 : mlx5_free_srh_flex_parser(dev);
9200 [ # # ]: 0 : LIST_REMOVE(template, next);
9201 : 0 : flow_hw_flex_item_release(dev, &template->flex_item);
9202 : 0 : mlx5_geneve_tlv_options_unregister(priv, &template->geneve_opt_mng);
9203 : 0 : claim_zero(mlx5dr_match_template_destroy(template->mt));
9204 : 0 : mlx5_free(template->items);
9205 : 0 : mlx5_free(template);
9206 : 0 : return 0;
9207 : : }
9208 : :
9209 : : /*
9210 : : * Get information about HWS pre-configurable resources.
9211 : : *
9212 : : * @param[in] dev
9213 : : * Pointer to the rte_eth_dev structure.
9214 : : * @param[out] port_info
9215 : : * Pointer to port information.
9216 : : * @param[out] queue_info
9217 : : * Pointer to queue information.
9218 : : * @param[out] error
9219 : : * Pointer to error structure.
9220 : : *
9221 : : * @return
9222 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
9223 : : */
9224 : : static int
9225 : 0 : flow_hw_info_get(struct rte_eth_dev *dev,
9226 : : struct rte_flow_port_info *port_info,
9227 : : struct rte_flow_queue_info *queue_info,
9228 : : struct rte_flow_error *error __rte_unused)
9229 : : {
9230 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
9231 : 0 : uint16_t port_id = dev->data->port_id;
9232 : : struct rte_mtr_capabilities mtr_cap;
9233 : : int ret;
9234 : :
9235 : : memset(port_info, 0, sizeof(*port_info));
9236 : : /* Queue size is unlimited from low-level. */
9237 : 0 : port_info->max_nb_queues = UINT32_MAX;
9238 : 0 : queue_info->max_size = UINT32_MAX;
9239 : :
9240 : : memset(&mtr_cap, 0, sizeof(struct rte_mtr_capabilities));
9241 : 0 : ret = rte_mtr_capabilities_get(port_id, &mtr_cap, NULL);
9242 [ # # ]: 0 : if (!ret)
9243 : 0 : port_info->max_nb_meters = mtr_cap.n_max;
9244 : 0 : port_info->max_nb_counters = priv->sh->hws_max_nb_counters;
9245 : 0 : port_info->max_nb_aging_objects = port_info->max_nb_counters;
9246 : 0 : return 0;
9247 : : }
9248 : :
9249 : : /**
9250 : : * Create group callback.
9251 : : *
9252 : : * @param[in] tool_ctx
9253 : : * Pointer to the hash list related context.
9254 : : * @param[in] cb_ctx
9255 : : * Pointer to the group creation context.
9256 : : *
9257 : : * @return
9258 : : * Group entry on success, NULL otherwise and rte_errno is set.
9259 : : */
9260 : : struct mlx5_list_entry *
9261 : 0 : flow_hw_grp_create_cb(void *tool_ctx, void *cb_ctx)
9262 : : {
9263 : : struct mlx5_dev_ctx_shared *sh = tool_ctx;
9264 : : struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9265 : 0 : struct rte_eth_dev *dev = ctx->dev;
9266 : 0 : struct rte_flow_attr *attr = (struct rte_flow_attr *)ctx->data;
9267 : 0 : uint32_t *specialize = (uint32_t *)ctx->data2;
9268 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
9269 : : bool unified_fdb = is_unified_fdb(priv);
9270 : 0 : struct mlx5dr_table_attr dr_tbl_attr = {0};
9271 : 0 : struct rte_flow_error *error = ctx->error;
9272 : : struct mlx5_flow_group *grp_data;
9273 : : struct mlx5dr_table *tbl = NULL;
9274 : : struct mlx5dr_action *jump;
9275 : : uint32_t hws_flags;
9276 : 0 : uint32_t idx = 0;
9277 [ # # # # : 0 : MKSTR(matcher_name, "%s_%s_%u_%u_matcher_list",
# # # # ]
9278 : : attr->transfer ? "FDB" : "NIC", attr->egress ? "egress" : "ingress",
9279 : : attr->group, idx);
9280 : :
9281 : 0 : grp_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_HW_GRP], &idx);
9282 [ # # ]: 0 : if (!grp_data) {
9283 : 0 : rte_flow_error_set(error, ENOMEM,
9284 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9285 : : NULL,
9286 : : "cannot allocate flow table data entry");
9287 : 0 : return NULL;
9288 : : }
9289 : 0 : dr_tbl_attr.level = attr->group;
9290 : 0 : dr_tbl_attr.type = get_mlx5dr_table_type(attr, *specialize, unified_fdb);
9291 : 0 : tbl = mlx5dr_table_create(priv->dr_ctx, &dr_tbl_attr);
9292 [ # # ]: 0 : if (!tbl)
9293 : 0 : goto error;
9294 : 0 : grp_data->tbl = tbl;
9295 [ # # ]: 0 : if (attr->group) {
9296 : 0 : hws_flags = mlx5_hw_act_dest_table_flag[dr_tbl_attr.type];
9297 : : /* For case of jump from FDB Tx to FDB Rx as it is supported now. */
9298 [ # # # # ]: 0 : if (priv->jump_fdb_rx_en &&
9299 : : dr_tbl_attr.type == MLX5DR_TABLE_TYPE_FDB_RX)
9300 : 0 : hws_flags |= MLX5DR_ACTION_FLAG_HWS_FDB_TX;
9301 : : /* Jump action be used by non-root table. */
9302 : 0 : jump = mlx5dr_action_create_dest_table
9303 : : (priv->dr_ctx, tbl,
9304 : : hws_flags);
9305 [ # # ]: 0 : if (!jump)
9306 : 0 : goto error;
9307 : 0 : grp_data->jump.hws_action = jump;
9308 : : /* Jump action be used by root table. */
9309 : 0 : jump = mlx5dr_action_create_dest_table
9310 : : (priv->dr_ctx, tbl,
9311 : : mlx5_hw_act_flag[MLX5_HW_ACTION_FLAG_ROOT]
9312 : 0 : [dr_tbl_attr.type]);
9313 [ # # ]: 0 : if (!jump)
9314 : 0 : goto error;
9315 : 0 : grp_data->jump.root_action = jump;
9316 : : }
9317 : :
9318 : 0 : grp_data->matchers = mlx5_list_create(matcher_name, sh, true,
9319 : : flow_matcher_create_cb,
9320 : : flow_matcher_match_cb,
9321 : : flow_matcher_remove_cb,
9322 : : flow_matcher_clone_cb,
9323 : : flow_matcher_clone_free_cb);
9324 : 0 : grp_data->dev = dev;
9325 : 0 : grp_data->idx = idx;
9326 : 0 : grp_data->group_id = attr->group;
9327 : 0 : grp_data->type = dr_tbl_attr.type;
9328 : 0 : return &grp_data->entry;
9329 : 0 : error:
9330 [ # # ]: 0 : if (grp_data->jump.root_action)
9331 : 0 : mlx5dr_action_destroy(grp_data->jump.root_action);
9332 [ # # ]: 0 : if (grp_data->jump.hws_action)
9333 : 0 : mlx5dr_action_destroy(grp_data->jump.hws_action);
9334 [ # # ]: 0 : if (tbl)
9335 : 0 : mlx5dr_table_destroy(tbl);
9336 [ # # ]: 0 : if (idx)
9337 : 0 : mlx5_ipool_free(sh->ipool[MLX5_IPOOL_HW_GRP], idx);
9338 : 0 : rte_flow_error_set(error, ENOMEM,
9339 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9340 : : NULL,
9341 : : "cannot allocate flow dr table");
9342 : 0 : return NULL;
9343 : : }
9344 : :
9345 : : /**
9346 : : * Remove group callback.
9347 : : *
9348 : : * @param[in] tool_ctx
9349 : : * Pointer to the hash list related context.
9350 : : * @param[in] entry
9351 : : * Pointer to the entry to be removed.
9352 : : */
9353 : : void
9354 : 0 : flow_hw_grp_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
9355 : : {
9356 : : struct mlx5_dev_ctx_shared *sh = tool_ctx;
9357 : : struct mlx5_flow_group *grp_data =
9358 : : container_of(entry, struct mlx5_flow_group, entry);
9359 : :
9360 : : MLX5_ASSERT(entry && sh);
9361 : : /* To use the wrapper glue functions instead. */
9362 [ # # ]: 0 : if (grp_data->jump.hws_action)
9363 : 0 : mlx5dr_action_destroy(grp_data->jump.hws_action);
9364 [ # # ]: 0 : if (grp_data->jump.root_action)
9365 : 0 : mlx5dr_action_destroy(grp_data->jump.root_action);
9366 : 0 : mlx5_list_destroy(grp_data->matchers);
9367 : 0 : mlx5dr_table_destroy(grp_data->tbl);
9368 : 0 : mlx5_ipool_free(sh->ipool[MLX5_IPOOL_HW_GRP], grp_data->idx);
9369 : 0 : }
9370 : :
9371 : : /**
9372 : : * Match group callback.
9373 : : *
9374 : : * @param[in] tool_ctx
9375 : : * Pointer to the hash list related context.
9376 : : * @param[in] entry
9377 : : * Pointer to the group to be matched.
9378 : : * @param[in] cb_ctx
9379 : : * Pointer to the group matching context.
9380 : : *
9381 : : * @return
9382 : : * 0 on matched, 1 on miss matched.
9383 : : */
9384 : : int
9385 : 0 : flow_hw_grp_match_cb(void *tool_ctx __rte_unused, struct mlx5_list_entry *entry,
9386 : : void *cb_ctx)
9387 : : {
9388 : : struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9389 : : struct mlx5_flow_group *grp_data =
9390 : : container_of(entry, struct mlx5_flow_group, entry);
9391 : 0 : struct rte_flow_attr *attr =
9392 : : (struct rte_flow_attr *)ctx->data;
9393 : :
9394 : 0 : return (grp_data->dev != ctx->dev) ||
9395 [ # # ]: 0 : (grp_data->group_id != attr->group) ||
9396 [ # # # # ]: 0 : ((grp_data->type < MLX5DR_TABLE_TYPE_FDB) &&
9397 [ # # ]: 0 : attr->transfer) ||
9398 [ # # ]: 0 : ((grp_data->type != MLX5DR_TABLE_TYPE_NIC_TX) &&
9399 [ # # # # ]: 0 : attr->egress) ||
9400 [ # # ]: 0 : ((grp_data->type != MLX5DR_TABLE_TYPE_NIC_RX) &&
9401 : : attr->ingress);
9402 : : }
9403 : :
9404 : : /**
9405 : : * Clone group entry callback.
9406 : : *
9407 : : * @param[in] tool_ctx
9408 : : * Pointer to the hash list related context.
9409 : : * @param[in] entry
9410 : : * Pointer to the group to be matched.
9411 : : * @param[in] cb_ctx
9412 : : * Pointer to the group matching context.
9413 : : *
9414 : : * @return
9415 : : * 0 on matched, 1 on miss matched.
9416 : : */
9417 : : struct mlx5_list_entry *
9418 : 0 : flow_hw_grp_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
9419 : : void *cb_ctx)
9420 : : {
9421 : : struct mlx5_dev_ctx_shared *sh = tool_ctx;
9422 : : struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9423 : : struct mlx5_flow_group *grp_data;
9424 : 0 : struct rte_flow_error *error = ctx->error;
9425 : 0 : uint32_t idx = 0;
9426 : :
9427 : 0 : grp_data = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_HW_GRP], &idx);
9428 [ # # ]: 0 : if (!grp_data) {
9429 : 0 : rte_flow_error_set(error, ENOMEM,
9430 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9431 : : NULL,
9432 : : "cannot allocate flow table data entry");
9433 : 0 : return NULL;
9434 : : }
9435 : : memcpy(grp_data, oentry, sizeof(*grp_data));
9436 : 0 : grp_data->idx = idx;
9437 : 0 : return &grp_data->entry;
9438 : : }
9439 : :
9440 : : /**
9441 : : * Free cloned group entry callback.
9442 : : *
9443 : : * @param[in] tool_ctx
9444 : : * Pointer to the hash list related context.
9445 : : * @param[in] entry
9446 : : * Pointer to the group to be freed.
9447 : : */
9448 : : void
9449 : 0 : flow_hw_grp_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
9450 : : {
9451 : : struct mlx5_dev_ctx_shared *sh = tool_ctx;
9452 : : struct mlx5_flow_group *grp_data =
9453 : : container_of(entry, struct mlx5_flow_group, entry);
9454 : :
9455 : 0 : mlx5_ipool_free(sh->ipool[MLX5_IPOOL_HW_GRP], grp_data->idx);
9456 : 0 : }
9457 : :
9458 : : /**
9459 : : * Create and cache a vport action for given @p dev port. vport actions
9460 : : * cache is used in HWS with FDB flows.
9461 : : *
9462 : : * This function does not create any function if proxy port for @p dev port
9463 : : * was not configured for HW Steering.
9464 : : *
9465 : : * This function assumes that E-Switch is enabled and PMD is running with
9466 : : * HW Steering configured.
9467 : : *
9468 : : * @param dev
9469 : : * Pointer to Ethernet device which will be the action destination.
9470 : : *
9471 : : * @return
9472 : : * 0 on success, positive value otherwise.
9473 : : */
9474 : : int
9475 : 0 : flow_hw_create_vport_action(struct rte_eth_dev *dev)
9476 : : {
9477 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
9478 : : struct rte_eth_dev *proxy_dev;
9479 : : struct mlx5_priv *proxy_priv;
9480 : 0 : uint16_t port_id = dev->data->port_id;
9481 : 0 : uint16_t proxy_port_id = port_id;
9482 : : int ret;
9483 : :
9484 : 0 : ret = mlx5_flow_pick_transfer_proxy(dev, &proxy_port_id, NULL);
9485 [ # # ]: 0 : if (ret)
9486 : : return ret;
9487 : 0 : proxy_dev = &rte_eth_devices[proxy_port_id];
9488 : 0 : proxy_priv = proxy_dev->data->dev_private;
9489 [ # # ]: 0 : if (!proxy_priv->hw_vport)
9490 : : return 0;
9491 [ # # ]: 0 : if (proxy_priv->hw_vport[port_id]) {
9492 : 0 : DRV_LOG(ERR, "port %u HWS vport action already created",
9493 : : port_id);
9494 : 0 : return -EINVAL;
9495 : : }
9496 [ # # ]: 0 : proxy_priv->hw_vport[port_id] = mlx5dr_action_create_dest_vport
9497 : : (proxy_priv->dr_ctx, priv->dev_port,
9498 : : is_unified_fdb(priv) ?
9499 : : (MLX5DR_ACTION_FLAG_HWS_FDB_RX |
9500 : : MLX5DR_ACTION_FLAG_HWS_FDB_TX |
9501 : : MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED) :
9502 : : MLX5DR_ACTION_FLAG_HWS_FDB);
9503 [ # # ]: 0 : if (!proxy_priv->hw_vport[port_id]) {
9504 : 0 : DRV_LOG(ERR, "port %u unable to create HWS vport action",
9505 : : port_id);
9506 : 0 : return -EINVAL;
9507 : : }
9508 : : return 0;
9509 : : }
9510 : :
9511 : : /**
9512 : : * Destroys the vport action associated with @p dev device
9513 : : * from actions' cache.
9514 : : *
9515 : : * This function does not destroy any action if there is no action cached
9516 : : * for @p dev or proxy port was not configured for HW Steering.
9517 : : *
9518 : : * This function assumes that E-Switch is enabled and PMD is running with
9519 : : * HW Steering configured.
9520 : : *
9521 : : * @param dev
9522 : : * Pointer to Ethernet device which will be the action destination.
9523 : : */
9524 : : void
9525 : 0 : flow_hw_destroy_vport_action(struct rte_eth_dev *dev)
9526 : : {
9527 : : struct rte_eth_dev *proxy_dev;
9528 : : struct mlx5_priv *proxy_priv;
9529 : 0 : uint16_t port_id = dev->data->port_id;
9530 : 0 : uint16_t proxy_port_id = port_id;
9531 : :
9532 [ # # ]: 0 : if (mlx5_flow_pick_transfer_proxy(dev, &proxy_port_id, NULL))
9533 : 0 : return;
9534 : 0 : proxy_dev = &rte_eth_devices[proxy_port_id];
9535 : 0 : proxy_priv = proxy_dev->data->dev_private;
9536 [ # # # # ]: 0 : if (!proxy_priv->hw_vport || !proxy_priv->hw_vport[port_id])
9537 : : return;
9538 : 0 : mlx5dr_action_destroy(proxy_priv->hw_vport[port_id]);
9539 : 0 : proxy_priv->hw_vport[port_id] = NULL;
9540 : : }
9541 : :
9542 : : static int
9543 : 0 : flow_hw_create_vport_actions(struct mlx5_priv *priv)
9544 : : {
9545 : : uint16_t port_id;
9546 : :
9547 : : MLX5_ASSERT(!priv->hw_vport);
9548 : : bool unified_fdb = is_unified_fdb(priv);
9549 : 0 : priv->hw_vport = mlx5_malloc(MLX5_MEM_ZERO,
9550 : : sizeof(*priv->hw_vport) * RTE_MAX_ETHPORTS,
9551 : : 0, SOCKET_ID_ANY);
9552 [ # # ]: 0 : if (!priv->hw_vport)
9553 : : return -ENOMEM;
9554 : 0 : DRV_LOG(DEBUG, "port %u :: creating vport actions", priv->dev_data->port_id);
9555 : 0 : DRV_LOG(DEBUG, "port %u :: domain_id=%u", priv->dev_data->port_id, priv->domain_id);
9556 [ # # ]: 0 : MLX5_ETH_FOREACH_DEV(port_id, NULL) {
9557 : 0 : struct mlx5_priv *port_priv = rte_eth_devices[port_id].data->dev_private;
9558 : :
9559 [ # # ]: 0 : if (!port_priv ||
9560 [ # # ]: 0 : port_priv->domain_id != priv->domain_id)
9561 : 0 : continue;
9562 : 0 : DRV_LOG(DEBUG, "port %u :: for port_id=%u, calling mlx5dr_action_create_dest_vport() with ibport=%u",
9563 : : priv->dev_data->port_id, port_id, port_priv->dev_port);
9564 [ # # ]: 0 : priv->hw_vport[port_id] = mlx5dr_action_create_dest_vport
9565 : : (priv->dr_ctx, port_priv->dev_port,
9566 : : unified_fdb ?
9567 : : (MLX5DR_ACTION_FLAG_HWS_FDB_RX |
9568 : : MLX5DR_ACTION_FLAG_HWS_FDB_TX |
9569 : : MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED) :
9570 : : MLX5DR_ACTION_FLAG_HWS_FDB);
9571 : 0 : DRV_LOG(DEBUG, "port %u :: priv->hw_vport[%u]=%p",
9572 : : priv->dev_data->port_id, port_id, (void *)priv->hw_vport[port_id]);
9573 [ # # ]: 0 : if (!priv->hw_vport[port_id])
9574 : : return -EINVAL;
9575 : : }
9576 : : return 0;
9577 : : }
9578 : :
9579 : : static void
9580 : 0 : flow_hw_free_vport_actions(struct mlx5_priv *priv)
9581 : : {
9582 : : uint16_t port_id;
9583 : :
9584 [ # # ]: 0 : if (!priv->hw_vport)
9585 : : return;
9586 [ # # ]: 0 : for (port_id = 0; port_id < RTE_MAX_ETHPORTS; ++port_id)
9587 [ # # ]: 0 : if (priv->hw_vport[port_id])
9588 : 0 : mlx5dr_action_destroy(priv->hw_vport[port_id]);
9589 : 0 : mlx5_free(priv->hw_vport);
9590 : 0 : priv->hw_vport = NULL;
9591 : : }
9592 : :
9593 : : #ifdef HAVE_MLX5DV_DR_ACTION_CREATE_DEST_ROOT_TABLE
9594 : : static __rte_always_inline void
9595 : : _create_send_to_kernel_actions(struct mlx5_priv *priv, int type)
9596 : : {
9597 : : int action_flag;
9598 : :
9599 : : action_flag = mlx5_hw_act_flag[1][type];
9600 : : priv->hw_send_to_kernel[type] =
9601 : : mlx5dr_action_create_dest_root(priv->dr_ctx,
9602 : : MLX5_HW_LOWEST_PRIO_ROOT,
9603 : : action_flag);
9604 : : if (!priv->hw_send_to_kernel[type])
9605 : : DRV_LOG(WARNING, "Unable to create HWS send to kernel action");
9606 : : }
9607 : : #endif
9608 : :
9609 : : static void
9610 : : flow_hw_create_send_to_kernel_actions(__rte_unused struct mlx5_priv *priv,
9611 : : __rte_unused bool is_proxy)
9612 : : {
9613 : : #ifdef HAVE_MLX5DV_DR_ACTION_CREATE_DEST_ROOT_TABLE
9614 : : int i, from, to;
9615 : : bool unified_fdb = is_unified_fdb(priv);
9616 : :
9617 : : for (i = MLX5DR_TABLE_TYPE_NIC_RX; i <= MLX5DR_TABLE_TYPE_NIC_TX; i++)
9618 : : _create_send_to_kernel_actions(priv, i);
9619 : :
9620 : : if (is_proxy) {
9621 : : from = unified_fdb ? MLX5DR_TABLE_TYPE_FDB_RX : MLX5DR_TABLE_TYPE_FDB;
9622 : : to = unified_fdb ? MLX5DR_TABLE_TYPE_FDB_UNIFIED : MLX5DR_TABLE_TYPE_FDB;
9623 : : for (i = from; i <= to; i++)
9624 : : _create_send_to_kernel_actions(priv, i);
9625 : : }
9626 : : #endif
9627 : : }
9628 : :
9629 : : static void
9630 : 0 : flow_hw_destroy_send_to_kernel_action(struct mlx5_priv *priv)
9631 : : {
9632 : : int i;
9633 : :
9634 [ # # ]: 0 : for (i = MLX5DR_TABLE_TYPE_NIC_RX; i < MLX5DR_TABLE_TYPE_MAX; i++) {
9635 [ # # ]: 0 : if (priv->hw_send_to_kernel[i]) {
9636 : 0 : mlx5dr_action_destroy(priv->hw_send_to_kernel[i]);
9637 : 0 : priv->hw_send_to_kernel[i] = NULL;
9638 : : }
9639 : : }
9640 : 0 : }
9641 : :
9642 : : static bool
9643 : : flow_hw_should_create_nat64_actions(struct mlx5_priv *priv)
9644 : : {
9645 : : int i;
9646 : :
9647 : : /* Check if all registers are available. */
9648 [ # # ]: 0 : for (i = 0; i < MLX5_FLOW_NAT64_REGS_MAX; ++i)
9649 [ # # ]: 0 : if (priv->sh->registers.nat64_regs[i] == REG_NON)
9650 : : return false;
9651 : :
9652 : : return true;
9653 : : }
9654 : :
9655 : : static void
9656 : 0 : flow_hw_destroy_nat64_actions(struct mlx5_priv *priv)
9657 : : {
9658 : : uint32_t i;
9659 : :
9660 [ # # ]: 0 : for (i = MLX5DR_TABLE_TYPE_NIC_RX; i < MLX5DR_TABLE_TYPE_MAX; i++) {
9661 [ # # ]: 0 : if (priv->action_nat64[i][RTE_FLOW_NAT64_6TO4]) {
9662 : 0 : (void)mlx5dr_action_destroy(priv->action_nat64[i][RTE_FLOW_NAT64_6TO4]);
9663 : 0 : priv->action_nat64[i][RTE_FLOW_NAT64_6TO4] = NULL;
9664 : : }
9665 [ # # ]: 0 : if (priv->action_nat64[i][RTE_FLOW_NAT64_4TO6]) {
9666 : 0 : (void)mlx5dr_action_destroy(priv->action_nat64[i][RTE_FLOW_NAT64_4TO6]);
9667 : 0 : priv->action_nat64[i][RTE_FLOW_NAT64_4TO6] = NULL;
9668 : : }
9669 : : }
9670 : 0 : }
9671 : :
9672 : : static int
9673 : 0 : _create_nat64_actions(struct mlx5_priv *priv,
9674 : : struct mlx5dr_action_nat64_attr *attr,
9675 : : int type,
9676 : : struct rte_flow_error *error)
9677 : : {
9678 : 0 : const uint32_t flags[MLX5DR_TABLE_TYPE_MAX] = {
9679 : : MLX5DR_ACTION_FLAG_HWS_RX | MLX5DR_ACTION_FLAG_SHARED,
9680 : : MLX5DR_ACTION_FLAG_HWS_TX | MLX5DR_ACTION_FLAG_SHARED,
9681 : : MLX5DR_ACTION_FLAG_HWS_FDB | MLX5DR_ACTION_FLAG_SHARED,
9682 : : MLX5DR_ACTION_FLAG_HWS_FDB_RX | MLX5DR_ACTION_FLAG_SHARED,
9683 : : MLX5DR_ACTION_FLAG_HWS_FDB_TX | MLX5DR_ACTION_FLAG_SHARED,
9684 : : MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED | MLX5DR_ACTION_FLAG_SHARED,
9685 : : };
9686 : : struct mlx5dr_action *act;
9687 : :
9688 : 0 : attr->flags = (enum mlx5dr_action_nat64_flags)
9689 : : (MLX5DR_ACTION_NAT64_V6_TO_V4 | MLX5DR_ACTION_NAT64_BACKUP_ADDR);
9690 : 0 : act = mlx5dr_action_create_nat64(priv->dr_ctx, attr, flags[type]);
9691 [ # # ]: 0 : if (!act)
9692 : 0 : return rte_flow_error_set(error, rte_errno,
9693 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9694 : : "Failed to create v6 to v4 action.");
9695 : 0 : priv->action_nat64[type][RTE_FLOW_NAT64_6TO4] = act;
9696 : 0 : attr->flags = (enum mlx5dr_action_nat64_flags)
9697 : : (MLX5DR_ACTION_NAT64_V4_TO_V6 | MLX5DR_ACTION_NAT64_BACKUP_ADDR);
9698 : 0 : act = mlx5dr_action_create_nat64(priv->dr_ctx, attr, flags[type]);
9699 [ # # ]: 0 : if (!act)
9700 : 0 : return rte_flow_error_set(error, rte_errno,
9701 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9702 : : "Failed to create v4 to v6 action.");
9703 : 0 : priv->action_nat64[type][RTE_FLOW_NAT64_4TO6] = act;
9704 : 0 : return 0;
9705 : : }
9706 : :
9707 : : static int
9708 : 0 : flow_hw_create_nat64_actions(struct mlx5_priv *priv, struct rte_flow_error *error)
9709 : : {
9710 : : struct mlx5dr_action_nat64_attr attr;
9711 : : uint8_t regs[MLX5_FLOW_NAT64_REGS_MAX];
9712 : : uint32_t i, from, to;
9713 : : int rc;
9714 : : bool unified_fdb = is_unified_fdb(priv);
9715 : :
9716 : 0 : attr.registers = regs;
9717 : : /* Try to use 3 registers by default. */
9718 : 0 : attr.num_of_registers = MLX5_FLOW_NAT64_REGS_MAX;
9719 [ # # ]: 0 : for (i = 0; i < MLX5_FLOW_NAT64_REGS_MAX; i++) {
9720 : : MLX5_ASSERT(priv->sh->registers.nat64_regs[i] != REG_NON);
9721 : 0 : regs[i] = mlx5_convert_reg_to_field(priv->sh->registers.nat64_regs[i]);
9722 : : }
9723 [ # # ]: 0 : for (i = MLX5DR_TABLE_TYPE_NIC_RX; i <= MLX5DR_TABLE_TYPE_NIC_TX; i++) {
9724 : 0 : rc = _create_nat64_actions(priv, &attr, i, error);
9725 [ # # ]: 0 : if (rc)
9726 : 0 : return rc;
9727 : : }
9728 [ # # ]: 0 : if (priv->sh->config.dv_esw_en) {
9729 [ # # ]: 0 : from = unified_fdb ? MLX5DR_TABLE_TYPE_FDB_RX :
9730 : : MLX5DR_TABLE_TYPE_FDB;
9731 [ # # ]: 0 : to = unified_fdb ? MLX5DR_TABLE_TYPE_FDB_UNIFIED :
9732 : : MLX5DR_TABLE_TYPE_FDB;
9733 : :
9734 [ # # ]: 0 : for (i = from; i <= to; i++) {
9735 : 0 : rc = _create_nat64_actions(priv, &attr, i, error);
9736 [ # # ]: 0 : if (rc)
9737 : 0 : return rc;
9738 : : }
9739 : : }
9740 : : return 0;
9741 : : }
9742 : :
9743 : : /**
9744 : : * Create an egress pattern template matching on source SQ.
9745 : : *
9746 : : * @param dev
9747 : : * Pointer to Ethernet device.
9748 : : * @param[out] error
9749 : : * Pointer to error structure.
9750 : : *
9751 : : * @return
9752 : : * Pointer to pattern template on success. NULL otherwise, and rte_errno is set.
9753 : : */
9754 : : static struct rte_flow_pattern_template *
9755 : 0 : flow_hw_create_tx_repr_sq_pattern_tmpl(struct rte_eth_dev *dev, struct rte_flow_error *error)
9756 : : {
9757 : 0 : struct rte_flow_pattern_template_attr attr = {
9758 : : .relaxed_matching = 0,
9759 : : .egress = 1,
9760 : : };
9761 : 0 : struct mlx5_rte_flow_item_sq sq_mask = {
9762 : : .queue = UINT32_MAX,
9763 : : };
9764 : 0 : struct rte_flow_item items[] = {
9765 : : {
9766 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_SQ,
9767 : : .mask = &sq_mask,
9768 : : },
9769 : : {
9770 : : .type = RTE_FLOW_ITEM_TYPE_END,
9771 : : },
9772 : : };
9773 : :
9774 : 0 : return flow_hw_pattern_template_create(dev, &attr, items, error);
9775 : : }
9776 : :
9777 : : static __rte_always_inline uint32_t
9778 : : flow_hw_tx_tag_regc_mask(struct rte_eth_dev *dev)
9779 : : {
9780 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
9781 : 0 : uint32_t mask = priv->sh->dv_regc0_mask;
9782 : :
9783 : : /* Mask is verified during device initialization. Sanity checking here. */
9784 : : MLX5_ASSERT(mask != 0);
9785 : : /*
9786 : : * Availability of sufficient number of bits in REG_C_0 is verified on initialization.
9787 : : * Sanity checking here.
9788 : : */
9789 : : MLX5_ASSERT(rte_popcount32(mask) >= rte_popcount32(priv->vport_meta_mask));
9790 : : return mask;
9791 : : }
9792 : :
9793 : : static __rte_always_inline uint32_t
9794 : : flow_hw_tx_tag_regc_value(struct rte_eth_dev *dev)
9795 : : {
9796 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
9797 : : uint32_t tag;
9798 : :
9799 : : /* Mask is verified during device initialization. Sanity checking here. */
9800 : : MLX5_ASSERT(priv->vport_meta_mask != 0);
9801 [ # # ]: 0 : tag = priv->vport_meta_tag >> (rte_bsf32(priv->vport_meta_mask));
9802 : : /*
9803 : : * Availability of sufficient number of bits in REG_C_0 is verified on initialization.
9804 : : * Sanity checking here.
9805 : : */
9806 : : MLX5_ASSERT((tag & priv->sh->dv_regc0_mask) == tag);
9807 : : return tag;
9808 : : }
9809 : :
9810 : : static void
9811 : : flow_hw_update_action_mask(struct rte_flow_action *action,
9812 : : struct rte_flow_action *mask,
9813 : : enum rte_flow_action_type type,
9814 : : void *conf_v,
9815 : : void *conf_m)
9816 : : {
9817 : 0 : action->type = type;
9818 : 0 : action->conf = conf_v;
9819 : 0 : mask->type = type;
9820 : 0 : mask->conf = conf_m;
9821 : : }
9822 : :
9823 : : /**
9824 : : * Create an egress actions template with MODIFY_FIELD action for setting unused REG_C_0 bits
9825 : : * to vport tag and JUMP action to group 1.
9826 : : *
9827 : : * If extended metadata mode is enabled, then MODIFY_FIELD action for copying software metadata
9828 : : * to REG_C_1 is added as well.
9829 : : *
9830 : : * @param dev
9831 : : * Pointer to Ethernet device.
9832 : : * @param[out] error
9833 : : * Pointer to error structure.
9834 : : *
9835 : : * @return
9836 : : * Pointer to actions template on success. NULL otherwise, and rte_errno is set.
9837 : : */
9838 : : static struct rte_flow_actions_template *
9839 : 0 : flow_hw_create_tx_repr_tag_jump_acts_tmpl(struct rte_eth_dev *dev,
9840 : : struct rte_flow_error *error)
9841 : : {
9842 [ # # ]: 0 : uint32_t tag_mask = flow_hw_tx_tag_regc_mask(dev);
9843 : 0 : uint32_t tag_value = flow_hw_tx_tag_regc_value(dev);
9844 : 0 : struct rte_flow_actions_template_attr attr = {
9845 : : .egress = 1,
9846 : : };
9847 [ # # ]: 0 : struct rte_flow_action_modify_field set_tag_v = {
9848 : : .operation = RTE_FLOW_MODIFY_SET,
9849 : : .dst = {
9850 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
9851 : : .tag_index = REG_C_0,
9852 : : .offset = rte_bsf32(tag_mask),
9853 : : },
9854 : : .src = {
9855 : : .field = RTE_FLOW_FIELD_VALUE,
9856 : : },
9857 : : .width = rte_popcount32(tag_mask),
9858 : : };
9859 : 0 : struct rte_flow_action_modify_field set_tag_m = {
9860 : : .operation = RTE_FLOW_MODIFY_SET,
9861 : : .dst = {
9862 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
9863 : : .level = UINT8_MAX,
9864 : : .tag_index = UINT8_MAX,
9865 : : .offset = UINT32_MAX,
9866 : : },
9867 : : .src = {
9868 : : .field = RTE_FLOW_FIELD_VALUE,
9869 : : },
9870 : : .width = UINT32_MAX,
9871 : : };
9872 : 0 : struct rte_flow_action_modify_field copy_metadata_v = {
9873 : : .operation = RTE_FLOW_MODIFY_SET,
9874 : : .dst = {
9875 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
9876 : : .tag_index = REG_C_1,
9877 : : },
9878 : : .src = {
9879 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
9880 : : .tag_index = REG_A,
9881 : : },
9882 : : .width = 32,
9883 : : };
9884 : 0 : struct rte_flow_action_modify_field copy_metadata_m = {
9885 : : .operation = RTE_FLOW_MODIFY_SET,
9886 : : .dst = {
9887 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
9888 : : .level = UINT8_MAX,
9889 : : .tag_index = UINT8_MAX,
9890 : : .offset = UINT32_MAX,
9891 : : },
9892 : : .src = {
9893 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
9894 : : .level = UINT8_MAX,
9895 : : .tag_index = UINT8_MAX,
9896 : : .offset = UINT32_MAX,
9897 : : },
9898 : : .width = UINT32_MAX,
9899 : : };
9900 : 0 : struct rte_flow_action_jump jump_v = {
9901 : : .group = MLX5_HW_LOWEST_USABLE_GROUP,
9902 : : };
9903 : 0 : struct rte_flow_action_jump jump_m = {
9904 : : .group = UINT32_MAX,
9905 : : };
9906 : 0 : struct rte_flow_action actions_v[4] = { { 0 } };
9907 [ # # ]: 0 : struct rte_flow_action actions_m[4] = { { 0 } };
9908 : : unsigned int idx = 0;
9909 : :
9910 : : rte_memcpy(set_tag_v.src.value, &tag_value, sizeof(tag_value));
9911 : : rte_memcpy(set_tag_m.src.value, &tag_mask, sizeof(tag_mask));
9912 : : flow_hw_update_action_mask(&actions_v[idx], &actions_m[idx],
9913 : : RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
9914 : : &set_tag_v, &set_tag_m);
9915 : : idx++;
9916 [ # # ]: 0 : if (MLX5_SH(dev)->config.dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS) {
9917 : : flow_hw_update_action_mask(&actions_v[idx], &actions_m[idx],
9918 : : RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
9919 : : ©_metadata_v, ©_metadata_m);
9920 : : idx++;
9921 : : }
9922 : : flow_hw_update_action_mask(&actions_v[idx], &actions_m[idx], RTE_FLOW_ACTION_TYPE_JUMP,
9923 : : &jump_v, &jump_m);
9924 : 0 : idx++;
9925 : : flow_hw_update_action_mask(&actions_v[idx], &actions_m[idx], RTE_FLOW_ACTION_TYPE_END,
9926 : : NULL, NULL);
9927 : : idx++;
9928 : : MLX5_ASSERT(idx <= RTE_DIM(actions_v));
9929 : 0 : return flow_hw_actions_template_create(dev, &attr, actions_v, actions_m, error);
9930 : : }
9931 : :
9932 : : static void
9933 : 0 : flow_hw_cleanup_tx_repr_tagging(struct rte_eth_dev *dev)
9934 : : {
9935 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
9936 : :
9937 [ # # ]: 0 : if (priv->hw_tx_repr_tagging_tbl) {
9938 : 0 : flow_hw_table_destroy(dev, priv->hw_tx_repr_tagging_tbl, NULL);
9939 : 0 : priv->hw_tx_repr_tagging_tbl = NULL;
9940 : : }
9941 [ # # ]: 0 : if (priv->hw_tx_repr_tagging_at) {
9942 : 0 : flow_hw_actions_template_destroy(dev, priv->hw_tx_repr_tagging_at, NULL);
9943 : 0 : priv->hw_tx_repr_tagging_at = NULL;
9944 : : }
9945 [ # # ]: 0 : if (priv->hw_tx_repr_tagging_pt) {
9946 : 0 : flow_hw_pattern_template_destroy(dev, priv->hw_tx_repr_tagging_pt, NULL);
9947 : 0 : priv->hw_tx_repr_tagging_pt = NULL;
9948 : : }
9949 : 0 : }
9950 : :
9951 : : /**
9952 : : * Setup templates and table used to create default Tx flow rules. These default rules
9953 : : * allow for matching Tx representor traffic using a vport tag placed in unused bits of
9954 : : * REG_C_0 register.
9955 : : *
9956 : : * @param dev
9957 : : * Pointer to Ethernet device.
9958 : : * @param[out] error
9959 : : * Pointer to error structure.
9960 : : *
9961 : : * @return
9962 : : * 0 on success, negative errno value otherwise.
9963 : : */
9964 : : static int
9965 : 0 : flow_hw_setup_tx_repr_tagging(struct rte_eth_dev *dev, struct rte_flow_error *error)
9966 : : {
9967 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
9968 : 0 : struct rte_flow_template_table_attr attr = {
9969 : : .flow_attr = {
9970 : : .group = 0,
9971 : : .priority = MLX5_HW_LOWEST_PRIO_ROOT,
9972 : : .egress = 1,
9973 : : },
9974 : : .nb_flows = MLX5_HW_CTRL_FLOW_NB_RULES,
9975 : : };
9976 : 0 : struct mlx5_flow_template_table_cfg cfg = {
9977 : : .attr = attr,
9978 : : .external = false,
9979 : : };
9980 : :
9981 : : MLX5_ASSERT(priv->sh->config.dv_esw_en);
9982 : : MLX5_ASSERT(priv->sh->config.repr_matching);
9983 : 0 : priv->hw_tx_repr_tagging_pt =
9984 : 0 : flow_hw_create_tx_repr_sq_pattern_tmpl(dev, error);
9985 [ # # ]: 0 : if (!priv->hw_tx_repr_tagging_pt)
9986 : 0 : goto err;
9987 : 0 : priv->hw_tx_repr_tagging_at =
9988 : 0 : flow_hw_create_tx_repr_tag_jump_acts_tmpl(dev, error);
9989 [ # # ]: 0 : if (!priv->hw_tx_repr_tagging_at)
9990 : 0 : goto err;
9991 : 0 : priv->hw_tx_repr_tagging_tbl = flow_hw_table_create(dev, &cfg,
9992 : : &priv->hw_tx_repr_tagging_pt, 1,
9993 : : &priv->hw_tx_repr_tagging_at, 1,
9994 : : error);
9995 [ # # ]: 0 : if (!priv->hw_tx_repr_tagging_tbl)
9996 : 0 : goto err;
9997 : : return 0;
9998 : 0 : err:
9999 : 0 : flow_hw_cleanup_tx_repr_tagging(dev);
10000 : 0 : return -rte_errno;
10001 : : }
10002 : :
10003 : : static uint32_t
10004 : : flow_hw_esw_mgr_regc_marker_mask(struct rte_eth_dev *dev)
10005 : : {
10006 : 0 : uint32_t mask = MLX5_SH(dev)->dv_regc0_mask;
10007 : :
10008 : : /* Mask is verified during device initialization. */
10009 : : MLX5_ASSERT(mask != 0);
10010 : : return mask;
10011 : : }
10012 : :
10013 : : static uint32_t
10014 : : flow_hw_esw_mgr_regc_marker(struct rte_eth_dev *dev)
10015 : : {
10016 : 0 : uint32_t mask = MLX5_SH(dev)->dv_regc0_mask;
10017 : :
10018 : : /* Mask is verified during device initialization. */
10019 : : MLX5_ASSERT(mask != 0);
10020 : 0 : return RTE_BIT32(rte_bsf32(mask));
10021 : : }
10022 : :
10023 : : /**
10024 : : * Creates a flow pattern template used to match on E-Switch Manager.
10025 : : * This template is used to set up a table for SQ miss default flow.
10026 : : *
10027 : : * @param dev
10028 : : * Pointer to Ethernet device.
10029 : : * @param error
10030 : : * Pointer to error structure.
10031 : : *
10032 : : * @return
10033 : : * Pointer to flow pattern template on success, NULL otherwise.
10034 : : */
10035 : : static struct rte_flow_pattern_template *
10036 : 0 : flow_hw_create_ctrl_esw_mgr_pattern_template(struct rte_eth_dev *dev,
10037 : : struct rte_flow_error *error)
10038 : : {
10039 : 0 : struct rte_flow_pattern_template_attr attr = {
10040 : : .relaxed_matching = 0,
10041 : : .transfer = 1,
10042 : : };
10043 : 0 : struct rte_flow_item_ethdev port_spec = {
10044 : : .port_id = MLX5_REPRESENTED_PORT_ESW_MGR,
10045 : : };
10046 : 0 : struct rte_flow_item_ethdev port_mask = {
10047 : : .port_id = UINT16_MAX,
10048 : : };
10049 : 0 : struct mlx5_rte_flow_item_sq sq_mask = {
10050 : : .queue = UINT32_MAX,
10051 : : };
10052 : 0 : struct rte_flow_item items[] = {
10053 : : {
10054 : : .type = RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT,
10055 : : .spec = &port_spec,
10056 : : .mask = &port_mask,
10057 : : },
10058 : : {
10059 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_SQ,
10060 : : .mask = &sq_mask,
10061 : : },
10062 : : {
10063 : : .type = RTE_FLOW_ITEM_TYPE_END,
10064 : : },
10065 : : };
10066 : :
10067 : 0 : return flow_hw_pattern_template_create(dev, &attr, items, error);
10068 : : }
10069 : :
10070 : : /**
10071 : : * Creates a flow pattern template used to match REG_C_0 and a SQ.
10072 : : * Matching on REG_C_0 is set up to match on all bits usable by user-space.
10073 : : * If traffic was sent from E-Switch Manager, then all usable bits will be set to 0,
10074 : : * except the least significant bit, which will be set to 1.
10075 : : *
10076 : : * This template is used to set up a table for SQ miss default flow.
10077 : : *
10078 : : * @param dev
10079 : : * Pointer to Ethernet device.
10080 : : * @param error
10081 : : * Pointer to error structure.
10082 : : *
10083 : : * @return
10084 : : * Pointer to flow pattern template on success, NULL otherwise.
10085 : : */
10086 : : static struct rte_flow_pattern_template *
10087 : 0 : flow_hw_create_ctrl_regc_sq_pattern_template(struct rte_eth_dev *dev,
10088 : : struct rte_flow_error *error)
10089 : : {
10090 : 0 : struct rte_flow_pattern_template_attr attr = {
10091 : : .relaxed_matching = 0,
10092 : : .transfer = 1,
10093 : : };
10094 : 0 : struct rte_flow_item_tag reg_c0_spec = {
10095 : : .index = (uint8_t)REG_C_0,
10096 : : };
10097 : 0 : struct rte_flow_item_tag reg_c0_mask = {
10098 : : .index = 0xff,
10099 : : .data = flow_hw_esw_mgr_regc_marker_mask(dev),
10100 : : };
10101 : 0 : struct mlx5_rte_flow_item_sq queue_mask = {
10102 : : .queue = UINT32_MAX,
10103 : : };
10104 : 0 : struct rte_flow_item items[] = {
10105 : : {
10106 : : .type = (enum rte_flow_item_type)
10107 : : MLX5_RTE_FLOW_ITEM_TYPE_TAG,
10108 : : .spec = ®_c0_spec,
10109 : : .mask = ®_c0_mask,
10110 : : },
10111 : : {
10112 : : .type = (enum rte_flow_item_type)
10113 : : MLX5_RTE_FLOW_ITEM_TYPE_SQ,
10114 : : .mask = &queue_mask,
10115 : : },
10116 : : {
10117 : : .type = RTE_FLOW_ITEM_TYPE_END,
10118 : : },
10119 : : };
10120 : :
10121 : 0 : return flow_hw_pattern_template_create(dev, &attr, items, error);
10122 : : }
10123 : :
10124 : : /**
10125 : : * Creates a flow pattern template with unmasked represented port matching.
10126 : : * This template is used to set up a table for default transfer flows
10127 : : * directing packets to group 1.
10128 : : *
10129 : : * @param dev
10130 : : * Pointer to Ethernet device.
10131 : : * @param error
10132 : : * Pointer to error structure.
10133 : : *
10134 : : * @return
10135 : : * Pointer to flow pattern template on success, NULL otherwise.
10136 : : */
10137 : : static struct rte_flow_pattern_template *
10138 : 0 : flow_hw_create_ctrl_port_pattern_template(struct rte_eth_dev *dev,
10139 : : struct rte_flow_error *error)
10140 : : {
10141 : 0 : struct rte_flow_pattern_template_attr attr = {
10142 : : .relaxed_matching = 0,
10143 : : .transfer = 1,
10144 : : };
10145 : 0 : struct rte_flow_item_ethdev port_mask = {
10146 : : .port_id = UINT16_MAX,
10147 : : };
10148 : 0 : struct rte_flow_item items[] = {
10149 : : {
10150 : : .type = RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT,
10151 : : .mask = &port_mask,
10152 : : },
10153 : : {
10154 : : .type = RTE_FLOW_ITEM_TYPE_END,
10155 : : },
10156 : : };
10157 : :
10158 : 0 : return flow_hw_pattern_template_create(dev, &attr, items, error);
10159 : : }
10160 : :
10161 : : /*
10162 : : * Creating a flow pattern template with all ETH packets matching.
10163 : : * This template is used to set up a table for default Tx copy (Tx metadata
10164 : : * to REG_C_1) flow rule usage.
10165 : : *
10166 : : * @param dev
10167 : : * Pointer to Ethernet device.
10168 : : * @param error
10169 : : * Pointer to error structure.
10170 : : *
10171 : : * @return
10172 : : * Pointer to flow pattern template on success, NULL otherwise.
10173 : : */
10174 : : static struct rte_flow_pattern_template *
10175 : 0 : flow_hw_create_tx_default_mreg_copy_pattern_template(struct rte_eth_dev *dev,
10176 : : struct rte_flow_error *error)
10177 : : {
10178 : 0 : struct rte_flow_pattern_template_attr tx_pa_attr = {
10179 : : .relaxed_matching = 0,
10180 : : .egress = 1,
10181 : : };
10182 : 0 : struct rte_flow_item_eth promisc = {
10183 : : .hdr.dst_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
10184 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
10185 : : .hdr.ether_type = 0,
10186 : : };
10187 : 0 : struct rte_flow_item eth_all[] = {
10188 : : [0] = {
10189 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
10190 : : .spec = &promisc,
10191 : : .mask = &promisc,
10192 : : },
10193 : : [1] = {
10194 : : .type = RTE_FLOW_ITEM_TYPE_END,
10195 : : },
10196 : : };
10197 : :
10198 : 0 : return flow_hw_pattern_template_create(dev, &tx_pa_attr, eth_all, error);
10199 : : }
10200 : :
10201 : : /*
10202 : : * Creating a flow pattern template with all LACP packets matching, only for NIC
10203 : : * ingress domain.
10204 : : *
10205 : : * @param dev
10206 : : * Pointer to Ethernet device.
10207 : : * @param error
10208 : : * Pointer to error structure.
10209 : : *
10210 : : * @return
10211 : : * Pointer to flow pattern template on success, NULL otherwise.
10212 : : */
10213 : : static struct rte_flow_pattern_template *
10214 : 0 : flow_hw_create_lacp_rx_pattern_template(struct rte_eth_dev *dev, struct rte_flow_error *error)
10215 : : {
10216 : 0 : struct rte_flow_pattern_template_attr pa_attr = {
10217 : : .relaxed_matching = 0,
10218 : : .ingress = 1,
10219 : : };
10220 : 0 : struct rte_flow_item_eth lacp_mask = {
10221 : : .dst.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
10222 : : .src.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
10223 : : .type = 0xFFFF,
10224 : : };
10225 : 0 : struct rte_flow_item eth_all[] = {
10226 : : [0] = {
10227 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
10228 : : .mask = &lacp_mask,
10229 : : },
10230 : : [1] = {
10231 : : .type = RTE_FLOW_ITEM_TYPE_END,
10232 : : },
10233 : : };
10234 : 0 : return flow_hw_pattern_template_create(dev, &pa_attr, eth_all, error);
10235 : : }
10236 : :
10237 : : /**
10238 : : * Creates a flow actions template with modify field action and masked jump action.
10239 : : * Modify field action sets the least significant bit of REG_C_0 (usable by user-space)
10240 : : * to 1, meaning that packet was originated from E-Switch Manager. Jump action
10241 : : * transfers steering to group 1.
10242 : : *
10243 : : * @param dev
10244 : : * Pointer to Ethernet device.
10245 : : * @param error
10246 : : * Pointer to error structure.
10247 : : *
10248 : : * @return
10249 : : * Pointer to flow actions template on success, NULL otherwise.
10250 : : */
10251 : : static struct rte_flow_actions_template *
10252 : 0 : flow_hw_create_ctrl_regc_jump_actions_template(struct rte_eth_dev *dev,
10253 : : struct rte_flow_error *error)
10254 : : {
10255 [ # # ]: 0 : uint32_t marker_mask = flow_hw_esw_mgr_regc_marker_mask(dev);
10256 : 0 : uint32_t marker_bits = flow_hw_esw_mgr_regc_marker(dev);
10257 : 0 : struct rte_flow_actions_template_attr attr = {
10258 : : .transfer = 1,
10259 : : };
10260 [ # # ]: 0 : struct rte_flow_action_modify_field set_reg_v = {
10261 : : .operation = RTE_FLOW_MODIFY_SET,
10262 : : .dst = {
10263 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
10264 : : .tag_index = REG_C_0,
10265 : : },
10266 : : .src = {
10267 : : .field = RTE_FLOW_FIELD_VALUE,
10268 : : },
10269 : : .width = rte_popcount32(marker_mask),
10270 : : };
10271 : 0 : struct rte_flow_action_modify_field set_reg_m = {
10272 : : .operation = RTE_FLOW_MODIFY_SET,
10273 : : .dst = {
10274 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
10275 : : .level = UINT8_MAX,
10276 : : .tag_index = UINT8_MAX,
10277 : : .offset = UINT32_MAX,
10278 : : },
10279 : : .src = {
10280 : : .field = RTE_FLOW_FIELD_VALUE,
10281 : : },
10282 : : .width = UINT32_MAX,
10283 : : };
10284 : 0 : struct rte_flow_action_jump jump_v = {
10285 : : .group = MLX5_HW_LOWEST_USABLE_GROUP,
10286 : : };
10287 : 0 : struct rte_flow_action_jump jump_m = {
10288 : : .group = UINT32_MAX,
10289 : : };
10290 : 0 : struct rte_flow_action actions_v[] = {
10291 : : {
10292 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
10293 : : .conf = &set_reg_v,
10294 : : },
10295 : : {
10296 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
10297 : : .conf = &jump_v,
10298 : : },
10299 : : {
10300 : : .type = RTE_FLOW_ACTION_TYPE_END,
10301 : : }
10302 : : };
10303 : 0 : struct rte_flow_action actions_m[] = {
10304 : : {
10305 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
10306 : : .conf = &set_reg_m,
10307 : : },
10308 : : {
10309 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
10310 : : .conf = &jump_m,
10311 : : },
10312 : : {
10313 : : .type = RTE_FLOW_ACTION_TYPE_END,
10314 : : }
10315 : : };
10316 : :
10317 [ # # ]: 0 : set_reg_v.dst.offset = rte_bsf32(marker_mask);
10318 : : rte_memcpy(set_reg_v.src.value, &marker_bits, sizeof(marker_bits));
10319 : : rte_memcpy(set_reg_m.src.value, &marker_mask, sizeof(marker_mask));
10320 : 0 : return flow_hw_actions_template_create(dev, &attr, actions_v, actions_m, error);
10321 : : }
10322 : :
10323 : : /**
10324 : : * Creates a flow actions template with an unmasked JUMP action. Flows
10325 : : * based on this template will perform a jump to some group. This template
10326 : : * is used to set up tables for control flows.
10327 : : *
10328 : : * @param dev
10329 : : * Pointer to Ethernet device.
10330 : : * @param group
10331 : : * Destination group for this action template.
10332 : : * @param error
10333 : : * Pointer to error structure.
10334 : : *
10335 : : * @return
10336 : : * Pointer to flow actions template on success, NULL otherwise.
10337 : : */
10338 : : static struct rte_flow_actions_template *
10339 : 0 : flow_hw_create_ctrl_jump_actions_template(struct rte_eth_dev *dev,
10340 : : uint32_t group,
10341 : : struct rte_flow_error *error)
10342 : : {
10343 : 0 : struct rte_flow_actions_template_attr attr = {
10344 : : .transfer = 1,
10345 : : };
10346 : 0 : struct rte_flow_action_jump jump_v = {
10347 : : .group = group,
10348 : : };
10349 : 0 : struct rte_flow_action_jump jump_m = {
10350 : : .group = UINT32_MAX,
10351 : : };
10352 : 0 : struct rte_flow_action actions_v[] = {
10353 : : {
10354 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
10355 : : .conf = &jump_v,
10356 : : },
10357 : : {
10358 : : .type = RTE_FLOW_ACTION_TYPE_END,
10359 : : }
10360 : : };
10361 : 0 : struct rte_flow_action actions_m[] = {
10362 : : {
10363 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
10364 : : .conf = &jump_m,
10365 : : },
10366 : : {
10367 : : .type = RTE_FLOW_ACTION_TYPE_END,
10368 : : }
10369 : : };
10370 : :
10371 : 0 : return flow_hw_actions_template_create(dev, &attr, actions_v,
10372 : : actions_m, error);
10373 : : }
10374 : :
10375 : : /**
10376 : : * Creates a flow action template with a unmasked REPRESENTED_PORT action.
10377 : : * It is used to create control flow tables.
10378 : : *
10379 : : * @param dev
10380 : : * Pointer to Ethernet device.
10381 : : * @param error
10382 : : * Pointer to error structure.
10383 : : *
10384 : : * @return
10385 : : * Pointer to flow action template on success, NULL otherwise.
10386 : : */
10387 : : static struct rte_flow_actions_template *
10388 : 0 : flow_hw_create_ctrl_port_actions_template(struct rte_eth_dev *dev,
10389 : : struct rte_flow_error *error)
10390 : : {
10391 : 0 : struct rte_flow_actions_template_attr attr = {
10392 : : .transfer = 1,
10393 : : };
10394 : 0 : struct rte_flow_action_ethdev port_v = {
10395 : : .port_id = 0,
10396 : : };
10397 : 0 : struct rte_flow_action actions_v[] = {
10398 : : {
10399 : : .type = RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT,
10400 : : .conf = &port_v,
10401 : : },
10402 : : {
10403 : : .type = RTE_FLOW_ACTION_TYPE_END,
10404 : : }
10405 : : };
10406 : 0 : struct rte_flow_action_ethdev port_m = {
10407 : : .port_id = 0,
10408 : : };
10409 : 0 : struct rte_flow_action actions_m[] = {
10410 : : {
10411 : : .type = RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT,
10412 : : .conf = &port_m,
10413 : : },
10414 : : {
10415 : : .type = RTE_FLOW_ACTION_TYPE_END,
10416 : : }
10417 : : };
10418 : :
10419 : 0 : return flow_hw_actions_template_create(dev, &attr, actions_v, actions_m, error);
10420 : : }
10421 : :
10422 : : /*
10423 : : * Creating an actions template to use header modify action for register
10424 : : * copying. This template is used to set up a table for copy flow.
10425 : : *
10426 : : * @param dev
10427 : : * Pointer to Ethernet device.
10428 : : * @param error
10429 : : * Pointer to error structure.
10430 : : *
10431 : : * @return
10432 : : * Pointer to flow actions template on success, NULL otherwise.
10433 : : */
10434 : : static struct rte_flow_actions_template *
10435 : 0 : flow_hw_create_tx_default_mreg_copy_actions_template(struct rte_eth_dev *dev,
10436 : : struct rte_flow_error *error)
10437 : : {
10438 : 0 : struct rte_flow_actions_template_attr tx_act_attr = {
10439 : : .egress = 1,
10440 : : };
10441 : 0 : const struct rte_flow_action_modify_field mreg_action = {
10442 : : .operation = RTE_FLOW_MODIFY_SET,
10443 : : .dst = {
10444 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
10445 : : .tag_index = REG_C_1,
10446 : : },
10447 : : .src = {
10448 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
10449 : : .tag_index = REG_A,
10450 : : },
10451 : : .width = 32,
10452 : : };
10453 : 0 : const struct rte_flow_action_modify_field mreg_mask = {
10454 : : .operation = RTE_FLOW_MODIFY_SET,
10455 : : .dst = {
10456 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
10457 : : .level = UINT8_MAX,
10458 : : .tag_index = UINT8_MAX,
10459 : : .offset = UINT32_MAX,
10460 : : },
10461 : : .src = {
10462 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
10463 : : .level = UINT8_MAX,
10464 : : .tag_index = UINT8_MAX,
10465 : : .offset = UINT32_MAX,
10466 : : },
10467 : : .width = UINT32_MAX,
10468 : : };
10469 : 0 : const struct rte_flow_action_jump jump_action = {
10470 : : .group = 1,
10471 : : };
10472 : 0 : const struct rte_flow_action_jump jump_mask = {
10473 : : .group = UINT32_MAX,
10474 : : };
10475 : 0 : const struct rte_flow_action actions[] = {
10476 : : [0] = {
10477 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
10478 : : .conf = &mreg_action,
10479 : : },
10480 : : [1] = {
10481 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
10482 : : .conf = &jump_action,
10483 : : },
10484 : : [2] = {
10485 : : .type = RTE_FLOW_ACTION_TYPE_END,
10486 : : },
10487 : : };
10488 : 0 : const struct rte_flow_action masks[] = {
10489 : : [0] = {
10490 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
10491 : : .conf = &mreg_mask,
10492 : : },
10493 : : [1] = {
10494 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
10495 : : .conf = &jump_mask,
10496 : : },
10497 : : [2] = {
10498 : : .type = RTE_FLOW_ACTION_TYPE_END,
10499 : : },
10500 : : };
10501 : :
10502 : 0 : return flow_hw_actions_template_create(dev, &tx_act_attr, actions,
10503 : : masks, error);
10504 : : }
10505 : :
10506 : : /*
10507 : : * Creating an actions template to use default miss to re-route packets to the
10508 : : * kernel driver stack.
10509 : : * On root table, only DEFAULT_MISS action can be used.
10510 : : *
10511 : : * @param dev
10512 : : * Pointer to Ethernet device.
10513 : : * @param error
10514 : : * Pointer to error structure.
10515 : : *
10516 : : * @return
10517 : : * Pointer to flow actions template on success, NULL otherwise.
10518 : : */
10519 : : static struct rte_flow_actions_template *
10520 : 0 : flow_hw_create_lacp_rx_actions_template(struct rte_eth_dev *dev, struct rte_flow_error *error)
10521 : : {
10522 : 0 : struct rte_flow_actions_template_attr act_attr = {
10523 : : .ingress = 1,
10524 : : };
10525 : 0 : const struct rte_flow_action actions[] = {
10526 : : [0] = {
10527 : : .type = (enum rte_flow_action_type)
10528 : : MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS,
10529 : : },
10530 : : [1] = {
10531 : : .type = RTE_FLOW_ACTION_TYPE_END,
10532 : : },
10533 : : };
10534 : :
10535 : 0 : return flow_hw_actions_template_create(dev, &act_attr, actions, actions, error);
10536 : : }
10537 : :
10538 : : /**
10539 : : * Creates a control flow table used to transfer traffic from E-Switch Manager
10540 : : * and TX queues from group 0 to group 1.
10541 : : *
10542 : : * @param dev
10543 : : * Pointer to Ethernet device.
10544 : : * @param it
10545 : : * Pointer to flow pattern template.
10546 : : * @param at
10547 : : * Pointer to flow actions template.
10548 : : * @param error
10549 : : * Pointer to error structure.
10550 : : *
10551 : : * @return
10552 : : * Pointer to flow table on success, NULL otherwise.
10553 : : */
10554 : : static struct rte_flow_template_table*
10555 : 0 : flow_hw_create_ctrl_sq_miss_root_table(struct rte_eth_dev *dev,
10556 : : struct rte_flow_pattern_template *it,
10557 : : struct rte_flow_actions_template *at,
10558 : : struct rte_flow_error *error)
10559 : : {
10560 : 0 : struct rte_flow_template_table_attr attr = {
10561 : : .flow_attr = {
10562 : : .group = 0,
10563 : : .priority = MLX5_HW_LOWEST_PRIO_ROOT,
10564 : : .ingress = 0,
10565 : : .egress = 0,
10566 : : .transfer = 1,
10567 : : },
10568 : : .nb_flows = MLX5_HW_CTRL_FLOW_NB_RULES,
10569 : : };
10570 : 0 : struct mlx5_flow_template_table_cfg cfg = {
10571 : : .attr = attr,
10572 : : .external = false,
10573 : : };
10574 : :
10575 : 0 : return flow_hw_table_create(dev, &cfg, &it, 1, &at, 1, error);
10576 : : }
10577 : :
10578 : :
10579 : : /**
10580 : : * Creates a control flow table used to transfer traffic from E-Switch Manager
10581 : : * and TX queues from group 0 to group 1.
10582 : : *
10583 : : * @param dev
10584 : : * Pointer to Ethernet device.
10585 : : * @param it
10586 : : * Pointer to flow pattern template.
10587 : : * @param at
10588 : : * Pointer to flow actions template.
10589 : : * @param error
10590 : : * Pointer to error structure.
10591 : : *
10592 : : * @return
10593 : : * Pointer to flow table on success, NULL otherwise.
10594 : : */
10595 : : static struct rte_flow_template_table*
10596 : 0 : flow_hw_create_ctrl_sq_miss_table(struct rte_eth_dev *dev,
10597 : : struct rte_flow_pattern_template *it,
10598 : : struct rte_flow_actions_template *at,
10599 : : struct rte_flow_error *error)
10600 : : {
10601 : 0 : struct rte_flow_template_table_attr attr = {
10602 : : .flow_attr = {
10603 : : .group = 1,
10604 : : .priority = MLX5_HW_LOWEST_PRIO_NON_ROOT,
10605 : : .ingress = 0,
10606 : : .egress = 0,
10607 : : .transfer = 1,
10608 : : },
10609 : : .nb_flows = MLX5_HW_CTRL_FLOW_NB_RULES,
10610 : : };
10611 : 0 : struct mlx5_flow_template_table_cfg cfg = {
10612 : : .attr = attr,
10613 : : .external = false,
10614 : : };
10615 : :
10616 : 0 : return flow_hw_table_create(dev, &cfg, &it, 1, &at, 1, error);
10617 : : }
10618 : :
10619 : : /*
10620 : : * Creating the default Tx metadata copy table on NIC Tx group 0.
10621 : : *
10622 : : * @param dev
10623 : : * Pointer to Ethernet device.
10624 : : * @param pt
10625 : : * Pointer to flow pattern template.
10626 : : * @param at
10627 : : * Pointer to flow actions template.
10628 : : * @param error
10629 : : * Pointer to error structure.
10630 : : *
10631 : : * @return
10632 : : * Pointer to flow table on success, NULL otherwise.
10633 : : */
10634 : : static struct rte_flow_template_table*
10635 : 0 : flow_hw_create_tx_default_mreg_copy_table(struct rte_eth_dev *dev,
10636 : : struct rte_flow_pattern_template *pt,
10637 : : struct rte_flow_actions_template *at,
10638 : : struct rte_flow_error *error)
10639 : : {
10640 : 0 : struct rte_flow_template_table_attr tx_tbl_attr = {
10641 : : .flow_attr = {
10642 : : .group = 0, /* Root */
10643 : : .priority = MLX5_HW_LOWEST_PRIO_ROOT,
10644 : : .egress = 1,
10645 : : },
10646 : : .nb_flows = 1, /* One default flow rule for all. */
10647 : : };
10648 : 0 : struct mlx5_flow_template_table_cfg tx_tbl_cfg = {
10649 : : .attr = tx_tbl_attr,
10650 : : .external = false,
10651 : : };
10652 : :
10653 : 0 : return flow_hw_table_create(dev, &tx_tbl_cfg, &pt, 1, &at, 1, error);
10654 : : }
10655 : :
10656 : : /**
10657 : : * Creates a control flow table used to transfer traffic
10658 : : * from group 0 to group 1.
10659 : : *
10660 : : * @param dev
10661 : : * Pointer to Ethernet device.
10662 : : * @param it
10663 : : * Pointer to flow pattern template.
10664 : : * @param at
10665 : : * Pointer to flow actions template.
10666 : : * @param error
10667 : : * Pointer to error structure.
10668 : : *
10669 : : * @return
10670 : : * Pointer to flow table on success, NULL otherwise.
10671 : : */
10672 : : static struct rte_flow_template_table *
10673 : 0 : flow_hw_create_ctrl_jump_table(struct rte_eth_dev *dev,
10674 : : struct rte_flow_pattern_template *it,
10675 : : struct rte_flow_actions_template *at,
10676 : : struct rte_flow_error *error)
10677 : : {
10678 : 0 : struct rte_flow_template_table_attr attr = {
10679 : : .flow_attr = {
10680 : : .group = 0,
10681 : : .priority = 0,
10682 : : .ingress = 0,
10683 : : .egress = 0,
10684 : : .transfer = 1,
10685 : : },
10686 : : .nb_flows = MLX5_HW_CTRL_FLOW_NB_RULES,
10687 : : };
10688 : 0 : struct mlx5_flow_template_table_cfg cfg = {
10689 : : .attr = attr,
10690 : : .external = false,
10691 : : };
10692 : :
10693 : 0 : return flow_hw_table_create(dev, &cfg, &it, 1, &at, 1, error);
10694 : : }
10695 : :
10696 : : /**
10697 : : * Cleans up all template tables and pattern, and actions templates used for
10698 : : * FDB control flow rules.
10699 : : *
10700 : : * @param dev
10701 : : * Pointer to Ethernet device.
10702 : : */
10703 : : static void
10704 : 0 : flow_hw_cleanup_ctrl_fdb_tables(struct rte_eth_dev *dev)
10705 : : {
10706 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
10707 : : struct mlx5_flow_hw_ctrl_fdb *hw_ctrl_fdb;
10708 : :
10709 [ # # ]: 0 : if (!priv->hw_ctrl_fdb)
10710 : : return;
10711 : : hw_ctrl_fdb = priv->hw_ctrl_fdb;
10712 : : /* Clean up templates used for LACP default miss table. */
10713 [ # # ]: 0 : if (hw_ctrl_fdb->hw_lacp_rx_tbl)
10714 : 0 : claim_zero(flow_hw_table_destroy(dev, hw_ctrl_fdb->hw_lacp_rx_tbl, NULL));
10715 [ # # ]: 0 : if (hw_ctrl_fdb->lacp_rx_actions_tmpl)
10716 : 0 : claim_zero(flow_hw_actions_template_destroy(dev, hw_ctrl_fdb->lacp_rx_actions_tmpl,
10717 : : NULL));
10718 [ # # ]: 0 : if (hw_ctrl_fdb->lacp_rx_items_tmpl)
10719 : 0 : claim_zero(flow_hw_pattern_template_destroy(dev, hw_ctrl_fdb->lacp_rx_items_tmpl,
10720 : : NULL));
10721 : : /* Clean up templates used for default Tx metadata copy. */
10722 [ # # ]: 0 : if (hw_ctrl_fdb->hw_tx_meta_cpy_tbl)
10723 : 0 : claim_zero(flow_hw_table_destroy(dev, hw_ctrl_fdb->hw_tx_meta_cpy_tbl, NULL));
10724 [ # # ]: 0 : if (hw_ctrl_fdb->tx_meta_actions_tmpl)
10725 : 0 : claim_zero(flow_hw_actions_template_destroy(dev, hw_ctrl_fdb->tx_meta_actions_tmpl,
10726 : : NULL));
10727 [ # # ]: 0 : if (hw_ctrl_fdb->tx_meta_items_tmpl)
10728 : 0 : claim_zero(flow_hw_pattern_template_destroy(dev, hw_ctrl_fdb->tx_meta_items_tmpl,
10729 : : NULL));
10730 : : /* Clean up templates used for default FDB jump rule. */
10731 [ # # ]: 0 : if (hw_ctrl_fdb->hw_esw_zero_tbl)
10732 : 0 : claim_zero(flow_hw_table_destroy(dev, hw_ctrl_fdb->hw_esw_zero_tbl, NULL));
10733 [ # # ]: 0 : if (hw_ctrl_fdb->jump_one_actions_tmpl)
10734 : 0 : claim_zero(flow_hw_actions_template_destroy(dev, hw_ctrl_fdb->jump_one_actions_tmpl,
10735 : : NULL));
10736 [ # # ]: 0 : if (hw_ctrl_fdb->port_items_tmpl)
10737 : 0 : claim_zero(flow_hw_pattern_template_destroy(dev, hw_ctrl_fdb->port_items_tmpl,
10738 : : NULL));
10739 : : /* Clean up templates used for default SQ miss flow rules - non-root table. */
10740 [ # # ]: 0 : if (hw_ctrl_fdb->hw_esw_sq_miss_tbl)
10741 : 0 : claim_zero(flow_hw_table_destroy(dev, hw_ctrl_fdb->hw_esw_sq_miss_tbl, NULL));
10742 [ # # ]: 0 : if (hw_ctrl_fdb->regc_sq_items_tmpl)
10743 : 0 : claim_zero(flow_hw_pattern_template_destroy(dev, hw_ctrl_fdb->regc_sq_items_tmpl,
10744 : : NULL));
10745 [ # # ]: 0 : if (hw_ctrl_fdb->port_actions_tmpl)
10746 : 0 : claim_zero(flow_hw_actions_template_destroy(dev, hw_ctrl_fdb->port_actions_tmpl,
10747 : : NULL));
10748 : : /* Clean up templates used for default SQ miss flow rules - root table. */
10749 [ # # ]: 0 : if (hw_ctrl_fdb->hw_esw_sq_miss_root_tbl)
10750 : 0 : claim_zero(flow_hw_table_destroy(dev, hw_ctrl_fdb->hw_esw_sq_miss_root_tbl, NULL));
10751 [ # # ]: 0 : if (hw_ctrl_fdb->regc_jump_actions_tmpl)
10752 : 0 : claim_zero(flow_hw_actions_template_destroy(dev,
10753 : : hw_ctrl_fdb->regc_jump_actions_tmpl, NULL));
10754 [ # # ]: 0 : if (hw_ctrl_fdb->esw_mgr_items_tmpl)
10755 : 0 : claim_zero(flow_hw_pattern_template_destroy(dev, hw_ctrl_fdb->esw_mgr_items_tmpl,
10756 : : NULL));
10757 : : /* Clean up templates structure for FDB control flow rules. */
10758 : 0 : mlx5_free(hw_ctrl_fdb);
10759 : 0 : priv->hw_ctrl_fdb = NULL;
10760 : : }
10761 : :
10762 : : /*
10763 : : * Create a table on the root group to for the LACP traffic redirecting.
10764 : : *
10765 : : * @param dev
10766 : : * Pointer to Ethernet device.
10767 : : * @param it
10768 : : * Pointer to flow pattern template.
10769 : : * @param at
10770 : : * Pointer to flow actions template.
10771 : : *
10772 : : * @return
10773 : : * Pointer to flow table on success, NULL otherwise.
10774 : : */
10775 : : static struct rte_flow_template_table *
10776 : 0 : flow_hw_create_lacp_rx_table(struct rte_eth_dev *dev,
10777 : : struct rte_flow_pattern_template *it,
10778 : : struct rte_flow_actions_template *at,
10779 : : struct rte_flow_error *error)
10780 : : {
10781 : 0 : struct rte_flow_template_table_attr attr = {
10782 : : .flow_attr = {
10783 : : .group = 0,
10784 : : .priority = 0,
10785 : : .ingress = 1,
10786 : : .egress = 0,
10787 : : .transfer = 0,
10788 : : },
10789 : : .nb_flows = 1,
10790 : : };
10791 : 0 : struct mlx5_flow_template_table_cfg cfg = {
10792 : : .attr = attr,
10793 : : .external = false,
10794 : : };
10795 : :
10796 : 0 : return flow_hw_table_create(dev, &cfg, &it, 1, &at, 1, error);
10797 : : }
10798 : :
10799 : : /**
10800 : : * Creates a set of flow tables used to create control flows used
10801 : : * when E-Switch is engaged.
10802 : : *
10803 : : * @param dev
10804 : : * Pointer to Ethernet device.
10805 : : * @param error
10806 : : * Pointer to error structure.
10807 : : *
10808 : : * @return
10809 : : * 0 on success, negative values otherwise
10810 : : */
10811 : : static int
10812 : 0 : flow_hw_create_ctrl_tables(struct rte_eth_dev *dev, struct rte_flow_error *error)
10813 : : {
10814 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
10815 : : struct mlx5_flow_hw_ctrl_fdb *hw_ctrl_fdb;
10816 : 0 : uint32_t xmeta = priv->sh->config.dv_xmeta_en;
10817 : 0 : uint32_t repr_matching = priv->sh->config.repr_matching;
10818 : 0 : uint32_t fdb_def_rule = priv->sh->config.fdb_def_rule;
10819 : :
10820 : : MLX5_ASSERT(priv->hw_ctrl_fdb == NULL);
10821 : 0 : hw_ctrl_fdb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*hw_ctrl_fdb), 0, SOCKET_ID_ANY);
10822 [ # # ]: 0 : if (!hw_ctrl_fdb) {
10823 : 0 : DRV_LOG(ERR, "port %u failed to allocate memory for FDB control flow templates",
10824 : : dev->data->port_id);
10825 : 0 : rte_errno = ENOMEM;
10826 : 0 : goto err;
10827 : : }
10828 : 0 : priv->hw_ctrl_fdb = hw_ctrl_fdb;
10829 [ # # ]: 0 : if (fdb_def_rule) {
10830 : : /* Create templates and table for default SQ miss flow rules - root table. */
10831 : 0 : hw_ctrl_fdb->esw_mgr_items_tmpl =
10832 : 0 : flow_hw_create_ctrl_esw_mgr_pattern_template(dev, error);
10833 [ # # ]: 0 : if (!hw_ctrl_fdb->esw_mgr_items_tmpl) {
10834 : 0 : DRV_LOG(ERR, "port %u failed to create E-Switch Manager item"
10835 : : " template for control flows", dev->data->port_id);
10836 : 0 : goto err;
10837 : : }
10838 : 0 : hw_ctrl_fdb->regc_jump_actions_tmpl =
10839 : 0 : flow_hw_create_ctrl_regc_jump_actions_template(dev, error);
10840 [ # # ]: 0 : if (!hw_ctrl_fdb->regc_jump_actions_tmpl) {
10841 : 0 : DRV_LOG(ERR, "port %u failed to create REG_C set and jump action template"
10842 : : " for control flows", dev->data->port_id);
10843 : 0 : goto err;
10844 : : }
10845 : 0 : hw_ctrl_fdb->hw_esw_sq_miss_root_tbl =
10846 : 0 : flow_hw_create_ctrl_sq_miss_root_table
10847 : : (dev, hw_ctrl_fdb->esw_mgr_items_tmpl,
10848 : : hw_ctrl_fdb->regc_jump_actions_tmpl, error);
10849 [ # # ]: 0 : if (!hw_ctrl_fdb->hw_esw_sq_miss_root_tbl) {
10850 : 0 : DRV_LOG(ERR, "port %u failed to create table for default sq miss (root table)"
10851 : : " for control flows", dev->data->port_id);
10852 : 0 : goto err;
10853 : : }
10854 : : /* Create templates and table for default SQ miss flow rules - non-root table. */
10855 : 0 : hw_ctrl_fdb->regc_sq_items_tmpl =
10856 : 0 : flow_hw_create_ctrl_regc_sq_pattern_template(dev, error);
10857 [ # # ]: 0 : if (!hw_ctrl_fdb->regc_sq_items_tmpl) {
10858 : 0 : DRV_LOG(ERR, "port %u failed to create SQ item template for"
10859 : : " control flows", dev->data->port_id);
10860 : 0 : goto err;
10861 : : }
10862 : 0 : hw_ctrl_fdb->port_actions_tmpl =
10863 : 0 : flow_hw_create_ctrl_port_actions_template(dev, error);
10864 [ # # ]: 0 : if (!hw_ctrl_fdb->port_actions_tmpl) {
10865 : 0 : DRV_LOG(ERR, "port %u failed to create port action template"
10866 : : " for control flows", dev->data->port_id);
10867 : 0 : goto err;
10868 : : }
10869 : 0 : hw_ctrl_fdb->hw_esw_sq_miss_tbl =
10870 : 0 : flow_hw_create_ctrl_sq_miss_table
10871 : : (dev, hw_ctrl_fdb->regc_sq_items_tmpl,
10872 : : hw_ctrl_fdb->port_actions_tmpl, error);
10873 [ # # ]: 0 : if (!hw_ctrl_fdb->hw_esw_sq_miss_tbl) {
10874 : 0 : DRV_LOG(ERR, "port %u failed to create table for default sq miss (non-root table)"
10875 : : " for control flows", dev->data->port_id);
10876 : 0 : goto err;
10877 : : }
10878 : : /* Create templates and table for default FDB jump flow rules. */
10879 : 0 : hw_ctrl_fdb->port_items_tmpl =
10880 : 0 : flow_hw_create_ctrl_port_pattern_template(dev, error);
10881 [ # # ]: 0 : if (!hw_ctrl_fdb->port_items_tmpl) {
10882 : 0 : DRV_LOG(ERR, "port %u failed to create SQ item template for"
10883 : : " control flows", dev->data->port_id);
10884 : 0 : goto err;
10885 : : }
10886 : 0 : hw_ctrl_fdb->jump_one_actions_tmpl =
10887 : 0 : flow_hw_create_ctrl_jump_actions_template
10888 : : (dev, MLX5_HW_LOWEST_USABLE_GROUP, error);
10889 [ # # ]: 0 : if (!hw_ctrl_fdb->jump_one_actions_tmpl) {
10890 : 0 : DRV_LOG(ERR, "port %u failed to create jump action template"
10891 : : " for control flows", dev->data->port_id);
10892 : 0 : goto err;
10893 : : }
10894 : 0 : hw_ctrl_fdb->hw_esw_zero_tbl = flow_hw_create_ctrl_jump_table
10895 : : (dev, hw_ctrl_fdb->port_items_tmpl,
10896 : : hw_ctrl_fdb->jump_one_actions_tmpl, error);
10897 [ # # ]: 0 : if (!hw_ctrl_fdb->hw_esw_zero_tbl) {
10898 : 0 : DRV_LOG(ERR, "port %u failed to create table for default jump to group 1"
10899 : : " for control flows", dev->data->port_id);
10900 : 0 : goto err;
10901 : : }
10902 : : }
10903 : : /* Create templates and table for default Tx metadata copy flow rule. */
10904 [ # # ]: 0 : if (!repr_matching && xmeta == MLX5_XMETA_MODE_META32_HWS) {
10905 : 0 : hw_ctrl_fdb->tx_meta_items_tmpl =
10906 : 0 : flow_hw_create_tx_default_mreg_copy_pattern_template(dev, error);
10907 [ # # ]: 0 : if (!hw_ctrl_fdb->tx_meta_items_tmpl) {
10908 : 0 : DRV_LOG(ERR, "port %u failed to Tx metadata copy pattern"
10909 : : " template for control flows", dev->data->port_id);
10910 : 0 : goto err;
10911 : : }
10912 : 0 : hw_ctrl_fdb->tx_meta_actions_tmpl =
10913 : 0 : flow_hw_create_tx_default_mreg_copy_actions_template(dev, error);
10914 [ # # ]: 0 : if (!hw_ctrl_fdb->tx_meta_actions_tmpl) {
10915 : 0 : DRV_LOG(ERR, "port %u failed to Tx metadata copy actions"
10916 : : " template for control flows", dev->data->port_id);
10917 : 0 : goto err;
10918 : : }
10919 : 0 : hw_ctrl_fdb->hw_tx_meta_cpy_tbl =
10920 : 0 : flow_hw_create_tx_default_mreg_copy_table
10921 : : (dev, hw_ctrl_fdb->tx_meta_items_tmpl,
10922 : : hw_ctrl_fdb->tx_meta_actions_tmpl, error);
10923 [ # # ]: 0 : if (!hw_ctrl_fdb->hw_tx_meta_cpy_tbl) {
10924 : 0 : DRV_LOG(ERR, "port %u failed to create table for default"
10925 : : " Tx metadata copy flow rule", dev->data->port_id);
10926 : 0 : goto err;
10927 : : }
10928 : : }
10929 : : /* Create LACP default miss table. */
10930 [ # # # # : 0 : if (!priv->sh->config.lacp_by_user && priv->pf_bond >= 0 && priv->master) {
# # ]
10931 : 0 : hw_ctrl_fdb->lacp_rx_items_tmpl =
10932 : 0 : flow_hw_create_lacp_rx_pattern_template(dev, error);
10933 [ # # ]: 0 : if (!hw_ctrl_fdb->lacp_rx_items_tmpl) {
10934 : 0 : DRV_LOG(ERR, "port %u failed to create pattern template"
10935 : : " for LACP Rx traffic", dev->data->port_id);
10936 : 0 : goto err;
10937 : : }
10938 : 0 : hw_ctrl_fdb->lacp_rx_actions_tmpl =
10939 : 0 : flow_hw_create_lacp_rx_actions_template(dev, error);
10940 [ # # ]: 0 : if (!hw_ctrl_fdb->lacp_rx_actions_tmpl) {
10941 : 0 : DRV_LOG(ERR, "port %u failed to create actions template"
10942 : : " for LACP Rx traffic", dev->data->port_id);
10943 : 0 : goto err;
10944 : : }
10945 : 0 : hw_ctrl_fdb->hw_lacp_rx_tbl = flow_hw_create_lacp_rx_table
10946 : : (dev, hw_ctrl_fdb->lacp_rx_items_tmpl,
10947 : : hw_ctrl_fdb->lacp_rx_actions_tmpl, error);
10948 [ # # ]: 0 : if (!hw_ctrl_fdb->hw_lacp_rx_tbl) {
10949 : 0 : DRV_LOG(ERR, "port %u failed to create template table for"
10950 : : " for LACP Rx traffic", dev->data->port_id);
10951 : 0 : goto err;
10952 : : }
10953 : : }
10954 : : return 0;
10955 : :
10956 : 0 : err:
10957 : 0 : flow_hw_cleanup_ctrl_fdb_tables(dev);
10958 : 0 : return -EINVAL;
10959 : : }
10960 : :
10961 : : static void
10962 : 0 : flow_hw_ct_mng_destroy(struct rte_eth_dev *dev,
10963 : : struct mlx5_aso_ct_pools_mng *ct_mng)
10964 : : {
10965 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
10966 : :
10967 : 0 : mlx5_aso_ct_queue_uninit(priv->sh, ct_mng);
10968 : 0 : mlx5_free(ct_mng);
10969 : 0 : }
10970 : :
10971 : : static void
10972 : 0 : flow_hw_ct_pool_destroy(struct rte_eth_dev *dev,
10973 : : struct mlx5_aso_ct_pool *pool)
10974 : : {
10975 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
10976 : :
10977 [ # # ]: 0 : if (pool->dr_action)
10978 : 0 : mlx5dr_action_destroy(pool->dr_action);
10979 [ # # ]: 0 : if (!priv->shared_host) {
10980 [ # # ]: 0 : if (pool->devx_obj)
10981 : 0 : claim_zero(mlx5_devx_cmd_destroy(pool->devx_obj));
10982 [ # # ]: 0 : if (pool->cts)
10983 : 0 : mlx5_ipool_destroy(pool->cts);
10984 : : }
10985 : 0 : mlx5_free(pool);
10986 : 0 : }
10987 : :
10988 : : static struct mlx5_aso_ct_pool *
10989 : 0 : flow_hw_ct_pool_create(struct rte_eth_dev *dev,
10990 : : uint32_t nb_conn_tracks)
10991 : : {
10992 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
10993 : : struct mlx5_aso_ct_pool *pool;
10994 : : struct mlx5_devx_obj *obj;
10995 : : uint32_t nb_cts = rte_align32pow2(nb_conn_tracks);
10996 : : uint32_t log_obj_size = rte_log2_u32(nb_cts);
10997 : 0 : struct mlx5_indexed_pool_config cfg = {
10998 : : .size = sizeof(struct mlx5_aso_ct_action),
10999 : : .trunk_size = 1 << 12,
11000 : : .per_core_cache = 1 << 13,
11001 : : .need_lock = 1,
11002 : 0 : .release_mem_en = !!priv->sh->config.reclaim_mode,
11003 : : .malloc = mlx5_malloc,
11004 : : .free = mlx5_free,
11005 : : .type = "mlx5_hw_ct_action",
11006 : : };
11007 : : int reg_id;
11008 : : uint32_t flags = 0;
11009 : :
11010 : 0 : pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
11011 [ # # ]: 0 : if (!pool) {
11012 : 0 : rte_errno = ENOMEM;
11013 : 0 : return NULL;
11014 : : }
11015 [ # # ]: 0 : if (!priv->shared_host) {
11016 : : /*
11017 : : * No need for local cache if CT number is a small number. Since
11018 : : * flow insertion rate will be very limited in that case. Here let's
11019 : : * set the number to less than default trunk size 4K.
11020 : : */
11021 [ # # ]: 0 : if (nb_cts <= cfg.trunk_size) {
11022 : 0 : cfg.per_core_cache = 0;
11023 : 0 : cfg.trunk_size = nb_cts;
11024 [ # # ]: 0 : } else if (nb_cts <= MLX5_HW_IPOOL_SIZE_THRESHOLD) {
11025 : 0 : cfg.per_core_cache = MLX5_HW_IPOOL_CACHE_MIN;
11026 : : }
11027 : 0 : cfg.max_idx = nb_cts;
11028 : 0 : pool->cts = mlx5_ipool_create(&cfg);
11029 [ # # ]: 0 : if (!pool->cts)
11030 : 0 : goto err;
11031 : 0 : obj = mlx5_devx_cmd_create_conn_track_offload_obj(priv->sh->cdev->ctx,
11032 : 0 : priv->sh->cdev->pdn,
11033 : : log_obj_size);
11034 [ # # ]: 0 : if (!obj) {
11035 : 0 : rte_errno = ENODATA;
11036 : 0 : DRV_LOG(ERR, "Failed to create conn_track_offload_obj using DevX.");
11037 : 0 : goto err;
11038 : : }
11039 : 0 : pool->devx_obj = obj;
11040 : : } else {
11041 : : struct rte_eth_dev *host_dev = priv->shared_host;
11042 : 0 : struct mlx5_priv *host_priv = host_dev->data->dev_private;
11043 : :
11044 : 0 : pool->devx_obj = host_priv->hws_ctpool->devx_obj;
11045 : 0 : pool->cts = host_priv->hws_ctpool->cts;
11046 : : MLX5_ASSERT(pool->cts);
11047 : : MLX5_ASSERT(!nb_conn_tracks);
11048 : : }
11049 : 0 : reg_id = mlx5_flow_get_reg_id(dev, MLX5_ASO_CONNTRACK, 0, NULL);
11050 : : flags |= MLX5DR_ACTION_FLAG_HWS_RX | MLX5DR_ACTION_FLAG_HWS_TX;
11051 [ # # # # ]: 0 : if (priv->sh->config.dv_esw_en && priv->master) {
11052 : 0 : flags |= ((is_unified_fdb(priv)) ?
11053 : : (MLX5DR_ACTION_FLAG_HWS_FDB_RX |
11054 : : MLX5DR_ACTION_FLAG_HWS_FDB_TX |
11055 [ # # ]: 0 : MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED) :
11056 : : MLX5DR_ACTION_FLAG_HWS_FDB);
11057 : : }
11058 : 0 : pool->dr_action = mlx5dr_action_create_aso_ct(priv->dr_ctx,
11059 : 0 : (struct mlx5dr_devx_obj *)pool->devx_obj,
11060 : 0 : reg_id - REG_C_0, flags);
11061 [ # # ]: 0 : if (!pool->dr_action)
11062 : 0 : goto err;
11063 : 0 : pool->sq = priv->ct_mng->aso_sqs;
11064 : : /* Assign the last extra ASO SQ as public SQ. */
11065 : 0 : pool->shared_sq = &priv->ct_mng->aso_sqs[priv->nb_queue - 1];
11066 : 0 : return pool;
11067 : 0 : err:
11068 : 0 : flow_hw_ct_pool_destroy(dev, pool);
11069 : 0 : return NULL;
11070 : : }
11071 : :
11072 : : static int
11073 : 0 : mlx5_flow_ct_init(struct rte_eth_dev *dev,
11074 : : uint32_t nb_conn_tracks,
11075 : : uint16_t nb_queue)
11076 : : {
11077 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11078 : : uint32_t mem_size;
11079 : : int ret = -ENOMEM;
11080 : :
11081 [ # # ]: 0 : if (!priv->shared_host) {
11082 : 0 : mem_size = sizeof(struct mlx5_aso_sq) * nb_queue +
11083 : : sizeof(*priv->ct_mng);
11084 : 0 : priv->ct_mng = mlx5_malloc(MLX5_MEM_ZERO, mem_size,
11085 : : RTE_CACHE_LINE_SIZE,
11086 : : SOCKET_ID_ANY);
11087 [ # # ]: 0 : if (!priv->ct_mng)
11088 : 0 : goto err;
11089 : 0 : ret = mlx5_aso_ct_queue_init(priv->sh, priv->ct_mng,
11090 : : nb_queue);
11091 [ # # ]: 0 : if (ret)
11092 : 0 : goto err;
11093 : : }
11094 : 0 : priv->hws_ctpool = flow_hw_ct_pool_create(dev, nb_conn_tracks);
11095 [ # # ]: 0 : if (!priv->hws_ctpool)
11096 : 0 : goto err;
11097 : 0 : priv->sh->ct_aso_en = 1;
11098 : 0 : return 0;
11099 : :
11100 : 0 : err:
11101 [ # # ]: 0 : if (priv->hws_ctpool) {
11102 : 0 : flow_hw_ct_pool_destroy(dev, priv->hws_ctpool);
11103 : 0 : priv->hws_ctpool = NULL;
11104 : : }
11105 [ # # ]: 0 : if (priv->ct_mng) {
11106 : 0 : flow_hw_ct_mng_destroy(dev, priv->ct_mng);
11107 : 0 : priv->ct_mng = NULL;
11108 : : }
11109 : : return ret;
11110 : : }
11111 : :
11112 : : static void
11113 : 0 : flow_hw_destroy_vlan(struct rte_eth_dev *dev)
11114 : : {
11115 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11116 : : enum mlx5dr_table_type i;
11117 : :
11118 [ # # ]: 0 : for (i = MLX5DR_TABLE_TYPE_NIC_RX; i < MLX5DR_TABLE_TYPE_MAX; i++) {
11119 [ # # ]: 0 : if (priv->hw_pop_vlan[i]) {
11120 : 0 : mlx5dr_action_destroy(priv->hw_pop_vlan[i]);
11121 : 0 : priv->hw_pop_vlan[i] = NULL;
11122 : : }
11123 [ # # ]: 0 : if (priv->hw_push_vlan[i]) {
11124 : 0 : mlx5dr_action_destroy(priv->hw_push_vlan[i]);
11125 : 0 : priv->hw_push_vlan[i] = NULL;
11126 : : }
11127 : : }
11128 : 0 : }
11129 : :
11130 : : static int
11131 : 0 : _create_vlan(struct mlx5_priv *priv, enum mlx5dr_table_type type)
11132 : : {
11133 : 0 : const enum mlx5dr_action_flags flags[MLX5DR_TABLE_TYPE_MAX] = {
11134 : : MLX5DR_ACTION_FLAG_HWS_RX,
11135 : : MLX5DR_ACTION_FLAG_HWS_TX,
11136 : : MLX5DR_ACTION_FLAG_HWS_FDB,
11137 : : MLX5DR_ACTION_FLAG_HWS_FDB_RX,
11138 : : MLX5DR_ACTION_FLAG_HWS_FDB_TX,
11139 : : MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED,
11140 : : };
11141 : :
11142 : : /* rte_errno is set in the mlx5dr_action* functions. */
11143 : 0 : priv->hw_pop_vlan[type] =
11144 : 0 : mlx5dr_action_create_pop_vlan(priv->dr_ctx, flags[type]);
11145 [ # # ]: 0 : if (!priv->hw_pop_vlan[type])
11146 : 0 : return -rte_errno;
11147 : 0 : priv->hw_push_vlan[type] =
11148 : 0 : mlx5dr_action_create_push_vlan(priv->dr_ctx, flags[type]);
11149 [ # # ]: 0 : if (!priv->hw_push_vlan[type])
11150 : 0 : return -rte_errno;
11151 : : return 0;
11152 : : }
11153 : :
11154 : : static int
11155 : 0 : flow_hw_create_vlan(struct rte_eth_dev *dev)
11156 : : {
11157 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11158 : : enum mlx5dr_table_type i, from, to;
11159 : : int rc;
11160 : : bool unified_fdb = is_unified_fdb(priv);
11161 : :
11162 [ # # ]: 0 : for (i = MLX5DR_TABLE_TYPE_NIC_RX; i <= MLX5DR_TABLE_TYPE_NIC_TX; i++) {
11163 : 0 : rc = _create_vlan(priv, i);
11164 [ # # ]: 0 : if (rc)
11165 : 0 : return rc;
11166 : : }
11167 [ # # ]: 0 : from = unified_fdb ? MLX5DR_TABLE_TYPE_FDB_RX : MLX5DR_TABLE_TYPE_FDB;
11168 [ # # ]: 0 : to = unified_fdb ? MLX5DR_TABLE_TYPE_FDB_UNIFIED : MLX5DR_TABLE_TYPE_FDB;
11169 [ # # # # ]: 0 : if (priv->sh->config.dv_esw_en && priv->master) {
11170 [ # # ]: 0 : for (i = from; i <= to; i++) {
11171 : 0 : rc = _create_vlan(priv, i);
11172 [ # # ]: 0 : if (rc)
11173 : 0 : return rc;
11174 : : }
11175 : : }
11176 : : return 0;
11177 : : }
11178 : :
11179 : : static void
11180 : 0 : flow_hw_cleanup_ctrl_rx_tables(struct rte_eth_dev *dev)
11181 : : {
11182 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11183 : : unsigned int i;
11184 : : unsigned int j;
11185 : :
11186 [ # # ]: 0 : if (!priv->hw_ctrl_rx)
11187 : : return;
11188 [ # # ]: 0 : for (i = 0; i < MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_MAX; ++i) {
11189 [ # # ]: 0 : for (j = 0; j < MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX; ++j) {
11190 : 0 : struct rte_flow_template_table *tbl = priv->hw_ctrl_rx->tables[i][j].tbl;
11191 : 0 : struct rte_flow_pattern_template *pt = priv->hw_ctrl_rx->tables[i][j].pt;
11192 : :
11193 [ # # ]: 0 : if (tbl)
11194 : 0 : claim_zero(flow_hw_table_destroy(dev, tbl, NULL));
11195 [ # # ]: 0 : if (pt)
11196 : 0 : claim_zero(flow_hw_pattern_template_destroy(dev, pt, NULL));
11197 : : }
11198 : : }
11199 [ # # ]: 0 : for (i = 0; i < MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX; ++i) {
11200 : 0 : struct rte_flow_actions_template *at = priv->hw_ctrl_rx->rss[i];
11201 : :
11202 [ # # ]: 0 : if (at)
11203 : 0 : claim_zero(flow_hw_actions_template_destroy(dev, at, NULL));
11204 : : }
11205 : 0 : mlx5_free(priv->hw_ctrl_rx);
11206 : 0 : priv->hw_ctrl_rx = NULL;
11207 : : }
11208 : :
11209 : : static uint64_t
11210 : : flow_hw_ctrl_rx_rss_type_hash_types(const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
11211 : : {
11212 : : switch (rss_type) {
11213 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_NON_IP:
11214 : : return 0;
11215 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4:
11216 : : return RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_FRAG_IPV4 | RTE_ETH_RSS_NONFRAG_IPV4_OTHER;
11217 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_UDP:
11218 : : return RTE_ETH_RSS_NONFRAG_IPV4_UDP;
11219 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_TCP:
11220 : : return RTE_ETH_RSS_NONFRAG_IPV4_TCP;
11221 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6:
11222 : : return RTE_ETH_RSS_IPV6 | RTE_ETH_RSS_FRAG_IPV6 | RTE_ETH_RSS_NONFRAG_IPV6_OTHER;
11223 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_UDP:
11224 : : return RTE_ETH_RSS_NONFRAG_IPV6_UDP | RTE_ETH_RSS_IPV6_UDP_EX;
11225 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_TCP:
11226 : : return RTE_ETH_RSS_NONFRAG_IPV6_TCP | RTE_ETH_RSS_IPV6_TCP_EX;
11227 : : default:
11228 : : /* Should not reach here. */
11229 : : MLX5_ASSERT(false);
11230 : : return 0;
11231 : : }
11232 : : }
11233 : :
11234 : : static struct rte_flow_actions_template *
11235 : 0 : flow_hw_create_ctrl_rx_rss_template(struct rte_eth_dev *dev,
11236 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
11237 : : {
11238 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11239 : 0 : struct rte_flow_actions_template_attr attr = {
11240 : : .ingress = 1,
11241 : : };
11242 : : uint16_t queue[RTE_MAX_QUEUES_PER_PORT];
11243 : 0 : struct rte_flow_action_rss rss_conf = {
11244 : : .func = RTE_ETH_HASH_FUNCTION_DEFAULT,
11245 : : .level = 0,
11246 : : .types = 0,
11247 : 0 : .key_len = priv->rss_conf.rss_key_len,
11248 : 0 : .key = priv->rss_conf.rss_key,
11249 : 0 : .queue_num = priv->reta_idx_n,
11250 : : .queue = queue,
11251 : : };
11252 : 0 : struct rte_flow_action actions[] = {
11253 : : {
11254 : : .type = RTE_FLOW_ACTION_TYPE_RSS,
11255 : : .conf = &rss_conf,
11256 : : },
11257 : : {
11258 : : .type = RTE_FLOW_ACTION_TYPE_END,
11259 : : }
11260 : : };
11261 [ # # ]: 0 : struct rte_flow_action masks[] = {
11262 : : {
11263 : : .type = RTE_FLOW_ACTION_TYPE_RSS,
11264 : : .conf = &rss_conf,
11265 : : },
11266 : : {
11267 : : .type = RTE_FLOW_ACTION_TYPE_END,
11268 : : }
11269 : : };
11270 : : struct rte_flow_actions_template *at;
11271 : : struct rte_flow_error error;
11272 : : unsigned int i;
11273 : :
11274 : : MLX5_ASSERT(priv->reta_idx_n > 0 && priv->reta_idx);
11275 : : /* Select proper RSS hash types and based on that configure the actions template. */
11276 : 0 : rss_conf.types = flow_hw_ctrl_rx_rss_type_hash_types(rss_type);
11277 [ # # ]: 0 : if (rss_conf.types) {
11278 [ # # ]: 0 : for (i = 0; i < priv->reta_idx_n; ++i)
11279 : 0 : queue[i] = (*priv->reta_idx)[i];
11280 : : } else {
11281 : 0 : rss_conf.queue_num = 1;
11282 : 0 : queue[0] = (*priv->reta_idx)[0];
11283 : : }
11284 : : at = flow_hw_actions_template_create(dev, &attr, actions, masks, &error);
11285 [ # # ]: 0 : if (!at)
11286 [ # # ]: 0 : DRV_LOG(ERR,
11287 : : "Failed to create ctrl flow actions template: rte_errno(%d), type(%d): %s",
11288 : : rte_errno, error.type,
11289 : : error.message ? error.message : "(no stated reason)");
11290 : 0 : return at;
11291 : : }
11292 : :
11293 : : static uint32_t ctrl_rx_rss_priority_map[MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX] = {
11294 : : [MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_NON_IP] = MLX5_HW_CTRL_RX_PRIO_L2,
11295 : : [MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4] = MLX5_HW_CTRL_RX_PRIO_L3,
11296 : : [MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_UDP] = MLX5_HW_CTRL_RX_PRIO_L4,
11297 : : [MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_TCP] = MLX5_HW_CTRL_RX_PRIO_L4,
11298 : : [MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6] = MLX5_HW_CTRL_RX_PRIO_L3,
11299 : : [MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_UDP] = MLX5_HW_CTRL_RX_PRIO_L4,
11300 : : [MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_TCP] = MLX5_HW_CTRL_RX_PRIO_L4,
11301 : : };
11302 : :
11303 : : static uint32_t ctrl_rx_nb_flows_map[MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_MAX] = {
11304 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL] = 1,
11305 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL_MCAST] = 1,
11306 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST] = 1,
11307 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST_VLAN] = MLX5_MAX_VLAN_IDS,
11308 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST] = 1,
11309 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST_VLAN] = MLX5_MAX_VLAN_IDS,
11310 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST] = 1,
11311 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST_VLAN] = MLX5_MAX_VLAN_IDS,
11312 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC] = MLX5_MAX_UC_MAC_ADDRESSES,
11313 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN] =
11314 : : MLX5_MAX_UC_MAC_ADDRESSES * MLX5_MAX_VLAN_IDS,
11315 : : };
11316 : :
11317 : : static struct rte_flow_template_table_attr
11318 : : flow_hw_get_ctrl_rx_table_attr(enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type,
11319 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
11320 : : {
11321 : 0 : return (struct rte_flow_template_table_attr){
11322 : : .flow_attr = {
11323 : : .group = 0,
11324 : 0 : .priority = ctrl_rx_rss_priority_map[rss_type],
11325 : : .ingress = 1,
11326 : : },
11327 : 0 : .nb_flows = ctrl_rx_nb_flows_map[eth_pattern_type],
11328 : : };
11329 : : }
11330 : :
11331 : : static struct rte_flow_item
11332 : : flow_hw_get_ctrl_rx_eth_item(const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type)
11333 : : {
11334 : : struct rte_flow_item item = {
11335 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
11336 : : .mask = NULL,
11337 : : };
11338 : :
11339 : 0 : switch (eth_pattern_type) {
11340 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL:
11341 : : item.mask = &ctrl_rx_eth_promisc_mask;
11342 : : break;
11343 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL_MCAST:
11344 : : item.mask = &ctrl_rx_eth_mcast_mask;
11345 : 0 : break;
11346 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST:
11347 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST_VLAN:
11348 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC:
11349 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN:
11350 : : item.mask = &ctrl_rx_eth_dmac_mask;
11351 : 0 : break;
11352 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST:
11353 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST_VLAN:
11354 : : item.mask = &ctrl_rx_eth_ipv4_mcast_mask;
11355 : 0 : break;
11356 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST:
11357 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST_VLAN:
11358 : : item.mask = &ctrl_rx_eth_ipv6_mcast_mask;
11359 : 0 : break;
11360 : 0 : default:
11361 : : /* Should not reach here - ETH mask must be present. */
11362 : : item.type = RTE_FLOW_ITEM_TYPE_END;
11363 : : MLX5_ASSERT(false);
11364 : 0 : break;
11365 : : }
11366 : 0 : return item;
11367 : : }
11368 : :
11369 : : static struct rte_flow_item
11370 : : flow_hw_get_ctrl_rx_vlan_item(const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type)
11371 : : {
11372 : : struct rte_flow_item item = {
11373 : : .type = RTE_FLOW_ITEM_TYPE_VOID,
11374 : : .mask = NULL,
11375 : : };
11376 : :
11377 [ # # ]: 0 : switch (eth_pattern_type) {
11378 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST_VLAN:
11379 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST_VLAN:
11380 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST_VLAN:
11381 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN:
11382 : : item.type = RTE_FLOW_ITEM_TYPE_VLAN;
11383 : : item.mask = &rte_flow_item_vlan_mask;
11384 : 0 : break;
11385 : : default:
11386 : : /* Nothing to update. */
11387 : : break;
11388 : : }
11389 : 0 : return item;
11390 : : }
11391 : :
11392 : : static struct rte_flow_item
11393 : : flow_hw_get_ctrl_rx_l3_item(const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
11394 : : {
11395 : : struct rte_flow_item item = {
11396 : : .type = RTE_FLOW_ITEM_TYPE_VOID,
11397 : : .mask = NULL,
11398 : : };
11399 : :
11400 [ # # # ]: 0 : switch (rss_type) {
11401 : 0 : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4:
11402 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_UDP:
11403 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_TCP:
11404 : : item.type = RTE_FLOW_ITEM_TYPE_IPV4;
11405 : 0 : break;
11406 : 0 : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6:
11407 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_UDP:
11408 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_TCP:
11409 : : item.type = RTE_FLOW_ITEM_TYPE_IPV6;
11410 : 0 : break;
11411 : : default:
11412 : : /* Nothing to update. */
11413 : : break;
11414 : : }
11415 : 0 : return item;
11416 : : }
11417 : :
11418 : : static struct rte_flow_item
11419 : : flow_hw_get_ctrl_rx_l4_item(const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
11420 : : {
11421 : : struct rte_flow_item item = {
11422 : : .type = RTE_FLOW_ITEM_TYPE_VOID,
11423 : : .mask = NULL,
11424 : : };
11425 : :
11426 [ # # # ]: 0 : switch (rss_type) {
11427 : 0 : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_UDP:
11428 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_UDP:
11429 : : item.type = RTE_FLOW_ITEM_TYPE_UDP;
11430 : 0 : break;
11431 : 0 : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_TCP:
11432 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_TCP:
11433 : : item.type = RTE_FLOW_ITEM_TYPE_TCP;
11434 : 0 : break;
11435 : : default:
11436 : : /* Nothing to update. */
11437 : : break;
11438 : : }
11439 : 0 : return item;
11440 : : }
11441 : :
11442 : : static struct rte_flow_pattern_template *
11443 : 0 : flow_hw_create_ctrl_rx_pattern_template
11444 : : (struct rte_eth_dev *dev,
11445 : : const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type,
11446 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
11447 : : {
11448 : 0 : const struct rte_flow_pattern_template_attr attr = {
11449 : : .relaxed_matching = 0,
11450 : : .ingress = 1,
11451 : : };
11452 [ # # # # : 0 : struct rte_flow_item items[] = {
# # ]
11453 : : /* Matching patterns */
11454 : : flow_hw_get_ctrl_rx_eth_item(eth_pattern_type),
11455 : : flow_hw_get_ctrl_rx_vlan_item(eth_pattern_type),
11456 : : flow_hw_get_ctrl_rx_l3_item(rss_type),
11457 : : flow_hw_get_ctrl_rx_l4_item(rss_type),
11458 : : /* Terminate pattern */
11459 : : { .type = RTE_FLOW_ITEM_TYPE_END }
11460 : : };
11461 : :
11462 : 0 : return flow_hw_pattern_template_create(dev, &attr, items, NULL);
11463 : : }
11464 : :
11465 : : static int
11466 : 0 : flow_hw_create_ctrl_rx_tables(struct rte_eth_dev *dev)
11467 : : {
11468 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11469 : : unsigned int i;
11470 : : unsigned int j;
11471 : : int ret;
11472 : :
11473 : : MLX5_ASSERT(!priv->hw_ctrl_rx);
11474 : 0 : priv->hw_ctrl_rx = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*priv->hw_ctrl_rx),
11475 : : RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
11476 [ # # ]: 0 : if (!priv->hw_ctrl_rx) {
11477 : 0 : DRV_LOG(ERR, "Failed to allocate memory for Rx control flow tables");
11478 : 0 : rte_errno = ENOMEM;
11479 : 0 : return -rte_errno;
11480 : : }
11481 : : /* Create all pattern template variants. */
11482 [ # # ]: 0 : for (i = 0; i < MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_MAX; ++i) {
11483 : : enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type = i;
11484 : :
11485 [ # # ]: 0 : for (j = 0; j < MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX; ++j) {
11486 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type = j;
11487 : : struct rte_flow_template_table_attr attr;
11488 : : struct rte_flow_pattern_template *pt;
11489 : :
11490 : : attr = flow_hw_get_ctrl_rx_table_attr(eth_pattern_type, rss_type);
11491 : 0 : pt = flow_hw_create_ctrl_rx_pattern_template(dev, eth_pattern_type,
11492 : : rss_type);
11493 [ # # ]: 0 : if (!pt)
11494 : 0 : goto err;
11495 : 0 : priv->hw_ctrl_rx->tables[i][j].attr = attr;
11496 : 0 : priv->hw_ctrl_rx->tables[i][j].pt = pt;
11497 : : }
11498 : : }
11499 : : return 0;
11500 : : err:
11501 : 0 : ret = rte_errno;
11502 : 0 : flow_hw_cleanup_ctrl_rx_tables(dev);
11503 : 0 : rte_errno = ret;
11504 : 0 : return -ret;
11505 : : }
11506 : :
11507 : : void
11508 : 0 : mlx5_flow_hw_cleanup_ctrl_rx_templates(struct rte_eth_dev *dev)
11509 : : {
11510 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11511 : : struct mlx5_flow_hw_ctrl_rx *hw_ctrl_rx;
11512 : : unsigned int i;
11513 : : unsigned int j;
11514 : :
11515 [ # # ]: 0 : if (!priv->dr_ctx)
11516 : : return;
11517 [ # # ]: 0 : if (!priv->hw_ctrl_rx)
11518 : : return;
11519 : : hw_ctrl_rx = priv->hw_ctrl_rx;
11520 [ # # ]: 0 : for (i = 0; i < MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_MAX; ++i) {
11521 [ # # ]: 0 : for (j = 0; j < MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX; ++j) {
11522 : : struct mlx5_flow_hw_ctrl_rx_table *tmpls = &hw_ctrl_rx->tables[i][j];
11523 : :
11524 [ # # ]: 0 : if (tmpls->tbl) {
11525 : 0 : claim_zero(flow_hw_table_destroy(dev, tmpls->tbl, NULL));
11526 : 0 : tmpls->tbl = NULL;
11527 : : }
11528 : : }
11529 : : }
11530 [ # # ]: 0 : for (j = 0; j < MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX; ++j) {
11531 [ # # ]: 0 : if (hw_ctrl_rx->rss[j]) {
11532 : 0 : claim_zero(flow_hw_actions_template_destroy(dev, hw_ctrl_rx->rss[j], NULL));
11533 : 0 : hw_ctrl_rx->rss[j] = NULL;
11534 : : }
11535 : : }
11536 : : }
11537 : :
11538 : : /**
11539 : : * Copy the provided HWS configuration to a newly allocated buffer.
11540 : : *
11541 : : * @param[in] port_attr
11542 : : * Port configuration attributes.
11543 : : * @param[in] nb_queue
11544 : : * Number of queue.
11545 : : * @param[in] queue_attr
11546 : : * Array that holds attributes for each flow queue.
11547 : : * @param[in] nt_mode
11548 : : * Non template mode.
11549 : : *
11550 : : * @return
11551 : : * Pointer to copied HWS configuration is returned on success.
11552 : : * Otherwise, NULL is returned and rte_errno is set.
11553 : : */
11554 : : static struct mlx5_flow_hw_attr *
11555 : 0 : flow_hw_alloc_copy_config(const struct rte_flow_port_attr *port_attr,
11556 : : const uint16_t nb_queue,
11557 : : const struct rte_flow_queue_attr *queue_attr[],
11558 : : bool nt_mode,
11559 : : struct rte_flow_error *error)
11560 : : {
11561 : : struct mlx5_flow_hw_attr *hw_attr;
11562 : : size_t hw_attr_size;
11563 : : unsigned int i;
11564 : :
11565 : 0 : hw_attr_size = sizeof(*hw_attr) + nb_queue * sizeof(*hw_attr->queue_attr);
11566 : 0 : hw_attr = mlx5_malloc(MLX5_MEM_ZERO, hw_attr_size, 0, SOCKET_ID_ANY);
11567 [ # # ]: 0 : if (!hw_attr) {
11568 : 0 : rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11569 : : "Not enough memory to store configuration");
11570 : 0 : return NULL;
11571 : : }
11572 : 0 : memcpy(&hw_attr->port_attr, port_attr, sizeof(*port_attr));
11573 : 0 : hw_attr->nb_queue = nb_queue;
11574 : : /* Queue attributes are placed after the mlx5_flow_hw_attr. */
11575 : 0 : hw_attr->queue_attr = (struct rte_flow_queue_attr *)(hw_attr + 1);
11576 [ # # ]: 0 : for (i = 0; i < nb_queue; ++i)
11577 : 0 : memcpy(&hw_attr->queue_attr[i], queue_attr[i], sizeof(hw_attr->queue_attr[i]));
11578 : 0 : hw_attr->nt_mode = nt_mode;
11579 : 0 : return hw_attr;
11580 : : }
11581 : :
11582 : : /**
11583 : : * Compares the preserved HWS configuration with the provided one.
11584 : : *
11585 : : * @param[in] hw_attr
11586 : : * Pointer to preserved HWS configuration.
11587 : : * @param[in] new_pa
11588 : : * Port configuration attributes to compare.
11589 : : * @param[in] new_nbq
11590 : : * Number of queues to compare.
11591 : : * @param[in] new_qa
11592 : : * Array that holds attributes for each flow queue.
11593 : : *
11594 : : * @return
11595 : : * True if configurations are the same, false otherwise.
11596 : : */
11597 : : static bool
11598 : 0 : flow_hw_compare_config(const struct mlx5_flow_hw_attr *hw_attr,
11599 : : const struct rte_flow_port_attr *new_pa,
11600 : : const uint16_t new_nbq,
11601 : : const struct rte_flow_queue_attr *new_qa[])
11602 : : {
11603 : : const struct rte_flow_port_attr *old_pa = &hw_attr->port_attr;
11604 : 0 : const uint16_t old_nbq = hw_attr->nb_queue;
11605 : 0 : const struct rte_flow_queue_attr *old_qa = hw_attr->queue_attr;
11606 : : unsigned int i;
11607 : :
11608 [ # # ]: 0 : if (old_pa->nb_counters != new_pa->nb_counters ||
11609 [ # # ]: 0 : old_pa->nb_aging_objects != new_pa->nb_aging_objects ||
11610 [ # # ]: 0 : old_pa->nb_meters != new_pa->nb_meters ||
11611 [ # # ]: 0 : old_pa->nb_conn_tracks != new_pa->nb_conn_tracks ||
11612 [ # # ]: 0 : old_pa->flags != new_pa->flags)
11613 : : return false;
11614 [ # # ]: 0 : if (old_nbq != new_nbq)
11615 : : return false;
11616 [ # # ]: 0 : for (i = 0; i < old_nbq; ++i)
11617 [ # # ]: 0 : if (old_qa[i].size != new_qa[i]->size)
11618 : : return false;
11619 : : return true;
11620 : : }
11621 : :
11622 : : /*
11623 : : * No need to explicitly release drop action templates on port stop.
11624 : : * Drop action templates release with other action templates during
11625 : : * mlx5_dev_close -> flow_hw_resource_release -> flow_hw_actions_template_destroy
11626 : : */
11627 : : static void
11628 : 0 : flow_hw_action_template_drop_release(struct rte_eth_dev *dev)
11629 : : {
11630 : : int i;
11631 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11632 : :
11633 [ # # ]: 0 : for (i = 0; i < MLX5DR_TABLE_TYPE_MAX; i++) {
11634 [ # # ]: 0 : if (!priv->action_template_drop[i])
11635 : 0 : continue;
11636 : 0 : flow_hw_actions_template_destroy(dev,
11637 : : priv->action_template_drop[i],
11638 : : NULL);
11639 : 0 : priv->action_template_drop[i] = NULL;
11640 : : }
11641 : 0 : }
11642 : :
11643 : : static int
11644 : 0 : flow_hw_action_template_drop_init(struct rte_eth_dev *dev,
11645 : : struct rte_flow_error *error)
11646 : : {
11647 : : uint32_t i, from, to;
11648 : 0 : const struct rte_flow_action drop[2] = {
11649 : : [0] = { .type = RTE_FLOW_ACTION_TYPE_DROP },
11650 : : [1] = { .type = RTE_FLOW_ACTION_TYPE_END },
11651 : : };
11652 : : const struct rte_flow_action *actions = drop;
11653 : : const struct rte_flow_action *masks = drop;
11654 : 0 : const struct rte_flow_actions_template_attr attr[MLX5DR_TABLE_TYPE_MAX] = {
11655 : : [MLX5DR_TABLE_TYPE_NIC_RX] = { .ingress = 1 },
11656 : : [MLX5DR_TABLE_TYPE_NIC_TX] = { .egress = 1 },
11657 : : [MLX5DR_TABLE_TYPE_FDB] = { .transfer = 1 },
11658 : : [MLX5DR_TABLE_TYPE_FDB_RX] = { .transfer = 1 },
11659 : : [MLX5DR_TABLE_TYPE_FDB_TX] = { .transfer = 1 },
11660 : : [MLX5DR_TABLE_TYPE_FDB_UNIFIED] = { .transfer = 1 },
11661 : : };
11662 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11663 : :
11664 : : from = MLX5DR_TABLE_TYPE_NIC_RX;
11665 : : to = MLX5DR_TABLE_TYPE_NIC_TX;
11666 [ # # ]: 0 : for (i = from; i <= to; i++) {
11667 : 0 : priv->action_template_drop[i] =
11668 : 0 : flow_hw_actions_template_create(dev, &attr[i], actions, masks, error);
11669 [ # # ]: 0 : if (!priv->action_template_drop[i])
11670 : : return -1;
11671 : : }
11672 : :
11673 [ # # # # ]: 0 : if (!(priv->sh->config.dv_esw_en && priv->master))
11674 : : return 0;
11675 : :
11676 : : from = MLX5DR_TABLE_TYPE_FDB;
11677 [ # # ]: 0 : to = is_unified_fdb(priv) ? MLX5DR_TABLE_TYPE_FDB_UNIFIED : MLX5DR_TABLE_TYPE_FDB;
11678 [ # # ]: 0 : for (i = from; i <= to; i++) {
11679 : 0 : priv->action_template_drop[i] =
11680 : 0 : flow_hw_actions_template_create(dev, &attr[i], actions, masks, error);
11681 [ # # ]: 0 : if (!priv->action_template_drop[i])
11682 : : return -1;
11683 : : }
11684 : : return 0;
11685 : : }
11686 : :
11687 : : static void
11688 : 0 : __flow_hw_resource_release(struct rte_eth_dev *dev, bool ctx_close)
11689 : : {
11690 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11691 : : struct rte_flow_template_table *tbl, *temp_tbl;
11692 : : struct rte_flow_pattern_template *it, *temp_it;
11693 : : struct rte_flow_actions_template *at, *temp_at;
11694 : : struct mlx5_flow_group *grp, *temp_grp;
11695 : : uint32_t i;
11696 : :
11697 : 0 : flow_hw_rxq_flag_set(dev, false);
11698 : 0 : flow_hw_flush_all_ctrl_flows(dev);
11699 : 0 : flow_hw_cleanup_ctrl_fdb_tables(dev);
11700 : 0 : flow_hw_cleanup_tx_repr_tagging(dev);
11701 : 0 : flow_hw_cleanup_ctrl_rx_tables(dev);
11702 : 0 : flow_hw_action_template_drop_release(dev);
11703 : 0 : grp = LIST_FIRST(&priv->flow_hw_grp);
11704 [ # # ]: 0 : while (grp) {
11705 : 0 : temp_grp = LIST_NEXT(grp, next);
11706 : 0 : claim_zero(flow_hw_group_unset_miss_group(dev, grp, NULL));
11707 : : grp = temp_grp;
11708 : : }
11709 : 0 : tbl = LIST_FIRST(&priv->flow_hw_tbl_ongo);
11710 [ # # ]: 0 : while (tbl) {
11711 : 0 : temp_tbl = LIST_NEXT(tbl, next);
11712 : 0 : claim_zero(flow_hw_table_destroy(dev, tbl, NULL));
11713 : : tbl = temp_tbl;
11714 : : }
11715 : 0 : tbl = LIST_FIRST(&priv->flow_hw_tbl);
11716 [ # # ]: 0 : while (tbl) {
11717 : 0 : temp_tbl = LIST_NEXT(tbl, next);
11718 : 0 : claim_zero(flow_hw_table_destroy(dev, tbl, NULL));
11719 : : tbl = temp_tbl;
11720 : : }
11721 : 0 : it = LIST_FIRST(&priv->flow_hw_itt);
11722 [ # # ]: 0 : while (it) {
11723 : 0 : temp_it = LIST_NEXT(it, next);
11724 : 0 : claim_zero(flow_hw_pattern_template_destroy(dev, it, NULL));
11725 : : it = temp_it;
11726 : : }
11727 : 0 : at = LIST_FIRST(&priv->flow_hw_at);
11728 [ # # ]: 0 : while (at) {
11729 : 0 : temp_at = LIST_NEXT(at, next);
11730 : 0 : claim_zero(flow_hw_actions_template_destroy(dev, at, NULL));
11731 : : at = temp_at;
11732 : : }
11733 [ # # ]: 0 : for (i = 0; i < MLX5_HW_ACTION_FLAG_MAX; i++) {
11734 [ # # ]: 0 : if (priv->hw_drop[i])
11735 : 0 : mlx5dr_action_destroy(priv->hw_drop[i]);
11736 [ # # ]: 0 : if (priv->hw_tag[i])
11737 : 0 : mlx5dr_action_destroy(priv->hw_tag[i]);
11738 : : }
11739 [ # # ]: 0 : if (priv->hw_def_miss)
11740 : 0 : mlx5dr_action_destroy(priv->hw_def_miss);
11741 : 0 : flow_hw_destroy_nat64_actions(priv);
11742 : 0 : flow_hw_destroy_vlan(dev);
11743 : 0 : flow_hw_destroy_send_to_kernel_action(priv);
11744 : 0 : flow_hw_free_vport_actions(priv);
11745 [ # # ]: 0 : if (priv->acts_ipool) {
11746 : 0 : mlx5_ipool_destroy(priv->acts_ipool);
11747 : 0 : priv->acts_ipool = NULL;
11748 : : }
11749 [ # # ]: 0 : if (priv->hws_age_req)
11750 : 0 : mlx5_hws_age_pool_destroy(priv);
11751 [ # # # # ]: 0 : if (!priv->shared_host && priv->hws_cpool) {
11752 : 0 : mlx5_hws_cnt_pool_destroy(priv->sh, priv->hws_cpool);
11753 : 0 : priv->hws_cpool = NULL;
11754 : : }
11755 [ # # ]: 0 : if (priv->hws_ctpool) {
11756 : 0 : flow_hw_ct_pool_destroy(dev, priv->hws_ctpool);
11757 : 0 : priv->hws_ctpool = NULL;
11758 : : }
11759 [ # # ]: 0 : if (priv->ct_mng) {
11760 : 0 : flow_hw_ct_mng_destroy(dev, priv->ct_mng);
11761 : 0 : priv->ct_mng = NULL;
11762 : : }
11763 : 0 : mlx5_flow_quota_destroy(dev);
11764 [ # # ]: 0 : if (priv->hw_q) {
11765 [ # # ]: 0 : for (i = 0; i < priv->nb_queue; i++) {
11766 : 0 : struct mlx5_hw_q *hwq = &priv->hw_q[i];
11767 : 0 : rte_ring_free(hwq->indir_iq);
11768 : 0 : rte_ring_free(hwq->indir_cq);
11769 : 0 : rte_ring_free(hwq->flow_transfer_pending);
11770 : 0 : rte_ring_free(hwq->flow_transfer_completed);
11771 : : }
11772 : 0 : mlx5_free(priv->hw_q);
11773 : 0 : priv->hw_q = NULL;
11774 : : }
11775 [ # # ]: 0 : if (ctx_close) {
11776 [ # # ]: 0 : if (priv->dr_ctx) {
11777 : 0 : claim_zero(mlx5dr_context_close(priv->dr_ctx));
11778 : 0 : priv->dr_ctx = NULL;
11779 : : }
11780 : : }
11781 [ # # ]: 0 : if (priv->shared_host) {
11782 : 0 : struct mlx5_priv *host_priv = priv->shared_host->data->dev_private;
11783 : 0 : rte_atomic_fetch_sub_explicit(&host_priv->shared_refcnt, 1,
11784 : : rte_memory_order_relaxed);
11785 : 0 : priv->shared_host = NULL;
11786 : : }
11787 [ # # ]: 0 : if (priv->hw_attr) {
11788 : 0 : mlx5_free(priv->hw_attr);
11789 : 0 : priv->hw_attr = NULL;
11790 : : }
11791 : 0 : priv->nb_queue = 0;
11792 : 0 : }
11793 : :
11794 : : static __rte_always_inline struct rte_ring *
11795 : : mlx5_hwq_ring_create(uint16_t port_id, uint32_t queue, uint32_t size, const char *str)
11796 : : {
11797 : : char mz_name[RTE_MEMZONE_NAMESIZE];
11798 : :
11799 : : snprintf(mz_name, sizeof(mz_name), "port_%u_%s_%u", port_id, str, queue);
11800 : 0 : return rte_ring_create(mz_name, size, SOCKET_ID_ANY,
11801 : : RING_F_SP_ENQ | RING_F_SC_DEQ | RING_F_EXACT_SZ);
11802 : : }
11803 : :
11804 : : static int
11805 : 0 : flow_hw_validate_attributes(const struct rte_flow_port_attr *port_attr,
11806 : : uint16_t nb_queue,
11807 : : const struct rte_flow_queue_attr *queue_attr[],
11808 : : bool nt_mode, struct rte_flow_error *error)
11809 : : {
11810 : : uint32_t size;
11811 : : unsigned int i;
11812 : :
11813 [ # # ]: 0 : if (port_attr == NULL)
11814 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11815 : : "Port attributes must be non-NULL");
11816 : :
11817 [ # # ]: 0 : if (nb_queue == 0 && !nt_mode)
11818 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11819 : : "At least one flow queue is required");
11820 : :
11821 [ # # ]: 0 : if (queue_attr == NULL)
11822 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11823 : : "Queue attributes must be non-NULL");
11824 : :
11825 : 0 : size = queue_attr[0]->size;
11826 [ # # ]: 0 : for (i = 1; i < nb_queue; ++i) {
11827 [ # # ]: 0 : if (queue_attr[i]->size != size)
11828 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11829 : : NULL,
11830 : : "All flow queues must have the same size");
11831 : : }
11832 : :
11833 : : return 0;
11834 : : }
11835 : :
11836 : : /**
11837 : : * Configure port HWS resources.
11838 : : *
11839 : : * @param[in] dev
11840 : : * Pointer to the rte_eth_dev structure.
11841 : : * @param[in] port_attr
11842 : : * Port configuration attributes.
11843 : : * @param[in] nb_queue
11844 : : * Number of queue.
11845 : : * @param[in] queue_attr
11846 : : * Array that holds attributes for each flow queue.
11847 : : * @param[in] nt_mode
11848 : : * Non-template mode.
11849 : : * @param[out] error
11850 : : * Pointer to error structure.
11851 : : *
11852 : : * @return
11853 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
11854 : : */
11855 : : static int
11856 : 0 : __flow_hw_configure(struct rte_eth_dev *dev,
11857 : : const struct rte_flow_port_attr *port_attr,
11858 : : uint16_t nb_queue,
11859 : : const struct rte_flow_queue_attr *queue_attr[],
11860 : : bool nt_mode,
11861 : : struct rte_flow_error *error)
11862 : : {
11863 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11864 : : struct mlx5_priv *host_priv = NULL;
11865 : 0 : struct mlx5dr_context_attr dr_ctx_attr = {0};
11866 : : struct mlx5_hw_q *hw_q;
11867 : : struct mlx5_hw_q_job *job = NULL;
11868 : : uint32_t mem_size, i, j;
11869 : 0 : struct mlx5_indexed_pool_config cfg = {
11870 : : .size = sizeof(struct mlx5_action_construct_data),
11871 : : .trunk_size = 4096,
11872 : : .need_lock = 1,
11873 : 0 : .release_mem_en = !!priv->sh->config.reclaim_mode,
11874 : : .malloc = mlx5_malloc,
11875 : : .free = mlx5_free,
11876 : : .type = "mlx5_hw_action_construct_data",
11877 : : };
11878 : : /*
11879 : : * Adds one queue to be used by PMD.
11880 : : * The last queue will be used by the PMD.
11881 : : */
11882 : : uint16_t nb_q_updated = 0;
11883 : : struct rte_flow_queue_attr **_queue_attr = NULL;
11884 : 0 : struct rte_flow_queue_attr ctrl_queue_attr = {0};
11885 [ # # # # ]: 0 : bool is_proxy = !!(priv->sh->config.dv_esw_en && priv->master);
11886 : : bool unified_fdb = is_unified_fdb(priv);
11887 : : int ret = 0;
11888 : : uint32_t action_flags;
11889 : : bool strict_queue = false;
11890 : :
11891 : 0 : error->type = RTE_FLOW_ERROR_TYPE_NONE;
11892 [ # # ]: 0 : if (mlx5dr_rule_get_handle_size() != MLX5_DR_RULE_SIZE) {
11893 : 0 : rte_errno = EINVAL;
11894 : 0 : goto err;
11895 : : }
11896 [ # # ]: 0 : if (flow_hw_validate_attributes(port_attr, nb_queue, queue_attr, nt_mode, error))
11897 : 0 : return -rte_errno;
11898 : : /*
11899 : : * Calling rte_flow_configure() again is allowed if
11900 : : * provided configuration matches the initially provided one,
11901 : : * or previous configuration was default non template one.
11902 : : */
11903 [ # # ]: 0 : if (priv->dr_ctx) {
11904 : : MLX5_ASSERT(priv->hw_attr != NULL);
11905 [ # # ]: 0 : for (i = 0; i < priv->nb_queue; i++) {
11906 : 0 : hw_q = &priv->hw_q[i];
11907 : : /* Make sure all queues are empty. */
11908 [ # # ]: 0 : if (hw_q->size != hw_q->job_idx) {
11909 : 0 : rte_errno = EBUSY;
11910 : 0 : goto err;
11911 : : }
11912 : : }
11913 : : /* If previous configuration was not default non template mode config. */
11914 [ # # ]: 0 : if (!priv->hw_attr->nt_mode) {
11915 [ # # ]: 0 : if (flow_hw_compare_config(priv->hw_attr, port_attr, nb_queue, queue_attr))
11916 : : return 0;
11917 : : else
11918 : 0 : return rte_flow_error_set(error, ENOTSUP,
11919 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11920 : : "Changing HWS configuration attributes "
11921 : : "is not supported");
11922 : : }
11923 : : /* Reconfiguration, need to release all resources from previous allocation. */
11924 : 0 : __flow_hw_resource_release(dev, true);
11925 : : }
11926 : 0 : priv->hw_attr = flow_hw_alloc_copy_config(port_attr, nb_queue, queue_attr, nt_mode, error);
11927 [ # # ]: 0 : if (!priv->hw_attr) {
11928 : 0 : ret = -rte_errno;
11929 : 0 : goto err;
11930 : : }
11931 : 0 : ctrl_queue_attr.size = queue_attr[0]->size;
11932 : 0 : nb_q_updated = nb_queue + 1;
11933 : 0 : _queue_attr = mlx5_malloc(MLX5_MEM_ZERO,
11934 : : nb_q_updated *
11935 : : sizeof(struct rte_flow_queue_attr *),
11936 : : 64, SOCKET_ID_ANY);
11937 [ # # ]: 0 : if (!_queue_attr) {
11938 : 0 : rte_errno = ENOMEM;
11939 : 0 : goto err;
11940 : : }
11941 : :
11942 : 0 : memcpy(_queue_attr, queue_attr, sizeof(void *) * nb_queue);
11943 : 0 : _queue_attr[nb_queue] = &ctrl_queue_attr;
11944 : 0 : priv->acts_ipool = mlx5_ipool_create(&cfg);
11945 [ # # ]: 0 : if (!priv->acts_ipool)
11946 : 0 : goto err;
11947 : : /* Allocate the queue job descriptor LIFO. */
11948 : 0 : mem_size = sizeof(priv->hw_q[0]) * nb_q_updated;
11949 [ # # ]: 0 : for (i = 0; i < nb_q_updated; i++) {
11950 : 0 : mem_size += (sizeof(struct mlx5_hw_q_job *) +
11951 : 0 : sizeof(struct mlx5_hw_q_job)) * _queue_attr[i]->size;
11952 : : }
11953 : 0 : priv->hw_q = mlx5_malloc(MLX5_MEM_ZERO, mem_size,
11954 : : 64, SOCKET_ID_ANY);
11955 [ # # ]: 0 : if (!priv->hw_q) {
11956 : 0 : rte_errno = ENOMEM;
11957 : 0 : goto err;
11958 : : }
11959 [ # # ]: 0 : for (i = 0; i < nb_q_updated; i++) {
11960 : 0 : priv->hw_q[i].job_idx = _queue_attr[i]->size;
11961 : 0 : priv->hw_q[i].size = _queue_attr[i]->size;
11962 : 0 : priv->hw_q[i].ongoing_flow_ops = 0;
11963 [ # # ]: 0 : if (i == 0)
11964 : 0 : priv->hw_q[i].job = (struct mlx5_hw_q_job **)
11965 : 0 : &priv->hw_q[nb_q_updated];
11966 : : else
11967 : 0 : priv->hw_q[i].job = (struct mlx5_hw_q_job **)&job[_queue_attr[i - 1]->size];
11968 : 0 : job = (struct mlx5_hw_q_job *)
11969 : 0 : &priv->hw_q[i].job[_queue_attr[i]->size];
11970 [ # # ]: 0 : for (j = 0; j < _queue_attr[i]->size; j++)
11971 : 0 : priv->hw_q[i].job[j] = &job[j];
11972 : : /* Notice ring name length is limited. */
11973 : 0 : priv->hw_q[i].indir_cq = mlx5_hwq_ring_create
11974 : 0 : (dev->data->port_id, i, _queue_attr[i]->size, "indir_act_cq");
11975 [ # # ]: 0 : if (!priv->hw_q[i].indir_cq)
11976 : 0 : goto err;
11977 : 0 : priv->hw_q[i].indir_iq = mlx5_hwq_ring_create
11978 : 0 : (dev->data->port_id, i, _queue_attr[i]->size, "indir_act_iq");
11979 [ # # ]: 0 : if (!priv->hw_q[i].indir_iq)
11980 : 0 : goto err;
11981 : 0 : priv->hw_q[i].flow_transfer_pending = mlx5_hwq_ring_create
11982 : 0 : (dev->data->port_id, i, _queue_attr[i]->size, "tx_pending");
11983 [ # # ]: 0 : if (!priv->hw_q[i].flow_transfer_pending)
11984 : 0 : goto err;
11985 : 0 : priv->hw_q[i].flow_transfer_completed = mlx5_hwq_ring_create
11986 : 0 : (dev->data->port_id, i, _queue_attr[i]->size, "tx_done");
11987 [ # # ]: 0 : if (!priv->hw_q[i].flow_transfer_completed)
11988 : 0 : goto err;
11989 : : }
11990 : 0 : dr_ctx_attr.pd = priv->sh->cdev->pd;
11991 : 0 : dr_ctx_attr.queues = nb_q_updated;
11992 : : /* Assign initial value of STC numbers for representors. */
11993 [ # # ]: 0 : if (priv->representor)
11994 : 0 : dr_ctx_attr.initial_log_stc_memory = MLX5_REPR_STC_MEMORY_LOG;
11995 : : /* Queue size should all be the same. Take the first one. */
11996 : 0 : dr_ctx_attr.queue_size = _queue_attr[0]->size;
11997 [ # # ]: 0 : if (port_attr->flags & RTE_FLOW_PORT_FLAG_SHARE_INDIRECT) {
11998 : : struct rte_eth_dev *host_dev = NULL;
11999 : : uint16_t port_id;
12000 : :
12001 : : MLX5_ASSERT(rte_eth_dev_is_valid_port(port_attr->host_port_id));
12002 [ # # ]: 0 : if (is_proxy) {
12003 : 0 : DRV_LOG(ERR, "cross vHCA shared mode not supported "
12004 : : "for E-Switch confgiurations");
12005 : 0 : rte_errno = ENOTSUP;
12006 : 0 : goto err;
12007 : : }
12008 [ # # ]: 0 : MLX5_ETH_FOREACH_DEV(port_id, dev->device) {
12009 [ # # ]: 0 : if (port_id == port_attr->host_port_id) {
12010 : 0 : host_dev = &rte_eth_devices[port_id];
12011 : 0 : break;
12012 : : }
12013 : : }
12014 [ # # ]: 0 : if (!host_dev || host_dev == dev ||
12015 [ # # # # ]: 0 : !host_dev->data || !host_dev->data->dev_private) {
12016 : 0 : DRV_LOG(ERR, "Invalid cross vHCA host port %u",
12017 : : port_attr->host_port_id);
12018 : 0 : rte_errno = EINVAL;
12019 : 0 : goto err;
12020 : : }
12021 : : host_priv = host_dev->data->dev_private;
12022 [ # # ]: 0 : if (host_priv->sh->cdev->ctx == priv->sh->cdev->ctx) {
12023 : 0 : DRV_LOG(ERR, "Sibling ports %u and %u do not "
12024 : : "require cross vHCA sharing mode",
12025 : : dev->data->port_id, port_attr->host_port_id);
12026 : 0 : rte_errno = EINVAL;
12027 : 0 : goto err;
12028 : : }
12029 [ # # ]: 0 : if (host_priv->shared_host) {
12030 : 0 : DRV_LOG(ERR, "Host port %u is not the sharing base",
12031 : : port_attr->host_port_id);
12032 : 0 : rte_errno = EINVAL;
12033 : 0 : goto err;
12034 : : }
12035 [ # # ]: 0 : if (port_attr->nb_counters ||
12036 [ # # ]: 0 : port_attr->nb_aging_objects ||
12037 [ # # ]: 0 : port_attr->nb_meters ||
12038 [ # # ]: 0 : port_attr->nb_conn_tracks) {
12039 : 0 : DRV_LOG(ERR,
12040 : : "Object numbers on guest port must be zeros");
12041 : 0 : rte_errno = EINVAL;
12042 : 0 : goto err;
12043 : : }
12044 : 0 : dr_ctx_attr.shared_ibv_ctx = host_priv->sh->cdev->ctx;
12045 : 0 : priv->shared_host = host_dev;
12046 : 0 : rte_atomic_fetch_add_explicit(&host_priv->shared_refcnt, 1,
12047 : : rte_memory_order_relaxed);
12048 : : }
12049 : : /* Set backward compatibale mode to support non template RTE FLOW API.*/
12050 : 0 : dr_ctx_attr.bwc = true;
12051 : 0 : priv->dr_ctx = mlx5dr_context_open(priv->sh->cdev->ctx, &dr_ctx_attr);
12052 : : /* rte_errno has been updated by HWS layer. */
12053 [ # # ]: 0 : if (!priv->dr_ctx)
12054 : 0 : goto err;
12055 : 0 : priv->nb_queue = nb_q_updated;
12056 : 0 : ret = flow_hw_action_template_drop_init(dev, error);
12057 [ # # ]: 0 : if (ret)
12058 : 0 : goto err;
12059 : 0 : ret = flow_hw_create_ctrl_rx_tables(dev);
12060 [ # # ]: 0 : if (ret) {
12061 : 0 : rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12062 : : "Failed to set up Rx control flow templates");
12063 : 0 : goto err;
12064 : : }
12065 : : /* Initialize quotas */
12066 [ # # # # : 0 : if (port_attr->nb_quotas || (host_priv && host_priv->quota_ctx.devx_obj)) {
# # ]
12067 : 0 : ret = mlx5_flow_quota_init(dev, port_attr->nb_quotas);
12068 [ # # ]: 0 : if (ret) {
12069 : 0 : rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12070 : : "Failed to initialize quota.");
12071 : 0 : goto err;
12072 : : }
12073 : : }
12074 : : /* Initialize meter library*/
12075 [ # # # # : 0 : if (port_attr->nb_meters || (host_priv && host_priv->hws_mpool))
# # ]
12076 [ # # ]: 0 : if (mlx5_flow_meter_init(dev, port_attr->nb_meters, 0, 0, nb_q_updated))
12077 : 0 : goto err;
12078 : : /* Add global actions. */
12079 [ # # ]: 0 : for (i = 0; i < MLX5_HW_ACTION_FLAG_MAX; i++) {
12080 : : uint32_t act_flags = 0;
12081 : 0 : uint32_t tag_flags = mlx5_hw_act_flag[i][0];
12082 : 0 : bool tag_fdb_rx = !!priv->sh->cdev->config.hca_attr.fdb_rx_set_flow_tag_stc;
12083 : :
12084 : 0 : act_flags = mlx5_hw_act_flag[i][MLX5DR_TABLE_TYPE_NIC_RX] |
12085 : 0 : mlx5_hw_act_flag[i][MLX5DR_TABLE_TYPE_NIC_TX];
12086 [ # # ]: 0 : if (is_proxy) {
12087 [ # # ]: 0 : if (unified_fdb) {
12088 : 0 : act_flags |=
12089 : 0 : (mlx5_hw_act_flag[i][MLX5DR_TABLE_TYPE_FDB_RX] |
12090 : 0 : mlx5_hw_act_flag[i][MLX5DR_TABLE_TYPE_FDB_TX] |
12091 : 0 : mlx5_hw_act_flag[i][MLX5DR_TABLE_TYPE_FDB_UNIFIED]);
12092 [ # # ]: 0 : if (i == MLX5_HW_ACTION_FLAG_NONE_ROOT && tag_fdb_rx)
12093 : 0 : tag_flags |= mlx5_hw_act_flag[i][MLX5DR_TABLE_TYPE_FDB_RX];
12094 : : } else {
12095 : 0 : act_flags |= mlx5_hw_act_flag[i][MLX5DR_TABLE_TYPE_FDB];
12096 [ # # ]: 0 : if (i == MLX5_HW_ACTION_FLAG_NONE_ROOT && tag_fdb_rx)
12097 : 0 : tag_flags |= mlx5_hw_act_flag[i][MLX5DR_TABLE_TYPE_FDB];
12098 : : }
12099 : : }
12100 : 0 : priv->hw_drop[i] = mlx5dr_action_create_dest_drop(priv->dr_ctx, act_flags);
12101 [ # # ]: 0 : if (!priv->hw_drop[i])
12102 : 0 : goto err;
12103 : 0 : priv->hw_tag[i] = mlx5dr_action_create_tag
12104 : : (priv->dr_ctx, tag_flags);
12105 [ # # ]: 0 : if (!priv->hw_tag[i])
12106 : 0 : goto err;
12107 : : }
12108 [ # # ]: 0 : if (priv->sh->config.dv_esw_en && priv->sh->config.repr_matching) {
12109 : 0 : ret = flow_hw_setup_tx_repr_tagging(dev, error);
12110 [ # # ]: 0 : if (ret)
12111 : 0 : goto err;
12112 : : }
12113 : : /*
12114 : : * DEFAULT_MISS action have different behaviors in different domains.
12115 : : * In FDB, it will steering the packets to the E-switch manager.
12116 : : * In NIC Rx root, it will steering the packet to the kernel driver stack.
12117 : : * An action with all bits set in the flag can be created and the HWS
12118 : : * layer will translate it properly when being used in different rules.
12119 : : */
12120 : : action_flags = MLX5DR_ACTION_FLAG_ROOT_RX | MLX5DR_ACTION_FLAG_HWS_RX |
12121 : : MLX5DR_ACTION_FLAG_ROOT_TX | MLX5DR_ACTION_FLAG_HWS_TX;
12122 [ # # ]: 0 : if (is_proxy) {
12123 [ # # ]: 0 : if (unified_fdb)
12124 : : action_flags |=
12125 : : (MLX5DR_ACTION_FLAG_ROOT_FDB |
12126 : : MLX5DR_ACTION_FLAG_HWS_FDB_RX |
12127 : : MLX5DR_ACTION_FLAG_HWS_FDB_TX |
12128 : : MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED);
12129 : : else
12130 : : action_flags |=
12131 : : (MLX5DR_ACTION_FLAG_ROOT_FDB |
12132 : : MLX5DR_ACTION_FLAG_HWS_FDB);
12133 : : }
12134 : 0 : priv->hw_def_miss = mlx5dr_action_create_default_miss(priv->dr_ctx, action_flags);
12135 [ # # ]: 0 : if (!priv->hw_def_miss)
12136 : 0 : goto err;
12137 [ # # ]: 0 : if (is_proxy) {
12138 : 0 : ret = flow_hw_create_vport_actions(priv);
12139 [ # # ]: 0 : if (ret) {
12140 : 0 : rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12141 : : NULL, "Failed to create vport actions.");
12142 : 0 : goto err;
12143 : : }
12144 : 0 : ret = flow_hw_create_ctrl_tables(dev, error);
12145 [ # # ]: 0 : if (ret) {
12146 : 0 : rte_errno = -ret;
12147 : 0 : goto err;
12148 : : }
12149 : : }
12150 : : if (!priv->shared_host)
12151 : : flow_hw_create_send_to_kernel_actions(priv, is_proxy);
12152 [ # # # # : 0 : if (port_attr->nb_conn_tracks || (host_priv && host_priv->hws_ctpool)) {
# # ]
12153 [ # # ]: 0 : if (mlx5_flow_ct_init(dev, port_attr->nb_conn_tracks, nb_q_updated))
12154 : 0 : goto err;
12155 : : }
12156 [ # # # # : 0 : if (port_attr->nb_counters || (host_priv && host_priv->hws_cpool)) {
# # ]
12157 [ # # ]: 0 : struct mlx5_hws_cnt_pool *hws_cpool = host_priv ? host_priv->hws_cpool : NULL;
12158 : :
12159 : 0 : ret = mlx5_hws_cnt_pool_create(dev, port_attr->nb_counters,
12160 : : nb_queue, hws_cpool, error);
12161 [ # # ]: 0 : if (ret)
12162 : 0 : goto err;
12163 : : }
12164 [ # # ]: 0 : if (port_attr->nb_aging_objects) {
12165 [ # # ]: 0 : if (port_attr->nb_counters == 0) {
12166 : : /*
12167 : : * Aging management uses counter. Number counters
12168 : : * requesting should take into account a counter for
12169 : : * each flow rules containing AGE without counter.
12170 : : */
12171 : 0 : DRV_LOG(ERR, "Port %u AGE objects are requested (%u) "
12172 : : "without counters requesting.",
12173 : : dev->data->port_id,
12174 : : port_attr->nb_aging_objects);
12175 : 0 : rte_errno = EINVAL;
12176 : 0 : goto err;
12177 : : }
12178 [ # # ]: 0 : if (port_attr->flags & RTE_FLOW_PORT_FLAG_SHARE_INDIRECT) {
12179 : 0 : DRV_LOG(ERR, "Aging is not supported "
12180 : : "in cross vHCA sharing mode");
12181 : : ret = -ENOTSUP;
12182 : 0 : goto err;
12183 : : }
12184 : 0 : strict_queue = !!(port_attr->flags & RTE_FLOW_PORT_FLAG_STRICT_QUEUE);
12185 : 0 : ret = mlx5_hws_age_pool_init(dev, port_attr->nb_aging_objects,
12186 : : nb_queue, strict_queue);
12187 [ # # ]: 0 : if (ret < 0)
12188 : 0 : goto err;
12189 : : }
12190 : 0 : ret = flow_hw_create_vlan(dev);
12191 [ # # ]: 0 : if (ret) {
12192 : 0 : rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12193 : : NULL, "Failed to VLAN actions.");
12194 : 0 : goto err;
12195 : : }
12196 [ # # ]: 0 : if (flow_hw_should_create_nat64_actions(priv)) {
12197 [ # # ]: 0 : if (flow_hw_create_nat64_actions(priv, error))
12198 : 0 : goto err;
12199 : : } else {
12200 : 0 : DRV_LOG(WARNING, "Cannot create NAT64 action on port %u, "
12201 : : "please check the FW version. NAT64 will not be supported.",
12202 : : dev->data->port_id);
12203 : : }
12204 : : if (_queue_attr)
12205 : 0 : mlx5_free(_queue_attr);
12206 [ # # ]: 0 : if (port_attr->flags & RTE_FLOW_PORT_FLAG_STRICT_QUEUE)
12207 : 0 : priv->hws_strict_queue = 1;
12208 : 0 : dev->flow_fp_ops = &mlx5_flow_hw_fp_ops;
12209 : 0 : return 0;
12210 : 0 : err:
12211 : 0 : __flow_hw_resource_release(dev, true);
12212 [ # # ]: 0 : if (_queue_attr)
12213 : 0 : mlx5_free(_queue_attr);
12214 : : /* Do not overwrite the internal errno information. */
12215 [ # # # # ]: 0 : if (ret && error->type != RTE_FLOW_ERROR_TYPE_NONE)
12216 : : return ret;
12217 : 0 : return rte_flow_error_set(error, rte_errno,
12218 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12219 : : "fail to configure port");
12220 : : }
12221 : :
12222 : : /**
12223 : : * Configure port HWS resources.
12224 : : *
12225 : : * @param[in] dev
12226 : : * Pointer to the rte_eth_dev structure.
12227 : : * @param[in] port_attr
12228 : : * Port configuration attributes.
12229 : : * @param[in] nb_queue
12230 : : * Number of queue.
12231 : : * @param[in] queue_attr
12232 : : * Array that holds attributes for each flow queue.
12233 : : * @param[out] error
12234 : : * Pointer to error structure.
12235 : : *
12236 : : * @return
12237 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
12238 : : */
12239 : : static int
12240 : 0 : flow_hw_configure(struct rte_eth_dev *dev,
12241 : : const struct rte_flow_port_attr *port_attr,
12242 : : uint16_t nb_queue,
12243 : : const struct rte_flow_queue_attr *queue_attr[],
12244 : : struct rte_flow_error *error)
12245 : : {
12246 : 0 : struct rte_flow_error shadow_error = {0, };
12247 : :
12248 [ # # ]: 0 : if (!error)
12249 : : error = &shadow_error;
12250 : 0 : return __flow_hw_configure(dev, port_attr, nb_queue, queue_attr, false, error);
12251 : : }
12252 : :
12253 : : /**
12254 : : * Release HWS resources.
12255 : : *
12256 : : * @param[in] dev
12257 : : * Pointer to the rte_eth_dev structure.
12258 : : */
12259 : : void
12260 : 0 : flow_hw_resource_release(struct rte_eth_dev *dev)
12261 : : {
12262 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12263 : :
12264 [ # # ]: 0 : if (!priv->dr_ctx)
12265 : : return;
12266 : 0 : __flow_hw_resource_release(dev, false);
12267 : : }
12268 : :
12269 : : /* Sets vport tag and mask, for given port, used in HWS rules. */
12270 : : void
12271 : 0 : flow_hw_set_port_info(struct rte_eth_dev *dev)
12272 : : {
12273 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12274 : 0 : uint16_t port_id = dev->data->port_id;
12275 : : struct flow_hw_port_info *info;
12276 : :
12277 : : MLX5_ASSERT(port_id < RTE_MAX_ETHPORTS);
12278 : 0 : info = &mlx5_flow_hw_port_infos[port_id];
12279 : 0 : info->regc_mask = priv->vport_meta_mask;
12280 [ # # ]: 0 : info->regc_value = priv->vport_meta_tag;
12281 [ # # ]: 0 : info->is_wire = mlx5_is_port_on_mpesw_device(priv) ? priv->mpesw_uplink : priv->master;
12282 : 0 : }
12283 : :
12284 : : /* Clears vport tag and mask used for HWS rules. */
12285 : : void
12286 : 0 : flow_hw_clear_port_info(struct rte_eth_dev *dev)
12287 : : {
12288 : 0 : uint16_t port_id = dev->data->port_id;
12289 : : struct flow_hw_port_info *info;
12290 : :
12291 : : MLX5_ASSERT(port_id < RTE_MAX_ETHPORTS);
12292 : 0 : info = &mlx5_flow_hw_port_infos[port_id];
12293 : 0 : info->regc_mask = 0;
12294 : 0 : info->regc_value = 0;
12295 : 0 : info->is_wire = 0;
12296 : 0 : }
12297 : :
12298 : : static int
12299 : 0 : flow_hw_conntrack_destroy(struct rte_eth_dev *dev,
12300 : : uint32_t idx,
12301 : : struct rte_flow_error *error)
12302 : : {
12303 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12304 : 0 : struct mlx5_aso_ct_pool *pool = priv->hws_ctpool;
12305 : : struct mlx5_aso_ct_action *ct;
12306 : :
12307 [ # # ]: 0 : if (priv->shared_host)
12308 : 0 : return rte_flow_error_set(error, ENOTSUP,
12309 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12310 : : NULL,
12311 : : "CT destruction is not allowed to guest port");
12312 : 0 : ct = mlx5_ipool_get(pool->cts, idx);
12313 [ # # ]: 0 : if (!ct) {
12314 : 0 : return rte_flow_error_set(error, EINVAL,
12315 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12316 : : NULL,
12317 : : "Invalid CT destruction index");
12318 : : }
12319 : 0 : rte_atomic_store_explicit(&ct->state, ASO_CONNTRACK_FREE,
12320 : : rte_memory_order_relaxed);
12321 : 0 : mlx5_ipool_free(pool->cts, idx);
12322 : 0 : return 0;
12323 : : }
12324 : :
12325 : : static int
12326 : 0 : flow_hw_conntrack_query(struct rte_eth_dev *dev, uint32_t queue, uint32_t idx,
12327 : : struct rte_flow_action_conntrack *profile,
12328 : : void *user_data, bool push,
12329 : : struct rte_flow_error *error)
12330 : : {
12331 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12332 : 0 : struct mlx5_aso_ct_pool *pool = priv->hws_ctpool;
12333 : : struct mlx5_aso_ct_action *ct;
12334 : :
12335 [ # # ]: 0 : if (priv->shared_host)
12336 : 0 : return rte_flow_error_set(error, ENOTSUP,
12337 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12338 : : NULL,
12339 : : "CT query is not allowed to guest port");
12340 : 0 : ct = mlx5_ipool_get(pool->cts, idx);
12341 [ # # ]: 0 : if (!ct) {
12342 : 0 : return rte_flow_error_set(error, EINVAL,
12343 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12344 : : NULL,
12345 : : "Invalid CT query index");
12346 : : }
12347 : 0 : profile->peer_port = ct->peer;
12348 : 0 : profile->is_original_dir = ct->is_original;
12349 [ # # ]: 0 : if (mlx5_aso_ct_query_by_wqe(priv->sh, queue, ct, profile, user_data, push))
12350 : 0 : return rte_flow_error_set(error, EIO,
12351 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12352 : : NULL,
12353 : : "Failed to query CT context");
12354 : : return 0;
12355 : : }
12356 : :
12357 : :
12358 : : static int
12359 : 0 : flow_hw_conntrack_update(struct rte_eth_dev *dev, uint32_t queue,
12360 : : const struct rte_flow_modify_conntrack *action_conf,
12361 : : uint32_t idx, void *user_data, bool push,
12362 : : struct rte_flow_error *error)
12363 : : {
12364 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12365 : 0 : struct mlx5_aso_ct_pool *pool = priv->hws_ctpool;
12366 : : struct mlx5_aso_ct_action *ct;
12367 : : const struct rte_flow_action_conntrack *new_prf;
12368 : : int ret = 0;
12369 : :
12370 [ # # ]: 0 : if (priv->shared_host)
12371 : 0 : return rte_flow_error_set(error, ENOTSUP,
12372 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12373 : : NULL,
12374 : : "CT update is not allowed to guest port");
12375 : 0 : ct = mlx5_ipool_get(pool->cts, idx);
12376 [ # # ]: 0 : if (!ct) {
12377 : 0 : return rte_flow_error_set(error, EINVAL,
12378 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12379 : : NULL,
12380 : : "Invalid CT update index");
12381 : : }
12382 : 0 : new_prf = &action_conf->new_ct;
12383 [ # # ]: 0 : if (action_conf->direction)
12384 : 0 : ct->is_original = !!new_prf->is_original_dir;
12385 [ # # ]: 0 : if (action_conf->state) {
12386 : : /* Only validate the profile when it needs to be updated. */
12387 : 0 : ret = mlx5_validate_action_ct(dev, new_prf, error);
12388 [ # # ]: 0 : if (ret)
12389 : : return ret;
12390 : 0 : ret = mlx5_aso_ct_update_by_wqe(priv->sh, queue, ct, new_prf,
12391 : : user_data, push);
12392 [ # # ]: 0 : if (ret)
12393 : 0 : return rte_flow_error_set(error, EIO,
12394 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12395 : : NULL,
12396 : : "Failed to send CT context update WQE");
12397 [ # # ]: 0 : if (queue != MLX5_HW_INV_QUEUE)
12398 : : return 0;
12399 : : /* Block until ready or a failure in synchronous mode. */
12400 : 0 : ret = mlx5_aso_ct_available(priv->sh, queue, ct);
12401 [ # # ]: 0 : if (ret)
12402 : 0 : rte_flow_error_set(error, rte_errno,
12403 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12404 : : NULL,
12405 : : "Timeout to get the CT update");
12406 : : }
12407 : : return ret;
12408 : : }
12409 : :
12410 : : static struct rte_flow_action_handle *
12411 : 0 : flow_hw_conntrack_create(struct rte_eth_dev *dev, uint32_t queue,
12412 : : const struct rte_flow_action_conntrack *pro,
12413 : : void *user_data, bool push,
12414 : : struct rte_flow_error *error)
12415 : : {
12416 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12417 : 0 : struct mlx5_aso_ct_pool *pool = priv->hws_ctpool;
12418 : : struct mlx5_aso_ct_action *ct;
12419 : 0 : uint32_t ct_idx = 0;
12420 : : int ret;
12421 : : bool async = !!(queue != MLX5_HW_INV_QUEUE);
12422 : :
12423 [ # # ]: 0 : if (priv->shared_host) {
12424 : 0 : rte_flow_error_set(error, ENOTSUP,
12425 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12426 : : NULL,
12427 : : "CT create is not allowed to guest port");
12428 : 0 : return NULL;
12429 : : }
12430 [ # # ]: 0 : if (!pool) {
12431 : 0 : rte_flow_error_set(error, EINVAL,
12432 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12433 : : "CT is not enabled");
12434 : 0 : return 0;
12435 : : }
12436 : 0 : ct = mlx5_ipool_zmalloc(pool->cts, &ct_idx);
12437 [ # # ]: 0 : if (!ct) {
12438 : 0 : rte_flow_error_set(error, rte_errno,
12439 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12440 : : "Failed to allocate CT object");
12441 : 0 : return 0;
12442 : : }
12443 : 0 : ct->offset = ct_idx - 1;
12444 : 0 : ct->is_original = !!pro->is_original_dir;
12445 : 0 : ct->peer = pro->peer_port;
12446 : 0 : ct->pool = pool;
12447 [ # # ]: 0 : if (mlx5_aso_ct_update_by_wqe(priv->sh, queue, ct, pro, user_data, push)) {
12448 : 0 : mlx5_ipool_free(pool->cts, ct_idx);
12449 : 0 : rte_flow_error_set(error, EBUSY,
12450 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12451 : : "Failed to update CT");
12452 : 0 : return 0;
12453 : : }
12454 [ # # ]: 0 : if (!async) {
12455 : 0 : ret = mlx5_aso_ct_available(priv->sh, queue, ct);
12456 [ # # ]: 0 : if (ret) {
12457 : 0 : mlx5_ipool_free(pool->cts, ct_idx);
12458 : 0 : rte_flow_error_set(error, rte_errno,
12459 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12460 : : NULL,
12461 : : "Timeout to get the CT update");
12462 : 0 : return 0;
12463 : : }
12464 : : }
12465 : 0 : return MLX5_INDIRECT_ACT_HWS_CT_GEN_IDX(ct_idx);
12466 : : }
12467 : :
12468 : : /**
12469 : : * Validate shared action.
12470 : : *
12471 : : * @param[in] dev
12472 : : * Pointer to the rte_eth_dev structure.
12473 : : * @param[in] queue
12474 : : * Which queue to be used.
12475 : : * @param[in] attr
12476 : : * Operation attribute.
12477 : : * @param[in] conf
12478 : : * Indirect action configuration.
12479 : : * @param[in] action
12480 : : * rte_flow action detail.
12481 : : * @param[in] user_data
12482 : : * Pointer to the user_data.
12483 : : * @param[out] error
12484 : : * Pointer to error structure.
12485 : : *
12486 : : * @return
12487 : : * 0 on success, otherwise negative errno value.
12488 : : */
12489 : : static int
12490 : 0 : flow_hw_action_handle_validate(struct rte_eth_dev *dev, uint32_t queue,
12491 : : const struct rte_flow_op_attr *attr,
12492 : : const struct rte_flow_indir_action_conf *conf,
12493 : : const struct rte_flow_action *action,
12494 : : void *user_data,
12495 : : struct rte_flow_error *error)
12496 : : {
12497 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12498 : :
12499 : : RTE_SET_USED(attr);
12500 : : RTE_SET_USED(queue);
12501 : : RTE_SET_USED(user_data);
12502 [ # # # # : 0 : switch (action->type) {
# # # ]
12503 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
12504 [ # # ]: 0 : if (!priv->hws_age_req) {
12505 [ # # ]: 0 : if (flow_hw_allocate_actions(dev, MLX5_FLOW_ACTION_AGE,
12506 : : error))
12507 : 0 : return rte_flow_error_set
12508 : : (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
12509 : : NULL, "aging pool not initialized");
12510 : : }
12511 : : break;
12512 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
12513 [ # # ]: 0 : if (!priv->hws_cpool) {
12514 [ # # ]: 0 : if (flow_hw_allocate_actions(dev, MLX5_FLOW_ACTION_COUNT,
12515 : : error))
12516 : 0 : return rte_flow_error_set
12517 : : (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
12518 : : NULL, "counters pool not initialized");
12519 : : }
12520 : : break;
12521 : 0 : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
12522 [ # # ]: 0 : if (priv->hws_ctpool == NULL) {
12523 [ # # ]: 0 : if (flow_hw_allocate_actions(dev, MLX5_FLOW_ACTION_CT,
12524 : : error))
12525 : 0 : return rte_flow_error_set
12526 : : (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
12527 : : NULL, "CT pool not initialized");
12528 : : }
12529 : 0 : return mlx5_validate_action_ct(dev, action->conf, error);
12530 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
12531 : 0 : return flow_hw_validate_action_meter_mark(dev, action, true, error);
12532 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
12533 : 0 : return flow_dv_action_validate(dev, conf, action, error);
12534 : : case RTE_FLOW_ACTION_TYPE_QUOTA:
12535 : : return 0;
12536 : 0 : default:
12537 : 0 : return rte_flow_error_set(error, ENOTSUP,
12538 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12539 : : "action type not supported");
12540 : : }
12541 : : return 0;
12542 : : }
12543 : :
12544 : : static __rte_always_inline bool
12545 : : flow_hw_action_push(const struct rte_flow_op_attr *attr)
12546 : : {
12547 [ # # # # : 0 : return attr ? !attr->postpone : true;
# # # # #
# # # #
# ]
12548 : : }
12549 : :
12550 : : static __rte_always_inline struct mlx5_hw_q_job *
12551 : : flow_hw_action_job_init(struct mlx5_priv *priv, uint32_t queue,
12552 : : const struct rte_flow_action_handle *handle,
12553 : : void *user_data, void *query_data,
12554 : : enum mlx5_hw_job_type type,
12555 : : enum mlx5_hw_indirect_type indirect_type,
12556 : : struct rte_flow_error *error)
12557 : : {
12558 : : struct mlx5_hw_q_job *job;
12559 : :
12560 [ # # # # : 0 : if (queue == MLX5_HW_INV_QUEUE)
# # # # #
# # # #
# ]
12561 [ # # # # : 0 : queue = CTRL_QUEUE_ID(priv);
# # # # #
# # # ]
12562 : : job = flow_hw_job_get(priv, queue);
12563 [ # # # # : 0 : if (!job) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # ]
12564 : 0 : rte_flow_error_set(error, ENOMEM,
12565 : : RTE_FLOW_ERROR_TYPE_ACTION_NUM, NULL,
12566 : : "Action destroy failed due to queue full.");
12567 : 0 : return NULL;
12568 : : }
12569 : 0 : job->type = type;
12570 : 0 : job->action = handle;
12571 : 0 : job->user_data = user_data;
12572 : 0 : job->query.user = query_data;
12573 [ # # # # : 0 : job->indirect_type = indirect_type;
# # # # #
# # # ]
12574 : 0 : return job;
12575 : : }
12576 : :
12577 : : struct mlx5_hw_q_job *
12578 [ # # ]: 0 : mlx5_flow_action_job_init(struct mlx5_priv *priv, uint32_t queue,
12579 : : const struct rte_flow_action_handle *handle,
12580 : : void *user_data, void *query_data,
12581 : : enum mlx5_hw_job_type type,
12582 : : struct rte_flow_error *error)
12583 : : {
12584 : 0 : return flow_hw_action_job_init(priv, queue, handle, user_data, query_data,
12585 : : type, MLX5_HW_INDIRECT_TYPE_LEGACY, error);
12586 : : }
12587 : :
12588 : : static __rte_always_inline void
12589 : : flow_hw_action_finalize(struct rte_eth_dev *dev, uint32_t queue,
12590 : : struct mlx5_hw_q_job *job,
12591 : : bool push, bool aso, bool status)
12592 : : {
12593 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12594 : :
12595 [ # # ]: 0 : if (queue == MLX5_HW_INV_QUEUE)
12596 : 0 : queue = CTRL_QUEUE_ID(priv);
12597 [ # # # # : 0 : if (likely(status)) {
# # # # #
# # # ]
12598 : : /* 1. add new job to a queue */
12599 [ # # # # : 0 : if (!aso)
# # # # #
# ]
12600 [ # # # # : 0 : rte_ring_enqueue(push ?
# # # # #
# # # #
# ]
12601 : 0 : priv->hw_q[queue].indir_cq :
12602 : 0 : priv->hw_q[queue].indir_iq,
12603 : : job);
12604 : : /* 2. send pending jobs */
12605 [ # # # # : 0 : if (push)
# # # # #
# # # #
# ]
12606 : 0 : __flow_hw_push_action(dev, queue);
12607 : : } else {
12608 : : flow_hw_job_put(priv, job, queue);
12609 : : }
12610 : : }
12611 : :
12612 : : /**
12613 : : * Create shared action.
12614 : : *
12615 : : * @param[in] dev
12616 : : * Pointer to the rte_eth_dev structure.
12617 : : * @param[in] queue
12618 : : * Which queue to be used.
12619 : : * @param[in] attr
12620 : : * Operation attribute.
12621 : : * @param[in] conf
12622 : : * Indirect action configuration.
12623 : : * @param[in] action
12624 : : * rte_flow action detail.
12625 : : * @param[in] user_data
12626 : : * Pointer to the user_data.
12627 : : * @param[out] error
12628 : : * Pointer to error structure.
12629 : : *
12630 : : * @return
12631 : : * Action handle on success, NULL otherwise and rte_errno is set.
12632 : : */
12633 : : static struct rte_flow_action_handle *
12634 : 0 : flow_hw_action_handle_create(struct rte_eth_dev *dev, uint32_t queue,
12635 : : const struct rte_flow_op_attr *attr,
12636 : : const struct rte_flow_indir_action_conf *conf,
12637 : : const struct rte_flow_action *action,
12638 : : void *user_data,
12639 : : struct rte_flow_error *error)
12640 : : {
12641 : : struct rte_flow_action_handle *handle = NULL;
12642 : : struct mlx5_hw_q_job *job = NULL;
12643 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
12644 : : const struct rte_flow_action_age *age;
12645 : : struct mlx5_aso_mtr *aso_mtr;
12646 : : cnt_id_t cnt_id;
12647 : : uint32_t age_idx;
12648 : : bool push = flow_hw_action_push(attr);
12649 : : bool aso = false;
12650 : 0 : bool force_job = action->type == RTE_FLOW_ACTION_TYPE_METER_MARK;
12651 : :
12652 [ # # ]: 0 : if (!mlx5_hw_ctx_validate(dev, error))
12653 : : return NULL;
12654 [ # # ]: 0 : if (attr || force_job) {
12655 : : job = flow_hw_action_job_init(priv, queue, NULL, user_data,
12656 : : NULL, MLX5_HW_Q_JOB_TYPE_CREATE,
12657 : : MLX5_HW_INDIRECT_TYPE_LEGACY, error);
12658 : : if (!job)
12659 : 0 : return NULL;
12660 : : }
12661 [ # # # # : 0 : switch (action->type) {
# # # ]
12662 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
12663 [ # # ]: 0 : if (priv->hws_strict_queue) {
12664 : 0 : struct mlx5_age_info *info = GET_PORT_AGE_INFO(priv);
12665 : :
12666 [ # # ]: 0 : if (queue >= info->hw_q_age->nb_rings) {
12667 : 0 : rte_flow_error_set(error, EINVAL,
12668 : : RTE_FLOW_ERROR_TYPE_ACTION,
12669 : : NULL,
12670 : : "Invalid queue ID for indirect AGE.");
12671 : 0 : rte_errno = EINVAL;
12672 : 0 : return NULL;
12673 : : }
12674 : : }
12675 : 0 : age = action->conf;
12676 : 0 : age_idx = mlx5_hws_age_action_create(priv, queue, true, age,
12677 : : 0, error);
12678 [ # # ]: 0 : if (age_idx == 0) {
12679 : 0 : rte_flow_error_set(error, ENODEV,
12680 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12681 : : "AGE are not configured!");
12682 : : } else {
12683 : 0 : age_idx = (MLX5_INDIRECT_ACTION_TYPE_AGE <<
12684 : : MLX5_INDIRECT_ACTION_TYPE_OFFSET) | age_idx;
12685 : 0 : handle =
12686 : 0 : (struct rte_flow_action_handle *)(uintptr_t)age_idx;
12687 : : }
12688 : : break;
12689 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
12690 [ # # ]: 0 : if (mlx5_hws_cnt_shared_get(priv->hws_cpool, &cnt_id, 0))
12691 : 0 : rte_flow_error_set(error, ENODEV,
12692 : : RTE_FLOW_ERROR_TYPE_ACTION,
12693 : : NULL,
12694 : : "counter are not configured!");
12695 : : else
12696 : 0 : handle = (struct rte_flow_action_handle *)
12697 : 0 : (uintptr_t)cnt_id;
12698 : : break;
12699 : 0 : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
12700 : : aso = true;
12701 : 0 : handle = flow_hw_conntrack_create(dev, queue, action->conf, job,
12702 : : push, error);
12703 : 0 : break;
12704 [ # # ]: 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
12705 : : aso = true;
12706 : : aso_mtr = flow_hw_meter_mark_alloc(dev, queue, action, job, push, error);
12707 : : if (!aso_mtr)
12708 : : break;
12709 : 0 : handle = (void *)(uintptr_t)job->action;
12710 : 0 : break;
12711 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
12712 : 0 : handle = flow_dv_action_create(dev, conf, action, error);
12713 : 0 : break;
12714 : 0 : case RTE_FLOW_ACTION_TYPE_QUOTA:
12715 : : aso = true;
12716 : 0 : handle = mlx5_quota_alloc(dev, queue, action->conf,
12717 : : job, push, error);
12718 : 0 : break;
12719 : 0 : default:
12720 : 0 : rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
12721 : : NULL, "action type not supported");
12722 : 0 : break;
12723 : : }
12724 [ # # ]: 0 : if (job && !force_job) {
12725 : 0 : job->action = handle;
12726 [ # # ]: 0 : flow_hw_action_finalize(dev, queue, job, push, aso,
12727 : : handle != NULL);
12728 : : }
12729 : : return handle;
12730 : : }
12731 : :
12732 : : static int
12733 : 0 : mlx5_flow_update_meter_mark(struct rte_eth_dev *dev, uint32_t queue,
12734 : : const struct rte_flow_update_meter_mark *upd_meter_mark,
12735 : : uint32_t idx, bool push,
12736 : : struct mlx5_hw_q_job *job, struct rte_flow_error *error)
12737 : : {
12738 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12739 : 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
12740 : : const struct rte_flow_action_meter_mark *meter_mark = &upd_meter_mark->meter_mark;
12741 : 0 : struct mlx5_aso_mtr *aso_mtr = mlx5_ipool_get(pool->idx_pool, idx);
12742 : : struct mlx5_flow_meter_info *fm;
12743 : :
12744 [ # # ]: 0 : if (!aso_mtr)
12745 : 0 : return rte_flow_error_set(error, EINVAL,
12746 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12747 : : NULL, "Invalid meter_mark update index");
12748 : : fm = &aso_mtr->fm;
12749 [ # # ]: 0 : if (upd_meter_mark->profile_valid)
12750 : 0 : fm->profile = (struct mlx5_flow_meter_profile *)
12751 : 0 : (meter_mark->profile);
12752 [ # # ]: 0 : if (upd_meter_mark->color_mode_valid)
12753 : 0 : fm->color_aware = meter_mark->color_mode;
12754 [ # # ]: 0 : if (upd_meter_mark->state_valid)
12755 : 0 : fm->is_enable = meter_mark->state;
12756 [ # # ]: 0 : aso_mtr->state = (queue == MLX5_HW_INV_QUEUE) ?
12757 : : ASO_METER_WAIT : ASO_METER_WAIT_ASYNC;
12758 : : /* Update ASO flow meter by wqe. */
12759 [ # # ]: 0 : if (mlx5_aso_meter_update_by_wqe(priv, queue,
12760 : : aso_mtr, &priv->mtr_bulk, job, push))
12761 : 0 : return rte_flow_error_set(error, EINVAL,
12762 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12763 : : NULL, "Unable to update ASO meter WQE");
12764 : : /* Wait for ASO object completion. */
12765 [ # # # # ]: 0 : if (queue == MLX5_HW_INV_QUEUE &&
12766 : 0 : mlx5_aso_mtr_wait(priv, aso_mtr, true))
12767 : 0 : return rte_flow_error_set(error, EINVAL,
12768 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12769 : : NULL, "Unable to wait for ASO meter CQE");
12770 : : return 0;
12771 : : }
12772 : :
12773 : : /**
12774 : : * Update shared action.
12775 : : *
12776 : : * @param[in] dev
12777 : : * Pointer to the rte_eth_dev structure.
12778 : : * @param[in] queue
12779 : : * Which queue to be used.
12780 : : * @param[in] attr
12781 : : * Operation attribute.
12782 : : * @param[in] handle
12783 : : * Action handle to be updated.
12784 : : * @param[in] update
12785 : : * Update value.
12786 : : * @param[in] user_data
12787 : : * Pointer to the user_data.
12788 : : * @param[out] error
12789 : : * Pointer to error structure.
12790 : : *
12791 : : * @return
12792 : : * 0 on success, negative value otherwise and rte_errno is set.
12793 : : */
12794 : : static int
12795 : 0 : flow_hw_action_handle_update(struct rte_eth_dev *dev, uint32_t queue,
12796 : : const struct rte_flow_op_attr *attr,
12797 : : struct rte_flow_action_handle *handle,
12798 : : const void *update,
12799 : : void *user_data,
12800 : : struct rte_flow_error *error)
12801 : : {
12802 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12803 : : const struct rte_flow_modify_conntrack *ct_conf =
12804 : : (const struct rte_flow_modify_conntrack *)update;
12805 : : struct mlx5_hw_q_job *job = NULL;
12806 : 0 : uint32_t act_idx = (uint32_t)(uintptr_t)handle;
12807 : 0 : uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
12808 [ # # ]: 0 : uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
12809 : : int ret = 0;
12810 : : bool push = flow_hw_action_push(attr);
12811 : : bool aso = false;
12812 : 0 : bool force_job = type == MLX5_INDIRECT_ACTION_TYPE_METER_MARK;
12813 : :
12814 [ # # ]: 0 : if (attr || force_job) {
12815 : : job = flow_hw_action_job_init(priv, queue, handle, user_data,
12816 : : NULL, MLX5_HW_Q_JOB_TYPE_UPDATE,
12817 : : MLX5_HW_INDIRECT_TYPE_LEGACY, error);
12818 : : if (!job)
12819 : 0 : return -rte_errno;
12820 : : }
12821 [ # # # # : 0 : switch (type) {
# # ]
12822 : 0 : case MLX5_INDIRECT_ACTION_TYPE_AGE:
12823 : 0 : ret = mlx5_hws_age_action_update(priv, idx, update, error);
12824 : 0 : break;
12825 : 0 : case MLX5_INDIRECT_ACTION_TYPE_CT:
12826 [ # # ]: 0 : if (ct_conf->state)
12827 : : aso = true;
12828 : 0 : ret = flow_hw_conntrack_update(dev, queue, update, idx,
12829 : : job, push, error);
12830 : 0 : break;
12831 : 0 : case MLX5_INDIRECT_ACTION_TYPE_METER_MARK:
12832 : : aso = true;
12833 : 0 : ret = mlx5_flow_update_meter_mark(dev, queue, update, idx, push,
12834 : : job, error);
12835 : 0 : break;
12836 : 0 : case MLX5_INDIRECT_ACTION_TYPE_RSS:
12837 : 0 : ret = flow_dv_action_update(dev, handle, update, error);
12838 : 0 : break;
12839 : 0 : case MLX5_INDIRECT_ACTION_TYPE_QUOTA:
12840 : : aso = true;
12841 : 0 : ret = mlx5_quota_query_update(dev, queue, handle, update, NULL,
12842 : : job, push, error);
12843 : 0 : break;
12844 : 0 : default:
12845 : : ret = -ENOTSUP;
12846 : 0 : rte_flow_error_set(error, ENOTSUP,
12847 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12848 : : "action type not supported");
12849 : 0 : break;
12850 : : }
12851 [ # # ]: 0 : if (job && !force_job)
12852 [ # # ]: 0 : flow_hw_action_finalize(dev, queue, job, push, aso, ret == 0);
12853 : : return ret;
12854 : : }
12855 : :
12856 : : /**
12857 : : * Destroy shared action.
12858 : : *
12859 : : * @param[in] dev
12860 : : * Pointer to the rte_eth_dev structure.
12861 : : * @param[in] queue
12862 : : * Which queue to be used.
12863 : : * @param[in] attr
12864 : : * Operation attribute.
12865 : : * @param[in] handle
12866 : : * Action handle to be destroyed.
12867 : : * @param[in] user_data
12868 : : * Pointer to the user_data.
12869 : : * @param[out] error
12870 : : * Pointer to error structure.
12871 : : *
12872 : : * @return
12873 : : * 0 on success, negative value otherwise and rte_errno is set.
12874 : : */
12875 : : static int
12876 : 0 : flow_hw_action_handle_destroy(struct rte_eth_dev *dev, uint32_t queue,
12877 : : const struct rte_flow_op_attr *attr,
12878 : : struct rte_flow_action_handle *handle,
12879 : : void *user_data,
12880 : : struct rte_flow_error *error)
12881 : : {
12882 : 0 : uint32_t act_idx = (uint32_t)(uintptr_t)handle;
12883 : 0 : uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
12884 : 0 : uint32_t age_idx = act_idx & MLX5_HWS_AGE_IDX_MASK;
12885 : : uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
12886 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12887 [ # # ]: 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
12888 : : struct mlx5_hw_q_job *job = NULL;
12889 : : struct mlx5_aso_mtr *aso_mtr;
12890 : : struct mlx5_flow_meter_info *fm;
12891 : : bool push = flow_hw_action_push(attr);
12892 : : bool aso = false;
12893 : : int ret = 0;
12894 : 0 : bool force_job = type == MLX5_INDIRECT_ACTION_TYPE_METER_MARK;
12895 : :
12896 [ # # ]: 0 : if (attr || force_job) {
12897 : : job = flow_hw_action_job_init(priv, queue, handle, user_data,
12898 : : NULL, MLX5_HW_Q_JOB_TYPE_DESTROY,
12899 : : MLX5_HW_INDIRECT_TYPE_LEGACY, error);
12900 : : if (!job)
12901 : 0 : return -rte_errno;
12902 : : }
12903 [ # # # # : 0 : switch (type) {
# # # ]
12904 : 0 : case MLX5_INDIRECT_ACTION_TYPE_AGE:
12905 : 0 : ret = mlx5_hws_age_action_destroy(priv, age_idx, error);
12906 : 0 : break;
12907 : 0 : case MLX5_INDIRECT_ACTION_TYPE_COUNT:
12908 [ # # ]: 0 : age_idx = mlx5_hws_cnt_age_get(priv->hws_cpool, act_idx);
12909 [ # # ]: 0 : if (age_idx != 0)
12910 : : /*
12911 : : * If this counter belongs to indirect AGE, here is the
12912 : : * time to update the AGE.
12913 : : */
12914 : : mlx5_hws_age_nb_cnt_decrease(priv, age_idx);
12915 [ # # ]: 0 : mlx5_hws_cnt_shared_put(priv->hws_cpool, &act_idx);
12916 : : break;
12917 : 0 : case MLX5_INDIRECT_ACTION_TYPE_CT:
12918 : 0 : ret = flow_hw_conntrack_destroy(dev, idx, error);
12919 : 0 : break;
12920 : 0 : case MLX5_INDIRECT_ACTION_TYPE_METER_MARK:
12921 : 0 : aso_mtr = mlx5_ipool_get(pool->idx_pool, idx);
12922 [ # # ]: 0 : if (!aso_mtr) {
12923 : : ret = -EINVAL;
12924 : 0 : rte_flow_error_set(error, EINVAL,
12925 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12926 : : NULL, "Invalid meter_mark destroy index");
12927 : 0 : break;
12928 : : }
12929 : : fm = &aso_mtr->fm;
12930 : 0 : fm->is_enable = 0;
12931 : : /* Update ASO flow meter by wqe. */
12932 [ # # ]: 0 : if (mlx5_aso_meter_update_by_wqe(priv, queue, aso_mtr,
12933 : : &priv->mtr_bulk, job, push)) {
12934 : : ret = -EINVAL;
12935 : 0 : rte_flow_error_set(error, EINVAL,
12936 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12937 : : NULL, "Unable to update ASO meter WQE");
12938 : 0 : break;
12939 : : }
12940 : : /* Wait for ASO object completion. */
12941 [ # # # # ]: 0 : if (queue == MLX5_HW_INV_QUEUE &&
12942 : 0 : mlx5_aso_mtr_wait(priv, aso_mtr, true)) {
12943 : : ret = -EINVAL;
12944 : 0 : rte_flow_error_set(error, EINVAL,
12945 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12946 : : NULL, "Unable to wait for ASO meter CQE");
12947 : 0 : break;
12948 : : }
12949 : : aso = true;
12950 : : break;
12951 : 0 : case MLX5_INDIRECT_ACTION_TYPE_RSS:
12952 : 0 : ret = flow_dv_action_destroy(dev, handle, error);
12953 : 0 : break;
12954 : : case MLX5_INDIRECT_ACTION_TYPE_QUOTA:
12955 : : break;
12956 : 0 : default:
12957 : : ret = -ENOTSUP;
12958 : 0 : rte_flow_error_set(error, ENOTSUP,
12959 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12960 : : "action type not supported");
12961 : 0 : break;
12962 : : }
12963 [ # # ]: 0 : if (job && !force_job)
12964 [ # # ]: 0 : flow_hw_action_finalize(dev, queue, job, push, aso, ret == 0);
12965 : : return ret;
12966 : : }
12967 : :
12968 : : static int
12969 : 0 : flow_hw_query_counter(const struct rte_eth_dev *dev, uint32_t counter,
12970 : : void *data, struct rte_flow_error *error)
12971 : : {
12972 : : struct mlx5_hws_cnt_pool *hpool;
12973 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
12974 : : struct mlx5_hws_cnt *cnt;
12975 : : struct rte_flow_query_count *qc = data;
12976 : : uint32_t iidx;
12977 : : uint64_t pkts, bytes;
12978 : :
12979 [ # # ]: 0 : if (!mlx5_hws_cnt_id_valid(counter))
12980 : 0 : return rte_flow_error_set(error, EINVAL,
12981 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12982 : : "counter are not available");
12983 [ # # ]: 0 : hpool = mlx5_hws_cnt_host_pool(priv->hws_cpool);
12984 : : iidx = mlx5_hws_cnt_iidx(hpool, counter);
12985 : 0 : cnt = &hpool->pool[iidx];
12986 : : __hws_cnt_query_raw(priv->hws_cpool, counter, &pkts, &bytes);
12987 : 0 : qc->hits_set = 1;
12988 : 0 : qc->bytes_set = 1;
12989 : 0 : qc->hits = pkts - cnt->reset.hits;
12990 : 0 : qc->bytes = bytes - cnt->reset.bytes;
12991 [ # # ]: 0 : if (qc->reset) {
12992 : 0 : cnt->reset.bytes = bytes;
12993 : 0 : cnt->reset.hits = pkts;
12994 : : }
12995 : : return 0;
12996 : : }
12997 : :
12998 : : /**
12999 : : * Query a flow rule AGE action for aging information.
13000 : : *
13001 : : * @param[in] dev
13002 : : * Pointer to Ethernet device.
13003 : : * @param[in] age_idx
13004 : : * Index of AGE action parameter.
13005 : : * @param[out] data
13006 : : * Data retrieved by the query.
13007 : : * @param[out] error
13008 : : * Perform verbose error reporting if not NULL.
13009 : : *
13010 : : * @return
13011 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
13012 : : */
13013 : : static int
13014 : 0 : flow_hw_query_age(const struct rte_eth_dev *dev, uint32_t age_idx, void *data,
13015 : : struct rte_flow_error *error)
13016 : : {
13017 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13018 : 0 : struct mlx5_age_info *age_info = GET_PORT_AGE_INFO(priv);
13019 : 0 : struct mlx5_indexed_pool *ipool = age_info->ages_ipool;
13020 : 0 : struct mlx5_hws_age_param *param = mlx5_ipool_get(ipool, age_idx);
13021 : : struct rte_flow_query_age *resp = data;
13022 : :
13023 [ # # # # ]: 0 : if (!param || !param->timeout)
13024 : 0 : return rte_flow_error_set(error, EINVAL,
13025 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13026 : : NULL, "age data not available");
13027 [ # # # ]: 0 : switch (rte_atomic_load_explicit(¶m->state, rte_memory_order_relaxed)) {
13028 : 0 : case HWS_AGE_AGED_OUT_REPORTED:
13029 : : case HWS_AGE_AGED_OUT_NOT_REPORTED:
13030 : 0 : resp->aged = 1;
13031 : 0 : break;
13032 : 0 : case HWS_AGE_CANDIDATE:
13033 : : case HWS_AGE_CANDIDATE_INSIDE_RING:
13034 : 0 : resp->aged = 0;
13035 : 0 : break;
13036 : : case HWS_AGE_FREE:
13037 : : /*
13038 : : * When state is FREE the flow itself should be invalid.
13039 : : * Fall-through.
13040 : : */
13041 : : default:
13042 : : MLX5_ASSERT(0);
13043 : : break;
13044 : : }
13045 : 0 : resp->sec_since_last_hit_valid = !resp->aged;
13046 [ # # ]: 0 : if (resp->sec_since_last_hit_valid)
13047 : 0 : resp->sec_since_last_hit = rte_atomic_load_explicit
13048 : : (¶m->sec_since_last_hit, rte_memory_order_relaxed);
13049 : : return 0;
13050 : : }
13051 : :
13052 : : static int
13053 : 0 : flow_hw_query(struct rte_eth_dev *dev, struct rte_flow *flow,
13054 : : const struct rte_flow_action *actions, void *data,
13055 : : struct rte_flow_error *error)
13056 : : {
13057 : : int ret = -EINVAL;
13058 : : struct rte_flow_hw *hw_flow = (struct rte_flow_hw *)flow;
13059 : : struct rte_flow_hw_aux *aux;
13060 : :
13061 [ # # ]: 0 : for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
13062 [ # # # # ]: 0 : switch (actions->type) {
13063 : : case RTE_FLOW_ACTION_TYPE_VOID:
13064 : : break;
13065 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
13066 [ # # ]: 0 : if (!(hw_flow->flags & MLX5_FLOW_HW_FLOW_FLAG_CNT_ID))
13067 : 0 : return rte_flow_error_set(error, EINVAL,
13068 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13069 : : "counter not defined in the rule");
13070 : 0 : ret = flow_hw_query_counter(dev, hw_flow->cnt_id, data,
13071 : : error);
13072 : 0 : break;
13073 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
13074 [ # # ]: 0 : if (!(hw_flow->flags & MLX5_FLOW_HW_FLOW_FLAG_AGE_IDX))
13075 : 0 : return rte_flow_error_set(error, EINVAL,
13076 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13077 : : "age data not available");
13078 [ # # ]: 0 : aux = mlx5_flow_hw_aux(dev->data->port_id, hw_flow);
13079 : 0 : ret = flow_hw_query_age(dev, mlx5_flow_hw_aux_get_age_idx(hw_flow, aux),
13080 : : data, error);
13081 : 0 : break;
13082 : 0 : default:
13083 : 0 : return rte_flow_error_set(error, ENOTSUP,
13084 : : RTE_FLOW_ERROR_TYPE_ACTION,
13085 : : actions,
13086 : : "action not supported");
13087 : : }
13088 : : }
13089 : : return ret;
13090 : : }
13091 : :
13092 : : /**
13093 : : * Validate indirect action.
13094 : : *
13095 : : * @param[in] dev
13096 : : * Pointer to the Ethernet device structure.
13097 : : * @param[in] conf
13098 : : * Shared action configuration.
13099 : : * @param[in] action
13100 : : * Action specification used to create indirect action.
13101 : : * @param[out] error
13102 : : * Perform verbose error reporting if not NULL. Initialized in case of
13103 : : * error only.
13104 : : *
13105 : : * @return
13106 : : * 0 on success, otherwise negative errno value.
13107 : : */
13108 : : static int
13109 : 0 : flow_hw_action_validate(struct rte_eth_dev *dev,
13110 : : const struct rte_flow_indir_action_conf *conf,
13111 : : const struct rte_flow_action *action,
13112 : : struct rte_flow_error *err)
13113 : : {
13114 : 0 : struct rte_flow_error shadow_error = {0, };
13115 : :
13116 [ # # ]: 0 : if (!err)
13117 : : err = &shadow_error;
13118 : 0 : return flow_hw_action_handle_validate(dev, MLX5_HW_INV_QUEUE, NULL,
13119 : : conf, action, NULL, err);
13120 : : }
13121 : :
13122 : : /**
13123 : : * Create indirect action.
13124 : : *
13125 : : * @param[in] dev
13126 : : * Pointer to the Ethernet device structure.
13127 : : * @param[in] conf
13128 : : * Shared action configuration.
13129 : : * @param[in] action
13130 : : * Action specification used to create indirect action.
13131 : : * @param[out] error
13132 : : * Perform verbose error reporting if not NULL. Initialized in case of
13133 : : * error only.
13134 : : *
13135 : : * @return
13136 : : * A valid shared action handle in case of success, NULL otherwise and
13137 : : * rte_errno is set.
13138 : : */
13139 : : static struct rte_flow_action_handle *
13140 : 0 : flow_hw_action_create(struct rte_eth_dev *dev,
13141 : : const struct rte_flow_indir_action_conf *conf,
13142 : : const struct rte_flow_action *action,
13143 : : struct rte_flow_error *err)
13144 : : {
13145 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13146 : :
13147 [ # # # # ]: 0 : if (action->type == RTE_FLOW_ACTION_TYPE_AGE && priv->hws_strict_queue) {
13148 : 0 : rte_flow_error_set(err, EINVAL, RTE_FLOW_ERROR_TYPE_STATE, NULL,
13149 : : "Cannot create age action synchronously with strict queueing");
13150 : 0 : return NULL;
13151 : : }
13152 : :
13153 : 0 : return flow_hw_action_handle_create(dev, MLX5_HW_INV_QUEUE,
13154 : : NULL, conf, action, NULL, err);
13155 : : }
13156 : :
13157 : : /**
13158 : : * Destroy the indirect action.
13159 : : * Release action related resources on the NIC and the memory.
13160 : : * Lock free, (mutex should be acquired by caller).
13161 : : * Dispatcher for action type specific call.
13162 : : *
13163 : : * @param[in] dev
13164 : : * Pointer to the Ethernet device structure.
13165 : : * @param[in] handle
13166 : : * The indirect action object handle to be removed.
13167 : : * @param[out] error
13168 : : * Perform verbose error reporting if not NULL. Initialized in case of
13169 : : * error only.
13170 : : *
13171 : : * @return
13172 : : * 0 on success, otherwise negative errno value.
13173 : : */
13174 : : static int
13175 : 0 : flow_hw_action_destroy(struct rte_eth_dev *dev,
13176 : : struct rte_flow_action_handle *handle,
13177 : : struct rte_flow_error *error)
13178 : : {
13179 : 0 : return flow_hw_action_handle_destroy(dev, MLX5_HW_INV_QUEUE,
13180 : : NULL, handle, NULL, error);
13181 : : }
13182 : :
13183 : : /**
13184 : : * Updates in place shared action configuration.
13185 : : *
13186 : : * @param[in] dev
13187 : : * Pointer to the Ethernet device structure.
13188 : : * @param[in] handle
13189 : : * The indirect action object handle to be updated.
13190 : : * @param[in] update
13191 : : * Action specification used to modify the action pointed by *handle*.
13192 : : * *update* could be of same type with the action pointed by the *handle*
13193 : : * handle argument, or some other structures like a wrapper, depending on
13194 : : * the indirect action type.
13195 : : * @param[out] error
13196 : : * Perform verbose error reporting if not NULL. Initialized in case of
13197 : : * error only.
13198 : : *
13199 : : * @return
13200 : : * 0 on success, otherwise negative errno value.
13201 : : */
13202 : : static int
13203 : 0 : flow_hw_action_update(struct rte_eth_dev *dev,
13204 : : struct rte_flow_action_handle *handle,
13205 : : const void *update,
13206 : : struct rte_flow_error *err)
13207 : : {
13208 : 0 : return flow_hw_action_handle_update(dev, MLX5_HW_INV_QUEUE,
13209 : : NULL, handle, update, NULL, err);
13210 : : }
13211 : :
13212 : : static int
13213 : 0 : flow_hw_action_handle_query(struct rte_eth_dev *dev, uint32_t queue,
13214 : : const struct rte_flow_op_attr *attr,
13215 : : const struct rte_flow_action_handle *handle,
13216 : : void *data, void *user_data,
13217 : : struct rte_flow_error *error)
13218 : : {
13219 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13220 : : struct mlx5_hw_q_job *job = NULL;
13221 : 0 : uint32_t act_idx = (uint32_t)(uintptr_t)handle;
13222 : 0 : uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
13223 [ # # ]: 0 : uint32_t idx = MLX5_INDIRECT_ACTION_IDX_GET(handle);
13224 : : uint32_t age_idx = act_idx & MLX5_HWS_AGE_IDX_MASK;
13225 : : int ret;
13226 : : bool push = flow_hw_action_push(attr);
13227 : : bool aso = false;
13228 : :
13229 [ # # ]: 0 : if (attr) {
13230 : : job = flow_hw_action_job_init(priv, queue, handle, user_data,
13231 : : data, MLX5_HW_Q_JOB_TYPE_QUERY,
13232 : : MLX5_HW_INDIRECT_TYPE_LEGACY, error);
13233 : : if (!job)
13234 : 0 : return -rte_errno;
13235 : : }
13236 [ # # # # : 0 : switch (type) {
# ]
13237 : 0 : case MLX5_INDIRECT_ACTION_TYPE_AGE:
13238 : 0 : ret = flow_hw_query_age(dev, age_idx, data, error);
13239 : 0 : break;
13240 : 0 : case MLX5_INDIRECT_ACTION_TYPE_COUNT:
13241 : 0 : ret = flow_hw_query_counter(dev, act_idx, data, error);
13242 : 0 : break;
13243 : 0 : case MLX5_INDIRECT_ACTION_TYPE_CT:
13244 : : aso = true;
13245 [ # # ]: 0 : if (job)
13246 : 0 : job->query.user = data;
13247 : 0 : ret = flow_hw_conntrack_query(dev, queue, idx, data,
13248 : : job, push, error);
13249 : 0 : break;
13250 : 0 : case MLX5_INDIRECT_ACTION_TYPE_QUOTA:
13251 : : aso = true;
13252 : 0 : ret = mlx5_quota_query(dev, queue, handle, data,
13253 : : job, push, error);
13254 : 0 : break;
13255 : 0 : default:
13256 : : ret = -ENOTSUP;
13257 : 0 : rte_flow_error_set(error, ENOTSUP,
13258 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13259 : : "action type not supported");
13260 : 0 : break;
13261 : : }
13262 [ # # ]: 0 : if (job)
13263 [ # # ]: 0 : flow_hw_action_finalize(dev, queue, job, push, aso, ret == 0);
13264 : : return ret;
13265 : : }
13266 : :
13267 : : static int
13268 : 0 : flow_hw_async_action_handle_query_update
13269 : : (struct rte_eth_dev *dev, uint32_t queue,
13270 : : const struct rte_flow_op_attr *attr,
13271 : : struct rte_flow_action_handle *handle,
13272 : : const void *update, void *query,
13273 : : enum rte_flow_query_update_mode qu_mode,
13274 : : void *user_data, struct rte_flow_error *error)
13275 : : {
13276 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
13277 : : bool push = flow_hw_action_push(attr);
13278 : : bool aso = false;
13279 : : struct mlx5_hw_q_job *job = NULL;
13280 : : int ret = 0;
13281 : :
13282 [ # # ]: 0 : if (attr) {
13283 : : job = flow_hw_action_job_init(priv, queue, handle, user_data,
13284 : : query,
13285 : : MLX5_HW_Q_JOB_TYPE_UPDATE_QUERY,
13286 : : MLX5_HW_INDIRECT_TYPE_LEGACY, error);
13287 : : if (!job)
13288 : 0 : return -rte_errno;
13289 : : }
13290 [ # # ]: 0 : switch (MLX5_INDIRECT_ACTION_TYPE_GET(handle)) {
13291 : 0 : case MLX5_INDIRECT_ACTION_TYPE_QUOTA:
13292 [ # # ]: 0 : if (qu_mode != RTE_FLOW_QU_QUERY_FIRST) {
13293 : 0 : ret = rte_flow_error_set
13294 : : (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION_CONF,
13295 : : NULL, "quota action must query before update");
13296 : 0 : break;
13297 : : }
13298 : : aso = true;
13299 : 0 : ret = mlx5_quota_query_update(dev, queue, handle,
13300 : : update, query, job, push, error);
13301 : 0 : break;
13302 : 0 : default:
13303 : 0 : ret = rte_flow_error_set(error, ENOTSUP,
13304 : : RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, "update and query not supportred");
13305 : : }
13306 [ # # ]: 0 : if (job)
13307 [ # # ]: 0 : flow_hw_action_finalize(dev, queue, job, push, aso, ret == 0);
13308 : : return ret;
13309 : : }
13310 : :
13311 : : static int
13312 : 0 : flow_hw_action_query(struct rte_eth_dev *dev,
13313 : : const struct rte_flow_action_handle *handle, void *data,
13314 : : struct rte_flow_error *error)
13315 : : {
13316 : 0 : return flow_hw_action_handle_query(dev, MLX5_HW_INV_QUEUE, NULL,
13317 : : handle, data, NULL, error);
13318 : : }
13319 : :
13320 : : static int
13321 : 0 : flow_hw_action_query_update(struct rte_eth_dev *dev,
13322 : : struct rte_flow_action_handle *handle,
13323 : : const void *update, void *query,
13324 : : enum rte_flow_query_update_mode qu_mode,
13325 : : struct rte_flow_error *error)
13326 : : {
13327 : 0 : return flow_hw_async_action_handle_query_update(dev, MLX5_HW_INV_QUEUE,
13328 : : NULL, handle, update,
13329 : : query, qu_mode, NULL,
13330 : : error);
13331 : : }
13332 : :
13333 : : /**
13334 : : * Get aged-out flows of a given port on the given HWS flow queue.
13335 : : *
13336 : : * @param[in] dev
13337 : : * Pointer to the Ethernet device structure.
13338 : : * @param[in] queue_id
13339 : : * Flow queue to query. Ignored when RTE_FLOW_PORT_FLAG_STRICT_QUEUE not set.
13340 : : * @param[in, out] contexts
13341 : : * The address of an array of pointers to the aged-out flows contexts.
13342 : : * @param[in] nb_contexts
13343 : : * The length of context array pointers.
13344 : : * @param[out] error
13345 : : * Perform verbose error reporting if not NULL. Initialized in case of
13346 : : * error only.
13347 : : *
13348 : : * @return
13349 : : * if nb_contexts is 0, return the amount of all aged contexts.
13350 : : * if nb_contexts is not 0 , return the amount of aged flows reported
13351 : : * in the context array, otherwise negative errno value.
13352 : : */
13353 : : static int
13354 : 0 : flow_hw_get_q_aged_flows(struct rte_eth_dev *dev, uint32_t queue_id,
13355 : : void **contexts, uint32_t nb_contexts,
13356 : : struct rte_flow_error *error)
13357 : : {
13358 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13359 : 0 : struct mlx5_age_info *age_info = GET_PORT_AGE_INFO(priv);
13360 : : struct rte_ring *r;
13361 : : int nb_flows = 0;
13362 : :
13363 [ # # ]: 0 : if (nb_contexts && !contexts)
13364 : 0 : return rte_flow_error_set(error, EINVAL,
13365 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13366 : : NULL, "empty context");
13367 [ # # ]: 0 : if (!priv->hws_age_req)
13368 : 0 : return rte_flow_error_set(error, ENOENT,
13369 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13370 : : NULL, "No aging initialized");
13371 [ # # ]: 0 : if (priv->hws_strict_queue) {
13372 : : /* Queue is invalid in sync query. Sync query and strict queueing is disallowed. */
13373 : : MLX5_ASSERT(queue_id != MLX5_HW_INV_QUEUE);
13374 [ # # ]: 0 : if (queue_id >= age_info->hw_q_age->nb_rings)
13375 : 0 : return rte_flow_error_set(error, EINVAL,
13376 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13377 : : NULL, "invalid queue id");
13378 : 0 : r = age_info->hw_q_age->aged_lists[queue_id];
13379 : : } else {
13380 : 0 : r = age_info->hw_age.aged_list;
13381 : 0 : MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
13382 : : }
13383 [ # # ]: 0 : if (nb_contexts == 0)
13384 : 0 : return rte_ring_count(r);
13385 [ # # ]: 0 : while ((uint32_t)nb_flows < nb_contexts) {
13386 : : uint32_t age_idx;
13387 : :
13388 : : if (rte_ring_dequeue_elem(r, &age_idx, sizeof(uint32_t)) < 0)
13389 : : break;
13390 : : /* get the AGE context if the aged-out index is still valid. */
13391 : 0 : contexts[nb_flows] = mlx5_hws_age_context_get(priv, age_idx);
13392 [ # # ]: 0 : if (!contexts[nb_flows])
13393 : 0 : continue;
13394 : 0 : nb_flows++;
13395 : : }
13396 : : return nb_flows;
13397 : : }
13398 : :
13399 : : /**
13400 : : * Get aged-out flows.
13401 : : *
13402 : : * This function is relevant only if RTE_FLOW_PORT_FLAG_STRICT_QUEUE isn't set.
13403 : : *
13404 : : * @param[in] dev
13405 : : * Pointer to the Ethernet device structure.
13406 : : * @param[in] contexts
13407 : : * The address of an array of pointers to the aged-out flows contexts.
13408 : : * @param[in] nb_contexts
13409 : : * The length of context array pointers.
13410 : : * @param[out] error
13411 : : * Perform verbose error reporting if not NULL. Initialized in case of
13412 : : * error only.
13413 : : *
13414 : : * @return
13415 : : * how many contexts get in success, otherwise negative errno value.
13416 : : * if nb_contexts is 0, return the amount of all aged contexts.
13417 : : * if nb_contexts is not 0 , return the amount of aged flows reported
13418 : : * in the context array.
13419 : : */
13420 : : static int
13421 : 0 : flow_hw_get_aged_flows(struct rte_eth_dev *dev, void **contexts,
13422 : : uint32_t nb_contexts, struct rte_flow_error *error)
13423 : : {
13424 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13425 : :
13426 [ # # ]: 0 : if (priv->hws_strict_queue)
13427 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_STATE, NULL,
13428 : : "Cannot get aged flows synchronously with strict queueing");
13429 : :
13430 : 0 : return flow_hw_get_q_aged_flows(dev, MLX5_HW_INV_QUEUE, contexts, nb_contexts, error);
13431 : : }
13432 : : /**
13433 : : * Initialization function for non template API which calls
13434 : : * flow_hw_configure with default values.
13435 : : * Configure non queues cause 1 queue is configured by default for inner usage.
13436 : : *
13437 : : * @param[in] dev
13438 : : * Pointer to the Ethernet device structure.
13439 : : * @param[out] error
13440 : : * Pointer to the error structure.
13441 : : *
13442 : : * @return
13443 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
13444 : : */
13445 : : int
13446 : 0 : flow_hw_init(struct rte_eth_dev *dev,
13447 : : struct rte_flow_error *error)
13448 : : {
13449 : 0 : const struct rte_flow_port_attr port_attr = {0};
13450 : 0 : const struct rte_flow_queue_attr queue_attr = {.size = MLX5_NT_DEFAULT_QUEUE_SIZE};
13451 : 0 : const struct rte_flow_queue_attr *attr_list = &queue_attr;
13452 : :
13453 : : /**
13454 : : * If user uses template and non template API:
13455 : : * User will call flow_hw_configure and non template
13456 : : * API will use the allocated actions.
13457 : : * Init function will not call flow_hw_configure.
13458 : : *
13459 : : * If user uses only non template API's:
13460 : : * Init function will call flow_hw_configure.
13461 : : * It will not allocate memory for actions.
13462 : : * When needed allocation, it will handle same as for SWS today,
13463 : : * meaning using bulk allocations and resize as needed.
13464 : : */
13465 : : /* Configure hws with default values. */
13466 : 0 : DRV_LOG(DEBUG, "Apply default configuration, zero number of queues, inner control queue size is %u",
13467 : : MLX5_NT_DEFAULT_QUEUE_SIZE);
13468 : 0 : return __flow_hw_configure(dev, &port_attr, 0, &attr_list, true, error);
13469 : : }
13470 : :
13471 : 0 : static int flow_hw_prepare(struct rte_eth_dev *dev,
13472 : : const struct rte_flow_action actions[] __rte_unused,
13473 : : enum mlx5_flow_type type,
13474 : : struct rte_flow_hw **flow,
13475 : : struct rte_flow_error *error)
13476 : : {
13477 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13478 : 0 : uint32_t idx = 0;
13479 : :
13480 : : /*
13481 : : * Notice pool idx size = (sizeof(struct rte_flow_hw)
13482 : : * + sizeof(struct rte_flow_nt2hws)) for HWS mode.
13483 : : */
13484 : 0 : *flow = mlx5_ipool_zmalloc(priv->flows[type], &idx);
13485 [ # # ]: 0 : if (!(*flow))
13486 : 0 : return rte_flow_error_set(error, ENOMEM,
13487 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13488 : : "cannot allocate flow memory");
13489 : : /* Allocating 2 structures in one pool slot, updating nt2hw pointer.*/
13490 : 0 : (*flow)->nt2hws = (struct rte_flow_nt2hws *)
13491 : 0 : ((uintptr_t)(*flow) + sizeof(struct rte_flow_hw));
13492 : 0 : (*flow)->idx = idx;
13493 : 0 : (*flow)->nt2hws->flow_aux = mlx5_malloc(MLX5_MEM_ZERO, sizeof(struct rte_flow_hw_aux),
13494 : 0 : RTE_CACHE_LINE_SIZE, rte_dev_numa_node(dev->device));
13495 [ # # ]: 0 : if (!(*flow)->nt2hws->flow_aux)
13496 : 0 : return rte_flow_error_set(error, ENOMEM,
13497 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13498 : : "cannot allocate flow aux memory");
13499 : : return 0;
13500 : : }
13501 : :
13502 : : static inline void
13503 : 0 : flow_hw_set_dv_fields(struct rte_flow_template_table_attr *table_attr, uint32_t fdb_unified_en,
13504 : : bool *root, uint8_t *ft_type, uint64_t *flags)
13505 : : {
13506 [ # # ]: 0 : if (table_attr->flow_attr.transfer)
13507 : 0 : *ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
13508 : : else
13509 : 0 : *ft_type = table_attr->flow_attr.egress ?
13510 : 0 : MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
13511 : : MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
13512 : 0 : uint32_t group = table_attr->flow_attr.group;
13513 : 0 : *root = group ? 0 : 1;
13514 : 0 : *flags = mlx5_hw_act_flag[!!group][get_mlx5dr_table_type(&table_attr->flow_attr,
13515 : : table_attr->specialize,
13516 : : fdb_unified_en)];
13517 : 0 : }
13518 : :
13519 : : static int
13520 : 0 : flow_hw_modify_hdr_resource_register
13521 : : (struct rte_eth_dev *dev,
13522 : : struct rte_flow_template_table *table,
13523 : : struct mlx5_hw_actions *hw_acts,
13524 : : struct rte_flow_hw *dev_flow,
13525 : : struct rte_flow_error *error)
13526 : : {
13527 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
13528 : : bool unified_fdb = is_unified_fdb(priv);
13529 : 0 : struct rte_flow_template_table_attr *table_attr = &table->cfg.attr;
13530 : 0 : struct mlx5_flow_dv_modify_hdr_resource *dv_resource_ptr = NULL;
13531 : : union {
13532 : : struct mlx5_flow_dv_modify_hdr_resource dv_resource;
13533 : : uint8_t data[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
13534 : : sizeof(struct mlx5_modification_cmd) * MLX5_MHDR_MAX_CMD];
13535 : : } dummy;
13536 : : int ret;
13537 : :
13538 [ # # ]: 0 : if (hw_acts->mhdr) {
13539 : 0 : dummy.dv_resource.actions_num = hw_acts->mhdr->mhdr_cmds_num;
13540 : 0 : memcpy(dummy.dv_resource.actions, hw_acts->mhdr->mhdr_cmds,
13541 : 0 : sizeof(struct mlx5_modification_cmd) * dummy.dv_resource.actions_num);
13542 : : } else {
13543 : : return 0;
13544 : : }
13545 : 0 : flow_hw_set_dv_fields(table_attr, unified_fdb,
13546 : : &dummy.dv_resource.root, &dummy.dv_resource.ft_type,
13547 : : &dummy.dv_resource.flags);
13548 : 0 : dummy.dv_resource.flags |= MLX5DR_ACTION_FLAG_SHARED;
13549 : 0 : ret = __flow_modify_hdr_resource_register(dev, &dummy.dv_resource,
13550 : : &dv_resource_ptr, error);
13551 [ # # ]: 0 : if (ret)
13552 : : return ret;
13553 : : MLX5_ASSERT(dv_resource_ptr);
13554 : 0 : dev_flow->nt2hws->modify_hdr = dv_resource_ptr;
13555 : : /* keep action for the rule construction. */
13556 : 0 : hw_acts->rule_acts[hw_acts->mhdr->pos].action = dv_resource_ptr->action;
13557 : : /* Bulk size is 1, so index is 1. */
13558 : 0 : dev_flow->res_idx = 1;
13559 : 0 : return 0;
13560 : : }
13561 : :
13562 : : static int
13563 : 0 : flow_hw_encap_decap_resource_register
13564 : : (struct rte_eth_dev *dev,
13565 : : struct rte_flow_template_table *table,
13566 : : struct mlx5_hw_actions *hw_acts,
13567 : : struct rte_flow_hw *dev_flow,
13568 : : struct rte_flow_error *error)
13569 : : {
13570 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
13571 : : bool unified_fdb = is_unified_fdb(priv);
13572 : 0 : struct rte_flow_template_table_attr *table_attr = &table->cfg.attr;
13573 : 0 : struct mlx5_flow_dv_encap_decap_resource *dv_resource_ptr = NULL;
13574 : : struct mlx5_flow_dv_encap_decap_resource dv_resource;
13575 : : struct mlx5_tbl_multi_pattern_ctx *mpctx = &table->mpctx;
13576 : : int ret;
13577 : : bool is_root;
13578 : : int ix;
13579 : :
13580 [ # # ]: 0 : if (hw_acts->encap_decap)
13581 : 0 : dv_resource.reformat_type = hw_acts->encap_decap->action_type;
13582 : : else
13583 : : return 0;
13584 : 0 : flow_hw_set_dv_fields(table_attr, unified_fdb, &is_root, &dv_resource.ft_type,
13585 : : &dv_resource.flags);
13586 [ # # ]: 0 : ix = mlx5_bwc_multi_pattern_reformat_to_index((enum mlx5dr_action_type)
13587 : : dv_resource.reformat_type);
13588 : : if (ix < 0)
13589 : 0 : return ix;
13590 [ # # ]: 0 : if (hw_acts->encap_decap->shared) {
13591 : 0 : dv_resource.size = hw_acts->encap_decap->data_size;
13592 : : MLX5_ASSERT(dv_resource.size <= MLX5_ENCAP_MAX_LEN);
13593 : 0 : memcpy(&dv_resource.buf, hw_acts->encap_decap->data, dv_resource.size);
13594 : 0 : dv_resource.flags |= MLX5DR_ACTION_FLAG_SHARED;
13595 : : } else {
13596 : 0 : typeof(mpctx->reformat[0]) *reformat = mpctx->reformat + ix;
13597 [ # # ]: 0 : if (!reformat->elements_num)
13598 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
13599 : : NULL, "No reformat action exist in the table.");
13600 : 0 : dv_resource.size = reformat->reformat_hdr->sz;
13601 : : MLX5_ASSERT(dv_resource.size <= MLX5_ENCAP_MAX_LEN);
13602 : 0 : memcpy(&dv_resource.buf, reformat->reformat_hdr->data, dv_resource.size);
13603 : : }
13604 : 0 : ret = __flow_encap_decap_resource_register(dev, &dv_resource, is_root,
13605 : : &dv_resource_ptr, error);
13606 [ # # ]: 0 : if (ret)
13607 : : return ret;
13608 : : MLX5_ASSERT(dv_resource_ptr);
13609 : 0 : dev_flow->nt2hws->rix_encap_decap = dv_resource_ptr->idx;
13610 : : /* keep action for the rule construction. */
13611 [ # # ]: 0 : if (hw_acts->encap_decap->shared)
13612 : 0 : hw_acts->rule_acts[hw_acts->encap_decap_pos].action = dv_resource_ptr->action;
13613 : : else
13614 : 0 : mpctx->segments[0].reformat_action[ix] = dv_resource_ptr->action;
13615 : : /* Bulk size is 1, so index is 1. */
13616 : 0 : dev_flow->res_idx = 1;
13617 : 0 : return 0;
13618 : : }
13619 : :
13620 : : static enum rte_flow_action_type
13621 : : flow_nta_get_indirect_action_type(const struct rte_flow_action *action)
13622 : : {
13623 [ # # ]: 0 : switch (MLX5_INDIRECT_ACTION_TYPE_GET(action->conf)) {
13624 : : case MLX5_INDIRECT_ACTION_TYPE_RSS:
13625 : : return RTE_FLOW_ACTION_TYPE_RSS;
13626 : : case MLX5_INDIRECT_ACTION_TYPE_AGE:
13627 : : return RTE_FLOW_ACTION_TYPE_AGE;
13628 : : case MLX5_INDIRECT_ACTION_TYPE_COUNT:
13629 : : return RTE_FLOW_ACTION_TYPE_COUNT;
13630 : : case MLX5_INDIRECT_ACTION_TYPE_CT:
13631 : : return RTE_FLOW_ACTION_TYPE_CONNTRACK;
13632 : : default:
13633 : : break;
13634 : : }
13635 : : return RTE_FLOW_ACTION_TYPE_END;
13636 : : }
13637 : :
13638 : : static void
13639 : : flow_nta_set_mh_mask_conf(const struct rte_flow_action_modify_field *action_conf,
13640 : : struct rte_flow_action_modify_field *mask_conf)
13641 : : {
13642 : : memset(mask_conf, 0xff, sizeof(*mask_conf));
13643 : 0 : mask_conf->operation = action_conf->operation;
13644 : 0 : mask_conf->dst.field = action_conf->dst.field;
13645 : 0 : mask_conf->src.field = action_conf->src.field;
13646 : : }
13647 : :
13648 : : union actions_conf {
13649 : : struct rte_flow_action_modify_field modify_field;
13650 : : struct rte_flow_action_raw_encap raw_encap;
13651 : : struct rte_flow_action_vxlan_encap vxlan_encap;
13652 : : struct rte_flow_action_nvgre_encap nvgre_encap;
13653 : : };
13654 : :
13655 : : static int
13656 : 0 : flow_nta_build_template_mask(const struct rte_flow_action actions[],
13657 : : struct rte_flow_action masks[MLX5_HW_MAX_ACTS],
13658 : : union actions_conf mask_conf[MLX5_HW_MAX_ACTS])
13659 : : {
13660 : : int i;
13661 : :
13662 [ # # # # ]: 0 : for (i = 0; i == 0 || actions[i - 1].type != RTE_FLOW_ACTION_TYPE_END; i++) {
13663 : 0 : const struct rte_flow_action *action = &actions[i];
13664 : 0 : struct rte_flow_action *mask = &masks[i];
13665 : 0 : union actions_conf *conf = &mask_conf[i];
13666 : :
13667 : 0 : mask->type = action->type;
13668 [ # # # # : 0 : switch (action->type) {
# # # ]
13669 : : case RTE_FLOW_ACTION_TYPE_INDIRECT:
13670 : 0 : mask->type = flow_nta_get_indirect_action_type(action);
13671 [ # # ]: 0 : if (!mask->type)
13672 : : return -EINVAL;
13673 : : break;
13674 : 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
13675 : 0 : flow_nta_set_mh_mask_conf(action->conf, (void *)conf);
13676 : 0 : mask->conf = conf;
13677 : 0 : break;
13678 : : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
13679 : : /* This mask will set this action as shared. */
13680 : : memset(conf, 0xff, sizeof(struct rte_flow_action_raw_encap));
13681 : 0 : mask->conf = conf;
13682 : 0 : break;
13683 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
13684 : : /* This mask will set this action as shared. */
13685 : 0 : conf->vxlan_encap.definition =
13686 : : ((const struct rte_flow_action_vxlan_encap *)
13687 : 0 : action->conf)->definition;
13688 : 0 : mask->conf = conf;
13689 : 0 : break;
13690 : 0 : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
13691 : : /* This mask will set this action as shared. */
13692 : 0 : conf->nvgre_encap.definition =
13693 : : ((const struct rte_flow_action_nvgre_encap *)
13694 : 0 : action->conf)->definition;
13695 : 0 : mask->conf = conf;
13696 : 0 : break;
13697 : : case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
13698 : : memset(conf, 0xff, sizeof(struct rte_flow_action_of_set_vlan_vid));
13699 : 0 : mask->conf = conf;
13700 : 0 : break;
13701 : : default:
13702 : : break;
13703 : : }
13704 : : }
13705 : : return 0;
13706 : : #undef NTA_CHECK_CONF_BUF_SIZE
13707 : : }
13708 : :
13709 : : static int
13710 : 0 : flow_hw_translate_flow_actions(struct rte_eth_dev *dev,
13711 : : const struct rte_flow_attr *attr,
13712 : : const struct rte_flow_action actions[],
13713 : : struct rte_flow_hw *flow,
13714 : : struct mlx5_flow_hw_action_params *ap,
13715 : : struct mlx5_hw_actions *hw_acts,
13716 : : uint64_t item_flags, uint64_t action_flags,
13717 : : bool external,
13718 : : struct rte_flow_error *error)
13719 : : {
13720 : : int ret = 0;
13721 : 0 : uint32_t src_group = 0;
13722 : : enum mlx5dr_table_type table_type;
13723 : : struct mlx5_flow_group grp;
13724 : : struct rte_flow_actions_template *at = NULL;
13725 : 0 : struct rte_flow_actions_template_attr template_attr = {
13726 : 0 : .egress = attr->egress,
13727 : 0 : .ingress = attr->ingress,
13728 : 0 : .transfer = attr->transfer,
13729 : : };
13730 : : struct rte_flow_action masks[MLX5_HW_MAX_ACTS];
13731 : : union actions_conf mask_conf[MLX5_HW_MAX_ACTS];
13732 : :
13733 : : RTE_SET_USED(action_flags);
13734 : : memset(masks, 0, sizeof(masks));
13735 : : memset(mask_conf, 0, sizeof(mask_conf));
13736 : : /* Only set the needed fields explicitly. */
13737 : 0 : struct mlx5_flow_workspace *wks = mlx5_flow_push_thread_workspace();
13738 : : struct rte_flow_template_table *table;
13739 : :
13740 : : /*
13741 : : * Notice All direct actions will be unmasked,
13742 : : * except for modify header and encap,
13743 : : * and therefore will be parsed as part of action construct.
13744 : : * Modify header is always shared in HWS,
13745 : : * encap is masked such that it will be treated as shared.
13746 : : * shared actions will be parsed as part of template translation
13747 : : * and not during action construct.
13748 : : */
13749 [ # # ]: 0 : if (!wks)
13750 : 0 : return rte_flow_error_set(error, ENOMEM,
13751 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13752 : : NULL,
13753 : : "failed to push flow workspace");
13754 : 0 : table = wks->table;
13755 : 0 : flow_nta_build_template_mask(actions, masks, mask_conf);
13756 : : /* The group in the attribute translation was done in advance. */
13757 : 0 : ret = __translate_group(dev, attr, external, attr->group, &src_group, error);
13758 [ # # ]: 0 : if (ret)
13759 : : return ret;
13760 [ # # ]: 0 : if (attr->transfer)
13761 : : table_type = MLX5DR_TABLE_TYPE_FDB;
13762 [ # # ]: 0 : else if (attr->egress)
13763 : : table_type = MLX5DR_TABLE_TYPE_NIC_TX;
13764 : : else
13765 : : table_type = MLX5DR_TABLE_TYPE_NIC_RX;
13766 : 0 : at = __flow_hw_actions_template_create(dev, &template_attr, actions, masks, true, error);
13767 [ # # ]: 0 : if (!at) {
13768 : 0 : ret = -rte_errno;
13769 : 0 : goto end;
13770 : : }
13771 : 0 : grp.group_id = src_group;
13772 : 0 : table->grp = &grp;
13773 : 0 : table->type = table_type;
13774 : 0 : table->cfg.external = external;
13775 : 0 : table->nb_action_templates = 1;
13776 : 0 : memcpy(&table->cfg.attr.flow_attr, attr, sizeof(*attr));
13777 : 0 : table->cfg.attr.flow_attr.group = src_group;
13778 : 0 : table->ats[0].action_template = at;
13779 : 0 : ret = __flow_hw_translate_actions_template(dev, &table->cfg, hw_acts, at,
13780 : : &table->mpctx, true, error);
13781 [ # # ]: 0 : if (ret)
13782 : 0 : goto end;
13783 : : /* handle bulk actions register. */
13784 : 0 : ret = flow_hw_encap_decap_resource_register(dev, table, hw_acts, flow, error);
13785 [ # # ]: 0 : if (ret)
13786 : 0 : goto end;
13787 : 0 : ret = flow_hw_modify_hdr_resource_register(dev, table, hw_acts, flow, error);
13788 [ # # ]: 0 : if (ret)
13789 : 0 : goto end;
13790 : 0 : table->ats[0].acts = *hw_acts;
13791 : 0 : ret = flow_hw_actions_construct(dev, flow, ap,
13792 : : &table->ats[0], item_flags, table,
13793 [ # # ]: 0 : actions, hw_acts->rule_acts, 0, error);
13794 [ # # ]: 0 : if (ret)
13795 : 0 : goto end;
13796 : 0 : goto end;
13797 : 0 : end:
13798 [ # # ]: 0 : if (ret)
13799 : : /* Make sure that there is no garbage in the actions. */
13800 : 0 : __flow_hw_action_template_destroy(dev, hw_acts);
13801 : : else
13802 : 0 : __flow_hw_act_data_flush(dev, hw_acts);
13803 [ # # ]: 0 : if (at)
13804 : 0 : mlx5_free(at);
13805 : 0 : mlx5_flow_pop_thread_workspace();
13806 : 0 : return ret;
13807 : : }
13808 : :
13809 : : static int
13810 : 0 : flow_hw_unregister_matcher(struct rte_eth_dev *dev,
13811 : : struct mlx5_flow_dv_matcher *matcher)
13812 : : {
13813 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13814 : 0 : struct mlx5_flow_group *group = matcher->group;
13815 : : int ret = 0;
13816 : :
13817 [ # # ]: 0 : if (group) {
13818 [ # # ]: 0 : if (matcher->matcher_object)
13819 : 0 : ret |= mlx5_list_unregister(group->matchers, &matcher->entry);
13820 : 0 : ret |= mlx5_hlist_unregister(priv->sh->groups, &group->entry);
13821 : : }
13822 : 0 : return ret;
13823 : : }
13824 : :
13825 : 0 : static int flow_hw_register_matcher(struct rte_eth_dev *dev,
13826 : : const struct rte_flow_attr *attr,
13827 : : const struct rte_flow_item items[],
13828 : : bool external,
13829 : : struct rte_flow_hw *flow,
13830 : : struct mlx5_flow_dv_matcher *matcher,
13831 : : struct rte_flow_error *error)
13832 : : {
13833 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13834 : 0 : struct rte_flow_error sub_error = {
13835 : : .type = RTE_FLOW_ERROR_TYPE_NONE,
13836 : : .cause = NULL,
13837 : : .message = NULL,
13838 : : };
13839 : 0 : struct rte_flow_attr flow_attr = *attr;
13840 : 0 : uint32_t specialize = 0; /* No unified FDB. */
13841 : 0 : struct mlx5_flow_cb_ctx ctx = {
13842 : : .dev = dev,
13843 : : .error = &sub_error,
13844 : : .data = &flow_attr,
13845 : : .data2 = &specialize,
13846 : : };
13847 : : void *items_ptr = &items;
13848 : 0 : struct mlx5_flow_cb_ctx matcher_ctx = {
13849 : : .error = &sub_error,
13850 : : .data = matcher,
13851 : : .data2 = items_ptr,
13852 : : };
13853 : : struct mlx5_list_entry *group_entry = NULL;
13854 : : struct mlx5_list_entry *matcher_entry = NULL;
13855 : : struct mlx5_flow_dv_matcher *resource;
13856 : : struct mlx5_list *matchers_list;
13857 : : struct mlx5_flow_group *flow_group;
13858 : : int ret;
13859 : :
13860 : :
13861 : 0 : matcher->crc = rte_raw_cksum((const void *)matcher->mask.buf,
13862 : : matcher->mask.size);
13863 : 0 : matcher->priority = attr->priority;
13864 : 0 : ret = __translate_group(dev, attr, external, attr->group, &flow_attr.group, error);
13865 [ # # ]: 0 : if (ret)
13866 : : return ret;
13867 : :
13868 : : /* Register the flow group. */
13869 : 0 : group_entry = mlx5_hlist_register(priv->sh->groups, flow_attr.group, &ctx);
13870 [ # # ]: 0 : if (!group_entry)
13871 : 0 : goto error;
13872 : : flow_group = container_of(group_entry, struct mlx5_flow_group, entry);
13873 : :
13874 : 0 : matchers_list = flow_group->matchers;
13875 : 0 : matcher->group = flow_group;
13876 : 0 : matcher_entry = mlx5_list_register(matchers_list, &matcher_ctx);
13877 [ # # ]: 0 : if (!matcher_entry)
13878 : 0 : goto error;
13879 : : resource = container_of(matcher_entry, typeof(*resource), entry);
13880 : 0 : flow->nt2hws->matcher = resource;
13881 : 0 : return 0;
13882 : :
13883 : 0 : error:
13884 [ # # ]: 0 : if (group_entry)
13885 : 0 : mlx5_hlist_unregister(priv->sh->groups, group_entry);
13886 [ # # ]: 0 : if (error) {
13887 [ # # ]: 0 : if (sub_error.type != RTE_FLOW_ERROR_TYPE_NONE)
13888 : : rte_memcpy(error, &sub_error, sizeof(sub_error));
13889 : : }
13890 : 0 : return rte_flow_error_set(error, rte_errno,
13891 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13892 : : NULL, "fail to register matcher");
13893 : : }
13894 : :
13895 : : static int
13896 : 0 : flow_hw_allocate_actions(struct rte_eth_dev *dev,
13897 : : uint64_t action_flags,
13898 : : struct rte_flow_error *error)
13899 : : {
13900 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13901 : : int ret;
13902 : : uint obj_num;
13903 : :
13904 : 0 : error->type = RTE_FLOW_ERROR_TYPE_NONE;
13905 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_AGE) {
13906 : : /* If no age objects were previously allocated. */
13907 [ # # ]: 0 : if (!priv->hws_age_req) {
13908 : : /* If no counters were previously allocated. */
13909 [ # # ]: 0 : if (!priv->hws_cpool) {
13910 : 0 : obj_num = MLX5_CNT_NT_MAX(priv);
13911 : 0 : ret = mlx5_hws_cnt_pool_create(dev, obj_num,
13912 : 0 : priv->nb_queue,
13913 : : NULL, error);
13914 [ # # ]: 0 : if (ret)
13915 : 0 : goto err;
13916 : : }
13917 : : /* Allocate same number of counters. */
13918 : 0 : ret = mlx5_hws_age_pool_init(dev, priv->hws_cpool->cfg.request_num,
13919 : 0 : priv->nb_queue, false);
13920 [ # # ]: 0 : if (ret)
13921 : 0 : goto err;
13922 : : }
13923 : : }
13924 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_COUNT) {
13925 : : /* If no counters were previously allocated. */
13926 [ # # ]: 0 : if (!priv->hws_cpool) {
13927 : 0 : obj_num = MLX5_CNT_NT_MAX(priv);
13928 : 0 : ret = mlx5_hws_cnt_pool_create(dev, obj_num,
13929 : 0 : priv->nb_queue, NULL,
13930 : : error);
13931 [ # # ]: 0 : if (ret)
13932 : 0 : goto err;
13933 : : }
13934 : : }
13935 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_CT) {
13936 : : /* If no CT were previously allocated. */
13937 [ # # ]: 0 : if (!priv->hws_ctpool) {
13938 : 0 : obj_num = MLX5_CT_NT_MAX(priv);
13939 : 0 : ret = mlx5_flow_ct_init(dev, obj_num, priv->nb_queue);
13940 [ # # ]: 0 : if (ret)
13941 : 0 : goto err;
13942 : : }
13943 : : }
13944 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_METER) {
13945 : : /* If no meters were previously allocated. */
13946 [ # # ]: 0 : if (!priv->hws_mpool) {
13947 : 0 : obj_num = MLX5_MTR_NT_MAX(priv);
13948 : 0 : ret = mlx5_flow_meter_init(dev, obj_num, 0, 0,
13949 : : priv->nb_queue);
13950 [ # # ]: 0 : if (ret)
13951 : 0 : goto err;
13952 : : }
13953 : : }
13954 : : return 0;
13955 : 0 : err:
13956 [ # # ]: 0 : if (ret && error->type != RTE_FLOW_ERROR_TYPE_NONE)
13957 : : return ret;
13958 : 0 : return rte_flow_error_set(error, ret,
13959 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13960 : : NULL, "fail to allocate actions");
13961 : : }
13962 : :
13963 : 0 : static int flow_hw_apply(const struct rte_flow_item items[],
13964 : : struct mlx5dr_rule_action rule_actions[],
13965 : : struct rte_flow_hw *flow,
13966 : : struct rte_flow_error *error)
13967 : : {
13968 : : struct mlx5dr_bwc_rule *rule = NULL;
13969 : :
13970 : 0 : rule = mlx5dr_bwc_rule_create((struct mlx5dr_bwc_matcher *)
13971 : 0 : flow->nt2hws->matcher->matcher_object,
13972 : : items, rule_actions);
13973 : 0 : flow->nt2hws->nt_rule = rule;
13974 [ # # ]: 0 : if (!rule) {
13975 : 0 : return rte_flow_error_set(error, EINVAL,
13976 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13977 : : NULL, "fail to create rte flow");
13978 : : }
13979 : : return 0;
13980 : : }
13981 : :
13982 : : #ifdef HAVE_MLX5_HWS_SUPPORT
13983 : : /**
13984 : : * Create a flow.
13985 : : *
13986 : : * @param[in] dev
13987 : : * Pointer to Ethernet device.
13988 : : * @param[in] type
13989 : : * Flow type.
13990 : : * @param[in] attr
13991 : : * Flow rule attributes.
13992 : : * @param[in] items
13993 : : * Pattern specification (list terminated by the END pattern item).
13994 : : * @param[in] actions
13995 : : * Associated actions (list terminated by the END action).
13996 : : * @param[in] external
13997 : : * This flow rule is created by request external to PMD.
13998 : : * @param[out] flow
13999 : : * Flow pointer
14000 : : * @param[out] error
14001 : : * Perform verbose error reporting if not NULL.
14002 : : *
14003 : : * @return
14004 : : * 0 on success, negative errno value otherwise and rte_errno set.
14005 : : */
14006 : : int
14007 : 0 : flow_hw_create_flow(struct rte_eth_dev *dev, enum mlx5_flow_type type,
14008 : : const struct rte_flow_attr *attr,
14009 : : const struct rte_flow_item items[],
14010 : : const struct rte_flow_action actions[],
14011 : : uint64_t item_flags, uint64_t action_flags, bool external,
14012 : : struct rte_flow_hw **flow, struct rte_flow_error *error)
14013 : : {
14014 : : int ret;
14015 : 0 : struct mlx5_hw_actions hw_act = { { NULL } };
14016 : : struct mlx5_flow_hw_action_params ap;
14017 : 0 : struct mlx5_flow_dv_matcher matcher = {
14018 : : .mask = {
14019 : : .size = sizeof(matcher.mask.buf),
14020 : : },
14021 : : };
14022 : : uint32_t tbl_type;
14023 : :
14024 : 0 : struct mlx5_flow_attr flow_attr = {
14025 : 0 : .port_id = dev->data->port_id,
14026 : 0 : .group = attr->group,
14027 : 0 : .priority = attr->priority,
14028 : : .rss_level = 0,
14029 : : .act_flags = action_flags,
14030 : : .tbl_type = 0,
14031 : : };
14032 : :
14033 [ # # ]: 0 : if (attr->transfer)
14034 : : tbl_type = MLX5DR_TABLE_TYPE_FDB;
14035 [ # # ]: 0 : else if (attr->egress)
14036 : : tbl_type = MLX5DR_TABLE_TYPE_NIC_TX;
14037 : : else
14038 : : tbl_type = MLX5DR_TABLE_TYPE_NIC_RX;
14039 : 0 : flow_attr.tbl_type = tbl_type;
14040 : :
14041 : : /* Allocate needed memory. */
14042 : 0 : ret = flow_hw_prepare(dev, actions, type, flow, error);
14043 [ # # ]: 0 : if (ret)
14044 : 0 : goto error;
14045 : :
14046 : : /* TODO TBD flow_hw_handle_tunnel_offload(). */
14047 : 0 : (*flow)->nt_rule = true;
14048 : 0 : (*flow)->nt2hws->matcher = &matcher;
14049 : 0 : ret = __flow_dv_translate_items_hws(items, &flow_attr, &matcher.mask.buf,
14050 : : MLX5_SET_MATCHER_HS_M, NULL,
14051 : : NULL, true, error);
14052 : :
14053 [ # # ]: 0 : if (ret)
14054 : 0 : goto error;
14055 : :
14056 [ # # # # ]: 0 : if (item_flags & MLX5_FLOW_LAYER_ECPRI && !mlx5_flex_parser_ecpri_exist(dev))
14057 [ # # ]: 0 : if (mlx5_flex_parser_ecpri_alloc(dev)) {
14058 : 0 : rte_flow_error_set(error, EIO,
14059 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14060 : : NULL,
14061 : : "failed to create Flex parser "
14062 : : "profile for ECPRI");
14063 : 0 : goto error;
14064 : : }
14065 : 0 : ret = flow_hw_register_matcher(dev, attr, items, external, *flow, &matcher, error);
14066 [ # # ]: 0 : if (ret) {
14067 [ # # ]: 0 : if (rte_errno == E2BIG)
14068 : 0 : rte_flow_error_set(error, E2BIG, RTE_FLOW_ERROR_TYPE_ITEM, NULL,
14069 : : "flow pattern is too big");
14070 : 0 : goto error;
14071 : : }
14072 : :
14073 : : /*
14074 : : * ASO allocation – iterating on actions list to allocate missing resources.
14075 : : * In the future when validate function in hws will be added,
14076 : : * The output actions bit mask instead of
14077 : : * looping on the actions array twice.
14078 : : */
14079 : 0 : ret = flow_hw_allocate_actions(dev, action_flags, error);
14080 [ # # ]: 0 : if (ret)
14081 : 0 : goto error;
14082 : :
14083 : : /* Note: the actions should be saved in the sub-flow rule itself for reference. */
14084 : 0 : ret = flow_hw_translate_flow_actions(dev, attr, actions, *flow, &ap, &hw_act,
14085 : : item_flags, action_flags, external, error);
14086 [ # # ]: 0 : if (ret)
14087 : 0 : goto error;
14088 : :
14089 : : /*
14090 : : * If the flow is external (from application) OR device is started,
14091 : : * OR mreg discover, then apply immediately.
14092 : : */
14093 [ # # # # ]: 0 : if (external || dev->data->dev_started ||
14094 [ # # ]: 0 : (attr->group == MLX5_FLOW_MREG_CP_TABLE_GROUP &&
14095 [ # # ]: 0 : attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR)) {
14096 : 0 : ret = flow_hw_apply(items, hw_act.rule_acts, *flow, error);
14097 [ # # ]: 0 : if (ret)
14098 : 0 : goto error;
14099 : : }
14100 : : ret = 0;
14101 : 0 : error:
14102 : : /*
14103 : : * Release memory allocated.
14104 : : * Cannot use __flow_hw_actions_release(dev, &hw_act);
14105 : : * since it destroys the actions as well.
14106 : : */
14107 [ # # ]: 0 : if (hw_act.encap_decap)
14108 : 0 : mlx5_free(hw_act.encap_decap);
14109 [ # # ]: 0 : if (hw_act.push_remove)
14110 : 0 : mlx5_free(hw_act.push_remove);
14111 [ # # ]: 0 : if (hw_act.mhdr)
14112 : 0 : mlx5_free(hw_act.mhdr);
14113 : 0 : return ret;
14114 : : }
14115 : : #endif
14116 : :
14117 : : void
14118 : 0 : flow_hw_destroy(struct rte_eth_dev *dev, struct rte_flow_hw *flow)
14119 : : {
14120 : : int ret;
14121 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14122 : :
14123 [ # # # # ]: 0 : if (!flow || !flow->nt2hws)
14124 : : return;
14125 : :
14126 [ # # ]: 0 : if (flow->nt2hws->nt_rule) {
14127 : 0 : ret = mlx5dr_bwc_rule_destroy(flow->nt2hws->nt_rule);
14128 [ # # ]: 0 : if (ret)
14129 : 0 : DRV_LOG(ERR, "bwc rule destroy failed");
14130 : 0 : flow->nt2hws->nt_rule = NULL;
14131 : : }
14132 [ # # ]: 0 : flow->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_DESTROY;
14133 : : /* Notice this function does not handle shared/static actions. */
14134 : : hw_cmpl_flow_update_or_destroy(dev, flow, 0, NULL);
14135 : :
14136 : : /**
14137 : : * TODO: TBD - Release tunnel related memory allocations(mlx5_flow_tunnel_free)
14138 : : * – needed only if supporting tunnel offloads, notice update RX queue flags in SWS.
14139 : : */
14140 : :
14141 : : /**
14142 : : * Notice matcher destroy will take place when matcher's list is destroyed
14143 : : * , same as for DV.
14144 : : */
14145 [ # # ]: 0 : if (flow->nt2hws->flow_aux) {
14146 : 0 : mlx5_free(flow->nt2hws->flow_aux);
14147 : 0 : flow->nt2hws->flow_aux = NULL;
14148 : : }
14149 [ # # ]: 0 : if (flow->nt2hws->rix_encap_decap) {
14150 : 0 : flow_encap_decap_resource_release(dev, flow->nt2hws->rix_encap_decap);
14151 : 0 : flow->nt2hws->rix_encap_decap = 0;
14152 : : }
14153 [ # # ]: 0 : if (flow->nt2hws->modify_hdr) {
14154 : : MLX5_ASSERT(flow->nt2hws->modify_hdr->action);
14155 : 0 : mlx5_hlist_unregister(priv->sh->modify_cmds,
14156 : : &flow->nt2hws->modify_hdr->entry);
14157 : 0 : flow->nt2hws->modify_hdr = NULL;
14158 : : }
14159 [ # # ]: 0 : if (flow->nt2hws->matcher) {
14160 : 0 : flow_hw_unregister_matcher(dev, flow->nt2hws->matcher);
14161 : 0 : flow->nt2hws->matcher = NULL;
14162 : : }
14163 [ # # ]: 0 : if (flow->nt2hws->sample_release_ctx != NULL) {
14164 : 0 : mlx5_nta_sample_mirror_entry_release(dev, flow->nt2hws->sample_release_ctx);
14165 : 0 : flow->nt2hws->sample_release_ctx = NULL;
14166 : : }
14167 : : }
14168 : :
14169 : : #ifdef HAVE_MLX5_HWS_SUPPORT
14170 : : /**
14171 : : * Destroy a flow.
14172 : : *
14173 : : * @param[in] dev
14174 : : * Pointer to Ethernet device.
14175 : : * @param[in] type
14176 : : * Flow type.
14177 : : * @param[in] flow_addr
14178 : : * Address of flow to destroy.
14179 : : */
14180 : : void
14181 : 0 : flow_hw_list_destroy(struct rte_eth_dev *dev, enum mlx5_flow_type type,
14182 : : uintptr_t flow_addr)
14183 : : {
14184 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14185 : 0 : struct rte_flow_hw *flow = (struct rte_flow_hw *)flow_addr;
14186 : : struct mlx5_nta_rss_flow_head head = { .slh_first = flow };
14187 : :
14188 [ # # # # : 0 : if (!flow || !flow->nt2hws || flow->nt2hws->chaned_flow)
# # ]
14189 : : return;
14190 : 0 : mlx5_flow_nta_del_copy_action(dev, flow->nt2hws->rix_mreg_copy);
14191 [ # # ]: 0 : while (!SLIST_EMPTY(&head)) {
14192 : : flow = SLIST_FIRST(&head);
14193 : 0 : SLIST_REMOVE_HEAD(&head, nt2hws->next);
14194 : 0 : flow_hw_destroy(dev, flow);
14195 : : /* Release flow memory by idx */
14196 : 0 : mlx5_ipool_free(priv->flows[type], flow->idx);
14197 : : }
14198 : : }
14199 : : #endif
14200 : :
14201 : : /**
14202 : : * Create a flow.
14203 : : *
14204 : : * @param[in] dev
14205 : : * Pointer to Ethernet device.
14206 : : * @param[in] type
14207 : : * Flow type.
14208 : : * @param[in] attr
14209 : : * Flow rule attributes.
14210 : : * @param[in] items
14211 : : * Pattern specification (list terminated by the END pattern item).
14212 : : * @param[in] actions
14213 : : * Associated actions (list terminated by the END action).
14214 : : * @param[in] external
14215 : : * This flow rule is created by request external to PMD.
14216 : : * @param[out] error
14217 : : * Perform verbose error reporting if not NULL.
14218 : : *
14219 : : * @return
14220 : : * A flow addr on success, 0 otherwise and rte_errno is set.
14221 : : */
14222 : 0 : static uintptr_t flow_hw_list_create(struct rte_eth_dev *dev,
14223 : : enum mlx5_flow_type type,
14224 : : const struct rte_flow_attr *attr,
14225 : : const struct rte_flow_item items[],
14226 : : const struct rte_flow_action actions[],
14227 : : bool external,
14228 : : struct rte_flow_error *error)
14229 : : {
14230 : : int ret;
14231 : : int split;
14232 : : int encap_idx;
14233 : 0 : uint32_t cpy_idx = 0;
14234 : 0 : int actions_n = 0;
14235 : 0 : struct rte_flow_hw *flow = NULL;
14236 : 0 : struct rte_flow_hw *prfx_flow = NULL;
14237 : 0 : const struct rte_flow_action *qrss = NULL;
14238 : 0 : const struct rte_flow_action *mark = NULL;
14239 : 0 : uint64_t item_flags = 0;
14240 : 0 : uint64_t action_flags = mlx5_flow_hw_action_flags_get(actions, &qrss, &mark,
14241 : : &encap_idx, &actions_n, error);
14242 : 0 : struct mlx5_flow_hw_split_resource resource = {
14243 : : .suffix = {
14244 : : .attr = attr,
14245 : : .items = items,
14246 : : .actions = actions,
14247 : : },
14248 : : };
14249 : 0 : struct rte_flow_error shadow_error = {0, };
14250 : 0 : const struct rte_flow_pattern_template_attr pattern_template_attr = {
14251 : : .relaxed_matching = 0,
14252 : 0 : .ingress = attr->ingress,
14253 : 0 : .egress = attr->egress,
14254 : 0 : .transfer = attr->transfer,
14255 : : };
14256 : :
14257 : : /* Validate application items only */
14258 : 0 : ret = __flow_hw_pattern_validate(dev, &pattern_template_attr, items,
14259 : : &item_flags, true, error);
14260 [ # # ]: 0 : if (ret < 0)
14261 : : return 0;
14262 : :
14263 : : RTE_SET_USED(encap_idx);
14264 [ # # ]: 0 : if (!error)
14265 : : error = &shadow_error;
14266 : 0 : split = mlx5_flow_nta_split_metadata(dev, attr, actions, qrss, action_flags,
14267 : : actions_n, external, &resource, error);
14268 [ # # ]: 0 : if (split < 0)
14269 : 0 : return split;
14270 : :
14271 : : /* Update the metadata copy table - MLX5_FLOW_MREG_CP_TABLE_GROUP */
14272 [ # # # # : 0 : if (((attr->ingress && attr->group != MLX5_FLOW_MREG_CP_TABLE_GROUP) ||
# # ]
14273 [ # # ]: 0 : attr->transfer) && external) {
14274 : 0 : ret = mlx5_flow_nta_update_copy_table(dev, &cpy_idx, mark,
14275 : : action_flags, error);
14276 [ # # ]: 0 : if (ret)
14277 : 0 : goto free;
14278 : : }
14279 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
14280 : 0 : flow = mlx5_nta_sample_flow_list_create(dev, type, attr, items, actions,
14281 : : item_flags, action_flags, error);
14282 [ # # ]: 0 : if (flow != NULL)
14283 : 0 : return (uintptr_t)flow;
14284 : 0 : goto free;
14285 : : }
14286 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_RSS) {
14287 : : const struct rte_flow_action_rss
14288 : 0 : *rss_conf = flow_nta_locate_rss(dev, actions, error);
14289 : 0 : flow = flow_nta_handle_rss(dev, attr, items, actions, rss_conf,
14290 : : item_flags, action_flags, external,
14291 : : type, error);
14292 [ # # ]: 0 : if (flow) {
14293 : 0 : flow->nt2hws->rix_mreg_copy = cpy_idx;
14294 : 0 : cpy_idx = 0;
14295 [ # # ]: 0 : if (!split)
14296 : 0 : return (uintptr_t)flow;
14297 : 0 : goto prefix_flow;
14298 : : }
14299 : 0 : goto free;
14300 : : }
14301 : : /* Create single flow. */
14302 : 0 : ret = flow_hw_create_flow(dev, type, resource.suffix.attr, resource.suffix.items,
14303 : : resource.suffix.actions, item_flags, action_flags,
14304 : : external, &flow, error);
14305 [ # # ]: 0 : if (ret)
14306 : 0 : goto free;
14307 [ # # ]: 0 : if (flow) {
14308 : 0 : flow->nt2hws->rix_mreg_copy = cpy_idx;
14309 : 0 : cpy_idx = 0;
14310 [ # # ]: 0 : if (!split)
14311 : 0 : return (uintptr_t)flow;
14312 : : /* Fall Through to prefix flow creation. */
14313 : : }
14314 : 0 : prefix_flow:
14315 : 0 : ret = flow_hw_create_flow(dev, type, attr, items, resource.prefix.actions,
14316 : : item_flags, action_flags, external, &prfx_flow, error);
14317 [ # # ]: 0 : if (ret)
14318 : 0 : goto free;
14319 [ # # ]: 0 : if (prfx_flow) {
14320 : 0 : prfx_flow->nt2hws->rix_mreg_copy = flow->nt2hws->rix_mreg_copy;
14321 : 0 : flow->nt2hws->chaned_flow = 1;
14322 : 0 : SLIST_INSERT_AFTER(prfx_flow, flow, nt2hws->next);
14323 : 0 : mlx5_flow_nta_split_resource_free(dev, &resource);
14324 : 0 : return (uintptr_t)prfx_flow;
14325 : : }
14326 : 0 : free:
14327 [ # # ]: 0 : if (prfx_flow)
14328 : 0 : flow_hw_list_destroy(dev, type, (uintptr_t)prfx_flow);
14329 [ # # ]: 0 : if (flow)
14330 : 0 : flow_hw_list_destroy(dev, type, (uintptr_t)flow);
14331 [ # # ]: 0 : if (cpy_idx)
14332 : 0 : mlx5_flow_nta_del_copy_action(dev, cpy_idx);
14333 [ # # ]: 0 : if (split > 0)
14334 : 0 : mlx5_flow_nta_split_resource_free(dev, &resource);
14335 : : return 0;
14336 : : }
14337 : :
14338 : : static void
14339 : 0 : mlx5_mirror_destroy_clone(struct rte_eth_dev *dev,
14340 : : struct mlx5_mirror_clone *clone)
14341 : : {
14342 [ # # # ]: 0 : switch (clone->type) {
14343 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
14344 : : case RTE_FLOW_ACTION_TYPE_QUEUE:
14345 : 0 : mlx5_hrxq_release(dev,
14346 : 0 : ((struct mlx5_hrxq *)(clone->action_ctx))->idx);
14347 : 0 : break;
14348 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP:
14349 : 0 : flow_hw_jump_release(dev, clone->action_ctx);
14350 : : break;
14351 : : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
14352 : : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
14353 : : case RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:
14354 : : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
14355 : : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
14356 : : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
14357 : : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
14358 : : default:
14359 : : break;
14360 : : }
14361 : 0 : }
14362 : :
14363 : : void
14364 [ # # ]: 0 : mlx5_hw_mirror_destroy(struct rte_eth_dev *dev, struct mlx5_mirror *mirror)
14365 : : {
14366 : : uint32_t i;
14367 : :
14368 : : mlx5_indirect_list_remove_entry(&mirror->indirect);
14369 [ # # ]: 0 : for (i = 0; i < mirror->clones_num; i++)
14370 : 0 : mlx5_mirror_destroy_clone(dev, &mirror->clone[i]);
14371 [ # # ]: 0 : if (mirror->mirror_action)
14372 : 0 : mlx5dr_action_destroy(mirror->mirror_action);
14373 : 0 : mlx5_free(mirror);
14374 : 0 : }
14375 : :
14376 : : static __rte_always_inline bool
14377 : : mlx5_mirror_terminal_action(const struct rte_flow_action *action)
14378 : : {
14379 : 0 : switch (action->type) {
14380 : : case RTE_FLOW_ACTION_TYPE_JUMP:
14381 : : case RTE_FLOW_ACTION_TYPE_RSS:
14382 : : case RTE_FLOW_ACTION_TYPE_QUEUE:
14383 : : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
14384 : : case RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:
14385 : : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
14386 : : case RTE_FLOW_ACTION_TYPE_DROP:
14387 : : return true;
14388 : : default:
14389 : : break;
14390 : : }
14391 : : return false;
14392 : : }
14393 : :
14394 : : static bool
14395 : 0 : mlx5_mirror_validate_sample_action(struct rte_eth_dev *dev,
14396 : : const struct rte_flow_attr *flow_attr,
14397 : : const struct rte_flow_action *action)
14398 : : {
14399 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14400 : : const struct rte_flow_action_ethdev *port = NULL;
14401 [ # # # # ]: 0 : bool is_proxy = MLX5_HW_PORT_IS_PROXY(priv);
14402 : :
14403 [ # # ]: 0 : if (!action)
14404 : : return false;
14405 [ # # # # : 0 : switch (action->type) {
# ]
14406 : 0 : case RTE_FLOW_ACTION_TYPE_QUEUE:
14407 : : case RTE_FLOW_ACTION_TYPE_RSS:
14408 [ # # ]: 0 : if (flow_attr->transfer)
14409 : : return false;
14410 : : break;
14411 : 0 : case RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:
14412 [ # # # # ]: 0 : if (!is_proxy || !flow_attr->transfer)
14413 : : return false;
14414 : 0 : port = action->conf;
14415 [ # # # # ]: 0 : if (!port || port->port_id != MLX5_REPRESENTED_PORT_ESW_MGR)
14416 : : return false;
14417 : : break;
14418 : 0 : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
14419 : : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
14420 : : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
14421 : : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
14422 : : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
14423 [ # # # # ]: 0 : if (!is_proxy || !flow_attr->transfer)
14424 : : return false;
14425 [ # # ]: 0 : if (action[0].type == RTE_FLOW_ACTION_TYPE_RAW_DECAP &&
14426 [ # # ]: 0 : action[1].type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP)
14427 : : return false;
14428 : : break;
14429 : : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
14430 : : case RTE_FLOW_ACTION_TYPE_JUMP:
14431 : : case RTE_FLOW_ACTION_TYPE_DROP:
14432 : : break;
14433 : : default:
14434 : : return false;
14435 : : }
14436 : 0 : return true;
14437 : : }
14438 : :
14439 : : /**
14440 : : * Valid mirror actions list includes one or two SAMPLE actions
14441 : : * followed by JUMP.
14442 : : *
14443 : : * @return
14444 : : * Number of mirrors *action* list was valid.
14445 : : * -EINVAL otherwise.
14446 : : */
14447 : : static int
14448 : 0 : mlx5_hw_mirror_actions_list_validate(struct rte_eth_dev *dev,
14449 : : const struct rte_flow_attr *flow_attr,
14450 : : const struct rte_flow_action *actions)
14451 : : {
14452 [ # # ]: 0 : if (actions[0].type == RTE_FLOW_ACTION_TYPE_SAMPLE) {
14453 : : int i = 1;
14454 : : bool valid;
14455 : 0 : const struct rte_flow_action_sample *sample = actions[0].conf;
14456 : 0 : valid = mlx5_mirror_validate_sample_action(dev, flow_attr,
14457 : 0 : sample->actions);
14458 [ # # ]: 0 : if (!valid)
14459 : : return -EINVAL;
14460 [ # # ]: 0 : if (actions[1].type == RTE_FLOW_ACTION_TYPE_SAMPLE) {
14461 : : i = 2;
14462 : 0 : sample = actions[1].conf;
14463 : 0 : valid = mlx5_mirror_validate_sample_action(dev, flow_attr,
14464 : 0 : sample->actions);
14465 [ # # ]: 0 : if (!valid)
14466 : : return -EINVAL;
14467 : : }
14468 [ # # ]: 0 : return mlx5_mirror_terminal_action(actions + i) ? i + 1 : -EINVAL;
14469 : : }
14470 : : return -EINVAL;
14471 : : }
14472 : :
14473 : : static int
14474 : 0 : mirror_format_tir(struct rte_eth_dev *dev,
14475 : : struct mlx5_mirror_clone *clone,
14476 : : const struct mlx5_flow_template_table_cfg *table_cfg,
14477 : : const struct rte_flow_action *action,
14478 : : struct mlx5dr_action_dest_attr *dest_attr,
14479 : : struct rte_flow_error *error)
14480 : : {
14481 : : uint32_t hws_flags;
14482 : : enum mlx5dr_table_type table_type;
14483 : : struct mlx5_hrxq *tir_ctx;
14484 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14485 : : bool unified_fdb = is_unified_fdb(priv);
14486 : :
14487 : 0 : table_type = get_mlx5dr_table_type(&table_cfg->attr.flow_attr, table_cfg->attr.specialize,
14488 : : unified_fdb);
14489 : 0 : hws_flags = mlx5_hw_act_flag[MLX5_HW_ACTION_FLAG_NONE_ROOT][table_type];
14490 : 0 : tir_ctx = flow_hw_tir_action_register(dev, hws_flags, action);
14491 [ # # ]: 0 : if (!tir_ctx)
14492 : 0 : return rte_flow_error_set(error, EINVAL,
14493 : : RTE_FLOW_ERROR_TYPE_ACTION,
14494 : : action, "failed to create QUEUE action for mirror clone");
14495 : 0 : dest_attr->dest = tir_ctx->action;
14496 : 0 : clone->action_ctx = tir_ctx;
14497 : 0 : return 0;
14498 : : }
14499 : :
14500 : : static int
14501 : 0 : mirror_format_jump(struct rte_eth_dev *dev,
14502 : : struct mlx5_mirror_clone *clone,
14503 : : const struct mlx5_flow_template_table_cfg *table_cfg,
14504 : : const struct rte_flow_action *action,
14505 : : struct mlx5dr_action_dest_attr *dest_attr,
14506 : : struct rte_flow_error *error)
14507 : : {
14508 : 0 : const struct rte_flow_action_jump *jump_conf = action->conf;
14509 : 0 : struct mlx5_hw_jump_action *jump = flow_hw_jump_action_register
14510 : : (dev, table_cfg,
14511 : 0 : jump_conf->group, error);
14512 : :
14513 [ # # ]: 0 : if (!jump)
14514 : 0 : return rte_flow_error_set(error, EINVAL,
14515 : : RTE_FLOW_ERROR_TYPE_ACTION,
14516 : : action, "failed to create JUMP action for mirror clone");
14517 : 0 : dest_attr->dest = jump->hws_action;
14518 : 0 : clone->action_ctx = jump;
14519 : 0 : return 0;
14520 : : }
14521 : :
14522 : : static int
14523 : : mirror_format_port(struct rte_eth_dev *dev,
14524 : : const struct rte_flow_action *action,
14525 : : struct mlx5dr_action_dest_attr *dest_attr,
14526 : : struct rte_flow_error __rte_unused *error)
14527 : : {
14528 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14529 : 0 : const struct rte_flow_action_ethdev *port_action = action->conf;
14530 : :
14531 : 0 : dest_attr->dest = priv->hw_vport[port_action->port_id];
14532 : : return 0;
14533 : : }
14534 : :
14535 : : static int
14536 : 0 : hw_mirror_clone_reformat(const struct rte_flow_action *actions,
14537 : : struct mlx5dr_action_dest_attr *dest_attr,
14538 : : enum mlx5dr_action_type *action_type,
14539 : : uint8_t *reformat_buf, bool decap)
14540 : : {
14541 : : int ret;
14542 : : const struct rte_flow_item *encap_item = NULL;
14543 : : const struct rte_flow_action_raw_encap *encap_conf = NULL;
14544 : : typeof(dest_attr->reformat) *reformat = &dest_attr->reformat;
14545 : :
14546 [ # # # # ]: 0 : switch (actions[0].type) {
14547 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
14548 : 0 : encap_conf = actions[0].conf;
14549 : 0 : break;
14550 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
14551 : 0 : encap_item = MLX5_CONST_ENCAP_ITEM(rte_flow_action_vxlan_encap,
14552 : : actions);
14553 : 0 : break;
14554 : 0 : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
14555 : 0 : encap_item = MLX5_CONST_ENCAP_ITEM(rte_flow_action_nvgre_encap,
14556 : : actions);
14557 : 0 : break;
14558 : : default:
14559 : : return -EINVAL;
14560 : : }
14561 : 0 : *action_type = decap ?
14562 [ # # ]: 0 : MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3 :
14563 : : MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;
14564 [ # # ]: 0 : if (encap_item) {
14565 : 0 : ret = flow_dv_convert_encap_data(encap_item, reformat_buf,
14566 : : &reformat->reformat_data_sz, NULL);
14567 [ # # ]: 0 : if (ret)
14568 : : return -EINVAL;
14569 : 0 : reformat->reformat_data = reformat_buf;
14570 : : } else {
14571 : 0 : reformat->reformat_data = (void *)(uintptr_t)encap_conf->data;
14572 : 0 : reformat->reformat_data_sz = encap_conf->size;
14573 : : }
14574 : : return 0;
14575 : : }
14576 : :
14577 : : static int
14578 : 0 : hw_mirror_format_clone(struct rte_eth_dev *dev,
14579 : : struct mlx5_mirror_clone *clone,
14580 : : const struct mlx5_flow_template_table_cfg *table_cfg,
14581 : : const struct rte_flow_action *actions,
14582 : : struct mlx5dr_action_dest_attr *dest_attr,
14583 : : uint8_t *reformat_buf, struct rte_flow_error *error)
14584 : : {
14585 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14586 : : int ret;
14587 : : uint32_t i;
14588 : : bool decap_seen = false;
14589 : :
14590 [ # # ]: 0 : for (i = 0; actions[i].type != RTE_FLOW_ACTION_TYPE_END; i++) {
14591 : 0 : dest_attr->action_type[i] = mlx5_hw_dr_action_types[actions[i].type];
14592 [ # # # # : 0 : switch (actions[i].type) {
# # # # ]
14593 : 0 : case RTE_FLOW_ACTION_TYPE_QUEUE:
14594 : : case RTE_FLOW_ACTION_TYPE_RSS:
14595 : 0 : ret = mirror_format_tir(dev, clone, table_cfg,
14596 : : &actions[i], dest_attr, error);
14597 [ # # ]: 0 : if (ret)
14598 : 0 : return ret;
14599 : : break;
14600 : 0 : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
14601 : : ret = mirror_format_port(dev, &actions[i],
14602 : : dest_attr, error);
14603 : : if (ret)
14604 : : return ret;
14605 : : break;
14606 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP:
14607 : 0 : ret = mirror_format_jump(dev, clone, table_cfg,
14608 : : &actions[i], dest_attr, error);
14609 [ # # ]: 0 : if (ret)
14610 : 0 : return ret;
14611 : : break;
14612 : 0 : case RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:
14613 : 0 : dest_attr->dest = priv->hw_def_miss;
14614 : 0 : break;
14615 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
14616 : : decap_seen = true;
14617 : 0 : break;
14618 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
14619 : : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
14620 : : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
14621 : 0 : ret = hw_mirror_clone_reformat(&actions[i], dest_attr,
14622 : : &dest_attr->action_type[i],
14623 : : reformat_buf, decap_seen);
14624 [ # # ]: 0 : if (ret < 0)
14625 : 0 : return rte_flow_error_set(error, EINVAL,
14626 : : RTE_FLOW_ERROR_TYPE_ACTION,
14627 : : &actions[i],
14628 : : "failed to create reformat action");
14629 : : break;
14630 : : case RTE_FLOW_ACTION_TYPE_DROP:
14631 : : break;
14632 : 0 : default:
14633 : 0 : return rte_flow_error_set(error, EINVAL,
14634 : : RTE_FLOW_ERROR_TYPE_ACTION,
14635 : : &actions[i], "unsupported sample action");
14636 : : }
14637 : 0 : clone->type = actions->type;
14638 : : }
14639 : 0 : dest_attr->action_type[i] = MLX5DR_ACTION_TYP_LAST;
14640 : 0 : return 0;
14641 : : }
14642 : :
14643 : : struct mlx5_mirror *
14644 : 0 : mlx5_hw_create_mirror(struct rte_eth_dev *dev,
14645 : : const struct mlx5_flow_template_table_cfg *table_cfg,
14646 : : const struct rte_flow_action *actions,
14647 : : struct rte_flow_error *error)
14648 : : {
14649 : : uint32_t hws_flags;
14650 : : int ret = 0, i, clones_num;
14651 : : struct mlx5_mirror *mirror;
14652 : : enum mlx5dr_table_type table_type;
14653 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
14654 : : bool unified_fdb = is_unified_fdb(priv);
14655 [ # # ]: 0 : const struct rte_flow_attr *flow_attr = &table_cfg->attr.flow_attr;
14656 : : uint8_t reformat_buf[MLX5_MIRROR_MAX_CLONES_NUM][MLX5_ENCAP_MAX_LEN];
14657 : : struct mlx5dr_action_dest_attr mirror_attr[MLX5_MIRROR_MAX_CLONES_NUM + 1];
14658 : : enum mlx5dr_action_type array_action_types[MLX5_MIRROR_MAX_CLONES_NUM + 1]
14659 : : [MLX5_MIRROR_MAX_SAMPLE_ACTIONS_LEN + 1];
14660 : :
14661 : : memset(mirror_attr, 0, sizeof(mirror_attr));
14662 : : memset(array_action_types, 0, sizeof(array_action_types));
14663 : 0 : table_type = get_mlx5dr_table_type(flow_attr, table_cfg->attr.specialize, unified_fdb);
14664 : 0 : hws_flags = mlx5_hw_act_flag[MLX5_HW_ACTION_FLAG_NONE_ROOT][table_type];
14665 : 0 : clones_num = mlx5_hw_mirror_actions_list_validate(dev, flow_attr,
14666 : : actions);
14667 [ # # ]: 0 : if (clones_num < 0) {
14668 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14669 : : actions, "Invalid mirror list format");
14670 : 0 : return NULL;
14671 : : }
14672 : 0 : mirror = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mirror),
14673 : : 0, SOCKET_ID_ANY);
14674 [ # # ]: 0 : if (!mirror) {
14675 : 0 : rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_ACTION,
14676 : : actions, "Failed to allocate mirror context");
14677 : 0 : return NULL;
14678 : : }
14679 : :
14680 : 0 : mirror->indirect.type = MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR;
14681 : 0 : mirror->clones_num = clones_num;
14682 [ # # ]: 0 : for (i = 0; i < clones_num; i++) {
14683 : : const struct rte_flow_action *clone_actions;
14684 : :
14685 : 0 : mirror_attr[i].action_type = array_action_types[i];
14686 [ # # ]: 0 : if (actions[i].type == RTE_FLOW_ACTION_TYPE_SAMPLE) {
14687 : 0 : const struct rte_flow_action_sample *sample = actions[i].conf;
14688 : :
14689 : 0 : clone_actions = sample->actions;
14690 : : } else {
14691 : : clone_actions = &actions[i];
14692 : : }
14693 : 0 : ret = hw_mirror_format_clone(dev, &mirror->clone[i], table_cfg,
14694 : : clone_actions, &mirror_attr[i],
14695 : 0 : reformat_buf[i], error);
14696 : :
14697 [ # # ]: 0 : if (ret)
14698 : 0 : goto error;
14699 : : }
14700 : 0 : hws_flags |= MLX5DR_ACTION_FLAG_SHARED;
14701 : 0 : mirror->mirror_action = mlx5dr_action_create_dest_array(priv->dr_ctx,
14702 : : clones_num,
14703 : : mirror_attr,
14704 : : hws_flags);
14705 [ # # ]: 0 : if (!mirror->mirror_action) {
14706 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14707 : : actions, "Failed to create HWS mirror action");
14708 : 0 : goto error;
14709 : : }
14710 : : return mirror;
14711 : 0 : error:
14712 : 0 : mlx5_hw_mirror_destroy(dev, mirror);
14713 : 0 : return NULL;
14714 : : }
14715 : :
14716 : : static struct rte_flow_action_list_handle *
14717 : 0 : mlx5_hw_mirror_handle_create(struct rte_eth_dev *dev,
14718 : : const struct mlx5_flow_template_table_cfg *table_cfg,
14719 : : const struct rte_flow_action *actions,
14720 : : struct rte_flow_error *error)
14721 : : {
14722 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14723 : 0 : struct mlx5_mirror *mirror = mlx5_hw_create_mirror(dev, table_cfg, actions, error);
14724 : :
14725 [ # # ]: 0 : if (mirror)
14726 [ # # ]: 0 : mlx5_indirect_list_add_entry(&priv->indirect_list_head, &mirror->indirect);
14727 : 0 : return (struct rte_flow_action_list_handle *)mirror;
14728 : : }
14729 : :
14730 : : void
14731 : 0 : mlx5_destroy_legacy_indirect(__rte_unused struct rte_eth_dev *dev,
14732 : : struct mlx5_indirect_list *ptr)
14733 : : {
14734 : : struct mlx5_indlst_legacy *obj = (typeof(obj))ptr;
14735 : :
14736 : : switch (obj->legacy_type) {
14737 : : case RTE_FLOW_ACTION_TYPE_METER_MARK:
14738 : : break; /* ASO meters were released in mlx5_flow_meter_flush() */
14739 : : default:
14740 : : break;
14741 : : }
14742 : 0 : mlx5_free(obj);
14743 : 0 : }
14744 : :
14745 : : static struct rte_flow_action_list_handle *
14746 : 0 : mlx5_create_legacy_indlst(struct rte_eth_dev *dev, uint32_t queue,
14747 : : const struct rte_flow_op_attr *attr,
14748 : : const struct rte_flow_indir_action_conf *conf,
14749 : : const struct rte_flow_action *actions,
14750 : : void *user_data, struct rte_flow_error *error)
14751 : : {
14752 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14753 : 0 : struct mlx5_indlst_legacy *indlst_obj = mlx5_malloc(MLX5_MEM_ZERO,
14754 : : sizeof(*indlst_obj),
14755 : : 0, SOCKET_ID_ANY);
14756 : :
14757 [ # # ]: 0 : if (!indlst_obj)
14758 : : return NULL;
14759 : 0 : indlst_obj->handle = flow_hw_action_handle_create(dev, queue, attr, conf,
14760 : : actions, user_data,
14761 : : error);
14762 [ # # ]: 0 : if (!indlst_obj->handle) {
14763 : 0 : mlx5_free(indlst_obj);
14764 : 0 : return NULL;
14765 : : }
14766 : 0 : indlst_obj->legacy_type = actions[0].type;
14767 : 0 : indlst_obj->indirect.type = MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY;
14768 [ # # ]: 0 : mlx5_indirect_list_add_entry(&priv->indirect_list_head, &indlst_obj->indirect);
14769 : 0 : return (struct rte_flow_action_list_handle *)indlst_obj;
14770 : : }
14771 : :
14772 : : static __rte_always_inline enum mlx5_indirect_list_type
14773 : : flow_hw_inlist_type_get(const struct rte_flow_action *actions)
14774 : : {
14775 [ # # # # ]: 0 : switch (actions[0].type) {
14776 : : case RTE_FLOW_ACTION_TYPE_SAMPLE:
14777 : : return MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR;
14778 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
14779 : 0 : return actions[1].type == RTE_FLOW_ACTION_TYPE_END ?
14780 : 0 : MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY :
14781 : : MLX5_INDIRECT_ACTION_LIST_TYPE_ERR;
14782 : : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
14783 : : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
14784 : : return MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT;
14785 : : default:
14786 : : break;
14787 : : }
14788 : : return MLX5_INDIRECT_ACTION_LIST_TYPE_ERR;
14789 : : }
14790 : :
14791 : : static struct rte_flow_action_list_handle*
14792 : 0 : mlx5_hw_decap_encap_handle_create(struct rte_eth_dev *dev,
14793 : : const struct mlx5_flow_template_table_cfg *table_cfg,
14794 : : const struct rte_flow_action *actions,
14795 : : struct rte_flow_error *error)
14796 : : {
14797 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14798 : : const struct rte_flow_attr *flow_attr = &table_cfg->attr.flow_attr;
14799 : : const struct rte_flow_action *encap = NULL;
14800 : : const struct rte_flow_action *decap = NULL;
14801 : 0 : struct rte_flow_indir_action_conf indirect_conf = {
14802 : 0 : .ingress = flow_attr->ingress,
14803 : 0 : .egress = flow_attr->egress,
14804 : 0 : .transfer = flow_attr->transfer,
14805 : : };
14806 : : struct mlx5_hw_encap_decap_action *handle;
14807 : : uint64_t action_flags = 0;
14808 : :
14809 : : /*
14810 : : * Allow
14811 : : * 1. raw_decap / raw_encap / end
14812 : : * 2. raw_encap / end
14813 : : * 3. raw_decap / end
14814 : : */
14815 [ # # ]: 0 : while (actions->type != RTE_FLOW_ACTION_TYPE_END) {
14816 [ # # ]: 0 : if (actions->type == RTE_FLOW_ACTION_TYPE_RAW_DECAP) {
14817 [ # # ]: 0 : if (action_flags) {
14818 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14819 : : actions, "Invalid indirect action list sequence");
14820 : 0 : return NULL;
14821 : : }
14822 : : action_flags |= MLX5_FLOW_ACTION_DECAP;
14823 : : decap = actions;
14824 [ # # ]: 0 : } else if (actions->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
14825 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_ENCAP) {
14826 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14827 : : actions, "Invalid indirect action list sequence");
14828 : 0 : return NULL;
14829 : : }
14830 : 0 : action_flags |= MLX5_FLOW_ACTION_ENCAP;
14831 : : encap = actions;
14832 : : } else {
14833 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14834 : : actions, "Invalid indirect action type in list");
14835 : 0 : return NULL;
14836 : : }
14837 : 0 : actions++;
14838 : : }
14839 [ # # ]: 0 : if (!decap && !encap) {
14840 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14841 : : actions, "Invalid indirect action combinations");
14842 : 0 : return NULL;
14843 : : }
14844 : 0 : handle = mlx5_reformat_action_create(dev, &indirect_conf, encap, decap, error);
14845 [ # # ]: 0 : if (!handle) {
14846 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14847 : : actions, "Failed to create HWS decap_encap action");
14848 : 0 : return NULL;
14849 : : }
14850 : 0 : handle->indirect.type = MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT;
14851 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->indirect_list_head, &handle->indirect, entry);
14852 : 0 : return (struct rte_flow_action_list_handle *)handle;
14853 : : }
14854 : :
14855 : : static struct rte_flow_action_list_handle *
14856 [ # # ]: 0 : flow_hw_async_action_list_handle_create(struct rte_eth_dev *dev, uint32_t queue,
14857 : : const struct rte_flow_op_attr *attr,
14858 : : const struct rte_flow_indir_action_conf *conf,
14859 : : const struct rte_flow_action *actions,
14860 : : void *user_data,
14861 : : struct rte_flow_error *error)
14862 : : {
14863 : : struct mlx5_hw_q_job *job = NULL;
14864 : : bool push = flow_hw_action_push(attr);
14865 : : enum mlx5_indirect_list_type list_type;
14866 : : struct rte_flow_action_list_handle *handle;
14867 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14868 : 0 : struct mlx5_flow_template_table_cfg table_cfg = {
14869 : : .external = true,
14870 : : .attr = {
14871 : : .flow_attr = {
14872 : 0 : .ingress = conf->ingress,
14873 : 0 : .egress = conf->egress,
14874 : 0 : .transfer = conf->transfer
14875 : : }
14876 : : }
14877 : : };
14878 : :
14879 [ # # ]: 0 : if (!mlx5_hw_ctx_validate(dev, error))
14880 : : return NULL;
14881 [ # # ]: 0 : if (!actions) {
14882 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14883 : : NULL, "No action list");
14884 : 0 : return NULL;
14885 : : }
14886 : : list_type = flow_hw_inlist_type_get(actions);
14887 [ # # ]: 0 : if (list_type == MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY) {
14888 : : /*
14889 : : * Legacy indirect actions already have
14890 : : * async resources management. No need to do it twice.
14891 : : */
14892 : 0 : handle = mlx5_create_legacy_indlst(dev, queue, attr, conf,
14893 : : actions, user_data, error);
14894 : 0 : goto end;
14895 : : }
14896 [ # # ]: 0 : if (attr) {
14897 : : job = flow_hw_action_job_init(priv, queue, NULL, user_data,
14898 : : NULL, MLX5_HW_Q_JOB_TYPE_CREATE,
14899 : : MLX5_HW_INDIRECT_TYPE_LIST, error);
14900 : : if (!job)
14901 : 0 : return NULL;
14902 : : }
14903 [ # # # ]: 0 : switch (list_type) {
14904 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR:
14905 : : /*
14906 : : * Mirror action is only supported in HWS group. Setting group to
14907 : : * non-zero will ensure that the action resources are allocated correctly.
14908 : : */
14909 : 0 : table_cfg.attr.flow_attr.group = 1;
14910 : 0 : handle = mlx5_hw_mirror_handle_create(dev, &table_cfg,
14911 : : actions, error);
14912 : 0 : break;
14913 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT:
14914 : 0 : handle = mlx5_hw_decap_encap_handle_create(dev, &table_cfg,
14915 : : actions, error);
14916 : 0 : break;
14917 : 0 : default:
14918 : : handle = NULL;
14919 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14920 : : actions, "Invalid list");
14921 : : }
14922 [ # # ]: 0 : if (job) {
14923 : 0 : job->action = handle;
14924 [ # # ]: 0 : flow_hw_action_finalize(dev, queue, job, push, false,
14925 : : handle != NULL);
14926 : : }
14927 : 0 : end:
14928 : : return handle;
14929 : : }
14930 : :
14931 : : static struct rte_flow_action_list_handle *
14932 : 0 : flow_hw_action_list_handle_create(struct rte_eth_dev *dev,
14933 : : const struct rte_flow_indir_action_conf *conf,
14934 : : const struct rte_flow_action *actions,
14935 : : struct rte_flow_error *error)
14936 : : {
14937 : 0 : return flow_hw_async_action_list_handle_create(dev, MLX5_HW_INV_QUEUE,
14938 : : NULL, conf, actions,
14939 : : NULL, error);
14940 : : }
14941 : :
14942 : : static int
14943 [ # # ]: 0 : flow_hw_async_action_list_handle_destroy
14944 : : (struct rte_eth_dev *dev, uint32_t queue,
14945 : : const struct rte_flow_op_attr *attr,
14946 : : struct rte_flow_action_list_handle *handle,
14947 : : void *user_data, struct rte_flow_error *error)
14948 : : {
14949 : : int ret = 0;
14950 : : struct mlx5_hw_q_job *job = NULL;
14951 : : bool push = flow_hw_action_push(attr);
14952 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
14953 : : enum mlx5_indirect_list_type type =
14954 : : mlx5_get_indirect_list_type((void *)handle);
14955 : :
14956 [ # # ]: 0 : if (type == MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY) {
14957 : : struct mlx5_indlst_legacy *legacy = (typeof(legacy))handle;
14958 : :
14959 : 0 : ret = flow_hw_action_handle_destroy(dev, queue, attr,
14960 : : legacy->handle,
14961 : : user_data, error);
14962 : : mlx5_indirect_list_remove_entry(&legacy->indirect);
14963 : 0 : goto end;
14964 : : }
14965 [ # # ]: 0 : if (attr) {
14966 : : job = flow_hw_action_job_init(priv, queue, NULL, user_data,
14967 : : NULL, MLX5_HW_Q_JOB_TYPE_DESTROY,
14968 : : MLX5_HW_INDIRECT_TYPE_LIST, error);
14969 : : if (!job)
14970 : 0 : return rte_errno;
14971 : : }
14972 [ # # # ]: 0 : switch (type) {
14973 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR:
14974 : 0 : mlx5_hw_mirror_destroy(dev, (struct mlx5_mirror *)handle);
14975 : 0 : break;
14976 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT:
14977 [ # # ]: 0 : LIST_REMOVE(&((struct mlx5_hw_encap_decap_action *)handle)->indirect,
14978 : : entry);
14979 : 0 : mlx5_reformat_action_destroy(dev, handle, error);
14980 : 0 : break;
14981 : 0 : default:
14982 : 0 : ret = rte_flow_error_set(error, EINVAL,
14983 : : RTE_FLOW_ERROR_TYPE_ACTION,
14984 : : NULL, "Invalid indirect list handle");
14985 : : }
14986 [ # # ]: 0 : if (job) {
14987 : : flow_hw_action_finalize(dev, queue, job, push, false, true);
14988 : : }
14989 : 0 : end:
14990 : : return ret;
14991 : : }
14992 : :
14993 : : static int
14994 : 0 : flow_hw_action_list_handle_destroy(struct rte_eth_dev *dev,
14995 : : struct rte_flow_action_list_handle *handle,
14996 : : struct rte_flow_error *error)
14997 : : {
14998 : 0 : return flow_hw_async_action_list_handle_destroy(dev, MLX5_HW_INV_QUEUE,
14999 : : NULL, handle, NULL,
15000 : : error);
15001 : : }
15002 : :
15003 : : static int
15004 [ # # ]: 0 : flow_hw_async_action_list_handle_query_update
15005 : : (struct rte_eth_dev *dev, uint32_t queue_id,
15006 : : const struct rte_flow_op_attr *attr,
15007 : : const struct rte_flow_action_list_handle *handle,
15008 : : const void **update, void **query,
15009 : : enum rte_flow_query_update_mode mode,
15010 : : void *user_data, struct rte_flow_error *error)
15011 : : {
15012 : : enum mlx5_indirect_list_type type =
15013 : : mlx5_get_indirect_list_type((const void *)handle);
15014 : :
15015 [ # # ]: 0 : if (type == MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY) {
15016 : : struct mlx5_indlst_legacy *legacy = (void *)(uintptr_t)handle;
15017 : :
15018 [ # # ]: 0 : if (update && query)
15019 : 0 : return flow_hw_async_action_handle_query_update
15020 : : (dev, queue_id, attr, legacy->handle,
15021 : : update, query, mode, user_data, error);
15022 [ # # # # ]: 0 : else if (update && update[0])
15023 : 0 : return flow_hw_action_handle_update(dev, queue_id, attr,
15024 : : legacy->handle, update[0],
15025 : : user_data, error);
15026 [ # # # # ]: 0 : else if (query && query[0])
15027 : 0 : return flow_hw_action_handle_query(dev, queue_id, attr,
15028 : 0 : legacy->handle, query[0],
15029 : : user_data, error);
15030 : : else
15031 : 0 : return rte_flow_error_set(error, EINVAL,
15032 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15033 : : NULL, "invalid legacy handle query_update parameters");
15034 : : }
15035 : : return -ENOTSUP;
15036 : : }
15037 : :
15038 : : static int
15039 : 0 : flow_hw_action_list_handle_query_update(struct rte_eth_dev *dev,
15040 : : const struct rte_flow_action_list_handle *handle,
15041 : : const void **update, void **query,
15042 : : enum rte_flow_query_update_mode mode,
15043 : : struct rte_flow_error *error)
15044 : : {
15045 : 0 : return flow_hw_async_action_list_handle_query_update
15046 : : (dev, MLX5_HW_INV_QUEUE, NULL, handle,
15047 : : update, query, mode, NULL, error);
15048 : : }
15049 : :
15050 : : static int
15051 : 0 : flow_hw_calc_table_hash(struct rte_eth_dev *dev,
15052 : : const struct rte_flow_template_table *table,
15053 : : const struct rte_flow_item pattern[],
15054 : : uint8_t pattern_template_index,
15055 : : uint32_t *hash, struct rte_flow_error *error)
15056 : : {
15057 : : const struct rte_flow_item *items;
15058 : : struct mlx5_flow_hw_pattern_params pp;
15059 : : int res;
15060 : :
15061 : 0 : items = flow_hw_get_rule_items(dev, table, pattern,
15062 : : pattern_template_index,
15063 : : &pp);
15064 : 0 : res = mlx5dr_rule_hash_calculate(mlx5_table_matcher(table), items,
15065 : : pattern_template_index,
15066 : : MLX5DR_RULE_HASH_CALC_MODE_RAW,
15067 : : hash);
15068 [ # # ]: 0 : if (res)
15069 : 0 : return rte_flow_error_set(error, res,
15070 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15071 : : NULL,
15072 : : "hash could not be calculated");
15073 : : return 0;
15074 : : }
15075 : :
15076 : : static int
15077 : 0 : flow_hw_calc_encap_hash(struct rte_eth_dev *dev,
15078 : : const struct rte_flow_item pattern[],
15079 : : enum rte_flow_encap_hash_field dest_field,
15080 : : uint8_t *hash,
15081 : : struct rte_flow_error *error)
15082 : : {
15083 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
15084 : : struct mlx5dr_crc_encap_entropy_hash_fields data;
15085 : 0 : enum mlx5dr_crc_encap_entropy_hash_size res_size =
15086 : : dest_field == RTE_FLOW_ENCAP_HASH_FIELD_SRC_PORT ?
15087 : 0 : MLX5DR_CRC_ENCAP_ENTROPY_HASH_SIZE_16 :
15088 : : MLX5DR_CRC_ENCAP_ENTROPY_HASH_SIZE_8;
15089 : : int res;
15090 : :
15091 : : memset(&data, 0, sizeof(struct mlx5dr_crc_encap_entropy_hash_fields));
15092 : :
15093 [ # # ]: 0 : for (; pattern->type != RTE_FLOW_ITEM_TYPE_END; pattern++) {
15094 [ # # # # : 0 : switch (pattern->type) {
# # # # ]
15095 : 0 : case RTE_FLOW_ITEM_TYPE_IPV4:
15096 : 0 : data.dst.ipv4_addr =
15097 : 0 : ((const struct rte_flow_item_ipv4 *)(pattern->spec))->hdr.dst_addr;
15098 : 0 : data.src.ipv4_addr =
15099 : 0 : ((const struct rte_flow_item_ipv4 *)(pattern->spec))->hdr.src_addr;
15100 : 0 : break;
15101 : 0 : case RTE_FLOW_ITEM_TYPE_IPV6:
15102 : : memcpy(data.dst.ipv6_addr,
15103 : 0 : &((const struct rte_flow_item_ipv6 *)(pattern->spec))->hdr.dst_addr,
15104 : : sizeof(data.dst.ipv6_addr));
15105 : : memcpy(data.src.ipv6_addr,
15106 : : &((const struct rte_flow_item_ipv6 *)(pattern->spec))->hdr.src_addr,
15107 : : sizeof(data.src.ipv6_addr));
15108 : : break;
15109 : 0 : case RTE_FLOW_ITEM_TYPE_UDP:
15110 : 0 : data.next_protocol = IPPROTO_UDP;
15111 : 0 : data.dst_port =
15112 : 0 : ((const struct rte_flow_item_udp *)(pattern->spec))->hdr.dst_port;
15113 : 0 : data.src_port =
15114 : 0 : ((const struct rte_flow_item_udp *)(pattern->spec))->hdr.src_port;
15115 : 0 : break;
15116 : 0 : case RTE_FLOW_ITEM_TYPE_TCP:
15117 : 0 : data.next_protocol = IPPROTO_TCP;
15118 : 0 : data.dst_port =
15119 : 0 : ((const struct rte_flow_item_tcp *)(pattern->spec))->hdr.dst_port;
15120 : 0 : data.src_port =
15121 : 0 : ((const struct rte_flow_item_tcp *)(pattern->spec))->hdr.src_port;
15122 : 0 : break;
15123 : 0 : case RTE_FLOW_ITEM_TYPE_ICMP:
15124 : 0 : data.next_protocol = IPPROTO_ICMP;
15125 : 0 : break;
15126 : 0 : case RTE_FLOW_ITEM_TYPE_ICMP6:
15127 : 0 : data.next_protocol = IPPROTO_ICMPV6;
15128 : 0 : break;
15129 : 0 : case RTE_FLOW_ITEM_TYPE_GRE:
15130 : 0 : data.next_protocol = IPPROTO_GRE;
15131 : 0 : break;
15132 : : default:
15133 : : break;
15134 : : }
15135 : : }
15136 : 0 : res = mlx5dr_crc_encap_entropy_hash_calc(priv->dr_ctx, &data, hash, res_size);
15137 [ # # ]: 0 : if (res)
15138 : 0 : return rte_flow_error_set(error, res,
15139 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15140 : : NULL, "error while calculating encap hash");
15141 : : return 0;
15142 : : }
15143 : :
15144 : : static int
15145 : 0 : flow_hw_table_resize_multi_pattern_actions(struct rte_eth_dev *dev,
15146 : : struct rte_flow_template_table *table,
15147 : : uint32_t nb_flows,
15148 : : struct rte_flow_error *error)
15149 : : {
15150 : 0 : struct mlx5_multi_pattern_segment *segment = table->mpctx.segments;
15151 : : uint32_t bulk_size;
15152 : : int i, ret;
15153 : :
15154 : : /**
15155 : : * Segment always allocates Modify Header Argument Objects number in
15156 : : * powers of 2.
15157 : : * On resize, PMD adds minimal required argument objects number.
15158 : : * For example, if table size was 10, it allocated 16 argument objects.
15159 : : * Resize to 15 will not add new objects.
15160 : : */
15161 : 0 : for (i = 1;
15162 [ # # # # ]: 0 : i < MLX5_MAX_TABLE_RESIZE_NUM && segment->capacity;
15163 : 0 : i++, segment++) {
15164 : : /* keep the devtools/checkpatches.sh happy */
15165 : : }
15166 [ # # ]: 0 : if (i == MLX5_MAX_TABLE_RESIZE_NUM)
15167 : 0 : return rte_flow_error_set(error, EINVAL,
15168 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15169 : : table, "too many resizes");
15170 [ # # ]: 0 : if (segment->head_index - 1 >= nb_flows)
15171 : : return 0;
15172 [ # # ]: 0 : bulk_size = rte_align32pow2(nb_flows - segment->head_index + 1);
15173 : 0 : ret = mlx5_tbl_multi_pattern_process(dev, table, segment,
15174 : : rte_log2_u32(bulk_size),
15175 : : error);
15176 [ # # ]: 0 : if (ret)
15177 : 0 : return rte_flow_error_set(error, EINVAL,
15178 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15179 : : table, "too many resizes");
15180 : : return i;
15181 : : }
15182 : :
15183 : : static int
15184 : 0 : flow_hw_table_resize(struct rte_eth_dev *dev,
15185 : : struct rte_flow_template_table *table,
15186 : : uint32_t nb_flows,
15187 : : struct rte_flow_error *error)
15188 : : {
15189 : : struct mlx5dr_action_template *at[MLX5_HW_TBL_MAX_ACTION_TEMPLATE];
15190 : : struct mlx5dr_match_template *mt[MLX5_HW_TBL_MAX_ITEM_TEMPLATE];
15191 : 0 : struct mlx5dr_matcher_attr matcher_attr = table->matcher_attr;
15192 : 0 : struct mlx5dr_action_jump_to_matcher_attr jump_attr = {
15193 : : .type = MLX5DR_ACTION_JUMP_TO_MATCHER_BY_INDEX,
15194 : : .matcher = NULL,
15195 : : };
15196 : : struct mlx5_multi_pattern_segment *segment = NULL;
15197 : : struct mlx5dr_matcher *matcher = NULL;
15198 : : struct mlx5dr_action *jump = NULL;
15199 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
15200 : 0 : uint32_t i, selector = table->matcher_selector;
15201 : 0 : uint32_t other_selector = (selector + 1) & 1;
15202 : : int ret;
15203 : :
15204 [ # # ]: 0 : if (!rte_flow_template_table_resizable(dev->data->port_id, &table->cfg.attr))
15205 : 0 : return rte_flow_error_set(error, EINVAL,
15206 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15207 : : table, "no resizable attribute");
15208 [ # # ]: 0 : if (table->matcher_info[other_selector].matcher)
15209 : 0 : return rte_flow_error_set(error, EINVAL,
15210 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15211 : : table, "last table resize was not completed");
15212 [ # # ]: 0 : if (nb_flows <= table->cfg.attr.nb_flows)
15213 : 0 : return rte_flow_error_set(error, EINVAL,
15214 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15215 : : table, "shrinking table is not supported");
15216 : 0 : ret = mlx5_ipool_resize(table->flow, nb_flows, error);
15217 [ # # ]: 0 : if (ret)
15218 : : return ret;
15219 : : /*
15220 : : * A resizable matcher doesn't support rule update. In this case, the ipool
15221 : : * for the resource is not created and there is no need to resize it.
15222 : : */
15223 : : MLX5_ASSERT(!table->resource);
15224 [ # # ]: 0 : if (mlx5_is_multi_pattern_active(&table->mpctx)) {
15225 : 0 : ret = flow_hw_table_resize_multi_pattern_actions(dev, table, nb_flows, error);
15226 [ # # ]: 0 : if (ret < 0)
15227 : : return ret;
15228 [ # # ]: 0 : if (ret > 0)
15229 : 0 : segment = table->mpctx.segments + ret;
15230 : : }
15231 [ # # ]: 0 : for (i = 0; i < table->nb_item_templates; i++)
15232 : 0 : mt[i] = table->its[i]->mt;
15233 [ # # ]: 0 : for (i = 0; i < table->nb_action_templates; i++)
15234 : 0 : at[i] = table->ats[i].action_template->tmpl;
15235 : : nb_flows = rte_align32pow2(nb_flows);
15236 : 0 : matcher_attr.rule.num_log = rte_log2_u32(nb_flows);
15237 : 0 : matcher = mlx5dr_matcher_create(table->grp->tbl, mt,
15238 : : table->nb_item_templates, at,
15239 : : table->nb_action_templates,
15240 : : &matcher_attr);
15241 [ # # ]: 0 : if (!matcher) {
15242 : 0 : ret = rte_flow_error_set(error, rte_errno,
15243 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15244 : : table, "failed to create new matcher");
15245 : 0 : goto error;
15246 : : }
15247 [ # # ]: 0 : if (matcher_attr.isolated) {
15248 : 0 : jump_attr.matcher = matcher;
15249 : 0 : jump = mlx5dr_action_create_jump_to_matcher(priv->dr_ctx, &jump_attr,
15250 : 0 : mlx5_hw_act_flag[!!table->cfg.attr.flow_attr.group][table->type]);
15251 [ # # ]: 0 : if (!jump) {
15252 : 0 : ret = rte_flow_error_set(error, rte_errno,
15253 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15254 : : table, "failed to create jump to matcher action");
15255 : 0 : goto error;
15256 : : }
15257 : : }
15258 : 0 : rte_rwlock_write_lock(&table->matcher_replace_rwlk);
15259 : 0 : ret = mlx5dr_matcher_resize_set_target
15260 : : (table->matcher_info[selector].matcher, matcher);
15261 [ # # ]: 0 : if (ret) {
15262 : : rte_rwlock_write_unlock(&table->matcher_replace_rwlk);
15263 : 0 : ret = rte_flow_error_set(error, rte_errno,
15264 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15265 : : table, "failed to initiate matcher swap");
15266 : 0 : goto error;
15267 : : }
15268 : 0 : table->cfg.attr.nb_flows = nb_flows;
15269 : 0 : table->matcher_info[other_selector].matcher = matcher;
15270 : 0 : table->matcher_info[other_selector].jump = jump;
15271 : 0 : table->matcher_selector = other_selector;
15272 : 0 : rte_atomic_store_explicit(&table->matcher_info[other_selector].refcnt,
15273 : : 0, rte_memory_order_relaxed);
15274 : : rte_rwlock_write_unlock(&table->matcher_replace_rwlk);
15275 : 0 : return 0;
15276 : 0 : error:
15277 [ # # ]: 0 : if (segment)
15278 : 0 : mlx5_destroy_multi_pattern_segment(segment);
15279 [ # # ]: 0 : if (jump)
15280 : 0 : mlx5dr_action_destroy(jump);
15281 [ # # ]: 0 : if (matcher) {
15282 : 0 : ret = mlx5dr_matcher_destroy(matcher);
15283 : 0 : return rte_flow_error_set(error, rte_errno,
15284 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15285 : : table, "failed to destroy new matcher");
15286 : : }
15287 : : return ret;
15288 : : }
15289 : :
15290 : : static int
15291 : 0 : flow_hw_table_resize_complete(__rte_unused struct rte_eth_dev *dev,
15292 : : struct rte_flow_template_table *table,
15293 : : struct rte_flow_error *error)
15294 : : {
15295 : : int ret;
15296 : 0 : uint32_t selector = table->matcher_selector;
15297 : 0 : uint32_t other_selector = (selector + 1) & 1;
15298 : : struct mlx5_matcher_info *matcher_info = &table->matcher_info[other_selector];
15299 : : uint32_t matcher_refcnt;
15300 : :
15301 [ # # ]: 0 : if (!rte_flow_template_table_resizable(dev->data->port_id, &table->cfg.attr))
15302 : 0 : return rte_flow_error_set(error, EINVAL,
15303 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15304 : : table, "no resizable attribute");
15305 : 0 : matcher_refcnt = rte_atomic_load_explicit(&matcher_info->refcnt,
15306 : : rte_memory_order_relaxed);
15307 [ # # # # ]: 0 : if (!matcher_info->matcher || matcher_refcnt)
15308 : 0 : return rte_flow_error_set(error, EBUSY,
15309 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15310 : : table, "cannot complete table resize");
15311 [ # # ]: 0 : if (matcher_info->jump)
15312 : 0 : mlx5dr_action_destroy(matcher_info->jump);
15313 : 0 : ret = mlx5dr_matcher_destroy(matcher_info->matcher);
15314 [ # # ]: 0 : if (ret)
15315 : 0 : return rte_flow_error_set(error, rte_errno,
15316 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15317 : : table, "failed to destroy retired matcher");
15318 : 0 : matcher_info->matcher = NULL;
15319 : 0 : return 0;
15320 : : }
15321 : :
15322 : : static int
15323 : 0 : flow_hw_update_resized(struct rte_eth_dev *dev, uint32_t queue,
15324 : : const struct rte_flow_op_attr *attr,
15325 : : struct rte_flow *flow, void *user_data,
15326 : : struct rte_flow_error *error)
15327 : : {
15328 : : int ret;
15329 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
15330 : : struct rte_flow_hw *hw_flow = (struct rte_flow_hw *)flow;
15331 : 0 : struct rte_flow_template_table *table = hw_flow->table;
15332 [ # # ]: 0 : struct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(dev->data->port_id, hw_flow);
15333 : 0 : uint32_t table_selector = table->matcher_selector;
15334 : 0 : uint32_t rule_selector = aux->matcher_selector;
15335 : : uint32_t other_selector;
15336 : : struct mlx5dr_matcher *other_matcher;
15337 : 0 : struct mlx5dr_rule_attr rule_attr = {
15338 : : .queue_id = queue,
15339 : 0 : .burst = attr->postpone,
15340 : : };
15341 : :
15342 : : MLX5_ASSERT(hw_flow->flags & MLX5_FLOW_HW_FLOW_FLAG_MATCHER_SELECTOR);
15343 : : /**
15344 : : * mlx5dr_matcher_resize_rule_move() accepts original table matcher -
15345 : : * the one that was used BEFORE table resize.
15346 : : * Since the function is called AFTER table resize,
15347 : : * `table->matcher_selector` always points to the new matcher and
15348 : : * `aux->matcher_selector` points to a matcher used to create the flow.
15349 : : */
15350 : : other_selector = rule_selector == table_selector ?
15351 [ # # ]: 0 : (rule_selector + 1) & 1 : rule_selector;
15352 : 0 : other_matcher = table->matcher_info[other_selector].matcher;
15353 [ # # ]: 0 : if (!other_matcher)
15354 : 0 : return rte_flow_error_set(error, EINVAL,
15355 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
15356 : : "no active table resize");
15357 : 0 : hw_flow->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_MOVE;
15358 : 0 : hw_flow->user_data = user_data;
15359 : 0 : rule_attr.user_data = hw_flow;
15360 [ # # ]: 0 : if (rule_selector == table_selector) {
15361 : 0 : struct rte_ring *ring = !attr->postpone ?
15362 [ # # ]: 0 : priv->hw_q[queue].flow_transfer_completed :
15363 : 0 : priv->hw_q[queue].flow_transfer_pending;
15364 : 0 : rte_ring_enqueue(ring, hw_flow);
15365 : : flow_hw_q_inc_flow_ops(priv, queue);
15366 : 0 : return 0;
15367 : : }
15368 : 0 : ret = mlx5dr_matcher_resize_rule_move(other_matcher,
15369 : 0 : (struct mlx5dr_rule *)hw_flow->rule,
15370 : : &rule_attr);
15371 [ # # ]: 0 : if (ret) {
15372 : 0 : return rte_flow_error_set(error, rte_errno,
15373 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
15374 : : "flow transfer failed");
15375 : : }
15376 : : flow_hw_q_inc_flow_ops(priv, queue);
15377 : 0 : return 0;
15378 : : }
15379 : :
15380 : : /**
15381 : : * Internal validation function. For validating both actions and items.
15382 : : *
15383 : : * @param[in] dev
15384 : : * Pointer to the rte_eth_dev structure.
15385 : : * @param[in] attr
15386 : : * Pointer to the flow attributes.
15387 : : * @param[in] items
15388 : : * Pointer to the list of items.
15389 : : * @param[in] actions
15390 : : * Pointer to the list of actions.
15391 : : * @param[in] external
15392 : : * This flow rule is created by request external to PMD.
15393 : : * @param[in] hairpin
15394 : : * Number of hairpin TX actions, 0 means classic flow.
15395 : : * @param[out] error
15396 : : * Pointer to the error structure.
15397 : : *
15398 : : * @return
15399 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
15400 : : */
15401 : : static int
15402 : 0 : flow_hw_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
15403 : : const struct rte_flow_item items[],
15404 : : const struct rte_flow_action actions[] __rte_unused,
15405 : : bool external, int hairpin __rte_unused,
15406 : : struct rte_flow_error *error)
15407 : : {
15408 : 0 : const struct rte_flow_pattern_template_attr pattern_template_attr = {
15409 : : .relaxed_matching = 0,
15410 : 0 : .ingress = attr->ingress,
15411 : 0 : .egress = attr->egress,
15412 : 0 : .transfer = attr->transfer,
15413 : : };
15414 : 0 : uint64_t item_flags = 0;
15415 : : int ret = 0;
15416 : :
15417 [ # # ]: 0 : if (external) {
15418 : : /* Validate application items only */
15419 : 0 : ret = __flow_hw_pattern_validate(dev, &pattern_template_attr, items,
15420 : : &item_flags, true, error);
15421 [ # # ]: 0 : if (ret < 0)
15422 : 0 : return -rte_errno;
15423 : : }
15424 : : return 0;
15425 : : }
15426 : :
15427 : : const struct mlx5_flow_driver_ops mlx5_flow_hw_drv_ops = {
15428 : : .list_create = flow_hw_list_create,
15429 : : .list_destroy = flow_hw_list_destroy,
15430 : : .validate = flow_hw_validate,
15431 : : .info_get = flow_hw_info_get,
15432 : : .configure = flow_hw_configure,
15433 : : .pattern_validate = flow_hw_pattern_validate,
15434 : : .pattern_template_create = flow_hw_pattern_template_create,
15435 : : .pattern_template_destroy = flow_hw_pattern_template_destroy,
15436 : : .actions_validate = flow_hw_actions_validate,
15437 : : .actions_template_create = flow_hw_actions_template_create,
15438 : : .actions_template_destroy = flow_hw_actions_template_destroy,
15439 : : .template_table_create = flow_hw_template_table_create,
15440 : : .template_table_destroy = flow_hw_table_destroy,
15441 : : .table_resize = flow_hw_table_resize,
15442 : : .group_set_miss_actions = mlx5_flow_hw_group_set_miss_actions,
15443 : : .async_flow_create = flow_hw_async_flow_create,
15444 : : .async_flow_create_by_index = flow_hw_async_flow_create_by_index,
15445 : : .async_flow_update = flow_hw_async_flow_update,
15446 : : .async_flow_destroy = flow_hw_async_flow_destroy,
15447 : : .flow_update_resized = flow_hw_update_resized,
15448 : : .table_resize_complete = flow_hw_table_resize_complete,
15449 : : .pull = flow_hw_pull,
15450 : : .push = flow_hw_push,
15451 : : .async_action_create = flow_hw_action_handle_create,
15452 : : .async_action_destroy = flow_hw_action_handle_destroy,
15453 : : .async_action_update = flow_hw_action_handle_update,
15454 : : .async_action_query_update = flow_hw_async_action_handle_query_update,
15455 : : .async_action_query = flow_hw_action_handle_query,
15456 : : .action_validate = flow_hw_action_validate,
15457 : : .action_create = flow_hw_action_create,
15458 : : .action_destroy = flow_hw_action_destroy,
15459 : : .action_update = flow_hw_action_update,
15460 : : .action_query = flow_hw_action_query,
15461 : : .action_query_update = flow_hw_action_query_update,
15462 : : .action_list_handle_create = flow_hw_action_list_handle_create,
15463 : : .action_list_handle_destroy = flow_hw_action_list_handle_destroy,
15464 : : .action_list_handle_query_update =
15465 : : flow_hw_action_list_handle_query_update,
15466 : : .async_action_list_handle_create =
15467 : : flow_hw_async_action_list_handle_create,
15468 : : .async_action_list_handle_destroy =
15469 : : flow_hw_async_action_list_handle_destroy,
15470 : : .async_action_list_handle_query_update =
15471 : : flow_hw_async_action_list_handle_query_update,
15472 : : .query = flow_hw_query,
15473 : : .get_aged_flows = flow_hw_get_aged_flows,
15474 : : .get_q_aged_flows = flow_hw_get_q_aged_flows,
15475 : : .item_create = flow_dv_item_create,
15476 : : .item_release = flow_dv_item_release,
15477 : : .flow_calc_table_hash = flow_hw_calc_table_hash,
15478 : : .flow_calc_encap_hash = flow_hw_calc_encap_hash,
15479 : : };
15480 : :
15481 : : /**
15482 : : * Creates a control flow using flow template API on @p proxy_dev device,
15483 : : * on behalf of @p owner_dev device.
15484 : : *
15485 : : * This function uses locks internally to synchronize access to the
15486 : : * flow queue.
15487 : : *
15488 : : * Created flow is stored in private list associated with @p proxy_dev device.
15489 : : *
15490 : : * @param owner_dev
15491 : : * Pointer to Ethernet device on behalf of which flow is created.
15492 : : * @param proxy_dev
15493 : : * Pointer to Ethernet device on which flow is created.
15494 : : * @param table
15495 : : * Pointer to flow table.
15496 : : * @param items
15497 : : * Pointer to flow rule items.
15498 : : * @param item_template_idx
15499 : : * Index of an item template associated with @p table.
15500 : : * @param actions
15501 : : * Pointer to flow rule actions.
15502 : : * @param action_template_idx
15503 : : * Index of an action template associated with @p table.
15504 : : * @param info
15505 : : * Additional info about control flow rule.
15506 : : * @param external
15507 : : * External ctrl flow.
15508 : : *
15509 : : * @return
15510 : : * 0 on success, negative errno value otherwise and rte_errno set.
15511 : : */
15512 : : static __rte_unused int
15513 : 0 : flow_hw_create_ctrl_flow(struct rte_eth_dev *owner_dev,
15514 : : struct rte_eth_dev *proxy_dev,
15515 : : struct rte_flow_template_table *table,
15516 : : struct rte_flow_item items[],
15517 : : uint8_t item_template_idx,
15518 : : struct rte_flow_action actions[],
15519 : : uint8_t action_template_idx,
15520 : : struct mlx5_ctrl_flow_info *info,
15521 : : bool external)
15522 : : {
15523 : 0 : struct mlx5_priv *priv = proxy_dev->data->dev_private;
15524 : 0 : uint32_t queue = CTRL_QUEUE_ID(priv);
15525 : 0 : struct rte_flow_op_attr op_attr = {
15526 : : .postpone = 0,
15527 : : };
15528 : : struct rte_flow *flow = NULL;
15529 : : struct mlx5_ctrl_flow_entry *entry = NULL;
15530 : : int ret;
15531 : :
15532 : 0 : rte_spinlock_lock(&priv->hw_ctrl_lock);
15533 : 0 : entry = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_SYS, sizeof(*entry),
15534 : : 0, SOCKET_ID_ANY);
15535 [ # # ]: 0 : if (!entry) {
15536 : 0 : DRV_LOG(ERR, "port %u not enough memory to create control flows",
15537 : : proxy_dev->data->port_id);
15538 : 0 : rte_errno = ENOMEM;
15539 : : ret = -rte_errno;
15540 : 0 : goto error;
15541 : : }
15542 : 0 : flow = flow_hw_async_flow_create(proxy_dev, queue, &op_attr, table,
15543 : : items, item_template_idx,
15544 : : actions, action_template_idx,
15545 : : NULL, NULL);
15546 [ # # ]: 0 : if (!flow) {
15547 : 0 : DRV_LOG(ERR, "port %u failed to enqueue create control"
15548 : : " flow operation", proxy_dev->data->port_id);
15549 : 0 : ret = -rte_errno;
15550 : 0 : goto error;
15551 : : }
15552 : 0 : ret = __flow_hw_pull_comp(proxy_dev, queue, NULL);
15553 [ # # ]: 0 : if (ret) {
15554 : 0 : DRV_LOG(ERR, "port %u failed to insert control flow",
15555 : : proxy_dev->data->port_id);
15556 : 0 : rte_errno = EINVAL;
15557 : : ret = -rte_errno;
15558 : 0 : goto error;
15559 : : }
15560 : 0 : entry->owner_dev = owner_dev;
15561 : 0 : entry->flow = flow;
15562 [ # # ]: 0 : if (info)
15563 : 0 : entry->info = *info;
15564 : : else
15565 : 0 : entry->info.type = MLX5_CTRL_FLOW_TYPE_GENERAL;
15566 [ # # ]: 0 : if (external)
15567 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->hw_ext_ctrl_flows, entry, next);
15568 : : else
15569 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->hw_ctrl_flows, entry, next);
15570 : : rte_spinlock_unlock(&priv->hw_ctrl_lock);
15571 : 0 : return 0;
15572 : 0 : error:
15573 [ # # ]: 0 : if (entry)
15574 : 0 : mlx5_free(entry);
15575 : : rte_spinlock_unlock(&priv->hw_ctrl_lock);
15576 : 0 : return ret;
15577 : : }
15578 : :
15579 : : /**
15580 : : * Destroys a control flow @p flow using flow template API on @p dev device.
15581 : : *
15582 : : * This function uses locks internally to synchronize access to the
15583 : : * flow queue.
15584 : : *
15585 : : * If the @p flow is stored on any private list/pool, then caller must free up
15586 : : * the relevant resources.
15587 : : *
15588 : : * @param dev
15589 : : * Pointer to Ethernet device.
15590 : : * @param flow
15591 : : * Pointer to flow rule.
15592 : : *
15593 : : * @return
15594 : : * 0 on success, non-zero value otherwise.
15595 : : */
15596 : : static int
15597 : 0 : flow_hw_destroy_ctrl_flow(struct rte_eth_dev *dev, struct rte_flow *flow)
15598 : : {
15599 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
15600 : 0 : uint32_t queue = CTRL_QUEUE_ID(priv);
15601 : 0 : struct rte_flow_op_attr op_attr = {
15602 : : .postpone = 0,
15603 : : };
15604 : : int ret;
15605 : :
15606 : 0 : rte_spinlock_lock(&priv->hw_ctrl_lock);
15607 : 0 : ret = flow_hw_async_flow_destroy(dev, queue, &op_attr, flow, NULL, NULL);
15608 [ # # ]: 0 : if (ret) {
15609 : 0 : DRV_LOG(ERR, "port %u failed to enqueue destroy control"
15610 : : " flow operation", dev->data->port_id);
15611 : 0 : goto exit;
15612 : : }
15613 : 0 : ret = __flow_hw_pull_comp(dev, queue, NULL);
15614 [ # # ]: 0 : if (ret) {
15615 : 0 : DRV_LOG(ERR, "port %u failed to destroy control flow",
15616 : : dev->data->port_id);
15617 : 0 : rte_errno = EINVAL;
15618 : : ret = -rte_errno;
15619 : 0 : goto exit;
15620 : : }
15621 : 0 : exit:
15622 : : rte_spinlock_unlock(&priv->hw_ctrl_lock);
15623 : 0 : return ret;
15624 : : }
15625 : :
15626 : : /**
15627 : : * Destroys control flows created on behalf of @p owner device on @p dev device.
15628 : : *
15629 : : * @param dev
15630 : : * Pointer to Ethernet device on which control flows were created.
15631 : : * @param owner
15632 : : * Pointer to Ethernet device owning control flows.
15633 : : *
15634 : : * @return
15635 : : * 0 on success, otherwise negative error code is returned and
15636 : : * rte_errno is set.
15637 : : */
15638 : : static int
15639 : 0 : flow_hw_flush_ctrl_flows_owned_by(struct rte_eth_dev *dev, struct rte_eth_dev *owner)
15640 : : {
15641 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
15642 : : struct mlx5_ctrl_flow_entry *cf;
15643 : : struct mlx5_ctrl_flow_entry *cf_next;
15644 : : int ret;
15645 : :
15646 : 0 : cf = LIST_FIRST(&priv->hw_ctrl_flows);
15647 [ # # ]: 0 : while (cf != NULL) {
15648 : 0 : cf_next = LIST_NEXT(cf, next);
15649 [ # # ]: 0 : if (cf->owner_dev == owner) {
15650 : 0 : ret = flow_hw_destroy_ctrl_flow(dev, cf->flow);
15651 [ # # ]: 0 : if (ret) {
15652 : 0 : rte_errno = ret;
15653 : 0 : return -ret;
15654 : : }
15655 [ # # ]: 0 : LIST_REMOVE(cf, next);
15656 : 0 : mlx5_free(cf);
15657 : : }
15658 : : cf = cf_next;
15659 : : }
15660 : : return 0;
15661 : : }
15662 : :
15663 : : /**
15664 : : * Destroys control flows created for @p owner_dev device.
15665 : : *
15666 : : * @param owner_dev
15667 : : * Pointer to Ethernet device owning control flows.
15668 : : *
15669 : : * @return
15670 : : * 0 on success, otherwise negative error code is returned and
15671 : : * rte_errno is set.
15672 : : */
15673 : : int
15674 : 0 : mlx5_flow_hw_flush_ctrl_flows(struct rte_eth_dev *owner_dev)
15675 : : {
15676 : 0 : struct mlx5_priv *owner_priv = owner_dev->data->dev_private;
15677 : : struct rte_eth_dev *proxy_dev;
15678 : 0 : uint16_t owner_port_id = owner_dev->data->port_id;
15679 : 0 : uint16_t proxy_port_id = owner_dev->data->port_id;
15680 : : int ret;
15681 : :
15682 : : /* Flush all flows created by this port for itself. */
15683 : 0 : ret = flow_hw_flush_ctrl_flows_owned_by(owner_dev, owner_dev);
15684 [ # # ]: 0 : if (ret)
15685 : : return ret;
15686 : : /* Flush all flows created for this port on proxy port. */
15687 [ # # ]: 0 : if (owner_priv->sh->config.dv_esw_en) {
15688 : 0 : ret = rte_flow_pick_transfer_proxy(owner_port_id, &proxy_port_id, NULL);
15689 [ # # ]: 0 : if (ret == -ENODEV) {
15690 : 0 : DRV_LOG(DEBUG, "Unable to find transfer proxy port for port %u. It was "
15691 : : "probably closed. Control flows were cleared.",
15692 : : owner_port_id);
15693 : 0 : rte_errno = 0;
15694 : 0 : return 0;
15695 [ # # ]: 0 : } else if (ret) {
15696 : 0 : DRV_LOG(ERR, "Unable to find proxy port for port %u (ret = %d)",
15697 : : owner_port_id, ret);
15698 : 0 : return ret;
15699 : : }
15700 : 0 : proxy_dev = &rte_eth_devices[proxy_port_id];
15701 : : } else {
15702 : : proxy_dev = owner_dev;
15703 : : }
15704 : 0 : return flow_hw_flush_ctrl_flows_owned_by(proxy_dev, owner_dev);
15705 : : }
15706 : :
15707 : : /**
15708 : : * Destroys all control flows created on @p dev device.
15709 : : *
15710 : : * @param owner_dev
15711 : : * Pointer to Ethernet device.
15712 : : *
15713 : : * @return
15714 : : * 0 on success, otherwise negative error code is returned and
15715 : : * rte_errno is set.
15716 : : */
15717 : : static int
15718 : 0 : flow_hw_flush_all_ctrl_flows(struct rte_eth_dev *dev)
15719 : : {
15720 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
15721 : : struct mlx5_ctrl_flow_entry *cf;
15722 : : struct mlx5_ctrl_flow_entry *cf_next;
15723 : : int ret;
15724 : :
15725 : 0 : cf = LIST_FIRST(&priv->hw_ctrl_flows);
15726 [ # # ]: 0 : while (cf != NULL) {
15727 : 0 : cf_next = LIST_NEXT(cf, next);
15728 : 0 : ret = flow_hw_destroy_ctrl_flow(dev, cf->flow);
15729 [ # # ]: 0 : if (ret) {
15730 : 0 : rte_errno = ret;
15731 : 0 : return -ret;
15732 : : }
15733 [ # # ]: 0 : LIST_REMOVE(cf, next);
15734 : 0 : mlx5_free(cf);
15735 : : cf = cf_next;
15736 : : }
15737 : 0 : cf = LIST_FIRST(&priv->hw_ext_ctrl_flows);
15738 [ # # ]: 0 : while (cf != NULL) {
15739 : 0 : cf_next = LIST_NEXT(cf, next);
15740 : 0 : ret = flow_hw_destroy_ctrl_flow(dev, cf->flow);
15741 [ # # ]: 0 : if (ret) {
15742 : 0 : rte_errno = ret;
15743 : 0 : return -ret;
15744 : : }
15745 [ # # ]: 0 : LIST_REMOVE(cf, next);
15746 : 0 : mlx5_free(cf);
15747 : : cf = cf_next;
15748 : : }
15749 : : return 0;
15750 : : }
15751 : :
15752 : : int
15753 : 0 : mlx5_flow_hw_esw_create_sq_miss_flow(struct rte_eth_dev *dev, uint32_t sqn, bool external)
15754 : : {
15755 : 0 : uint16_t port_id = dev->data->port_id;
15756 : 0 : struct rte_flow_item_ethdev esw_mgr_spec = {
15757 : : .port_id = MLX5_REPRESENTED_PORT_ESW_MGR,
15758 : : };
15759 : 0 : struct rte_flow_item_ethdev esw_mgr_mask = {
15760 : : .port_id = MLX5_REPRESENTED_PORT_ESW_MGR,
15761 : : };
15762 : 0 : struct rte_flow_item_tag reg_c0_spec = {
15763 : : .index = (uint8_t)REG_C_0,
15764 : : .data = flow_hw_esw_mgr_regc_marker(dev),
15765 : : };
15766 : 0 : struct rte_flow_item_tag reg_c0_mask = {
15767 : : .index = 0xff,
15768 : : .data = flow_hw_esw_mgr_regc_marker_mask(dev),
15769 : : };
15770 : 0 : struct mlx5_rte_flow_item_sq sq_spec = {
15771 : : .queue = sqn,
15772 : : };
15773 : 0 : struct rte_flow_action_ethdev port = {
15774 : : .port_id = port_id,
15775 : : };
15776 : 0 : struct rte_flow_item items[3] = { { 0 } };
15777 : 0 : struct rte_flow_action actions[3] = { { 0 } };
15778 : 0 : struct mlx5_ctrl_flow_info flow_info = {
15779 : : .type = MLX5_CTRL_FLOW_TYPE_SQ_MISS_ROOT,
15780 : : .esw_mgr_sq = sqn,
15781 : : };
15782 : : struct rte_eth_dev *proxy_dev;
15783 : : struct mlx5_priv *proxy_priv;
15784 : 0 : uint16_t proxy_port_id = dev->data->port_id;
15785 : : int ret;
15786 : :
15787 : 0 : ret = rte_flow_pick_transfer_proxy(port_id, &proxy_port_id, NULL);
15788 [ # # ]: 0 : if (ret) {
15789 : 0 : DRV_LOG(ERR, "Unable to pick transfer proxy port for port %u. Transfer proxy "
15790 : : "port must be present to create default SQ miss flows.",
15791 : : port_id);
15792 : 0 : return ret;
15793 : : }
15794 : 0 : proxy_dev = &rte_eth_devices[proxy_port_id];
15795 : 0 : proxy_priv = proxy_dev->data->dev_private;
15796 [ # # ]: 0 : if (!proxy_priv->dr_ctx) {
15797 : 0 : DRV_LOG(DEBUG, "Transfer proxy port (port %u) of port %u must be configured "
15798 : : "for HWS to create default SQ miss flows. Default flows will "
15799 : : "not be created.",
15800 : : proxy_port_id, port_id);
15801 : 0 : return 0;
15802 : : }
15803 [ # # ]: 0 : if (!proxy_priv->hw_ctrl_fdb ||
15804 [ # # ]: 0 : !proxy_priv->hw_ctrl_fdb->hw_esw_sq_miss_root_tbl ||
15805 [ # # ]: 0 : !proxy_priv->hw_ctrl_fdb->hw_esw_sq_miss_tbl) {
15806 : 0 : DRV_LOG(ERR, "Transfer proxy port (port %u) of port %u was configured, but "
15807 : : "default flow tables were not created.",
15808 : : proxy_port_id, port_id);
15809 : 0 : rte_errno = ENOMEM;
15810 : 0 : return -rte_errno;
15811 : : }
15812 : : /*
15813 : : * Create a root SQ miss flow rule - match E-Switch Manager and SQ,
15814 : : * and jump to group 1.
15815 : : */
15816 : 0 : items[0] = (struct rte_flow_item){
15817 : : .type = RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT,
15818 : : .spec = &esw_mgr_spec,
15819 : : .mask = &esw_mgr_mask,
15820 : : };
15821 : 0 : items[1] = (struct rte_flow_item){
15822 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_SQ,
15823 : : .spec = &sq_spec,
15824 : : };
15825 : 0 : items[2] = (struct rte_flow_item){
15826 : : .type = RTE_FLOW_ITEM_TYPE_END,
15827 : : };
15828 : 0 : actions[0] = (struct rte_flow_action){
15829 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
15830 : : };
15831 : 0 : actions[1] = (struct rte_flow_action){
15832 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
15833 : : };
15834 : 0 : actions[2] = (struct rte_flow_action) {
15835 : : .type = RTE_FLOW_ACTION_TYPE_END,
15836 : : };
15837 : 0 : ret = flow_hw_create_ctrl_flow(dev, proxy_dev,
15838 : : proxy_priv->hw_ctrl_fdb->hw_esw_sq_miss_root_tbl,
15839 : : items, 0, actions, 0, &flow_info, external);
15840 [ # # ]: 0 : if (ret) {
15841 : 0 : DRV_LOG(ERR, "Port %u failed to create root SQ miss flow rule for SQ %u, ret %d",
15842 : : port_id, sqn, ret);
15843 : 0 : return ret;
15844 : : }
15845 : : /*
15846 : : * Create a non-root SQ miss flow rule - match REG_C_0 marker and SQ,
15847 : : * and forward to port.
15848 : : */
15849 : 0 : items[0] = (struct rte_flow_item){
15850 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_TAG,
15851 : : .spec = ®_c0_spec,
15852 : : .mask = ®_c0_mask,
15853 : : };
15854 : 0 : items[1] = (struct rte_flow_item){
15855 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_SQ,
15856 : : .spec = &sq_spec,
15857 : : };
15858 : 0 : items[2] = (struct rte_flow_item){
15859 : : .type = RTE_FLOW_ITEM_TYPE_END,
15860 : : };
15861 : 0 : actions[0] = (struct rte_flow_action){
15862 : : .type = RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT,
15863 : : .conf = &port,
15864 : : };
15865 : 0 : actions[1] = (struct rte_flow_action){
15866 : : .type = RTE_FLOW_ACTION_TYPE_END,
15867 : : };
15868 : 0 : flow_info.type = MLX5_CTRL_FLOW_TYPE_SQ_MISS;
15869 : 0 : ret = flow_hw_create_ctrl_flow(dev, proxy_dev,
15870 : 0 : proxy_priv->hw_ctrl_fdb->hw_esw_sq_miss_tbl,
15871 : : items, 0, actions, 0, &flow_info, external);
15872 [ # # ]: 0 : if (ret) {
15873 : 0 : DRV_LOG(ERR, "Port %u failed to create HWS SQ miss flow rule for SQ %u, ret %d",
15874 : : port_id, sqn, ret);
15875 : 0 : return ret;
15876 : : }
15877 : : return 0;
15878 : : }
15879 : :
15880 : : static bool
15881 : : flow_hw_is_matching_sq_miss_flow(struct mlx5_ctrl_flow_entry *cf,
15882 : : struct rte_eth_dev *dev,
15883 : : uint32_t sqn)
15884 : : {
15885 : 0 : if (cf->owner_dev != dev)
15886 : : return false;
15887 [ # # # # ]: 0 : if (cf->info.type == MLX5_CTRL_FLOW_TYPE_SQ_MISS_ROOT && cf->info.esw_mgr_sq == sqn)
15888 : : return true;
15889 [ # # # # ]: 0 : if (cf->info.type == MLX5_CTRL_FLOW_TYPE_SQ_MISS && cf->info.esw_mgr_sq == sqn)
15890 : : return true;
15891 : : return false;
15892 : : }
15893 : :
15894 : : int
15895 : 0 : mlx5_flow_hw_esw_destroy_sq_miss_flow(struct rte_eth_dev *dev, uint32_t sqn)
15896 : : {
15897 : 0 : uint16_t port_id = dev->data->port_id;
15898 : 0 : uint16_t proxy_port_id = dev->data->port_id;
15899 : : struct rte_eth_dev *proxy_dev;
15900 : : struct mlx5_priv *proxy_priv;
15901 : : struct mlx5_ctrl_flow_entry *cf;
15902 : : struct mlx5_ctrl_flow_entry *cf_next;
15903 : : int ret;
15904 : :
15905 : 0 : ret = rte_flow_pick_transfer_proxy(port_id, &proxy_port_id, NULL);
15906 [ # # ]: 0 : if (ret) {
15907 : 0 : DRV_LOG(ERR, "Unable to pick transfer proxy port for port %u. Transfer proxy "
15908 : : "port must be present for default SQ miss flow rules to exist.",
15909 : : port_id);
15910 : 0 : return ret;
15911 : : }
15912 : 0 : proxy_dev = &rte_eth_devices[proxy_port_id];
15913 : 0 : proxy_priv = proxy_dev->data->dev_private;
15914 : : /* FDB default flow rules must be enabled. */
15915 : : MLX5_ASSERT(proxy_priv->sh->config.fdb_def_rule);
15916 [ # # ]: 0 : if (!proxy_priv->dr_ctx)
15917 : : return 0;
15918 [ # # ]: 0 : if (!proxy_priv->hw_ctrl_fdb ||
15919 [ # # ]: 0 : !proxy_priv->hw_ctrl_fdb->hw_esw_sq_miss_root_tbl ||
15920 [ # # ]: 0 : !proxy_priv->hw_ctrl_fdb->hw_esw_sq_miss_tbl)
15921 : : return 0;
15922 : 0 : cf = LIST_FIRST(&proxy_priv->hw_ctrl_flows);
15923 [ # # ]: 0 : while (cf != NULL) {
15924 [ # # ]: 0 : cf_next = LIST_NEXT(cf, next);
15925 : : if (flow_hw_is_matching_sq_miss_flow(cf, dev, sqn)) {
15926 : 0 : claim_zero(flow_hw_destroy_ctrl_flow(proxy_dev, cf->flow));
15927 [ # # ]: 0 : LIST_REMOVE(cf, next);
15928 : 0 : mlx5_free(cf);
15929 : : }
15930 : : cf = cf_next;
15931 : : }
15932 : : return 0;
15933 : : }
15934 : :
15935 : : int
15936 : 0 : mlx5_flow_hw_esw_create_default_jump_flow(struct rte_eth_dev *dev)
15937 : : {
15938 : 0 : uint16_t port_id = dev->data->port_id;
15939 : 0 : struct rte_flow_item_ethdev port_spec = {
15940 : : .port_id = port_id,
15941 : : };
15942 : 0 : struct rte_flow_item items[] = {
15943 : : {
15944 : : .type = RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT,
15945 : : .spec = &port_spec,
15946 : : },
15947 : : {
15948 : : .type = RTE_FLOW_ITEM_TYPE_END,
15949 : : },
15950 : : };
15951 : 0 : struct rte_flow_action_jump jump = {
15952 : : .group = 1,
15953 : : };
15954 : 0 : struct rte_flow_action actions[] = {
15955 : : {
15956 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
15957 : : .conf = &jump,
15958 : : },
15959 : : {
15960 : : .type = RTE_FLOW_ACTION_TYPE_END,
15961 : : }
15962 : : };
15963 : 0 : struct mlx5_ctrl_flow_info flow_info = {
15964 : : .type = MLX5_CTRL_FLOW_TYPE_DEFAULT_JUMP,
15965 : : };
15966 : : struct rte_eth_dev *proxy_dev;
15967 : : struct mlx5_priv *proxy_priv;
15968 : 0 : uint16_t proxy_port_id = dev->data->port_id;
15969 : : int ret;
15970 : :
15971 : 0 : ret = rte_flow_pick_transfer_proxy(port_id, &proxy_port_id, NULL);
15972 [ # # ]: 0 : if (ret) {
15973 : 0 : DRV_LOG(ERR, "Unable to pick transfer proxy port for port %u. Transfer proxy "
15974 : : "port must be present to create default FDB jump rule.",
15975 : : port_id);
15976 : 0 : return ret;
15977 : : }
15978 : 0 : proxy_dev = &rte_eth_devices[proxy_port_id];
15979 : 0 : proxy_priv = proxy_dev->data->dev_private;
15980 : : /* FDB default flow rules must be enabled. */
15981 : : MLX5_ASSERT(proxy_priv->sh->config.fdb_def_rule);
15982 [ # # ]: 0 : if (!proxy_priv->dr_ctx) {
15983 : 0 : DRV_LOG(DEBUG, "Transfer proxy port (port %u) of port %u must be configured "
15984 : : "for HWS to create default FDB jump rule. Default rule will "
15985 : : "not be created.",
15986 : : proxy_port_id, port_id);
15987 : 0 : return 0;
15988 : : }
15989 [ # # # # ]: 0 : if (!proxy_priv->hw_ctrl_fdb || !proxy_priv->hw_ctrl_fdb->hw_esw_zero_tbl) {
15990 : 0 : DRV_LOG(ERR, "Transfer proxy port (port %u) of port %u was configured, but "
15991 : : "default flow tables were not created.",
15992 : : proxy_port_id, port_id);
15993 : 0 : rte_errno = EINVAL;
15994 : 0 : return -rte_errno;
15995 : : }
15996 : 0 : return flow_hw_create_ctrl_flow(dev, proxy_dev,
15997 : : proxy_priv->hw_ctrl_fdb->hw_esw_zero_tbl,
15998 : : items, 0, actions, 0, &flow_info, false);
15999 : : }
16000 : :
16001 : : int
16002 : 0 : mlx5_flow_hw_create_tx_default_mreg_copy_flow(struct rte_eth_dev *dev)
16003 : : {
16004 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16005 : 0 : struct rte_flow_item_eth promisc = {
16006 : : .hdr.dst_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
16007 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
16008 : : .hdr.ether_type = 0,
16009 : : };
16010 : 0 : struct rte_flow_item eth_all[] = {
16011 : : [0] = {
16012 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
16013 : : .spec = &promisc,
16014 : : .mask = &promisc,
16015 : : },
16016 : : [1] = {
16017 : : .type = RTE_FLOW_ITEM_TYPE_END,
16018 : : },
16019 : : };
16020 : 0 : struct rte_flow_action_modify_field mreg_action = {
16021 : : .operation = RTE_FLOW_MODIFY_SET,
16022 : : .dst = {
16023 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
16024 : : .tag_index = REG_C_1,
16025 : : },
16026 : : .src = {
16027 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
16028 : : .tag_index = REG_A,
16029 : : },
16030 : : .width = 32,
16031 : : };
16032 : 0 : struct rte_flow_action copy_reg_action[] = {
16033 : : [0] = {
16034 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
16035 : : .conf = &mreg_action,
16036 : : },
16037 : : [1] = {
16038 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
16039 : : },
16040 : : [2] = {
16041 : : .type = RTE_FLOW_ACTION_TYPE_END,
16042 : : },
16043 : : };
16044 : 0 : struct mlx5_ctrl_flow_info flow_info = {
16045 : : .type = MLX5_CTRL_FLOW_TYPE_TX_META_COPY,
16046 : : };
16047 : :
16048 : : MLX5_ASSERT(priv->master);
16049 [ # # ]: 0 : if (!priv->dr_ctx ||
16050 [ # # ]: 0 : !priv->hw_ctrl_fdb ||
16051 [ # # ]: 0 : !priv->hw_ctrl_fdb->hw_tx_meta_cpy_tbl)
16052 : : return 0;
16053 : 0 : return flow_hw_create_ctrl_flow(dev, dev,
16054 : : priv->hw_ctrl_fdb->hw_tx_meta_cpy_tbl,
16055 : : eth_all, 0, copy_reg_action, 0, &flow_info, false);
16056 : : }
16057 : :
16058 : : int
16059 : 0 : mlx5_flow_hw_tx_repr_matching_flow(struct rte_eth_dev *dev, uint32_t sqn, bool external)
16060 : : {
16061 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16062 : 0 : struct mlx5_rte_flow_item_sq sq_spec = {
16063 : : .queue = sqn,
16064 : : };
16065 : 0 : struct rte_flow_item items[] = {
16066 : : {
16067 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_SQ,
16068 : : .spec = &sq_spec,
16069 : : },
16070 : : {
16071 : : .type = RTE_FLOW_ITEM_TYPE_END,
16072 : : },
16073 : : };
16074 : : /*
16075 : : * Allocate actions array suitable for all cases - extended metadata enabled or not.
16076 : : * With extended metadata there will be an additional MODIFY_FIELD action before JUMP.
16077 : : */
16078 : 0 : struct rte_flow_action actions[] = {
16079 : : { .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD },
16080 : : { .type = RTE_FLOW_ACTION_TYPE_JUMP },
16081 : : { .type = RTE_FLOW_ACTION_TYPE_END },
16082 : : { .type = RTE_FLOW_ACTION_TYPE_END },
16083 : : };
16084 : 0 : struct mlx5_ctrl_flow_info flow_info = {
16085 : : .type = MLX5_CTRL_FLOW_TYPE_TX_REPR_MATCH,
16086 : : .tx_repr_sq = sqn,
16087 : : };
16088 : :
16089 : : /* It is assumed that caller checked for representor matching. */
16090 : : MLX5_ASSERT(priv->sh->config.repr_matching);
16091 [ # # ]: 0 : if (!priv->dr_ctx) {
16092 : 0 : DRV_LOG(DEBUG, "Port %u must be configured for HWS, before creating "
16093 : : "default egress flow rules. Omitting creation.",
16094 : : dev->data->port_id);
16095 : 0 : return 0;
16096 : : }
16097 [ # # ]: 0 : if (!priv->hw_tx_repr_tagging_tbl) {
16098 : 0 : DRV_LOG(ERR, "Port %u is configured for HWS, but table for default "
16099 : : "egress flow rules does not exist.",
16100 : : dev->data->port_id);
16101 : 0 : rte_errno = EINVAL;
16102 : 0 : return -rte_errno;
16103 : : }
16104 : : /*
16105 : : * If extended metadata mode is enabled, then an additional MODIFY_FIELD action must be
16106 : : * placed before terminating JUMP action.
16107 : : */
16108 [ # # ]: 0 : if (priv->sh->config.dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS) {
16109 : 0 : actions[1].type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD;
16110 : 0 : actions[2].type = RTE_FLOW_ACTION_TYPE_JUMP;
16111 : : }
16112 : 0 : return flow_hw_create_ctrl_flow(dev, dev, priv->hw_tx_repr_tagging_tbl,
16113 : : items, 0, actions, 0, &flow_info, external);
16114 : : }
16115 : :
16116 : : int
16117 : 0 : mlx5_flow_hw_lacp_rx_flow(struct rte_eth_dev *dev)
16118 : : {
16119 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16120 : 0 : struct rte_flow_item_eth lacp_item = {
16121 : : .type = RTE_BE16(RTE_ETHER_TYPE_SLOW),
16122 : : };
16123 : 0 : struct rte_flow_item eth_lacp[] = {
16124 : : [0] = {
16125 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
16126 : : .spec = &lacp_item,
16127 : : .mask = &lacp_item,
16128 : : },
16129 : : [1] = {
16130 : : .type = RTE_FLOW_ITEM_TYPE_END,
16131 : : },
16132 : : };
16133 : 0 : struct rte_flow_action miss_action[] = {
16134 : : [0] = {
16135 : : .type = (enum rte_flow_action_type)
16136 : : MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS,
16137 : : },
16138 : : [1] = {
16139 : : .type = RTE_FLOW_ACTION_TYPE_END,
16140 : : },
16141 : : };
16142 : 0 : struct mlx5_ctrl_flow_info flow_info = {
16143 : : .type = MLX5_CTRL_FLOW_TYPE_LACP_RX,
16144 : : };
16145 : :
16146 [ # # # # : 0 : if (!priv->dr_ctx || !priv->hw_ctrl_fdb || !priv->hw_ctrl_fdb->hw_lacp_rx_tbl)
# # ]
16147 : : return 0;
16148 : 0 : return flow_hw_create_ctrl_flow(dev, dev,
16149 : : priv->hw_ctrl_fdb->hw_lacp_rx_tbl,
16150 : : eth_lacp, 0, miss_action, 0, &flow_info, false);
16151 : : }
16152 : :
16153 : : static uint32_t
16154 : : __calc_pattern_flags(const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type)
16155 : : {
16156 : : switch (eth_pattern_type) {
16157 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL:
16158 : : return MLX5_CTRL_PROMISCUOUS;
16159 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL_MCAST:
16160 : : return MLX5_CTRL_ALL_MULTICAST;
16161 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST:
16162 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST_VLAN:
16163 : : return MLX5_CTRL_BROADCAST;
16164 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST:
16165 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST_VLAN:
16166 : : return MLX5_CTRL_IPV4_MULTICAST;
16167 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST:
16168 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST_VLAN:
16169 : : return MLX5_CTRL_IPV6_MULTICAST;
16170 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC:
16171 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN:
16172 : : return MLX5_CTRL_DMAC;
16173 : : default:
16174 : : /* Should not reach here. */
16175 : : MLX5_ASSERT(false);
16176 : : return 0;
16177 : : }
16178 : : }
16179 : :
16180 : : static uint32_t
16181 : : __calc_vlan_flags(const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type)
16182 : : {
16183 [ # # ]: 0 : switch (eth_pattern_type) {
16184 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST_VLAN:
16185 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST_VLAN:
16186 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST_VLAN:
16187 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN:
16188 : : return MLX5_CTRL_VLAN_FILTER;
16189 : 0 : default:
16190 : 0 : return 0;
16191 : : }
16192 : : }
16193 : :
16194 : : static bool
16195 [ # # ]: 0 : eth_pattern_type_is_requested(const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type,
16196 : : uint32_t flags)
16197 : : {
16198 : : uint32_t pattern_flags = __calc_pattern_flags(eth_pattern_type);
16199 : : uint32_t vlan_flags = __calc_vlan_flags(eth_pattern_type);
16200 : 0 : bool pattern_requested = !!(pattern_flags & flags);
16201 [ # # # # ]: 0 : bool consider_vlan = vlan_flags || (MLX5_CTRL_VLAN_FILTER & flags);
16202 : 0 : bool vlan_requested = !!(vlan_flags & flags);
16203 : :
16204 [ # # ]: 0 : if (consider_vlan)
16205 : 0 : return pattern_requested && vlan_requested;
16206 : : else
16207 : : return pattern_requested;
16208 : : }
16209 : :
16210 : : static bool
16211 : : rss_type_is_requested(struct mlx5_priv *priv,
16212 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
16213 : : {
16214 : 0 : struct rte_flow_actions_template *at = priv->hw_ctrl_rx->rss[rss_type];
16215 : : unsigned int i;
16216 : :
16217 [ # # # # ]: 0 : for (i = 0; at->actions[i].type != RTE_FLOW_ACTION_TYPE_END; ++i) {
16218 [ # # # # ]: 0 : if (at->actions[i].type == RTE_FLOW_ACTION_TYPE_RSS) {
16219 : 0 : const struct rte_flow_action_rss *rss = at->actions[i].conf;
16220 : 0 : uint64_t rss_types = rss->types;
16221 : :
16222 [ # # # # ]: 0 : if ((rss_types & priv->rss_conf.rss_hf) != rss_types)
16223 : : return false;
16224 : : }
16225 : : }
16226 : : return true;
16227 : : }
16228 : :
16229 : : static const struct rte_flow_item_eth *
16230 : : __get_eth_spec(const enum mlx5_flow_ctrl_rx_eth_pattern_type pattern)
16231 : : {
16232 : 0 : switch (pattern) {
16233 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL:
16234 : : return &ctrl_rx_eth_promisc_spec;
16235 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL_MCAST:
16236 : 0 : return &ctrl_rx_eth_mcast_spec;
16237 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST:
16238 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST_VLAN:
16239 : 0 : return &ctrl_rx_eth_bcast_spec;
16240 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST:
16241 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST_VLAN:
16242 : 0 : return &ctrl_rx_eth_ipv4_mcast_spec;
16243 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST:
16244 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST_VLAN:
16245 : 0 : return &ctrl_rx_eth_ipv6_mcast_spec;
16246 : 0 : default:
16247 : : /* This case should not be reached. */
16248 : : MLX5_ASSERT(false);
16249 : 0 : return NULL;
16250 : : }
16251 : : }
16252 : :
16253 : : static int
16254 [ # # # # : 0 : __flow_hw_ctrl_flows_single(struct rte_eth_dev *dev,
# # ]
16255 : : struct rte_flow_template_table *tbl,
16256 : : const enum mlx5_flow_ctrl_rx_eth_pattern_type pattern_type,
16257 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
16258 : : {
16259 : : const struct rte_flow_item_eth *eth_spec = __get_eth_spec(pattern_type);
16260 : : struct rte_flow_item items[5];
16261 : 0 : struct rte_flow_action actions[] = {
16262 : : { .type = RTE_FLOW_ACTION_TYPE_RSS },
16263 : : { .type = RTE_FLOW_ACTION_TYPE_END },
16264 : : };
16265 : 0 : struct mlx5_ctrl_flow_info flow_info = {
16266 : : .type = MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS,
16267 : : };
16268 : :
16269 [ # # ]: 0 : if (!eth_spec)
16270 : : return -EINVAL;
16271 : : memset(items, 0, sizeof(items));
16272 : 0 : items[0] = (struct rte_flow_item){
16273 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
16274 : : .spec = eth_spec,
16275 : : };
16276 [ # # # ]: 0 : items[1] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_VOID };
16277 [ # # # ]: 0 : items[2] = flow_hw_get_ctrl_rx_l3_item(rss_type);
16278 : 0 : items[3] = flow_hw_get_ctrl_rx_l4_item(rss_type);
16279 : 0 : items[4] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_END };
16280 : : /* Without VLAN filtering, only a single flow rule must be created. */
16281 : 0 : return flow_hw_create_ctrl_flow(dev, dev, tbl, items, 0, actions, 0, &flow_info, false);
16282 : : }
16283 : :
16284 : : static int
16285 : 0 : __flow_hw_ctrl_flows_single_vlan(struct rte_eth_dev *dev,
16286 : : struct rte_flow_template_table *tbl,
16287 : : const enum mlx5_flow_ctrl_rx_eth_pattern_type pattern_type,
16288 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
16289 : : {
16290 [ # # # # : 0 : struct mlx5_priv *priv = dev->data->dev_private;
# # ]
16291 : : const struct rte_flow_item_eth *eth_spec = __get_eth_spec(pattern_type);
16292 : : struct rte_flow_item items[5];
16293 : 0 : struct rte_flow_action actions[] = {
16294 : : { .type = RTE_FLOW_ACTION_TYPE_RSS },
16295 : : { .type = RTE_FLOW_ACTION_TYPE_END },
16296 : : };
16297 : 0 : struct mlx5_ctrl_flow_info flow_info = {
16298 : : .type = MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS,
16299 : : };
16300 : : unsigned int i;
16301 : :
16302 [ # # ]: 0 : if (!eth_spec)
16303 : : return -EINVAL;
16304 : : memset(items, 0, sizeof(items));
16305 : 0 : items[0] = (struct rte_flow_item){
16306 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
16307 : : .spec = eth_spec,
16308 : : };
16309 : : /* Optional VLAN for now will be VOID - will be filled later. */
16310 [ # # # ]: 0 : items[1] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_VLAN };
16311 [ # # # ]: 0 : items[2] = flow_hw_get_ctrl_rx_l3_item(rss_type);
16312 : 0 : items[3] = flow_hw_get_ctrl_rx_l4_item(rss_type);
16313 : 0 : items[4] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_END };
16314 : : /* Since VLAN filtering is done, create a single flow rule for each registered vid. */
16315 [ # # ]: 0 : for (i = 0; i < priv->vlan_filter_n; ++i) {
16316 : 0 : uint16_t vlan = priv->vlan_filter[i];
16317 : 0 : struct rte_flow_item_vlan vlan_spec = {
16318 [ # # ]: 0 : .hdr.vlan_tci = rte_cpu_to_be_16(vlan),
16319 : : };
16320 : :
16321 : 0 : items[1].spec = &vlan_spec;
16322 [ # # ]: 0 : if (flow_hw_create_ctrl_flow(dev, dev,
16323 : : tbl, items, 0, actions, 0, &flow_info, false))
16324 : 0 : return -rte_errno;
16325 : : }
16326 : : return 0;
16327 : : }
16328 : :
16329 : : static int
16330 : 0 : __flow_hw_ctrl_flows_unicast_create(struct rte_eth_dev *dev,
16331 : : struct rte_flow_template_table *tbl,
16332 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type,
16333 : : const struct rte_ether_addr *addr)
16334 : : {
16335 : 0 : struct rte_flow_item_eth eth_spec = {
16336 : : .hdr.dst_addr = *addr,
16337 : : };
16338 : : struct rte_flow_item items[5];
16339 : 0 : struct rte_flow_action actions[] = {
16340 : : { .type = RTE_FLOW_ACTION_TYPE_RSS },
16341 : : { .type = RTE_FLOW_ACTION_TYPE_END },
16342 : : };
16343 [ # # # ]: 0 : struct mlx5_ctrl_flow_info flow_info = {
16344 : : .type = MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC,
16345 : : .uc = {
16346 : : .dmac = *addr,
16347 : : },
16348 : : };
16349 : :
16350 : : memset(items, 0, sizeof(items));
16351 : 0 : items[0] = (struct rte_flow_item){
16352 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
16353 : : .spec = ð_spec,
16354 : : };
16355 [ # # # ]: 0 : items[1] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_VOID };
16356 [ # # # ]: 0 : items[2] = flow_hw_get_ctrl_rx_l3_item(rss_type);
16357 : 0 : items[3] = flow_hw_get_ctrl_rx_l4_item(rss_type);
16358 : 0 : items[4] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_END };
16359 : :
16360 [ # # ]: 0 : if (flow_hw_create_ctrl_flow(dev, dev, tbl, items, 0, actions, 0, &flow_info, false))
16361 : 0 : return -rte_errno;
16362 : :
16363 : : return 0;
16364 : : }
16365 : :
16366 : : static int
16367 : 0 : __flow_hw_ctrl_flows_unicast(struct rte_eth_dev *dev,
16368 : : struct rte_flow_template_table *tbl,
16369 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
16370 : : {
16371 : : unsigned int i;
16372 : : int ret;
16373 : :
16374 [ # # ]: 0 : for (i = 0; i < MLX5_MAX_MAC_ADDRESSES; ++i) {
16375 [ # # ]: 0 : struct rte_ether_addr *mac = &dev->data->mac_addrs[i];
16376 : :
16377 [ # # ]: 0 : if (rte_is_zero_ether_addr(mac))
16378 : 0 : continue;
16379 : :
16380 : 0 : ret = __flow_hw_ctrl_flows_unicast_create(dev, tbl, rss_type, mac);
16381 [ # # ]: 0 : if (ret < 0)
16382 : 0 : return ret;
16383 : : }
16384 : : return 0;
16385 : : }
16386 : :
16387 : : static int
16388 : 0 : __flow_hw_ctrl_flows_unicast_vlan_create(struct rte_eth_dev *dev,
16389 : : struct rte_flow_template_table *tbl,
16390 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type,
16391 : : const struct rte_ether_addr *addr,
16392 : : const uint16_t vid)
16393 : : {
16394 : 0 : struct rte_flow_item_eth eth_spec = {
16395 : : .hdr.dst_addr = *addr,
16396 : : };
16397 : 0 : struct rte_flow_item_vlan vlan_spec = {
16398 [ # # ]: 0 : .tci = rte_cpu_to_be_16(vid),
16399 : : };
16400 : : struct rte_flow_item items[5];
16401 : 0 : struct rte_flow_action actions[] = {
16402 : : { .type = RTE_FLOW_ACTION_TYPE_RSS },
16403 : : { .type = RTE_FLOW_ACTION_TYPE_END },
16404 : : };
16405 [ # # # ]: 0 : struct mlx5_ctrl_flow_info flow_info = {
16406 : : .type = MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC_VLAN,
16407 : : .uc = {
16408 : : .dmac = *addr,
16409 : : .vlan = vid,
16410 : : },
16411 : : };
16412 : :
16413 : : memset(items, 0, sizeof(items));
16414 : 0 : items[0] = (struct rte_flow_item){
16415 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
16416 : : .spec = ð_spec,
16417 : : };
16418 [ # # # ]: 0 : items[1] = (struct rte_flow_item){
16419 : : .type = RTE_FLOW_ITEM_TYPE_VLAN,
16420 : : .spec = &vlan_spec,
16421 : : };
16422 [ # # # ]: 0 : items[2] = flow_hw_get_ctrl_rx_l3_item(rss_type);
16423 : 0 : items[3] = flow_hw_get_ctrl_rx_l4_item(rss_type);
16424 : 0 : items[4] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_END };
16425 : :
16426 [ # # ]: 0 : if (flow_hw_create_ctrl_flow(dev, dev, tbl, items, 0, actions, 0, &flow_info, false))
16427 : 0 : return -rte_errno;
16428 : :
16429 : : return 0;
16430 : : }
16431 : :
16432 : : static int
16433 : 0 : __flow_hw_ctrl_flows_unicast_vlan(struct rte_eth_dev *dev,
16434 : : struct rte_flow_template_table *tbl,
16435 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
16436 : : {
16437 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16438 : : unsigned int i;
16439 : : unsigned int j;
16440 : :
16441 [ # # ]: 0 : for (i = 0; i < MLX5_MAX_MAC_ADDRESSES; ++i) {
16442 [ # # ]: 0 : struct rte_ether_addr *mac = &dev->data->mac_addrs[i];
16443 : :
16444 [ # # ]: 0 : if (rte_is_zero_ether_addr(mac))
16445 : 0 : continue;
16446 : :
16447 [ # # ]: 0 : for (j = 0; j < priv->vlan_filter_n; ++j) {
16448 : 0 : uint16_t vlan = priv->vlan_filter[j];
16449 : : int ret;
16450 : :
16451 : 0 : ret = __flow_hw_ctrl_flows_unicast_vlan_create(dev, tbl, rss_type,
16452 : : mac, vlan);
16453 [ # # ]: 0 : if (ret < 0)
16454 : 0 : return ret;
16455 : : }
16456 : : }
16457 : : return 0;
16458 : : }
16459 : :
16460 : : static int
16461 : 0 : __flow_hw_ctrl_flows(struct rte_eth_dev *dev,
16462 : : struct rte_flow_template_table *tbl,
16463 : : const enum mlx5_flow_ctrl_rx_eth_pattern_type pattern_type,
16464 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
16465 : : {
16466 [ # # # # : 0 : switch (pattern_type) {
# ]
16467 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL:
16468 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL_MCAST:
16469 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST:
16470 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST:
16471 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST:
16472 : 0 : return __flow_hw_ctrl_flows_single(dev, tbl, pattern_type, rss_type);
16473 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST_VLAN:
16474 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST_VLAN:
16475 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST_VLAN:
16476 : 0 : return __flow_hw_ctrl_flows_single_vlan(dev, tbl, pattern_type, rss_type);
16477 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC:
16478 : 0 : return __flow_hw_ctrl_flows_unicast(dev, tbl, rss_type);
16479 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN:
16480 : 0 : return __flow_hw_ctrl_flows_unicast_vlan(dev, tbl, rss_type);
16481 : 0 : default:
16482 : : /* Should not reach here. */
16483 : : MLX5_ASSERT(false);
16484 : 0 : rte_errno = EINVAL;
16485 : 0 : return -EINVAL;
16486 : : }
16487 : : }
16488 : :
16489 : :
16490 : : int
16491 : 0 : mlx5_flow_hw_ctrl_flows(struct rte_eth_dev *dev, uint32_t flags)
16492 : : {
16493 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16494 : : struct mlx5_flow_hw_ctrl_rx *hw_ctrl_rx;
16495 : : unsigned int i;
16496 : : int j;
16497 : : int ret = 0;
16498 : :
16499 : : RTE_SET_USED(priv);
16500 : : RTE_SET_USED(flags);
16501 [ # # ]: 0 : if (!priv->dr_ctx) {
16502 : 0 : DRV_LOG(DEBUG, "port %u Control flow rules will not be created. "
16503 : : "HWS needs to be configured beforehand.",
16504 : : dev->data->port_id);
16505 : 0 : return 0;
16506 : : }
16507 [ # # ]: 0 : if (!priv->hw_ctrl_rx) {
16508 : 0 : DRV_LOG(ERR, "port %u Control flow rules templates were not created.",
16509 : : dev->data->port_id);
16510 : 0 : rte_errno = EINVAL;
16511 : 0 : return -rte_errno;
16512 : : }
16513 : : hw_ctrl_rx = priv->hw_ctrl_rx;
16514 [ # # ]: 0 : for (i = 0; i < MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_MAX; ++i) {
16515 : : const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type = i;
16516 : :
16517 [ # # ]: 0 : if (!eth_pattern_type_is_requested(eth_pattern_type, flags))
16518 : 0 : continue;
16519 [ # # ]: 0 : for (j = 0; j < MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX; ++j) {
16520 : 0 : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type = j;
16521 : : struct rte_flow_actions_template *at;
16522 : : struct mlx5_flow_hw_ctrl_rx_table *tmpls = &hw_ctrl_rx->tables[i][j];
16523 : 0 : const struct mlx5_flow_template_table_cfg cfg = {
16524 : : .attr = tmpls->attr,
16525 : : .external = 0,
16526 : : };
16527 : :
16528 [ # # ]: 0 : if (!hw_ctrl_rx->rss[rss_type]) {
16529 : 0 : at = flow_hw_create_ctrl_rx_rss_template(dev, rss_type);
16530 [ # # ]: 0 : if (!at)
16531 : 0 : return -rte_errno;
16532 : 0 : hw_ctrl_rx->rss[rss_type] = at;
16533 : : } else {
16534 : 0 : at = hw_ctrl_rx->rss[rss_type];
16535 : : }
16536 [ # # ]: 0 : if (!rss_type_is_requested(priv, rss_type))
16537 : 0 : continue;
16538 [ # # ]: 0 : if (!tmpls->tbl) {
16539 : 0 : tmpls->tbl = flow_hw_table_create(dev, &cfg,
16540 : : &tmpls->pt, 1, &at, 1, NULL);
16541 [ # # ]: 0 : if (!tmpls->tbl) {
16542 : 0 : DRV_LOG(ERR, "port %u Failed to create template table "
16543 : : "for control flow rules. Unable to create "
16544 : : "control flow rules.",
16545 : : dev->data->port_id);
16546 : 0 : return -rte_errno;
16547 : : }
16548 : : }
16549 : :
16550 : 0 : ret = __flow_hw_ctrl_flows(dev, tmpls->tbl, eth_pattern_type, rss_type);
16551 [ # # ]: 0 : if (ret) {
16552 : 0 : DRV_LOG(ERR, "port %u Failed to create control flow rule.",
16553 : : dev->data->port_id);
16554 : 0 : return ret;
16555 : : }
16556 : : }
16557 : : }
16558 : : return 0;
16559 : : }
16560 : :
16561 : : static int
16562 : 0 : mlx5_flow_hw_ctrl_flow_single(struct rte_eth_dev *dev,
16563 : : const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type,
16564 : : const struct rte_ether_addr *addr,
16565 : : const uint16_t vlan)
16566 : : {
16567 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16568 : : struct mlx5_flow_hw_ctrl_rx *hw_ctrl_rx;
16569 : : unsigned int j;
16570 : : int ret = 0;
16571 : :
16572 [ # # ]: 0 : if (!priv->dr_ctx) {
16573 : 0 : DRV_LOG(DEBUG, "port %u Control flow rules will not be created. "
16574 : : "HWS needs to be configured beforehand.",
16575 : : dev->data->port_id);
16576 : 0 : return 0;
16577 : : }
16578 [ # # ]: 0 : if (!priv->hw_ctrl_rx) {
16579 : 0 : DRV_LOG(ERR, "port %u Control flow rules templates were not created.",
16580 : : dev->data->port_id);
16581 : 0 : rte_errno = EINVAL;
16582 : 0 : return -rte_errno;
16583 : : }
16584 : : hw_ctrl_rx = priv->hw_ctrl_rx;
16585 : :
16586 : : /* TODO: this part should be somehow refactored. It's common with common flow creation. */
16587 [ # # ]: 0 : for (j = 0; j < MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX; ++j) {
16588 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type = j;
16589 : : const unsigned int pti = eth_pattern_type;
16590 : : struct rte_flow_actions_template *at;
16591 : : struct mlx5_flow_hw_ctrl_rx_table *tmpls = &hw_ctrl_rx->tables[pti][j];
16592 : 0 : const struct mlx5_flow_template_table_cfg cfg = {
16593 : : .attr = tmpls->attr,
16594 : : .external = 0,
16595 : : };
16596 : :
16597 [ # # ]: 0 : if (!hw_ctrl_rx->rss[rss_type]) {
16598 : 0 : at = flow_hw_create_ctrl_rx_rss_template(dev, rss_type);
16599 [ # # ]: 0 : if (!at)
16600 : 0 : return -rte_errno;
16601 : 0 : hw_ctrl_rx->rss[rss_type] = at;
16602 : : } else {
16603 : 0 : at = hw_ctrl_rx->rss[rss_type];
16604 : : }
16605 [ # # ]: 0 : if (!rss_type_is_requested(priv, rss_type))
16606 : 0 : continue;
16607 [ # # ]: 0 : if (!tmpls->tbl) {
16608 : 0 : tmpls->tbl = flow_hw_table_create(dev, &cfg,
16609 : : &tmpls->pt, 1, &at, 1, NULL);
16610 [ # # ]: 0 : if (!tmpls->tbl) {
16611 : 0 : DRV_LOG(ERR, "port %u Failed to create template table "
16612 : : "for control flow rules. Unable to create "
16613 : : "control flow rules.",
16614 : : dev->data->port_id);
16615 : 0 : return -rte_errno;
16616 : : }
16617 : : }
16618 : :
16619 : : MLX5_ASSERT(eth_pattern_type == MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC ||
16620 : : eth_pattern_type == MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN);
16621 : :
16622 [ # # ]: 0 : if (eth_pattern_type == MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC)
16623 : 0 : ret = __flow_hw_ctrl_flows_unicast_create(dev, tmpls->tbl, rss_type, addr);
16624 : : else
16625 : 0 : ret = __flow_hw_ctrl_flows_unicast_vlan_create(dev, tmpls->tbl, rss_type,
16626 : : addr, vlan);
16627 [ # # ]: 0 : if (ret) {
16628 : 0 : DRV_LOG(ERR, "port %u Failed to create unicast control flow rule.",
16629 : : dev->data->port_id);
16630 : 0 : return ret;
16631 : : }
16632 : : }
16633 : :
16634 : : return 0;
16635 : : }
16636 : :
16637 : : int
16638 : 0 : mlx5_flow_hw_ctrl_flow_dmac(struct rte_eth_dev *dev,
16639 : : const struct rte_ether_addr *addr)
16640 : : {
16641 : 0 : return mlx5_flow_hw_ctrl_flow_single(dev, MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC,
16642 : : addr, 0);
16643 : : }
16644 : :
16645 : :
16646 : : int
16647 : 0 : mlx5_flow_hw_ctrl_flow_dmac_destroy(struct rte_eth_dev *dev,
16648 : : const struct rte_ether_addr *addr)
16649 : : {
16650 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16651 : : struct mlx5_ctrl_flow_entry *entry;
16652 : : struct mlx5_ctrl_flow_entry *tmp;
16653 : : int ret;
16654 : :
16655 : : /*
16656 : : * HWS does not have automatic RSS flow expansion,
16657 : : * so each variant of the control flow rule is a separate entry in the list.
16658 : : * In that case, the whole list must be traversed.
16659 : : */
16660 : 0 : entry = LIST_FIRST(&priv->hw_ctrl_flows);
16661 [ # # ]: 0 : while (entry != NULL) {
16662 : 0 : tmp = LIST_NEXT(entry, next);
16663 : :
16664 [ # # # # ]: 0 : if (entry->info.type != MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC ||
16665 : : !rte_is_same_ether_addr(addr, &entry->info.uc.dmac)) {
16666 : : entry = tmp;
16667 : 0 : continue;
16668 : : }
16669 : :
16670 : 0 : ret = flow_hw_destroy_ctrl_flow(dev, entry->flow);
16671 [ # # ]: 0 : LIST_REMOVE(entry, next);
16672 : 0 : mlx5_free(entry);
16673 [ # # ]: 0 : if (ret)
16674 : 0 : return ret;
16675 : :
16676 : : entry = tmp;
16677 : : }
16678 : : return 0;
16679 : : }
16680 : :
16681 : : int
16682 : 0 : mlx5_flow_hw_ctrl_flow_dmac_vlan(struct rte_eth_dev *dev,
16683 : : const struct rte_ether_addr *addr,
16684 : : const uint16_t vlan)
16685 : : {
16686 : 0 : return mlx5_flow_hw_ctrl_flow_single(dev, MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN,
16687 : : addr, vlan);
16688 : : }
16689 : :
16690 : : int
16691 : 0 : mlx5_flow_hw_ctrl_flow_dmac_vlan_destroy(struct rte_eth_dev *dev,
16692 : : const struct rte_ether_addr *addr,
16693 : : const uint16_t vlan)
16694 : : {
16695 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16696 : : struct mlx5_ctrl_flow_entry *entry;
16697 : : struct mlx5_ctrl_flow_entry *tmp;
16698 : : int ret;
16699 : :
16700 : : /*
16701 : : * HWS does not have automatic RSS flow expansion,
16702 : : * so each variant of the control flow rule is a separate entry in the list.
16703 : : * In that case, the whole list must be traversed.
16704 : : */
16705 : 0 : entry = LIST_FIRST(&priv->hw_ctrl_flows);
16706 [ # # ]: 0 : while (entry != NULL) {
16707 : 0 : tmp = LIST_NEXT(entry, next);
16708 : :
16709 [ # # # # ]: 0 : if (entry->info.type != MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC_VLAN ||
16710 : 0 : !rte_is_same_ether_addr(addr, &entry->info.uc.dmac) ||
16711 [ # # ]: 0 : vlan != entry->info.uc.vlan) {
16712 : : entry = tmp;
16713 : 0 : continue;
16714 : : }
16715 : :
16716 : 0 : ret = flow_hw_destroy_ctrl_flow(dev, entry->flow);
16717 [ # # ]: 0 : LIST_REMOVE(entry, next);
16718 : 0 : mlx5_free(entry);
16719 [ # # ]: 0 : if (ret)
16720 : 0 : return ret;
16721 : :
16722 : : entry = tmp;
16723 : : }
16724 : : return 0;
16725 : : }
16726 : :
16727 : : struct mlx5_ecpri_parser_profile *
16728 : 0 : flow_hw_get_ecpri_parser_profile(void *dr_ctx)
16729 : : {
16730 : : uint16_t port_id;
16731 : : bool found = false;
16732 : : struct mlx5_priv *priv;
16733 : :
16734 [ # # ]: 0 : MLX5_ETH_FOREACH_DEV(port_id, NULL) {
16735 : 0 : priv = rte_eth_devices[port_id].data->dev_private;
16736 [ # # ]: 0 : if (priv->dr_ctx == dr_ctx) {
16737 : : found = true;
16738 : : break;
16739 : : }
16740 : : }
16741 [ # # ]: 0 : if (found)
16742 : 0 : return &priv->sh->ecpri_parser;
16743 : 0 : rte_errno = ENODEV;
16744 : 0 : return NULL;
16745 : : }
16746 : :
16747 : :
16748 : : static __rte_always_inline uint32_t
16749 : : mlx5_reformat_domain_to_tbl_type(const struct rte_flow_indir_action_conf *domain,
16750 : : bool fdb_unified_en)
16751 : : {
16752 : : uint32_t tbl_type;
16753 : :
16754 [ # # ]: 0 : if (domain->transfer)
16755 : : tbl_type = (fdb_unified_en ?
16756 : : (MLX5DR_ACTION_FLAG_HWS_FDB_RX |
16757 : : MLX5DR_ACTION_FLAG_HWS_FDB_TX |
16758 [ # # ]: 0 : MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED) :
16759 : : MLX5DR_ACTION_FLAG_HWS_FDB);
16760 [ # # ]: 0 : else if (domain->egress)
16761 : : tbl_type = MLX5DR_ACTION_FLAG_HWS_TX;
16762 [ # # ]: 0 : else if (domain->ingress)
16763 : : tbl_type = MLX5DR_ACTION_FLAG_HWS_RX;
16764 : : else
16765 : : tbl_type = UINT32_MAX;
16766 : : return tbl_type;
16767 : : }
16768 : :
16769 : : static struct mlx5_hw_encap_decap_action *
16770 : 0 : __mlx5_reformat_create(struct rte_eth_dev *dev,
16771 : : const struct rte_flow_action_raw_encap *encap_conf,
16772 : : const struct rte_flow_indir_action_conf *domain,
16773 : : enum mlx5dr_action_type type)
16774 : : {
16775 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
16776 : : struct mlx5_hw_encap_decap_action *handle;
16777 : : struct mlx5dr_action_reformat_header hdr;
16778 : : uint32_t flags;
16779 : : bool unified_fdb = is_unified_fdb(priv);
16780 : :
16781 : : flags = mlx5_reformat_domain_to_tbl_type(domain, unified_fdb);
16782 : 0 : flags |= (uint32_t)MLX5DR_ACTION_FLAG_SHARED;
16783 [ # # ]: 0 : if (flags == UINT32_MAX) {
16784 : 0 : DRV_LOG(ERR, "Reformat: invalid indirect action configuration");
16785 : 0 : return NULL;
16786 : : }
16787 : : /* Allocate new list entry. */
16788 : 0 : handle = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*handle), 0, SOCKET_ID_ANY);
16789 [ # # ]: 0 : if (!handle) {
16790 : 0 : DRV_LOG(ERR, "Reformat: failed to allocate reformat entry");
16791 : 0 : return NULL;
16792 : : }
16793 : 0 : handle->action_type = type;
16794 [ # # ]: 0 : hdr.sz = encap_conf ? encap_conf->size : 0;
16795 [ # # ]: 0 : hdr.data = encap_conf ? encap_conf->data : NULL;
16796 : 0 : handle->action = mlx5dr_action_create_reformat(priv->dr_ctx,
16797 : : type, 1, &hdr, 0, flags);
16798 [ # # ]: 0 : if (!handle->action) {
16799 : 0 : DRV_LOG(ERR, "Reformat: failed to create reformat action");
16800 : 0 : mlx5_free(handle);
16801 : 0 : return NULL;
16802 : : }
16803 : : return handle;
16804 : : }
16805 : :
16806 : : /**
16807 : : * Create mlx5 reformat action.
16808 : : *
16809 : : * @param[in] dev
16810 : : * Pointer to rte_eth_dev structure.
16811 : : * @param[in] conf
16812 : : * Pointer to the indirect action parameters.
16813 : : * @param[in] encap_action
16814 : : * Pointer to the raw_encap action configuration.
16815 : : * @param[in] decap_action
16816 : : * Pointer to the raw_decap action configuration.
16817 : : * @param[out] error
16818 : : * Pointer to error structure.
16819 : : *
16820 : : * @return
16821 : : * A valid shared action handle in case of success, NULL otherwise and
16822 : : * rte_errno is set.
16823 : : */
16824 : : struct mlx5_hw_encap_decap_action*
16825 : 0 : mlx5_reformat_action_create(struct rte_eth_dev *dev,
16826 : : const struct rte_flow_indir_action_conf *conf,
16827 : : const struct rte_flow_action *encap_action,
16828 : : const struct rte_flow_action *decap_action,
16829 : : struct rte_flow_error *error)
16830 : : {
16831 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16832 : : struct mlx5_hw_encap_decap_action *handle;
16833 : : const struct rte_flow_action_raw_encap *encap = NULL;
16834 : : const struct rte_flow_action_raw_decap *decap = NULL;
16835 : : enum mlx5dr_action_type type = MLX5DR_ACTION_TYP_LAST;
16836 : :
16837 : : MLX5_ASSERT(!encap_action || encap_action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP);
16838 : : MLX5_ASSERT(!decap_action || decap_action->type == RTE_FLOW_ACTION_TYPE_RAW_DECAP);
16839 [ # # ]: 0 : if (priv->sh->config.dv_flow_en != 2) {
16840 : 0 : rte_flow_error_set(error, ENOTSUP,
16841 : : RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
16842 : : "Reformat: hardware does not support");
16843 : 0 : return NULL;
16844 : : }
16845 [ # # # # ]: 0 : if (!conf || (conf->transfer + conf->egress + conf->ingress != 1)) {
16846 : 0 : rte_flow_error_set(error, EINVAL,
16847 : : RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
16848 : : "Reformat: domain should be specified");
16849 : 0 : return NULL;
16850 : : }
16851 [ # # # # : 0 : if ((encap_action && !encap_action->conf) || (decap_action && !decap_action->conf)) {
# # # # ]
16852 : 0 : rte_flow_error_set(error, EINVAL,
16853 : : RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
16854 : : "Reformat: missed action configuration");
16855 : 0 : return NULL;
16856 : : }
16857 [ # # ]: 0 : if (encap_action && !decap_action) {
16858 : 0 : encap = (const struct rte_flow_action_raw_encap *)encap_action->conf;
16859 [ # # ]: 0 : if (!encap->size || encap->size > MLX5_ENCAP_MAX_LEN ||
16860 : : encap->size < MLX5_ENCAPSULATION_DECISION_SIZE) {
16861 : 0 : rte_flow_error_set(error, EINVAL,
16862 : : RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
16863 : : "Reformat: Invalid encap length");
16864 : 0 : return NULL;
16865 : : }
16866 : : type = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;
16867 [ # # ]: 0 : } else if (decap_action && !encap_action) {
16868 : 0 : decap = (const struct rte_flow_action_raw_decap *)decap_action->conf;
16869 [ # # ]: 0 : if (!decap->size || decap->size < MLX5_ENCAPSULATION_DECISION_SIZE) {
16870 : 0 : rte_flow_error_set(error, EINVAL,
16871 : : RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
16872 : : "Reformat: Invalid decap length");
16873 : 0 : return NULL;
16874 : : }
16875 : : type = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2;
16876 [ # # ]: 0 : } else if (encap_action && decap_action) {
16877 : 0 : decap = (const struct rte_flow_action_raw_decap *)decap_action->conf;
16878 : 0 : encap = (const struct rte_flow_action_raw_encap *)encap_action->conf;
16879 [ # # ]: 0 : if (decap->size < MLX5_ENCAPSULATION_DECISION_SIZE &&
16880 [ # # # # ]: 0 : encap->size >= MLX5_ENCAPSULATION_DECISION_SIZE &&
16881 : : encap->size <= MLX5_ENCAP_MAX_LEN) {
16882 : : type = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3;
16883 [ # # ]: 0 : } else if (decap->size >= MLX5_ENCAPSULATION_DECISION_SIZE &&
16884 [ # # ]: 0 : encap->size < MLX5_ENCAPSULATION_DECISION_SIZE) {
16885 : : type = MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2;
16886 : : } else {
16887 : 0 : rte_flow_error_set(error, EINVAL,
16888 : : RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
16889 : : "Reformat: Invalid decap & encap length");
16890 : 0 : return NULL;
16891 : : }
16892 [ # # ]: 0 : } else if (!encap_action && !decap_action) {
16893 : 0 : rte_flow_error_set(error, EINVAL,
16894 : : RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
16895 : : "Reformat: Invalid decap & encap configurations");
16896 : 0 : return NULL;
16897 : : }
16898 [ # # ]: 0 : if (!priv->dr_ctx) {
16899 : 0 : rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
16900 : : encap_action, "Reformat: HWS not supported");
16901 : 0 : return NULL;
16902 : : }
16903 : 0 : handle = __mlx5_reformat_create(dev, encap, conf, type);
16904 [ # # ]: 0 : if (!handle) {
16905 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
16906 : : "Reformat: failed to create indirect action");
16907 : 0 : return NULL;
16908 : : }
16909 : : return handle;
16910 : : }
16911 : :
16912 : : /**
16913 : : * Destroy the indirect reformat action.
16914 : : * Release action related resources on the NIC and the memory.
16915 : : * Lock free, (mutex should be acquired by caller).
16916 : : *
16917 : : * @param[in] dev
16918 : : * Pointer to the Ethernet device structure.
16919 : : * @param[in] handle
16920 : : * The indirect action list handle to be removed.
16921 : : * @param[out] error
16922 : : * Perform verbose error reporting if not NULL. Initialized in case of
16923 : : * error only.
16924 : : *
16925 : : * @return
16926 : : * 0 on success, otherwise negative errno value.
16927 : : */
16928 : : int
16929 : 0 : mlx5_reformat_action_destroy(struct rte_eth_dev *dev,
16930 : : struct rte_flow_action_list_handle *handle,
16931 : : struct rte_flow_error *error)
16932 : : {
16933 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16934 : : struct mlx5_hw_encap_decap_action *action;
16935 : :
16936 : : action = (struct mlx5_hw_encap_decap_action *)handle;
16937 [ # # # # ]: 0 : if (!priv->dr_ctx || !action)
16938 : 0 : return rte_flow_error_set(error, ENOTSUP,
16939 : : RTE_FLOW_ERROR_TYPE_ACTION, handle,
16940 : : "Reformat: invalid action handle");
16941 : 0 : mlx5dr_action_destroy(action->action);
16942 : 0 : mlx5_free(handle);
16943 : 0 : return 0;
16944 : : }
16945 : :
16946 : : static bool
16947 : 0 : flow_hw_is_item_masked(const struct rte_flow_item *item)
16948 : : {
16949 : : const uint8_t *byte;
16950 : : int size;
16951 : : int i;
16952 : :
16953 [ # # ]: 0 : if (item->mask == NULL)
16954 : : return false;
16955 : :
16956 [ # # ]: 0 : switch ((int)item->type) {
16957 : : case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
16958 : : size = sizeof(struct rte_flow_item_tag);
16959 : : break;
16960 : : case MLX5_RTE_FLOW_ITEM_TYPE_SQ:
16961 : : size = sizeof(struct mlx5_rte_flow_item_sq);
16962 : : break;
16963 : 0 : default:
16964 : 0 : size = rte_flow_conv(RTE_FLOW_CONV_OP_ITEM_MASK, NULL, 0, item, NULL);
16965 : : /*
16966 : : * Pattern template items are passed to this function.
16967 : : * These items were already validated, so error is not expected.
16968 : : * Also, if mask is NULL, then spec size is bigger than 0 always.
16969 : : */
16970 : : MLX5_ASSERT(size > 0);
16971 : : }
16972 : :
16973 : 0 : byte = (const uint8_t *)item->mask;
16974 [ # # ]: 0 : for (i = 0; i < size; ++i)
16975 [ # # ]: 0 : if (byte[i])
16976 : : return true;
16977 : :
16978 : : return false;
16979 : : }
16980 : :
16981 : : static int
16982 : 0 : flow_hw_validate_rule_pattern(struct rte_eth_dev *dev,
16983 : : const struct rte_flow_template_table *table,
16984 : : const uint8_t pattern_template_idx,
16985 : : const struct rte_flow_item items[],
16986 : : struct rte_flow_error *error)
16987 : : {
16988 : : const struct rte_flow_pattern_template *pt;
16989 : : const struct rte_flow_item *pt_item;
16990 : :
16991 [ # # ]: 0 : if (pattern_template_idx >= table->nb_item_templates)
16992 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
16993 : : "Pattern template index out of range");
16994 : :
16995 : 0 : pt = table->its[pattern_template_idx];
16996 : 0 : pt_item = pt->items;
16997 : :
16998 : : /* If any item was prepended, skip it. */
16999 [ # # ]: 0 : if (pt->implicit_port || pt->implicit_tag)
17000 : 0 : pt_item++;
17001 : :
17002 [ # # ]: 0 : for (; pt_item->type != RTE_FLOW_ITEM_TYPE_END; pt_item++, items++) {
17003 [ # # ]: 0 : if (pt_item->type != items->type)
17004 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM,
17005 : : items, "Item type does not match the template");
17006 : :
17007 : : /*
17008 : : * Assumptions:
17009 : : * - Currently mlx5dr layer contains info on which fields in masks are supported.
17010 : : * - This info is not exposed to PMD directly.
17011 : : * - Because of that, it is assumed that since pattern template is correct,
17012 : : * then, items' masks in pattern template have nonzero values only in
17013 : : * supported fields.
17014 : : * This is known, because a temporary mlx5dr matcher is created during pattern
17015 : : * template creation to validate the template.
17016 : : * - As a result, it is safe to look for nonzero bytes in mask to determine if
17017 : : * item spec is needed in a flow rule.
17018 : : */
17019 [ # # ]: 0 : if (!flow_hw_is_item_masked(pt_item))
17020 : 0 : continue;
17021 : :
17022 [ # # ]: 0 : if (items->spec == NULL)
17023 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
17024 : : items, "Item spec is required");
17025 : :
17026 [ # # # # ]: 0 : switch (items->type) {
17027 : : const struct rte_flow_item_ethdev *ethdev;
17028 : : const struct rte_flow_item_tx_queue *tx_queue;
17029 : : const struct rte_flow_item_conntrack *spec;
17030 : : struct mlx5_txq_ctrl *txq;
17031 : :
17032 : 0 : case RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT:
17033 : : ethdev = items->spec;
17034 [ # # ]: 0 : if (flow_hw_validate_target_port_id(dev, ethdev->port_id)) {
17035 : 0 : return rte_flow_error_set(error, EINVAL,
17036 : : RTE_FLOW_ERROR_TYPE_ITEM_SPEC, items,
17037 : : "Invalid port");
17038 : : }
17039 : : break;
17040 : 0 : case RTE_FLOW_ITEM_TYPE_TX_QUEUE:
17041 : : tx_queue = items->spec;
17042 [ # # # # ]: 0 : if (mlx5_is_external_txq(dev, tx_queue->tx_queue))
17043 : 0 : continue;
17044 : 0 : txq = mlx5_txq_get(dev, tx_queue->tx_queue);
17045 [ # # ]: 0 : if (!txq)
17046 : 0 : return rte_flow_error_set(error, EINVAL,
17047 : : RTE_FLOW_ERROR_TYPE_ITEM_SPEC, items,
17048 : : "Invalid Tx queue");
17049 : 0 : mlx5_txq_release(dev, tx_queue->tx_queue);
17050 : 0 : break;
17051 : 0 : case RTE_FLOW_ITEM_TYPE_CONNTRACK:
17052 : : spec = items->spec;
17053 [ # # ]: 0 : if (spec->flags & ~MLX5_FLOW_CONNTRACK_PKT_STATE_ALL)
17054 : 0 : return rte_flow_error_set(error, EINVAL,
17055 : : RTE_FLOW_ERROR_TYPE_ITEM,
17056 : : NULL,
17057 : : "Invalid CT item flags");
17058 : : break;
17059 : : default:
17060 : : break;
17061 : : }
17062 : : }
17063 : :
17064 : : return 0;
17065 : : }
17066 : :
17067 : : static bool
17068 : 0 : flow_hw_valid_indirect_action_type(const struct rte_flow_action *user_action,
17069 : : const enum rte_flow_action_type expected_type)
17070 : : {
17071 : 0 : uint32_t user_indirect_type = MLX5_INDIRECT_ACTION_TYPE_GET(user_action->conf);
17072 : : uint32_t expected_indirect_type;
17073 : :
17074 [ # # # # : 0 : switch ((int)expected_type) {
# # # ]
17075 : : case RTE_FLOW_ACTION_TYPE_RSS:
17076 : : case MLX5_RTE_FLOW_ACTION_TYPE_RSS:
17077 : : expected_indirect_type = MLX5_INDIRECT_ACTION_TYPE_RSS;
17078 : : break;
17079 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
17080 : : case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
17081 : : expected_indirect_type = MLX5_INDIRECT_ACTION_TYPE_COUNT;
17082 : 0 : break;
17083 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
17084 : : expected_indirect_type = MLX5_INDIRECT_ACTION_TYPE_AGE;
17085 : 0 : break;
17086 : 0 : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
17087 : : expected_indirect_type = MLX5_INDIRECT_ACTION_TYPE_CT;
17088 : 0 : break;
17089 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
17090 : : case MLX5_RTE_FLOW_ACTION_TYPE_METER_MARK:
17091 : : expected_indirect_type = MLX5_INDIRECT_ACTION_TYPE_METER_MARK;
17092 : 0 : break;
17093 : 0 : case RTE_FLOW_ACTION_TYPE_QUOTA:
17094 : : expected_indirect_type = MLX5_INDIRECT_ACTION_TYPE_QUOTA;
17095 : 0 : break;
17096 : : default:
17097 : : return false;
17098 : : }
17099 : :
17100 : 0 : return user_indirect_type == expected_indirect_type;
17101 : : }
17102 : :
17103 : : static int
17104 : 0 : flow_hw_validate_rule_actions(struct rte_eth_dev *dev,
17105 : : const struct rte_flow_template_table *table,
17106 : : const uint8_t actions_template_idx,
17107 : : const struct rte_flow_action actions[],
17108 : : struct rte_flow_error *error)
17109 : : {
17110 : : const struct rte_flow_actions_template *at;
17111 : : const struct mlx5_hw_actions *hw_acts;
17112 : : const struct mlx5_action_construct_data *act_data;
17113 : : unsigned int idx;
17114 : :
17115 [ # # ]: 0 : if (actions_template_idx >= table->nb_action_templates)
17116 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17117 : : "Actions template index out of range");
17118 : :
17119 : 0 : at = table->ats[actions_template_idx].action_template;
17120 : : hw_acts = &table->ats[actions_template_idx].acts;
17121 : :
17122 [ # # ]: 0 : for (idx = 0; actions[idx].type != RTE_FLOW_ACTION_TYPE_END; ++idx) {
17123 : : const struct rte_flow_action *user_action = &actions[idx];
17124 : 0 : const struct rte_flow_action *tmpl_action = &at->orig_actions[idx];
17125 : :
17126 [ # # ]: 0 : if (user_action->type != tmpl_action->type)
17127 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
17128 : : user_action,
17129 : : "Action type does not match type specified in "
17130 : : "actions template");
17131 : : }
17132 : :
17133 : : /*
17134 : : * Only go through unmasked actions and check if configuration is provided.
17135 : : * Configuration of masked actions is ignored.
17136 : : */
17137 [ # # ]: 0 : LIST_FOREACH(act_data, &hw_acts->act_list, next) {
17138 : : const struct rte_flow_action *user_action;
17139 : :
17140 : 0 : user_action = &actions[act_data->action_src];
17141 : :
17142 : : /* Skip actions which do not require conf. */
17143 [ # # ]: 0 : switch ((int)act_data->type) {
17144 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
17145 : : case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
17146 : : case MLX5_RTE_FLOW_ACTION_TYPE_METER_MARK:
17147 : : case MLX5_RTE_FLOW_ACTION_TYPE_RSS:
17148 : 0 : continue;
17149 : : default:
17150 : : break;
17151 : : }
17152 : :
17153 [ # # ]: 0 : if (user_action->conf == NULL)
17154 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
17155 : : user_action,
17156 : : "Action requires configuration");
17157 : :
17158 [ # # # # : 0 : switch ((int)user_action->type) {
# # ]
17159 : : enum rte_flow_action_type expected_type;
17160 : : const struct rte_flow_action_ethdev *ethdev;
17161 : : const struct rte_flow_action_modify_field *mf;
17162 : :
17163 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT:
17164 : 0 : expected_type = act_data->indirect.expected_type;
17165 [ # # ]: 0 : if (!flow_hw_valid_indirect_action_type(user_action, expected_type))
17166 : 0 : return rte_flow_error_set(error, EINVAL,
17167 : : RTE_FLOW_ERROR_TYPE_ACTION_CONF,
17168 : : user_action,
17169 : : "Indirect action type does not match "
17170 : : "the type specified in the mask");
17171 : : break;
17172 : 0 : case RTE_FLOW_ACTION_TYPE_QUEUE:
17173 [ # # ]: 0 : if (mlx5_flow_validate_target_queue(dev, user_action, error))
17174 : 0 : return -rte_errno;
17175 : : break;
17176 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
17177 [ # # ]: 0 : if (mlx5_validate_action_rss(dev, user_action, error))
17178 : 0 : return -rte_errno;
17179 : : break;
17180 : 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
17181 : : /* TODO: Compare other fields if needed. */
17182 : : mf = user_action->conf;
17183 [ # # ]: 0 : if (mf->operation != act_data->modify_header.action.operation ||
17184 [ # # ]: 0 : mf->src.field != act_data->modify_header.action.src.field ||
17185 [ # # ]: 0 : mf->dst.field != act_data->modify_header.action.dst.field ||
17186 [ # # ]: 0 : mf->width != act_data->modify_header.action.width)
17187 : 0 : return rte_flow_error_set(error, EINVAL,
17188 : : RTE_FLOW_ERROR_TYPE_ACTION_CONF,
17189 : : user_action,
17190 : : "Modify field configuration does not "
17191 : : "match configuration from actions "
17192 : : "template");
17193 : : break;
17194 : 0 : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
17195 : : ethdev = user_action->conf;
17196 [ # # ]: 0 : if (flow_hw_validate_target_port_id(dev, ethdev->port_id)) {
17197 : 0 : return rte_flow_error_set(error, EINVAL,
17198 : : RTE_FLOW_ERROR_TYPE_ACTION_CONF,
17199 : : user_action, "Invalid port");
17200 : : }
17201 : : break;
17202 : : default:
17203 : : break;
17204 : : }
17205 : : }
17206 : :
17207 : : return 0;
17208 : : }
17209 : :
17210 : : static int
17211 : 0 : flow_hw_async_op_validate(struct rte_eth_dev *dev,
17212 : : const uint32_t queue,
17213 : : const struct rte_flow_template_table *table,
17214 : : struct rte_flow_error *error)
17215 : : {
17216 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
17217 : :
17218 : : MLX5_ASSERT(table != NULL);
17219 : :
17220 [ # # # # ]: 0 : if (table->cfg.external && queue >= priv->hw_attr->nb_queue)
17221 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17222 : : "Incorrect queue");
17223 : :
17224 : : return 0;
17225 : : }
17226 : :
17227 : : /**
17228 : : * Validate user input for rte_flow_async_create() implementation.
17229 : : *
17230 : : * If RTE_LIBRTE_MLX5_DEBUG macro is not defined, this function is a no-op.
17231 : : *
17232 : : * @param[in] dev
17233 : : * Pointer to the rte_eth_dev structure.
17234 : : * @param[in] queue
17235 : : * The queue to create the flow.
17236 : : * @param[in] table
17237 : : * Pointer to template table.
17238 : : * @param[in] rule_index
17239 : : * The item pattern flow follows from the table.
17240 : : * @param[in] items
17241 : : * Items with flow spec value.
17242 : : * @param[in] pattern_template_index
17243 : : * The item pattern flow follows from the table.
17244 : : * @param[in] actions
17245 : : * Action with flow spec value.
17246 : : * @param[in] action_template_index
17247 : : * The action pattern flow follows from the table.
17248 : : * @param[out] error
17249 : : * Pointer to error structure.
17250 : : *
17251 : : * @return
17252 : : * 0 if user input is valid.
17253 : : * Negative errno otherwise, rte_errno and error struct is populated.
17254 : : */
17255 : : static int
17256 : 0 : flow_hw_async_create_validate(struct rte_eth_dev *dev,
17257 : : const uint32_t queue,
17258 : : const struct rte_flow_template_table *table,
17259 : : enum rte_flow_table_insertion_type insertion_type,
17260 : : uint32_t rule_index,
17261 : : const struct rte_flow_item items[],
17262 : : const uint8_t pattern_template_index,
17263 : : const struct rte_flow_action actions[],
17264 : : const uint8_t action_template_index,
17265 : : struct rte_flow_error *error)
17266 : : {
17267 [ # # ]: 0 : if (flow_hw_async_op_validate(dev, queue, table, error))
17268 : 0 : return -rte_errno;
17269 : :
17270 [ # # ]: 0 : if (insertion_type != table->cfg.attr.insertion_type)
17271 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
17272 : : NULL, "Flow rule insertion type mismatch with table configuration");
17273 : :
17274 [ # # ]: 0 : if (table->cfg.attr.insertion_type != RTE_FLOW_TABLE_INSERTION_TYPE_PATTERN)
17275 [ # # ]: 0 : if (rule_index >= table->cfg.attr.nb_flows)
17276 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
17277 : : NULL, "Flow rule index exceeds table size");
17278 : :
17279 [ # # ]: 0 : if (table->cfg.attr.insertion_type != RTE_FLOW_TABLE_INSERTION_TYPE_INDEX)
17280 [ # # ]: 0 : if (flow_hw_validate_rule_pattern(dev, table, pattern_template_index, items, error))
17281 : 0 : return -rte_errno;
17282 : :
17283 [ # # ]: 0 : if (flow_hw_validate_rule_actions(dev, table, action_template_index, actions, error))
17284 : 0 : return -rte_errno;
17285 : :
17286 : : return 0;
17287 : : }
17288 : :
17289 : : /**
17290 : : * Validate user input for rte_flow_async_update() implementation.
17291 : : *
17292 : : * If RTE_LIBRTE_MLX5_DEBUG macro is not defined, this function is a no-op.
17293 : : *
17294 : : * @param[in] dev
17295 : : * Pointer to the rte_eth_dev structure.
17296 : : * @param[in] queue
17297 : : * The queue to create the flow.
17298 : : * @param[in] flow
17299 : : * Flow rule to be updated.
17300 : : * @param[in] actions
17301 : : * Action with flow spec value.
17302 : : * @param[in] action_template_index
17303 : : * The action pattern flow follows from the table.
17304 : : * @param[out] error
17305 : : * Pointer to error structure.
17306 : : *
17307 : : * @return
17308 : : * 0 if user input is valid.
17309 : : * Negative errno otherwise, rte_errno and error struct is set.
17310 : : */
17311 : : static int
17312 : 0 : flow_hw_async_update_validate(struct rte_eth_dev *dev,
17313 : : const uint32_t queue,
17314 : : const struct rte_flow_hw *flow,
17315 : : const struct rte_flow_action actions[],
17316 : : const uint8_t action_template_index,
17317 : : struct rte_flow_error *error)
17318 : : {
17319 [ # # ]: 0 : if (flow_hw_async_op_validate(dev, queue, flow->table, error))
17320 : 0 : return -rte_errno;
17321 : :
17322 [ # # ]: 0 : if (flow_hw_validate_rule_actions(dev, flow->table, action_template_index, actions, error))
17323 : 0 : return -rte_errno;
17324 : :
17325 : : return 0;
17326 : : }
17327 : :
17328 : : /**
17329 : : * Validate user input for rte_flow_async_destroy() implementation.
17330 : : *
17331 : : * If RTE_LIBRTE_MLX5_DEBUG macro is not defined, this function is a no-op.
17332 : : *
17333 : : * @param[in] dev
17334 : : * Pointer to the rte_eth_dev structure.
17335 : : * @param[in] queue
17336 : : * The queue to create the flow.
17337 : : * @param[in] flow
17338 : : * Flow rule to be destroyed.
17339 : : * @param[out] error
17340 : : * Pointer to error structure.
17341 : : *
17342 : : * @return
17343 : : * 0 if user input is valid.
17344 : : * Negative errno otherwise, rte_errno and error struct is set.
17345 : : */
17346 : : static int
17347 : : flow_hw_async_destroy_validate(struct rte_eth_dev *dev,
17348 : : const uint32_t queue,
17349 : : const struct rte_flow_hw *flow,
17350 : : struct rte_flow_error *error)
17351 : : {
17352 : : if (flow_hw_async_op_validate(dev, queue, flow->table, error))
17353 : : return -rte_errno;
17354 : :
17355 : : return 0;
17356 : : }
17357 : :
17358 : : static struct rte_flow_fp_ops mlx5_flow_hw_fp_ops = {
17359 : : .async_create = flow_hw_async_flow_create,
17360 : : .async_create_by_index = flow_hw_async_flow_create_by_index,
17361 : : .async_create_by_index_with_pattern = flow_hw_async_flow_create_by_index_with_pattern,
17362 : : .async_actions_update = flow_hw_async_flow_update,
17363 : : .async_destroy = flow_hw_async_flow_destroy,
17364 : : .push = flow_hw_push,
17365 : : .pull = flow_hw_pull,
17366 : : .async_action_handle_create = flow_hw_action_handle_create,
17367 : : .async_action_handle_destroy = flow_hw_action_handle_destroy,
17368 : : .async_action_handle_update = flow_hw_action_handle_update,
17369 : : .async_action_handle_query = flow_hw_action_handle_query,
17370 : : .async_action_handle_query_update = flow_hw_async_action_handle_query_update,
17371 : : .async_action_list_handle_create = flow_hw_async_action_list_handle_create,
17372 : : .async_action_list_handle_destroy = flow_hw_async_action_list_handle_destroy,
17373 : : .async_action_list_handle_query_update =
17374 : : flow_hw_async_action_list_handle_query_update,
17375 : : };
17376 : :
17377 : : #endif
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