Branch data Line data Source code
1 : : /* SPDX-License-Identifier: BSD-3-Clause
2 : : * Copyright(c) 2024 Realtek Corporation. All rights reserved
3 : : */
4 : :
5 : : #include "../r8169_ethdev.h"
6 : : #include "../r8169_hw.h"
7 : : #include "../r8169_phy.h"
8 : : #include "rtl8126a_mcu.h"
9 : :
10 : : /* For RTL8126A, CFG_METHOD_69,70,71 */
11 : :
12 : : static void
13 : 0 : hw_init_rxcfg_8126a(struct rtl_hw *hw)
14 : : {
15 [ # # # ]: 0 : switch (hw->mcfg) {
16 : 0 : case CFG_METHOD_69:
17 : 0 : RTL_W32(hw, RxConfig, Rx_Fetch_Number_8 | RxCfg_pause_slot_en |
18 : : (RX_DMA_BURST_512 << RxCfgDMAShift));
19 : : break;
20 : 0 : case CFG_METHOD_70:
21 : : case CFG_METHOD_71:
22 : 0 : RTL_W32(hw, RxConfig, Rx_Fetch_Number_8 | Rx_Close_Multiple |
23 : : RxCfg_pause_slot_en | (RX_DMA_BURST_512 << RxCfgDMAShift));
24 : : break;
25 : : }
26 : 0 : }
27 : :
28 : : static void
29 : 0 : hw_ephy_config_8126a(struct rtl_hw *hw)
30 : : {
31 : : switch (hw->mcfg) {
32 : : case CFG_METHOD_69:
33 : : case CFG_METHOD_70:
34 : : case CFG_METHOD_71:
35 : : /* nothing to do */
36 : : break;
37 : : }
38 : 0 : }
39 : :
40 : : static void
41 : : rtl_hw_phy_config_8126a_1(struct rtl_hw *hw)
42 : : {
43 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA442, BIT_11);
44 : 0 : }
45 : :
46 : : static void
47 : 0 : rtl_hw_phy_config_8126a_2(struct rtl_hw *hw)
48 : : {
49 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA442, BIT_11);
50 : :
51 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80BF);
52 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xED00);
53 : :
54 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80CD);
55 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x1000);
56 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80D1);
57 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xC800);
58 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80D4);
59 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xC800);
60 : :
61 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80E1);
62 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x10CC);
63 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80E5);
64 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x4F0C);
65 : :
66 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8387);
67 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x4700);
68 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA80C, (BIT_7 | BIT_6), BIT_7);
69 : :
70 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xAC90, BIT_4);
71 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xAD2C, BIT_15);
72 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8321);
73 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x1100);
74 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xACF8, (BIT_3 | BIT_2));
75 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8183);
76 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x5900);
77 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xAD94, BIT_5);
78 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA654, BIT_11);
79 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xB648, BIT_14);
80 : :
81 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x839E);
82 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x2F00);
83 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x83F2);
84 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0800);
85 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xADA0, BIT_1);
86 : :
87 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x80F3);
88 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x9900);
89 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8126);
90 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0xC100);
91 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x893A);
92 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x8080);
93 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8647);
94 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0xE600);
95 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x862C);
96 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x1200);
97 : :
98 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x864A);
99 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0xE600);
100 : :
101 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x80A0);
102 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0xBCBC);
103 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x805E);
104 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0xBCBC);
105 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8056);
106 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x3077);
107 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8058);
108 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x5A00);
109 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8098);
110 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x3077);
111 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x809A);
112 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x5A00);
113 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8052);
114 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x3733);
115 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8094);
116 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x3733);
117 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x807F);
118 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x7C75);
119 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x803D);
120 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x7C75);
121 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8036);
122 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x3000);
123 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8078);
124 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x3000);
125 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8031);
126 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x3300);
127 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8073);
128 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x3300);
129 : :
130 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAE06, 0xFC00, 0x7C00);
131 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x89D1);
132 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0004);
133 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8FBD);
134 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x0A00);
135 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8FBE);
136 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0D09);
137 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x89CD);
138 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0F0F);
139 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x89CF);
140 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0F0F);
141 : :
142 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x83A4);
143 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x6600);
144 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x83A6);
145 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x6601);
146 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x83C0);
147 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x6600);
148 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x83C2);
149 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x6601);
150 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8414);
151 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x6600);
152 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8416);
153 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x6601);
154 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x83F8);
155 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x6600);
156 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x83FA);
157 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x6601);
158 : :
159 : 0 : rtl_set_phy_mcu_patch_request(hw);
160 : :
161 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBD96, 0x1F00, 0x1000);
162 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBF1C, 0x0007, 0x0007);
163 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xBFBE, BIT_15);
164 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBF40, 0x0380, 0x0280);
165 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBF90, BIT_7, (BIT_6 | BIT_5));
166 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBF90, BIT_4, (BIT_3 | BIT_2));
167 : 0 : rtl_clear_phy_mcu_patch_request(hw);
168 : :
169 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x843B);
170 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x2000);
171 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x843D);
172 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x2000);
173 : :
174 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xB516, 0x7F);
175 : :
176 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xBF80, (BIT_5 | BIT_4));
177 : :
178 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8188);
179 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0044);
180 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00A8);
181 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00D6);
182 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00EC);
183 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00F6);
184 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00FC);
185 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00FE);
186 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00FE);
187 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00BC);
188 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0058);
189 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x002A);
190 : :
191 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8015);
192 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0800);
193 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FFD);
194 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0000);
195 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FFF);
196 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x7F00);
197 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FFB);
198 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
199 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FE9);
200 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0002);
201 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FEF);
202 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x00A5);
203 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FF1);
204 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0106);
205 : :
206 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FE1);
207 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0102);
208 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FE3);
209 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0400);
210 : :
211 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA654, BIT_11);
212 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0XA65A, (BIT_1 | BIT_0));
213 : :
214 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xAC3A, 0x5851);
215 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0XAC3C, (BIT_15 | BIT_14 | BIT_12),
216 : : BIT_13);
217 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAC42, BIT_9, (BIT_8 | BIT_7 | BIT_6));
218 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xAC3E, (BIT_15 | BIT_14 | BIT_13));
219 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xAC42, (BIT_5 | BIT_4 | BIT_3));
220 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAC42, BIT_1, (BIT_2 | BIT_0));
221 : :
222 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xAC1A, 0x00DB);
223 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xADE4, 0x01B5);
224 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xAD9C, (BIT_11 | BIT_10));
225 : :
226 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x814B);
227 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x1100);
228 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x814D);
229 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x1100);
230 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x814F);
231 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0B00);
232 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8142);
233 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
234 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8144);
235 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
236 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8150);
237 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
238 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8118);
239 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0700);
240 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x811A);
241 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0700);
242 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x811C);
243 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0500);
244 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x810F);
245 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
246 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8111);
247 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
248 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x811D);
249 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
250 : :
251 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xAC36, BIT_12);
252 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xAD1C, BIT_8);
253 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xADE8, 0xFFC0, 0x1400);
254 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x864B);
255 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x9D00);
256 : :
257 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8F97);
258 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x003F);
259 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x3F02);
260 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x023C);
261 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x3B0A);
262 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1C00);
263 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
264 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
265 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
266 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
267 : :
268 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xAD9C, BIT_5);
269 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8122);
270 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0C00);
271 : :
272 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x82C8);
273 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03ED);
274 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03FF);
275 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0009);
276 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03FE);
277 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x000B);
278 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0021);
279 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03F7);
280 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03B8);
281 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03E0);
282 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0049);
283 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0049);
284 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03E0);
285 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03B8);
286 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03F7);
287 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0021);
288 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x000B);
289 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03FE);
290 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0009);
291 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03FF);
292 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03ED);
293 : :
294 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x80EF);
295 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0C00);
296 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x82A0);
297 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x000E);
298 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03FE);
299 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03ED);
300 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0006);
301 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x001A);
302 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03F1);
303 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03D8);
304 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0023);
305 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0054);
306 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0322);
307 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x00DD);
308 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03AB);
309 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03DC);
310 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0027);
311 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x000E);
312 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03E5);
313 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03F9);
314 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0012);
315 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0001);
316 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03F1);
317 : :
318 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8018);
319 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA438, BIT_13);
320 : :
321 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FE4);
322 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0000);
323 : :
324 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB54C, 0xFFC0, 0x3700);
325 : 0 : }
326 : :
327 : : static void
328 : 0 : rtl_hw_phy_config_8126a_3(struct rtl_hw *hw)
329 : : {
330 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA442, BIT_11);
331 : :
332 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8183);
333 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x5900);
334 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA654, BIT_11);
335 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xB648, BIT_14);
336 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xAD2C, BIT_15);
337 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xAD94, BIT_5);
338 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xADA0, BIT_1);
339 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAE06, (BIT_15 | BIT_14 |
340 : : BIT_13 | BIT_12 | BIT_11 | BIT_10),
341 : : (BIT_14 | BIT_13 | BIT_12 | BIT_11 | BIT_10));
342 : :
343 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8647);
344 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0xE600);
345 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8036);
346 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x3000);
347 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8078);
348 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x3000);
349 : :
350 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x89E9);
351 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00);
352 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FFD);
353 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
354 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FFE);
355 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0200);
356 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FFF);
357 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0400);
358 : :
359 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8018);
360 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x7700);
361 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8F9C);
362 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0005);
363 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
364 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00ED);
365 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0502);
366 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0B00);
367 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xD401);
368 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8FA8);
369 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x2900);
370 : :
371 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x814B);
372 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x1100);
373 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x814D);
374 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x1100);
375 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x814F);
376 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0B00);
377 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8142);
378 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
379 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8144);
380 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
381 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8150);
382 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
383 : :
384 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8118);
385 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0700);
386 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x811A);
387 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0700);
388 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x811C);
389 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0500);
390 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x810F);
391 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
392 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8111);
393 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
394 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x811D);
395 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
396 : :
397 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xAD1C, BIT_8);
398 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xADE8, (BIT_15 | BIT_14 |
399 : : BIT_13 | BIT_12 | BIT_11 | BIT_10 |
400 : : BIT_9 | BIT_8 | BIT_7 | BIT_6),
401 : : (BIT_12 | BIT_10));
402 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x864B);
403 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x9D00);
404 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x862C);
405 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x1200);
406 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8566);
407 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x003F);
408 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x3F02);
409 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x023C);
410 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x3B0A);
411 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1C00);
412 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
413 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
414 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
415 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
416 : :
417 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xAD9C, BIT_5);
418 : :
419 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8122);
420 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0C00);
421 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x82C8);
422 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03ED);
423 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03FF);
424 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0009);
425 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03FE);
426 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x000B);
427 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0021);
428 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03F7);
429 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03B8);
430 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03E0);
431 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0049);
432 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0049);
433 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03E0);
434 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03B8);
435 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03F7);
436 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0021);
437 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x000B);
438 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03FE);
439 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0009);
440 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03FF);
441 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03ED);
442 : :
443 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x80EF);
444 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0C00);
445 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x82A0);
446 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x000E);
447 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03FE);
448 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03ED);
449 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0006);
450 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x001A);
451 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03F1);
452 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03D8);
453 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0023);
454 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0054);
455 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0322);
456 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x00DD);
457 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03AB);
458 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03DC);
459 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0027);
460 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x000E);
461 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03E5);
462 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03F9);
463 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0012);
464 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0001);
465 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03F1);
466 : :
467 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA430, BIT_1 | BIT_0);
468 : :
469 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB54C, 0xFFC0, 0x3700);
470 : 0 : }
471 : :
472 : : static void
473 : 0 : hw_phy_config_8126a(struct rtl_hw *hw)
474 : : {
475 [ # # # # ]: 0 : switch (hw->mcfg) {
476 : : case CFG_METHOD_69:
477 : : rtl_hw_phy_config_8126a_1(hw);
478 : : break;
479 : 0 : case CFG_METHOD_70:
480 : 0 : rtl_hw_phy_config_8126a_2(hw);
481 : 0 : break;
482 : 0 : case CFG_METHOD_71:
483 : 0 : rtl_hw_phy_config_8126a_3(hw);
484 : 0 : break;
485 : : }
486 : 0 : }
487 : :
488 : : static void
489 : 0 : hw_mac_mcu_config_8126a(struct rtl_hw *hw)
490 : : {
491 [ # # ]: 0 : if (hw->NotWrMcuPatchCode)
492 : : return;
493 : :
494 : 0 : rtl_hw_disable_mac_mcu_bps(hw);
495 : :
496 : : /* Get H/W mac mcu patch code version */
497 : 0 : hw->hw_mcu_patch_code_ver = rtl_get_hw_mcu_patch_code_ver(hw);
498 : :
499 [ # # # # ]: 0 : switch (hw->mcfg) {
500 : 0 : case CFG_METHOD_69:
501 : 0 : rtl_set_mac_mcu_8126a_1(hw);
502 : 0 : break;
503 : 0 : case CFG_METHOD_70:
504 : 0 : rtl_set_mac_mcu_8126a_2(hw);
505 : 0 : break;
506 : 0 : case CFG_METHOD_71:
507 : 0 : rtl_set_mac_mcu_8126a_3(hw);
508 : 0 : break;
509 : : }
510 : : }
511 : :
512 : : static void
513 : 0 : hw_phy_mcu_config_8126a(struct rtl_hw *hw)
514 : : {
515 [ # # # # ]: 0 : switch (hw->mcfg) {
516 : 0 : case CFG_METHOD_69:
517 : 0 : rtl_set_phy_mcu_8126a_1(hw);
518 : 0 : break;
519 : 0 : case CFG_METHOD_70:
520 : 0 : rtl_set_phy_mcu_8126a_2(hw);
521 : 0 : break;
522 : 0 : case CFG_METHOD_71:
523 : 0 : rtl_set_phy_mcu_8126a_3(hw);
524 : 0 : break;
525 : : }
526 : 0 : }
527 : :
528 : : const struct rtl_hw_ops rtl8126a_ops = {
529 : : .hw_init_rxcfg = hw_init_rxcfg_8126a,
530 : : .hw_ephy_config = hw_ephy_config_8126a,
531 : : .hw_phy_config = hw_phy_config_8126a,
532 : : .hw_mac_mcu_config = hw_mac_mcu_config_8126a,
533 : : .hw_phy_mcu_config = hw_phy_mcu_config_8126a,
534 : : };
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