Branch data Line data Source code
1 : : /* SPDX-License-Identifier: BSD-3-Clause
2 : : * Copyright(c) 2024 Realtek Corporation. All rights reserved
3 : : */
4 : :
5 : : #include "../r8169_ethdev.h"
6 : : #include "../r8169_hw.h"
7 : : #include "../r8169_phy.h"
8 : : #include "rtl8125d_mcu.h"
9 : :
10 : : /* For RTL8125D, CFG_METHOD_56,57 */
11 : :
12 : : static void
13 : 0 : hw_init_rxcfg_8125d(struct rtl_hw *hw)
14 : : {
15 : 0 : RTL_W32(hw, RxConfig, Rx_Fetch_Number_8 | Rx_Close_Multiple |
16 : : RxCfg_pause_slot_en | (RX_DMA_BURST_256 << RxCfgDMAShift));
17 : 0 : }
18 : :
19 : : static void
20 : 0 : hw_ephy_config_8125d(struct rtl_hw *hw)
21 : : {
22 : : switch (hw->mcfg) {
23 : : case CFG_METHOD_56:
24 : : case CFG_METHOD_57:
25 : : /* Nothing to do */
26 : : break;
27 : : }
28 : 0 : }
29 : :
30 : : static void
31 : 0 : rtl_hw_phy_config_8125d_1(struct rtl_hw *hw)
32 : : {
33 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA442, BIT_11);
34 : :
35 : 0 : rtl_set_phy_mcu_patch_request(hw);
36 : :
37 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xBF96, BIT_15);
38 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBF94, 0x0007, 0x0005);
39 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBF8E, 0x3C00, 0x2800);
40 : :
41 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBCD8, 0xC000, 0x4000);
42 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xBCD8, BIT_15 | BIT_14);
43 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBCD8, 0xC000, 0x4000);
44 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBC80, 0x001F, 0x0004);
45 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xBC82, BIT_15 | BIT_14 | BIT_13);
46 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xBC82, BIT_12 | BIT_11 | BIT_10);
47 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBC80, 0x001F, 0x0005);
48 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBC82, 0x00E0, 0x0040);
49 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xBC82, BIT_4 | BIT_3 | BIT_2);
50 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xBCD8, BIT_15 | BIT_14);
51 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBCD8, 0xC000, 0x8000);
52 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xBCD8, BIT_15 | BIT_14);
53 : :
54 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xBD70, BIT_8);
55 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA466, BIT_1);
56 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x836a);
57 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA438, 0xFF00);
58 : :
59 : 0 : rtl_clear_phy_mcu_patch_request(hw);
60 : :
61 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x832C);
62 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0500);
63 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB106, 0x0700, 0x0100);
64 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB206, 0x0700, 0x0200);
65 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB306, 0x0700, 0x0300);
66 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x80CB);
67 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0300);
68 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xBCF4, 0x0000);
69 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xBCF6, 0x0000);
70 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xBC12, 0x0000);
71 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x844d);
72 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0200);
73 [ # # ]: 0 : if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(hw)) {
74 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8feb);
75 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
76 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8fe9);
77 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0600);
78 : : }
79 : :
80 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAC7E, 0x01FC, 0x00B4);
81 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8105);
82 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x7A00);
83 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8117);
84 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x3A00);
85 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8103);
86 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x7400);
87 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8115);
88 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x3400);
89 : :
90 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xAD40, BIT_5 | BIT_4);
91 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAD66, 0x000F, 0x0007);
92 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAD68, 0xF000, 0x8000);
93 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAD68, 0x0F00, 0x0500);
94 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAD68, 0x000F, 0x0002);
95 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAD6A, 0xF000, 0x7000);
96 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xAC50, 0x01E8);
97 : :
98 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x81FA);
99 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x5400);
100 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA864, 0x00F0, 0x00C0);
101 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA42C, 0x00FF, 0x0002);
102 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80E1);
103 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x0F00);
104 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80DE);
105 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xF000, 0x0700);
106 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA846, BIT_7);
107 : :
108 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80BA);
109 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8A04);
110 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80BD);
111 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xCA00);
112 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80B7);
113 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xB300);
114 : :
115 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80CE);
116 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8A04);
117 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80D1);
118 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xCA00);
119 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80CB);
120 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xBB00);
121 : :
122 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80A6);
123 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x4909);
124 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80A8);
125 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x05B8);
126 : :
127 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8200);
128 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x5800);
129 : :
130 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8FF1);
131 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x7078);
132 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8FF3);
133 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x5D78);
134 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8FF5);
135 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x7862);
136 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8FF7);
137 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x1400);
138 : :
139 [ # # ]: 0 : if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(hw)) {
140 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x814C);
141 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8455);
142 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x814E);
143 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x84A6);
144 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8163);
145 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x0600);
146 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x816A);
147 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x0500);
148 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8171);
149 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x1f00);
150 : : }
151 : :
152 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBC3A, 0x000F, 0x0006);
153 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8064);
154 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA438, BIT_10 | BIT_9 | BIT_8);
155 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8067);
156 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA438, BIT_10 | BIT_9 | BIT_8);
157 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x806A);
158 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA438, BIT_10 | BIT_9 | BIT_8);
159 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x806D);
160 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA438, BIT_10 | BIT_9 | BIT_8);
161 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8070);
162 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA438, BIT_10 | BIT_9 | BIT_8);
163 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8073);
164 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA438, BIT_10 | BIT_9 | BIT_8);
165 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8076);
166 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA438, BIT_10 | BIT_9 | BIT_8);
167 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8079);
168 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA438, BIT_10 | BIT_9 | BIT_8);
169 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x807C);
170 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA438, BIT_10 | BIT_9 | BIT_8);
171 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x807F);
172 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA438, BIT_10 | BIT_9 | BIT_8);
173 : :
174 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBFA0, 0xFF70, 0x5500);
175 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xBFA2, 0x9D00);
176 : :
177 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8165);
178 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0x0700, 0x0200);
179 : :
180 [ # # ]: 0 : if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(hw)) {
181 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8019);
182 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA438, BIT_8);
183 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8FE3);
184 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0005);
185 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
186 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00ED);
187 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0502);
188 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0B00);
189 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xD401);
190 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x2900);
191 : : }
192 : :
193 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8018);
194 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x1700);
195 : :
196 [ # # ]: 0 : if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(hw)) {
197 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x815B);
198 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x1700);
199 : : }
200 : :
201 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA4E0, BIT_15);
202 : :
203 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA5D4, BIT_5);
204 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA654, BIT_11);
205 : :
206 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA430, BIT_12 | BIT_0);
207 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA442, BIT_7);
208 : 0 : }
209 : :
210 : : static void
211 : 0 : rtl_hw_phy_config_8125d_2(struct rtl_hw *hw)
212 : : {
213 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA442, BIT_11);
214 : :
215 : 0 : rtl_set_phy_mcu_patch_request(hw);
216 : :
217 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBCD8, 0xC000, 0x4000);
218 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xBCD8, BIT_15 | BIT_14);
219 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBCD8, 0xC000, 0x4000);
220 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBC80, 0x001F, 0x0004);
221 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xBC82, BIT_15 | BIT_14 | BIT_13);
222 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xBC82, BIT_12 | BIT_11 | BIT_10);
223 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBC80, 0x001F, 0x0005);
224 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBC82, 0x00E0, 0x0040);
225 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xBC82, BIT_4 | BIT_3 | BIT_2);
226 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xBCD8, BIT_15 | BIT_14);
227 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBCD8, 0xC000, 0x8000);
228 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xBCD8, BIT_15 | BIT_14);
229 : :
230 : 0 : rtl_clear_phy_mcu_patch_request(hw);
231 : :
232 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAC7E, 0x01FC, 0x00B4);
233 : :
234 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8105);
235 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x7A00);
236 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8117);
237 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x3A00);
238 : :
239 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8103);
240 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x7400);
241 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8115);
242 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x3400);
243 : :
244 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FEB);
245 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0500);
246 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FEA);
247 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0700);
248 : :
249 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x80D6);
250 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0xEF00);
251 : :
252 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA5D4, BIT_5);
253 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA654, BIT_11);
254 : :
255 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA430, BIT_12 | BIT_0);
256 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA442, BIT_7);
257 : 0 : }
258 : :
259 : : static void
260 : 0 : hw_phy_config_8125d(struct rtl_hw *hw)
261 : : {
262 [ # # # ]: 0 : switch (hw->mcfg) {
263 : 0 : case CFG_METHOD_56:
264 : 0 : rtl_hw_phy_config_8125d_1(hw);
265 : 0 : break;
266 : 0 : case CFG_METHOD_57:
267 : 0 : rtl_hw_phy_config_8125d_2(hw);
268 : 0 : break;
269 : : }
270 : 0 : }
271 : :
272 : : static void
273 : 0 : hw_mac_mcu_config_8125d(struct rtl_hw *hw)
274 : : {
275 [ # # ]: 0 : if (hw->NotWrMcuPatchCode)
276 : : return;
277 : :
278 : 0 : rtl_hw_disable_mac_mcu_bps(hw);
279 : :
280 [ # # ]: 0 : switch (hw->mcfg) {
281 : 0 : case CFG_METHOD_56:
282 : 0 : rtl_set_mac_mcu_8125d_1(hw);
283 : 0 : break;
284 : : }
285 : : }
286 : :
287 : : static void
288 : 0 : hw_phy_mcu_config_8125d(struct rtl_hw *hw)
289 : : {
290 [ # # # ]: 0 : switch (hw->mcfg) {
291 : 0 : case CFG_METHOD_56:
292 : 0 : rtl_set_phy_mcu_8125d_1(hw);
293 : 0 : break;
294 : 0 : case CFG_METHOD_57:
295 : 0 : rtl_set_phy_mcu_8125d_2(hw);
296 : 0 : break;
297 : : }
298 : 0 : }
299 : :
300 : : const struct rtl_hw_ops rtl8125d_ops = {
301 : : .hw_init_rxcfg = hw_init_rxcfg_8125d,
302 : : .hw_ephy_config = hw_ephy_config_8125d,
303 : : .hw_phy_config = hw_phy_config_8125d,
304 : : .hw_mac_mcu_config = hw_mac_mcu_config_8125d,
305 : : .hw_phy_mcu_config = hw_phy_mcu_config_8125d,
306 : : };
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