Branch data Line data Source code
1 : : /* SPDX-License-Identifier: BSD-3-Clause
2 : : * Copyright (c) 2022 NVIDIA Corporation & Affiliates
3 : : */
4 : :
5 : : #include <rte_flow.h>
6 : : #include <rte_flow_driver.h>
7 : : #include <rte_stdatomic.h>
8 : :
9 : : #include <mlx5_malloc.h>
10 : :
11 : : #include "mlx5.h"
12 : : #include "mlx5_common.h"
13 : : #include "mlx5_defs.h"
14 : : #include "mlx5_flow.h"
15 : : #include "mlx5_flow_os.h"
16 : : #include "mlx5_rx.h"
17 : :
18 : : #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
19 : : #include "mlx5_hws_cnt.h"
20 : :
21 : : /** Fast path async flow API functions. */
22 : : static struct rte_flow_fp_ops mlx5_flow_hw_fp_ops;
23 : :
24 : : /*
25 : : * The default ipool threshold value indicates which per_core_cache
26 : : * value to set.
27 : : */
28 : : #define MLX5_HW_IPOOL_SIZE_THRESHOLD (1 << 19)
29 : : /* The default min local cache size. */
30 : : #define MLX5_HW_IPOOL_CACHE_MIN (1 << 9)
31 : :
32 : : /* Default push burst threshold. */
33 : : #define BURST_THR 32u
34 : :
35 : : /* Default queue to flush the flows. */
36 : : #define MLX5_DEFAULT_FLUSH_QUEUE 0
37 : :
38 : : /* Maximum number of rules in control flow tables. */
39 : : #define MLX5_HW_CTRL_FLOW_NB_RULES (4096)
40 : :
41 : : /* Lowest flow group usable by an application if group translation is done. */
42 : : #define MLX5_HW_LOWEST_USABLE_GROUP (1)
43 : :
44 : : /* Maximum group index usable by user applications for transfer flows. */
45 : : #define MLX5_HW_MAX_TRANSFER_GROUP (UINT32_MAX - 1)
46 : :
47 : : /* Maximum group index usable by user applications for egress flows. */
48 : : #define MLX5_HW_MAX_EGRESS_GROUP (UINT32_MAX - 1)
49 : :
50 : : /* Lowest priority for HW root table. */
51 : : #define MLX5_HW_LOWEST_PRIO_ROOT 15
52 : :
53 : : /* Lowest priority for HW non-root table. */
54 : : #define MLX5_HW_LOWEST_PRIO_NON_ROOT (UINT32_MAX)
55 : :
56 : : /* Priorities for Rx control flow rules. */
57 : : #define MLX5_HW_CTRL_RX_PRIO_L2 (MLX5_HW_LOWEST_PRIO_ROOT)
58 : : #define MLX5_HW_CTRL_RX_PRIO_L3 (MLX5_HW_LOWEST_PRIO_ROOT - 1)
59 : : #define MLX5_HW_CTRL_RX_PRIO_L4 (MLX5_HW_LOWEST_PRIO_ROOT - 2)
60 : :
61 : : #define MLX5_HW_VLAN_PUSH_TYPE_IDX 0
62 : : #define MLX5_HW_VLAN_PUSH_VID_IDX 1
63 : : #define MLX5_HW_VLAN_PUSH_PCP_IDX 2
64 : :
65 : : #define MLX5_HW_PORT_IS_PROXY(priv) \
66 : : (!!((priv)->sh->esw_mode && (priv)->master))
67 : :
68 : :
69 : : struct mlx5_indlst_legacy {
70 : : struct mlx5_indirect_list indirect;
71 : : struct rte_flow_action_handle *handle;
72 : : enum rte_flow_action_type legacy_type;
73 : : };
74 : :
75 : : #define MLX5_CONST_ENCAP_ITEM(encap_type, ptr) \
76 : : (((const struct encap_type *)(ptr))->definition)
77 : :
78 : : /**
79 : : * Returns the size of a struct with a following layout:
80 : : *
81 : : * @code{.c}
82 : : * struct rte_flow_hw {
83 : : * // rte_flow_hw fields
84 : : * uint8_t rule[mlx5dr_rule_get_handle_size()];
85 : : * };
86 : : * @endcode
87 : : *
88 : : * Such struct is used as a basic container for HW Steering flow rule.
89 : : */
90 : : static size_t
91 : : mlx5_flow_hw_entry_size(void)
92 : : {
93 : 0 : return sizeof(struct rte_flow_hw) + mlx5dr_rule_get_handle_size();
94 : : }
95 : :
96 : : /**
97 : : * Returns the size of "auxed" rte_flow_hw structure which is assumed to be laid out as follows:
98 : : *
99 : : * @code{.c}
100 : : * struct {
101 : : * struct rte_flow_hw {
102 : : * // rte_flow_hw fields
103 : : * uint8_t rule[mlx5dr_rule_get_handle_size()];
104 : : * } flow;
105 : : * struct rte_flow_hw_aux aux;
106 : : * };
107 : : * @endcode
108 : : *
109 : : * Such struct is used whenever rte_flow_hw_aux cannot be allocated separately from the rte_flow_hw
110 : : * e.g., when table is resizable.
111 : : */
112 : : static size_t
113 : : mlx5_flow_hw_auxed_entry_size(void)
114 : : {
115 : 0 : size_t rule_size = mlx5dr_rule_get_handle_size();
116 : :
117 : 0 : return sizeof(struct rte_flow_hw) + rule_size + sizeof(struct rte_flow_hw_aux);
118 : : }
119 : :
120 : : /**
121 : : * Returns a valid pointer to rte_flow_hw_aux associated with given rte_flow_hw
122 : : * depending on template table configuration.
123 : : */
124 : : static __rte_always_inline struct rte_flow_hw_aux *
125 : : mlx5_flow_hw_aux(uint16_t port_id, struct rte_flow_hw *flow)
126 : : {
127 : 0 : struct rte_flow_template_table *table = flow->table;
128 : :
129 : 0 : if (!flow->nt_rule) {
130 [ # # # # : 0 : if (rte_flow_template_table_resizable(port_id, &table->cfg.attr)) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # #
# ]
131 : 0 : size_t offset = sizeof(struct rte_flow_hw) + mlx5dr_rule_get_handle_size();
132 : :
133 : 0 : return RTE_PTR_ADD(flow, offset);
134 : : } else {
135 : 0 : return &table->flow_aux[flow->idx - 1];
136 : : }
137 : : } else {
138 : 0 : return flow->nt2hws->flow_aux;
139 : : }
140 : : }
141 : :
142 : : static __rte_always_inline void
143 : : mlx5_flow_hw_aux_set_age_idx(struct rte_flow_hw *flow,
144 : : struct rte_flow_hw_aux *aux,
145 : : uint32_t age_idx)
146 : : {
147 : : /*
148 : : * Only when creating a flow rule, the type will be set explicitly.
149 : : * Or else, it should be none in the rule update case.
150 : : */
151 [ # # # # : 0 : if (unlikely(flow->operation_type == MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE))
# # # # #
# # # # #
# # # # #
# ]
152 : 0 : aux->upd.age_idx = age_idx;
153 : : else
154 : 0 : aux->orig.age_idx = age_idx;
155 : : }
156 : :
157 : : static __rte_always_inline uint32_t
158 : : mlx5_flow_hw_aux_get_age_idx(struct rte_flow_hw *flow, struct rte_flow_hw_aux *aux)
159 : : {
160 [ # # # # : 0 : if (unlikely(flow->operation_type == MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE))
# # # # #
# # # ]
161 : 0 : return aux->upd.age_idx;
162 : : else
163 : 0 : return aux->orig.age_idx;
164 : : }
165 : :
166 : : static __rte_always_inline void
167 : : mlx5_flow_hw_aux_set_mtr_id(struct rte_flow_hw *flow,
168 : : struct rte_flow_hw_aux *aux,
169 : : uint32_t mtr_id)
170 : : {
171 [ # # # # : 0 : if (unlikely(flow->operation_type == MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE))
# # # # #
# ]
172 : 0 : aux->upd.mtr_id = mtr_id;
173 : : else
174 : 0 : aux->orig.mtr_id = mtr_id;
175 : : }
176 : :
177 : : static __rte_always_inline uint32_t
178 : : mlx5_flow_hw_aux_get_mtr_id(struct rte_flow_hw *flow, struct rte_flow_hw_aux *aux)
179 : : {
180 [ # # ]: 0 : if (unlikely(flow->operation_type == MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE))
181 : 0 : return aux->upd.mtr_id;
182 : : else
183 : 0 : return aux->orig.mtr_id;
184 : : }
185 : :
186 : : static __rte_always_inline struct mlx5_hw_q_job *
187 : : flow_hw_action_job_init(struct mlx5_priv *priv, uint32_t queue,
188 : : const struct rte_flow_action_handle *handle,
189 : : void *user_data, void *query_data,
190 : : enum mlx5_hw_job_type type,
191 : : enum mlx5_hw_indirect_type indirect_type,
192 : : struct rte_flow_error *error);
193 : : static void
194 : : flow_hw_age_count_release(struct mlx5_priv *priv, uint32_t queue, struct rte_flow_hw *flow,
195 : : struct rte_flow_error *error);
196 : :
197 : : static int
198 : : mlx5_tbl_multi_pattern_process(struct rte_eth_dev *dev,
199 : : struct rte_flow_template_table *tbl,
200 : : struct mlx5_multi_pattern_segment *segment,
201 : : uint32_t bulk_size,
202 : : struct rte_flow_error *error);
203 : : static void
204 : : mlx5_destroy_multi_pattern_segment(struct mlx5_multi_pattern_segment *segment);
205 : :
206 : : static __rte_always_inline enum mlx5_indirect_list_type
207 : : flow_hw_inlist_type_get(const struct rte_flow_action *actions);
208 : :
209 : : static int
210 : : flow_hw_allocate_actions(struct rte_eth_dev *dev,
211 : : uint64_t action_flags,
212 : : struct rte_flow_error *error);
213 : :
214 : : static int
215 : : flow_hw_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
216 : : const struct rte_flow_item items[],
217 : : const struct rte_flow_action actions[],
218 : : bool external __rte_unused, int hairpin __rte_unused,
219 : : struct rte_flow_error *error);
220 : :
221 : : bool
222 : 0 : mlx5_hw_ctx_validate(const struct rte_eth_dev *dev, struct rte_flow_error *error)
223 : : {
224 : 0 : const struct mlx5_priv *priv = dev->data->dev_private;
225 : :
226 [ # # ]: 0 : if (!priv->dr_ctx) {
227 : 0 : rte_flow_error_set(error, EINVAL,
228 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
229 : : "non-template flow engine was not configured");
230 : 0 : return false;
231 : : }
232 : : return true;
233 : : }
234 : :
235 : : static int
236 : : flow_hw_allocate_actions(struct rte_eth_dev *dev,
237 : : uint64_t action_flags,
238 : : struct rte_flow_error *error);
239 : :
240 : : static __rte_always_inline int
241 : : mlx5_multi_pattern_reformat_to_index(enum mlx5dr_action_type type)
242 : : {
243 : : switch (type) {
244 : : case MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2:
245 : : return 0;
246 : : case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2:
247 : : return 1;
248 : : case MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2:
249 : : return 2;
250 : : case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3:
251 : : return 3;
252 : : default:
253 : : break;
254 : : }
255 : : return -1;
256 : : }
257 : :
258 : : /* Include only supported reformat actions for BWC non template API. */
259 : : static __rte_always_inline int
260 : : mlx5_bwc_multi_pattern_reformat_to_index(enum mlx5dr_action_type type)
261 : : {
262 : 0 : switch (type) {
263 : : case MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2:
264 : : case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2:
265 : : case MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2:
266 : : case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3:
267 : : return mlx5_multi_pattern_reformat_to_index(type);
268 : : default:
269 : : break;
270 : : }
271 : : return -1;
272 : : }
273 : :
274 : : static __rte_always_inline enum mlx5dr_action_type
275 : : mlx5_multi_pattern_reformat_index_to_type(uint32_t ix)
276 : : {
277 : : switch (ix) {
278 : : case 0:
279 : : return MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2;
280 : : case 1:
281 : : return MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;
282 : : case 2:
283 : : return MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2;
284 : : case 3:
285 : : return MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3;
286 : : default:
287 : : break;
288 : : }
289 : : return MLX5DR_ACTION_TYP_MAX;
290 : : }
291 : :
292 : : static inline enum mlx5dr_table_type
293 : : get_mlx5dr_fdb_table_type(const struct rte_flow_attr *attr,
294 : : uint32_t specialize, bool fdb_unified_en)
295 : : {
296 [ # # # # ]: 0 : if (fdb_unified_en && !!attr->group) {
297 [ # # ]: 0 : if ((specialize & (RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_WIRE_ORIG |
298 : : RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_VPORT_ORIG)) == 0)
299 : : return MLX5DR_TABLE_TYPE_FDB_UNIFIED;
300 : : MLX5_ASSERT((specialize & (RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_WIRE_ORIG |
301 : : RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_VPORT_ORIG)) !=
302 : : (RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_WIRE_ORIG |
303 : : RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_VPORT_ORIG));
304 [ # # ]: 0 : if (specialize & RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_WIRE_ORIG)
305 : : return MLX5DR_TABLE_TYPE_FDB_RX;
306 [ # # ]: 0 : if (specialize & RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_VPORT_ORIG)
307 : 0 : return MLX5DR_TABLE_TYPE_FDB_TX;
308 : : }
309 : :
310 : : return MLX5DR_TABLE_TYPE_FDB;
311 : : }
312 : :
313 : : static inline enum mlx5dr_table_type
314 : 0 : get_mlx5dr_table_type(const struct rte_flow_attr *attr, uint32_t specialize,
315 : : bool fdb_unified_en)
316 : : {
317 : : enum mlx5dr_table_type type;
318 : :
319 [ # # ]: 0 : if (attr->transfer)
320 : : type = get_mlx5dr_fdb_table_type(attr, specialize, fdb_unified_en);
321 [ # # ]: 0 : else if (attr->egress)
322 : : type = MLX5DR_TABLE_TYPE_NIC_TX;
323 : : else
324 : : type = MLX5DR_TABLE_TYPE_NIC_RX;
325 : 0 : return type;
326 : : }
327 : :
328 : : /* Non template default queue size used for inner ctrl queue. */
329 : : #define MLX5_NT_DEFAULT_QUEUE_SIZE 32
330 : :
331 : : static int flow_hw_flush_all_ctrl_flows(struct rte_eth_dev *dev);
332 : : static int flow_hw_translate_group(struct rte_eth_dev *dev,
333 : : const struct mlx5_flow_template_table_cfg *cfg,
334 : : uint32_t group,
335 : : uint32_t *table_group,
336 : : struct rte_flow_error *error);
337 : : static __rte_always_inline int
338 : : flow_hw_set_vlan_vid_construct(struct rte_eth_dev *dev,
339 : : struct mlx5_modification_cmd *mhdr_cmd,
340 : : struct mlx5_action_construct_data *act_data,
341 : : const struct mlx5_hw_actions *hw_acts,
342 : : const struct rte_flow_action *action);
343 : : static void
344 : : flow_hw_construct_quota(struct mlx5_priv *priv,
345 : : struct mlx5dr_rule_action *rule_act, uint32_t qid);
346 : :
347 : : static int
348 : : mlx5_flow_ct_init(struct rte_eth_dev *dev,
349 : : uint32_t nb_conn_tracks,
350 : : uint16_t nb_queue);
351 : :
352 : : static __rte_always_inline uint32_t flow_hw_tx_tag_regc_mask(struct rte_eth_dev *dev);
353 : : static __rte_always_inline uint32_t flow_hw_tx_tag_regc_value(struct rte_eth_dev *dev);
354 : :
355 : : static int flow_hw_async_create_validate(struct rte_eth_dev *dev,
356 : : const uint32_t queue,
357 : : const struct rte_flow_template_table *table,
358 : : enum rte_flow_table_insertion_type insertion_type,
359 : : const uint32_t rule_index,
360 : : const struct rte_flow_item items[],
361 : : const uint8_t pattern_template_index,
362 : : const struct rte_flow_action actions[],
363 : : const uint8_t action_template_index,
364 : : struct rte_flow_error *error);
365 : : static int flow_hw_async_update_validate(struct rte_eth_dev *dev,
366 : : const uint32_t queue,
367 : : const struct rte_flow_hw *flow,
368 : : const struct rte_flow_action actions[],
369 : : const uint8_t action_template_index,
370 : : struct rte_flow_error *error);
371 : : static int flow_hw_async_destroy_validate(struct rte_eth_dev *dev,
372 : : const uint32_t queue,
373 : : const struct rte_flow_hw *flow,
374 : : struct rte_flow_error *error);
375 : :
376 : : const struct mlx5_flow_driver_ops mlx5_flow_hw_drv_ops;
377 : :
378 : : /* DR action flags with different table. */
379 : : static uint32_t mlx5_hw_act_flag[MLX5_HW_ACTION_FLAG_MAX]
380 : : [MLX5DR_TABLE_TYPE_MAX] = {
381 : : {
382 : : MLX5DR_ACTION_FLAG_ROOT_RX,
383 : : MLX5DR_ACTION_FLAG_ROOT_TX,
384 : : MLX5DR_ACTION_FLAG_ROOT_FDB,
385 : : MLX5DR_ACTION_FLAG_ROOT_FDB,
386 : : MLX5DR_ACTION_FLAG_ROOT_FDB,
387 : : MLX5DR_ACTION_FLAG_ROOT_FDB,
388 : : },
389 : : {
390 : : MLX5DR_ACTION_FLAG_HWS_RX,
391 : : MLX5DR_ACTION_FLAG_HWS_TX,
392 : : MLX5DR_ACTION_FLAG_HWS_FDB,
393 : : MLX5DR_ACTION_FLAG_HWS_FDB_RX,
394 : : MLX5DR_ACTION_FLAG_HWS_FDB_TX,
395 : : MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED,
396 : : },
397 : : };
398 : :
399 : : /**
400 : : * Jump table flags.
401 : : * Can jump to FDB_RX table from FDB_RX or UNIFIED tables.
402 : : * Can jump to FDB_TX table from FDB_TX or UNIFIED tables.
403 : : * Can jump to UNIFIED table from all tables.
404 : : */
405 : : static uint32_t mlx5_hw_act_dest_table_flag[MLX5DR_TABLE_TYPE_MAX] = {
406 : : MLX5DR_ACTION_FLAG_HWS_RX,
407 : : MLX5DR_ACTION_FLAG_HWS_TX,
408 : : MLX5DR_ACTION_FLAG_HWS_FDB,
409 : : (MLX5DR_ACTION_FLAG_HWS_FDB_RX | MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED),
410 : : (MLX5DR_ACTION_FLAG_HWS_FDB_TX | MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED),
411 : : (MLX5DR_ACTION_FLAG_HWS_FDB_RX | MLX5DR_ACTION_FLAG_HWS_FDB_TX |
412 : : MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED),
413 : : };
414 : :
415 : : /* Ethernet item spec for promiscuous mode. */
416 : : static const struct rte_flow_item_eth ctrl_rx_eth_promisc_spec = {
417 : : .hdr.dst_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
418 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
419 : : .hdr.ether_type = 0,
420 : : };
421 : : /* Ethernet item mask for promiscuous mode. */
422 : : static const struct rte_flow_item_eth ctrl_rx_eth_promisc_mask = {
423 : : .hdr.dst_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
424 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
425 : : .hdr.ether_type = 0,
426 : : };
427 : :
428 : : /* Ethernet item spec for all multicast mode. */
429 : : static const struct rte_flow_item_eth ctrl_rx_eth_mcast_spec = {
430 : : .hdr.dst_addr.addr_bytes = { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 },
431 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
432 : : .hdr.ether_type = 0,
433 : : };
434 : : /* Ethernet item mask for all multicast mode. */
435 : : static const struct rte_flow_item_eth ctrl_rx_eth_mcast_mask = {
436 : : .hdr.dst_addr.addr_bytes = { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 },
437 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
438 : : .hdr.ether_type = 0,
439 : : };
440 : :
441 : : /* Ethernet item spec for IPv4 multicast traffic. */
442 : : static const struct rte_flow_item_eth ctrl_rx_eth_ipv4_mcast_spec = {
443 : : .hdr.dst_addr.addr_bytes = { 0x01, 0x00, 0x5e, 0x00, 0x00, 0x00 },
444 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
445 : : .hdr.ether_type = 0,
446 : : };
447 : : /* Ethernet item mask for IPv4 multicast traffic. */
448 : : static const struct rte_flow_item_eth ctrl_rx_eth_ipv4_mcast_mask = {
449 : : .hdr.dst_addr.addr_bytes = { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 },
450 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
451 : : .hdr.ether_type = 0,
452 : : };
453 : :
454 : : /* Ethernet item spec for IPv6 multicast traffic. */
455 : : static const struct rte_flow_item_eth ctrl_rx_eth_ipv6_mcast_spec = {
456 : : .hdr.dst_addr.addr_bytes = { 0x33, 0x33, 0x00, 0x00, 0x00, 0x00 },
457 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
458 : : .hdr.ether_type = 0,
459 : : };
460 : : /* Ethernet item mask for IPv6 multicast traffic. */
461 : : static const struct rte_flow_item_eth ctrl_rx_eth_ipv6_mcast_mask = {
462 : : .hdr.dst_addr.addr_bytes = { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 },
463 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
464 : : .hdr.ether_type = 0,
465 : : };
466 : :
467 : : /* Ethernet item mask for unicast traffic. */
468 : : static const struct rte_flow_item_eth ctrl_rx_eth_dmac_mask = {
469 : : .hdr.dst_addr.addr_bytes = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
470 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
471 : : .hdr.ether_type = 0,
472 : : };
473 : :
474 : : /* Ethernet item spec for broadcast. */
475 : : static const struct rte_flow_item_eth ctrl_rx_eth_bcast_spec = {
476 : : .hdr.dst_addr.addr_bytes = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
477 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
478 : : .hdr.ether_type = 0,
479 : : };
480 : :
481 : : static inline uint32_t
482 : : flow_hw_q_pending(struct mlx5_priv *priv, uint32_t queue)
483 : : {
484 : 0 : struct mlx5_hw_q *q = &priv->hw_q[queue];
485 : :
486 : : MLX5_ASSERT(q->size >= q->job_idx);
487 : 0 : return (q->size - q->job_idx) + q->ongoing_flow_ops;
488 : : }
489 : :
490 : : static inline void
491 : 0 : flow_hw_q_inc_flow_ops(struct mlx5_priv *priv, uint32_t queue)
492 : : {
493 : 0 : struct mlx5_hw_q *q = &priv->hw_q[queue];
494 : :
495 : 0 : q->ongoing_flow_ops++;
496 : 0 : }
497 : :
498 : : static inline void
499 : : flow_hw_q_dec_flow_ops(struct mlx5_priv *priv, uint32_t queue)
500 : : {
501 : 0 : struct mlx5_hw_q *q = &priv->hw_q[queue];
502 : :
503 : 0 : q->ongoing_flow_ops--;
504 : : }
505 : :
506 : : static inline enum mlx5dr_matcher_insert_mode
507 : : flow_hw_matcher_insert_mode_get(enum rte_flow_table_insertion_type insert_type)
508 : : {
509 : 0 : if (insert_type == RTE_FLOW_TABLE_INSERTION_TYPE_PATTERN)
510 : : return MLX5DR_MATCHER_INSERT_BY_HASH;
511 : : else
512 : 0 : return MLX5DR_MATCHER_INSERT_BY_INDEX;
513 : : }
514 : :
515 : : static inline enum mlx5dr_matcher_distribute_mode
516 : : flow_hw_matcher_distribute_mode_get(enum rte_flow_table_hash_func hash_func)
517 : : {
518 [ # # ]: 0 : if (hash_func == RTE_FLOW_TABLE_HASH_FUNC_LINEAR)
519 : : return MLX5DR_MATCHER_DISTRIBUTE_BY_LINEAR;
520 : : else
521 : 0 : return MLX5DR_MATCHER_DISTRIBUTE_BY_HASH;
522 : : }
523 : :
524 : : /**
525 : : * Set the hash fields according to the @p rss_desc information.
526 : : *
527 : : * @param[in] rss_desc
528 : : * Pointer to the mlx5_flow_rss_desc.
529 : : * @param[out] hash_fields
530 : : * Pointer to the RSS hash fields.
531 : : */
532 : : static void
533 : 0 : flow_hw_hashfields_set(struct mlx5_flow_rss_desc *rss_desc,
534 : : uint64_t *hash_fields)
535 : : {
536 : : uint64_t fields = 0;
537 : : int rss_inner = 0;
538 [ # # ]: 0 : uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
539 : :
540 : : #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
541 [ # # ]: 0 : if (rss_desc->level >= 2)
542 : : rss_inner = 1;
543 : : #endif
544 [ # # ]: 0 : if (rss_types & MLX5_IPV4_LAYER_TYPES) {
545 [ # # ]: 0 : if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
546 : : fields |= IBV_RX_HASH_SRC_IPV4;
547 [ # # ]: 0 : else if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
548 : : fields |= IBV_RX_HASH_DST_IPV4;
549 : : else
550 : : fields |= MLX5_IPV4_IBV_RX_HASH;
551 [ # # ]: 0 : } else if (rss_types & MLX5_IPV6_LAYER_TYPES) {
552 [ # # ]: 0 : if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
553 : : fields |= IBV_RX_HASH_SRC_IPV6;
554 [ # # ]: 0 : else if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
555 : : fields |= IBV_RX_HASH_DST_IPV6;
556 : : else
557 : : fields |= MLX5_IPV6_IBV_RX_HASH;
558 : : }
559 [ # # ]: 0 : if (rss_types & RTE_ETH_RSS_UDP) {
560 [ # # ]: 0 : if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
561 : 0 : fields |= IBV_RX_HASH_SRC_PORT_UDP;
562 [ # # ]: 0 : else if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
563 : 0 : fields |= IBV_RX_HASH_DST_PORT_UDP;
564 : : else
565 : 0 : fields |= MLX5_UDP_IBV_RX_HASH;
566 [ # # ]: 0 : } else if (rss_types & RTE_ETH_RSS_TCP) {
567 [ # # ]: 0 : if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
568 : 0 : fields |= IBV_RX_HASH_SRC_PORT_TCP;
569 [ # # ]: 0 : else if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
570 : 0 : fields |= IBV_RX_HASH_DST_PORT_TCP;
571 : : else
572 : 0 : fields |= MLX5_TCP_IBV_RX_HASH;
573 : : }
574 [ # # ]: 0 : if (rss_types & RTE_ETH_RSS_ESP)
575 : 0 : fields |= IBV_RX_HASH_IPSEC_SPI;
576 [ # # ]: 0 : if (rss_inner)
577 : 0 : fields |= IBV_RX_HASH_INNER;
578 : 0 : *hash_fields |= fields;
579 : 0 : }
580 : :
581 : : uint64_t
582 : 0 : mlx5_flow_hw_action_flags_get(const struct rte_flow_action actions[],
583 : : const struct rte_flow_action **qrss,
584 : : const struct rte_flow_action **mark,
585 : : int *encap_idx,
586 : : int *act_cnt,
587 : : struct rte_flow_error *error)
588 : : {
589 : : uint64_t action_flags = 0;
590 : : const struct rte_flow_action *action;
591 : : const struct rte_flow_action_raw_encap *raw_encap;
592 : : int raw_decap_idx = -1;
593 : : int action_idx;
594 : :
595 : 0 : *encap_idx = -1;
596 : : action_idx = 0;
597 [ # # ]: 0 : for (action = actions; action->type != RTE_FLOW_ACTION_TYPE_END; action++) {
598 : 0 : int type = (int)action->type;
599 [ # # # # : 0 : switch (type) {
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
600 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT:
601 [ # # # # : 0 : switch (MLX5_INDIRECT_ACTION_TYPE_GET(action->conf)) {
# # ]
602 : 0 : case MLX5_INDIRECT_ACTION_TYPE_RSS:
603 : 0 : goto rss;
604 : 0 : case MLX5_INDIRECT_ACTION_TYPE_AGE:
605 : 0 : goto age;
606 : 0 : case MLX5_INDIRECT_ACTION_TYPE_COUNT:
607 : 0 : goto count;
608 : 0 : case MLX5_INDIRECT_ACTION_TYPE_CT:
609 : 0 : goto ct;
610 : 0 : case MLX5_INDIRECT_ACTION_TYPE_METER_MARK:
611 : 0 : goto meter;
612 : 0 : default:
613 : 0 : goto error;
614 : : }
615 : : break;
616 : 0 : case RTE_FLOW_ACTION_TYPE_DROP:
617 : 0 : action_flags |= MLX5_FLOW_ACTION_DROP;
618 : 0 : break;
619 : 0 : case RTE_FLOW_ACTION_TYPE_FLAG:
620 : 0 : action_flags |= MLX5_FLOW_ACTION_FLAG;
621 : 0 : break;
622 : 0 : case RTE_FLOW_ACTION_TYPE_MARK:
623 : 0 : action_flags |= MLX5_FLOW_ACTION_MARK;
624 : 0 : *mark = action;
625 : 0 : break;
626 : 0 : case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
627 : 0 : action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
628 : 0 : break;
629 : 0 : case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
630 : 0 : action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
631 : 0 : break;
632 : 0 : case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
633 : 0 : action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
634 : 0 : break;
635 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP:
636 : 0 : action_flags |= MLX5_FLOW_ACTION_JUMP;
637 : 0 : break;
638 : 0 : case RTE_FLOW_ACTION_TYPE_QUEUE:
639 : 0 : action_flags |= MLX5_FLOW_ACTION_QUEUE;
640 : 0 : *qrss = action;
641 : 0 : break;
642 : : case RTE_FLOW_ACTION_TYPE_RSS:
643 : 0 : rss:
644 : 0 : action_flags |= MLX5_FLOW_ACTION_RSS;
645 : 0 : *qrss = action;
646 : 0 : break;
647 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
648 : : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
649 : 0 : action_flags |= MLX5_FLOW_ACTION_ENCAP;
650 : 0 : *encap_idx = action_idx;
651 : 0 : break;
652 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
653 : 0 : action_flags |= MLX5_FLOW_ACTION_ENCAP;
654 : 0 : raw_encap = action->conf;
655 [ # # ]: 0 : if (raw_encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
656 : 0 : *encap_idx = raw_decap_idx != -1 ?
657 [ # # ]: 0 : raw_decap_idx : action_idx;
658 : : break;
659 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
660 : : case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
661 : 0 : action_flags |= MLX5_FLOW_ACTION_DECAP;
662 : 0 : break;
663 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
664 : 0 : action_flags |= MLX5_FLOW_ACTION_DECAP;
665 : : raw_decap_idx = action_idx;
666 : 0 : break;
667 : 0 : case RTE_FLOW_ACTION_TYPE_SEND_TO_KERNEL:
668 : 0 : action_flags |= MLX5_FLOW_ACTION_SEND_TO_KERNEL;
669 : 0 : break;
670 : 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
671 : 0 : action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
672 : 0 : break;
673 : 0 : case RTE_FLOW_ACTION_TYPE_PORT_ID:
674 : : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
675 : 0 : action_flags |= MLX5_FLOW_ACTION_PORT_ID;
676 : 0 : break;
677 : : case RTE_FLOW_ACTION_TYPE_AGE:
678 : 0 : age:
679 : 0 : action_flags |= MLX5_FLOW_ACTION_AGE;
680 : 0 : break;
681 : : case RTE_FLOW_ACTION_TYPE_COUNT:
682 : 0 : count:
683 : 0 : action_flags |= MLX5_FLOW_ACTION_COUNT;
684 : 0 : break;
685 : : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
686 : 0 : ct:
687 : 0 : action_flags |= MLX5_FLOW_ACTION_CT;
688 : 0 : break;
689 : : case RTE_FLOW_ACTION_TYPE_METER_MARK:
690 : 0 : meter:
691 : 0 : action_flags |= MLX5_FLOW_ACTION_METER;
692 : 0 : break;
693 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
694 : 0 : action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
695 : 0 : break;
696 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
697 : 0 : action_flags |= MLX5_FLOW_ACTION_JUMP_TO_TABLE_INDEX;
698 : 0 : break;
699 : 0 : case RTE_FLOW_ACTION_TYPE_SAMPLE:
700 : 0 : action_flags |= MLX5_FLOW_ACTION_SAMPLE;
701 : 0 : break;
702 : : case RTE_FLOW_ACTION_TYPE_VOID:
703 : : case RTE_FLOW_ACTION_TYPE_END:
704 : : break;
705 : 0 : default:
706 : 0 : goto error;
707 : : }
708 : 0 : action_idx++;
709 : : }
710 [ # # ]: 0 : if (*encap_idx == -1)
711 : 0 : *encap_idx = action_idx;
712 : 0 : action_idx++; /* The END action. */
713 : 0 : *act_cnt = action_idx;
714 : 0 : return action_flags;
715 : 0 : error:
716 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
717 : : action, "invalid flow action");
718 : 0 : return 0;
719 : : }
720 : :
721 : : /**
722 : : * Register destination table DR jump action.
723 : : *
724 : : * @param[in] dev
725 : : * Pointer to the rte_eth_dev structure.
726 : : * @param[in] table_attr
727 : : * Pointer to the flow attributes.
728 : : * @param[in] dest_group
729 : : * The destination group ID.
730 : : * @param[out] error
731 : : * Pointer to error structure.
732 : : *
733 : : * @return
734 : : * Table on success, NULL otherwise and rte_errno is set.
735 : : */
736 : : static struct mlx5_hw_jump_action *
737 : 0 : flow_hw_jump_action_register(struct rte_eth_dev *dev,
738 : : const struct mlx5_flow_template_table_cfg *cfg,
739 : : uint32_t dest_group,
740 : : struct rte_flow_error *error)
741 : : {
742 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
743 : 0 : struct rte_flow_attr jattr = cfg->attr.flow_attr;
744 : 0 : uint32_t specialize = cfg->attr.specialize;
745 : : struct mlx5_flow_group *grp;
746 : 0 : struct mlx5_flow_cb_ctx ctx = {
747 : : .dev = dev,
748 : : .error = error,
749 : : .data = &jattr,
750 : : .data2 = &specialize,
751 : : };
752 : : struct mlx5_list_entry *ge;
753 : : uint32_t target_group;
754 : :
755 : 0 : target_group = dest_group;
756 [ # # ]: 0 : if (flow_hw_translate_group(dev, cfg, dest_group, &target_group, error))
757 : : return NULL;
758 : 0 : jattr.group = target_group;
759 : 0 : ge = mlx5_hlist_register(priv->sh->flow_tbls, target_group, &ctx);
760 [ # # ]: 0 : if (!ge)
761 : : return NULL;
762 : : grp = container_of(ge, struct mlx5_flow_group, entry);
763 : 0 : return &grp->jump;
764 : : }
765 : :
766 : : /**
767 : : * Release jump action.
768 : : *
769 : : * @param[in] dev
770 : : * Pointer to the rte_eth_dev structure.
771 : : * @param[in] jump
772 : : * Pointer to the jump action.
773 : : */
774 : :
775 : : static void
776 : : flow_hw_jump_release(struct rte_eth_dev *dev, struct mlx5_hw_jump_action *jump)
777 : : {
778 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
779 : : struct mlx5_flow_group *grp;
780 : :
781 : 0 : grp = container_of(jump, struct mlx5_flow_group, jump);
782 : 0 : mlx5_hlist_unregister(priv->sh->flow_tbls, &grp->entry);
783 : 0 : }
784 : :
785 : : /**
786 : : * Register queue/RSS action.
787 : : *
788 : : * @param[in] dev
789 : : * Pointer to the rte_eth_dev structure.
790 : : * @param[in] hws_flags
791 : : * DR action flags.
792 : : * @param[in] action
793 : : * rte flow action.
794 : : * @param[in] item_flags
795 : : * Item flags for non template rule.
796 : : * @param[in] is_template
797 : : * True if it is a template rule.
798 : : *
799 : : * @return
800 : : * Table on success, NULL otherwise and rte_errno is set.
801 : : */
802 : : static inline struct mlx5_hrxq*
803 : 0 : flow_hw_tir_action_register(struct rte_eth_dev *dev,
804 : : uint32_t hws_flags,
805 : : const struct rte_flow_action *action)
806 : : {
807 : 0 : struct mlx5_flow_rss_desc rss_desc = {
808 : : .hws_flags = hws_flags,
809 : : };
810 : : struct mlx5_hrxq *hrxq;
811 : :
812 [ # # ]: 0 : if (action->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
813 : 0 : const struct rte_flow_action_queue *queue = action->conf;
814 : :
815 : 0 : rss_desc.const_q = &queue->index;
816 : 0 : rss_desc.queue_num = 1;
817 : : } else {
818 : 0 : const struct rte_flow_action_rss *rss = action->conf;
819 : :
820 : 0 : rss_desc.queue_num = rss->queue_num;
821 : 0 : rss_desc.const_q = rss->queue;
822 : 0 : memcpy(rss_desc.key,
823 [ # # ]: 0 : !rss->key ? rss_hash_default_key : rss->key,
824 : : MLX5_RSS_HASH_KEY_LEN);
825 : 0 : rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
826 [ # # ]: 0 : rss_desc.types = !rss->types ? RTE_ETH_RSS_IP : rss->types;
827 : 0 : rss_desc.symmetric_hash_function = MLX5_RSS_IS_SYMM(rss->func);
828 : 0 : flow_hw_hashfields_set(&rss_desc, &rss_desc.hash_fields);
829 : 0 : flow_dv_action_rss_l34_hash_adjust(rss->types,
830 : : &rss_desc.hash_fields);
831 [ # # ]: 0 : if (rss->level > 1) {
832 : 0 : rss_desc.hash_fields |= IBV_RX_HASH_INNER;
833 : 0 : rss_desc.tunnel = 1;
834 : : }
835 : : }
836 : 0 : hrxq = mlx5_hrxq_get(dev, &rss_desc);
837 : 0 : return hrxq;
838 : : }
839 : :
840 : : static __rte_always_inline int
841 : : flow_hw_ct_compile(struct rte_eth_dev *dev,
842 : : uint32_t queue, uint32_t idx,
843 : : struct mlx5dr_rule_action *rule_act)
844 : : {
845 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
846 : : struct mlx5_aso_ct_action *ct;
847 : :
848 : 0 : ct = mlx5_ipool_get(priv->hws_ctpool->cts, idx);
849 [ # # # # : 0 : if (!ct || (!priv->shared_host && mlx5_aso_ct_available(priv->sh, queue, ct)))
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # ]
850 : : return -1;
851 : 0 : rule_act->action = priv->hws_ctpool->dr_action;
852 : 0 : rule_act->aso_ct.offset = ct->offset;
853 : 0 : rule_act->aso_ct.direction = ct->is_original ?
854 : 0 : MLX5DR_ACTION_ASO_CT_DIRECTION_INITIATOR :
855 : : MLX5DR_ACTION_ASO_CT_DIRECTION_RESPONDER;
856 : : return 0;
857 : : }
858 : :
859 : : static void
860 : : flow_hw_template_destroy_reformat_action(struct mlx5_hw_encap_decap_action *encap_decap)
861 : : {
862 [ # # # # ]: 0 : if (encap_decap->action && !encap_decap->multi_pattern)
863 : 0 : mlx5dr_action_destroy(encap_decap->action);
864 : : }
865 : :
866 : : static void
867 : : flow_hw_template_destroy_mhdr_action(struct mlx5_hw_modify_header_action *mhdr)
868 : : {
869 [ # # # # ]: 0 : if (mhdr->action && !mhdr->multi_pattern)
870 : 0 : mlx5dr_action_destroy(mhdr->action);
871 : : }
872 : :
873 : : /**
874 : : * Destroy DR actions created by action template.
875 : : *
876 : : * For DR actions created during table creation's action translate.
877 : : * Need to destroy the DR action when destroying the table.
878 : : *
879 : : * @param[in] dev
880 : : * Pointer to the rte_eth_dev structure.
881 : : * @param[in] acts
882 : : * Pointer to the template HW steering DR actions.
883 : : */
884 : : static void
885 : 0 : __flow_hw_actions_release(struct rte_eth_dev *dev, struct mlx5_hw_actions *acts)
886 : : {
887 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
888 : :
889 [ # # ]: 0 : if (acts->mark)
890 [ # # ]: 0 : if (!(rte_atomic_fetch_sub_explicit(&priv->hws_mark_refcnt, 1,
891 : : rte_memory_order_relaxed) - 1))
892 : 0 : flow_hw_rxq_flag_set(dev, false);
893 : :
894 [ # # ]: 0 : if (acts->jump) {
895 : : struct mlx5_flow_group *grp;
896 : :
897 : 0 : grp = container_of
898 : : (acts->jump, struct mlx5_flow_group, jump);
899 : 0 : mlx5_hlist_unregister(priv->sh->flow_tbls, &grp->entry);
900 : 0 : acts->jump = NULL;
901 : : }
902 [ # # ]: 0 : if (acts->tir) {
903 : 0 : mlx5_hrxq_release(dev, acts->tir->idx);
904 : 0 : acts->tir = NULL;
905 : : }
906 [ # # ]: 0 : if (acts->encap_decap) {
907 : : flow_hw_template_destroy_reformat_action(acts->encap_decap);
908 : 0 : mlx5_free(acts->encap_decap);
909 : 0 : acts->encap_decap = NULL;
910 : : }
911 [ # # ]: 0 : if (acts->push_remove) {
912 [ # # ]: 0 : if (acts->push_remove->action)
913 : 0 : mlx5dr_action_destroy(acts->push_remove->action);
914 : 0 : mlx5_free(acts->push_remove);
915 : 0 : acts->push_remove = NULL;
916 : : }
917 [ # # ]: 0 : if (acts->mhdr) {
918 : : flow_hw_template_destroy_mhdr_action(acts->mhdr);
919 : 0 : mlx5_free(acts->mhdr);
920 : 0 : acts->mhdr = NULL;
921 : : }
922 [ # # ]: 0 : if (mlx5_hws_cnt_id_valid(acts->cnt_id)) {
923 [ # # ]: 0 : mlx5_hws_cnt_shared_put(priv->hws_cpool, &acts->cnt_id);
924 : 0 : acts->cnt_id = 0;
925 : : }
926 [ # # ]: 0 : if (acts->mtr_id) {
927 : 0 : mlx5_ipool_free(priv->hws_mpool->idx_pool, acts->mtr_id);
928 : 0 : acts->mtr_id = 0;
929 : : }
930 : 0 : }
931 : :
932 : : /**
933 : : * Release the action data back into the pool without destroy any action.
934 : : *
935 : : * @param[in] dev
936 : : * Pointer to the rte_eth_dev structure.
937 : : * @param[in] acts
938 : : * Pointer to the template HW steering DR actions.
939 : : */
940 : : static inline void
941 : 0 : __flow_hw_act_data_flush(struct rte_eth_dev *dev, struct mlx5_hw_actions *acts)
942 : : {
943 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
944 : : struct mlx5_action_construct_data *data;
945 : :
946 [ # # ]: 0 : while (!LIST_EMPTY(&acts->act_list)) {
947 : : data = LIST_FIRST(&acts->act_list);
948 [ # # ]: 0 : LIST_REMOVE(data, next);
949 : 0 : mlx5_ipool_free(priv->acts_ipool, data->idx);
950 : : }
951 : 0 : }
952 : :
953 : : /*
954 : : * Destroy DR actions created by action template.
955 : : *
956 : : * For DR actions created during table creation's action translate.
957 : : * Need to destroy the DR action when destroying the table.
958 : : *
959 : : * @param[in] dev
960 : : * Pointer to the rte_eth_dev structure.
961 : : * @param[in] acts
962 : : * Pointer to the template HW steering DR actions.
963 : : */
964 : : static void
965 : 0 : __flow_hw_action_template_destroy(struct rte_eth_dev *dev, struct mlx5_hw_actions *acts)
966 : : {
967 : 0 : __flow_hw_act_data_flush(dev, acts);
968 : 0 : __flow_hw_actions_release(dev, acts);
969 : 0 : }
970 : :
971 : : /**
972 : : * Append dynamic action to the dynamic action list.
973 : : *
974 : : * @param[in] priv
975 : : * Pointer to the port private data structure.
976 : : * @param[in] acts
977 : : * Pointer to the template HW steering DR actions.
978 : : * @param[in] type
979 : : * Action type.
980 : : * @param[in] action_src
981 : : * Offset of source rte flow action.
982 : : * @param[in] action_dst
983 : : * Offset of destination DR action.
984 : : *
985 : : * @return
986 : : * 0 on success, negative value otherwise and rte_errno is set.
987 : : */
988 : : static __rte_always_inline struct mlx5_action_construct_data *
989 : : __flow_hw_act_data_alloc(struct mlx5_priv *priv,
990 : : enum rte_flow_action_type type,
991 : : uint16_t action_src,
992 : : uint16_t action_dst)
993 : : {
994 : : struct mlx5_action_construct_data *act_data;
995 : 0 : uint32_t idx = 0;
996 : :
997 : 0 : act_data = mlx5_ipool_zmalloc(priv->acts_ipool, &idx);
998 [ # # # # : 0 : if (!act_data)
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
999 : : return NULL;
1000 : 0 : act_data->idx = idx;
1001 : 0 : act_data->type = type;
1002 : 0 : act_data->action_src = action_src;
1003 : 0 : act_data->action_dst = action_dst;
1004 : : return act_data;
1005 : : }
1006 : :
1007 : : /**
1008 : : * Append dynamic action to the dynamic action list.
1009 : : *
1010 : : * @param[in] priv
1011 : : * Pointer to the port private data structure.
1012 : : * @param[in] acts
1013 : : * Pointer to the template HW steering DR actions.
1014 : : * @param[in] type
1015 : : * Action type.
1016 : : * @param[in] action_src
1017 : : * Offset of source rte flow action.
1018 : : * @param[in] action_dst
1019 : : * Offset of destination DR action.
1020 : : *
1021 : : * @return
1022 : : * 0 on success, negative value otherwise and rte_errno is set.
1023 : : */
1024 : : static __rte_always_inline int
1025 : : __flow_hw_act_data_general_append(struct mlx5_priv *priv,
1026 : : struct mlx5_hw_actions *acts,
1027 : : enum rte_flow_action_type type,
1028 : : uint16_t action_src,
1029 : : uint16_t action_dst)
1030 : : {
1031 : : struct mlx5_action_construct_data *act_data;
1032 : :
1033 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1034 : : if (!act_data)
1035 : : return -1;
1036 [ # # # # : 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
1037 : : return 0;
1038 : : }
1039 : :
1040 : : static __rte_always_inline int
1041 : : __flow_hw_act_data_indirect_append(struct mlx5_priv *priv,
1042 : : struct mlx5_hw_actions *acts,
1043 : : enum rte_flow_action_type type,
1044 : : enum rte_flow_action_type mask_type,
1045 : : uint16_t action_src,
1046 : : uint16_t action_dst)
1047 : : {
1048 : : struct mlx5_action_construct_data *act_data;
1049 : :
1050 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1051 : : if (!act_data)
1052 : : return -1;
1053 : 0 : act_data->indirect.expected_type = mask_type;
1054 [ # # ]: 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
1055 : : return 0;
1056 : : }
1057 : :
1058 : : static __rte_always_inline int
1059 : : flow_hw_act_data_indirect_list_append(struct mlx5_priv *priv,
1060 : : struct mlx5_hw_actions *acts,
1061 : : enum rte_flow_action_type type,
1062 : : uint16_t action_src, uint16_t action_dst,
1063 : : indirect_list_callback_t cb)
1064 : : {
1065 : : struct mlx5_action_construct_data *act_data;
1066 : :
1067 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1068 : : if (!act_data)
1069 : 0 : return -1;
1070 : 0 : act_data->indirect_list_cb = cb;
1071 [ # # # # : 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
# # ]
1072 : 0 : return 0;
1073 : : }
1074 : : /**
1075 : : * Append dynamic encap action to the dynamic action list.
1076 : : *
1077 : : * @param[in] priv
1078 : : * Pointer to the port private data structure.
1079 : : * @param[in] acts
1080 : : * Pointer to the template HW steering DR actions.
1081 : : * @param[in] type
1082 : : * Action type.
1083 : : * @param[in] action_src
1084 : : * Offset of source rte flow action.
1085 : : * @param[in] action_dst
1086 : : * Offset of destination DR action.
1087 : : * @param[in] len
1088 : : * Length of the data to be updated.
1089 : : *
1090 : : * @return
1091 : : * 0 on success, negative value otherwise and rte_errno is set.
1092 : : */
1093 : : static __rte_always_inline int
1094 : : __flow_hw_act_data_encap_append(struct mlx5_priv *priv,
1095 : : struct mlx5_hw_actions *acts,
1096 : : enum rte_flow_action_type type,
1097 : : uint16_t action_src,
1098 : : uint16_t action_dst,
1099 : : uint16_t len)
1100 : : {
1101 : : struct mlx5_action_construct_data *act_data;
1102 : :
1103 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1104 : : if (!act_data)
1105 : : return -1;
1106 : 0 : act_data->encap.len = len;
1107 [ # # ]: 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
1108 : : return 0;
1109 : : }
1110 : :
1111 : : /**
1112 : : * Append dynamic push action to the dynamic action list.
1113 : : *
1114 : : * @param[in] dev
1115 : : * Pointer to the port.
1116 : : * @param[in] acts
1117 : : * Pointer to the template HW steering DR actions.
1118 : : * @param[in] type
1119 : : * Action type.
1120 : : * @param[in] action_src
1121 : : * Offset of source rte flow action.
1122 : : * @param[in] action_dst
1123 : : * Offset of destination DR action.
1124 : : * @param[in] len
1125 : : * Length of the data to be updated.
1126 : : *
1127 : : * @return
1128 : : * Data pointer on success, NULL otherwise and rte_errno is set.
1129 : : */
1130 : : static __rte_always_inline void *
1131 : : __flow_hw_act_data_push_append(struct rte_eth_dev *dev,
1132 : : struct mlx5_hw_actions *acts,
1133 : : enum rte_flow_action_type type,
1134 : : uint16_t action_src,
1135 : : uint16_t action_dst,
1136 : : uint16_t len)
1137 : : {
1138 : : struct mlx5_action_construct_data *act_data;
1139 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1140 : :
1141 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1142 : : if (!act_data)
1143 : : return NULL;
1144 : 0 : act_data->ipv6_ext.len = len;
1145 [ # # ]: 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
1146 : : return act_data;
1147 : : }
1148 : :
1149 : : static __rte_always_inline int
1150 : : __flow_hw_act_data_hdr_modify_append(struct mlx5_priv *priv,
1151 : : struct mlx5_hw_actions *acts,
1152 : : enum rte_flow_action_type type,
1153 : : uint16_t action_src,
1154 : : uint16_t action_dst,
1155 : : const struct rte_flow_action_modify_field *mf,
1156 : : uint16_t mhdr_cmds_off,
1157 : : uint16_t mhdr_cmds_end,
1158 : : bool shared,
1159 : : struct field_modify_info *field,
1160 : : struct field_modify_info *dcopy,
1161 : : uint32_t *mask)
1162 : : {
1163 : : struct mlx5_action_construct_data *act_data;
1164 : :
1165 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1166 : : if (!act_data)
1167 : : return -1;
1168 : 0 : act_data->modify_header.action = *mf;
1169 : 0 : act_data->modify_header.mhdr_cmds_off = mhdr_cmds_off;
1170 : 0 : act_data->modify_header.mhdr_cmds_end = mhdr_cmds_end;
1171 : 0 : act_data->modify_header.shared = shared;
1172 [ # # ]: 0 : rte_memcpy(act_data->modify_header.field, field,
1173 : : sizeof(*field) * MLX5_ACT_MAX_MOD_FIELDS);
1174 [ # # ]: 0 : rte_memcpy(act_data->modify_header.dcopy, dcopy,
1175 : : sizeof(*dcopy) * MLX5_ACT_MAX_MOD_FIELDS);
1176 [ # # ]: 0 : rte_memcpy(act_data->modify_header.mask, mask,
1177 : : sizeof(*mask) * MLX5_ACT_MAX_MOD_FIELDS);
1178 [ # # ]: 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
1179 : : return 0;
1180 : : }
1181 : :
1182 : : /**
1183 : : * Append shared RSS action to the dynamic action list.
1184 : : *
1185 : : * @param[in] priv
1186 : : * Pointer to the port private data structure.
1187 : : * @param[in] acts
1188 : : * Pointer to the template HW steering DR actions.
1189 : : * @param[in] type
1190 : : * Action type.
1191 : : * @param[in] action_src
1192 : : * Offset of source rte flow action.
1193 : : * @param[in] action_dst
1194 : : * Offset of destination DR action.
1195 : : * @param[in] idx
1196 : : * Shared RSS index.
1197 : : * @param[in] rss
1198 : : * Pointer to the shared RSS info.
1199 : : *
1200 : : * @return
1201 : : * 0 on success, negative value otherwise and rte_errno is set.
1202 : : */
1203 : : static __rte_always_inline int
1204 : : __flow_hw_act_data_shared_rss_append(struct mlx5_priv *priv,
1205 : : struct mlx5_hw_actions *acts,
1206 : : enum rte_flow_action_type type,
1207 : : uint16_t action_src,
1208 : : uint16_t action_dst,
1209 : : uint32_t idx,
1210 : : struct mlx5_shared_action_rss *rss)
1211 : : {
1212 : : struct mlx5_action_construct_data *act_data;
1213 : :
1214 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1215 : : if (!act_data)
1216 : : return -1;
1217 : 0 : act_data->shared_rss.level = rss->origin.level;
1218 [ # # ]: 0 : act_data->shared_rss.types = !rss->origin.types ? RTE_ETH_RSS_IP :
1219 : : rss->origin.types;
1220 : 0 : act_data->shared_rss.idx = idx;
1221 : 0 : act_data->shared_rss.symmetric_hash_function =
1222 : 0 : MLX5_RSS_IS_SYMM(rss->origin.func);
1223 [ # # ]: 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
1224 : : return 0;
1225 : : }
1226 : :
1227 : : /**
1228 : : * Append shared counter action to the dynamic action list.
1229 : : *
1230 : : * @param[in] priv
1231 : : * Pointer to the port private data structure.
1232 : : * @param[in] acts
1233 : : * Pointer to the template HW steering DR actions.
1234 : : * @param[in] type
1235 : : * Action type.
1236 : : * @param[in] action_src
1237 : : * Offset of source rte flow action.
1238 : : * @param[in] action_dst
1239 : : * Offset of destination DR action.
1240 : : * @param[in] cnt_id
1241 : : * Shared counter id.
1242 : : *
1243 : : * @return
1244 : : * 0 on success, negative value otherwise and rte_errno is set.
1245 : : */
1246 : : static __rte_always_inline int
1247 : : __flow_hw_act_data_shared_cnt_append(struct mlx5_priv *priv,
1248 : : struct mlx5_hw_actions *acts,
1249 : : enum rte_flow_action_type type,
1250 : : uint16_t action_src,
1251 : : uint16_t action_dst,
1252 : : cnt_id_t cnt_id)
1253 : : {
1254 : : struct mlx5_action_construct_data *act_data;
1255 : :
1256 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1257 : : if (!act_data)
1258 : : return -1;
1259 : : act_data->type = type;
1260 : 0 : act_data->shared_counter.id = cnt_id;
1261 [ # # ]: 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
1262 : : return 0;
1263 : : }
1264 : :
1265 : : /**
1266 : : * Append shared meter_mark action to the dynamic action list.
1267 : : *
1268 : : * @param[in] priv
1269 : : * Pointer to the port private data structure.
1270 : : * @param[in] acts
1271 : : * Pointer to the template HW steering DR actions.
1272 : : * @param[in] type
1273 : : * Action type.
1274 : : * @param[in] action_src
1275 : : * Offset of source rte flow action.
1276 : : * @param[in] action_dst
1277 : : * Offset of destination DR action.
1278 : : * @param[in] mtr_id
1279 : : * Shared meter id.
1280 : : *
1281 : : * @return
1282 : : * 0 on success, negative value otherwise and rte_errno is set.
1283 : : */
1284 : : static __rte_always_inline int
1285 : : __flow_hw_act_data_shared_mtr_append(struct mlx5_priv *priv,
1286 : : struct mlx5_hw_actions *acts,
1287 : : enum rte_flow_action_type type,
1288 : : uint16_t action_src,
1289 : : uint16_t action_dst,
1290 : : cnt_id_t mtr_id)
1291 : : { struct mlx5_action_construct_data *act_data;
1292 : :
1293 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1294 : : if (!act_data)
1295 : : return -1;
1296 : : act_data->type = type;
1297 : 0 : act_data->shared_meter.id = mtr_id;
1298 [ # # ]: 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
1299 : : return 0;
1300 : : }
1301 : :
1302 : : /**
1303 : : * Translate shared indirect action.
1304 : : *
1305 : : * @param[in] dev
1306 : : * Pointer to the rte_eth_dev data structure.
1307 : : * @param[in] action
1308 : : * Pointer to the shared indirect rte_flow action.
1309 : : * @param[in] acts
1310 : : * Pointer to the template HW steering DR actions.
1311 : : * @param[in] action_src
1312 : : * Offset of source rte flow action.
1313 : : * @param[in] action_dst
1314 : : * Offset of destination DR action.
1315 : : *
1316 : : * @return
1317 : : * 0 on success, negative value otherwise and rte_errno is set.
1318 : : */
1319 : : static __rte_always_inline int
1320 : : flow_hw_shared_action_translate(struct rte_eth_dev *dev,
1321 : : const struct rte_flow_action *action,
1322 : : struct mlx5_hw_actions *acts,
1323 : : uint16_t action_src,
1324 : : uint16_t action_dst)
1325 : : {
1326 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1327 : : struct mlx5_shared_action_rss *shared_rss;
1328 : 0 : uint32_t act_idx = (uint32_t)(uintptr_t)action->conf;
1329 : 0 : uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
1330 : 0 : uint32_t idx = act_idx &
1331 : : ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
1332 : :
1333 : 0 : switch (type) {
1334 : 0 : case MLX5_INDIRECT_ACTION_TYPE_RSS:
1335 : 0 : shared_rss = mlx5_ipool_get
1336 : 0 : (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
1337 [ # # ]: 0 : if (!shared_rss || __flow_hw_act_data_shared_rss_append
1338 : : (priv, acts,
1339 : : (enum rte_flow_action_type)MLX5_RTE_FLOW_ACTION_TYPE_RSS,
1340 : : action_src, action_dst, idx, shared_rss)) {
1341 : 0 : DRV_LOG(WARNING, "Indirect RSS action index %d translate failed", act_idx);
1342 : : return -1;
1343 : : }
1344 : : break;
1345 : 0 : case MLX5_INDIRECT_ACTION_TYPE_COUNT:
1346 : : if (__flow_hw_act_data_shared_cnt_append(priv, acts,
1347 : : (enum rte_flow_action_type)
1348 : : MLX5_RTE_FLOW_ACTION_TYPE_COUNT,
1349 : : action_src, action_dst, act_idx)) {
1350 : 0 : DRV_LOG(WARNING, "Indirect count action translate failed");
1351 : : return -1;
1352 : : }
1353 : : break;
1354 : : case MLX5_INDIRECT_ACTION_TYPE_AGE:
1355 : : /* Not supported, prevent by validate function. */
1356 : : MLX5_ASSERT(0);
1357 : : break;
1358 : 0 : case MLX5_INDIRECT_ACTION_TYPE_CT:
1359 : : if (flow_hw_ct_compile(dev, MLX5_HW_INV_QUEUE,
1360 : : idx, &acts->rule_acts[action_dst])) {
1361 : 0 : DRV_LOG(WARNING, "Indirect CT action translate failed");
1362 : : return -1;
1363 : : }
1364 : : break;
1365 : 0 : case MLX5_INDIRECT_ACTION_TYPE_METER_MARK:
1366 : : if (__flow_hw_act_data_shared_mtr_append(priv, acts,
1367 : : (enum rte_flow_action_type)
1368 : : MLX5_RTE_FLOW_ACTION_TYPE_METER_MARK,
1369 : : action_src, action_dst, idx)) {
1370 : 0 : DRV_LOG(WARNING, "Indirect meter mark action translate failed");
1371 : : return -1;
1372 : : }
1373 : : break;
1374 : 0 : case MLX5_INDIRECT_ACTION_TYPE_QUOTA:
1375 : : flow_hw_construct_quota(priv, &acts->rule_acts[action_dst], idx);
1376 : : break;
1377 : 0 : default:
1378 : 0 : DRV_LOG(WARNING, "Unsupported shared action type:%d", type);
1379 : : break;
1380 : : }
1381 : : return 0;
1382 : : }
1383 : :
1384 : : static __rte_always_inline bool
1385 : : flow_hw_action_modify_field_is_shared(const struct rte_flow_action *action,
1386 : : const struct rte_flow_action *mask)
1387 : : {
1388 : : const struct rte_flow_action_modify_field *v = action->conf;
1389 : 0 : const struct rte_flow_action_modify_field *m = mask->conf;
1390 : :
1391 : 0 : if (v->src.field == RTE_FLOW_FIELD_VALUE) {
1392 : : uint32_t j;
1393 : :
1394 [ # # ]: 0 : for (j = 0; j < RTE_DIM(m->src.value); ++j) {
1395 : : /*
1396 : : * Immediate value is considered to be masked
1397 : : * (and thus shared by all flow rules), if mask
1398 : : * is non-zero. Partial mask over immediate value
1399 : : * is not allowed.
1400 : : */
1401 [ # # ]: 0 : if (m->src.value[j])
1402 : : return true;
1403 : : }
1404 : : return false;
1405 : : }
1406 [ # # ]: 0 : if (v->src.field == RTE_FLOW_FIELD_POINTER)
1407 : 0 : return m->src.pvalue != NULL;
1408 : : /*
1409 : : * Source field types other than VALUE and
1410 : : * POINTER are always shared.
1411 : : */
1412 : : return true;
1413 : : }
1414 : :
1415 : : static __rte_always_inline bool
1416 : : flow_hw_should_insert_nop(const struct mlx5_hw_modify_header_action *mhdr,
1417 : : const struct mlx5_modification_cmd *cmd,
1418 : : const struct rte_flow_attr *attr)
1419 : : {
1420 : : struct mlx5_modification_cmd last_cmd = { { 0 } };
1421 : : struct mlx5_modification_cmd new_cmd = { { 0 } };
1422 : 0 : const uint32_t cmds_num = mhdr->mhdr_cmds_num;
1423 : : unsigned int last_type;
1424 : : bool should_insert = false;
1425 : :
1426 : : /*
1427 : : * Modify header action list does not require NOPs in root table,
1428 : : * because different type of underlying object is used:
1429 : : * - in root table - MODIFY_HEADER_CONTEXT (does not require NOPs),
1430 : : * - in non-root - either inline modify action or based on Modify Header Pattern
1431 : : * (which requires NOPs).
1432 : : */
1433 [ # # # # ]: 0 : if (attr->group == 0)
1434 : : return false;
1435 [ # # # # ]: 0 : if (cmds_num == 0)
1436 : : return false;
1437 : 0 : last_cmd = *(&mhdr->mhdr_cmds[cmds_num - 1]);
1438 [ # # # # ]: 0 : last_cmd.data0 = rte_be_to_cpu_32(last_cmd.data0);
1439 [ # # # # ]: 0 : last_cmd.data1 = rte_be_to_cpu_32(last_cmd.data1);
1440 : 0 : last_type = last_cmd.action_type;
1441 : 0 : new_cmd = *cmd;
1442 [ # # # # ]: 0 : new_cmd.data0 = rte_be_to_cpu_32(new_cmd.data0);
1443 [ # # # # ]: 0 : new_cmd.data1 = rte_be_to_cpu_32(new_cmd.data1);
1444 [ # # # # : 0 : switch (new_cmd.action_type) {
# # ]
1445 : 0 : case MLX5_MODIFICATION_TYPE_SET:
1446 : : case MLX5_MODIFICATION_TYPE_ADD:
1447 [ # # # # ]: 0 : if (last_type == MLX5_MODIFICATION_TYPE_SET ||
1448 : : last_type == MLX5_MODIFICATION_TYPE_ADD)
1449 : 0 : should_insert = new_cmd.field == last_cmd.field;
1450 : 0 : else if (last_type == MLX5_MODIFICATION_TYPE_COPY ||
1451 [ # # # # ]: 0 : last_type == MLX5_MODIFICATION_TYPE_ADD_FIELD)
1452 : 0 : should_insert = new_cmd.field == last_cmd.dst_field;
1453 : : else if (last_type == MLX5_MODIFICATION_TYPE_NOP)
1454 : : should_insert = false;
1455 : : else
1456 : : MLX5_ASSERT(false); /* Other types are not supported. */
1457 : : break;
1458 : 0 : case MLX5_MODIFICATION_TYPE_COPY:
1459 : : case MLX5_MODIFICATION_TYPE_ADD_FIELD:
1460 [ # # # # ]: 0 : if (last_type == MLX5_MODIFICATION_TYPE_SET ||
1461 : : last_type == MLX5_MODIFICATION_TYPE_ADD)
1462 [ # # # # ]: 0 : should_insert = (new_cmd.field == last_cmd.field ||
1463 [ # # # # ]: 0 : new_cmd.dst_field == last_cmd.field);
1464 : 0 : else if (last_type == MLX5_MODIFICATION_TYPE_COPY ||
1465 [ # # # # ]: 0 : last_type == MLX5_MODIFICATION_TYPE_ADD_FIELD)
1466 [ # # # # ]: 0 : should_insert = (new_cmd.field == last_cmd.dst_field ||
1467 [ # # # # ]: 0 : new_cmd.dst_field == last_cmd.dst_field);
1468 : : else if (last_type == MLX5_MODIFICATION_TYPE_NOP)
1469 : : should_insert = false;
1470 : : else
1471 : : MLX5_ASSERT(false); /* Other types are not supported. */
1472 : : break;
1473 : : default:
1474 : : /* Other action types should be rejected on AT validation. */
1475 : : MLX5_ASSERT(false);
1476 : : break;
1477 : : }
1478 : : return should_insert;
1479 : : }
1480 : :
1481 : : static __rte_always_inline int
1482 : : flow_hw_mhdr_cmd_nop_append(struct mlx5_hw_modify_header_action *mhdr)
1483 : : {
1484 : : struct mlx5_modification_cmd *nop;
1485 : : uint32_t num = mhdr->mhdr_cmds_num;
1486 : :
1487 [ # # # # ]: 0 : if (num + 1 >= MLX5_MHDR_MAX_CMD)
1488 : : return -ENOMEM;
1489 : 0 : nop = mhdr->mhdr_cmds + num;
1490 : : nop->data0 = 0;
1491 : : nop->action_type = MLX5_MODIFICATION_TYPE_NOP;
1492 : 0 : nop->data0 = rte_cpu_to_be_32(nop->data0);
1493 : 0 : nop->data1 = 0;
1494 : 0 : mhdr->mhdr_cmds_num = num + 1;
1495 : : return 0;
1496 : : }
1497 : :
1498 : : static __rte_always_inline int
1499 : : flow_hw_mhdr_cmd_append(struct mlx5_hw_modify_header_action *mhdr,
1500 : : struct mlx5_modification_cmd *cmd)
1501 : : {
1502 : 0 : uint32_t num = mhdr->mhdr_cmds_num;
1503 : :
1504 [ # # ]: 0 : if (num + 1 >= MLX5_MHDR_MAX_CMD)
1505 : : return -ENOMEM;
1506 : 0 : mhdr->mhdr_cmds[num] = *cmd;
1507 : 0 : mhdr->mhdr_cmds_num = num + 1;
1508 : : return 0;
1509 : : }
1510 : :
1511 : : static __rte_always_inline int
1512 : : flow_hw_converted_mhdr_cmds_append(struct mlx5_hw_modify_header_action *mhdr,
1513 : : struct mlx5_flow_dv_modify_hdr_resource *resource,
1514 : : const struct rte_flow_attr *attr)
1515 : : {
1516 : : uint32_t idx;
1517 : : int ret;
1518 : :
1519 [ # # ]: 0 : for (idx = 0; idx < resource->actions_num; ++idx) {
1520 : : struct mlx5_modification_cmd *src = &resource->actions[idx];
1521 : :
1522 [ # # ]: 0 : if (flow_hw_should_insert_nop(mhdr, src, attr)) {
1523 : : ret = flow_hw_mhdr_cmd_nop_append(mhdr);
1524 : : if (ret)
1525 : : return ret;
1526 : : }
1527 : : ret = flow_hw_mhdr_cmd_append(mhdr, src);
1528 : : if (ret)
1529 : : return ret;
1530 : : }
1531 : : return 0;
1532 : : }
1533 : :
1534 : : static __rte_always_inline void
1535 : : flow_hw_modify_field_init(struct mlx5_hw_modify_header_action *mhdr,
1536 : : struct rte_flow_actions_template *at)
1537 : : {
1538 : : memset(mhdr, 0, sizeof(*mhdr));
1539 : : /* Modify header action without any commands is shared by default. */
1540 : 0 : mhdr->shared = true;
1541 : 0 : mhdr->pos = at->mhdr_off;
1542 : : }
1543 : :
1544 : : static __rte_always_inline int
1545 : : flow_hw_modify_field_compile(struct rte_eth_dev *dev,
1546 : : const struct rte_flow_attr *attr,
1547 : : const struct rte_flow_action *action, /* Current action from AT. */
1548 : : const struct rte_flow_action *action_mask, /* Current mask from AT. */
1549 : : struct mlx5_hw_actions *acts,
1550 : : struct mlx5_hw_modify_header_action *mhdr,
1551 : : uint16_t src_pos,
1552 : : struct rte_flow_error *error)
1553 : : {
1554 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1555 : 0 : const struct rte_flow_action_modify_field *conf = action->conf;
1556 : : union {
1557 : : struct mlx5_flow_dv_modify_hdr_resource resource;
1558 : : uint8_t data[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
1559 : : sizeof(struct mlx5_modification_cmd) * MLX5_MHDR_MAX_CMD];
1560 : : } dummy;
1561 : : struct mlx5_flow_dv_modify_hdr_resource *resource;
1562 : 0 : struct rte_flow_item item = {
1563 : : .spec = NULL,
1564 : : .mask = NULL
1565 : : };
1566 : 0 : struct field_modify_info field[MLX5_ACT_MAX_MOD_FIELDS] = {
1567 : : {0, 0, MLX5_MODI_OUT_NONE} };
1568 : 0 : struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {
1569 : : {0, 0, MLX5_MODI_OUT_NONE} };
1570 : 0 : uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = { 0 };
1571 : 0 : uint32_t type, value = 0;
1572 : : uint16_t cmds_start, cmds_end;
1573 : : bool shared;
1574 : : int ret;
1575 : :
1576 : : /*
1577 : : * Modify header action is shared if previous modify_field actions
1578 : : * are shared and currently compiled action is shared.
1579 : : */
1580 : : shared = flow_hw_action_modify_field_is_shared(action, action_mask);
1581 : 0 : mhdr->shared &= shared;
1582 [ # # ]: 0 : if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
1583 : : conf->src.field == RTE_FLOW_FIELD_VALUE) {
1584 [ # # ]: 0 : type = conf->operation == RTE_FLOW_MODIFY_SET ? MLX5_MODIFICATION_TYPE_SET :
1585 : : MLX5_MODIFICATION_TYPE_ADD;
1586 : : /* For SET/ADD fill the destination field (field) first. */
1587 : 0 : mlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,
1588 : 0 : conf->width, dev,
1589 : : attr, error);
1590 : 0 : item.spec = conf->src.field == RTE_FLOW_FIELD_POINTER ?
1591 [ # # ]: 0 : (void *)(uintptr_t)conf->src.pvalue :
1592 : : (void *)(uintptr_t)&conf->src.value;
1593 [ # # ]: 0 : if (conf->dst.field == RTE_FLOW_FIELD_META ||
1594 [ # # ]: 0 : conf->dst.field == RTE_FLOW_FIELD_TAG ||
1595 [ # # ]: 0 : conf->dst.field == RTE_FLOW_FIELD_METER_COLOR ||
1596 : 0 : conf->dst.field == (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG) {
1597 : : uint8_t tag_index = flow_tag_index_get(&conf->dst);
1598 : :
1599 : 0 : value = *(const unaligned_uint32_t *)item.spec;
1600 [ # # # # ]: 0 : if (conf->dst.field == RTE_FLOW_FIELD_TAG &&
1601 : : tag_index == RTE_PMD_MLX5_LINEAR_HASH_TAG_INDEX)
1602 [ # # ]: 0 : value = rte_cpu_to_be_32(value << 16);
1603 : : else
1604 [ # # ]: 0 : value = rte_cpu_to_be_32(value);
1605 : 0 : item.spec = &value;
1606 [ # # ]: 0 : } else if (conf->dst.field == RTE_FLOW_FIELD_GTP_PSC_QFI ||
1607 : : conf->dst.field == RTE_FLOW_FIELD_GENEVE_OPT_TYPE) {
1608 : : /*
1609 : : * Both QFI and Geneve option type are passed as an uint8_t integer,
1610 : : * but it is accessed through a 2nd least significant byte of a 32-bit
1611 : : * field in modify header command.
1612 : : */
1613 : 0 : value = *(const uint8_t *)item.spec;
1614 [ # # ]: 0 : value = rte_cpu_to_be_32(value << 8);
1615 : 0 : item.spec = &value;
1616 [ # # ]: 0 : } else if (conf->dst.field == RTE_FLOW_FIELD_VXLAN_LAST_RSVD) {
1617 : 0 : value = *(const uint8_t *)item.spec << 24;
1618 [ # # ]: 0 : value = rte_cpu_to_be_32(value);
1619 : 0 : item.spec = &value;
1620 : : }
1621 : : } else {
1622 : 0 : type = conf->operation == RTE_FLOW_MODIFY_SET ?
1623 [ # # ]: 0 : MLX5_MODIFICATION_TYPE_COPY : MLX5_MODIFICATION_TYPE_ADD_FIELD;
1624 : : /* For COPY fill the destination field (dcopy) without mask. */
1625 : 0 : mlx5_flow_field_id_to_modify_info(&conf->dst, dcopy, NULL,
1626 : 0 : conf->width, dev,
1627 : : attr, error);
1628 : : /* Then construct the source field (field) with mask. */
1629 : 0 : mlx5_flow_field_id_to_modify_info(&conf->src, field, mask,
1630 : 0 : conf->width, dev,
1631 : : attr, error);
1632 : : }
1633 : 0 : item.mask = &mask;
1634 : : memset(&dummy, 0, sizeof(dummy));
1635 : : resource = &dummy.resource;
1636 : 0 : ret = flow_dv_convert_modify_action(&item, field, dcopy, resource, type, error);
1637 [ # # ]: 0 : if (ret)
1638 : : return ret;
1639 : : MLX5_ASSERT(resource->actions_num > 0);
1640 : : /*
1641 : : * If previous modify field action collide with this one, then insert NOP command.
1642 : : * This NOP command will not be a part of action's command range used to update commands
1643 : : * on rule creation.
1644 : : */
1645 [ # # ]: 0 : if (flow_hw_should_insert_nop(mhdr, &resource->actions[0], attr)) {
1646 : : ret = flow_hw_mhdr_cmd_nop_append(mhdr);
1647 : : if (ret)
1648 : 0 : return rte_flow_error_set(error, ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1649 : : NULL, "too many modify field operations specified");
1650 : : }
1651 : 0 : cmds_start = mhdr->mhdr_cmds_num;
1652 : : ret = flow_hw_converted_mhdr_cmds_append(mhdr, resource, attr);
1653 [ # # ]: 0 : if (ret)
1654 : 0 : return rte_flow_error_set(error, ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1655 : : NULL, "too many modify field operations specified");
1656 : :
1657 : 0 : cmds_end = mhdr->mhdr_cmds_num;
1658 [ # # ]: 0 : if (shared)
1659 : : return 0;
1660 : : ret = __flow_hw_act_data_hdr_modify_append(priv, acts, RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
1661 : 0 : src_pos, mhdr->pos, conf,
1662 : : cmds_start, cmds_end, shared,
1663 : : field, dcopy, mask);
1664 : : if (ret)
1665 : 0 : return rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1666 : : NULL, "not enough memory to store modify field metadata");
1667 : : return 0;
1668 : : }
1669 : :
1670 : : static uint32_t
1671 : 0 : flow_hw_count_nop_modify_field(struct mlx5_hw_modify_header_action *mhdr)
1672 : : {
1673 : : uint32_t i;
1674 : : uint32_t nops = 0;
1675 : :
1676 [ # # ]: 0 : for (i = 0; i < mhdr->mhdr_cmds_num; ++i) {
1677 : 0 : struct mlx5_modification_cmd cmd = mhdr->mhdr_cmds[i];
1678 : :
1679 [ # # ]: 0 : cmd.data0 = rte_be_to_cpu_32(cmd.data0);
1680 [ # # ]: 0 : if (cmd.action_type == MLX5_MODIFICATION_TYPE_NOP)
1681 : 0 : ++nops;
1682 : : }
1683 : 0 : return nops;
1684 : : }
1685 : :
1686 : : static int
1687 : 0 : flow_hw_validate_compiled_modify_field(struct rte_eth_dev *dev,
1688 : : const struct mlx5_flow_template_table_cfg *cfg,
1689 : : struct mlx5_hw_modify_header_action *mhdr,
1690 : : struct rte_flow_error *error)
1691 : : {
1692 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1693 : 0 : struct mlx5_hca_attr *hca_attr = &priv->sh->cdev->config.hca_attr;
1694 : :
1695 : : /*
1696 : : * Header modify pattern length limitation is only valid for HWS groups, i.e. groups > 0.
1697 : : * In group 0, MODIFY_FIELD actions are handled with header modify actions
1698 : : * managed by rdma-core.
1699 : : */
1700 [ # # ]: 0 : if (cfg->attr.flow_attr.group != 0 &&
1701 [ # # ]: 0 : mhdr->mhdr_cmds_num > hca_attr->max_header_modify_pattern_length) {
1702 : 0 : uint32_t nops = flow_hw_count_nop_modify_field(mhdr);
1703 : :
1704 : 0 : DRV_LOG(ERR, "Too many modify header commands generated from "
1705 : : "MODIFY_FIELD actions. "
1706 : : "Generated HW commands = %u (amount of NOP commands = %u). "
1707 : : "Maximum supported = %u.",
1708 : : mhdr->mhdr_cmds_num, nops,
1709 : : hca_attr->max_header_modify_pattern_length);
1710 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1711 : : "Number of MODIFY_FIELD actions exceeds maximum "
1712 : : "supported limit of actions");
1713 : : }
1714 : : return 0;
1715 : : }
1716 : :
1717 : : static int
1718 : 0 : flow_hw_represented_port_compile(struct rte_eth_dev *dev,
1719 : : const struct rte_flow_attr *attr,
1720 : : const struct rte_flow_action *action,
1721 : : const struct rte_flow_action *action_mask,
1722 : : struct mlx5_hw_actions *acts,
1723 : : uint16_t action_src, uint16_t action_dst,
1724 : : struct rte_flow_error *error)
1725 : : {
1726 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1727 : 0 : const struct rte_flow_action_ethdev *v = action->conf;
1728 : 0 : const struct rte_flow_action_ethdev *m = action_mask->conf;
1729 : : int ret;
1730 : :
1731 [ # # ]: 0 : if (!attr->group)
1732 : 0 : return rte_flow_error_set(error, EINVAL,
1733 : : RTE_FLOW_ERROR_TYPE_ATTR, NULL,
1734 : : "represented_port action cannot"
1735 : : " be used on group 0");
1736 [ # # ]: 0 : if (!attr->transfer)
1737 : 0 : return rte_flow_error_set(error, EINVAL,
1738 : : RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER,
1739 : : NULL,
1740 : : "represented_port action requires"
1741 : : " transfer attribute");
1742 [ # # ]: 0 : if (attr->ingress || attr->egress)
1743 : 0 : return rte_flow_error_set(error, EINVAL,
1744 : : RTE_FLOW_ERROR_TYPE_ATTR, NULL,
1745 : : "represented_port action cannot"
1746 : : " be used with direction attributes");
1747 [ # # ]: 0 : if (!priv->master)
1748 : 0 : return rte_flow_error_set(error, EINVAL,
1749 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1750 : : "represented_port action must"
1751 : : " be used on proxy port");
1752 [ # # # # ]: 0 : if (m && !!m->port_id) {
1753 : : struct mlx5_priv *port_priv;
1754 : :
1755 [ # # ]: 0 : if (!v)
1756 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
1757 : : action, "port index was not provided");
1758 : 0 : port_priv = mlx5_port_to_eswitch_info(v->port_id, false);
1759 [ # # ]: 0 : if (port_priv == NULL)
1760 : 0 : return rte_flow_error_set
1761 : : (error, EINVAL,
1762 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1763 : : "port does not exist or unable to"
1764 : : " obtain E-Switch info for port");
1765 : : MLX5_ASSERT(priv->hw_vport != NULL);
1766 [ # # ]: 0 : if (priv->hw_vport[v->port_id]) {
1767 : 0 : acts->rule_acts[action_dst].action =
1768 : : priv->hw_vport[v->port_id];
1769 : : } else {
1770 : 0 : return rte_flow_error_set
1771 : : (error, EINVAL,
1772 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1773 : : "cannot use represented_port action"
1774 : : " with this port");
1775 : : }
1776 : : } else {
1777 : : ret = __flow_hw_act_data_general_append
1778 : 0 : (priv, acts, action->type,
1779 : : action_src, action_dst);
1780 : : if (ret)
1781 : 0 : return rte_flow_error_set
1782 : : (error, ENOMEM,
1783 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1784 : : "not enough memory to store"
1785 : : " vport action");
1786 : : }
1787 : : return 0;
1788 : : }
1789 : :
1790 : : static __rte_always_inline int
1791 : : flow_hw_cnt_compile(struct rte_eth_dev *dev, uint32_t start_pos,
1792 : : struct mlx5_hw_actions *acts)
1793 : : {
1794 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1795 : : uint32_t pos = start_pos;
1796 : : cnt_id_t cnt_id;
1797 : : int ret;
1798 : :
1799 : 0 : ret = mlx5_hws_cnt_shared_get(priv->hws_cpool, &cnt_id, 0);
1800 : : if (ret != 0)
1801 : : return ret;
1802 : 0 : ret = mlx5_hws_cnt_pool_get_action_offset
1803 : : (priv->hws_cpool,
1804 : : cnt_id,
1805 : : &acts->rule_acts[pos].action,
1806 : : &acts->rule_acts[pos].counter.offset);
1807 : : if (ret != 0)
1808 : : return ret;
1809 : 0 : acts->cnt_id = cnt_id;
1810 : : return 0;
1811 : : }
1812 : :
1813 : : static __rte_always_inline bool
1814 : : is_of_vlan_pcp_present(const struct rte_flow_action *actions)
1815 : : {
1816 : : /*
1817 : : * Order of RTE VLAN push actions is
1818 : : * OF_PUSH_VLAN / OF_SET_VLAN_VID [ / OF_SET_VLAN_PCP ]
1819 : : */
1820 : 0 : return actions[MLX5_HW_VLAN_PUSH_PCP_IDX].type ==
1821 : : RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP;
1822 : : }
1823 : :
1824 : : static __rte_always_inline bool
1825 : : is_template_masked_push_vlan(const struct rte_flow_action_of_push_vlan *mask)
1826 : : {
1827 : : /*
1828 : : * In masked push VLAN template all RTE push actions are masked.
1829 : : */
1830 [ # # ]: 0 : return mask && mask->ethertype != 0;
1831 : : }
1832 : :
1833 : 0 : static rte_be32_t vlan_hdr_to_be32(const struct rte_flow_action *actions)
1834 : : {
1835 : : /*
1836 : : * OpenFlow Switch Specification defines 801.1q VID as 12+1 bits.
1837 : : */
1838 : : rte_be32_t type, vid, pcp;
1839 : : #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
1840 : : rte_be32_t vid_lo, vid_hi;
1841 : : #endif
1842 : :
1843 : 0 : type = ((const struct rte_flow_action_of_push_vlan *)
1844 : 0 : actions[MLX5_HW_VLAN_PUSH_TYPE_IDX].conf)->ethertype;
1845 : 0 : vid = ((const struct rte_flow_action_of_set_vlan_vid *)
1846 : 0 : actions[MLX5_HW_VLAN_PUSH_VID_IDX].conf)->vlan_vid;
1847 : : pcp = is_of_vlan_pcp_present(actions) ?
1848 : : ((const struct rte_flow_action_of_set_vlan_pcp *)
1849 [ # # # # ]: 0 : actions[MLX5_HW_VLAN_PUSH_PCP_IDX].conf)->vlan_pcp : 0;
1850 : : #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
1851 : 0 : vid_hi = vid & 0xff;
1852 : : vid_lo = vid >> 8;
1853 : 0 : return (((vid_lo << 8) | (pcp << 5) | vid_hi) << 16) | type;
1854 : : #else
1855 : : return (type << 16) | (pcp << 13) | vid;
1856 : : #endif
1857 : : }
1858 : :
1859 : : static __rte_always_inline struct mlx5_aso_mtr *
1860 : : flow_hw_meter_mark_alloc(struct rte_eth_dev *dev, uint32_t queue,
1861 : : const struct rte_flow_action *action,
1862 : : struct mlx5_hw_q_job *job, bool push,
1863 : : struct rte_flow_error *error)
1864 : : {
1865 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1866 : 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
1867 : 0 : const struct rte_flow_action_meter_mark *meter_mark = action->conf;
1868 : : struct mlx5_aso_mtr *aso_mtr;
1869 : : struct mlx5_flow_meter_info *fm;
1870 : 0 : uint32_t mtr_id = 0;
1871 : : uintptr_t handle = (uintptr_t)MLX5_INDIRECT_ACTION_TYPE_METER_MARK <<
1872 : : MLX5_INDIRECT_ACTION_TYPE_OFFSET;
1873 : :
1874 : 0 : if (priv->shared_host) {
1875 : 0 : rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1876 : : "Meter mark actions can only be created on the host port");
1877 : : return NULL;
1878 : : }
1879 [ # # # # : 0 : if (meter_mark->profile == NULL)
# # # # #
# # # #
# ]
1880 : : return NULL;
1881 : 0 : aso_mtr = mlx5_ipool_malloc(pool->idx_pool, &mtr_id);
1882 [ # # # # : 0 : if (!aso_mtr) {
# # # # #
# # # #
# ]
1883 : 0 : rte_flow_error_set(error, ENOMEM,
1884 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1885 : : NULL,
1886 : : "failed to allocate aso meter entry");
1887 [ # # # # : 0 : if (mtr_id)
# # # # #
# # # #
# ]
1888 : 0 : mlx5_ipool_free(pool->idx_pool, mtr_id);
1889 : : return NULL;
1890 : : }
1891 : : /* Fill the flow meter parameters. */
1892 : 0 : aso_mtr->type = ASO_METER_INDIRECT;
1893 : : fm = &aso_mtr->fm;
1894 : 0 : fm->meter_id = mtr_id;
1895 : 0 : fm->profile = (struct mlx5_flow_meter_profile *)(meter_mark->profile);
1896 : 0 : fm->is_enable = meter_mark->state;
1897 : 0 : fm->color_aware = meter_mark->color_mode;
1898 : 0 : aso_mtr->pool = pool;
1899 [ # # ]: 0 : aso_mtr->state = (queue == MLX5_HW_INV_QUEUE) ?
1900 : : ASO_METER_WAIT : ASO_METER_WAIT_ASYNC;
1901 : 0 : aso_mtr->offset = mtr_id - 1;
1902 [ # # # # : 0 : aso_mtr->init_color = fm->color_aware ? RTE_COLORS : RTE_COLOR_GREEN;
# # # # #
# # # #
# ]
1903 : 0 : job->action = (void *)(handle | mtr_id);
1904 : : /* Update ASO flow meter by wqe. */
1905 [ # # # # : 0 : if (mlx5_aso_meter_update_by_wqe(priv, queue, aso_mtr,
# # # # #
# # # #
# ]
1906 : : &priv->mtr_bulk, job, push)) {
1907 : 0 : mlx5_ipool_free(pool->idx_pool, mtr_id);
1908 : : return NULL;
1909 : : }
1910 : : /* Wait for ASO object completion. */
1911 [ # # # # : 0 : if (queue == MLX5_HW_INV_QUEUE &&
# # # # #
# # # # #
# # ]
1912 : 0 : mlx5_aso_mtr_wait(priv, aso_mtr, true)) {
1913 : 0 : mlx5_ipool_free(pool->idx_pool, mtr_id);
1914 : : return NULL;
1915 : : }
1916 : : return aso_mtr;
1917 : : }
1918 : :
1919 : : static __rte_always_inline int
1920 : : flow_hw_meter_mark_compile(struct rte_eth_dev *dev,
1921 : : uint16_t aso_mtr_pos,
1922 : : const struct rte_flow_action *action,
1923 : : struct mlx5dr_rule_action *acts,
1924 : : uint32_t *index,
1925 : : uint32_t queue,
1926 : : struct rte_flow_error *error)
1927 : : {
1928 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1929 : 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
1930 : : struct mlx5_aso_mtr *aso_mtr;
1931 : : struct mlx5_hw_q_job *job =
1932 : : flow_hw_action_job_init(priv, queue, NULL, NULL, NULL,
1933 : : MLX5_HW_Q_JOB_TYPE_CREATE,
1934 : : MLX5_HW_INDIRECT_TYPE_LEGACY, NULL);
1935 : :
1936 : : if (!job)
1937 : : return -1;
1938 : : aso_mtr = flow_hw_meter_mark_alloc(dev, queue, action, job,
1939 : : true, error);
1940 : : if (!aso_mtr) {
1941 : : flow_hw_job_put(priv, job, queue);
1942 : : return -1;
1943 : : }
1944 : :
1945 : : /* Compile METER_MARK action */
1946 : 0 : acts[aso_mtr_pos].action = pool->action;
1947 : 0 : acts[aso_mtr_pos].aso_meter.offset = aso_mtr->offset;
1948 : 0 : *index = aso_mtr->fm.meter_id;
1949 : : return 0;
1950 : : }
1951 : :
1952 : : static int
1953 : 0 : flow_hw_translate_indirect_mirror(__rte_unused struct rte_eth_dev *dev,
1954 : : __rte_unused const struct mlx5_action_construct_data *act_data,
1955 : : const struct rte_flow_action *action,
1956 : : struct mlx5dr_rule_action *dr_rule)
1957 : : {
1958 : 0 : const struct rte_flow_action_indirect_list *list_conf = action->conf;
1959 : 0 : const struct mlx5_mirror *mirror = (typeof(mirror))list_conf->handle;
1960 : :
1961 : 0 : dr_rule->action = mirror->mirror_action;
1962 : 0 : return 0;
1963 : : }
1964 : :
1965 : : /**
1966 : : * HWS mirror implemented as FW island.
1967 : : * The action does not support indirect list flow configuration.
1968 : : * If template handle was masked, use handle mirror action in flow rules.
1969 : : * Otherwise let flow rule specify mirror handle.
1970 : : */
1971 : : static int
1972 : 0 : hws_table_tmpl_translate_indirect_mirror(struct rte_eth_dev *dev,
1973 : : const struct rte_flow_action *action,
1974 : : const struct rte_flow_action *mask,
1975 : : struct mlx5_hw_actions *acts,
1976 : : uint16_t action_src, uint16_t action_dst)
1977 : : {
1978 : : int ret = 0;
1979 : 0 : const struct rte_flow_action_indirect_list *mask_conf = mask->conf;
1980 : :
1981 [ # # # # ]: 0 : if (mask_conf && mask_conf->handle) {
1982 : : /**
1983 : : * If mirror handle was masked, assign fixed DR5 mirror action.
1984 : : */
1985 : : flow_hw_translate_indirect_mirror(dev, NULL, action,
1986 : 0 : &acts->rule_acts[action_dst]);
1987 : : } else {
1988 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1989 : : ret = flow_hw_act_data_indirect_list_append
1990 : : (priv, acts, RTE_FLOW_ACTION_TYPE_INDIRECT_LIST,
1991 : : action_src, action_dst,
1992 : : flow_hw_translate_indirect_mirror);
1993 : : }
1994 : :
1995 : 0 : return ret;
1996 : : }
1997 : :
1998 : : static int
1999 : 0 : flow_hw_reformat_action(__rte_unused struct rte_eth_dev *dev,
2000 : : __rte_unused const struct mlx5_action_construct_data *data,
2001 : : const struct rte_flow_action *action,
2002 : : struct mlx5dr_rule_action *dr_rule)
2003 : : {
2004 : 0 : const struct rte_flow_action_indirect_list *indlst_conf = action->conf;
2005 : :
2006 : 0 : dr_rule->action = ((struct mlx5_hw_encap_decap_action *)
2007 : 0 : (indlst_conf->handle))->action;
2008 [ # # ]: 0 : if (!dr_rule->action)
2009 : 0 : return -EINVAL;
2010 : : return 0;
2011 : : }
2012 : :
2013 : : /**
2014 : : * Template conf must not be masked. If handle is masked, use the one in template,
2015 : : * otherwise update per flow rule.
2016 : : */
2017 : : static int
2018 : 0 : hws_table_tmpl_translate_indirect_reformat(struct rte_eth_dev *dev,
2019 : : const struct rte_flow_action *action,
2020 : : const struct rte_flow_action *mask,
2021 : : struct mlx5_hw_actions *acts,
2022 : : uint16_t action_src, uint16_t action_dst)
2023 : : {
2024 : : int ret = -1;
2025 : 0 : const struct rte_flow_action_indirect_list *mask_conf = mask->conf;
2026 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
2027 : :
2028 [ # # # # : 0 : if (mask_conf && mask_conf->handle && !mask_conf->conf)
# # ]
2029 : : /**
2030 : : * If handle was masked, assign fixed DR action.
2031 : : */
2032 : : ret = flow_hw_reformat_action(dev, NULL, action,
2033 [ # # ]: 0 : &acts->rule_acts[action_dst]);
2034 [ # # # # : 0 : else if (mask_conf && !mask_conf->handle && !mask_conf->conf)
# # ]
2035 : : ret = flow_hw_act_data_indirect_list_append
2036 : : (priv, acts, RTE_FLOW_ACTION_TYPE_INDIRECT_LIST,
2037 : : action_src, action_dst, flow_hw_reformat_action);
2038 : 0 : return ret;
2039 : : }
2040 : :
2041 : : static int
2042 : 0 : flow_dr_set_meter(struct mlx5_priv *priv,
2043 : : struct mlx5dr_rule_action *dr_rule,
2044 : : const struct rte_flow_action_indirect_list *action_conf)
2045 : : {
2046 : 0 : const struct mlx5_indlst_legacy *legacy_obj =
2047 : : (typeof(legacy_obj))action_conf->handle;
2048 : 0 : struct mlx5_aso_mtr_pool *mtr_pool = priv->hws_mpool;
2049 : 0 : uint32_t act_idx = (uint32_t)(uintptr_t)legacy_obj->handle;
2050 : 0 : uint32_t mtr_id = act_idx & (RTE_BIT32(MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
2051 : 0 : struct mlx5_aso_mtr *aso_mtr = mlx5_ipool_get(mtr_pool->idx_pool, mtr_id);
2052 : :
2053 [ # # ]: 0 : if (!aso_mtr)
2054 : : return -EINVAL;
2055 : 0 : dr_rule->action = mtr_pool->action;
2056 : 0 : dr_rule->aso_meter.offset = aso_mtr->offset;
2057 : 0 : return 0;
2058 : : }
2059 : :
2060 : : __rte_always_inline static void
2061 : : flow_dr_mtr_flow_color(struct mlx5dr_rule_action *dr_rule, enum rte_color init_color)
2062 : : {
2063 : 0 : dr_rule->aso_meter.init_color =
2064 : 0 : (enum mlx5dr_action_aso_meter_color)rte_col_2_mlx5_col(init_color);
2065 : 0 : }
2066 : :
2067 : : static int
2068 : 0 : flow_hw_translate_indirect_meter(struct rte_eth_dev *dev,
2069 : : const struct mlx5_action_construct_data *act_data,
2070 : : const struct rte_flow_action *action,
2071 : : struct mlx5dr_rule_action *dr_rule)
2072 : : {
2073 : : int ret;
2074 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
2075 : 0 : const struct rte_flow_action_indirect_list *action_conf = action->conf;
2076 : 0 : const struct rte_flow_indirect_update_flow_meter_mark **flow_conf =
2077 : : (typeof(flow_conf))action_conf->conf;
2078 : :
2079 : 0 : ret = flow_dr_set_meter(priv, dr_rule, action_conf);
2080 [ # # ]: 0 : if (ret)
2081 : : return ret;
2082 [ # # ]: 0 : if (!act_data->shared_meter.conf_masked) {
2083 [ # # # # : 0 : if (flow_conf && flow_conf[0] && flow_conf[0]->init_color < RTE_COLORS)
# # ]
2084 : : flow_dr_mtr_flow_color(dr_rule, flow_conf[0]->init_color);
2085 : : }
2086 : : return 0;
2087 : : }
2088 : :
2089 : : static int
2090 : 0 : hws_table_tmpl_translate_indirect_meter(struct rte_eth_dev *dev,
2091 : : const struct rte_flow_action *action,
2092 : : const struct rte_flow_action *mask,
2093 : : struct mlx5_hw_actions *acts,
2094 : : uint16_t action_src, uint16_t action_dst)
2095 : : {
2096 : : int ret;
2097 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
2098 : 0 : const struct rte_flow_action_indirect_list *action_conf = action->conf;
2099 : 0 : const struct rte_flow_action_indirect_list *mask_conf = mask->conf;
2100 [ # # # # ]: 0 : bool is_handle_masked = mask_conf && mask_conf->handle;
2101 [ # # # # : 0 : bool is_conf_masked = mask_conf && mask_conf->conf && mask_conf->conf[0];
# # ]
2102 : 0 : struct mlx5dr_rule_action *dr_rule = &acts->rule_acts[action_dst];
2103 : :
2104 [ # # ]: 0 : if (is_handle_masked) {
2105 : 0 : ret = flow_dr_set_meter(priv, dr_rule, action->conf);
2106 [ # # ]: 0 : if (ret)
2107 : : return ret;
2108 : : }
2109 [ # # ]: 0 : if (is_conf_masked) {
2110 : : const struct
2111 : 0 : rte_flow_indirect_update_flow_meter_mark **flow_conf =
2112 : : (typeof(flow_conf))action_conf->conf;
2113 : : flow_dr_mtr_flow_color(dr_rule,
2114 [ # # ]: 0 : flow_conf[0]->init_color);
2115 : : }
2116 [ # # ]: 0 : if (!is_handle_masked || !is_conf_masked) {
2117 : : struct mlx5_action_construct_data *act_data;
2118 : :
2119 : : ret = flow_hw_act_data_indirect_list_append
2120 : : (priv, acts, RTE_FLOW_ACTION_TYPE_INDIRECT_LIST,
2121 : : action_src, action_dst, flow_hw_translate_indirect_meter);
2122 : : if (ret)
2123 : 0 : return ret;
2124 : : act_data = LIST_FIRST(&acts->act_list);
2125 : 0 : act_data->shared_meter.conf_masked = is_conf_masked;
2126 : : }
2127 : : return 0;
2128 : : }
2129 : :
2130 : : static int
2131 : : hws_table_tmpl_translate_indirect_legacy(struct rte_eth_dev *dev,
2132 : : const struct rte_flow_action *action,
2133 : : const struct rte_flow_action *mask,
2134 : : struct mlx5_hw_actions *acts,
2135 : : uint16_t action_src, uint16_t action_dst)
2136 : : {
2137 : : int ret;
2138 : : const struct rte_flow_action_indirect_list *indlst_conf = action->conf;
2139 : : struct mlx5_indlst_legacy *indlst_obj = (typeof(indlst_obj))indlst_conf->handle;
2140 : 0 : uint32_t act_idx = (uint32_t)(uintptr_t)indlst_obj->handle;
2141 : 0 : uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
2142 : :
2143 : 0 : switch (type) {
2144 : 0 : case MLX5_INDIRECT_ACTION_TYPE_METER_MARK:
2145 : 0 : ret = hws_table_tmpl_translate_indirect_meter(dev, action, mask,
2146 : : acts, action_src,
2147 : : action_dst);
2148 : 0 : break;
2149 : : default:
2150 : : ret = -EINVAL;
2151 : : break;
2152 : : }
2153 : : return ret;
2154 : : }
2155 : :
2156 : : /*
2157 : : * template .. indirect_list handle Ht conf Ct ..
2158 : : * mask .. indirect_list handle Hm conf Cm ..
2159 : : *
2160 : : * PMD requires Ht != 0 to resolve handle type.
2161 : : * If Ht was masked (Hm != 0) DR5 action will be set according to Ht and will
2162 : : * not change. Otherwise, DR5 action will be resolved during flow rule build.
2163 : : * If Ct was masked (Cm != 0), table template processing updates base
2164 : : * indirect action configuration with Ct parameters.
2165 : : */
2166 : : static int
2167 : 0 : table_template_translate_indirect_list(struct rte_eth_dev *dev,
2168 : : const struct rte_flow_action *action,
2169 : : const struct rte_flow_action *mask,
2170 : : struct mlx5_hw_actions *acts,
2171 : : uint16_t action_src, uint16_t action_dst)
2172 : : {
2173 : : int ret = 0;
2174 : : enum mlx5_indirect_list_type type;
2175 : 0 : const struct rte_flow_action_indirect_list *list_conf = action->conf;
2176 : :
2177 [ # # # # ]: 0 : if (!list_conf || !list_conf->handle)
2178 : : return -EINVAL;
2179 : : type = mlx5_get_indirect_list_type(list_conf->handle);
2180 [ # # # # ]: 0 : switch (type) {
2181 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY:
2182 [ # # ]: 0 : ret = hws_table_tmpl_translate_indirect_legacy(dev, action, mask,
2183 : : acts, action_src,
2184 : : action_dst);
2185 : : break;
2186 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR:
2187 : 0 : ret = hws_table_tmpl_translate_indirect_mirror(dev, action, mask,
2188 : : acts, action_src,
2189 : : action_dst);
2190 : 0 : break;
2191 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT:
2192 [ # # ]: 0 : if (list_conf->conf)
2193 : : return -EINVAL;
2194 : 0 : ret = hws_table_tmpl_translate_indirect_reformat(dev, action, mask,
2195 : : acts, action_src,
2196 : : action_dst);
2197 : 0 : break;
2198 : : default:
2199 : : return -EINVAL;
2200 : : }
2201 : : return ret;
2202 : : }
2203 : :
2204 : : static void
2205 : : mlx5_set_reformat_header(struct mlx5dr_action_reformat_header *hdr,
2206 : : uint8_t *encap_data,
2207 : : size_t data_size)
2208 : : {
2209 : 0 : hdr->sz = data_size;
2210 : 0 : hdr->data = encap_data;
2211 : : }
2212 : :
2213 : : static int
2214 [ # # ]: 0 : mlx5_tbl_translate_reformat(struct mlx5_priv *priv,
2215 : : struct mlx5_hw_actions *acts,
2216 : : struct rte_flow_actions_template *at,
2217 : : const struct rte_flow_item *enc_item,
2218 : : const struct rte_flow_item *enc_item_m,
2219 : : uint8_t *encap_data, uint8_t *encap_data_m,
2220 : : struct mlx5_tbl_multi_pattern_ctx *mp_ctx,
2221 : : size_t data_size, uint16_t reformat_src,
2222 : : enum mlx5dr_action_type refmt_type,
2223 : : struct rte_flow_error *error)
2224 : : {
2225 : : int mp_reformat_ix = mlx5_multi_pattern_reformat_to_index(refmt_type);
2226 : : struct mlx5dr_action_reformat_header hdr;
2227 : : uint8_t buf[MLX5_ENCAP_MAX_LEN];
2228 : : bool shared_rfmt = false;
2229 : : int ret;
2230 : :
2231 : : MLX5_ASSERT(at->reformat_off != UINT16_MAX);
2232 [ # # ]: 0 : if (enc_item) {
2233 : : MLX5_ASSERT(!encap_data);
2234 : 0 : ret = flow_dv_convert_encap_data(enc_item, buf, &data_size, error);
2235 [ # # ]: 0 : if (ret)
2236 : : return ret;
2237 : : encap_data = buf;
2238 [ # # ]: 0 : if (enc_item_m)
2239 : : shared_rfmt = true;
2240 [ # # ]: 0 : } else if (encap_data && encap_data_m) {
2241 : : shared_rfmt = true;
2242 : : }
2243 : 0 : acts->encap_decap = mlx5_malloc(MLX5_MEM_ZERO,
2244 : : sizeof(*acts->encap_decap) + data_size,
2245 : : 0, SOCKET_ID_ANY);
2246 [ # # ]: 0 : if (!acts->encap_decap)
2247 : 0 : return rte_flow_error_set(error, ENOMEM,
2248 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2249 : : NULL, "no memory for reformat context");
2250 : 0 : acts->encap_decap_pos = at->reformat_off;
2251 : 0 : acts->encap_decap->data_size = data_size;
2252 : 0 : acts->encap_decap->action_type = refmt_type;
2253 [ # # ]: 0 : if (shared_rfmt || mp_reformat_ix < 0) {
2254 : : uint16_t reformat_ix = at->reformat_off;
2255 : : /*
2256 : : * This copy is only needed in non template mode.
2257 : : * In order to create the action later.
2258 : : */
2259 : 0 : memcpy(acts->encap_decap->data, encap_data, data_size);
2260 : 0 : acts->rule_acts[reformat_ix].reformat.data = acts->encap_decap->data;
2261 : 0 : acts->rule_acts[reformat_ix].reformat.offset = 0;
2262 : 0 : acts->encap_decap->shared = true;
2263 : : } else {
2264 : : uint32_t ix;
2265 : 0 : typeof(mp_ctx->reformat[0]) *reformat = mp_ctx->reformat +
2266 : : mp_reformat_ix;
2267 : : mlx5_set_reformat_header(&hdr, encap_data, data_size);
2268 : 0 : ix = reformat->elements_num++;
2269 : 0 : reformat->reformat_hdr[ix] = hdr;
2270 : 0 : acts->rule_acts[at->reformat_off].reformat.hdr_idx = ix;
2271 : 0 : acts->encap_decap->multi_pattern = 1;
2272 : 0 : ret = __flow_hw_act_data_encap_append
2273 : 0 : (priv, acts, (at->actions + reformat_src)->type,
2274 : : reformat_src, at->reformat_off, data_size);
2275 : : if (ret)
2276 : 0 : return -rte_errno;
2277 : : mlx5_multi_pattern_activate(mp_ctx);
2278 : : }
2279 : : return 0;
2280 : : }
2281 : :
2282 : : static int
2283 : 0 : mlx5_tbl_create_reformat_action(struct mlx5_priv *priv,
2284 : : const struct rte_flow_template_table_attr *table_attr,
2285 : : struct mlx5_hw_actions *acts,
2286 : : struct rte_flow_actions_template *at,
2287 : : uint8_t *encap_data,
2288 : : size_t data_size,
2289 : : enum mlx5dr_action_type refmt_type)
2290 : : {
2291 : 0 : const struct rte_flow_attr *attr = &table_attr->flow_attr;
2292 : : bool unified_fdb = is_unified_fdb(priv);
2293 : 0 : enum mlx5dr_table_type tbl_type = get_mlx5dr_table_type(attr, table_attr->specialize,
2294 : : unified_fdb);
2295 : : struct mlx5dr_action_reformat_header hdr;
2296 : :
2297 : : mlx5_set_reformat_header(&hdr, encap_data, data_size);
2298 : 0 : uint16_t reformat_ix = at->reformat_off;
2299 : 0 : uint32_t flags = mlx5_hw_act_flag[!!attr->group][tbl_type] |
2300 : : MLX5DR_ACTION_FLAG_SHARED;
2301 : :
2302 : 0 : acts->encap_decap->action = mlx5dr_action_create_reformat(priv->dr_ctx, refmt_type,
2303 : : 1, &hdr, 0, flags);
2304 [ # # ]: 0 : if (!acts->encap_decap->action)
2305 : 0 : return -rte_errno;
2306 : 0 : acts->rule_acts[reformat_ix].action = acts->encap_decap->action;
2307 : 0 : return 0;
2308 : : }
2309 : :
2310 : : static int
2311 : 0 : mlx5_tbl_translate_modify_header(struct rte_eth_dev *dev,
2312 : : const struct mlx5_flow_template_table_cfg *cfg,
2313 : : struct mlx5_hw_actions *acts,
2314 : : struct mlx5_tbl_multi_pattern_ctx *mp_ctx,
2315 : : struct mlx5_hw_modify_header_action *mhdr,
2316 : : struct rte_flow_error *error)
2317 : : {
2318 : 0 : uint16_t mhdr_ix = mhdr->pos;
2319 : : struct mlx5dr_action_mh_pattern pattern = {
2320 : 0 : .sz = sizeof(struct mlx5_modification_cmd) * mhdr->mhdr_cmds_num
2321 : : };
2322 : :
2323 [ # # ]: 0 : if (flow_hw_validate_compiled_modify_field(dev, cfg, mhdr, error)) {
2324 : : __flow_hw_action_template_destroy(dev, acts);
2325 : 0 : return -rte_errno;
2326 : : }
2327 : 0 : acts->mhdr = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*acts->mhdr),
2328 : : 0, SOCKET_ID_ANY);
2329 [ # # ]: 0 : if (!acts->mhdr)
2330 : 0 : return rte_flow_error_set(error, ENOMEM,
2331 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2332 : : NULL, "translate modify_header: no memory for modify header context");
2333 : : rte_memcpy(acts->mhdr, mhdr, sizeof(*mhdr));
2334 [ # # ]: 0 : if (!mhdr->shared) {
2335 : 0 : pattern.data = (__be64 *)acts->mhdr->mhdr_cmds;
2336 : : typeof(mp_ctx->mh) *mh = &mp_ctx->mh;
2337 : 0 : uint32_t idx = mh->elements_num;
2338 : 0 : mh->pattern[mh->elements_num++] = pattern;
2339 : 0 : acts->mhdr->multi_pattern = 1;
2340 : 0 : acts->rule_acts[mhdr_ix].modify_header.pattern_idx = idx;
2341 : : mlx5_multi_pattern_activate(mp_ctx);
2342 : : }
2343 : : return 0;
2344 : : }
2345 : :
2346 : : static int
2347 : 0 : mlx5_tbl_ensure_shared_modify_header(struct rte_eth_dev *dev,
2348 : : const struct mlx5_flow_template_table_cfg *cfg,
2349 : : struct mlx5_hw_actions *acts,
2350 : : struct rte_flow_error *error)
2351 : : {
2352 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
2353 : : bool unified_fdb = is_unified_fdb(priv);
2354 : : const struct rte_flow_template_table_attr *table_attr = &cfg->attr;
2355 : 0 : const struct rte_flow_attr *attr = &table_attr->flow_attr;
2356 : 0 : enum mlx5dr_table_type tbl_type = get_mlx5dr_table_type(attr, table_attr->specialize,
2357 : : unified_fdb);
2358 : 0 : struct mlx5dr_action_mh_pattern pattern = {
2359 : 0 : .sz = sizeof(struct mlx5_modification_cmd) * acts->mhdr->mhdr_cmds_num
2360 : : };
2361 : 0 : uint16_t mhdr_ix = acts->mhdr->pos;
2362 : 0 : uint32_t flags = mlx5_hw_act_flag[!!attr->group][tbl_type] | MLX5DR_ACTION_FLAG_SHARED;
2363 : :
2364 : 0 : pattern.data = (__be64 *)acts->mhdr->mhdr_cmds;
2365 : 0 : acts->mhdr->action = mlx5dr_action_create_modify_header(priv->dr_ctx, 1,
2366 : : &pattern, 0, flags);
2367 [ # # ]: 0 : if (!acts->mhdr->action)
2368 : 0 : return rte_flow_error_set(error, rte_errno,
2369 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2370 : : "translate modify_header: failed to create DR action");
2371 : 0 : acts->rule_acts[mhdr_ix].action = acts->mhdr->action;
2372 : 0 : return 0;
2373 : : }
2374 : :
2375 : : static int
2376 : 0 : mlx5_create_ipv6_ext_reformat(struct rte_eth_dev *dev,
2377 : : const struct mlx5_flow_template_table_cfg *cfg,
2378 : : struct mlx5_hw_actions *acts,
2379 : : struct rte_flow_actions_template *at,
2380 : : uint8_t *push_data, uint8_t *push_data_m,
2381 : : size_t push_size, uint16_t recom_src,
2382 : : enum mlx5dr_action_type recom_type)
2383 : : {
2384 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
2385 : : bool unified_fdb = is_unified_fdb(priv);
2386 : : const struct rte_flow_template_table_attr *table_attr = &cfg->attr;
2387 : 0 : const struct rte_flow_attr *attr = &table_attr->flow_attr;
2388 : : enum mlx5dr_table_type type =
2389 : 0 : get_mlx5dr_table_type(attr, table_attr->specialize, unified_fdb);
2390 : : struct mlx5_action_construct_data *act_data;
2391 : 0 : struct mlx5dr_action_reformat_header hdr = {0};
2392 : : uint32_t flag, bulk = 0;
2393 : :
2394 : 0 : flag = mlx5_hw_act_flag[!!attr->group][type];
2395 : 0 : acts->push_remove = mlx5_malloc(MLX5_MEM_ZERO,
2396 : : sizeof(*acts->push_remove) + push_size,
2397 : : 0, SOCKET_ID_ANY);
2398 [ # # ]: 0 : if (!acts->push_remove)
2399 : : return -ENOMEM;
2400 : :
2401 [ # # # ]: 0 : switch (recom_type) {
2402 : 0 : case MLX5DR_ACTION_TYP_PUSH_IPV6_ROUTE_EXT:
2403 [ # # ]: 0 : if (!push_data || !push_size)
2404 : 0 : goto err1;
2405 [ # # ]: 0 : if (!push_data_m) {
2406 [ # # ]: 0 : bulk = rte_log2_u32(table_attr->nb_flows);
2407 : : } else {
2408 : 0 : flag |= MLX5DR_ACTION_FLAG_SHARED;
2409 : 0 : acts->push_remove->shared = 1;
2410 : : }
2411 : 0 : acts->push_remove->data_size = push_size;
2412 : 0 : memcpy(acts->push_remove->data, push_data, push_size);
2413 : 0 : hdr.data = push_data;
2414 : 0 : hdr.sz = push_size;
2415 : 0 : break;
2416 : 0 : case MLX5DR_ACTION_TYP_POP_IPV6_ROUTE_EXT:
2417 : 0 : flag |= MLX5DR_ACTION_FLAG_SHARED;
2418 : 0 : acts->push_remove->shared = 1;
2419 : 0 : break;
2420 : : default:
2421 : : break;
2422 : : }
2423 : :
2424 : 0 : acts->push_remove->action =
2425 : 0 : mlx5dr_action_create_reformat_ipv6_ext(priv->dr_ctx,
2426 : : recom_type, &hdr, bulk, flag);
2427 [ # # ]: 0 : if (!acts->push_remove->action)
2428 : 0 : goto err1;
2429 : 0 : acts->rule_acts[at->recom_off].action = acts->push_remove->action;
2430 : 0 : acts->rule_acts[at->recom_off].ipv6_ext.header = acts->push_remove->data;
2431 : 0 : acts->rule_acts[at->recom_off].ipv6_ext.offset = 0;
2432 : 0 : acts->push_remove_pos = at->recom_off;
2433 [ # # ]: 0 : if (!acts->push_remove->shared) {
2434 : 0 : act_data = __flow_hw_act_data_push_append(dev, acts,
2435 : : RTE_FLOW_ACTION_TYPE_IPV6_EXT_PUSH,
2436 : : recom_src, at->recom_off, push_size);
2437 : : if (!act_data)
2438 : 0 : goto err;
2439 : : }
2440 : : return 0;
2441 : : err:
2442 [ # # ]: 0 : if (acts->push_remove->action)
2443 : 0 : mlx5dr_action_destroy(acts->push_remove->action);
2444 : 0 : err1:
2445 [ # # ]: 0 : if (acts->push_remove) {
2446 : 0 : mlx5_free(acts->push_remove);
2447 : 0 : acts->push_remove = NULL;
2448 : : }
2449 : : return -EINVAL;
2450 : : }
2451 : :
2452 : : /**
2453 : : * Translate rte_flow actions to DR action.
2454 : : *
2455 : : * As the action template has already indicated the actions. Translate
2456 : : * the rte_flow actions to DR action if possbile. So in flow create
2457 : : * stage we will save cycles from handing the actions' organizing.
2458 : : * For the actions with limited information, need to add these to a
2459 : : * list.
2460 : : *
2461 : : * @param[in] dev
2462 : : * Pointer to the rte_eth_dev structure.
2463 : : * @param[in] cfg
2464 : : * Pointer to the table configuration.
2465 : : * @param[in/out] acts
2466 : : * Pointer to the template HW steering DR actions.
2467 : : * @param[in] at
2468 : : * Action template.
2469 : : * @param[in] nt_mode
2470 : : * Non template rule translate.
2471 : : * @param[out] error
2472 : : * Pointer to error structure.
2473 : : *
2474 : : * @return
2475 : : * 0 on success, a negative errno otherwise and rte_errno is set.
2476 : : */
2477 : : static int
2478 : 0 : __flow_hw_translate_actions_template(struct rte_eth_dev *dev,
2479 : : const struct mlx5_flow_template_table_cfg *cfg,
2480 : : struct mlx5_hw_actions *acts,
2481 : : struct rte_flow_actions_template *at,
2482 : : struct mlx5_tbl_multi_pattern_ctx *mp_ctx,
2483 : : bool nt_mode,
2484 : : struct rte_flow_error *error)
2485 : : {
2486 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
2487 : 0 : struct mlx5_hca_attr *hca_attr = &priv->sh->cdev->config.hca_attr;
2488 : 0 : const struct rte_flow_template_table_attr *table_attr = &cfg->attr;
2489 : 0 : const struct rte_flow_attr *attr = &table_attr->flow_attr;
2490 : 0 : struct rte_flow_action *actions = at->actions;
2491 : 0 : struct rte_flow_action *masks = at->masks;
2492 : : enum mlx5dr_action_type refmt_type = MLX5DR_ACTION_TYP_LAST;
2493 : : enum mlx5dr_action_type recom_type = MLX5DR_ACTION_TYP_LAST;
2494 : : const struct rte_flow_action_raw_encap *raw_encap_data;
2495 : : const struct rte_flow_action_ipv6_ext_push *ipv6_ext_data;
2496 : : const struct rte_flow_item *enc_item = NULL, *enc_item_m = NULL;
2497 : : uint16_t reformat_src = 0, recom_src = 0;
2498 : : uint8_t *encap_data = NULL, *encap_data_m = NULL;
2499 : : uint8_t *push_data = NULL, *push_data_m = NULL;
2500 : : size_t data_size = 0, push_size = 0;
2501 : : struct mlx5_hw_modify_header_action mhdr = { 0 };
2502 : 0 : struct rte_flow_error sub_error = {
2503 : : .type = RTE_FLOW_ERROR_TYPE_NONE,
2504 : : .cause = NULL,
2505 : : .message = NULL,
2506 : : };
2507 : : bool actions_end = false;
2508 : : uint32_t type;
2509 : : bool reformat_used = false;
2510 : : bool recom_used = false;
2511 : : unsigned int of_vlan_offset;
2512 : : uint32_t ct_idx;
2513 : : int ret, err;
2514 : 0 : uint32_t target_grp = 0;
2515 : : bool unified_fdb = is_unified_fdb(priv);
2516 : :
2517 : : flow_hw_modify_field_init(&mhdr, at);
2518 : 0 : type = get_mlx5dr_table_type(attr, cfg->attr.specialize, unified_fdb);
2519 [ # # ]: 0 : for (; !actions_end; actions++, masks++) {
2520 : 0 : uint64_t pos = actions - at->actions;
2521 : 0 : uint16_t src_pos = pos - at->src_off[pos];
2522 : 0 : uint16_t dr_pos = at->dr_off[pos];
2523 : :
2524 [ # # # # : 0 : switch ((int)actions->type) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
2525 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT_LIST:
2526 [ # # ]: 0 : if (!attr->group) {
2527 : 0 : DRV_LOG(ERR, "Indirect action is not supported in root table.");
2528 : 0 : goto err;
2529 : : }
2530 : 0 : ret = table_template_translate_indirect_list
2531 : : (dev, actions, masks, acts, src_pos, dr_pos);
2532 [ # # ]: 0 : if (ret)
2533 : 0 : goto err;
2534 : : break;
2535 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT:
2536 [ # # ]: 0 : if (!attr->group) {
2537 : 0 : DRV_LOG(ERR, "Indirect action is not supported in root table.");
2538 : 0 : goto err;
2539 : : }
2540 [ # # # # ]: 0 : if (actions->conf && masks->conf) {
2541 [ # # # # : 0 : if (flow_hw_shared_action_translate
# # # ]
2542 : : (dev, actions, acts, src_pos, dr_pos))
2543 : 0 : goto err;
2544 : 0 : } else if (__flow_hw_act_data_indirect_append
2545 : : (priv, acts, RTE_FLOW_ACTION_TYPE_INDIRECT,
2546 : : masks->type, src_pos, dr_pos)){
2547 : 0 : goto err;
2548 : : }
2549 : : break;
2550 : : case RTE_FLOW_ACTION_TYPE_VOID:
2551 : : break;
2552 : 0 : case RTE_FLOW_ACTION_TYPE_DROP:
2553 : 0 : acts->rule_acts[dr_pos].action =
2554 : 0 : priv->hw_drop[!!attr->group];
2555 : 0 : break;
2556 : 0 : case RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:
2557 [ # # ]: 0 : if (!attr->group) {
2558 : 0 : DRV_LOG(ERR, "Port representor is not supported in root table.");
2559 : 0 : goto err;
2560 : : }
2561 : 0 : acts->rule_acts[dr_pos].action = priv->hw_def_miss;
2562 : 0 : break;
2563 : 0 : case RTE_FLOW_ACTION_TYPE_FLAG:
2564 : 0 : acts->mark = true;
2565 : 0 : acts->rule_acts[dr_pos].tag.value =
2566 : : mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
2567 : 0 : acts->rule_acts[dr_pos].action =
2568 : 0 : priv->hw_tag[!!attr->group];
2569 : 0 : rte_atomic_fetch_add_explicit(&priv->hws_mark_refcnt, 1,
2570 : : rte_memory_order_relaxed);
2571 : 0 : flow_hw_rxq_flag_set(dev, true);
2572 : 0 : break;
2573 : 0 : case RTE_FLOW_ACTION_TYPE_MARK:
2574 : 0 : acts->mark = true;
2575 [ # # ]: 0 : if (masks->conf &&
2576 : : ((const struct rte_flow_action_mark *)
2577 [ # # ]: 0 : masks->conf)->id)
2578 : 0 : acts->rule_acts[dr_pos].tag.value =
2579 : : mlx5_flow_mark_set
2580 : : (((const struct rte_flow_action_mark *)
2581 [ # # ]: 0 : (actions->conf))->id);
2582 : : else if (__flow_hw_act_data_general_append(priv, acts,
2583 : : actions->type,
2584 : : src_pos, dr_pos))
2585 : 0 : goto err;
2586 : 0 : acts->rule_acts[dr_pos].action =
2587 : 0 : priv->hw_tag[!!attr->group];
2588 : 0 : rte_atomic_fetch_add_explicit(&priv->hws_mark_refcnt, 1,
2589 : : rte_memory_order_relaxed);
2590 : 0 : flow_hw_rxq_flag_set(dev, true);
2591 : 0 : break;
2592 : 0 : case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
2593 : 0 : acts->rule_acts[dr_pos].action =
2594 : 0 : priv->hw_push_vlan[type];
2595 [ # # # # ]: 0 : if (is_template_masked_push_vlan(masks->conf))
2596 : 0 : acts->rule_acts[dr_pos].push_vlan.vlan_hdr =
2597 : : vlan_hdr_to_be32(actions);
2598 : : else if (__flow_hw_act_data_general_append
2599 : : (priv, acts, actions->type,
2600 : : src_pos, dr_pos))
2601 : 0 : goto err;
2602 : : of_vlan_offset = is_of_vlan_pcp_present(actions) ?
2603 [ # # ]: 0 : MLX5_HW_VLAN_PUSH_PCP_IDX :
2604 : : MLX5_HW_VLAN_PUSH_VID_IDX;
2605 : 0 : actions += of_vlan_offset;
2606 : 0 : masks += of_vlan_offset;
2607 : 0 : break;
2608 : 0 : case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
2609 : 0 : acts->rule_acts[dr_pos].action =
2610 : 0 : priv->hw_pop_vlan[type];
2611 : 0 : break;
2612 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP:
2613 [ # # ]: 0 : if (masks->conf &&
2614 : : ((const struct rte_flow_action_jump *)
2615 [ # # ]: 0 : masks->conf)->group) {
2616 : 0 : uint32_t jump_group =
2617 : : ((const struct rte_flow_action_jump *)
2618 : 0 : actions->conf)->group;
2619 : 0 : acts->jump = flow_hw_jump_action_register
2620 : : (dev, cfg, jump_group, &sub_error);
2621 [ # # ]: 0 : if (!acts->jump)
2622 : 0 : goto err;
2623 : 0 : acts->rule_acts[dr_pos].action = (!!attr->group) ?
2624 [ # # ]: 0 : acts->jump->hws_action :
2625 : : acts->jump->root_action;
2626 : : } else if (__flow_hw_act_data_general_append
2627 : : (priv, acts, actions->type,
2628 : : src_pos, dr_pos)){
2629 : 0 : goto err;
2630 : : }
2631 : : break;
2632 : 0 : case RTE_FLOW_ACTION_TYPE_QUEUE:
2633 [ # # ]: 0 : if (masks->conf &&
2634 : : ((const struct rte_flow_action_queue *)
2635 [ # # ]: 0 : masks->conf)->index) {
2636 : 0 : acts->tir = flow_hw_tir_action_register
2637 : 0 : (dev, mlx5_hw_act_flag[!!attr->group][type],
2638 : : actions);
2639 [ # # ]: 0 : if (!acts->tir)
2640 : 0 : goto err;
2641 : 0 : acts->rule_acts[dr_pos].action =
2642 : 0 : acts->tir->action;
2643 : : } else if (__flow_hw_act_data_general_append
2644 : : (priv, acts, actions->type,
2645 : : src_pos, dr_pos)) {
2646 : 0 : goto err;
2647 : : }
2648 : : break;
2649 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
2650 [ # # # # ]: 0 : if (actions->conf && masks->conf) {
2651 : 0 : acts->tir = flow_hw_tir_action_register
2652 : 0 : (dev, mlx5_hw_act_flag[!!attr->group][type],
2653 : : actions);
2654 [ # # ]: 0 : if (!acts->tir)
2655 : 0 : goto err;
2656 : 0 : acts->rule_acts[dr_pos].action =
2657 : 0 : acts->tir->action;
2658 : : } else if (__flow_hw_act_data_general_append
2659 : : (priv, acts, actions->type,
2660 : : src_pos, dr_pos)) {
2661 : 0 : goto err;
2662 : : }
2663 : : break;
2664 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
2665 : : MLX5_ASSERT(!reformat_used);
2666 : 0 : enc_item = MLX5_CONST_ENCAP_ITEM(rte_flow_action_vxlan_encap,
2667 : : actions->conf);
2668 [ # # ]: 0 : if (masks->conf)
2669 : 0 : enc_item_m = MLX5_CONST_ENCAP_ITEM(rte_flow_action_vxlan_encap,
2670 : : masks->conf);
2671 : : reformat_used = true;
2672 : : reformat_src = src_pos;
2673 : : refmt_type = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;
2674 : : break;
2675 : 0 : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
2676 : : MLX5_ASSERT(!reformat_used);
2677 : 0 : enc_item = MLX5_CONST_ENCAP_ITEM(rte_flow_action_nvgre_encap,
2678 : : actions->conf);
2679 [ # # ]: 0 : if (masks->conf)
2680 : 0 : enc_item_m = MLX5_CONST_ENCAP_ITEM(rte_flow_action_nvgre_encap,
2681 : : masks->conf);
2682 : : reformat_used = true;
2683 : : reformat_src = src_pos;
2684 : : refmt_type = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;
2685 : : break;
2686 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
2687 : 0 : raw_encap_data =
2688 : : (const struct rte_flow_action_raw_encap *)
2689 : : masks->conf;
2690 [ # # ]: 0 : if (raw_encap_data)
2691 : 0 : encap_data_m = raw_encap_data->data;
2692 : 0 : raw_encap_data =
2693 : : (const struct rte_flow_action_raw_encap *)
2694 : : actions->conf;
2695 : 0 : encap_data = raw_encap_data->data;
2696 : 0 : data_size = raw_encap_data->size;
2697 [ # # ]: 0 : if (reformat_used) {
2698 : : refmt_type = data_size <
2699 : : MLX5_ENCAPSULATION_DECISION_SIZE ?
2700 [ # # ]: 0 : MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2 :
2701 : : MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3;
2702 : : } else {
2703 : : reformat_used = true;
2704 : : refmt_type =
2705 : : MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;
2706 : : }
2707 : : reformat_src = src_pos;
2708 : : break;
2709 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
2710 : : case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
2711 : : MLX5_ASSERT(!reformat_used);
2712 : : reformat_used = true;
2713 : : refmt_type = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2;
2714 : 0 : break;
2715 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
2716 : : reformat_used = true;
2717 : : refmt_type = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2;
2718 : 0 : break;
2719 : 0 : case RTE_FLOW_ACTION_TYPE_IPV6_EXT_PUSH:
2720 [ # # ]: 0 : if (!hca_attr->flex.query_match_sample_info ||
2721 : 0 : !hca_attr->flex.parse_graph_anchor ||
2722 [ # # ]: 0 : !priv->sh->srh_flex_parser.flex.mapnum) {
2723 : 0 : DRV_LOG(ERR, "SRv6 anchor is not supported.");
2724 : 0 : goto err;
2725 : : }
2726 : : MLX5_ASSERT(!recom_used && !recom_type);
2727 : : recom_used = true;
2728 : : recom_type = MLX5DR_ACTION_TYP_PUSH_IPV6_ROUTE_EXT;
2729 : 0 : ipv6_ext_data =
2730 : : (const struct rte_flow_action_ipv6_ext_push *)masks->conf;
2731 [ # # ]: 0 : if (ipv6_ext_data)
2732 : 0 : push_data_m = ipv6_ext_data->data;
2733 : 0 : ipv6_ext_data =
2734 : : (const struct rte_flow_action_ipv6_ext_push *)actions->conf;
2735 [ # # ]: 0 : if (ipv6_ext_data) {
2736 : 0 : push_data = ipv6_ext_data->data;
2737 : 0 : push_size = ipv6_ext_data->size;
2738 : : }
2739 : : recom_src = src_pos;
2740 : : break;
2741 : 0 : case RTE_FLOW_ACTION_TYPE_IPV6_EXT_REMOVE:
2742 [ # # ]: 0 : if (!hca_attr->flex.query_match_sample_info ||
2743 : 0 : !hca_attr->flex.parse_graph_anchor ||
2744 [ # # ]: 0 : !priv->sh->srh_flex_parser.flex.mapnum) {
2745 : 0 : DRV_LOG(ERR, "SRv6 anchor is not supported.");
2746 : 0 : goto err;
2747 : : }
2748 : : recom_used = true;
2749 : : recom_type = MLX5DR_ACTION_TYP_POP_IPV6_ROUTE_EXT;
2750 : : break;
2751 : 0 : case RTE_FLOW_ACTION_TYPE_SEND_TO_KERNEL:
2752 : 0 : ret = flow_hw_translate_group(dev, cfg, attr->group,
2753 : : &target_grp, &sub_error);
2754 [ # # ]: 0 : if (ret)
2755 : 0 : goto err;
2756 [ # # ]: 0 : if (target_grp == 0) {
2757 : : __flow_hw_action_template_destroy(dev, acts);
2758 : 0 : rte_flow_error_set(&sub_error, ENOTSUP,
2759 : : RTE_FLOW_ERROR_TYPE_ACTION,
2760 : : NULL,
2761 : : "Send to kernel action on root table is not supported in HW steering mode");
2762 : 0 : goto err;
2763 : : }
2764 : 0 : acts->rule_acts[dr_pos].action = priv->hw_send_to_kernel[type];
2765 : 0 : break;
2766 [ # # ]: 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
2767 : : err = flow_hw_modify_field_compile(dev, attr, actions,
2768 : : masks, acts, &mhdr,
2769 : : src_pos, &sub_error);
2770 [ # # ]: 0 : if (err)
2771 : 0 : goto err;
2772 : : break;
2773 : 0 : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
2774 [ # # ]: 0 : if (flow_hw_represented_port_compile
2775 : : (dev, attr, actions,
2776 : : masks, acts, src_pos, dr_pos, &sub_error))
2777 : 0 : goto err;
2778 : : break;
2779 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
2780 : 0 : ret = flow_hw_translate_group(dev, cfg, attr->group,
2781 : : &target_grp, &sub_error);
2782 [ # # ]: 0 : if (ret)
2783 : 0 : goto err;
2784 [ # # ]: 0 : if (target_grp == 0) {
2785 : : __flow_hw_action_template_destroy(dev, acts);
2786 : 0 : rte_flow_error_set(&sub_error, ENOTSUP,
2787 : : RTE_FLOW_ERROR_TYPE_ACTION,
2788 : : NULL,
2789 : : "Age action on root table is not supported in HW steering mode");
2790 : 0 : goto err;
2791 : : }
2792 : 0 : if (__flow_hw_act_data_general_append(priv, acts,
2793 : : actions->type,
2794 : : src_pos,
2795 : : dr_pos))
2796 : 0 : goto err;
2797 : : break;
2798 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
2799 : 0 : ret = flow_hw_translate_group(dev, cfg, attr->group,
2800 : : &target_grp, &sub_error);
2801 [ # # ]: 0 : if (ret)
2802 : 0 : goto err;
2803 [ # # ]: 0 : if (target_grp == 0) {
2804 : : __flow_hw_action_template_destroy(dev, acts);
2805 : 0 : rte_flow_error_set(&sub_error, ENOTSUP,
2806 : : RTE_FLOW_ERROR_TYPE_ACTION,
2807 : : NULL,
2808 : : "Counter action on root table is not supported in HW steering mode");
2809 : 0 : goto err;
2810 : : }
2811 [ # # ]: 0 : if ((at->action_flags & MLX5_FLOW_ACTION_AGE) ||
2812 : : (at->action_flags & MLX5_FLOW_ACTION_INDIRECT_AGE))
2813 : : /*
2814 : : * When both COUNT and AGE are requested, it is
2815 : : * saved as AGE action which creates also the
2816 : : * counter.
2817 : : */
2818 : : break;
2819 [ # # ]: 0 : if (masks->conf &&
2820 : : ((const struct rte_flow_action_count *)
2821 [ # # ]: 0 : masks->conf)->id) {
2822 [ # # ]: 0 : err = flow_hw_cnt_compile(dev, dr_pos, acts);
2823 : : if (err)
2824 : 0 : goto err;
2825 : 0 : } else if (__flow_hw_act_data_general_append
2826 : : (priv, acts, actions->type,
2827 : : src_pos, dr_pos)) {
2828 : 0 : goto err;
2829 : : }
2830 : : break;
2831 : 0 : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
2832 [ # # ]: 0 : if (masks->conf) {
2833 : 0 : ct_idx = MLX5_INDIRECT_ACTION_IDX_GET(actions->conf);
2834 : : if (flow_hw_ct_compile(dev, MLX5_HW_INV_QUEUE, ct_idx,
2835 : 0 : &acts->rule_acts[dr_pos]))
2836 : 0 : goto err;
2837 : : } else if (__flow_hw_act_data_general_append
2838 : : (priv, acts, actions->type,
2839 : : src_pos, dr_pos)) {
2840 : 0 : goto err;
2841 : : }
2842 : : break;
2843 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
2844 [ # # # # ]: 0 : if (actions->conf && masks->conf &&
2845 : : ((const struct rte_flow_action_meter_mark *)
2846 [ # # ]: 0 : masks->conf)->profile) {
2847 : : err = flow_hw_meter_mark_compile(dev,
2848 : : dr_pos, actions,
2849 : 0 : acts->rule_acts,
2850 : : &acts->mtr_id,
2851 : : MLX5_HW_INV_QUEUE,
2852 : : &sub_error);
2853 : : if (err)
2854 : 0 : goto err;
2855 : : } else if (__flow_hw_act_data_general_append(priv, acts,
2856 : : actions->type,
2857 : : src_pos,
2858 : : dr_pos))
2859 : 0 : goto err;
2860 : : break;
2861 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
2862 : : /* Internal, can be skipped. */
2863 [ # # ]: 0 : if (!!attr->group) {
2864 : 0 : DRV_LOG(ERR, "DEFAULT MISS action is only"
2865 : : " supported in root table.");
2866 : 0 : goto err;
2867 : : }
2868 : 0 : acts->rule_acts[dr_pos].action = priv->hw_def_miss;
2869 : 0 : break;
2870 : 0 : case RTE_FLOW_ACTION_TYPE_NAT64:
2871 [ # # ]: 0 : if (masks->conf &&
2872 [ # # ]: 0 : ((const struct rte_flow_action_nat64 *)masks->conf)->type) {
2873 : 0 : const struct rte_flow_action_nat64 *nat64_c =
2874 : : (const struct rte_flow_action_nat64 *)actions->conf;
2875 : :
2876 : 0 : acts->rule_acts[dr_pos].action =
2877 : 0 : priv->action_nat64[type][nat64_c->type];
2878 : : } else if (__flow_hw_act_data_general_append(priv, acts,
2879 : : actions->type,
2880 : : src_pos, dr_pos))
2881 : 0 : goto err;
2882 : : break;
2883 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
2884 [ # # ]: 0 : if (masks->conf &&
2885 : : ((const struct rte_flow_action_jump_to_table_index *)
2886 [ # # ]: 0 : masks->conf)->table) {
2887 : 0 : struct rte_flow_template_table *jump_table =
2888 : : ((const struct rte_flow_action_jump_to_table_index *)
2889 : 0 : actions->conf)->table;
2890 : 0 : acts->rule_acts[dr_pos].jump_to_matcher.offset =
2891 : : ((const struct rte_flow_action_jump_to_table_index *)
2892 : 0 : actions->conf)->index;
2893 [ # # ]: 0 : if (likely(!rte_flow_template_table_resizable(dev->data->port_id,
2894 : : &jump_table->cfg.attr))) {
2895 : 0 : acts->rule_acts[dr_pos].action =
2896 : 0 : jump_table->matcher_info[0].jump;
2897 : : } else {
2898 : : uint32_t selector;
2899 : 0 : rte_rwlock_read_lock(&jump_table->matcher_replace_rwlk);
2900 : 0 : selector = jump_table->matcher_selector;
2901 : 0 : acts->rule_acts[dr_pos].action =
2902 : 0 : jump_table->matcher_info[selector].jump;
2903 : : rte_rwlock_read_unlock(&jump_table->matcher_replace_rwlk);
2904 : : }
2905 : : } else if (__flow_hw_act_data_general_append
2906 : : (priv, acts, actions->type,
2907 : : src_pos, dr_pos)){
2908 : 0 : goto err;
2909 : : }
2910 : : break;
2911 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_MIRROR:
2912 : : if (__flow_hw_act_data_general_append(priv, acts,
2913 : : actions->type,
2914 : : src_pos, dr_pos))
2915 : 0 : goto err;
2916 : : break;
2917 : 0 : case RTE_FLOW_ACTION_TYPE_END:
2918 : : actions_end = true;
2919 : 0 : break;
2920 : : default:
2921 : : break;
2922 : : }
2923 : : }
2924 [ # # ]: 0 : if (mhdr.pos != UINT16_MAX) {
2925 : 0 : ret = mlx5_tbl_translate_modify_header(dev, cfg, acts, mp_ctx, &mhdr, &sub_error);
2926 [ # # ]: 0 : if (ret)
2927 : 0 : goto err;
2928 [ # # # # ]: 0 : if (!nt_mode && mhdr.shared) {
2929 : 0 : ret = mlx5_tbl_ensure_shared_modify_header(dev, cfg, acts, &sub_error);
2930 [ # # ]: 0 : if (ret)
2931 : 0 : goto err;
2932 : : }
2933 : : }
2934 [ # # ]: 0 : if (reformat_used) {
2935 : 0 : ret = mlx5_tbl_translate_reformat(priv, acts, at,
2936 : : enc_item, enc_item_m,
2937 : : encap_data, encap_data_m,
2938 : : mp_ctx, data_size,
2939 : : reformat_src,
2940 : : refmt_type, &sub_error);
2941 [ # # ]: 0 : if (ret)
2942 : 0 : goto err;
2943 [ # # # # ]: 0 : if (!nt_mode && acts->encap_decap->shared) {
2944 : 0 : ret = mlx5_tbl_create_reformat_action(priv, table_attr, acts, at,
2945 : : encap_data, data_size,
2946 : : refmt_type);
2947 [ # # ]: 0 : if (ret)
2948 : 0 : goto err;
2949 : : }
2950 : : }
2951 [ # # ]: 0 : if (recom_used) {
2952 : : MLX5_ASSERT(at->recom_off != UINT16_MAX);
2953 : 0 : ret = mlx5_create_ipv6_ext_reformat(dev, cfg, acts, at, push_data,
2954 : : push_data_m, push_size, recom_src,
2955 : : recom_type);
2956 [ # # ]: 0 : if (ret)
2957 : 0 : goto err;
2958 : : }
2959 : : return 0;
2960 : 0 : err:
2961 : : /* If rte_errno was not initialized and reached error state. */
2962 [ # # ]: 0 : if (!rte_errno)
2963 : 0 : rte_errno = EINVAL;
2964 : 0 : err = rte_errno;
2965 : : __flow_hw_action_template_destroy(dev, acts);
2966 [ # # # # ]: 0 : if (error != NULL && sub_error.type != RTE_FLOW_ERROR_TYPE_NONE) {
2967 : : rte_memcpy(error, &sub_error, sizeof(sub_error));
2968 : 0 : return -EINVAL;
2969 : : }
2970 : 0 : return rte_flow_error_set(error, err,
2971 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2972 : : "fail to create rte table");
2973 : : }
2974 : :
2975 : : /**
2976 : : * Translate rte_flow actions to DR action.
2977 : : *
2978 : : * As the action template has already indicated the actions. Translate
2979 : : * the rte_flow actions to DR action if possible. So in flow create
2980 : : * stage we will save cycles from handing the actions' organizing.
2981 : : * For the actions with limited information, need to add these to a
2982 : : * list.
2983 : : *
2984 : : * @param[in] dev
2985 : : * Pointer to the rte_eth_dev structure.
2986 : : * @param[in] cfg
2987 : : * Pointer to the table configuration.
2988 : : * @param[in/out] acts
2989 : : * Pointer to the template HW steering DR actions.
2990 : : * @param[in] at
2991 : : * Action template.
2992 : : * @param[out] error
2993 : : * Pointer to error structure.
2994 : : *
2995 : : * @return
2996 : : * 0 on success, a negative errno otherwise and rte_errno is set.
2997 : : */
2998 : : static int
2999 : : flow_hw_translate_actions_template(struct rte_eth_dev *dev,
3000 : : const struct mlx5_flow_template_table_cfg *cfg,
3001 : : struct mlx5_hw_actions *acts,
3002 : : struct rte_flow_actions_template *at,
3003 : : struct mlx5_tbl_multi_pattern_ctx *mp_ctx,
3004 : : struct rte_flow_error *error)
3005 : : {
3006 : 0 : return __flow_hw_translate_actions_template(dev, cfg, acts, at, mp_ctx, false, error);
3007 : : }
3008 : :
3009 : : static __rte_always_inline struct mlx5dr_rule_action *
3010 : : flow_hw_get_dr_action_buffer(struct mlx5_priv *priv,
3011 : : struct rte_flow_template_table *table,
3012 : : uint8_t action_template_index,
3013 : : uint32_t queue)
3014 : : {
3015 : 0 : uint32_t offset = action_template_index * priv->nb_queue + queue;
3016 : :
3017 : 0 : return &table->rule_acts[offset].acts[0];
3018 : : }
3019 : :
3020 : : static void
3021 : 0 : flow_hw_populate_rule_acts_caches(struct rte_eth_dev *dev,
3022 : : struct rte_flow_template_table *table,
3023 : : uint8_t at_idx)
3024 : : {
3025 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
3026 : : uint32_t q;
3027 : :
3028 [ # # ]: 0 : for (q = 0; q < priv->nb_queue; ++q) {
3029 : : struct mlx5dr_rule_action *rule_acts =
3030 : 0 : flow_hw_get_dr_action_buffer(priv, table, at_idx, q);
3031 : :
3032 [ # # ]: 0 : rte_memcpy(rule_acts, table->ats[at_idx].acts.rule_acts,
3033 : : sizeof(table->ats[at_idx].acts.rule_acts));
3034 : : }
3035 : 0 : }
3036 : :
3037 : : /**
3038 : : * Translate rte_flow actions to DR action.
3039 : : *
3040 : : * @param[in] dev
3041 : : * Pointer to the rte_eth_dev structure.
3042 : : * @param[in] tbl
3043 : : * Pointer to the flow template table.
3044 : : * @param[out] error
3045 : : * Pointer to error structure.
3046 : : *
3047 : : * @return
3048 : : * 0 on success, negative value otherwise and rte_errno is set.
3049 : : */
3050 : : static int
3051 : 0 : flow_hw_translate_all_actions_templates(struct rte_eth_dev *dev,
3052 : : struct rte_flow_template_table *tbl,
3053 : : struct rte_flow_error *error)
3054 : : {
3055 : : int ret;
3056 : : uint32_t i;
3057 : :
3058 [ # # ]: 0 : for (i = 0; i < tbl->nb_action_templates; i++) {
3059 [ # # ]: 0 : if (flow_hw_translate_actions_template(dev, &tbl->cfg,
3060 : : &tbl->ats[i].acts,
3061 : : tbl->ats[i].action_template,
3062 : : &tbl->mpctx, error))
3063 : 0 : goto err;
3064 : 0 : flow_hw_populate_rule_acts_caches(dev, tbl, i);
3065 : : }
3066 [ # # ]: 0 : ret = mlx5_tbl_multi_pattern_process(dev, tbl, &tbl->mpctx.segments[0],
3067 : : rte_log2_u32(tbl->cfg.attr.nb_flows),
3068 : : error);
3069 [ # # ]: 0 : if (ret)
3070 : 0 : goto err;
3071 : : return 0;
3072 : : err:
3073 [ # # ]: 0 : while (i--)
3074 : 0 : __flow_hw_action_template_destroy(dev, &tbl->ats[i].acts);
3075 : : return -1;
3076 : : }
3077 : :
3078 : : /**
3079 : : * Get shared indirect action.
3080 : : *
3081 : : * @param[in] dev
3082 : : * Pointer to the rte_eth_dev data structure.
3083 : : * @param[in] act_data
3084 : : * Pointer to the recorded action construct data.
3085 : : * @param[in] item_flags
3086 : : * The matcher itme_flags used for RSS lookup.
3087 : : * @param[in] rule_act
3088 : : * Pointer to the shared action's destination rule DR action.
3089 : : *
3090 : : * @return
3091 : : * 0 on success, negative value otherwise and rte_errno is set.
3092 : : */
3093 : : static __rte_always_inline int
3094 : : flow_hw_shared_action_get(struct rte_eth_dev *dev,
3095 : : struct mlx5_action_construct_data *act_data,
3096 : : const uint64_t item_flags,
3097 : : struct mlx5dr_rule_action *rule_act)
3098 : : {
3099 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
3100 : 0 : struct mlx5_flow_rss_desc rss_desc = { 0 };
3101 : 0 : uint64_t hash_fields = 0;
3102 : : uint32_t hrxq_idx = 0;
3103 : : struct mlx5_hrxq *hrxq = NULL;
3104 : : int act_type = act_data->type;
3105 : :
3106 : : switch (act_type) {
3107 : : case MLX5_RTE_FLOW_ACTION_TYPE_RSS:
3108 : 0 : rss_desc.level = act_data->shared_rss.level;
3109 : 0 : rss_desc.types = act_data->shared_rss.types;
3110 : 0 : rss_desc.symmetric_hash_function = act_data->shared_rss.symmetric_hash_function;
3111 : 0 : flow_dv_hashfields_set(item_flags, &rss_desc, &hash_fields);
3112 : 0 : hrxq_idx = flow_dv_action_rss_hrxq_lookup
3113 : : (dev, act_data->shared_rss.idx, hash_fields);
3114 [ # # # # : 0 : if (hrxq_idx)
# # # # #
# # # # #
# # # # #
# ]
3115 : 0 : hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
3116 : : hrxq_idx);
3117 [ # # # # : 0 : if (hrxq) {
# # # # #
# # # # #
# # # # #
# ]
3118 : 0 : rule_act->action = hrxq->action;
3119 : : return 0;
3120 : : }
3121 : : break;
3122 : : default:
3123 : : DRV_LOG(WARNING, "Unsupported shared action type:%d",
3124 : : act_data->type);
3125 : : break;
3126 : : }
3127 : : return -1;
3128 : : }
3129 : :
3130 : : static void
3131 : 0 : flow_hw_construct_quota(struct mlx5_priv *priv,
3132 : : struct mlx5dr_rule_action *rule_act, uint32_t qid)
3133 : : {
3134 : 0 : rule_act->action = priv->quota_ctx.dr_action;
3135 : 0 : rule_act->aso_meter.offset = qid - 1;
3136 : 0 : rule_act->aso_meter.init_color =
3137 : : MLX5DR_ACTION_ASO_METER_COLOR_GREEN;
3138 : 0 : }
3139 : :
3140 : : /**
3141 : : * Construct shared indirect action.
3142 : : *
3143 : : * @param[in] dev
3144 : : * Pointer to the rte_eth_dev data structure.
3145 : : * @param[in] queue
3146 : : * The flow creation queue index.
3147 : : * @param[in] action
3148 : : * Pointer to the shared indirect rte_flow action.
3149 : : * @param[in] table
3150 : : * Pointer to the flow table.
3151 : : * @param[in] item_flags
3152 : : * Item flags.
3153 : : * @param[in] action_flags
3154 : : * Actions bit-map detected in this template.
3155 : : * @param[in, out] flow
3156 : : * Pointer to the flow containing the counter.
3157 : : * @param[in] rule_act
3158 : : * Pointer to the shared action's destination rule DR action.
3159 : : *
3160 : : * @return
3161 : : * 0 on success, negative value otherwise and rte_errno is set.
3162 : : */
3163 : : static __rte_always_inline int
3164 : : flow_hw_shared_action_construct(struct rte_eth_dev *dev, uint32_t queue,
3165 : : const struct rte_flow_action *action,
3166 : : struct rte_flow_template_table *table __rte_unused,
3167 : : const uint64_t item_flags, uint64_t action_flags,
3168 : : struct rte_flow_hw *flow,
3169 : : struct mlx5dr_rule_action *rule_act)
3170 : : {
3171 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
3172 : 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
3173 : : struct mlx5_action_construct_data act_data;
3174 : : struct mlx5_shared_action_rss *shared_rss;
3175 : : struct mlx5_aso_mtr *aso_mtr;
3176 : : struct mlx5_age_info *age_info;
3177 : : struct mlx5_hws_age_param *param;
3178 : : struct rte_flow_hw_aux *aux;
3179 : 0 : uint32_t act_idx = (uint32_t)(uintptr_t)action->conf;
3180 : 0 : uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
3181 : 0 : uint32_t idx = act_idx &
3182 : : ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
3183 : : cnt_id_t age_cnt;
3184 : :
3185 : : memset(&act_data, 0, sizeof(act_data));
3186 [ # # # # : 0 : switch (type) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3187 : 0 : case MLX5_INDIRECT_ACTION_TYPE_RSS:
3188 : 0 : act_data.type = MLX5_RTE_FLOW_ACTION_TYPE_RSS;
3189 : 0 : shared_rss = mlx5_ipool_get
3190 : 0 : (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
3191 [ # # # # : 0 : if (!shared_rss)
# # # # #
# ]
3192 : : return -1;
3193 : 0 : act_data.shared_rss.idx = idx;
3194 : 0 : act_data.shared_rss.level = shared_rss->origin.level;
3195 : 0 : act_data.shared_rss.types = !shared_rss->origin.types ?
3196 [ # # # # : 0 : RTE_ETH_RSS_IP :
# # # # #
# ]
3197 : : shared_rss->origin.types;
3198 : 0 : act_data.shared_rss.symmetric_hash_function =
3199 : 0 : MLX5_RSS_IS_SYMM(shared_rss->origin.func);
3200 : :
3201 : : if (flow_hw_shared_action_get
3202 : : (dev, &act_data, item_flags, rule_act))
3203 : : return -1;
3204 : : break;
3205 : 0 : case MLX5_INDIRECT_ACTION_TYPE_COUNT:
3206 : 0 : if (mlx5_hws_cnt_pool_get_action_offset(priv->hws_cpool,
3207 : : act_idx,
3208 : : &rule_act->action,
3209 : : &rule_act->counter.offset))
3210 : : return -1;
3211 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_CNT_ID;
3212 : 0 : flow->cnt_id = act_idx;
3213 : : break;
3214 : 0 : case MLX5_INDIRECT_ACTION_TYPE_AGE:
3215 [ # # # # : 0 : aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
# # # # #
# ]
3216 : : /*
3217 : : * Save the index with the indirect type, to recognize
3218 : : * it in flow destroy.
3219 : : */
3220 : : mlx5_flow_hw_aux_set_age_idx(flow, aux, act_idx);
3221 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_AGE_IDX;
3222 [ # # # # : 0 : if (action_flags & MLX5_FLOW_ACTION_INDIRECT_COUNT)
# # # # #
# ]
3223 : : /*
3224 : : * The mutual update for idirect AGE & COUNT will be
3225 : : * performed later after we have ID for both of them.
3226 : : */
3227 : : break;
3228 : 0 : age_info = GET_PORT_AGE_INFO(priv);
3229 : 0 : param = mlx5_ipool_get(age_info->ages_ipool, idx);
3230 [ # # # # : 0 : if (param == NULL)
# # # # #
# ]
3231 : : return -1;
3232 [ # # # # : 0 : if (action_flags & MLX5_FLOW_ACTION_COUNT) {
# # # # #
# ]
3233 [ # # # # : 0 : if (mlx5_hws_cnt_pool_get(priv->hws_cpool,
# # # # #
# # # # #
# # # # #
# ]
3234 : : ¶m->queue_id, &age_cnt,
3235 : : idx) < 0)
3236 : : return -1;
3237 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_CNT_ID;
3238 : 0 : flow->cnt_id = age_cnt;
3239 : 0 : param->nb_cnts++;
3240 : : } else {
3241 : : /*
3242 : : * Get the counter of this indirect AGE or create one
3243 : : * if doesn't exist.
3244 : : */
3245 : : age_cnt = mlx5_hws_age_cnt_get(priv, param, idx);
3246 [ # # # # : 0 : if (age_cnt == 0)
# # # # #
# ]
3247 : : return -1;
3248 : : }
3249 : 0 : if (mlx5_hws_cnt_pool_get_action_offset(priv->hws_cpool,
3250 : : age_cnt, &rule_act->action,
3251 : : &rule_act->counter.offset))
3252 : : return -1;
3253 : : break;
3254 : : case MLX5_INDIRECT_ACTION_TYPE_CT:
3255 : : if (flow_hw_ct_compile(dev, queue, idx, rule_act))
3256 : : return -1;
3257 : : break;
3258 : 0 : case MLX5_INDIRECT_ACTION_TYPE_METER_MARK:
3259 : : /* Find ASO object. */
3260 : 0 : aso_mtr = mlx5_ipool_get(pool->idx_pool, idx);
3261 [ # # # # : 0 : if (!aso_mtr)
# # # # #
# ]
3262 : : return -1;
3263 : 0 : rule_act->action = pool->action;
3264 : 0 : rule_act->aso_meter.offset = aso_mtr->offset;
3265 : : break;
3266 : 0 : case MLX5_INDIRECT_ACTION_TYPE_QUOTA:
3267 : 0 : flow_hw_construct_quota(priv, rule_act, idx);
3268 : : break;
3269 : 0 : default:
3270 : 0 : DRV_LOG(WARNING, "Unsupported shared action type:%d", type);
3271 : : break;
3272 : : }
3273 : : return 0;
3274 : : }
3275 : :
3276 : : static __rte_always_inline int
3277 : : flow_hw_mhdr_cmd_is_nop(const struct mlx5_modification_cmd *cmd)
3278 : : {
3279 : : struct mlx5_modification_cmd cmd_he = {
3280 : 0 : .data0 = rte_be_to_cpu_32(cmd->data0),
3281 : : .data1 = 0,
3282 : : };
3283 : :
3284 : 0 : return cmd_he.action_type == MLX5_MODIFICATION_TYPE_NOP;
3285 : : }
3286 : :
3287 : : /**
3288 : : * Construct flow action array.
3289 : : *
3290 : : * For action template contains dynamic actions, these actions need to
3291 : : * be updated according to the rte_flow action during flow creation.
3292 : : *
3293 : : * @param[in] dev
3294 : : * Pointer to the rte_eth_dev structure.
3295 : : * @param[in] job
3296 : : * Pointer to job descriptor.
3297 : : * @param[in] hw_acts
3298 : : * Pointer to translated actions from template.
3299 : : * @param[in] it_idx
3300 : : * Item template index the action template refer to.
3301 : : * @param[in] actions
3302 : : * Array of rte_flow action need to be checked.
3303 : : * @param[in] rule_acts
3304 : : * Array of DR rule actions to be used during flow creation..
3305 : : * @param[in] acts_num
3306 : : * Pointer to the real acts_num flow has.
3307 : : *
3308 : : * @return
3309 : : * 0 on success, negative value otherwise and rte_errno is set.
3310 : : */
3311 : : static __rte_always_inline int
3312 : : flow_hw_modify_field_construct(struct mlx5_modification_cmd *mhdr_cmd,
3313 : : struct mlx5_action_construct_data *act_data,
3314 : : const struct mlx5_hw_actions *hw_acts,
3315 : : const struct rte_flow_action *action)
3316 : : {
3317 : 0 : const struct rte_flow_action_modify_field *mhdr_action = action->conf;
3318 : 0 : uint8_t values[16] = { 0 };
3319 : : unaligned_uint32_t *value_p;
3320 : : uint32_t i;
3321 : : struct field_modify_info *field;
3322 : :
3323 [ # # # # : 0 : if (!hw_acts->mhdr)
# # # # #
# ]
3324 : : return -1;
3325 [ # # # # : 0 : if (hw_acts->mhdr->shared || act_data->modify_header.shared)
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3326 : : return 0;
3327 : : MLX5_ASSERT(mhdr_action->operation == RTE_FLOW_MODIFY_SET ||
3328 : : mhdr_action->operation == RTE_FLOW_MODIFY_ADD);
3329 [ # # # # : 0 : if (mhdr_action->src.field != RTE_FLOW_FIELD_VALUE &&
# # # # #
# ]
3330 : : mhdr_action->src.field != RTE_FLOW_FIELD_POINTER)
3331 : : return 0;
3332 [ # # # # : 0 : if (mhdr_action->src.field == RTE_FLOW_FIELD_VALUE)
# # # # #
# ]
3333 [ # # # # : 0 : rte_memcpy(values, &mhdr_action->src.value, sizeof(values));
# # # # #
# ]
3334 : : else
3335 [ # # # # : 0 : rte_memcpy(values, mhdr_action->src.pvalue, sizeof(values));
# # # # #
# ]
3336 [ # # # # : 0 : if (mhdr_action->dst.field == RTE_FLOW_FIELD_META ||
# # # # #
# ]
3337 [ # # # # : 0 : mhdr_action->dst.field == RTE_FLOW_FIELD_TAG ||
# # # # #
# ]
3338 [ # # # # : 0 : mhdr_action->dst.field == RTE_FLOW_FIELD_METER_COLOR ||
# # # # #
# ]
3339 : : mhdr_action->dst.field == (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG) {
3340 : 0 : uint8_t tag_index = flow_tag_index_get(&mhdr_action->dst);
3341 : :
3342 : : value_p = (unaligned_uint32_t *)values;
3343 [ # # # # : 0 : if (mhdr_action->dst.field == RTE_FLOW_FIELD_TAG &&
# # # # #
# # # # #
# # # # #
# ]
3344 : : tag_index == RTE_PMD_MLX5_LINEAR_HASH_TAG_INDEX)
3345 [ # # # # : 0 : *value_p = rte_cpu_to_be_32(*value_p << 16);
# # # # #
# ]
3346 : : else
3347 [ # # # # : 0 : *value_p = rte_cpu_to_be_32(*value_p);
# # # # #
# ]
3348 [ # # # # : 0 : } else if (mhdr_action->dst.field == RTE_FLOW_FIELD_GTP_PSC_QFI ||
# # # # #
# ]
3349 : : mhdr_action->dst.field == RTE_FLOW_FIELD_GENEVE_OPT_TYPE) {
3350 : : uint32_t tmp;
3351 : :
3352 : : /*
3353 : : * Both QFI and Geneve option type are passed as an uint8_t integer,
3354 : : * but it is accessed through a 2nd least significant byte of a 32-bit
3355 : : * field in modify header command.
3356 : : */
3357 : 0 : tmp = values[0];
3358 : : value_p = (unaligned_uint32_t *)values;
3359 [ # # # # : 0 : *value_p = rte_cpu_to_be_32(tmp << 8);
# # # # #
# ]
3360 : : }
3361 : 0 : i = act_data->modify_header.mhdr_cmds_off;
3362 : 0 : field = act_data->modify_header.field;
3363 : : do {
3364 : : uint32_t off_b;
3365 : : uint32_t mask;
3366 : : uint32_t data;
3367 : : const uint8_t *mask_src;
3368 : :
3369 [ # # # # : 0 : if (i >= act_data->modify_header.mhdr_cmds_end)
# # # # #
# # # # #
# # # # #
# ]
3370 : : return -1;
3371 [ # # # # : 0 : if (flow_hw_mhdr_cmd_is_nop(&mhdr_cmd[i])) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3372 : 0 : ++i;
3373 : 0 : continue;
3374 : : }
3375 : 0 : mask_src = (const uint8_t *)act_data->modify_header.mask;
3376 : 0 : mask = flow_dv_fetch_field(mask_src + field->offset, field->size);
3377 [ # # # # : 0 : if (!mask) {
# # # # #
# # # # #
# # # # #
# ]
3378 : 0 : ++field;
3379 : 0 : continue;
3380 : : }
3381 : 0 : off_b = rte_bsf32(mask);
3382 : 0 : data = flow_dv_fetch_field(values + field->offset, field->size);
3383 : : /*
3384 : : * IPv6 DSCP uses OUT_IPV6_TRAFFIC_CLASS as ID but it starts from 2
3385 : : * bits left. Shift the data left for IPv6 DSCP
3386 : : */
3387 [ # # # # : 0 : if (field->id == MLX5_MODI_OUT_IPV6_TRAFFIC_CLASS &&
# # # # #
# # # #
# ]
3388 [ # # # # : 0 : mhdr_action->dst.field == RTE_FLOW_FIELD_IPV6_DSCP)
# # ]
3389 : 0 : data <<= MLX5_IPV6_HDR_DSCP_SHIFT;
3390 : 0 : data = (data & mask) >> off_b;
3391 [ # # # # : 0 : mhdr_cmd[i++].data1 = rte_cpu_to_be_32(data);
# # # # #
# # # # #
# # # # #
# ]
3392 : 0 : ++field;
3393 [ # # # # : 0 : } while (field->size);
# # # # #
# # # # #
# # # # #
# ]
3394 : : return 0;
3395 : : }
3396 : :
3397 : : /**
3398 : : * Release any actions allocated for the flow rule during actions construction.
3399 : : *
3400 : : * @param[in] flow
3401 : : * Pointer to flow structure.
3402 : : */
3403 : : static void
3404 : 0 : flow_hw_release_actions(struct rte_eth_dev *dev,
3405 : : uint32_t queue,
3406 : : struct rte_flow_hw *flow)
3407 : : {
3408 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
3409 : 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
3410 [ # # ]: 0 : struct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
3411 : :
3412 [ # # ]: 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_FATE_JUMP)
3413 : 0 : flow_hw_jump_release(dev, flow->jump);
3414 [ # # ]: 0 : else if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_FATE_HRXQ)
3415 : 0 : mlx5_hrxq_obj_release(dev, flow->hrxq);
3416 [ # # ]: 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_CNT_ID)
3417 : 0 : flow_hw_age_count_release(priv, queue, flow, NULL);
3418 [ # # ]: 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_MTR_ID)
3419 : 0 : mlx5_ipool_free(pool->idx_pool, mlx5_flow_hw_aux_get_mtr_id(flow, aux));
3420 : 0 : }
3421 : :
3422 : : /**
3423 : : * Construct flow action array.
3424 : : *
3425 : : * For action template contains dynamic actions, these actions need to
3426 : : * be updated according to the rte_flow action during flow creation.
3427 : : *
3428 : : * @param[in] dev
3429 : : * Pointer to the rte_eth_dev structure.
3430 : : * @param[in] flow
3431 : : * Pointer to flow structure.
3432 : : * @param[in] ap
3433 : : * Pointer to container for temporarily constructed actions' parameters.
3434 : : * @param[in] hw_acts
3435 : : * Pointer to translated actions from template.
3436 : : * @param[in] items_flags
3437 : : * Item flags.
3438 : : * @param[in] table
3439 : : * Pointer to the template table.
3440 : : * @param[in] actions
3441 : : * Array of rte_flow action need to be checked.
3442 : : * @param[in] rule_acts
3443 : : * Array of DR rule actions to be used during flow creation..
3444 : : * @param[in] acts_num
3445 : : * Pointer to the real acts_num flow has.
3446 : : *
3447 : : * @return
3448 : : * 0 on success, negative value otherwise and rte_errno is set.
3449 : : */
3450 : : static __rte_always_inline int
3451 : : flow_hw_actions_construct(struct rte_eth_dev *dev,
3452 : : struct rte_flow_hw *flow,
3453 : : struct mlx5_flow_hw_action_params *ap,
3454 : : const struct mlx5_hw_action_template *hw_at,
3455 : : uint64_t item_flags,
3456 : : struct rte_flow_template_table *table,
3457 : : const struct rte_flow_action actions[],
3458 : : struct mlx5dr_rule_action *rule_acts,
3459 : : uint32_t queue,
3460 : : struct rte_flow_error *error)
3461 : : {
3462 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
3463 : 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
3464 : : struct mlx5_action_construct_data *act_data;
3465 : 0 : const struct rte_flow_actions_template *at = hw_at->action_template;
3466 : : const struct mlx5_hw_actions *hw_acts = &hw_at->acts;
3467 : : const struct rte_flow_action *action;
3468 : : const struct rte_flow_action_raw_encap *raw_encap_data;
3469 : : const struct rte_flow_action_ipv6_ext_push *ipv6_push;
3470 : : const struct rte_flow_item *enc_item = NULL;
3471 : : const struct rte_flow_action_ethdev *port_action = NULL;
3472 : : const struct rte_flow_action_age *age = NULL;
3473 : : const struct rte_flow_action_nat64 *nat64_c = NULL;
3474 : 0 : struct rte_flow_attr attr = {
3475 : : .ingress = 1,
3476 : : };
3477 : : uint32_t ft_flag;
3478 : : int ret;
3479 : 0 : size_t encap_len = 0;
3480 : : uint32_t age_idx = 0;
3481 : : uint32_t mtr_idx = 0;
3482 : : struct mlx5_aso_mtr *aso_mtr;
3483 : : struct mlx5_multi_pattern_segment *mp_segment = NULL;
3484 : : struct rte_flow_hw_aux *aux;
3485 : :
3486 : 0 : attr.group = table->grp->group_id;
3487 : 0 : ft_flag = mlx5_hw_act_flag[!!table->grp->group_id][table->type];
3488 : 0 : if (table->type >= MLX5DR_TABLE_TYPE_FDB && table->type < MLX5DR_TABLE_TYPE_MAX) {
3489 : 0 : attr.transfer = 1;
3490 : : attr.ingress = 1;
3491 [ # # # # : 0 : } else if (table->type == MLX5DR_TABLE_TYPE_NIC_TX) {
# # # # #
# ]
3492 : 0 : attr.egress = 1;
3493 : 0 : attr.ingress = 0;
3494 : : } else {
3495 : : attr.ingress = 1;
3496 : : }
3497 [ # # # # : 0 : if (hw_acts->mhdr && hw_acts->mhdr->mhdr_cmds_num > 0 && !hw_acts->mhdr->shared) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3498 : 0 : uint16_t pos = hw_acts->mhdr->pos;
3499 : :
3500 : 0 : mp_segment = mlx5_multi_pattern_segment_find(table, flow->res_idx);
3501 [ # # # # : 0 : if (!mp_segment || !mp_segment->mhdr_action)
# # # # #
# # # # #
# # # # #
# ]
3502 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3503 : : NULL, "No modify header action found");
3504 : 0 : rule_acts[pos].action = mp_segment->mhdr_action;
3505 : : /* offset is relative to DR action */
3506 : 0 : rule_acts[pos].modify_header.offset =
3507 : 0 : flow->res_idx - mp_segment->head_index;
3508 : 0 : rule_acts[pos].modify_header.data =
3509 : 0 : (uint8_t *)ap->mhdr_cmd;
3510 : : MLX5_ASSERT(hw_acts->mhdr->mhdr_cmds_num <= MLX5_MHDR_MAX_CMD);
3511 : 0 : rte_memcpy(ap->mhdr_cmd, hw_acts->mhdr->mhdr_cmds,
3512 [ # # # # : 0 : sizeof(*ap->mhdr_cmd) * hw_acts->mhdr->mhdr_cmds_num);
# # # # #
# ]
3513 : : }
3514 [ # # # # : 0 : LIST_FOREACH(act_data, &hw_acts->act_list, next) {
# # # # #
# ]
3515 : : uint32_t jump_group;
3516 : : uint32_t tag;
3517 : : struct mlx5_hw_jump_action *jump;
3518 : : struct mlx5_hrxq *hrxq;
3519 : : uint32_t ct_idx;
3520 : : cnt_id_t cnt_id;
3521 : : uint32_t *cnt_queue;
3522 : : uint32_t mtr_id;
3523 : : struct rte_flow_template_table *jump_table;
3524 : :
3525 : 0 : action = &actions[act_data->action_src];
3526 : : /*
3527 : : * action template construction replaces
3528 : : * OF_SET_VLAN_VID with MODIFY_FIELD
3529 : : */
3530 : 0 : if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)
3531 : : MLX5_ASSERT(act_data->type ==
3532 : : RTE_FLOW_ACTION_TYPE_MODIFY_FIELD);
3533 : : else
3534 : : MLX5_ASSERT(action->type ==
3535 : : RTE_FLOW_ACTION_TYPE_INDIRECT ||
3536 : : (int)action->type == act_data->type);
3537 [ # # # # : 0 : switch ((int)act_data->type) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3538 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT_LIST:
3539 : 0 : act_data->indirect_list_cb(dev, act_data, action,
3540 : 0 : &rule_acts[act_data->action_dst]);
3541 : 0 : break;
3542 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT:
3543 : 0 : if (flow_hw_shared_action_construct
3544 : : (dev, queue, action, table,
3545 : 0 : item_flags, at->action_flags, flow,
3546 [ # # # # : 0 : &rule_acts[act_data->action_dst]))
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3547 : 0 : goto error;
3548 : : break;
3549 : : case RTE_FLOW_ACTION_TYPE_VOID:
3550 : : break;
3551 : 0 : case RTE_FLOW_ACTION_TYPE_MARK:
3552 : 0 : tag = mlx5_flow_mark_set
3553 : : (((const struct rte_flow_action_mark *)
3554 : 0 : (action->conf))->id);
3555 : 0 : rule_acts[act_data->action_dst].tag.value = tag;
3556 : 0 : break;
3557 : 0 : case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
3558 : 0 : rule_acts[act_data->action_dst].push_vlan.vlan_hdr =
3559 : 0 : vlan_hdr_to_be32(action);
3560 : 0 : break;
3561 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP:
3562 : 0 : jump_group = ((const struct rte_flow_action_jump *)
3563 : 0 : action->conf)->group;
3564 : 0 : jump = flow_hw_jump_action_register
3565 : 0 : (dev, &table->cfg, jump_group, NULL);
3566 [ # # # # : 0 : if (!jump)
# # # # #
# ]
3567 : 0 : goto error;
3568 : 0 : rule_acts[act_data->action_dst].action =
3569 [ # # # # : 0 : (!!attr.group) ? jump->hws_action : jump->root_action;
# # # # #
# ]
3570 : 0 : flow->jump = jump;
3571 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_FATE_JUMP;
3572 : 0 : break;
3573 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
3574 : : case RTE_FLOW_ACTION_TYPE_QUEUE:
3575 : 0 : hrxq = flow_hw_tir_action_register(dev, ft_flag, action);
3576 [ # # # # : 0 : if (!hrxq)
# # # # #
# ]
3577 : 0 : goto error;
3578 : 0 : rule_acts[act_data->action_dst].action = hrxq->action;
3579 : 0 : flow->hrxq = hrxq;
3580 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_FATE_HRXQ;
3581 : 0 : break;
3582 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_RSS:
3583 : 0 : if (flow_hw_shared_action_get
3584 : : (dev, act_data, item_flags,
3585 : 0 : &rule_acts[act_data->action_dst]))
3586 : 0 : goto error;
3587 : : break;
3588 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
3589 : 0 : enc_item = ((const struct rte_flow_action_vxlan_encap *)
3590 : 0 : action->conf)->definition;
3591 [ # # # # : 0 : if (flow_dv_convert_encap_data(enc_item, ap->encap_data, &encap_len, NULL))
# # # # #
# ]
3592 : 0 : goto error;
3593 : : break;
3594 : 0 : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
3595 : 0 : enc_item = ((const struct rte_flow_action_nvgre_encap *)
3596 : 0 : action->conf)->definition;
3597 [ # # # # : 0 : if (flow_dv_convert_encap_data(enc_item, ap->encap_data, &encap_len, NULL))
# # # # #
# ]
3598 : 0 : goto error;
3599 : : break;
3600 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
3601 : 0 : raw_encap_data =
3602 : : (const struct rte_flow_action_raw_encap *)
3603 : : action->conf;
3604 : : MLX5_ASSERT(raw_encap_data->size == act_data->encap.len);
3605 [ # # # # : 0 : if (unlikely(act_data->encap.len > MLX5_ENCAP_MAX_LEN))
# # # # #
# ]
3606 : : return -1;
3607 [ # # # # : 0 : rte_memcpy(ap->encap_data, raw_encap_data->data, act_data->encap.len);
# # # # #
# ]
3608 : : break;
3609 : 0 : case RTE_FLOW_ACTION_TYPE_IPV6_EXT_PUSH:
3610 : 0 : ipv6_push =
3611 : : (const struct rte_flow_action_ipv6_ext_push *)action->conf;
3612 : : MLX5_ASSERT(ipv6_push->size == act_data->ipv6_ext.len);
3613 [ # # # # : 0 : if (unlikely(act_data->ipv6_ext.len > MLX5_PUSH_MAX_LEN))
# # # # #
# ]
3614 : : return -1;
3615 [ # # # # : 0 : rte_memcpy(ap->ipv6_push_data, ipv6_push->data,
# # # # #
# ]
3616 : : act_data->ipv6_ext.len);
3617 : : break;
3618 : 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
3619 [ # # # # : 0 : if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)
# # # # #
# ]
3620 : 0 : ret = flow_hw_set_vlan_vid_construct(dev, ap->mhdr_cmd,
3621 : : act_data,
3622 : : hw_acts,
3623 : : action);
3624 : : else
3625 [ # # # # : 0 : ret = flow_hw_modify_field_construct(ap->mhdr_cmd,
# # # # #
# ]
3626 : : act_data,
3627 : : hw_acts,
3628 : : action);
3629 [ # # # # : 0 : if (ret)
# # # # #
# ]
3630 : 0 : goto error;
3631 : : break;
3632 : 0 : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
3633 : 0 : port_action = action->conf;
3634 [ # # # # : 0 : if (!priv->hw_vport[port_action->port_id])
# # # # #
# ]
3635 : 0 : goto error;
3636 : 0 : rule_acts[act_data->action_dst].action =
3637 : : priv->hw_vport[port_action->port_id];
3638 : 0 : break;
3639 : 0 : case RTE_FLOW_ACTION_TYPE_QUOTA:
3640 : 0 : flow_hw_construct_quota(priv,
3641 : 0 : rule_acts + act_data->action_dst,
3642 : : act_data->shared_meter.id);
3643 : 0 : break;
3644 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
3645 [ # # # # : 0 : aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
# # # # #
# ]
3646 : 0 : age = action->conf;
3647 : : /*
3648 : : * First, create the AGE parameter, then create its
3649 : : * counter later:
3650 : : * Regular counter - in next case.
3651 : : * Indirect counter - update it after the loop.
3652 : : */
3653 : 0 : age_idx = mlx5_hws_age_action_create(priv, queue, 0,
3654 : : age,
3655 : : flow->res_idx,
3656 : : error);
3657 [ # # # # : 0 : if (age_idx == 0)
# # # # #
# ]
3658 : 0 : goto error;
3659 : : mlx5_flow_hw_aux_set_age_idx(flow, aux, age_idx);
3660 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_AGE_IDX;
3661 [ # # # # : 0 : if (at->action_flags & MLX5_FLOW_ACTION_INDIRECT_COUNT)
# # # # #
# ]
3662 : : /*
3663 : : * When AGE uses indirect counter, no need to
3664 : : * create counter but need to update it with the
3665 : : * AGE parameter, will be done after the loop.
3666 : : */
3667 : : break;
3668 : : /* Fall-through. */
3669 : : case RTE_FLOW_ACTION_TYPE_COUNT:
3670 : : cnt_queue = mlx5_hws_cnt_get_queue(priv, &queue);
3671 : : ret = mlx5_hws_cnt_pool_get(priv->hws_cpool, cnt_queue, &cnt_id, age_idx);
3672 [ # # # # : 0 : if (ret != 0) {
# # # # #
# ]
3673 : 0 : rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_ACTION,
3674 : : action, "Failed to allocate flow counter");
3675 : 0 : goto error;
3676 : : }
3677 : 0 : ret = mlx5_hws_cnt_pool_get_action_offset
3678 : : (priv->hws_cpool,
3679 : : cnt_id,
3680 : : &rule_acts[act_data->action_dst].action,
3681 : 0 : &rule_acts[act_data->action_dst].counter.offset
3682 : : );
3683 : : if (ret != 0)
3684 : : goto error;
3685 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_CNT_ID;
3686 : 0 : flow->cnt_id = cnt_id;
3687 : 0 : break;
3688 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
3689 : 0 : ret = mlx5_hws_cnt_pool_get_action_offset
3690 : : (priv->hws_cpool,
3691 : : act_data->shared_counter.id,
3692 : : &rule_acts[act_data->action_dst].action,
3693 : 0 : &rule_acts[act_data->action_dst].counter.offset
3694 : : );
3695 : : if (ret != 0)
3696 : : goto error;
3697 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_CNT_ID;
3698 : 0 : flow->cnt_id = act_data->shared_counter.id;
3699 : 0 : break;
3700 : 0 : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
3701 : 0 : ct_idx = MLX5_INDIRECT_ACTION_IDX_GET(action->conf);
3702 : 0 : if (flow_hw_ct_compile(dev, queue, ct_idx,
3703 : 0 : &rule_acts[act_data->action_dst]))
3704 : 0 : goto error;
3705 : : break;
3706 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_METER_MARK:
3707 : 0 : mtr_id = act_data->shared_meter.id &
3708 : : ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
3709 : : /* Find ASO object. */
3710 : 0 : aso_mtr = mlx5_ipool_get(pool->idx_pool, mtr_id);
3711 [ # # # # : 0 : if (!aso_mtr)
# # # # #
# ]
3712 : 0 : goto error;
3713 : 0 : rule_acts[act_data->action_dst].action =
3714 : 0 : pool->action;
3715 : 0 : rule_acts[act_data->action_dst].aso_meter.offset =
3716 : 0 : aso_mtr->offset;
3717 : 0 : break;
3718 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
3719 : : /*
3720 : : * Allocate meter directly will slow down flow
3721 : : * insertion rate.
3722 : : */
3723 : : ret = flow_hw_meter_mark_compile(dev,
3724 : 0 : act_data->action_dst, action,
3725 : : rule_acts, &mtr_idx, MLX5_HW_INV_QUEUE, error);
3726 : : if (ret != 0)
3727 : 0 : goto error;
3728 [ # # # # : 0 : aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
# # # # #
# ]
3729 : : mlx5_flow_hw_aux_set_mtr_id(flow, aux, mtr_idx);
3730 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_MTR_ID;
3731 : 0 : break;
3732 : 0 : case RTE_FLOW_ACTION_TYPE_NAT64:
3733 : 0 : nat64_c = action->conf;
3734 : : MLX5_ASSERT(table->type < MLX5DR_TABLE_TYPE_MAX);
3735 : 0 : rule_acts[act_data->action_dst].action =
3736 : 0 : priv->action_nat64[table->type][nat64_c->type];
3737 : 0 : break;
3738 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
3739 : 0 : jump_table = ((const struct rte_flow_action_jump_to_table_index *)
3740 : 0 : action->conf)->table;
3741 [ # # # # : 0 : if (likely(!rte_flow_template_table_resizable(dev->data->port_id,
# # # # #
# ]
3742 : : &table->cfg.attr))) {
3743 : 0 : rule_acts[act_data->action_dst].action =
3744 : 0 : jump_table->matcher_info[0].jump;
3745 : : } else {
3746 : : uint32_t selector;
3747 : 0 : rte_rwlock_read_lock(&table->matcher_replace_rwlk);
3748 : 0 : selector = table->matcher_selector;
3749 : 0 : rule_acts[act_data->action_dst].action =
3750 : 0 : jump_table->matcher_info[selector].jump;
3751 : 0 : rte_rwlock_read_unlock(&table->matcher_replace_rwlk);
3752 : : }
3753 : 0 : rule_acts[act_data->action_dst].jump_to_matcher.offset =
3754 : : ((const struct rte_flow_action_jump_to_table_index *)
3755 : 0 : action->conf)->index;
3756 : 0 : break;
3757 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_MIRROR: {
3758 : 0 : const struct mlx5_mirror *mirror = action->conf;
3759 : :
3760 : 0 : rule_acts[act_data->action_dst].action = mirror->mirror_action;
3761 : 0 : break;
3762 : : }
3763 : : default:
3764 : : break;
3765 : : }
3766 : : }
3767 [ # # # # : 0 : if (at->action_flags & MLX5_FLOW_ACTION_INDIRECT_COUNT) {
# # # # #
# ]
3768 : : /* If indirect count is used, then CNT_ID flag should be set. */
3769 : : MLX5_ASSERT(flow->flags & MLX5_FLOW_HW_FLOW_FLAG_CNT_ID);
3770 [ # # # # : 0 : if (at->action_flags & MLX5_FLOW_ACTION_INDIRECT_AGE) {
# # # # #
# ]
3771 : : /* If indirect AGE is used, then AGE_IDX flag should be set. */
3772 : : MLX5_ASSERT(flow->flags & MLX5_FLOW_HW_FLOW_FLAG_AGE_IDX);
3773 [ # # # # : 0 : aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
# # # # #
# ]
3774 : 0 : age_idx = mlx5_flow_hw_aux_get_age_idx(flow, aux) &
3775 : : MLX5_HWS_AGE_IDX_MASK;
3776 [ # # # # : 0 : if (mlx5_hws_cnt_age_get(priv->hws_cpool, flow->cnt_id) != age_idx)
# # # # #
# # # # #
# # # # #
# ]
3777 : : /*
3778 : : * This is first use of this indirect counter
3779 : : * for this indirect AGE, need to increase the
3780 : : * number of counters.
3781 : : */
3782 : : mlx5_hws_age_nb_cnt_increase(priv, age_idx);
3783 : : }
3784 : : /*
3785 : : * Update this indirect counter the indirect/direct AGE in which
3786 : : * using it.
3787 : : */
3788 [ # # # # : 0 : mlx5_hws_cnt_age_set(priv->hws_cpool, flow->cnt_id, age_idx);
# # # # #
# ]
3789 : : }
3790 [ # # # # : 0 : if (hw_acts->encap_decap && !hw_acts->encap_decap->shared) {
# # # # #
# # # # #
# # # # #
# ]
3791 [ # # # # : 0 : int ix = mlx5_multi_pattern_reformat_to_index(hw_acts->encap_decap->action_type);
# # # # #
# ]
3792 : 0 : struct mlx5dr_rule_action *ra = &rule_acts[hw_acts->encap_decap_pos];
3793 : :
3794 [ # # # # : 0 : if (ix < 0)
# # # # #
# ]
3795 : 0 : goto error;
3796 [ # # # # : 0 : if (!mp_segment)
# # # # #
# ]
3797 : 0 : mp_segment = mlx5_multi_pattern_segment_find(table, flow->res_idx);
3798 [ # # # # : 0 : if (!mp_segment || !mp_segment->reformat_action[ix])
# # # # #
# # # # #
# # # # #
# ]
3799 : 0 : goto error;
3800 : 0 : ra->action = mp_segment->reformat_action[ix];
3801 : : /* reformat offset is relative to selected DR action */
3802 : 0 : ra->reformat.offset = flow->res_idx - mp_segment->head_index;
3803 : 0 : ra->reformat.data = ap->encap_data;
3804 : : }
3805 [ # # # # : 0 : if (hw_acts->push_remove && !hw_acts->push_remove->shared) {
# # # # #
# # # # #
# # # # #
# ]
3806 : 0 : rule_acts[hw_acts->push_remove_pos].ipv6_ext.offset =
3807 : 0 : flow->res_idx - 1;
3808 : 0 : rule_acts[hw_acts->push_remove_pos].ipv6_ext.header = ap->ipv6_push_data;
3809 : : }
3810 [ # # # # : 0 : if (mlx5_hws_cnt_id_valid(hw_acts->cnt_id)) {
# # # # #
# ]
3811 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_CNT_ID;
3812 : 0 : flow->cnt_id = hw_acts->cnt_id;
3813 : : }
3814 : : return 0;
3815 : :
3816 : 0 : error:
3817 : 0 : flow_hw_release_actions(dev, queue, flow);
3818 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3819 : : NULL, "Action construction failed");
3820 : : }
3821 : :
3822 : : static const struct rte_flow_item *
3823 : 0 : flow_hw_get_rule_items(struct rte_eth_dev *dev,
3824 : : const struct rte_flow_template_table *table,
3825 : : const struct rte_flow_item items[],
3826 : : uint8_t pattern_template_index,
3827 : : struct mlx5_flow_hw_pattern_params *pp)
3828 : : {
3829 : 0 : struct rte_flow_pattern_template *pt = table->its[pattern_template_index];
3830 : :
3831 : : /* Only one implicit item can be added to flow rule pattern. */
3832 : : MLX5_ASSERT(!pt->implicit_port || !pt->implicit_tag);
3833 : : /* At least one item was allocated in pattern params for items. */
3834 : : MLX5_ASSERT(MLX5_HW_MAX_ITEMS >= 1);
3835 [ # # ]: 0 : if (pt->implicit_port) {
3836 [ # # ]: 0 : if (pt->orig_item_nb + 1 > MLX5_HW_MAX_ITEMS) {
3837 : 0 : rte_errno = ENOMEM;
3838 : 0 : return NULL;
3839 : : }
3840 : : /* Set up represented port item in pattern params. */
3841 : 0 : pp->port_spec = (struct rte_flow_item_ethdev){
3842 : 0 : .port_id = dev->data->port_id,
3843 : : };
3844 : 0 : pp->items[0] = (struct rte_flow_item){
3845 : : .type = RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT,
3846 : 0 : .spec = &pp->port_spec,
3847 : : };
3848 [ # # ]: 0 : rte_memcpy(&pp->items[1], items, sizeof(*items) * pt->orig_item_nb);
3849 : 0 : return pp->items;
3850 [ # # ]: 0 : } else if (pt->implicit_tag) {
3851 [ # # ]: 0 : if (pt->orig_item_nb + 1 > MLX5_HW_MAX_ITEMS) {
3852 : 0 : rte_errno = ENOMEM;
3853 : 0 : return NULL;
3854 : : }
3855 : : /* Set up tag item in pattern params. */
3856 : 0 : pp->tag_spec = (struct rte_flow_item_tag){
3857 : : .data = flow_hw_tx_tag_regc_value(dev),
3858 : : };
3859 : 0 : pp->items[0] = (struct rte_flow_item){
3860 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_TAG,
3861 : 0 : .spec = &pp->tag_spec,
3862 : : };
3863 : 0 : rte_memcpy(&pp->items[1], items, sizeof(*items) * pt->orig_item_nb);
3864 : 0 : return pp->items;
3865 : : } else {
3866 : : return items;
3867 : : }
3868 : : }
3869 : :
3870 : : /**
3871 : : * Enqueue HW steering flow creation.
3872 : : *
3873 : : * The flow will be applied to the HW only if the postpone bit is not set or
3874 : : * the extra push function is called.
3875 : : * The flow creation status should be checked from dequeue result.
3876 : : *
3877 : : * @param[in] dev
3878 : : * Pointer to the rte_eth_dev structure.
3879 : : * @param[in] queue
3880 : : * The queue to create the flow.
3881 : : * @param[in] attr
3882 : : * Pointer to the flow operation attributes.
3883 : : * @param[in] table
3884 : : * Pointer to the template table.
3885 : : * @param[in] insertion_type
3886 : : * Insertion type for flow rules.
3887 : : * @param[in] rule_index
3888 : : * The item pattern flow follows from the table.
3889 : : * @param[in] items
3890 : : * Items with flow spec value.
3891 : : * @param[in] pattern_template_index
3892 : : * The item pattern flow follows from the table.
3893 : : * @param[in] actions
3894 : : * Action with flow spec value.
3895 : : * @param[in] action_template_index
3896 : : * The action pattern flow follows from the table.
3897 : : * @param[in] user_data
3898 : : * Pointer to the user_data.
3899 : : * @param[out] error
3900 : : * Pointer to error structure.
3901 : : *
3902 : : * @return
3903 : : * Flow pointer on success, NULL otherwise and rte_errno is set.
3904 : : */
3905 : : static __rte_always_inline struct rte_flow *
3906 : : flow_hw_async_flow_create_generic(struct rte_eth_dev *dev,
3907 : : uint32_t queue,
3908 : : const struct rte_flow_op_attr *attr,
3909 : : struct rte_flow_template_table *table,
3910 : : enum rte_flow_table_insertion_type insertion_type,
3911 : : uint32_t rule_index,
3912 : : const struct rte_flow_item items[],
3913 : : uint8_t pattern_template_index,
3914 : : const struct rte_flow_action actions[],
3915 : : uint8_t action_template_index,
3916 : : void *user_data,
3917 : : struct rte_flow_error *error)
3918 : : {
3919 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
3920 : 0 : struct mlx5dr_rule_attr rule_attr = {
3921 : : .queue_id = queue,
3922 : : .user_data = user_data,
3923 : 0 : .burst = attr->postpone,
3924 : : };
3925 : : struct mlx5dr_rule_action *rule_acts;
3926 : : struct rte_flow_hw *flow = NULL;
3927 : : const struct rte_flow_item *rule_items;
3928 : 0 : struct rte_flow_error sub_error = { 0 };
3929 : 0 : uint32_t flow_idx = 0;
3930 : 0 : uint32_t res_idx = 0;
3931 : : int ret;
3932 : :
3933 : 0 : if (mlx5_fp_debug_enabled()) {
3934 [ # # # # : 0 : if (flow_hw_async_create_validate(dev, queue, table, insertion_type, rule_index,
# # ]
3935 : : items, pattern_template_index, actions, action_template_index, error))
3936 : : return NULL;
3937 : : }
3938 : 0 : flow = mlx5_ipool_malloc(table->flow, &flow_idx);
3939 [ # # # # : 0 : if (!flow) {
# # ]
3940 : 0 : rte_errno = ENOMEM;
3941 : 0 : goto error;
3942 : : }
3943 : 0 : flow->nt_rule = false;
3944 : : rule_acts = flow_hw_get_dr_action_buffer(priv, table, action_template_index, queue);
3945 : : /*
3946 : : * Set the table here in order to know the destination table
3947 : : * when free the flow afterward.
3948 : : */
3949 : 0 : flow->table = table;
3950 : 0 : flow->mt_idx = pattern_template_index;
3951 : 0 : flow->idx = flow_idx;
3952 [ # # # # : 0 : if (table->resource) {
# # ]
3953 : 0 : mlx5_ipool_malloc(table->resource, &res_idx);
3954 [ # # # # : 0 : if (!res_idx) {
# # ]
3955 : 0 : rte_errno = ENOMEM;
3956 : 0 : goto error;
3957 : : }
3958 : 0 : flow->res_idx = res_idx;
3959 : : } else {
3960 : 0 : flow->res_idx = flow_idx;
3961 : : }
3962 : 0 : flow->flags = 0;
3963 : : /*
3964 : : * Set the flow operation type here in order to know if the flow memory
3965 : : * should be freed or not when get the result from dequeue.
3966 : : */
3967 : 0 : flow->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_CREATE;
3968 : 0 : flow->user_data = user_data;
3969 : 0 : rule_attr.user_data = flow;
3970 : : /*
3971 : : * Indexed pool returns 1-based indices, but mlx5dr expects 0-based indices
3972 : : * for rule insertion hints.
3973 : : */
3974 [ # # # # ]: 0 : flow->rule_idx = (rule_index == UINT32_MAX) ? flow->res_idx - 1 : rule_index;
3975 : 0 : rule_attr.rule_idx = flow->rule_idx;
3976 : : /*
3977 : : * Construct the flow actions based on the input actions.
3978 : : * The implicitly appended action is always fixed, like metadata
3979 : : * copy action from FDB to NIC Rx.
3980 : : * No need to copy and contrust a new "actions" list based on the
3981 : : * user's input, in order to save the cost.
3982 : : */
3983 [ # # # # : 0 : if (flow_hw_actions_construct(dev, flow, &priv->hw_q[queue].ap,
# # ]
3984 : 0 : &table->ats[action_template_index],
3985 [ # # # # : 0 : table->its[pattern_template_index]->item_flags,
# # ]
3986 : : flow->table, actions,
3987 : : rule_acts, queue, &sub_error))
3988 : 0 : goto error;
3989 : 0 : rule_items = flow_hw_get_rule_items(dev, table, items,
3990 : 0 : pattern_template_index, &priv->hw_q[queue].pp);
3991 [ # # # # : 0 : if (!rule_items)
# # ]
3992 : 0 : goto error;
3993 [ # # # # : 0 : if (likely(!rte_flow_template_table_resizable(dev->data->port_id, &table->cfg.attr))) {
# # ]
3994 : 0 : ret = mlx5dr_rule_create(table->matcher_info[0].matcher,
3995 : : pattern_template_index, rule_items,
3996 : : action_template_index, rule_acts,
3997 : : &rule_attr,
3998 : 0 : (struct mlx5dr_rule *)flow->rule);
3999 : : } else {
4000 [ # # # # : 0 : struct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
# # ]
4001 : : uint32_t selector;
4002 : :
4003 : 0 : flow->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_CREATE;
4004 : 0 : rte_rwlock_read_lock(&table->matcher_replace_rwlk);
4005 : 0 : selector = table->matcher_selector;
4006 : 0 : ret = mlx5dr_rule_create(table->matcher_info[selector].matcher,
4007 : : pattern_template_index, rule_items,
4008 : : action_template_index, rule_acts,
4009 : : &rule_attr,
4010 : 0 : (struct mlx5dr_rule *)flow->rule);
4011 : 0 : rte_rwlock_read_unlock(&table->matcher_replace_rwlk);
4012 : 0 : aux->matcher_selector = selector;
4013 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_MATCHER_SELECTOR;
4014 : : }
4015 : :
4016 [ # # # # : 0 : if (likely(!ret)) {
# # ]
4017 : 0 : flow_hw_q_inc_flow_ops(priv, queue);
4018 : 0 : return (struct rte_flow *)flow;
4019 : : }
4020 : 0 : error:
4021 [ # # # # : 0 : if (table->resource && res_idx)
# # # # #
# # # ]
4022 : 0 : mlx5_ipool_free(table->resource, res_idx);
4023 [ # # # # : 0 : if (flow_idx)
# # ]
4024 : 0 : mlx5_ipool_free(table->flow, flow_idx);
4025 [ # # # # : 0 : if (sub_error.cause != RTE_FLOW_ERROR_TYPE_NONE && error != NULL)
# # # # #
# # # ]
4026 : 0 : *error = sub_error;
4027 : : else
4028 : 0 : rte_flow_error_set(error, rte_errno,
4029 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4030 : : "fail to create rte flow");
4031 : : return NULL;
4032 : : }
4033 : :
4034 : : static struct rte_flow *
4035 : 0 : flow_hw_async_flow_create(struct rte_eth_dev *dev,
4036 : : uint32_t queue,
4037 : : const struct rte_flow_op_attr *attr,
4038 : : struct rte_flow_template_table *table,
4039 : : const struct rte_flow_item items[],
4040 : : uint8_t pattern_template_index,
4041 : : const struct rte_flow_action actions[],
4042 : : uint8_t action_template_index,
4043 : : void *user_data,
4044 : : struct rte_flow_error *error)
4045 : : {
4046 : : uint32_t rule_index = UINT32_MAX;
4047 : :
4048 [ # # ]: 0 : return flow_hw_async_flow_create_generic(dev, queue, attr, table,
4049 : : RTE_FLOW_TABLE_INSERTION_TYPE_PATTERN, rule_index,
4050 : : items, pattern_template_index, actions, action_template_index,
4051 : : user_data, error);
4052 : : }
4053 : :
4054 : : static struct rte_flow *
4055 : 0 : flow_hw_async_flow_create_by_index(struct rte_eth_dev *dev,
4056 : : uint32_t queue,
4057 : : const struct rte_flow_op_attr *attr,
4058 : : struct rte_flow_template_table *table,
4059 : : uint32_t rule_index,
4060 : : const struct rte_flow_action actions[],
4061 : : uint8_t action_template_index,
4062 : : void *user_data,
4063 : : struct rte_flow_error *error)
4064 : : {
4065 : 0 : struct rte_flow_item items[] = {{.type = RTE_FLOW_ITEM_TYPE_END,}};
4066 : : uint8_t pattern_template_index = 0;
4067 : :
4068 [ # # ]: 0 : return flow_hw_async_flow_create_generic(dev, queue, attr, table,
4069 : : RTE_FLOW_TABLE_INSERTION_TYPE_INDEX, rule_index,
4070 : : items, pattern_template_index, actions, action_template_index,
4071 : : user_data, error);
4072 : : }
4073 : :
4074 : : static struct rte_flow *
4075 : 0 : flow_hw_async_flow_create_by_index_with_pattern(struct rte_eth_dev *dev,
4076 : : uint32_t queue,
4077 : : const struct rte_flow_op_attr *attr,
4078 : : struct rte_flow_template_table *table,
4079 : : uint32_t rule_index,
4080 : : const struct rte_flow_item items[],
4081 : : uint8_t pattern_template_index,
4082 : : const struct rte_flow_action actions[],
4083 : : uint8_t action_template_index,
4084 : : void *user_data,
4085 : : struct rte_flow_error *error)
4086 : : {
4087 [ # # ]: 0 : return flow_hw_async_flow_create_generic(dev, queue, attr, table,
4088 : : RTE_FLOW_TABLE_INSERTION_TYPE_INDEX_WITH_PATTERN, rule_index,
4089 : : items, pattern_template_index, actions, action_template_index,
4090 : : user_data, error);
4091 : : }
4092 : :
4093 : : /**
4094 : : * Enqueue HW steering flow update.
4095 : : *
4096 : : * The flow will be applied to the HW only if the postpone bit is not set or
4097 : : * the extra push function is called.
4098 : : * The flow destruction status should be checked from dequeue result.
4099 : : *
4100 : : * @param[in] dev
4101 : : * Pointer to the rte_eth_dev structure.
4102 : : * @param[in] queue
4103 : : * The queue to destroy the flow.
4104 : : * @param[in] attr
4105 : : * Pointer to the flow operation attributes.
4106 : : * @param[in] flow
4107 : : * Pointer to the flow to be destroyed.
4108 : : * @param[in] actions
4109 : : * Action with flow spec value.
4110 : : * @param[in] action_template_index
4111 : : * The action pattern flow follows from the table.
4112 : : * @param[in] user_data
4113 : : * Pointer to the user_data.
4114 : : * @param[out] error
4115 : : * Pointer to error structure.
4116 : : *
4117 : : * @return
4118 : : * 0 on success, negative value otherwise and rte_errno is set.
4119 : : */
4120 : : static int
4121 : 0 : flow_hw_async_flow_update(struct rte_eth_dev *dev,
4122 : : uint32_t queue,
4123 : : const struct rte_flow_op_attr *attr,
4124 : : struct rte_flow *flow,
4125 : : const struct rte_flow_action actions[],
4126 : : uint8_t action_template_index,
4127 : : void *user_data,
4128 : : struct rte_flow_error *error)
4129 : : {
4130 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4131 : 0 : struct mlx5dr_rule_attr rule_attr = {
4132 : : .queue_id = queue,
4133 : : .user_data = user_data,
4134 : 0 : .burst = attr->postpone,
4135 : : };
4136 : : struct mlx5dr_rule_action *rule_acts;
4137 : : struct rte_flow_hw *of = (struct rte_flow_hw *)flow;
4138 : : struct rte_flow_hw *nf;
4139 : : struct rte_flow_hw_aux *aux;
4140 : 0 : struct rte_flow_template_table *table = of->table;
4141 : 0 : uint32_t res_idx = 0;
4142 : : int ret;
4143 : :
4144 [ # # ]: 0 : if (mlx5_fp_debug_enabled()) {
4145 [ # # ]: 0 : if (flow_hw_async_update_validate(dev, queue, of, actions, action_template_index,
4146 : : error))
4147 : 0 : return -rte_errno;
4148 : : }
4149 [ # # ]: 0 : aux = mlx5_flow_hw_aux(dev->data->port_id, of);
4150 : 0 : nf = &aux->upd_flow;
4151 : 0 : nf->nt_rule = false;
4152 : 0 : rule_acts = flow_hw_get_dr_action_buffer(priv, table, action_template_index, queue);
4153 : : /*
4154 : : * Set the table here in order to know the destination table
4155 : : * when free the flow afterwards.
4156 : : */
4157 : 0 : nf->table = table;
4158 : 0 : nf->mt_idx = of->mt_idx;
4159 : 0 : nf->idx = of->idx;
4160 [ # # ]: 0 : if (table->resource) {
4161 : 0 : mlx5_ipool_malloc(table->resource, &res_idx);
4162 [ # # ]: 0 : if (!res_idx) {
4163 : 0 : rte_errno = ENOMEM;
4164 : 0 : goto error;
4165 : : }
4166 : 0 : nf->res_idx = res_idx;
4167 : : } else {
4168 : 0 : nf->res_idx = of->res_idx;
4169 : : }
4170 : 0 : nf->flags = 0;
4171 : : /* Indicate the construction function to set the proper fields. */
4172 : 0 : nf->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE;
4173 : : /*
4174 : : * Indexed pool returns 1-based indices, but mlx5dr expects 0-based indices
4175 : : * for rule insertion hints.
4176 : : * If there is only one STE, the update will be atomic by nature.
4177 : : */
4178 : 0 : nf->rule_idx = nf->res_idx - 1;
4179 : 0 : rule_attr.rule_idx = nf->rule_idx;
4180 : : /*
4181 : : * Construct the flow actions based on the input actions.
4182 : : * The implicitly appended action is always fixed, like metadata
4183 : : * copy action from FDB to NIC Rx.
4184 : : * No need to copy and contrust a new "actions" list based on the
4185 : : * user's input, in order to save the cost.
4186 : : */
4187 [ # # ]: 0 : if (flow_hw_actions_construct(dev, nf, &priv->hw_q[queue].ap,
4188 : 0 : &table->ats[action_template_index],
4189 [ # # ]: 0 : table->its[nf->mt_idx]->item_flags,
4190 : : table, actions,
4191 : : rule_acts, queue, error)) {
4192 : 0 : rte_errno = EINVAL;
4193 : 0 : goto error;
4194 : : }
4195 : : /*
4196 : : * Set the flow operation type here in order to know if the flow memory
4197 : : * should be freed or not when get the result from dequeue.
4198 : : */
4199 : 0 : of->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE;
4200 : 0 : of->user_data = user_data;
4201 : 0 : of->flags |= MLX5_FLOW_HW_FLOW_FLAG_UPD_FLOW;
4202 : 0 : rule_attr.user_data = of;
4203 : 0 : ret = mlx5dr_rule_action_update((struct mlx5dr_rule *)of->rule,
4204 : : action_template_index, rule_acts, &rule_attr);
4205 [ # # ]: 0 : if (likely(!ret)) {
4206 : 0 : flow_hw_q_inc_flow_ops(priv, queue);
4207 : 0 : return 0;
4208 : : }
4209 : 0 : error:
4210 [ # # # # ]: 0 : if (table->resource && res_idx)
4211 : 0 : mlx5_ipool_free(table->resource, res_idx);
4212 : 0 : return rte_flow_error_set(error, rte_errno,
4213 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4214 : : "fail to update rte flow");
4215 : : }
4216 : :
4217 : : /**
4218 : : * Enqueue HW steering flow destruction.
4219 : : *
4220 : : * The flow will be applied to the HW only if the postpone bit is not set or
4221 : : * the extra push function is called.
4222 : : * The flow destruction status should be checked from dequeue result.
4223 : : *
4224 : : * @param[in] dev
4225 : : * Pointer to the rte_eth_dev structure.
4226 : : * @param[in] queue
4227 : : * The queue to destroy the flow.
4228 : : * @param[in] attr
4229 : : * Pointer to the flow operation attributes.
4230 : : * @param[in] flow
4231 : : * Pointer to the flow to be destroyed.
4232 : : * @param[in] user_data
4233 : : * Pointer to the user_data.
4234 : : * @param[out] error
4235 : : * Pointer to error structure.
4236 : : *
4237 : : * @return
4238 : : * 0 on success, negative value otherwise and rte_errno is set.
4239 : : */
4240 : : static int
4241 : 0 : flow_hw_async_flow_destroy(struct rte_eth_dev *dev,
4242 : : uint32_t queue,
4243 : : const struct rte_flow_op_attr *attr,
4244 : : struct rte_flow *flow,
4245 : : void *user_data,
4246 : : struct rte_flow_error *error)
4247 : : {
4248 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4249 : 0 : struct mlx5dr_rule_attr rule_attr = {
4250 : : .queue_id = queue,
4251 : : .user_data = user_data,
4252 : 0 : .burst = attr->postpone,
4253 : : };
4254 : : struct rte_flow_hw *fh = (struct rte_flow_hw *)flow;
4255 : 0 : bool resizable = rte_flow_template_table_resizable(dev->data->port_id,
4256 : 0 : &fh->table->cfg.attr);
4257 : : int ret;
4258 : :
4259 : : if (mlx5_fp_debug_enabled()) {
4260 : : if (flow_hw_async_destroy_validate(dev, queue, fh, error))
4261 : : return -rte_errno;
4262 : : }
4263 [ # # ]: 0 : fh->operation_type = !resizable ?
4264 : : MLX5_FLOW_HW_FLOW_OP_TYPE_DESTROY :
4265 : : MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_DESTROY;
4266 : 0 : fh->user_data = user_data;
4267 : 0 : rule_attr.user_data = fh;
4268 : 0 : rule_attr.rule_idx = fh->rule_idx;
4269 : 0 : ret = mlx5dr_rule_destroy((struct mlx5dr_rule *)fh->rule, &rule_attr);
4270 [ # # ]: 0 : if (ret) {
4271 : 0 : return rte_flow_error_set(error, rte_errno,
4272 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4273 : : "fail to destroy rte flow");
4274 : : }
4275 : : flow_hw_q_inc_flow_ops(priv, queue);
4276 : 0 : return 0;
4277 : : }
4278 : :
4279 : : /**
4280 : : * Release the AGE and counter for given flow.
4281 : : *
4282 : : * @param[in] priv
4283 : : * Pointer to the port private data structure.
4284 : : * @param[in] queue
4285 : : * The queue to release the counter.
4286 : : * @param[in, out] flow
4287 : : * Pointer to the flow containing the counter.
4288 : : * @param[out] error
4289 : : * Pointer to error structure.
4290 : : */
4291 : : static void
4292 : 0 : flow_hw_age_count_release(struct mlx5_priv *priv, uint32_t queue,
4293 : : struct rte_flow_hw *flow,
4294 : : struct rte_flow_error *error)
4295 : : {
4296 [ # # ]: 0 : struct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(priv->dev_data->port_id, flow);
4297 : : uint32_t *cnt_queue;
4298 : 0 : uint32_t age_idx = aux->orig.age_idx;
4299 : :
4300 : : MLX5_ASSERT(flow->flags & MLX5_FLOW_HW_FLOW_FLAG_CNT_ID);
4301 [ # # # # ]: 0 : if (mlx5_hws_cnt_is_shared(priv->hws_cpool, flow->cnt_id)) {
4302 [ # # # # ]: 0 : if ((flow->flags & MLX5_FLOW_HW_FLOW_FLAG_AGE_IDX) &&
4303 : : !mlx5_hws_age_is_indirect(age_idx)) {
4304 : : /* Remove this AGE parameter from indirect counter. */
4305 : : mlx5_hws_cnt_age_set(priv->hws_cpool, flow->cnt_id, 0);
4306 : : /* Release the AGE parameter. */
4307 : 0 : mlx5_hws_age_action_destroy(priv, age_idx, error);
4308 : : }
4309 : 0 : return;
4310 : : }
4311 : : cnt_queue = mlx5_hws_cnt_get_queue(priv, &queue);
4312 : : /* Put the counter first to reduce the race risk in BG thread. */
4313 [ # # ]: 0 : mlx5_hws_cnt_pool_put(priv->hws_cpool, cnt_queue, &flow->cnt_id);
4314 [ # # ]: 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_AGE_IDX) {
4315 [ # # ]: 0 : if (mlx5_hws_age_is_indirect(age_idx)) {
4316 : 0 : uint32_t idx = age_idx & MLX5_HWS_AGE_IDX_MASK;
4317 : :
4318 : : mlx5_hws_age_nb_cnt_decrease(priv, idx);
4319 : : } else {
4320 : : /* Release the AGE parameter. */
4321 : 0 : mlx5_hws_age_action_destroy(priv, age_idx, error);
4322 : : }
4323 : : }
4324 : : }
4325 : :
4326 : : static __rte_always_inline void
4327 : : flow_hw_pull_legacy_indirect_comp(struct rte_eth_dev *dev, struct mlx5_hw_q_job *job,
4328 : : uint32_t queue)
4329 : : {
4330 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4331 : : struct mlx5_aso_ct_action *aso_ct;
4332 : : struct mlx5_aso_mtr *aso_mtr;
4333 : : uint32_t type, idx;
4334 : :
4335 [ # # ]: 0 : if (MLX5_INDIRECT_ACTION_TYPE_GET(job->action) ==
4336 : : MLX5_INDIRECT_ACTION_TYPE_QUOTA) {
4337 : 0 : mlx5_quota_async_completion(dev, queue, job);
4338 [ # # ]: 0 : } else if (job->type == MLX5_HW_Q_JOB_TYPE_DESTROY) {
4339 : : type = MLX5_INDIRECT_ACTION_TYPE_GET(job->action);
4340 [ # # ]: 0 : if (type == MLX5_INDIRECT_ACTION_TYPE_METER_MARK) {
4341 : 0 : idx = MLX5_INDIRECT_ACTION_IDX_GET(job->action);
4342 : 0 : mlx5_ipool_free(priv->hws_mpool->idx_pool, idx);
4343 : : }
4344 [ # # ]: 0 : } else if (job->type == MLX5_HW_Q_JOB_TYPE_CREATE) {
4345 : : type = MLX5_INDIRECT_ACTION_TYPE_GET(job->action);
4346 [ # # ]: 0 : if (type == MLX5_INDIRECT_ACTION_TYPE_METER_MARK) {
4347 : 0 : idx = MLX5_INDIRECT_ACTION_IDX_GET(job->action);
4348 : 0 : aso_mtr = mlx5_ipool_get(priv->hws_mpool->idx_pool, idx);
4349 : 0 : aso_mtr->state = ASO_METER_READY;
4350 [ # # ]: 0 : } else if (type == MLX5_INDIRECT_ACTION_TYPE_CT) {
4351 : 0 : idx = MLX5_INDIRECT_ACTION_IDX_GET(job->action);
4352 : 0 : aso_ct = mlx5_ipool_get(priv->hws_ctpool->cts, idx);
4353 : 0 : aso_ct->state = ASO_CONNTRACK_READY;
4354 : : }
4355 [ # # ]: 0 : } else if (job->type == MLX5_HW_Q_JOB_TYPE_QUERY) {
4356 : : type = MLX5_INDIRECT_ACTION_TYPE_GET(job->action);
4357 [ # # ]: 0 : if (type == MLX5_INDIRECT_ACTION_TYPE_CT) {
4358 : 0 : idx = MLX5_INDIRECT_ACTION_IDX_GET(job->action);
4359 : 0 : aso_ct = mlx5_ipool_get(priv->hws_ctpool->cts, idx);
4360 : 0 : mlx5_aso_ct_obj_analyze(job->query.user,
4361 : 0 : job->query.hw);
4362 : 0 : aso_ct->state = ASO_CONNTRACK_READY;
4363 : : }
4364 : : }
4365 : : }
4366 : :
4367 : : static __rte_always_inline int
4368 : : mlx5_hw_pull_flow_transfer_comp(struct rte_eth_dev *dev,
4369 : : uint32_t queue, struct rte_flow_op_result res[],
4370 : : uint16_t n_res)
4371 : : {
4372 : : uint32_t size, i;
4373 : 0 : struct rte_flow_hw *flow = NULL;
4374 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4375 : 0 : struct rte_ring *ring = priv->hw_q[queue].flow_transfer_completed;
4376 : :
4377 : 0 : size = RTE_MIN(rte_ring_count(ring), n_res);
4378 [ # # ]: 0 : for (i = 0; i < size; i++) {
4379 [ # # # # : 0 : res[i].status = RTE_FLOW_OP_SUCCESS;
# ]
4380 : : rte_ring_dequeue(ring, (void **)&flow);
4381 : 0 : res[i].user_data = flow->user_data;
4382 : : flow_hw_q_dec_flow_ops(priv, queue);
4383 : : }
4384 : 0 : return (int)size;
4385 : : }
4386 : :
4387 : : static inline int
4388 : 0 : __flow_hw_pull_indir_action_comp(struct rte_eth_dev *dev,
4389 : : uint32_t queue,
4390 : : struct rte_flow_op_result res[],
4391 : : uint16_t n_res)
4392 : :
4393 : : {
4394 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4395 : 0 : struct rte_ring *r = priv->hw_q[queue].indir_cq;
4396 : 0 : void *user_data = NULL;
4397 : : int ret_comp, i;
4398 : :
4399 : 0 : ret_comp = (int)rte_ring_count(r);
4400 : 0 : if (ret_comp > n_res)
4401 : : ret_comp = n_res;
4402 [ # # ]: 0 : for (i = 0; i < ret_comp; i++) {
4403 : : rte_ring_dequeue(r, &user_data);
4404 : 0 : res[i].user_data = user_data;
4405 : 0 : res[i].status = RTE_FLOW_OP_SUCCESS;
4406 : : }
4407 [ # # ]: 0 : if (!priv->shared_host) {
4408 [ # # # # ]: 0 : if (ret_comp < n_res && priv->hws_mpool)
4409 : 0 : ret_comp += mlx5_aso_pull_completion(&priv->hws_mpool->sq[queue],
4410 : 0 : &res[ret_comp], n_res - ret_comp);
4411 [ # # # # ]: 0 : if (ret_comp < n_res && priv->hws_ctpool)
4412 : 0 : ret_comp += mlx5_aso_pull_completion(&priv->ct_mng->aso_sqs[queue],
4413 : 0 : &res[ret_comp], n_res - ret_comp);
4414 : : }
4415 [ # # # # ]: 0 : if (ret_comp < n_res && priv->quota_ctx.sq)
4416 : 0 : ret_comp += mlx5_aso_pull_completion(&priv->quota_ctx.sq[queue],
4417 : 0 : &res[ret_comp],
4418 : 0 : n_res - ret_comp);
4419 [ # # ]: 0 : for (i = 0; i < ret_comp; i++) {
4420 : 0 : struct mlx5_hw_q_job *job = (struct mlx5_hw_q_job *)res[i].user_data;
4421 : :
4422 : : /* Restore user data. */
4423 : 0 : res[i].user_data = job->user_data;
4424 [ # # ]: 0 : if (job->indirect_type == MLX5_HW_INDIRECT_TYPE_LEGACY)
4425 : : flow_hw_pull_legacy_indirect_comp(dev, job, queue);
4426 : : /*
4427 : : * Current PMD supports 2 indirect action list types - MIRROR and REFORMAT.
4428 : : * These indirect list types do not post WQE to create action.
4429 : : * Future indirect list types that do post WQE will add
4430 : : * completion handlers here.
4431 : : */
4432 : : flow_hw_job_put(priv, job, queue);
4433 : : }
4434 : 0 : return ret_comp;
4435 : : }
4436 : :
4437 : : static __rte_always_inline void
4438 : : hw_cmpl_flow_update_or_destroy(struct rte_eth_dev *dev,
4439 : : struct rte_flow_hw *flow,
4440 : : uint32_t queue, struct rte_flow_error *error)
4441 : : {
4442 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4443 : 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
4444 : 0 : struct rte_flow_template_table *table = flow->table;
4445 : : /* Release the original resource index in case of update. */
4446 : 0 : uint32_t res_idx = flow->res_idx;
4447 : :
4448 [ # # ]: 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAGS_ALL) {
4449 [ # # # # : 0 : struct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
# # ]
4450 : :
4451 [ # # # # : 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_FATE_JUMP)
# # ]
4452 : 0 : flow_hw_jump_release(dev, flow->jump);
4453 [ # # # # : 0 : else if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_FATE_HRXQ)
# # ]
4454 : 0 : mlx5_hrxq_obj_release(dev, flow->hrxq);
4455 [ # # # # : 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_CNT_ID)
# # ]
4456 : 0 : flow_hw_age_count_release(priv, queue, flow, error);
4457 [ # # # # : 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_MTR_ID)
# # ]
4458 : 0 : mlx5_ipool_free(pool->idx_pool, aux->orig.mtr_id);
4459 [ # # # # : 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_UPD_FLOW) {
# # ]
4460 [ # # # # : 0 : struct rte_flow_hw *upd_flow = &aux->upd_flow;
# # ]
4461 : :
4462 : : rte_memcpy(flow, upd_flow, offsetof(struct rte_flow_hw, rule));
4463 : 0 : aux->orig = aux->upd;
4464 : 0 : flow->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_CREATE;
4465 [ # # # # : 0 : if (!flow->nt_rule && table->resource)
# # # # #
# # # ]
4466 : 0 : mlx5_ipool_free(table->resource, res_idx);
4467 : : }
4468 : : }
4469 [ # # # # : 0 : if (flow->operation_type == MLX5_FLOW_HW_FLOW_OP_TYPE_DESTROY ||
# # ]
4470 : : flow->operation_type == MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_DESTROY) {
4471 [ # # # # : 0 : if (!flow->nt_rule) {
# # ]
4472 [ # # # # : 0 : if (table->resource)
# # ]
4473 : 0 : mlx5_ipool_free(table->resource, res_idx);
4474 : 0 : mlx5_ipool_free(table->flow, flow->idx);
4475 : : }
4476 : : }
4477 : : }
4478 : :
4479 : : static __rte_always_inline void
4480 : : hw_cmpl_resizable_tbl(struct rte_eth_dev *dev,
4481 : : struct rte_flow_hw *flow,
4482 : : uint32_t queue, enum rte_flow_op_status status,
4483 : : struct rte_flow_error *error)
4484 : : {
4485 : 0 : struct rte_flow_template_table *table = flow->table;
4486 : 0 : struct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
4487 : 0 : uint32_t selector = aux->matcher_selector;
4488 : 0 : uint32_t other_selector = (selector + 1) & 1;
4489 : :
4490 : : MLX5_ASSERT(flow->flags & MLX5_FLOW_HW_FLOW_FLAG_MATCHER_SELECTOR);
4491 [ # # # # ]: 0 : switch (flow->operation_type) {
4492 : 0 : case MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_CREATE:
4493 : 0 : rte_atomic_fetch_add_explicit
4494 : : (&table->matcher_info[selector].refcnt, 1,
4495 : : rte_memory_order_relaxed);
4496 : 0 : break;
4497 : 0 : case MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_DESTROY:
4498 [ # # ]: 0 : rte_atomic_fetch_sub_explicit
4499 : : (&table->matcher_info[selector].refcnt, 1,
4500 : : rte_memory_order_relaxed);
4501 : : hw_cmpl_flow_update_or_destroy(dev, flow, queue, error);
4502 : : break;
4503 : 0 : case MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_MOVE:
4504 [ # # ]: 0 : if (status == RTE_FLOW_OP_SUCCESS) {
4505 : 0 : rte_atomic_fetch_sub_explicit
4506 : : (&table->matcher_info[selector].refcnt, 1,
4507 : : rte_memory_order_relaxed);
4508 : 0 : rte_atomic_fetch_add_explicit
4509 : : (&table->matcher_info[other_selector].refcnt, 1,
4510 : : rte_memory_order_relaxed);
4511 : 0 : aux->matcher_selector = other_selector;
4512 : : }
4513 : : break;
4514 : : default:
4515 : : break;
4516 : : }
4517 : : }
4518 : :
4519 : : /**
4520 : : * Pull the enqueued flows.
4521 : : *
4522 : : * For flows enqueued from creation/destruction, the status should be
4523 : : * checked from the dequeue result.
4524 : : *
4525 : : * @param[in] dev
4526 : : * Pointer to the rte_eth_dev structure.
4527 : : * @param[in] queue
4528 : : * The queue to pull the result.
4529 : : * @param[in/out] res
4530 : : * Array to save the results.
4531 : : * @param[in] n_res
4532 : : * Available result with the array.
4533 : : * @param[out] error
4534 : : * Pointer to error structure.
4535 : : *
4536 : : * @return
4537 : : * Result number on success, negative value otherwise and rte_errno is set.
4538 : : */
4539 : : static int
4540 : 0 : flow_hw_pull(struct rte_eth_dev *dev,
4541 : : uint32_t queue,
4542 : : struct rte_flow_op_result res[],
4543 : : uint16_t n_res,
4544 : : struct rte_flow_error *error)
4545 : : {
4546 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4547 : : int ret, i;
4548 : :
4549 : : /* 1. Pull the flow completion. */
4550 : 0 : ret = mlx5dr_send_queue_poll(priv->dr_ctx, queue, res, n_res);
4551 [ # # ]: 0 : if (ret < 0)
4552 : 0 : return rte_flow_error_set(error, rte_errno,
4553 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4554 : : "fail to query flow queue");
4555 [ # # ]: 0 : for (i = 0; i < ret; i++) {
4556 : 0 : struct rte_flow_hw *flow = res[i].user_data;
4557 : :
4558 : : /* Restore user data. */
4559 : 0 : res[i].user_data = flow->user_data;
4560 [ # # # ]: 0 : switch (flow->operation_type) {
4561 : : case MLX5_FLOW_HW_FLOW_OP_TYPE_DESTROY:
4562 : : case MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE:
4563 : : hw_cmpl_flow_update_or_destroy(dev, flow, queue, error);
4564 : : break;
4565 : 0 : case MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_CREATE:
4566 : : case MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_DESTROY:
4567 : : case MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_MOVE:
4568 [ # # ]: 0 : hw_cmpl_resizable_tbl(dev, flow, queue, res[i].status, error);
4569 : : break;
4570 : : default:
4571 : : break;
4572 : : }
4573 : : flow_hw_q_dec_flow_ops(priv, queue);
4574 : : }
4575 : : /* 2. Pull indirect action comp. */
4576 [ # # ]: 0 : if (ret < n_res)
4577 : 0 : ret += __flow_hw_pull_indir_action_comp(dev, queue, &res[ret],
4578 : 0 : n_res - ret);
4579 [ # # ]: 0 : if (ret < n_res)
4580 : 0 : ret += mlx5_hw_pull_flow_transfer_comp(dev, queue, &res[ret],
4581 : 0 : n_res - ret);
4582 : :
4583 : : return ret;
4584 : : }
4585 : :
4586 : : static uint32_t
4587 : 0 : mlx5_hw_push_queue(struct rte_ring *pending_q, struct rte_ring *cmpl_q)
4588 : : {
4589 : 0 : void *job = NULL;
4590 : : uint32_t i, size = rte_ring_count(pending_q);
4591 : :
4592 [ # # ]: 0 : for (i = 0; i < size; i++) {
4593 : : rte_ring_dequeue(pending_q, &job);
4594 [ # # # # : 0 : rte_ring_enqueue(cmpl_q, job);
# ]
4595 : : }
4596 : 0 : return size;
4597 : : }
4598 : :
4599 : : static inline uint32_t
4600 : 0 : __flow_hw_push_action(struct rte_eth_dev *dev,
4601 : : uint32_t queue)
4602 : : {
4603 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4604 : 0 : struct mlx5_hw_q *hw_q = &priv->hw_q[queue];
4605 : :
4606 : 0 : mlx5_hw_push_queue(hw_q->indir_iq, hw_q->indir_cq);
4607 : 0 : mlx5_hw_push_queue(hw_q->flow_transfer_pending,
4608 : : hw_q->flow_transfer_completed);
4609 [ # # ]: 0 : if (!priv->shared_host) {
4610 [ # # ]: 0 : if (priv->hws_ctpool)
4611 : 0 : mlx5_aso_push_wqe(priv->sh,
4612 : 0 : &priv->ct_mng->aso_sqs[queue]);
4613 [ # # ]: 0 : if (priv->hws_mpool)
4614 : 0 : mlx5_aso_push_wqe(priv->sh,
4615 : 0 : &priv->hws_mpool->sq[queue]);
4616 : : }
4617 : 0 : return flow_hw_q_pending(priv, queue);
4618 : : }
4619 : :
4620 : : static int
4621 : 0 : __flow_hw_push(struct rte_eth_dev *dev,
4622 : : uint32_t queue,
4623 : : struct rte_flow_error *error)
4624 : : {
4625 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4626 : : int ret, num;
4627 : :
4628 : 0 : num = __flow_hw_push_action(dev, queue);
4629 : 0 : ret = mlx5dr_send_queue_action(priv->dr_ctx, queue,
4630 : : MLX5DR_SEND_QUEUE_ACTION_DRAIN_ASYNC);
4631 [ # # ]: 0 : if (ret) {
4632 : 0 : rte_flow_error_set(error, rte_errno,
4633 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4634 : : "fail to push flows");
4635 : 0 : return ret;
4636 : : }
4637 : : return num;
4638 : : }
4639 : :
4640 : : /**
4641 : : * Push the enqueued flows to HW.
4642 : : *
4643 : : * Force apply all the enqueued flows to the HW.
4644 : : *
4645 : : * @param[in] dev
4646 : : * Pointer to the rte_eth_dev structure.
4647 : : * @param[in] queue
4648 : : * The queue to push the flow.
4649 : : * @param[out] error
4650 : : * Pointer to error structure.
4651 : : *
4652 : : * @return
4653 : : * 0 on success, negative value otherwise and rte_errno is set.
4654 : : */
4655 : : static int
4656 : 0 : flow_hw_push(struct rte_eth_dev *dev,
4657 : : uint32_t queue, struct rte_flow_error *error)
4658 : : {
4659 : 0 : int ret = __flow_hw_push(dev, queue, error);
4660 : :
4661 : 0 : return ret >= 0 ? 0 : ret;
4662 : : }
4663 : :
4664 : : /**
4665 : : * Drain the enqueued flows' completion.
4666 : : *
4667 : : * @param[in] dev
4668 : : * Pointer to the rte_eth_dev structure.
4669 : : * @param[in] queue
4670 : : * The queue to pull the flow.
4671 : : * @param[out] error
4672 : : * Pointer to error structure.
4673 : : *
4674 : : * @return
4675 : : * 0 on success, negative value otherwise and rte_errno is set.
4676 : : */
4677 : : static int
4678 : 0 : __flow_hw_pull_comp(struct rte_eth_dev *dev,
4679 : : uint32_t queue, struct rte_flow_error *error)
4680 : : {
4681 : : struct rte_flow_op_result comp[BURST_THR];
4682 : : int ret, i, empty_loop = 0;
4683 : : uint32_t pending_rules;
4684 : :
4685 : 0 : ret = __flow_hw_push(dev, queue, error);
4686 [ # # ]: 0 : if (ret < 0)
4687 : : return ret;
4688 : 0 : pending_rules = ret;
4689 [ # # ]: 0 : while (pending_rules) {
4690 : 0 : ret = flow_hw_pull(dev, queue, comp, BURST_THR, error);
4691 [ # # ]: 0 : if (ret < 0)
4692 : : return -1;
4693 [ # # ]: 0 : if (!ret) {
4694 : 0 : rte_delay_us_sleep(MLX5_ASO_WQE_CQE_RESPONSE_DELAY);
4695 [ # # ]: 0 : if (++empty_loop > 5) {
4696 : 0 : DRV_LOG(WARNING, "No available dequeue %u, quit.", pending_rules);
4697 : 0 : break;
4698 : : }
4699 : 0 : continue;
4700 : : }
4701 [ # # ]: 0 : for (i = 0; i < ret; i++) {
4702 [ # # ]: 0 : if (comp[i].status == RTE_FLOW_OP_ERROR)
4703 : 0 : DRV_LOG(WARNING, "Flow flush get error CQE.");
4704 : : }
4705 : : /*
4706 : : * Indirect **SYNC** METER_MARK and CT actions do not
4707 : : * remove completion after WQE post.
4708 : : * That implementation avoids HW timeout.
4709 : : * The completion is removed before the following WQE post.
4710 : : * However, HWS queue updates do not reflect that behaviour.
4711 : : * Therefore, during port destruction sync queue may have
4712 : : * pending completions.
4713 : : */
4714 : 0 : pending_rules -= RTE_MIN(pending_rules, (uint32_t)ret);
4715 : : empty_loop = 0;
4716 : : }
4717 : : return 0;
4718 : : }
4719 : :
4720 : : /**
4721 : : * Flush created flows.
4722 : : *
4723 : : * @param[in] dev
4724 : : * Pointer to the rte_eth_dev structure.
4725 : : * @param[out] error
4726 : : * Pointer to error structure.
4727 : : *
4728 : : * @return
4729 : : * 0 on success, negative value otherwise and rte_errno is set.
4730 : : */
4731 : : int
4732 : 0 : flow_hw_q_flow_flush(struct rte_eth_dev *dev,
4733 : : struct rte_flow_error *error)
4734 : : {
4735 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4736 : 0 : struct mlx5_hw_q *hw_q = &priv->hw_q[MLX5_DEFAULT_FLUSH_QUEUE];
4737 : : struct rte_flow_template_table *tbl;
4738 : : struct rte_flow_hw *flow;
4739 : 0 : struct rte_flow_op_attr attr = {
4740 : : .postpone = 0,
4741 : : };
4742 : : uint32_t pending_rules = 0;
4743 : : uint32_t queue;
4744 : : uint32_t fidx;
4745 : :
4746 : : /*
4747 : : * Ensure to push and dequeue all the enqueued flow
4748 : : * creation/destruction jobs in case user forgot to
4749 : : * dequeue. Or the enqueued created flows will be
4750 : : * leaked. The forgotten dequeues would also cause
4751 : : * flow flush get extra CQEs as expected and pending_rules
4752 : : * be minus value.
4753 : : */
4754 [ # # ]: 0 : for (queue = 0; queue < priv->nb_queue; queue++) {
4755 [ # # ]: 0 : if (__flow_hw_pull_comp(dev, queue, error))
4756 : : return -1;
4757 : : }
4758 : : /* Flush flow per-table from MLX5_DEFAULT_FLUSH_QUEUE. */
4759 [ # # ]: 0 : LIST_FOREACH(tbl, &priv->flow_hw_tbl, next) {
4760 [ # # ]: 0 : if (!tbl->cfg.external)
4761 : 0 : continue;
4762 [ # # ]: 0 : MLX5_IPOOL_FOREACH(tbl->flow, fidx, flow) {
4763 [ # # ]: 0 : if (flow_hw_async_flow_destroy(dev,
4764 : : MLX5_DEFAULT_FLUSH_QUEUE,
4765 : : &attr,
4766 : : (struct rte_flow *)flow,
4767 : : NULL,
4768 : : error))
4769 : : return -1;
4770 : 0 : pending_rules++;
4771 : : /* Drain completion with queue size. */
4772 [ # # ]: 0 : if (pending_rules >= hw_q->size) {
4773 [ # # ]: 0 : if (__flow_hw_pull_comp(dev,
4774 : : MLX5_DEFAULT_FLUSH_QUEUE,
4775 : : error))
4776 : : return -1;
4777 : : pending_rules = 0;
4778 : : }
4779 : : }
4780 : : }
4781 : : /* Drain left completion. */
4782 [ # # # # ]: 0 : if (pending_rules &&
4783 : 0 : __flow_hw_pull_comp(dev, MLX5_DEFAULT_FLUSH_QUEUE, error))
4784 : 0 : return -1;
4785 : : return 0;
4786 : : }
4787 : :
4788 : : static int
4789 : 0 : mlx5_tbl_multi_pattern_process(struct rte_eth_dev *dev,
4790 : : struct rte_flow_template_table *tbl,
4791 : : struct mlx5_multi_pattern_segment *segment,
4792 : : uint32_t bulk_size,
4793 : : struct rte_flow_error *error)
4794 : : {
4795 : : int ret = 0;
4796 : : uint32_t i;
4797 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4798 : : bool unified_fdb = is_unified_fdb(priv);
4799 : : struct mlx5_tbl_multi_pattern_ctx *mpctx = &tbl->mpctx;
4800 : : const struct rte_flow_template_table_attr *table_attr = &tbl->cfg.attr;
4801 : 0 : const struct rte_flow_attr *attr = &table_attr->flow_attr;
4802 : : enum mlx5dr_table_type type =
4803 : 0 : get_mlx5dr_table_type(attr, table_attr->specialize, unified_fdb);
4804 : 0 : uint32_t flags = mlx5_hw_act_flag[!!attr->group][type];
4805 : : struct mlx5dr_action *dr_action = NULL;
4806 : :
4807 [ # # ]: 0 : for (i = 0; i < MLX5_MULTIPATTERN_ENCAP_NUM; i++) {
4808 [ # # ]: 0 : typeof(mpctx->reformat[0]) *reformat = mpctx->reformat + i;
4809 : : enum mlx5dr_action_type reformat_type =
4810 : : mlx5_multi_pattern_reformat_index_to_type(i);
4811 : :
4812 [ # # ]: 0 : if (!reformat->elements_num)
4813 : 0 : continue;
4814 : : dr_action = reformat_type == MLX5DR_ACTION_TYP_INSERT_HEADER ?
4815 : : mlx5dr_action_create_insert_header
4816 : : (priv->dr_ctx, reformat->elements_num,
4817 : : reformat->insert_hdr, bulk_size, flags) :
4818 : 0 : mlx5dr_action_create_reformat
4819 : : (priv->dr_ctx, reformat_type, reformat->elements_num,
4820 : 0 : reformat->reformat_hdr, bulk_size, flags);
4821 [ # # ]: 0 : if (!dr_action) {
4822 : 0 : ret = rte_flow_error_set(error, rte_errno,
4823 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4824 : : NULL,
4825 : : "failed to create multi-pattern encap action");
4826 : 0 : goto error;
4827 : : }
4828 : 0 : segment->reformat_action[i] = dr_action;
4829 : : }
4830 [ # # ]: 0 : if (mpctx->mh.elements_num) {
4831 : : typeof(mpctx->mh) *mh = &mpctx->mh;
4832 : 0 : dr_action = mlx5dr_action_create_modify_header
4833 : 0 : (priv->dr_ctx, mpctx->mh.elements_num, mh->pattern,
4834 : : bulk_size, flags);
4835 [ # # ]: 0 : if (!dr_action) {
4836 : 0 : ret = rte_flow_error_set(error, rte_errno,
4837 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4838 : : NULL, "failed to create multi-pattern header modify action");
4839 : 0 : goto error;
4840 : : }
4841 : 0 : segment->mhdr_action = dr_action;
4842 : : }
4843 [ # # ]: 0 : if (dr_action) {
4844 : 0 : segment->capacity = RTE_BIT32(bulk_size);
4845 [ # # ]: 0 : if (segment != &mpctx->segments[MLX5_MAX_TABLE_RESIZE_NUM - 1])
4846 : 0 : segment[1].head_index = segment->head_index + segment->capacity;
4847 : : }
4848 : : return 0;
4849 : 0 : error:
4850 : 0 : mlx5_destroy_multi_pattern_segment(segment);
4851 : 0 : return ret;
4852 : : }
4853 : :
4854 : : static int
4855 : 0 : mlx5_hw_build_template_table(struct rte_eth_dev *dev,
4856 : : uint8_t nb_action_templates,
4857 : : struct rte_flow_actions_template *action_templates[],
4858 : : struct mlx5dr_action_template *at[],
4859 : : struct rte_flow_template_table *tbl,
4860 : : struct rte_flow_error *error)
4861 : : {
4862 : : int ret;
4863 : : uint8_t i;
4864 : :
4865 [ # # ]: 0 : for (i = 0; i < nb_action_templates; i++) {
4866 : 0 : uint32_t refcnt = rte_atomic_fetch_add_explicit(&action_templates[i]->refcnt, 1,
4867 : : rte_memory_order_relaxed) + 1;
4868 : :
4869 [ # # ]: 0 : if (refcnt <= 1) {
4870 : 0 : rte_flow_error_set(error, EINVAL,
4871 : : RTE_FLOW_ERROR_TYPE_ACTION,
4872 : : &action_templates[i], "invalid AT refcount");
4873 : 0 : goto at_error;
4874 : : }
4875 : 0 : at[i] = action_templates[i]->tmpl;
4876 : 0 : tbl->ats[i].action_template = action_templates[i];
4877 : 0 : LIST_INIT(&tbl->ats[i].acts.act_list);
4878 : : /* do NOT translate table action if `dev` was not started */
4879 [ # # ]: 0 : if (!dev->data->dev_started)
4880 : 0 : continue;
4881 : 0 : ret = flow_hw_translate_actions_template(dev, &tbl->cfg,
4882 : : &tbl->ats[i].acts,
4883 : : action_templates[i],
4884 : : &tbl->mpctx, error);
4885 [ # # ]: 0 : if (ret) {
4886 : 0 : i++;
4887 : 0 : goto at_error;
4888 : : }
4889 : 0 : flow_hw_populate_rule_acts_caches(dev, tbl, i);
4890 : : }
4891 [ # # ]: 0 : tbl->nb_action_templates = nb_action_templates;
4892 [ # # ]: 0 : if (mlx5_is_multi_pattern_active(&tbl->mpctx)) {
4893 [ # # ]: 0 : ret = mlx5_tbl_multi_pattern_process(dev, tbl,
4894 : : &tbl->mpctx.segments[0],
4895 : : rte_log2_u32(tbl->cfg.attr.nb_flows),
4896 : : error);
4897 [ # # ]: 0 : if (ret)
4898 : 0 : goto at_error;
4899 : : }
4900 : : return 0;
4901 : :
4902 : : at_error:
4903 [ # # ]: 0 : while (i--) {
4904 : 0 : __flow_hw_action_template_destroy(dev, &tbl->ats[i].acts);
4905 : 0 : rte_atomic_fetch_sub_explicit(&action_templates[i]->refcnt,
4906 : : 1, rte_memory_order_relaxed);
4907 : : }
4908 : 0 : return rte_errno;
4909 : : }
4910 : :
4911 : : static bool
4912 : : flow_hw_validate_template_domain(const struct rte_flow_attr *table_attr,
4913 : : uint32_t ingress, uint32_t egress, uint32_t transfer)
4914 : : {
4915 : 0 : if (table_attr->ingress)
4916 : : return ingress != 0;
4917 [ # # # # ]: 0 : else if (table_attr->egress)
4918 : : return egress != 0;
4919 : : else
4920 : 0 : return transfer;
4921 : : }
4922 : :
4923 : : static bool
4924 : : flow_hw_validate_table_domain(const struct rte_flow_attr *table_attr)
4925 : : {
4926 : 0 : return table_attr->ingress + table_attr->egress + table_attr->transfer
4927 : : == 1;
4928 : : }
4929 : :
4930 : : /**
4931 : : * Create flow table.
4932 : : *
4933 : : * The input item and action templates will be binded to the table.
4934 : : * Flow memory will also be allocated. Matcher will be created based
4935 : : * on the item template. Action will be translated to the dedicated
4936 : : * DR action if possible.
4937 : : *
4938 : : * @param[in] dev
4939 : : * Pointer to the rte_eth_dev structure.
4940 : : * @param[in] table_cfg
4941 : : * Pointer to the table configuration.
4942 : : * @param[in] item_templates
4943 : : * Item template array to be binded to the table.
4944 : : * @param[in] nb_item_templates
4945 : : * Number of item template.
4946 : : * @param[in] action_templates
4947 : : * Action template array to be binded to the table.
4948 : : * @param[in] nb_action_templates
4949 : : * Number of action template.
4950 : : * @param[out] error
4951 : : * Pointer to error structure.
4952 : : *
4953 : : * @return
4954 : : * Table on success, NULL otherwise and rte_errno is set.
4955 : : */
4956 : : static struct rte_flow_template_table *
4957 : 0 : flow_hw_table_create(struct rte_eth_dev *dev,
4958 : : const struct mlx5_flow_template_table_cfg *table_cfg,
4959 : : struct rte_flow_pattern_template *item_templates[],
4960 : : uint8_t nb_item_templates,
4961 : : struct rte_flow_actions_template *action_templates[],
4962 : : uint8_t nb_action_templates,
4963 : : struct rte_flow_error *error)
4964 : : {
4965 : 0 : struct rte_flow_error sub_error = {
4966 : : .type = RTE_FLOW_ERROR_TYPE_NONE,
4967 : : .cause = NULL,
4968 : : .message = NULL,
4969 : : };
4970 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
4971 : : bool unified_fdb = is_unified_fdb(priv);
4972 : 0 : struct mlx5dr_matcher_attr matcher_attr = {0};
4973 : 0 : struct mlx5dr_action_jump_to_matcher_attr jump_attr = {
4974 : : .type = MLX5DR_ACTION_JUMP_TO_MATCHER_BY_INDEX,
4975 : : .matcher = NULL,
4976 : : };
4977 : : struct rte_flow_template_table *tbl = NULL;
4978 : : struct mlx5_flow_group *grp;
4979 : : struct mlx5dr_match_template *mt[MLX5_HW_TBL_MAX_ITEM_TEMPLATE];
4980 : : struct mlx5dr_action_template *at[MLX5_HW_TBL_MAX_ACTION_TEMPLATE];
4981 : 0 : const struct rte_flow_template_table_attr *attr = &table_cfg->attr;
4982 : 0 : struct rte_flow_attr flow_attr = attr->flow_attr;
4983 : 0 : uint32_t specialize = table_cfg->attr.specialize;
4984 : 0 : struct mlx5_flow_cb_ctx ctx = {
4985 : : .dev = dev,
4986 : : .error = &sub_error,
4987 : : .data = &flow_attr,
4988 : : .data2 = &specialize,
4989 : : };
4990 : 0 : struct mlx5_indexed_pool_config cfg = {
4991 : : .trunk_size = 1 << 12,
4992 : : .per_core_cache = 1 << 13,
4993 : : .need_lock = 1,
4994 : 0 : .release_mem_en = !!priv->sh->config.reclaim_mode,
4995 : : .malloc = mlx5_malloc,
4996 : : .free = mlx5_free,
4997 : : .type = "mlx5_hw_table_flow",
4998 : : };
4999 : : struct mlx5_list_entry *ge;
5000 : : uint32_t i = 0, max_tpl = MLX5_HW_TBL_MAX_ITEM_TEMPLATE;
5001 [ # # ]: 0 : uint32_t nb_flows = rte_align32pow2(attr->nb_flows);
5002 : 0 : bool port_started = !!dev->data->dev_started;
5003 : : bool rpool_needed;
5004 : : size_t tbl_mem_size;
5005 : : enum mlx5dr_table_type table_type;
5006 : : int err;
5007 : :
5008 [ # # ]: 0 : if (!flow_hw_validate_table_domain(&attr->flow_attr)) {
5009 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ATTR,
5010 : : NULL, "invalid table domain attributes");
5011 : 0 : return NULL;
5012 : : }
5013 [ # # ]: 0 : for (i = 0; i < nb_item_templates; i++) {
5014 : : const struct rte_flow_pattern_template_attr *pt_attr =
5015 : 0 : &item_templates[i]->attr;
5016 : : bool match = flow_hw_validate_template_domain(&attr->flow_attr,
5017 : 0 : pt_attr->ingress,
5018 : 0 : pt_attr->egress,
5019 [ # # ]: 0 : pt_attr->transfer);
5020 [ # # ]: 0 : if (!match) {
5021 : 0 : rte_flow_error_set(error, EINVAL,
5022 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5023 : : NULL, "pattern template domain does not match table");
5024 : 0 : return NULL;
5025 : : }
5026 [ # # # # ]: 0 : if (item_templates[i]->item_flags & MLX5_FLOW_LAYER_ECPRI &&
5027 : 0 : !mlx5_flex_parser_ecpri_exist(dev))
5028 [ # # ]: 0 : if (mlx5_flex_parser_ecpri_alloc(dev)) {
5029 : 0 : rte_flow_error_set(error, EIO,
5030 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5031 : : NULL,
5032 : : "failed to create Flex parser "
5033 : : "profile for ECPRI");
5034 : 0 : goto error;
5035 : : }
5036 : : }
5037 [ # # ]: 0 : for (i = 0; i < nb_action_templates; i++) {
5038 : 0 : const struct rte_flow_actions_template *at = action_templates[i];
5039 : : bool match = flow_hw_validate_template_domain(&attr->flow_attr,
5040 : 0 : at->attr.ingress,
5041 : 0 : at->attr.egress,
5042 [ # # ]: 0 : at->attr.transfer);
5043 [ # # ]: 0 : if (!match) {
5044 : 0 : rte_flow_error_set(error, EINVAL,
5045 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5046 : : NULL, "action template domain does not match table");
5047 : 0 : return NULL;
5048 : : }
5049 : : }
5050 : : /* HWS layer accepts only 1 item template with root table. */
5051 [ # # ]: 0 : if (!attr->flow_attr.group)
5052 : : max_tpl = 1;
5053 : 0 : cfg.max_idx = nb_flows;
5054 [ # # ]: 0 : cfg.size = !rte_flow_template_table_resizable(dev->data->port_id, attr) ?
5055 : : mlx5_flow_hw_entry_size() :
5056 : : mlx5_flow_hw_auxed_entry_size();
5057 : : /* For table has very limited flows, disable cache. */
5058 [ # # ]: 0 : if (nb_flows < cfg.trunk_size) {
5059 : 0 : cfg.per_core_cache = 0;
5060 : 0 : cfg.trunk_size = nb_flows;
5061 [ # # ]: 0 : } else if (nb_flows <= MLX5_HW_IPOOL_SIZE_THRESHOLD) {
5062 : 0 : cfg.per_core_cache = MLX5_HW_IPOOL_CACHE_MIN;
5063 : : }
5064 : : /* Check if we requires too many templates. */
5065 [ # # # # ]: 0 : if (nb_item_templates > max_tpl ||
5066 : : nb_action_templates > MLX5_HW_TBL_MAX_ACTION_TEMPLATE) {
5067 : 0 : rte_errno = EINVAL;
5068 : 0 : goto error;
5069 : : }
5070 : : /*
5071 : : * Amount of memory required for rte_flow_template_table struct:
5072 : : * - Size of the struct itself.
5073 : : * - VLA of DR rule action containers at the end =
5074 : : * number of actions templates * number of queues * size of DR rule actions container.
5075 : : */
5076 : : tbl_mem_size = sizeof(*tbl);
5077 : 0 : tbl_mem_size += nb_action_templates * priv->nb_queue * sizeof(tbl->rule_acts[0]);
5078 : : /* Allocate the table memory. */
5079 : 0 : tbl = mlx5_malloc(MLX5_MEM_ZERO, tbl_mem_size, RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
5080 [ # # ]: 0 : if (!tbl)
5081 : 0 : goto error;
5082 : 0 : tbl->cfg = *table_cfg;
5083 : : /* Allocate flow indexed pool. */
5084 : 0 : tbl->flow = mlx5_ipool_create(&cfg);
5085 [ # # ]: 0 : if (!tbl->flow)
5086 : 0 : goto error;
5087 : : /* Allocate table of auxiliary flow rule structs. */
5088 : 0 : tbl->flow_aux = mlx5_malloc(MLX5_MEM_ZERO, sizeof(struct rte_flow_hw_aux) * nb_flows,
5089 : : RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
5090 [ # # ]: 0 : if (!tbl->flow_aux)
5091 : 0 : goto error;
5092 : : /* Register the flow group. */
5093 : 0 : ge = mlx5_hlist_register(priv->sh->groups, attr->flow_attr.group, &ctx);
5094 [ # # ]: 0 : if (!ge)
5095 : 0 : goto error;
5096 : : grp = container_of(ge, struct mlx5_flow_group, entry);
5097 : : /* Verify unified fdb sub domains consistency */
5098 : 0 : table_type = get_mlx5dr_table_type(&flow_attr, specialize, unified_fdb);
5099 [ # # ]: 0 : if (table_type != grp->type) {
5100 : 0 : DRV_LOG(ERR, "Table type (%u) does not match group id (%u) type (%u)",
5101 : : table_type, grp->group_id, grp->type);
5102 : 0 : rte_errno = EINVAL;
5103 : 0 : goto error;
5104 : : }
5105 : 0 : tbl->grp = grp;
5106 : : /* Prepare matcher information. */
5107 : 0 : matcher_attr.resizable = !!rte_flow_template_table_resizable
5108 : 0 : (dev->data->port_id, &table_cfg->attr);
5109 : 0 : matcher_attr.optimize_flow_src = MLX5DR_MATCHER_FLOW_SRC_ANY;
5110 : 0 : matcher_attr.priority = attr->flow_attr.priority;
5111 : 0 : matcher_attr.optimize_using_rule_idx = true;
5112 : 0 : matcher_attr.mode = MLX5DR_MATCHER_RESOURCE_MODE_RULE;
5113 [ # # ]: 0 : matcher_attr.insert_mode = flow_hw_matcher_insert_mode_get(attr->insertion_type);
5114 [ # # ]: 0 : if (matcher_attr.insert_mode == MLX5DR_MATCHER_INSERT_BY_INDEX) {
5115 [ # # ]: 0 : if (attr->insertion_type == RTE_FLOW_TABLE_INSERTION_TYPE_INDEX_WITH_PATTERN) {
5116 : 0 : matcher_attr.isolated = true;
5117 : 0 : matcher_attr.match_mode = MLX5DR_MATCHER_MATCH_MODE_DEFAULT;
5118 : : } else {
5119 : 0 : matcher_attr.isolated = false;
5120 : 0 : matcher_attr.match_mode = MLX5DR_MATCHER_MATCH_MODE_ALWAYS_HIT;
5121 : : }
5122 : : }
5123 [ # # ]: 0 : if (attr->hash_func == RTE_FLOW_TABLE_HASH_FUNC_CRC16) {
5124 : 0 : DRV_LOG(ERR, "16-bit checksum hash type is not supported");
5125 : 0 : rte_errno = ENOTSUP;
5126 : 0 : goto it_error;
5127 : : }
5128 [ # # ]: 0 : matcher_attr.distribute_mode = flow_hw_matcher_distribute_mode_get(attr->hash_func);
5129 : 0 : matcher_attr.rule.num_log = rte_log2_u32(nb_flows);
5130 : : /* Parse hints information. */
5131 [ # # ]: 0 : if (attr->specialize) {
5132 : : uint32_t val = RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_WIRE_ORIG |
5133 : : RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_VPORT_ORIG;
5134 : :
5135 [ # # ]: 0 : if ((attr->specialize & val) == val) {
5136 : 0 : DRV_LOG(ERR, "Invalid hint value %x",
5137 : : attr->specialize);
5138 : 0 : rte_errno = EINVAL;
5139 : 0 : goto it_error;
5140 : : }
5141 [ # # ]: 0 : if (attr->specialize &
5142 : : RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_WIRE_ORIG) {
5143 : 0 : matcher_attr.optimize_flow_src =
5144 : : MLX5DR_MATCHER_FLOW_SRC_WIRE;
5145 [ # # ]: 0 : } else if (attr->specialize &
5146 : : RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_VPORT_ORIG) {
5147 : 0 : matcher_attr.optimize_flow_src =
5148 : : MLX5DR_MATCHER_FLOW_SRC_VPORT;
5149 : : }
5150 : : }
5151 : : /* Build the item template. */
5152 [ # # ]: 0 : for (i = 0; i < nb_item_templates; i++) {
5153 : : uint32_t ret;
5154 : :
5155 [ # # # # ]: 0 : if ((flow_attr.ingress && !item_templates[i]->attr.ingress) ||
5156 [ # # # # ]: 0 : (flow_attr.egress && !item_templates[i]->attr.egress) ||
5157 [ # # # # ]: 0 : (flow_attr.transfer && !item_templates[i]->attr.transfer)) {
5158 : 0 : DRV_LOG(ERR, "pattern template and template table attribute mismatch");
5159 : 0 : rte_errno = EINVAL;
5160 : 0 : goto it_error;
5161 : : }
5162 [ # # ]: 0 : if (item_templates[i]->item_flags & MLX5_FLOW_ITEM_COMPARE)
5163 : 0 : matcher_attr.mode = MLX5DR_MATCHER_RESOURCE_MODE_HTABLE;
5164 : 0 : ret = rte_atomic_fetch_add_explicit(&item_templates[i]->refcnt, 1,
5165 : : rte_memory_order_relaxed) + 1;
5166 [ # # ]: 0 : if (ret <= 1) {
5167 : 0 : rte_errno = EINVAL;
5168 : 0 : goto it_error;
5169 : : }
5170 : 0 : mt[i] = item_templates[i]->mt;
5171 : 0 : tbl->its[i] = item_templates[i];
5172 : : }
5173 : 0 : tbl->nb_item_templates = nb_item_templates;
5174 : : /* Build the action template. */
5175 : 0 : err = mlx5_hw_build_template_table(dev, nb_action_templates,
5176 : : action_templates, at, tbl, &sub_error);
5177 [ # # ]: 0 : if (err) {
5178 : : i = nb_item_templates;
5179 : 0 : goto it_error;
5180 : : }
5181 : 0 : tbl->matcher_info[0].matcher = mlx5dr_matcher_create
5182 : 0 : (tbl->grp->tbl, mt, nb_item_templates, at, nb_action_templates, &matcher_attr);
5183 [ # # ]: 0 : if (!tbl->matcher_info[0].matcher)
5184 : 0 : goto at_error;
5185 : 0 : tbl->matcher_attr = matcher_attr;
5186 : 0 : tbl->type = table_type;
5187 [ # # ]: 0 : if (matcher_attr.isolated) {
5188 : 0 : jump_attr.matcher = tbl->matcher_info[0].matcher;
5189 : 0 : tbl->matcher_info[0].jump = mlx5dr_action_create_jump_to_matcher(priv->dr_ctx,
5190 : 0 : &jump_attr, mlx5_hw_act_flag[!!attr->flow_attr.group][tbl->type]);
5191 [ # # ]: 0 : if (!tbl->matcher_info[0].jump)
5192 : 0 : goto jtm_error;
5193 : : }
5194 : : /*
5195 : : * Only the matcher supports update and needs more than 1 WQE, an additional
5196 : : * index is needed. Or else the flow index can be reused.
5197 : : */
5198 [ # # # # ]: 0 : rpool_needed = mlx5dr_matcher_is_updatable(tbl->matcher_info[0].matcher) &&
5199 : 0 : mlx5dr_matcher_is_dependent(tbl->matcher_info[0].matcher);
5200 [ # # ]: 0 : if (rpool_needed) {
5201 : : /* Allocate rule indexed pool. */
5202 : 0 : cfg.size = 0;
5203 : 0 : cfg.type = "mlx5_hw_table_rule";
5204 : 0 : cfg.max_idx += priv->hw_q[0].size;
5205 : 0 : tbl->resource = mlx5_ipool_create(&cfg);
5206 [ # # ]: 0 : if (!tbl->resource)
5207 : 0 : goto res_error;
5208 : : }
5209 [ # # ]: 0 : if (port_started)
5210 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->flow_hw_tbl, tbl, next);
5211 : : else
5212 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->flow_hw_tbl_ongo, tbl, next);
5213 : : rte_rwlock_init(&tbl->matcher_replace_rwlk);
5214 : 0 : return tbl;
5215 : : res_error:
5216 [ # # ]: 0 : if (tbl->matcher_info[0].jump)
5217 : 0 : mlx5dr_action_destroy(tbl->matcher_info[0].jump);
5218 : 0 : jtm_error:
5219 [ # # ]: 0 : if (tbl->matcher_info[0].matcher)
5220 : 0 : (void)mlx5dr_matcher_destroy(tbl->matcher_info[0].matcher);
5221 : 0 : at_error:
5222 [ # # ]: 0 : for (i = 0; i < nb_action_templates; i++) {
5223 : 0 : __flow_hw_action_template_destroy(dev, &tbl->ats[i].acts);
5224 : 0 : rte_atomic_fetch_sub_explicit(&action_templates[i]->refcnt,
5225 : : 1, rte_memory_order_relaxed);
5226 : : }
5227 : : i = nb_item_templates;
5228 : : it_error:
5229 [ # # ]: 0 : while (i--)
5230 : 0 : rte_atomic_fetch_sub_explicit(&item_templates[i]->refcnt,
5231 : : 1, rte_memory_order_relaxed);
5232 : 0 : error:
5233 : 0 : err = rte_errno;
5234 [ # # ]: 0 : if (tbl) {
5235 [ # # ]: 0 : if (tbl->grp)
5236 : 0 : mlx5_hlist_unregister(priv->sh->groups,
5237 : : &tbl->grp->entry);
5238 [ # # ]: 0 : if (tbl->flow_aux)
5239 : 0 : mlx5_free(tbl->flow_aux);
5240 [ # # ]: 0 : if (tbl->flow)
5241 : 0 : mlx5_ipool_destroy(tbl->flow);
5242 : 0 : mlx5_free(tbl);
5243 : : }
5244 [ # # ]: 0 : if (error != NULL) {
5245 [ # # ]: 0 : if (sub_error.type == RTE_FLOW_ERROR_TYPE_NONE)
5246 : 0 : rte_flow_error_set(error, err, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5247 : : "Failed to create template table");
5248 : : else
5249 : : rte_memcpy(error, &sub_error, sizeof(sub_error));
5250 : : }
5251 : : return NULL;
5252 : : }
5253 : :
5254 : : /**
5255 : : * Update flow template table.
5256 : : *
5257 : : * @param[in] dev
5258 : : * Pointer to the rte_eth_dev structure.
5259 : : * @param[out] error
5260 : : * Pointer to error structure.
5261 : : *
5262 : : * @return
5263 : : * 0 on success, negative value otherwise and rte_errno is set.
5264 : : */
5265 : : int
5266 : 0 : flow_hw_table_update(struct rte_eth_dev *dev,
5267 : : struct rte_flow_error *error)
5268 : : {
5269 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
5270 : : struct rte_flow_template_table *tbl;
5271 : :
5272 [ # # ]: 0 : while ((tbl = LIST_FIRST(&priv->flow_hw_tbl_ongo)) != NULL) {
5273 [ # # ]: 0 : if (flow_hw_translate_all_actions_templates(dev, tbl, error))
5274 : : return -1;
5275 [ # # ]: 0 : LIST_REMOVE(tbl, next);
5276 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->flow_hw_tbl, tbl, next);
5277 : : }
5278 : : return 0;
5279 : : }
5280 : :
5281 : : static inline int
5282 : 0 : __translate_group(struct rte_eth_dev *dev,
5283 : : const struct rte_flow_attr *flow_attr,
5284 : : bool external,
5285 : : uint32_t group,
5286 : : uint32_t *table_group,
5287 : : struct rte_flow_error *error)
5288 : : {
5289 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
5290 : 0 : struct mlx5_sh_config *config = &priv->sh->config;
5291 : :
5292 [ # # ]: 0 : if (config->dv_esw_en &&
5293 [ # # # # ]: 0 : priv->fdb_def_rule &&
5294 [ # # ]: 0 : external &&
5295 : : flow_attr->transfer) {
5296 [ # # ]: 0 : if (group > MLX5_HW_MAX_TRANSFER_GROUP)
5297 : 0 : return rte_flow_error_set(error, EINVAL,
5298 : : RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5299 : : NULL,
5300 : : "group index not supported");
5301 : 0 : *table_group = group + 1;
5302 [ # # ]: 0 : } else if (config->dv_esw_en &&
5303 [ # # # # : 0 : (config->repr_matching || config->dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS) &&
# # ]
5304 [ # # ]: 0 : external &&
5305 : : flow_attr->egress) {
5306 : : /*
5307 : : * On E-Switch setups, default egress flow rules are inserted to allow
5308 : : * representor matching and/or preserving metadata across steering domains.
5309 : : * These flow rules are inserted in group 0 and this group is reserved by PMD
5310 : : * for these purposes.
5311 : : *
5312 : : * As a result, if representor matching or extended metadata mode is enabled,
5313 : : * group provided by the user must be incremented to avoid inserting flow rules
5314 : : * in group 0.
5315 : : */
5316 [ # # ]: 0 : if (group > MLX5_HW_MAX_EGRESS_GROUP)
5317 : 0 : return rte_flow_error_set(error, EINVAL,
5318 : : RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5319 : : NULL,
5320 : : "group index not supported");
5321 : 0 : *table_group = group + 1;
5322 : : } else {
5323 : 0 : *table_group = group;
5324 : : }
5325 : : return 0;
5326 : : }
5327 : :
5328 : : /**
5329 : : * Translates group index specified by the user in @p attr to internal
5330 : : * group index.
5331 : : *
5332 : : * Translation is done by incrementing group index, so group n becomes n + 1.
5333 : : *
5334 : : * @param[in] dev
5335 : : * Pointer to Ethernet device.
5336 : : * @param[in] cfg
5337 : : * Pointer to the template table configuration.
5338 : : * @param[in] group
5339 : : * Currently used group index (table group or jump destination).
5340 : : * @param[out] table_group
5341 : : * Pointer to output group index.
5342 : : * @param[out] error
5343 : : * Pointer to error structure.
5344 : : *
5345 : : * @return
5346 : : * 0 on success. Otherwise, returns negative error code, rte_errno is set
5347 : : * and error structure is filled.
5348 : : */
5349 : : static int
5350 : : flow_hw_translate_group(struct rte_eth_dev *dev,
5351 : : const struct mlx5_flow_template_table_cfg *cfg,
5352 : : uint32_t group,
5353 : : uint32_t *table_group,
5354 : : struct rte_flow_error *error)
5355 : : {
5356 : 0 : const struct rte_flow_attr *flow_attr = &cfg->attr.flow_attr;
5357 : :
5358 : 0 : return __translate_group(dev, flow_attr, cfg->external, group, table_group, error);
5359 : : }
5360 : :
5361 : : /**
5362 : : * Create flow table.
5363 : : *
5364 : : * This function is a wrapper over @ref flow_hw_table_create(), which translates parameters
5365 : : * provided by user to proper internal values.
5366 : : *
5367 : : * @param[in] dev
5368 : : * Pointer to Ethernet device.
5369 : : * @param[in] attr
5370 : : * Pointer to the table attributes.
5371 : : * @param[in] item_templates
5372 : : * Item template array to be binded to the table.
5373 : : * @param[in] nb_item_templates
5374 : : * Number of item templates.
5375 : : * @param[in] action_templates
5376 : : * Action template array to be binded to the table.
5377 : : * @param[in] nb_action_templates
5378 : : * Number of action templates.
5379 : : * @param[out] error
5380 : : * Pointer to error structure.
5381 : : *
5382 : : * @return
5383 : : * Table on success, Otherwise, returns negative error code, rte_errno is set
5384 : : * and error structure is filled.
5385 : : */
5386 : : static struct rte_flow_template_table *
5387 : 0 : flow_hw_template_table_create(struct rte_eth_dev *dev,
5388 : : const struct rte_flow_template_table_attr *attr,
5389 : : struct rte_flow_pattern_template *item_templates[],
5390 : : uint8_t nb_item_templates,
5391 : : struct rte_flow_actions_template *action_templates[],
5392 : : uint8_t nb_action_templates,
5393 : : struct rte_flow_error *error)
5394 : : {
5395 : 0 : struct mlx5_flow_template_table_cfg cfg = {
5396 : : .attr = *attr,
5397 : : .external = true,
5398 : : };
5399 : 0 : uint32_t group = attr->flow_attr.group;
5400 : :
5401 [ # # ]: 0 : if (flow_hw_translate_group(dev, &cfg, group, &cfg.attr.flow_attr.group, error))
5402 : : return NULL;
5403 [ # # # # ]: 0 : if (!cfg.attr.flow_attr.group &&
5404 : 0 : rte_flow_template_table_resizable(dev->data->port_id, attr)) {
5405 : 0 : rte_flow_error_set(error, EINVAL,
5406 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5407 : : "table cannot be resized: invalid group");
5408 : 0 : return NULL;
5409 : : }
5410 : 0 : return flow_hw_table_create(dev, &cfg, item_templates, nb_item_templates,
5411 : : action_templates, nb_action_templates, error);
5412 : : }
5413 : :
5414 : : static void
5415 : 0 : mlx5_destroy_multi_pattern_segment(struct mlx5_multi_pattern_segment *segment)
5416 : : {
5417 : : int i;
5418 : :
5419 [ # # ]: 0 : if (segment->mhdr_action)
5420 : 0 : mlx5dr_action_destroy(segment->mhdr_action);
5421 [ # # ]: 0 : for (i = 0; i < MLX5_MULTIPATTERN_ENCAP_NUM; i++) {
5422 [ # # ]: 0 : if (segment->reformat_action[i])
5423 : 0 : mlx5dr_action_destroy(segment->reformat_action[i]);
5424 : : }
5425 : 0 : segment->capacity = 0;
5426 : 0 : }
5427 : :
5428 : : static void
5429 : : flow_hw_destroy_table_multi_pattern_ctx(struct rte_flow_template_table *table)
5430 : : {
5431 : : int sx;
5432 : :
5433 [ # # ]: 0 : for (sx = 0; sx < MLX5_MAX_TABLE_RESIZE_NUM; sx++)
5434 : 0 : mlx5_destroy_multi_pattern_segment(table->mpctx.segments + sx);
5435 : : }
5436 : : /**
5437 : : * Destroy flow table.
5438 : : *
5439 : : * @param[in] dev
5440 : : * Pointer to the rte_eth_dev structure.
5441 : : * @param[in] table
5442 : : * Pointer to the table to be destroyed.
5443 : : * @param[out] error
5444 : : * Pointer to error structure.
5445 : : *
5446 : : * @return
5447 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
5448 : : */
5449 : : static int
5450 : 0 : flow_hw_table_destroy(struct rte_eth_dev *dev,
5451 : : struct rte_flow_template_table *table,
5452 : : struct rte_flow_error *error)
5453 : : {
5454 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
5455 : : int i;
5456 : 0 : uint32_t fidx = 1;
5457 : 0 : uint32_t ridx = 1;
5458 : :
5459 : : /* Build ipool allocated object bitmap. */
5460 [ # # ]: 0 : if (table->resource)
5461 : 0 : mlx5_ipool_flush_cache(table->resource);
5462 : 0 : mlx5_ipool_flush_cache(table->flow);
5463 : : /* Check if ipool has allocated objects. */
5464 [ # # # # ]: 0 : if (table->refcnt ||
5465 : 0 : mlx5_ipool_get_next(table->flow, &fidx) ||
5466 [ # # # # ]: 0 : (table->resource && mlx5_ipool_get_next(table->resource, &ridx))) {
5467 : 0 : DRV_LOG(WARNING, "Table %p is still in use.", (void *)table);
5468 : 0 : return rte_flow_error_set(error, EBUSY,
5469 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5470 : : NULL,
5471 : : "table is in use");
5472 : : }
5473 [ # # ]: 0 : LIST_REMOVE(table, next);
5474 [ # # ]: 0 : for (i = 0; i < table->nb_item_templates; i++)
5475 : 0 : rte_atomic_fetch_sub_explicit(&table->its[i]->refcnt,
5476 : : 1, rte_memory_order_relaxed);
5477 [ # # ]: 0 : for (i = 0; i < table->nb_action_templates; i++) {
5478 : 0 : __flow_hw_action_template_destroy(dev, &table->ats[i].acts);
5479 : 0 : rte_atomic_fetch_sub_explicit(&table->ats[i].action_template->refcnt,
5480 : : 1, rte_memory_order_relaxed);
5481 : : }
5482 : : flow_hw_destroy_table_multi_pattern_ctx(table);
5483 [ # # ]: 0 : if (table->matcher_info[0].jump)
5484 : 0 : mlx5dr_action_destroy(table->matcher_info[0].jump);
5485 [ # # ]: 0 : if (table->matcher_info[0].matcher)
5486 : 0 : mlx5dr_matcher_destroy(table->matcher_info[0].matcher);
5487 [ # # ]: 0 : if (table->matcher_info[1].jump)
5488 : 0 : mlx5dr_action_destroy(table->matcher_info[1].jump);
5489 [ # # ]: 0 : if (table->matcher_info[1].matcher)
5490 : 0 : mlx5dr_matcher_destroy(table->matcher_info[1].matcher);
5491 : 0 : mlx5_hlist_unregister(priv->sh->groups, &table->grp->entry);
5492 [ # # ]: 0 : if (table->resource)
5493 : 0 : mlx5_ipool_destroy(table->resource);
5494 : 0 : mlx5_free(table->flow_aux);
5495 : 0 : mlx5_ipool_destroy(table->flow);
5496 : 0 : mlx5_free(table);
5497 : 0 : return 0;
5498 : : }
5499 : :
5500 : : /**
5501 : : * Parse group's miss actions.
5502 : : *
5503 : : * @param[in] dev
5504 : : * Pointer to the rte_eth_dev structure.
5505 : : * @param[in] cfg
5506 : : * Pointer to the table_cfg structure.
5507 : : * @param[in] actions
5508 : : * Array of actions to perform on group miss. Supported types:
5509 : : * RTE_FLOW_ACTION_TYPE_JUMP, RTE_FLOW_ACTION_TYPE_VOID, RTE_FLOW_ACTION_TYPE_END.
5510 : : * @param[out] dst_group_id
5511 : : * Pointer to destination group id output. will be set to 0 if actions is END,
5512 : : * otherwise will be set to destination group id.
5513 : : * @param[out] error
5514 : : * Pointer to error structure.
5515 : : *
5516 : : * @return
5517 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
5518 : : */
5519 : :
5520 : : static int
5521 : 0 : flow_hw_group_parse_miss_actions(struct rte_eth_dev *dev,
5522 : : struct mlx5_flow_template_table_cfg *cfg,
5523 : : const struct rte_flow_action actions[],
5524 : : uint32_t *dst_group_id,
5525 : : struct rte_flow_error *error)
5526 : : {
5527 : : const struct rte_flow_action_jump *jump_conf;
5528 : 0 : uint32_t temp = 0;
5529 : : uint32_t i;
5530 : :
5531 [ # # ]: 0 : for (i = 0; actions[i].type != RTE_FLOW_ACTION_TYPE_END; i++) {
5532 [ # # # ]: 0 : switch (actions[i].type) {
5533 : 0 : case RTE_FLOW_ACTION_TYPE_VOID:
5534 : 0 : continue;
5535 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP:
5536 [ # # ]: 0 : if (temp)
5537 : 0 : return rte_flow_error_set(error, ENOTSUP,
5538 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, actions,
5539 : : "Miss actions can contain only a single JUMP");
5540 : :
5541 : 0 : jump_conf = (const struct rte_flow_action_jump *)actions[i].conf;
5542 [ # # ]: 0 : if (!jump_conf)
5543 : 0 : return rte_flow_error_set(error, EINVAL,
5544 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5545 : : jump_conf, "Jump conf must not be NULL");
5546 : :
5547 [ # # ]: 0 : if (flow_hw_translate_group(dev, cfg, jump_conf->group, &temp, error))
5548 : 0 : return -rte_errno;
5549 : :
5550 [ # # ]: 0 : if (!temp)
5551 : 0 : return rte_flow_error_set(error, EINVAL,
5552 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5553 : : "Failed to set group miss actions - Invalid target group");
5554 : : break;
5555 : 0 : default:
5556 : 0 : return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
5557 : : &actions[i], "Unsupported default miss action type");
5558 : : }
5559 : : }
5560 : :
5561 : 0 : *dst_group_id = temp;
5562 : 0 : return 0;
5563 : : }
5564 : :
5565 : : /**
5566 : : * Set group's miss group.
5567 : : *
5568 : : * @param[in] dev
5569 : : * Pointer to the rte_eth_dev structure.
5570 : : * @param[in] cfg
5571 : : * Pointer to the table_cfg structure.
5572 : : * @param[in] src_grp
5573 : : * Pointer to source group structure.
5574 : : * if NULL, a new group will be created based on group id from cfg->attr.flow_attr.group.
5575 : : * @param[in] dst_grp
5576 : : * Pointer to destination group structure.
5577 : : * @param[out] error
5578 : : * Pointer to error structure.
5579 : : *
5580 : : * @return
5581 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
5582 : : */
5583 : :
5584 : : static int
5585 : 0 : flow_hw_group_set_miss_group(struct rte_eth_dev *dev,
5586 : : struct mlx5_flow_template_table_cfg *cfg,
5587 : : struct mlx5_flow_group *src_grp,
5588 : : struct mlx5_flow_group *dst_grp,
5589 : : struct rte_flow_error *error)
5590 : : {
5591 : 0 : struct rte_flow_error sub_error = {
5592 : : .type = RTE_FLOW_ERROR_TYPE_NONE,
5593 : : .cause = NULL,
5594 : : .message = NULL,
5595 : : };
5596 : 0 : struct mlx5_flow_cb_ctx ctx = {
5597 : : .dev = dev,
5598 : : .error = &sub_error,
5599 : 0 : .data = &cfg->attr.flow_attr,
5600 : 0 : .data2 = &cfg->attr.specialize,
5601 : : };
5602 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
5603 : : struct mlx5_list_entry *ge;
5604 : : bool ref = false;
5605 : : int ret;
5606 : :
5607 [ # # ]: 0 : if (!dst_grp)
5608 : : return -EINVAL;
5609 : :
5610 : : /* If group doesn't exist - needs to be created. */
5611 [ # # ]: 0 : if (!src_grp) {
5612 : 0 : ge = mlx5_hlist_register(priv->sh->groups, cfg->attr.flow_attr.group, &ctx);
5613 [ # # ]: 0 : if (!ge)
5614 : 0 : return -rte_errno;
5615 : :
5616 : : src_grp = container_of(ge, struct mlx5_flow_group, entry);
5617 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->flow_hw_grp, src_grp, next);
5618 : : ref = true;
5619 [ # # ]: 0 : } else if (!src_grp->miss_group) {
5620 : : /* If group exists, but has no miss actions - need to increase ref_cnt. */
5621 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->flow_hw_grp, src_grp, next);
5622 : 0 : src_grp->entry.ref_cnt++;
5623 : : ref = true;
5624 : : }
5625 : :
5626 : 0 : ret = mlx5dr_table_set_default_miss(src_grp->tbl, dst_grp->tbl);
5627 [ # # ]: 0 : if (ret)
5628 : 0 : goto mlx5dr_error;
5629 : :
5630 : : /* If group existed and had old miss actions - ref_cnt is already correct.
5631 : : * However, need to reduce ref counter for old miss group.
5632 : : */
5633 [ # # ]: 0 : if (src_grp->miss_group)
5634 : 0 : mlx5_hlist_unregister(priv->sh->groups, &src_grp->miss_group->entry);
5635 : :
5636 : 0 : src_grp->miss_group = dst_grp;
5637 : 0 : return 0;
5638 : :
5639 : : mlx5dr_error:
5640 : : /* Reduce src_grp ref_cnt back & remove from grp list in case of mlx5dr error */
5641 [ # # ]: 0 : if (ref) {
5642 : 0 : mlx5_hlist_unregister(priv->sh->groups, &src_grp->entry);
5643 [ # # ]: 0 : LIST_REMOVE(src_grp, next);
5644 : : }
5645 : :
5646 : 0 : return rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5647 : : "Failed to set group miss actions");
5648 : : }
5649 : :
5650 : : /**
5651 : : * Unset group's miss group.
5652 : : *
5653 : : * @param[in] dev
5654 : : * Pointer to the rte_eth_dev structure.
5655 : : * @param[in] grp
5656 : : * Pointer to group structure.
5657 : : * @param[out] error
5658 : : * Pointer to error structure.
5659 : : *
5660 : : * @return
5661 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
5662 : : */
5663 : :
5664 : : static int
5665 : 0 : flow_hw_group_unset_miss_group(struct rte_eth_dev *dev,
5666 : : struct mlx5_flow_group *grp,
5667 : : struct rte_flow_error *error)
5668 : : {
5669 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
5670 : : int ret;
5671 : :
5672 : : /* If group doesn't exist - no need to change anything. */
5673 [ # # ]: 0 : if (!grp)
5674 : : return 0;
5675 : :
5676 : : /* If group exists, but miss actions is already default behavior -
5677 : : * no need to change anything.
5678 : : */
5679 [ # # ]: 0 : if (!grp->miss_group)
5680 : : return 0;
5681 : :
5682 : 0 : ret = mlx5dr_table_set_default_miss(grp->tbl, NULL);
5683 [ # # ]: 0 : if (ret)
5684 : 0 : return rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5685 : : "Failed to unset group miss actions");
5686 : :
5687 : 0 : mlx5_hlist_unregister(priv->sh->groups, &grp->miss_group->entry);
5688 : 0 : grp->miss_group = NULL;
5689 : :
5690 [ # # ]: 0 : LIST_REMOVE(grp, next);
5691 : 0 : mlx5_hlist_unregister(priv->sh->groups, &grp->entry);
5692 : :
5693 : 0 : return 0;
5694 : : }
5695 : :
5696 : : /**
5697 : : * Set group miss actions.
5698 : : *
5699 : : * @param[in] dev
5700 : : * Pointer to the rte_eth_dev structure.
5701 : : * @param[in] group_id
5702 : : * Group id.
5703 : : * @param[in] attr
5704 : : * Pointer to group attributes structure.
5705 : : * @param[in] actions
5706 : : * Array of actions to perform on group miss. Supported types:
5707 : : * RTE_FLOW_ACTION_TYPE_JUMP, RTE_FLOW_ACTION_TYPE_VOID, RTE_FLOW_ACTION_TYPE_END.
5708 : : * @param[out] error
5709 : : * Pointer to error structure.
5710 : : *
5711 : : * @return
5712 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
5713 : : */
5714 : :
5715 : : int
5716 : 0 : mlx5_flow_hw_group_set_miss_actions(struct rte_eth_dev *dev,
5717 : : uint32_t group_id,
5718 : : const struct rte_flow_group_attr *attr,
5719 : : const struct rte_flow_action actions[],
5720 : : struct rte_flow_error *error)
5721 : : {
5722 : 0 : struct rte_flow_error sub_error = {
5723 : : .type = RTE_FLOW_ERROR_TYPE_NONE,
5724 : : .cause = NULL,
5725 : : .message = NULL,
5726 : : };
5727 : 0 : struct mlx5_flow_template_table_cfg cfg = {
5728 : : .external = true,
5729 : : .attr = {
5730 : : .flow_attr = {
5731 : : .group = group_id,
5732 : 0 : .ingress = attr->ingress,
5733 : 0 : .egress = attr->egress,
5734 : 0 : .transfer = attr->transfer,
5735 : : },
5736 : : },
5737 : : };
5738 : 0 : struct mlx5_flow_cb_ctx ctx = {
5739 : : .dev = dev,
5740 : : .error = &sub_error,
5741 : : .data = &cfg.attr.flow_attr,
5742 : : .data2 = &cfg.attr.specialize,
5743 : : };
5744 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
5745 : : struct mlx5_flow_group *src_grp = NULL;
5746 : : struct mlx5_flow_group *dst_grp = NULL;
5747 : : struct mlx5_list_entry *ge;
5748 : 0 : uint32_t dst_group_id = 0;
5749 : : int ret;
5750 : :
5751 [ # # ]: 0 : if (flow_hw_translate_group(dev, &cfg, group_id, &group_id, error))
5752 : 0 : return -rte_errno;
5753 : :
5754 [ # # ]: 0 : if (!group_id)
5755 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5756 : : NULL, "Failed to set group miss actions - invalid group id");
5757 : :
5758 : 0 : ret = flow_hw_group_parse_miss_actions(dev, &cfg, actions, &dst_group_id, error);
5759 [ # # ]: 0 : if (ret)
5760 : 0 : return -rte_errno;
5761 : :
5762 [ # # ]: 0 : if (dst_group_id == group_id) {
5763 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5764 : : NULL, "Failed to set group miss actions - target group id must differ from group_id");
5765 : : }
5766 : :
5767 : 0 : cfg.attr.flow_attr.group = group_id;
5768 : 0 : ge = mlx5_hlist_lookup(priv->sh->groups, group_id, &ctx);
5769 [ # # ]: 0 : if (ge)
5770 : : src_grp = container_of(ge, struct mlx5_flow_group, entry);
5771 : :
5772 [ # # ]: 0 : if (dst_group_id) {
5773 : : /* Increase ref_cnt for new miss group. */
5774 : 0 : cfg.attr.flow_attr.group = dst_group_id;
5775 : 0 : ge = mlx5_hlist_register(priv->sh->groups, dst_group_id, &ctx);
5776 [ # # ]: 0 : if (!ge)
5777 : 0 : return -rte_errno;
5778 : :
5779 : : dst_grp = container_of(ge, struct mlx5_flow_group, entry);
5780 : :
5781 : 0 : cfg.attr.flow_attr.group = group_id;
5782 : 0 : ret = flow_hw_group_set_miss_group(dev, &cfg, src_grp, dst_grp, error);
5783 [ # # ]: 0 : if (ret)
5784 : 0 : goto error;
5785 : : } else {
5786 : 0 : return flow_hw_group_unset_miss_group(dev, src_grp, error);
5787 : : }
5788 : :
5789 : : return 0;
5790 : :
5791 : : error:
5792 : : if (dst_grp)
5793 : 0 : mlx5_hlist_unregister(priv->sh->groups, &dst_grp->entry);
5794 : 0 : return -rte_errno;
5795 : : }
5796 : :
5797 : : static bool
5798 : : flow_hw_modify_field_is_used(const struct rte_flow_action_modify_field *action,
5799 : : enum rte_flow_field_id field)
5800 : : {
5801 [ # # # # : 0 : return action->src.field == field || action->dst.field == field;
# # # # #
# # # # #
# # # # #
# # # # #
# # # # ]
5802 : : }
5803 : :
5804 : : static bool
5805 : : flow_hw_modify_field_is_geneve_opt(enum rte_flow_field_id field)
5806 : : {
5807 : : return field == RTE_FLOW_FIELD_GENEVE_OPT_TYPE ||
5808 : 0 : field == RTE_FLOW_FIELD_GENEVE_OPT_CLASS ||
5809 : : field == RTE_FLOW_FIELD_GENEVE_OPT_DATA;
5810 : : }
5811 : :
5812 : : static bool
5813 : 0 : flow_hw_modify_field_is_add_dst_valid(const struct rte_flow_action_modify_field *conf)
5814 : : {
5815 [ # # ]: 0 : if (conf->operation != RTE_FLOW_MODIFY_ADD)
5816 : : return true;
5817 [ # # ]: 0 : if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
5818 : : conf->src.field == RTE_FLOW_FIELD_VALUE)
5819 : : return true;
5820 [ # # ]: 0 : switch (conf->dst.field) {
5821 : : case RTE_FLOW_FIELD_IPV4_TTL:
5822 : : case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
5823 : : case RTE_FLOW_FIELD_TCP_SEQ_NUM:
5824 : : case RTE_FLOW_FIELD_TCP_ACK_NUM:
5825 : : case RTE_FLOW_FIELD_TAG:
5826 : : case RTE_FLOW_FIELD_META:
5827 : : case RTE_FLOW_FIELD_FLEX_ITEM:
5828 : : case RTE_FLOW_FIELD_TCP_DATA_OFFSET:
5829 : : case RTE_FLOW_FIELD_IPV4_IHL:
5830 : : case RTE_FLOW_FIELD_IPV4_TOTAL_LEN:
5831 : : case RTE_FLOW_FIELD_IPV6_PAYLOAD_LEN:
5832 : : return true;
5833 : : default:
5834 : : break;
5835 : : }
5836 : 0 : return false;
5837 : : }
5838 : :
5839 : : /**
5840 : : * Validate the level value for modify field action.
5841 : : *
5842 : : * @param[in] data
5843 : : * Pointer to the rte_flow_field_data structure either src or dst.
5844 : : * @param[in] inner_supported
5845 : : * Indicator whether inner should be supported.
5846 : : * @param[out] error
5847 : : * Pointer to error structure.
5848 : : *
5849 : : * @return
5850 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
5851 : : */
5852 : : static int
5853 : 0 : flow_hw_validate_modify_field_level(const struct rte_flow_field_data *data,
5854 : : bool inner_supported,
5855 : : struct rte_flow_error *error)
5856 : : {
5857 [ # # # # : 0 : switch ((int)data->field) {
# ]
5858 : : case RTE_FLOW_FIELD_START:
5859 : : case RTE_FLOW_FIELD_VLAN_TYPE:
5860 : : case RTE_FLOW_FIELD_RANDOM:
5861 : : case RTE_FLOW_FIELD_FLEX_ITEM:
5862 : : /*
5863 : : * Level shouldn't be valid since field isn't supported or
5864 : : * doesn't use 'level'.
5865 : : */
5866 : : break;
5867 : : case RTE_FLOW_FIELD_MARK:
5868 : : case RTE_FLOW_FIELD_META:
5869 : : case RTE_FLOW_FIELD_METER_COLOR:
5870 : : case RTE_FLOW_FIELD_HASH_RESULT:
5871 : : /* For meta data fields encapsulation level is don't-care. */
5872 : : break;
5873 : 0 : case RTE_FLOW_FIELD_TAG:
5874 : : case MLX5_RTE_FLOW_FIELD_META_REG:
5875 : : /*
5876 : : * The tag array for RTE_FLOW_FIELD_TAG type is provided using
5877 : : * 'tag_index' field. In old API, it was provided using 'level'
5878 : : * field and it is still supported for backwards compatibility.
5879 : : * Therefore, for meta tag field only, level is matter. It is
5880 : : * taken as tag index when 'tag_index' field isn't set, and
5881 : : * return error otherwise.
5882 : : */
5883 [ # # ]: 0 : if (data->level > 0) {
5884 [ # # ]: 0 : if (data->tag_index > 0)
5885 : 0 : return rte_flow_error_set(error, EINVAL,
5886 : : RTE_FLOW_ERROR_TYPE_ACTION,
5887 : : data,
5888 : : "tag array can be provided using 'level' or 'tag_index' fields, not both");
5889 : 0 : DRV_LOG(WARNING,
5890 : : "tag array provided in 'level' field instead of 'tag_index' field.");
5891 : : }
5892 : : break;
5893 : 0 : case RTE_FLOW_FIELD_MAC_DST:
5894 : : case RTE_FLOW_FIELD_MAC_SRC:
5895 : : case RTE_FLOW_FIELD_MAC_TYPE:
5896 : : case RTE_FLOW_FIELD_IPV4_IHL:
5897 : : case RTE_FLOW_FIELD_IPV4_TOTAL_LEN:
5898 : : case RTE_FLOW_FIELD_IPV4_DSCP:
5899 : : case RTE_FLOW_FIELD_IPV4_ECN:
5900 : : case RTE_FLOW_FIELD_IPV4_TTL:
5901 : : case RTE_FLOW_FIELD_IPV4_SRC:
5902 : : case RTE_FLOW_FIELD_IPV4_DST:
5903 : : case RTE_FLOW_FIELD_IPV6_TRAFFIC_CLASS:
5904 : : case RTE_FLOW_FIELD_IPV6_FLOW_LABEL:
5905 : : case RTE_FLOW_FIELD_IPV6_PAYLOAD_LEN:
5906 : : case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
5907 : : case RTE_FLOW_FIELD_IPV6_SRC:
5908 : : case RTE_FLOW_FIELD_IPV6_DST:
5909 : : case RTE_FLOW_FIELD_TCP_PORT_SRC:
5910 : : case RTE_FLOW_FIELD_TCP_PORT_DST:
5911 : : case RTE_FLOW_FIELD_TCP_FLAGS:
5912 : : case RTE_FLOW_FIELD_TCP_DATA_OFFSET:
5913 : : case RTE_FLOW_FIELD_UDP_PORT_SRC:
5914 : : case RTE_FLOW_FIELD_UDP_PORT_DST:
5915 [ # # ]: 0 : if (data->level > 2)
5916 : 0 : return rte_flow_error_set(error, ENOTSUP,
5917 : : RTE_FLOW_ERROR_TYPE_ACTION,
5918 : : data,
5919 : : "second inner header fields modification is not supported");
5920 [ # # ]: 0 : if (inner_supported)
5921 : : break;
5922 : : /* Fallthrough */
5923 : : case RTE_FLOW_FIELD_VLAN_ID:
5924 : : case RTE_FLOW_FIELD_IPV4_PROTO:
5925 : : case RTE_FLOW_FIELD_IPV6_PROTO:
5926 : : case RTE_FLOW_FIELD_IPV6_DSCP:
5927 : : case RTE_FLOW_FIELD_IPV6_ECN:
5928 : : case RTE_FLOW_FIELD_TCP_SEQ_NUM:
5929 : : case RTE_FLOW_FIELD_TCP_ACK_NUM:
5930 : : case RTE_FLOW_FIELD_ESP_PROTO:
5931 : : case RTE_FLOW_FIELD_ESP_SPI:
5932 : : case RTE_FLOW_FIELD_ESP_SEQ_NUM:
5933 : : case RTE_FLOW_FIELD_VXLAN_VNI:
5934 : : case RTE_FLOW_FIELD_VXLAN_LAST_RSVD:
5935 : : case RTE_FLOW_FIELD_GENEVE_VNI:
5936 : : case RTE_FLOW_FIELD_GENEVE_OPT_TYPE:
5937 : : case RTE_FLOW_FIELD_GENEVE_OPT_CLASS:
5938 : : case RTE_FLOW_FIELD_GENEVE_OPT_DATA:
5939 : : case RTE_FLOW_FIELD_GTP_TEID:
5940 : : case RTE_FLOW_FIELD_GTP_PSC_QFI:
5941 [ # # ]: 0 : if (data->level > 1)
5942 : 0 : return rte_flow_error_set(error, ENOTSUP,
5943 : : RTE_FLOW_ERROR_TYPE_ACTION,
5944 : : data,
5945 : : "inner header fields modification is not supported");
5946 : : break;
5947 : 0 : case RTE_FLOW_FIELD_MPLS:
5948 [ # # ]: 0 : if (data->level == 1)
5949 : 0 : return rte_flow_error_set(error, ENOTSUP,
5950 : : RTE_FLOW_ERROR_TYPE_ACTION,
5951 : : data,
5952 : : "outer MPLS header modification is not supported");
5953 [ # # ]: 0 : if (data->level > 2)
5954 : 0 : return rte_flow_error_set(error, ENOTSUP,
5955 : : RTE_FLOW_ERROR_TYPE_ACTION,
5956 : : data,
5957 : : "inner MPLS header modification is not supported");
5958 : : break;
5959 : 0 : case RTE_FLOW_FIELD_POINTER:
5960 : : case RTE_FLOW_FIELD_VALUE:
5961 : : default:
5962 : : MLX5_ASSERT(false);
5963 : : }
5964 : : return 0;
5965 : : }
5966 : :
5967 : : static int
5968 : 0 : flow_hw_validate_action_modify_field(struct rte_eth_dev *dev,
5969 : : const struct rte_flow_action *action,
5970 : : const struct rte_flow_action *mask,
5971 : : struct rte_flow_error *error)
5972 : : {
5973 : 0 : const struct rte_flow_action_modify_field *action_conf = action->conf;
5974 : 0 : const struct rte_flow_action_modify_field *mask_conf = mask->conf;
5975 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
5976 : 0 : struct mlx5_hca_attr *attr = &priv->sh->cdev->config.hca_attr;
5977 : : int ret;
5978 : :
5979 [ # # ]: 0 : if (!mask_conf)
5980 : 0 : return rte_flow_error_set(error, EINVAL,
5981 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
5982 : : "modify_field mask conf is missing");
5983 [ # # ]: 0 : if (action_conf->operation != mask_conf->operation)
5984 : 0 : return rte_flow_error_set(error, EINVAL,
5985 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
5986 : : "modify_field operation mask and template are not equal");
5987 [ # # ]: 0 : if (action_conf->dst.field != mask_conf->dst.field)
5988 : 0 : return rte_flow_error_set(error, EINVAL,
5989 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
5990 : : "destination field mask and template are not equal");
5991 : 0 : if (action_conf->dst.field == RTE_FLOW_FIELD_POINTER ||
5992 [ # # ]: 0 : action_conf->dst.field == RTE_FLOW_FIELD_VALUE ||
5993 : : action_conf->dst.field == RTE_FLOW_FIELD_HASH_RESULT)
5994 : 0 : return rte_flow_error_set(error, EINVAL,
5995 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
5996 : : "immediate value, pointer and hash result cannot be used as destination");
5997 : 0 : ret = flow_hw_validate_modify_field_level(&action_conf->dst, false, error);
5998 [ # # ]: 0 : if (ret)
5999 : : return ret;
6000 [ # # # # ]: 0 : if (action_conf->dst.field != RTE_FLOW_FIELD_FLEX_ITEM &&
6001 : : !flow_hw_modify_field_is_geneve_opt(action_conf->dst.field)) {
6002 [ # # ]: 0 : if (action_conf->dst.tag_index &&
6003 : : !flow_modify_field_support_tag_array(action_conf->dst.field))
6004 : 0 : return rte_flow_error_set(error, EINVAL,
6005 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6006 : : "destination tag index is not supported");
6007 [ # # ]: 0 : if (action_conf->dst.class_id)
6008 : 0 : return rte_flow_error_set(error, EINVAL,
6009 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6010 : : "destination class id is not supported");
6011 : : }
6012 [ # # ]: 0 : if (mask_conf->dst.level != UINT8_MAX)
6013 : 0 : return rte_flow_error_set(error, EINVAL,
6014 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6015 : : "destination encapsulation level must be fully masked");
6016 [ # # ]: 0 : if (mask_conf->dst.offset != UINT32_MAX)
6017 : 0 : return rte_flow_error_set(error, EINVAL,
6018 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6019 : : "destination offset level must be fully masked");
6020 [ # # ]: 0 : if (action_conf->src.field != mask_conf->src.field)
6021 : 0 : return rte_flow_error_set(error, EINVAL,
6022 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6023 : : "destination field mask and template are not equal");
6024 [ # # ]: 0 : if (action_conf->src.field != RTE_FLOW_FIELD_POINTER &&
6025 : : action_conf->src.field != RTE_FLOW_FIELD_VALUE) {
6026 [ # # # # ]: 0 : if (action_conf->src.field != RTE_FLOW_FIELD_FLEX_ITEM &&
6027 : : !flow_hw_modify_field_is_geneve_opt(action_conf->src.field)) {
6028 [ # # ]: 0 : if (action_conf->src.tag_index &&
6029 : : !flow_modify_field_support_tag_array(action_conf->src.field))
6030 : 0 : return rte_flow_error_set(error, EINVAL,
6031 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6032 : : "source tag index is not supported");
6033 [ # # ]: 0 : if (action_conf->src.class_id)
6034 : 0 : return rte_flow_error_set(error, EINVAL,
6035 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6036 : : "source class id is not supported");
6037 : : }
6038 [ # # ]: 0 : if (mask_conf->src.level != UINT8_MAX)
6039 : 0 : return rte_flow_error_set(error, EINVAL,
6040 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6041 : : "source encapsulation level must be fully masked");
6042 [ # # ]: 0 : if (mask_conf->src.offset != UINT32_MAX)
6043 : 0 : return rte_flow_error_set(error, EINVAL,
6044 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6045 : : "source offset level must be fully masked");
6046 : 0 : ret = flow_hw_validate_modify_field_level(&action_conf->src, true, error);
6047 [ # # ]: 0 : if (ret)
6048 : : return ret;
6049 : : }
6050 [ # # ]: 0 : if ((action_conf->dst.field == RTE_FLOW_FIELD_TAG &&
6051 [ # # # # ]: 0 : action_conf->dst.tag_index >= MLX5_FLOW_HW_TAGS_MAX &&
6052 : 0 : action_conf->dst.tag_index != RTE_PMD_MLX5_LINEAR_HASH_TAG_INDEX) ||
6053 [ # # ]: 0 : (action_conf->src.field == RTE_FLOW_FIELD_TAG &&
6054 [ # # # # ]: 0 : action_conf->src.tag_index >= MLX5_FLOW_HW_TAGS_MAX &&
6055 : : action_conf->src.tag_index != RTE_PMD_MLX5_LINEAR_HASH_TAG_INDEX))
6056 : 0 : return rte_flow_error_set(error, EINVAL,
6057 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6058 : : "tag index is out of range");
6059 [ # # # # ]: 0 : if ((action_conf->dst.field == RTE_FLOW_FIELD_TAG &&
6060 [ # # # # ]: 0 : flow_hw_get_reg_id(dev, RTE_FLOW_ITEM_TYPE_TAG, action_conf->dst.tag_index) == REG_NON) ||
6061 [ # # ]: 0 : (action_conf->src.field == RTE_FLOW_FIELD_TAG &&
6062 [ # # ]: 0 : flow_hw_get_reg_id(dev, RTE_FLOW_ITEM_TYPE_TAG, action_conf->src.tag_index) == REG_NON))
6063 : 0 : return rte_flow_error_set(error, EINVAL,
6064 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6065 : : "tag index is out of range");
6066 [ # # ]: 0 : if (mask_conf->width != UINT32_MAX)
6067 : 0 : return rte_flow_error_set(error, EINVAL,
6068 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6069 : : "modify_field width field must be fully masked");
6070 [ # # ]: 0 : if (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_START))
6071 : 0 : return rte_flow_error_set(error, EINVAL,
6072 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6073 : : "modifying arbitrary place in a packet is not supported");
6074 [ # # ]: 0 : if (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_VLAN_TYPE))
6075 : 0 : return rte_flow_error_set(error, EINVAL,
6076 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6077 : : "modifying vlan_type is not supported");
6078 [ # # ]: 0 : if (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_RANDOM))
6079 : 0 : return rte_flow_error_set(error, EINVAL,
6080 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6081 : : "modifying random value is not supported");
6082 : : /**
6083 : : * Geneve VNI modification is supported only when Geneve header is
6084 : : * parsed natively. When GENEVE options are supported, they both Geneve
6085 : : * and options headers are parsed as a flex parser.
6086 : : */
6087 [ # # ]: 0 : if (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_GENEVE_VNI) &&
6088 [ # # ]: 0 : attr->geneve_tlv_opt)
6089 : 0 : return rte_flow_error_set(error, EINVAL,
6090 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6091 : : "modifying Geneve VNI is not supported when GENEVE opt is supported");
6092 [ # # # # ]: 0 : if (priv->tlv_options == NULL &&
6093 [ # # ]: 0 : (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_GENEVE_OPT_TYPE) ||
6094 [ # # ]: 0 : flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_GENEVE_OPT_CLASS) ||
6095 : : flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_GENEVE_OPT_DATA)))
6096 : 0 : return rte_flow_error_set(error, EINVAL,
6097 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6098 : : "modifying Geneve TLV option is supported only after parser configuration");
6099 : : /* Due to HW bug, tunnel MPLS header is read only. */
6100 [ # # ]: 0 : if (action_conf->dst.field == RTE_FLOW_FIELD_MPLS)
6101 : 0 : return rte_flow_error_set(error, EINVAL,
6102 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6103 : : "MPLS cannot be used as destination");
6104 : : /* ADD_FIELD is not supported for all the fields. */
6105 [ # # ]: 0 : if (!flow_hw_modify_field_is_add_dst_valid(action_conf))
6106 : 0 : return rte_flow_error_set(error, EINVAL,
6107 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6108 : : "invalid add_field destination");
6109 : : return 0;
6110 : : }
6111 : :
6112 : : static int
6113 : 0 : flow_hw_validate_action_port_representor(struct rte_eth_dev *dev __rte_unused,
6114 : : const struct rte_flow_actions_template_attr *attr,
6115 : : const struct rte_flow_action *action,
6116 : : const struct rte_flow_action *mask,
6117 : : struct rte_flow_error *error)
6118 : : {
6119 : : const struct rte_flow_action_ethdev *action_conf = NULL;
6120 : : const struct rte_flow_action_ethdev *mask_conf = NULL;
6121 : :
6122 : : /* If transfer is set, port has been validated as proxy port. */
6123 [ # # ]: 0 : if (!attr->transfer)
6124 : 0 : return rte_flow_error_set(error, EINVAL,
6125 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6126 : : "cannot use port_representor actions"
6127 : : " without an E-Switch");
6128 [ # # ]: 0 : if (!action || !mask)
6129 : 0 : return rte_flow_error_set(error, EINVAL,
6130 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6131 : : "actiona and mask configuration must be set");
6132 : 0 : action_conf = action->conf;
6133 : 0 : mask_conf = mask->conf;
6134 [ # # # # : 0 : if (!mask_conf || mask_conf->port_id != MLX5_REPRESENTED_PORT_ESW_MGR ||
# # ]
6135 [ # # ]: 0 : !action_conf || action_conf->port_id != MLX5_REPRESENTED_PORT_ESW_MGR)
6136 : 0 : return rte_flow_error_set(error, EINVAL,
6137 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6138 : : "only eswitch manager port 0xffff is"
6139 : : " supported");
6140 : : return 0;
6141 : : }
6142 : :
6143 : : static int
6144 : 0 : flow_hw_validate_target_port_id(struct rte_eth_dev *dev,
6145 : : uint16_t target_port_id)
6146 : : {
6147 : : struct mlx5_priv *port_priv;
6148 : : struct mlx5_priv *dev_priv;
6149 : :
6150 [ # # ]: 0 : if (target_port_id == MLX5_REPRESENTED_PORT_ESW_MGR)
6151 : : return 0;
6152 : :
6153 : 0 : port_priv = mlx5_port_to_eswitch_info(target_port_id, false);
6154 [ # # ]: 0 : if (!port_priv) {
6155 : 0 : rte_errno = EINVAL;
6156 : 0 : DRV_LOG(ERR, "Port %u Failed to obtain E-Switch info for port %u",
6157 : : dev->data->port_id, target_port_id);
6158 : 0 : return -rte_errno;
6159 : : }
6160 : :
6161 : 0 : dev_priv = mlx5_dev_to_eswitch_info(dev);
6162 [ # # ]: 0 : if (!dev_priv) {
6163 : 0 : rte_errno = EINVAL;
6164 : 0 : DRV_LOG(ERR, "Port %u Failed to obtain E-Switch info for transfer proxy",
6165 : : dev->data->port_id);
6166 : 0 : return -rte_errno;
6167 : : }
6168 : :
6169 [ # # ]: 0 : if (port_priv->domain_id != dev_priv->domain_id) {
6170 : 0 : rte_errno = EINVAL;
6171 : 0 : DRV_LOG(ERR, "Port %u Failed to obtain E-Switch info for transfer proxy",
6172 : : dev->data->port_id);
6173 : 0 : return -rte_errno;
6174 : : }
6175 : :
6176 : : return 0;
6177 : : }
6178 : :
6179 : : static int
6180 : 0 : flow_hw_validate_action_represented_port(struct rte_eth_dev *dev,
6181 : : const struct rte_flow_action *action,
6182 : : const struct rte_flow_action *mask,
6183 : : struct rte_flow_error *error)
6184 : : {
6185 : 0 : const struct rte_flow_action_ethdev *action_conf = action->conf;
6186 : 0 : const struct rte_flow_action_ethdev *mask_conf = mask->conf;
6187 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6188 : :
6189 [ # # ]: 0 : if (!priv->sh->config.dv_esw_en)
6190 : 0 : return rte_flow_error_set(error, EINVAL,
6191 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6192 : : "cannot use represented_port actions"
6193 : : " without an E-Switch");
6194 [ # # # # ]: 0 : if (mask_conf && mask_conf->port_id) {
6195 [ # # ]: 0 : if (!action_conf)
6196 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
6197 : : action, "port index was not provided");
6198 : :
6199 [ # # ]: 0 : if (flow_hw_validate_target_port_id(dev, action_conf->port_id))
6200 : 0 : return rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
6201 : : action, "port index is invalid");
6202 : : }
6203 : : return 0;
6204 : : }
6205 : :
6206 : : /**
6207 : : * Validate AGE action.
6208 : : *
6209 : : * @param[in] dev
6210 : : * Pointer to rte_eth_dev structure.
6211 : : * @param[in] action
6212 : : * Pointer to the indirect action.
6213 : : * @param[in] action_flags
6214 : : * Holds the actions detected until now.
6215 : : * @param[in] fixed_cnt
6216 : : * Indicator if this list has a fixed COUNT action.
6217 : : * @param[out] error
6218 : : * Pointer to error structure.
6219 : : *
6220 : : * @return
6221 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
6222 : : */
6223 : : static int
6224 : 0 : flow_hw_validate_action_age(struct rte_eth_dev *dev,
6225 : : const struct rte_flow_action *action,
6226 : : uint64_t action_flags, bool fixed_cnt,
6227 : : struct rte_flow_error *error)
6228 : : {
6229 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6230 : 0 : struct mlx5_age_info *age_info = GET_PORT_AGE_INFO(priv);
6231 : :
6232 [ # # ]: 0 : if (!priv->sh->cdev->config.devx)
6233 : 0 : return rte_flow_error_set(error, ENOTSUP,
6234 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6235 : : NULL, "AGE action not supported");
6236 [ # # ]: 0 : if (age_info->ages_ipool == NULL)
6237 : 0 : return rte_flow_error_set(error, EINVAL,
6238 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6239 : : "aging pool not initialized");
6240 [ # # ]: 0 : if ((action_flags & MLX5_FLOW_ACTION_AGE) ||
6241 : : (action_flags & MLX5_FLOW_ACTION_INDIRECT_AGE))
6242 : 0 : return rte_flow_error_set(error, EINVAL,
6243 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6244 : : "duplicate AGE actions set");
6245 [ # # ]: 0 : if (fixed_cnt)
6246 : 0 : return rte_flow_error_set(error, EINVAL,
6247 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6248 : : "AGE and fixed COUNT combination is not supported");
6249 : : return 0;
6250 : : }
6251 : :
6252 : : /**
6253 : : * Validate count action.
6254 : : *
6255 : : * @param[in] dev
6256 : : * Pointer to rte_eth_dev structure.
6257 : : * @param[in] action
6258 : : * Pointer to the indirect action.
6259 : : * @param[in] mask
6260 : : * Pointer to the indirect action mask.
6261 : : * @param[in] action_flags
6262 : : * Holds the actions detected until now.
6263 : : * @param[out] error
6264 : : * Pointer to error structure.
6265 : : *
6266 : : * @return
6267 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
6268 : : */
6269 : : static int
6270 : 0 : flow_hw_validate_action_count(struct rte_eth_dev *dev,
6271 : : const struct rte_flow_action *action,
6272 : : const struct rte_flow_action *mask,
6273 : : uint64_t action_flags,
6274 : : struct rte_flow_error *error)
6275 : : {
6276 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6277 : 0 : const struct rte_flow_action_count *count = mask->conf;
6278 : :
6279 [ # # ]: 0 : if (!priv->sh->cdev->config.devx)
6280 : 0 : return rte_flow_error_set(error, ENOTSUP,
6281 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6282 : : "count action not supported");
6283 [ # # ]: 0 : if (!priv->hws_cpool)
6284 : 0 : return rte_flow_error_set(error, EINVAL,
6285 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6286 : : "counters pool not initialized");
6287 [ # # ]: 0 : if ((action_flags & MLX5_FLOW_ACTION_COUNT) ||
6288 : : (action_flags & MLX5_FLOW_ACTION_INDIRECT_COUNT))
6289 : 0 : return rte_flow_error_set(error, EINVAL,
6290 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6291 : : "duplicate count actions set");
6292 [ # # # # : 0 : if (count && count->id && (action_flags & MLX5_FLOW_ACTION_AGE))
# # ]
6293 : 0 : return rte_flow_error_set(error, EINVAL,
6294 : : RTE_FLOW_ERROR_TYPE_ACTION, mask,
6295 : : "AGE and COUNT action shared by mask combination is not supported");
6296 : : return 0;
6297 : : }
6298 : :
6299 : : /**
6300 : : * Validate meter_mark action.
6301 : : *
6302 : : * @param[in] dev
6303 : : * Pointer to rte_eth_dev structure.
6304 : : * @param[in] action
6305 : : * Pointer to the indirect action.
6306 : : * @param[in] indirect
6307 : : * If true, then provided action was passed using an indirect action.
6308 : : * @param[out] error
6309 : : * Pointer to error structure.
6310 : : *
6311 : : * @return
6312 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
6313 : : */
6314 : : static int
6315 : 0 : flow_hw_validate_action_meter_mark(struct rte_eth_dev *dev,
6316 : : const struct rte_flow_action *action,
6317 : : bool indirect,
6318 : : struct rte_flow_error *error)
6319 : : {
6320 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6321 : :
6322 : : RTE_SET_USED(action);
6323 : :
6324 [ # # ]: 0 : if (!priv->sh->cdev->config.devx)
6325 : 0 : return rte_flow_error_set(error, ENOTSUP,
6326 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6327 : : "meter_mark action not supported");
6328 [ # # # # ]: 0 : if (!indirect && priv->shared_host)
6329 : 0 : return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, action,
6330 : : "meter_mark action can only be used on host port");
6331 [ # # ]: 0 : if (!priv->hws_mpool)
6332 : 0 : return rte_flow_error_set(error, EINVAL,
6333 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6334 : : "meter_mark pool not initialized");
6335 : : return 0;
6336 : : }
6337 : :
6338 : : /**
6339 : : * Validate indirect action.
6340 : : *
6341 : : * @param[in] dev
6342 : : * Pointer to rte_eth_dev structure.
6343 : : * @param[in] action
6344 : : * Pointer to the indirect action.
6345 : : * @param[in] mask
6346 : : * Pointer to the indirect action mask.
6347 : : * @param[in, out] action_flags
6348 : : * Holds the actions detected until now.
6349 : : * @param[in, out] fixed_cnt
6350 : : * Pointer to indicator if this list has a fixed COUNT action.
6351 : : * @param[out] error
6352 : : * Pointer to error structure.
6353 : : *
6354 : : * @return
6355 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
6356 : : */
6357 : : static int
6358 : 0 : flow_hw_validate_action_indirect(struct rte_eth_dev *dev,
6359 : : const struct rte_flow_action *action,
6360 : : const struct rte_flow_action *mask,
6361 : : uint64_t *action_flags, bool *fixed_cnt,
6362 : : struct rte_flow_error *error)
6363 : : {
6364 : : uint32_t type;
6365 : : int ret;
6366 : :
6367 [ # # ]: 0 : if (!mask)
6368 : 0 : return rte_flow_error_set(error, EINVAL,
6369 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6370 : : "Unable to determine indirect action type without a mask specified");
6371 : 0 : type = mask->type;
6372 [ # # # # : 0 : switch (type) {
# # # ]
6373 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
6374 : 0 : ret = flow_hw_validate_action_meter_mark(dev, mask, true, error);
6375 [ # # ]: 0 : if (ret < 0)
6376 : : return ret;
6377 : 0 : *action_flags |= MLX5_FLOW_ACTION_METER;
6378 : 0 : break;
6379 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
6380 : : /* TODO: Validation logic (same as flow_hw_actions_validate) */
6381 : 0 : *action_flags |= MLX5_FLOW_ACTION_RSS;
6382 : 0 : break;
6383 : 0 : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
6384 : : /* TODO: Validation logic (same as flow_hw_actions_validate) */
6385 : 0 : *action_flags |= MLX5_FLOW_ACTION_CT;
6386 : 0 : break;
6387 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
6388 [ # # # # ]: 0 : if (action->conf && mask->conf) {
6389 [ # # ]: 0 : if ((*action_flags & MLX5_FLOW_ACTION_AGE) ||
6390 : : (*action_flags & MLX5_FLOW_ACTION_INDIRECT_AGE))
6391 : : /*
6392 : : * AGE cannot use indirect counter which is
6393 : : * shared with enother flow rules.
6394 : : */
6395 : 0 : return rte_flow_error_set(error, EINVAL,
6396 : : RTE_FLOW_ERROR_TYPE_ACTION,
6397 : : NULL,
6398 : : "AGE and fixed COUNT combination is not supported");
6399 : 0 : *fixed_cnt = true;
6400 : : }
6401 : 0 : ret = flow_hw_validate_action_count(dev, action, mask,
6402 : : *action_flags, error);
6403 [ # # ]: 0 : if (ret < 0)
6404 : : return ret;
6405 : 0 : *action_flags |= MLX5_FLOW_ACTION_INDIRECT_COUNT;
6406 : 0 : break;
6407 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
6408 : 0 : ret = flow_hw_validate_action_age(dev, action, *action_flags,
6409 : 0 : *fixed_cnt, error);
6410 [ # # ]: 0 : if (ret < 0)
6411 : : return ret;
6412 : 0 : *action_flags |= MLX5_FLOW_ACTION_INDIRECT_AGE;
6413 : 0 : break;
6414 : 0 : case RTE_FLOW_ACTION_TYPE_QUOTA:
6415 : : /* TODO: add proper quota verification */
6416 : 0 : *action_flags |= MLX5_FLOW_ACTION_QUOTA;
6417 : 0 : break;
6418 : 0 : default:
6419 : 0 : DRV_LOG(WARNING, "Unsupported shared action type: %d", type);
6420 : 0 : return rte_flow_error_set(error, ENOTSUP,
6421 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, mask,
6422 : : "Unsupported indirect action type");
6423 : : }
6424 : : return 0;
6425 : : }
6426 : :
6427 : : /**
6428 : : * Validate ipv6_ext_push action.
6429 : : *
6430 : : * @param[in] dev
6431 : : * Pointer to rte_eth_dev structure.
6432 : : * @param[in] action
6433 : : * Pointer to the indirect action.
6434 : : * @param[out] error
6435 : : * Pointer to error structure.
6436 : : *
6437 : : * @return
6438 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
6439 : : */
6440 : : static int
6441 : 0 : flow_hw_validate_action_ipv6_ext_push(struct rte_eth_dev *dev __rte_unused,
6442 : : const struct rte_flow_action *action,
6443 : : struct rte_flow_error *error)
6444 : : {
6445 : 0 : const struct rte_flow_action_ipv6_ext_push *raw_push_data = action->conf;
6446 : :
6447 [ # # # # : 0 : if (!raw_push_data || !raw_push_data->size || !raw_push_data->data)
# # ]
6448 : 0 : return rte_flow_error_set(error, EINVAL,
6449 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6450 : : "invalid ipv6_ext_push data");
6451 [ # # # # ]: 0 : if (raw_push_data->type != IPPROTO_ROUTING ||
6452 : : raw_push_data->size > MLX5_PUSH_MAX_LEN)
6453 : 0 : return rte_flow_error_set(error, EINVAL,
6454 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6455 : : "Unsupported ipv6_ext_push type or length");
6456 : : return 0;
6457 : : }
6458 : :
6459 : : /**
6460 : : * Process `... / raw_decap / raw_encap / ...` actions sequence.
6461 : : * The PMD handles the sequence as a single encap or decap reformat action,
6462 : : * depending on the raw_encap configuration.
6463 : : *
6464 : : * The function assumes that the raw_decap / raw_encap location
6465 : : * in actions template list complies with relative HWS actions order:
6466 : : * for the required reformat configuration:
6467 : : * ENCAP configuration must appear before [JUMP|DROP|PORT]
6468 : : * DECAP configuration must appear at the template head.
6469 : : */
6470 : : static uint64_t
6471 : : mlx5_decap_encap_reformat_type(const struct rte_flow_action *actions,
6472 : : uint32_t encap_ind, uint64_t flags)
6473 : : {
6474 : 0 : const struct rte_flow_action_raw_encap *encap = actions[encap_ind].conf;
6475 : :
6476 [ # # ]: 0 : if ((flags & MLX5_FLOW_ACTION_DECAP) == 0)
6477 : : return MLX5_FLOW_ACTION_ENCAP;
6478 [ # # ]: 0 : if (actions[encap_ind - 1].type != RTE_FLOW_ACTION_TYPE_RAW_DECAP)
6479 : : return MLX5_FLOW_ACTION_ENCAP;
6480 : 0 : return encap->size >= MLX5_ENCAPSULATION_DECISION_SIZE ?
6481 [ # # ]: 0 : MLX5_FLOW_ACTION_ENCAP : MLX5_FLOW_ACTION_DECAP;
6482 : : }
6483 : :
6484 : : enum mlx5_hw_indirect_list_relative_position {
6485 : : MLX5_INDIRECT_LIST_POSITION_UNKNOWN = -1,
6486 : : MLX5_INDIRECT_LIST_POSITION_BEFORE_MH = 0,
6487 : : MLX5_INDIRECT_LIST_POSITION_AFTER_MH,
6488 : : };
6489 : :
6490 : : static enum mlx5_hw_indirect_list_relative_position
6491 : 0 : mlx5_hw_indirect_list_mh_position(const struct rte_flow_action *action)
6492 : : {
6493 : 0 : const struct rte_flow_action_indirect_list *conf = action->conf;
6494 [ # # # # ]: 0 : enum mlx5_indirect_list_type list_type = mlx5_get_indirect_list_type(conf->handle);
6495 : : enum mlx5_hw_indirect_list_relative_position pos = MLX5_INDIRECT_LIST_POSITION_UNKNOWN;
6496 : : const union {
6497 : : struct mlx5_indlst_legacy *legacy;
6498 : : struct mlx5_hw_encap_decap_action *reformat;
6499 : : struct rte_flow_action_list_handle *handle;
6500 : : } h = { .handle = conf->handle};
6501 : :
6502 [ # # # # ]: 0 : switch (list_type) {
6503 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY:
6504 [ # # # ]: 0 : switch (h.legacy->legacy_type) {
6505 : : case RTE_FLOW_ACTION_TYPE_AGE:
6506 : : case RTE_FLOW_ACTION_TYPE_COUNT:
6507 : : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
6508 : : case RTE_FLOW_ACTION_TYPE_METER_MARK:
6509 : : case RTE_FLOW_ACTION_TYPE_QUOTA:
6510 : : pos = MLX5_INDIRECT_LIST_POSITION_BEFORE_MH;
6511 : : break;
6512 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
6513 : : pos = MLX5_INDIRECT_LIST_POSITION_AFTER_MH;
6514 : 0 : break;
6515 : 0 : default:
6516 : : pos = MLX5_INDIRECT_LIST_POSITION_UNKNOWN;
6517 : 0 : break;
6518 : : }
6519 : : break;
6520 : : case MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR:
6521 : : pos = MLX5_INDIRECT_LIST_POSITION_AFTER_MH;
6522 : : break;
6523 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT:
6524 [ # # # ]: 0 : switch (h.reformat->action_type) {
6525 : : case MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2:
6526 : : case MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2:
6527 : : pos = MLX5_INDIRECT_LIST_POSITION_BEFORE_MH;
6528 : : break;
6529 : 0 : case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2:
6530 : : case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3:
6531 : : pos = MLX5_INDIRECT_LIST_POSITION_AFTER_MH;
6532 : 0 : break;
6533 : 0 : default:
6534 : : pos = MLX5_INDIRECT_LIST_POSITION_UNKNOWN;
6535 : 0 : break;
6536 : : }
6537 : : break;
6538 : 0 : default:
6539 : : pos = MLX5_INDIRECT_LIST_POSITION_UNKNOWN;
6540 : 0 : break;
6541 : : }
6542 : 0 : return pos;
6543 : : }
6544 : :
6545 : : #define MLX5_HW_EXPAND_MH_FAILED 0xffff
6546 : :
6547 : : static inline uint16_t
6548 : 0 : flow_hw_template_expand_modify_field(struct rte_flow_action actions[],
6549 : : struct rte_flow_action masks[],
6550 : : const struct rte_flow_action *mf_actions,
6551 : : const struct rte_flow_action *mf_masks,
6552 : : uint64_t flags, uint32_t act_num,
6553 : : uint32_t mf_num)
6554 : : {
6555 : : uint32_t i, tail;
6556 : :
6557 : : MLX5_ASSERT(actions && masks);
6558 : : MLX5_ASSERT(mf_num > 0);
6559 [ # # ]: 0 : if (flags & MLX5_FLOW_ACTION_MODIFY_FIELD) {
6560 : : /*
6561 : : * Application action template already has Modify Field.
6562 : : * It's location will be used in DR.
6563 : : * Expanded MF action can be added before the END.
6564 : : */
6565 : 0 : i = act_num - 1;
6566 : 0 : goto insert;
6567 : : }
6568 : : /**
6569 : : * Locate the first action positioned BEFORE the new MF.
6570 : : *
6571 : : * Search for a place to insert modify header
6572 : : * from the END action backwards:
6573 : : * 1. END is always present in actions array
6574 : : * 2. END location is always at action[act_num - 1]
6575 : : * 3. END always positioned AFTER modify field location
6576 : : *
6577 : : * Relative actions order is the same for RX, TX and FDB.
6578 : : *
6579 : : * Current actions order (draft-3)
6580 : : * @see action_order_arr[]
6581 : : */
6582 [ # # ]: 0 : for (i = act_num - 2; (int)i >= 0; i--) {
6583 : : enum mlx5_hw_indirect_list_relative_position pos;
6584 : 0 : enum rte_flow_action_type type = actions[i].type;
6585 : : uint64_t reformat_type;
6586 : :
6587 [ # # ]: 0 : if (type == RTE_FLOW_ACTION_TYPE_INDIRECT)
6588 : 0 : type = masks[i].type;
6589 [ # # # # ]: 0 : switch (type) {
6590 : : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
6591 : : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
6592 : : case RTE_FLOW_ACTION_TYPE_DROP:
6593 : : case RTE_FLOW_ACTION_TYPE_SEND_TO_KERNEL:
6594 : : case RTE_FLOW_ACTION_TYPE_JUMP:
6595 : : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
6596 : : case RTE_FLOW_ACTION_TYPE_QUEUE:
6597 : : case RTE_FLOW_ACTION_TYPE_RSS:
6598 : : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
6599 : : case RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:
6600 : : case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
6601 : : case RTE_FLOW_ACTION_TYPE_VOID:
6602 : : case RTE_FLOW_ACTION_TYPE_END:
6603 : : break;
6604 : : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
6605 : : reformat_type =
6606 : : mlx5_decap_encap_reformat_type(actions, i,
6607 : : flags);
6608 : : if (reformat_type == MLX5_FLOW_ACTION_DECAP) {
6609 : 0 : i++;
6610 : 0 : goto insert;
6611 : : }
6612 [ # # ]: 0 : if (actions[i - 1].type == RTE_FLOW_ACTION_TYPE_RAW_DECAP)
6613 : : i--;
6614 : : break;
6615 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT_LIST:
6616 : 0 : pos = mlx5_hw_indirect_list_mh_position(&actions[i]);
6617 [ # # ]: 0 : if (pos == MLX5_INDIRECT_LIST_POSITION_UNKNOWN)
6618 : : return MLX5_HW_EXPAND_MH_FAILED;
6619 [ # # ]: 0 : if (pos == MLX5_INDIRECT_LIST_POSITION_BEFORE_MH)
6620 : 0 : goto insert;
6621 : : break;
6622 : 0 : default:
6623 : 0 : i++; /* new MF inserted AFTER actions[i] */
6624 : 0 : goto insert;
6625 : : }
6626 : : }
6627 : : i = 0;
6628 : 0 : insert:
6629 : 0 : tail = act_num - i; /* num action to move */
6630 : 0 : memmove(actions + i + mf_num, actions + i, sizeof(actions[0]) * tail);
6631 : 0 : memcpy(actions + i, mf_actions, sizeof(actions[0]) * mf_num);
6632 : 0 : memmove(masks + i + mf_num, masks + i, sizeof(masks[0]) * tail);
6633 : : memcpy(masks + i, mf_masks, sizeof(masks[0]) * mf_num);
6634 : 0 : return i;
6635 : : }
6636 : :
6637 : : static int
6638 : 0 : flow_hw_validate_action_push_vlan(struct rte_eth_dev *dev,
6639 : : const
6640 : : struct rte_flow_actions_template_attr *attr,
6641 : : const struct rte_flow_action *action,
6642 : : const struct rte_flow_action *mask,
6643 : : struct rte_flow_error *error)
6644 : : {
6645 : : #define X_FIELD(ptr, t, f) (((ptr)->conf) && ((t *)((ptr)->conf))->f)
6646 : :
6647 : 0 : const bool masked_push =
6648 [ # # # # ]: 0 : X_FIELD(mask + MLX5_HW_VLAN_PUSH_TYPE_IDX,
6649 : : const struct rte_flow_action_of_push_vlan, ethertype);
6650 : : bool masked_param;
6651 : :
6652 : : /*
6653 : : * Mandatory actions order:
6654 : : * OF_PUSH_VLAN / OF_SET_VLAN_VID [ / OF_SET_VLAN_PCP ]
6655 : : */
6656 : : RTE_SET_USED(dev);
6657 : : RTE_SET_USED(attr);
6658 : : /* Check that mark matches OF_PUSH_VLAN */
6659 [ # # ]: 0 : if (mask[MLX5_HW_VLAN_PUSH_TYPE_IDX].type !=
6660 : : RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN)
6661 : 0 : return rte_flow_error_set(error, EINVAL,
6662 : : RTE_FLOW_ERROR_TYPE_ACTION,
6663 : : action, "OF_PUSH_VLAN: mask does not match");
6664 : : /* Check that the second template and mask items are SET_VLAN_VID */
6665 [ # # ]: 0 : if (action[MLX5_HW_VLAN_PUSH_VID_IDX].type !=
6666 : 0 : RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID ||
6667 [ # # ]: 0 : mask[MLX5_HW_VLAN_PUSH_VID_IDX].type !=
6668 : : RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)
6669 : 0 : return rte_flow_error_set(error, EINVAL,
6670 : : RTE_FLOW_ERROR_TYPE_ACTION,
6671 : : action, "OF_PUSH_VLAN: invalid actions order");
6672 [ # # # # ]: 0 : masked_param = X_FIELD(mask + MLX5_HW_VLAN_PUSH_VID_IDX,
6673 : : const struct rte_flow_action_of_set_vlan_vid,
6674 : : vlan_vid);
6675 : : /*
6676 : : * PMD requires OF_SET_VLAN_VID mask to must match OF_PUSH_VLAN
6677 : : */
6678 [ # # ]: 0 : if (masked_push ^ masked_param)
6679 : 0 : return rte_flow_error_set(error, EINVAL,
6680 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6681 : : "OF_SET_VLAN_VID: mask does not match OF_PUSH_VLAN");
6682 [ # # ]: 0 : if (is_of_vlan_pcp_present(action)) {
6683 [ # # ]: 0 : if (mask[MLX5_HW_VLAN_PUSH_PCP_IDX].type !=
6684 : : RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)
6685 : 0 : return rte_flow_error_set(error, EINVAL,
6686 : : RTE_FLOW_ERROR_TYPE_ACTION,
6687 : : action, "OF_SET_VLAN_PCP: missing mask configuration");
6688 [ # # # # ]: 0 : masked_param = X_FIELD(mask + MLX5_HW_VLAN_PUSH_PCP_IDX,
6689 : : const struct
6690 : : rte_flow_action_of_set_vlan_pcp,
6691 : : vlan_pcp);
6692 : : /*
6693 : : * PMD requires OF_SET_VLAN_PCP mask to must match OF_PUSH_VLAN
6694 : : */
6695 [ # # ]: 0 : if (masked_push ^ masked_param)
6696 : 0 : return rte_flow_error_set(error, EINVAL,
6697 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6698 : : "OF_SET_VLAN_PCP: mask does not match OF_PUSH_VLAN");
6699 : : }
6700 : : return 0;
6701 : : #undef X_FIELD
6702 : : }
6703 : :
6704 : : static int
6705 : 0 : flow_hw_validate_action_default_miss(struct rte_eth_dev *dev,
6706 : : const struct rte_flow_actions_template_attr *attr,
6707 : : uint64_t action_flags,
6708 : : struct rte_flow_error *error)
6709 : : {
6710 : : /*
6711 : : * The private DEFAULT_MISS action is used internally for LACP in control
6712 : : * flows. So this validation can be ignored. It can be kept right now since
6713 : : * the validation will be done only once.
6714 : : */
6715 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6716 : :
6717 [ # # ]: 0 : if (!attr->ingress || attr->egress || attr->transfer)
6718 : 0 : return rte_flow_error_set(error, EINVAL,
6719 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6720 : : "DEFAULT MISS is only supported in ingress.");
6721 [ # # ]: 0 : if (!priv->hw_def_miss)
6722 : 0 : return rte_flow_error_set(error, EINVAL,
6723 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6724 : : "DEFAULT MISS action does not exist.");
6725 [ # # ]: 0 : if (action_flags & MLX5_FLOW_FATE_ACTIONS)
6726 : 0 : return rte_flow_error_set(error, EINVAL,
6727 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6728 : : "DEFAULT MISS should be the only termination.");
6729 : : return 0;
6730 : : }
6731 : :
6732 : : static int
6733 : 0 : flow_hw_validate_action_nat64(struct rte_eth_dev *dev,
6734 : : const struct rte_flow_actions_template_attr *attr,
6735 : : const struct rte_flow_action *action,
6736 : : const struct rte_flow_action *mask,
6737 : : uint64_t action_flags,
6738 : : struct rte_flow_error *error)
6739 : : {
6740 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6741 : : const struct rte_flow_action_nat64 *nat64_c;
6742 : : enum rte_flow_nat64_type cov_type;
6743 : :
6744 : : RTE_SET_USED(action_flags);
6745 [ # # # # ]: 0 : if (mask->conf && ((const struct rte_flow_action_nat64 *)mask->conf)->type) {
6746 : 0 : nat64_c = (const struct rte_flow_action_nat64 *)action->conf;
6747 : 0 : cov_type = nat64_c->type;
6748 [ # # # # ]: 0 : if ((attr->ingress && !priv->action_nat64[MLX5DR_TABLE_TYPE_NIC_RX][cov_type]) ||
6749 [ # # # # ]: 0 : (attr->egress && !priv->action_nat64[MLX5DR_TABLE_TYPE_NIC_TX][cov_type]))
6750 : 0 : goto err_out;
6751 [ # # ]: 0 : if (attr->transfer) {
6752 [ # # ]: 0 : if (!is_unified_fdb(priv)) {
6753 [ # # ]: 0 : if (!priv->action_nat64[MLX5DR_TABLE_TYPE_FDB][cov_type])
6754 : 0 : goto err_out;
6755 : : } else {
6756 [ # # ]: 0 : if (!priv->action_nat64[MLX5DR_TABLE_TYPE_FDB_RX][cov_type] ||
6757 [ # # ]: 0 : !priv->action_nat64[MLX5DR_TABLE_TYPE_FDB_TX][cov_type] ||
6758 [ # # ]: 0 : !priv->action_nat64[MLX5DR_TABLE_TYPE_FDB_UNIFIED][cov_type])
6759 : 0 : goto err_out;
6760 : : }
6761 : : }
6762 : : } else {
6763 : : /*
6764 : : * Usually, the actions will be used on both directions. For non-masked actions,
6765 : : * both directions' actions will be checked.
6766 : : */
6767 [ # # ]: 0 : if (attr->ingress)
6768 [ # # ]: 0 : if (!priv->action_nat64[MLX5DR_TABLE_TYPE_NIC_RX][RTE_FLOW_NAT64_6TO4] ||
6769 [ # # ]: 0 : !priv->action_nat64[MLX5DR_TABLE_TYPE_NIC_RX][RTE_FLOW_NAT64_4TO6])
6770 : 0 : goto err_out;
6771 [ # # ]: 0 : if (attr->egress)
6772 [ # # ]: 0 : if (!priv->action_nat64[MLX5DR_TABLE_TYPE_NIC_TX][RTE_FLOW_NAT64_6TO4] ||
6773 [ # # ]: 0 : !priv->action_nat64[MLX5DR_TABLE_TYPE_NIC_TX][RTE_FLOW_NAT64_4TO6])
6774 : 0 : goto err_out;
6775 [ # # ]: 0 : if (attr->transfer) {
6776 [ # # ]: 0 : if (!is_unified_fdb(priv)) {
6777 : 0 : if (!priv->action_nat64[MLX5DR_TABLE_TYPE_FDB]
6778 [ # # ]: 0 : [RTE_FLOW_NAT64_6TO4] ||
6779 : : !priv->action_nat64[MLX5DR_TABLE_TYPE_FDB]
6780 [ # # ]: 0 : [RTE_FLOW_NAT64_4TO6])
6781 : 0 : goto err_out;
6782 : : } else {
6783 : 0 : if (!priv->action_nat64[MLX5DR_TABLE_TYPE_FDB_RX]
6784 [ # # ]: 0 : [RTE_FLOW_NAT64_6TO4] ||
6785 : : !priv->action_nat64[MLX5DR_TABLE_TYPE_FDB_RX]
6786 [ # # ]: 0 : [RTE_FLOW_NAT64_4TO6] ||
6787 : : !priv->action_nat64[MLX5DR_TABLE_TYPE_FDB_TX]
6788 [ # # ]: 0 : [RTE_FLOW_NAT64_6TO4] ||
6789 : : !priv->action_nat64[MLX5DR_TABLE_TYPE_FDB_TX]
6790 [ # # ]: 0 : [RTE_FLOW_NAT64_4TO6] ||
6791 : : !priv->action_nat64[MLX5DR_TABLE_TYPE_FDB_UNIFIED]
6792 [ # # ]: 0 : [RTE_FLOW_NAT64_6TO4] ||
6793 : : !priv->action_nat64[MLX5DR_TABLE_TYPE_FDB_UNIFIED]
6794 [ # # ]: 0 : [RTE_FLOW_NAT64_4TO6])
6795 : 0 : goto err_out;
6796 : : }
6797 : : }
6798 : : }
6799 : : return 0;
6800 : 0 : err_out:
6801 : 0 : return rte_flow_error_set(error, EOPNOTSUPP, RTE_FLOW_ERROR_TYPE_ACTION,
6802 : : NULL, "NAT64 action is not supported.");
6803 : : }
6804 : :
6805 : : static int
6806 : 0 : flow_hw_validate_action_jump(struct rte_eth_dev *dev,
6807 : : const struct rte_flow_actions_template_attr *attr,
6808 : : const struct rte_flow_action *action,
6809 : : const struct rte_flow_action *mask,
6810 : : struct rte_flow_error *error)
6811 : : {
6812 : 0 : const struct rte_flow_action_jump *m = mask->conf;
6813 : 0 : const struct rte_flow_action_jump *v = action->conf;
6814 : 0 : struct mlx5_flow_template_table_cfg cfg = {
6815 : : .external = true,
6816 : : .attr = {
6817 : : .flow_attr = {
6818 : 0 : .ingress = attr->ingress,
6819 : 0 : .egress = attr->egress,
6820 : 0 : .transfer = attr->transfer,
6821 : : },
6822 : : },
6823 : : };
6824 : 0 : uint32_t t_group = 0;
6825 : :
6826 [ # # # # ]: 0 : if (!m || !m->group)
6827 : : return 0;
6828 [ # # ]: 0 : if (!v)
6829 : 0 : return rte_flow_error_set(error, EINVAL,
6830 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6831 : : "Invalid jump action configuration");
6832 [ # # ]: 0 : if (flow_hw_translate_group(dev, &cfg, v->group, &t_group, error))
6833 : 0 : return -rte_errno;
6834 [ # # ]: 0 : if (t_group == 0)
6835 : 0 : return rte_flow_error_set(error, EINVAL,
6836 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6837 : : "Unsupported action - jump to root table");
6838 : : return 0;
6839 : : }
6840 : :
6841 : : static int
6842 : 0 : mlx5_flow_validate_action_jump_to_table_index(const struct rte_flow_action *action,
6843 : : const struct rte_flow_action *mask,
6844 : : struct rte_flow_error *error)
6845 : : {
6846 : 0 : const struct rte_flow_action_jump_to_table_index *m = mask->conf;
6847 : 0 : const struct rte_flow_action_jump_to_table_index *v = action->conf;
6848 : : struct mlx5dr_action *jump_action;
6849 : : uint32_t t_group = 0;
6850 : :
6851 [ # # # # ]: 0 : if (!m || !m->table)
6852 : : return 0;
6853 [ # # ]: 0 : if (!v)
6854 : 0 : return rte_flow_error_set(error, EINVAL,
6855 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6856 : : "Invalid jump to matcher action configuration");
6857 : 0 : t_group = v->table->grp->group_id;
6858 [ # # ]: 0 : if (t_group == 0)
6859 : 0 : return rte_flow_error_set(error, EINVAL,
6860 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6861 : : "Unsupported action - jump to root table");
6862 [ # # ]: 0 : if (likely(!rte_flow_template_table_resizable(0, &v->table->cfg.attr))) {
6863 : 0 : jump_action = v->table->matcher_info[0].jump;
6864 : : } else {
6865 : : uint32_t selector;
6866 : 0 : rte_rwlock_read_lock(&v->table->matcher_replace_rwlk);
6867 : 0 : selector = v->table->matcher_selector;
6868 : 0 : jump_action = v->table->matcher_info[selector].jump;
6869 : : rte_rwlock_read_unlock(&v->table->matcher_replace_rwlk);
6870 : : }
6871 [ # # ]: 0 : if (jump_action == NULL)
6872 : 0 : return rte_flow_error_set(error, EINVAL,
6873 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6874 : : "Unsupported action - table is not an rule array");
6875 : : return 0;
6876 : : }
6877 : :
6878 : : static int
6879 : 0 : mlx5_hw_validate_action_mark(struct rte_eth_dev *dev,
6880 : : const struct rte_flow_action *template_action,
6881 : : const struct rte_flow_action *template_mask,
6882 : : uint64_t action_flags,
6883 : : const struct rte_flow_actions_template_attr *template_attr,
6884 : : struct rte_flow_error *error)
6885 : : {
6886 : 0 : const struct rte_flow_action_mark *mark_mask = template_mask->conf;
6887 : : const struct rte_flow_action *action =
6888 [ # # # # ]: 0 : mark_mask && mark_mask->id ? template_action :
6889 : 0 : &(const struct rte_flow_action) {
6890 : : .type = RTE_FLOW_ACTION_TYPE_MARK,
6891 : 0 : .conf = &(const struct rte_flow_action_mark) {
6892 : : .id = MLX5_FLOW_MARK_MAX - 1
6893 : : }
6894 : : };
6895 : 0 : const struct rte_flow_attr attr = {
6896 : 0 : .ingress = template_attr->ingress,
6897 : 0 : .egress = template_attr->egress,
6898 : 0 : .transfer = template_attr->transfer
6899 : : };
6900 : :
6901 : 0 : return mlx5_flow_validate_action_mark(dev, action, action_flags,
6902 : : &attr, error);
6903 : : }
6904 : :
6905 : : static int
6906 : 0 : mlx5_hw_validate_action_queue(struct rte_eth_dev *dev,
6907 : : const struct rte_flow_action *template_action,
6908 : : const struct rte_flow_action *template_mask,
6909 : : const struct rte_flow_actions_template_attr *template_attr,
6910 : : uint64_t action_flags,
6911 : : struct rte_flow_error *error)
6912 : : {
6913 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6914 : 0 : const struct rte_flow_action_queue *queue_mask = template_mask->conf;
6915 : 0 : const struct rte_flow_attr attr = {
6916 : 0 : .ingress = template_attr->ingress,
6917 : 0 : .egress = template_attr->egress,
6918 : 0 : .transfer = template_attr->transfer
6919 : : };
6920 [ # # # # ]: 0 : bool masked = queue_mask != NULL && queue_mask->index;
6921 : :
6922 [ # # # # : 0 : if (template_attr->egress || (template_attr->transfer && !priv->jump_fdb_rx_en))
# # ]
6923 : 0 : return rte_flow_error_set(error, EINVAL,
6924 : : RTE_FLOW_ERROR_TYPE_ATTR, NULL,
6925 : : "QUEUE action supported for ingress only");
6926 [ # # ]: 0 : if (masked)
6927 : 0 : return mlx5_flow_validate_action_queue(template_action, action_flags, dev,
6928 : : &attr, error);
6929 : : else
6930 : : return 0;
6931 : : }
6932 : :
6933 : : static int
6934 : 0 : mlx5_hw_validate_action_rss(struct rte_eth_dev *dev,
6935 : : const struct rte_flow_action *template_action,
6936 : : const struct rte_flow_action *template_mask,
6937 : : const struct rte_flow_actions_template_attr *template_attr,
6938 : : __rte_unused uint64_t action_flags,
6939 : : struct rte_flow_error *error)
6940 : : {
6941 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6942 : 0 : const struct rte_flow_action_rss *mask = template_mask->conf;
6943 : :
6944 [ # # # # : 0 : if (template_attr->egress || (template_attr->transfer && !priv->jump_fdb_rx_en))
# # ]
6945 : 0 : return rte_flow_error_set(error, EINVAL,
6946 : : RTE_FLOW_ERROR_TYPE_ATTR, NULL,
6947 : : "RSS action supported for ingress only");
6948 [ # # ]: 0 : if (mask != NULL)
6949 : 0 : return mlx5_validate_action_rss(dev, template_action, error);
6950 : : else
6951 : : return 0;
6952 : : }
6953 : :
6954 : : static int
6955 : 0 : mlx5_hw_validate_action_l2_encap(struct rte_eth_dev *dev,
6956 : : const struct rte_flow_action *template_action,
6957 : : const struct rte_flow_action *template_mask,
6958 : : const struct rte_flow_actions_template_attr *template_attr,
6959 : : uint64_t action_flags,
6960 : : struct rte_flow_error *error)
6961 : : {
6962 : 0 : const struct rte_flow_action_vxlan_encap default_action_conf = {
6963 : : .definition = (struct rte_flow_item *)
6964 : 0 : (struct rte_flow_item [1]) {
6965 : : [0] = { .type = RTE_FLOW_ITEM_TYPE_END }
6966 : : }
6967 : : };
6968 : 0 : const struct rte_flow_action *action = template_mask->conf ?
6969 [ # # ]: 0 : template_action : &(const struct rte_flow_action) {
6970 : 0 : .type = template_mask->type,
6971 : : .conf = &default_action_conf
6972 : : };
6973 : 0 : const struct rte_flow_attr attr = {
6974 : 0 : .ingress = template_attr->ingress,
6975 : 0 : .egress = template_attr->egress,
6976 : 0 : .transfer = template_attr->transfer
6977 : : };
6978 : :
6979 : 0 : return mlx5_flow_dv_validate_action_l2_encap(dev, action_flags, action,
6980 : : &attr, error);
6981 : : }
6982 : :
6983 : : static int
6984 : 0 : mlx5_hw_validate_action_l2_decap(struct rte_eth_dev *dev,
6985 : : const struct rte_flow_action *template_action,
6986 : : const struct rte_flow_action *template_mask,
6987 : : const struct rte_flow_actions_template_attr *template_attr,
6988 : : uint64_t action_flags,
6989 : : struct rte_flow_error *error)
6990 : : {
6991 : 0 : const struct rte_flow_action_vxlan_encap default_action_conf = {
6992 : : .definition = (struct rte_flow_item *)
6993 : 0 : (struct rte_flow_item [1]) {
6994 : : [0] = { .type = RTE_FLOW_ITEM_TYPE_END }
6995 : : }
6996 : : };
6997 : 0 : const struct rte_flow_action *action = template_mask->conf ?
6998 [ # # ]: 0 : template_action : &(const struct rte_flow_action) {
6999 : 0 : .type = template_mask->type,
7000 : : .conf = &default_action_conf
7001 : : };
7002 : 0 : const struct rte_flow_attr attr = {
7003 : 0 : .ingress = template_attr->ingress,
7004 : 0 : .egress = template_attr->egress,
7005 : 0 : .transfer = template_attr->transfer
7006 : : };
7007 : : uint64_t item_flags =
7008 : 0 : action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
7009 [ # # ]: 0 : MLX5_FLOW_LAYER_VXLAN : 0;
7010 : :
7011 : 0 : return mlx5_flow_dv_validate_action_decap(dev, action_flags, action,
7012 : : item_flags, &attr, error);
7013 : : }
7014 : :
7015 : : static int
7016 : : mlx5_hw_validate_action_conntrack(struct rte_eth_dev *dev,
7017 : : const struct rte_flow_action *template_action,
7018 : : const struct rte_flow_action *template_mask,
7019 : : const struct rte_flow_actions_template_attr *template_attr,
7020 : : uint64_t action_flags,
7021 : : struct rte_flow_error *error)
7022 : : {
7023 : : RTE_SET_USED(template_action);
7024 : : RTE_SET_USED(template_mask);
7025 : : RTE_SET_USED(template_attr);
7026 : 0 : return mlx5_flow_dv_validate_action_aso_ct(dev, action_flags,
7027 : : MLX5_FLOW_LAYER_OUTER_L4_TCP,
7028 : : false, error);
7029 : : }
7030 : :
7031 : : static int
7032 : 0 : flow_hw_validate_action_raw_encap(const struct rte_flow_action *action,
7033 : : const struct rte_flow_action *mask,
7034 : : struct rte_flow_error *error)
7035 : : {
7036 : 0 : const struct rte_flow_action_raw_encap *mask_conf = mask->conf;
7037 : 0 : const struct rte_flow_action_raw_encap *action_conf = action->conf;
7038 : :
7039 [ # # # # ]: 0 : if (!mask_conf || !mask_conf->size)
7040 : 0 : return rte_flow_error_set(error, EINVAL,
7041 : : RTE_FLOW_ERROR_TYPE_ACTION, mask,
7042 : : "raw_encap: size must be masked");
7043 [ # # # # ]: 0 : if (!action_conf || !action_conf->size)
7044 : 0 : return rte_flow_error_set(error, EINVAL,
7045 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
7046 : : "raw_encap: invalid action configuration");
7047 [ # # # # ]: 0 : if (mask_conf->data && !action_conf->data)
7048 : 0 : return rte_flow_error_set(error, EINVAL,
7049 : : RTE_FLOW_ERROR_TYPE_ACTION,
7050 : : action, "raw_encap: masked data is missing");
7051 : : return 0;
7052 : : }
7053 : :
7054 : :
7055 : : static int
7056 : 0 : flow_hw_validate_action_raw_reformat(struct rte_eth_dev *dev,
7057 : : const struct rte_flow_action *template_action,
7058 : : const struct rte_flow_action *template_mask,
7059 : : const struct
7060 : : rte_flow_actions_template_attr *template_attr,
7061 : : uint64_t *action_flags,
7062 : : struct rte_flow_error *error)
7063 : : {
7064 : : const struct rte_flow_action *encap_action = NULL;
7065 : : const struct rte_flow_action *encap_mask = NULL;
7066 : : const struct rte_flow_action_raw_decap *raw_decap = NULL;
7067 : : const struct rte_flow_action_raw_encap *raw_encap = NULL;
7068 : 0 : const struct rte_flow_attr attr = {
7069 : 0 : .ingress = template_attr->ingress,
7070 : 0 : .egress = template_attr->egress,
7071 : 0 : .transfer = template_attr->transfer
7072 : : };
7073 : : uint64_t item_flags = 0;
7074 : 0 : int ret, actions_n = 0;
7075 : :
7076 [ # # ]: 0 : if (template_action->type == RTE_FLOW_ACTION_TYPE_RAW_DECAP) {
7077 : 0 : raw_decap = template_mask->conf ?
7078 [ # # ]: 0 : template_action->conf : &empty_decap;
7079 [ # # ]: 0 : if ((template_action + 1)->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7080 [ # # ]: 0 : if ((template_mask + 1)->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP)
7081 : 0 : return rte_flow_error_set(error, EINVAL,
7082 : : RTE_FLOW_ERROR_TYPE_ACTION,
7083 : 0 : template_mask + 1, "invalid mask type");
7084 : 0 : encap_action = template_action + 1;
7085 : 0 : encap_mask = template_mask + 1;
7086 : : }
7087 : : } else {
7088 : : encap_action = template_action;
7089 : : encap_mask = template_mask;
7090 : : }
7091 [ # # ]: 0 : if (encap_action) {
7092 : 0 : raw_encap = encap_action->conf;
7093 : 0 : ret = flow_hw_validate_action_raw_encap(encap_action,
7094 : : encap_mask, error);
7095 [ # # ]: 0 : if (ret)
7096 : : return ret;
7097 : : }
7098 : 0 : return mlx5_flow_dv_validate_action_raw_encap_decap(dev, raw_decap,
7099 : : raw_encap, &attr,
7100 : : action_flags,
7101 : : &actions_n,
7102 : : template_action,
7103 : : item_flags, error);
7104 : : }
7105 : :
7106 : :
7107 : :
7108 : : static int
7109 : 0 : mlx5_flow_hw_actions_validate(struct rte_eth_dev *dev,
7110 : : const struct rte_flow_actions_template_attr *attr,
7111 : : const struct rte_flow_action actions[],
7112 : : const struct rte_flow_action masks[],
7113 : : uint64_t *act_flags,
7114 : : struct rte_flow_error *error)
7115 : : {
7116 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
7117 : : const struct rte_flow_action_count *count_mask = NULL;
7118 : 0 : bool fixed_cnt = false;
7119 : 0 : uint64_t action_flags = 0;
7120 : : bool actions_end = false;
7121 : : uint16_t i;
7122 : : int ret;
7123 : : const struct rte_flow_action_ipv6_ext_remove *remove_data;
7124 : :
7125 [ # # ]: 0 : if (!mlx5_hw_ctx_validate(dev, error))
7126 : 0 : return -rte_errno;
7127 : : /* FDB actions are only valid to proxy port. */
7128 [ # # # # : 0 : if (attr->transfer && (!priv->sh->config.dv_esw_en || !priv->master))
# # ]
7129 : 0 : return rte_flow_error_set(error, EINVAL,
7130 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7131 : : NULL,
7132 : : "transfer actions are only valid to proxy port");
7133 [ # # ]: 0 : for (i = 0; !actions_end; ++i) {
7134 : 0 : const struct rte_flow_action *action = &actions[i];
7135 : 0 : const struct rte_flow_action *mask = &masks[i];
7136 : :
7137 : : MLX5_ASSERT(i < MLX5_HW_MAX_ACTS);
7138 [ # # ]: 0 : if (action->type != RTE_FLOW_ACTION_TYPE_INDIRECT &&
7139 [ # # ]: 0 : action->type != mask->type)
7140 : 0 : return rte_flow_error_set(error, ENOTSUP,
7141 : : RTE_FLOW_ERROR_TYPE_ACTION,
7142 : : action,
7143 : : "mask type does not match action type");
7144 [ # # # # : 0 : switch ((int)action->type) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # ]
7145 : : case RTE_FLOW_ACTION_TYPE_VOID:
7146 : 0 : break;
7147 : : case RTE_FLOW_ACTION_TYPE_INDIRECT_LIST:
7148 : : break;
7149 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT:
7150 : 0 : ret = flow_hw_validate_action_indirect(dev, action,
7151 : : mask,
7152 : : &action_flags,
7153 : : &fixed_cnt,
7154 : : error);
7155 [ # # ]: 0 : if (ret < 0)
7156 : 0 : return ret;
7157 : : break;
7158 : 0 : case RTE_FLOW_ACTION_TYPE_FLAG:
7159 : : /* TODO: Validation logic */
7160 : 0 : action_flags |= MLX5_FLOW_ACTION_FLAG;
7161 : 0 : break;
7162 : 0 : case RTE_FLOW_ACTION_TYPE_MARK:
7163 : 0 : ret = mlx5_hw_validate_action_mark(dev, action, mask,
7164 : : action_flags,
7165 : : attr, error);
7166 [ # # ]: 0 : if (ret)
7167 : 0 : return ret;
7168 : 0 : action_flags |= MLX5_FLOW_ACTION_MARK;
7169 : 0 : break;
7170 : 0 : case RTE_FLOW_ACTION_TYPE_DROP:
7171 : 0 : ret = mlx5_flow_validate_action_drop
7172 : : (dev, action_flags,
7173 : 0 : &(struct rte_flow_attr){.egress = attr->egress},
7174 : : error);
7175 [ # # ]: 0 : if (ret)
7176 : 0 : return ret;
7177 : 0 : action_flags |= MLX5_FLOW_ACTION_DROP;
7178 : 0 : break;
7179 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP:
7180 : : /* Only validate the jump to root table in template stage. */
7181 : 0 : ret = flow_hw_validate_action_jump(dev, attr, action, mask, error);
7182 [ # # ]: 0 : if (ret)
7183 : 0 : return ret;
7184 : 0 : action_flags |= MLX5_FLOW_ACTION_JUMP;
7185 : 0 : break;
7186 : : #ifdef HAVE_MLX5DV_DR_ACTION_CREATE_DEST_ROOT_TABLE
7187 : : case RTE_FLOW_ACTION_TYPE_SEND_TO_KERNEL: {
7188 : : bool res;
7189 : :
7190 : : if (priv->shared_host)
7191 : : return rte_flow_error_set(error, ENOTSUP,
7192 : : RTE_FLOW_ERROR_TYPE_ACTION,
7193 : : action,
7194 : : "action not supported in guest port");
7195 : : if (attr->ingress) {
7196 : : res = priv->hw_send_to_kernel[MLX5DR_TABLE_TYPE_NIC_RX];
7197 : : } else if (attr->egress) {
7198 : : res = priv->hw_send_to_kernel[MLX5DR_TABLE_TYPE_NIC_TX];
7199 : : } else {
7200 : : if (!is_unified_fdb(priv))
7201 : : res = priv->hw_send_to_kernel[MLX5DR_TABLE_TYPE_FDB];
7202 : : else
7203 : : res =
7204 : : priv->hw_send_to_kernel[MLX5DR_TABLE_TYPE_FDB_RX] &&
7205 : : priv->hw_send_to_kernel[MLX5DR_TABLE_TYPE_FDB_TX] &&
7206 : : priv->hw_send_to_kernel[MLX5DR_TABLE_TYPE_FDB_UNIFIED];
7207 : : }
7208 : : if (!res)
7209 : : return rte_flow_error_set(error, ENOTSUP,
7210 : : RTE_FLOW_ERROR_TYPE_ACTION,
7211 : : action,
7212 : : "action is not available");
7213 : :
7214 : : action_flags |= MLX5_FLOW_ACTION_SEND_TO_KERNEL;
7215 : : break;
7216 : : }
7217 : : #endif
7218 : 0 : case RTE_FLOW_ACTION_TYPE_QUEUE:
7219 : 0 : ret = mlx5_hw_validate_action_queue(dev, action, mask,
7220 : : attr, action_flags,
7221 : : error);
7222 [ # # ]: 0 : if (ret)
7223 : 0 : return ret;
7224 : 0 : action_flags |= MLX5_FLOW_ACTION_QUEUE;
7225 : 0 : break;
7226 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
7227 : 0 : ret = mlx5_hw_validate_action_rss(dev, action, mask,
7228 : : attr, action_flags,
7229 : : error);
7230 [ # # ]: 0 : if (ret)
7231 : 0 : return ret;
7232 : 0 : action_flags |= MLX5_FLOW_ACTION_RSS;
7233 : 0 : break;
7234 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7235 : : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7236 : 0 : ret = mlx5_hw_validate_action_l2_encap(dev, action, mask,
7237 : : attr, action_flags,
7238 : : error);
7239 [ # # ]: 0 : if (ret)
7240 : 0 : return ret;
7241 : 0 : action_flags |= MLX5_FLOW_ACTION_ENCAP;
7242 : 0 : break;
7243 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7244 : : case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7245 : 0 : ret = mlx5_hw_validate_action_l2_decap(dev, action, mask,
7246 : : attr, action_flags,
7247 : : error);
7248 [ # # ]: 0 : if (ret)
7249 : 0 : return ret;
7250 : 0 : action_flags |= MLX5_FLOW_ACTION_DECAP;
7251 : 0 : break;
7252 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7253 : : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7254 : 0 : ret = flow_hw_validate_action_raw_reformat(dev, action,
7255 : : mask, attr,
7256 : : &action_flags,
7257 : : error);
7258 [ # # ]: 0 : if (ret)
7259 : 0 : return ret;
7260 [ # # ]: 0 : if (action->type == RTE_FLOW_ACTION_TYPE_RAW_DECAP &&
7261 [ # # ]: 0 : (action + 1)->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7262 : 0 : action_flags |= MLX5_FLOW_XCAP_ACTIONS;
7263 : 0 : i++;
7264 : : }
7265 : : break;
7266 : 0 : case RTE_FLOW_ACTION_TYPE_IPV6_EXT_PUSH:
7267 : 0 : ret = flow_hw_validate_action_ipv6_ext_push(dev, action, error);
7268 [ # # ]: 0 : if (ret < 0)
7269 : 0 : return ret;
7270 : 0 : action_flags |= MLX5_FLOW_ACTION_IPV6_ROUTING_PUSH;
7271 : 0 : break;
7272 : 0 : case RTE_FLOW_ACTION_TYPE_IPV6_EXT_REMOVE:
7273 : 0 : remove_data = action->conf;
7274 : : /* Remove action must be shared. */
7275 [ # # # # ]: 0 : if (remove_data->type != IPPROTO_ROUTING || !mask) {
7276 : 0 : DRV_LOG(ERR, "Only supports shared IPv6 routing remove");
7277 : 0 : return -EINVAL;
7278 : : }
7279 : 0 : action_flags |= MLX5_FLOW_ACTION_IPV6_ROUTING_REMOVE;
7280 : 0 : break;
7281 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
7282 : 0 : ret = flow_hw_validate_action_meter_mark(dev, action, false, error);
7283 [ # # ]: 0 : if (ret < 0)
7284 : 0 : return ret;
7285 : 0 : action_flags |= MLX5_FLOW_ACTION_METER;
7286 : 0 : break;
7287 : 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
7288 : 0 : ret = flow_hw_validate_action_modify_field(dev, action, mask,
7289 : : error);
7290 [ # # ]: 0 : if (ret < 0)
7291 : 0 : return ret;
7292 : 0 : action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
7293 : 0 : break;
7294 : 0 : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
7295 : 0 : ret = flow_hw_validate_action_represented_port
7296 : : (dev, action, mask, error);
7297 [ # # ]: 0 : if (ret < 0)
7298 : 0 : return ret;
7299 : 0 : action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7300 : 0 : break;
7301 : 0 : case RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:
7302 : 0 : ret = flow_hw_validate_action_port_representor
7303 : : (dev, attr, action, mask, error);
7304 [ # # ]: 0 : if (ret < 0)
7305 : 0 : return ret;
7306 : 0 : action_flags |= MLX5_FLOW_ACTION_PORT_REPRESENTOR;
7307 : 0 : break;
7308 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
7309 [ # # # # ]: 0 : if (count_mask && count_mask->id)
7310 : 0 : fixed_cnt = true;
7311 : 0 : ret = flow_hw_validate_action_age(dev, action,
7312 : : action_flags,
7313 : : fixed_cnt, error);
7314 [ # # ]: 0 : if (ret < 0)
7315 : 0 : return ret;
7316 : 0 : action_flags |= MLX5_FLOW_ACTION_AGE;
7317 : 0 : break;
7318 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
7319 : 0 : ret = flow_hw_validate_action_count(dev, action, mask,
7320 : : action_flags,
7321 : : error);
7322 [ # # ]: 0 : if (ret < 0)
7323 : 0 : return ret;
7324 : 0 : count_mask = mask->conf;
7325 : 0 : action_flags |= MLX5_FLOW_ACTION_COUNT;
7326 : 0 : break;
7327 : 0 : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
7328 : 0 : ret = mlx5_hw_validate_action_conntrack(dev, action, mask,
7329 : : attr, action_flags,
7330 : : error);
7331 [ # # ]: 0 : if (ret)
7332 : 0 : return ret;
7333 : 0 : action_flags |= MLX5_FLOW_ACTION_CT;
7334 : 0 : break;
7335 : 0 : case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7336 : 0 : action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7337 : 0 : break;
7338 : 0 : case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7339 : 0 : action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7340 : 0 : break;
7341 : 0 : case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7342 : 0 : ret = flow_hw_validate_action_push_vlan
7343 : : (dev, attr, action, mask, error);
7344 [ # # ]: 0 : if (ret != 0)
7345 : 0 : return ret;
7346 : 0 : i += is_of_vlan_pcp_present(action) ?
7347 [ # # ]: 0 : MLX5_HW_VLAN_PUSH_PCP_IDX :
7348 : : MLX5_HW_VLAN_PUSH_VID_IDX;
7349 : 0 : action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7350 : 0 : break;
7351 : 0 : case RTE_FLOW_ACTION_TYPE_NAT64:
7352 : 0 : ret = flow_hw_validate_action_nat64(dev, attr, action, mask,
7353 : : action_flags, error);
7354 [ # # ]: 0 : if (ret != 0)
7355 : 0 : return ret;
7356 : 0 : action_flags |= MLX5_FLOW_ACTION_NAT64;
7357 : 0 : break;
7358 : 0 : case RTE_FLOW_ACTION_TYPE_END:
7359 : : actions_end = true;
7360 : 0 : break;
7361 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
7362 : 0 : ret = flow_hw_validate_action_default_miss(dev, attr,
7363 : : action_flags, error);
7364 [ # # ]: 0 : if (ret < 0)
7365 : 0 : return ret;
7366 : 0 : action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
7367 : 0 : break;
7368 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
7369 : 0 : ret = mlx5_flow_validate_action_jump_to_table_index(action, mask, error);
7370 [ # # ]: 0 : if (ret < 0)
7371 : 0 : return ret;
7372 : 0 : action_flags |= MLX5_FLOW_ACTION_JUMP_TO_TABLE_INDEX;
7373 : 0 : break;
7374 : 0 : default:
7375 : 0 : return rte_flow_error_set(error, ENOTSUP,
7376 : : RTE_FLOW_ERROR_TYPE_ACTION,
7377 : : action,
7378 : : "action not supported in template API");
7379 : : }
7380 : : }
7381 [ # # ]: 0 : if (act_flags != NULL)
7382 : 0 : *act_flags = action_flags;
7383 : : return 0;
7384 : : }
7385 : :
7386 : : static int
7387 : 0 : flow_hw_actions_validate(struct rte_eth_dev *dev,
7388 : : const struct rte_flow_actions_template_attr *attr,
7389 : : const struct rte_flow_action actions[],
7390 : : const struct rte_flow_action masks[],
7391 : : struct rte_flow_error *error)
7392 : : {
7393 : 0 : return mlx5_flow_hw_actions_validate(dev, attr, actions, masks, NULL, error);
7394 : : }
7395 : :
7396 : :
7397 : : static enum mlx5dr_action_type mlx5_hw_dr_action_types[] = {
7398 : : [RTE_FLOW_ACTION_TYPE_MARK] = MLX5DR_ACTION_TYP_TAG,
7399 : : [RTE_FLOW_ACTION_TYPE_FLAG] = MLX5DR_ACTION_TYP_TAG,
7400 : : [RTE_FLOW_ACTION_TYPE_DROP] = MLX5DR_ACTION_TYP_DROP,
7401 : : [RTE_FLOW_ACTION_TYPE_JUMP] = MLX5DR_ACTION_TYP_TBL,
7402 : : [RTE_FLOW_ACTION_TYPE_QUEUE] = MLX5DR_ACTION_TYP_TIR,
7403 : : [RTE_FLOW_ACTION_TYPE_RSS] = MLX5DR_ACTION_TYP_TIR,
7404 : : [RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP] = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2,
7405 : : [RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP] = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2,
7406 : : [RTE_FLOW_ACTION_TYPE_VXLAN_DECAP] = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2,
7407 : : [RTE_FLOW_ACTION_TYPE_NVGRE_DECAP] = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2,
7408 : : [RTE_FLOW_ACTION_TYPE_MODIFY_FIELD] = MLX5DR_ACTION_TYP_MODIFY_HDR,
7409 : : [RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT] = MLX5DR_ACTION_TYP_VPORT,
7410 : : [RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR] = MLX5DR_ACTION_TYP_MISS,
7411 : : [RTE_FLOW_ACTION_TYPE_CONNTRACK] = MLX5DR_ACTION_TYP_ASO_CT,
7412 : : [RTE_FLOW_ACTION_TYPE_OF_POP_VLAN] = MLX5DR_ACTION_TYP_POP_VLAN,
7413 : : [RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN] = MLX5DR_ACTION_TYP_PUSH_VLAN,
7414 : : [RTE_FLOW_ACTION_TYPE_SEND_TO_KERNEL] = MLX5DR_ACTION_TYP_DEST_ROOT,
7415 : : [RTE_FLOW_ACTION_TYPE_IPV6_EXT_PUSH] = MLX5DR_ACTION_TYP_PUSH_IPV6_ROUTE_EXT,
7416 : : [RTE_FLOW_ACTION_TYPE_IPV6_EXT_REMOVE] = MLX5DR_ACTION_TYP_POP_IPV6_ROUTE_EXT,
7417 : : [RTE_FLOW_ACTION_TYPE_NAT64] = MLX5DR_ACTION_TYP_NAT64,
7418 : : [RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX] = MLX5DR_ACTION_TYP_JUMP_TO_MATCHER,
7419 : : };
7420 : :
7421 : : static inline void
7422 : : action_template_set_type(struct rte_flow_actions_template *at,
7423 : : enum mlx5dr_action_type *action_types,
7424 : : unsigned int action_src, uint16_t *curr_off,
7425 : : enum mlx5dr_action_type type)
7426 : : {
7427 : 0 : at->dr_off[action_src] = *curr_off;
7428 : 0 : action_types[*curr_off] = type;
7429 : 0 : *curr_off = *curr_off + 1;
7430 : 0 : }
7431 : :
7432 : : static int
7433 : 0 : flow_hw_dr_actions_template_handle_shared(int type, uint32_t action_src,
7434 : : enum mlx5dr_action_type *action_types,
7435 : : uint16_t *curr_off, uint16_t *cnt_off,
7436 : : struct rte_flow_actions_template *at)
7437 : : {
7438 [ # # # # : 0 : switch (type) {
# ]
7439 : : case RTE_FLOW_ACTION_TYPE_RSS:
7440 : : action_template_set_type(at, action_types, action_src, curr_off,
7441 : : MLX5DR_ACTION_TYP_TIR);
7442 : : break;
7443 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
7444 : : case RTE_FLOW_ACTION_TYPE_COUNT:
7445 : : /*
7446 : : * Both AGE and COUNT action need counter, the first one fills
7447 : : * the action_types array, and the second only saves the offset.
7448 : : */
7449 [ # # ]: 0 : if (*cnt_off == UINT16_MAX) {
7450 : 0 : *cnt_off = *curr_off;
7451 : : action_template_set_type(at, action_types,
7452 : : action_src, curr_off,
7453 : : MLX5DR_ACTION_TYP_CTR);
7454 : : }
7455 : 0 : at->dr_off[action_src] = *cnt_off;
7456 : 0 : break;
7457 : : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
7458 : : action_template_set_type(at, action_types, action_src, curr_off,
7459 : : MLX5DR_ACTION_TYP_ASO_CT);
7460 : : break;
7461 : : case RTE_FLOW_ACTION_TYPE_QUOTA:
7462 : : case RTE_FLOW_ACTION_TYPE_METER_MARK:
7463 : : action_template_set_type(at, action_types, action_src, curr_off,
7464 : : MLX5DR_ACTION_TYP_ASO_METER);
7465 : : break;
7466 : 0 : default:
7467 : 0 : DRV_LOG(WARNING, "Unsupported shared action type: %d", type);
7468 : 0 : return -EINVAL;
7469 : : }
7470 : : return 0;
7471 : : }
7472 : :
7473 : :
7474 : : static int
7475 : 0 : flow_hw_template_actions_list(struct rte_flow_actions_template *at,
7476 : : unsigned int action_src,
7477 : : enum mlx5dr_action_type *action_types,
7478 : : uint16_t *curr_off, uint16_t *cnt_off)
7479 : : {
7480 : : int ret;
7481 : 0 : const struct rte_flow_action_indirect_list *indlst_conf = at->actions[action_src].conf;
7482 [ # # # # ]: 0 : enum mlx5_indirect_list_type list_type = mlx5_get_indirect_list_type(indlst_conf->handle);
7483 : : const union {
7484 : : struct mlx5_indlst_legacy *legacy;
7485 : : struct rte_flow_action_list_handle *handle;
7486 : : } indlst_obj = { .handle = indlst_conf->handle };
7487 : : enum mlx5dr_action_type type;
7488 : :
7489 [ # # # # ]: 0 : switch (list_type) {
7490 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY:
7491 : 0 : ret = flow_hw_dr_actions_template_handle_shared
7492 : 0 : (indlst_obj.legacy->legacy_type, action_src,
7493 : : action_types, curr_off, cnt_off, at);
7494 [ # # ]: 0 : if (ret)
7495 : 0 : return ret;
7496 : : break;
7497 : : case MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR:
7498 : : action_template_set_type(at, action_types, action_src, curr_off,
7499 : : MLX5DR_ACTION_TYP_DEST_ARRAY);
7500 : : break;
7501 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT:
7502 : 0 : type = ((struct mlx5_hw_encap_decap_action *)
7503 : : (indlst_conf->handle))->action_type;
7504 : : action_template_set_type(at, action_types, action_src, curr_off, type);
7505 : : break;
7506 : 0 : default:
7507 : 0 : DRV_LOG(ERR, "Unsupported indirect list type");
7508 : 0 : return -EINVAL;
7509 : : }
7510 : : return 0;
7511 : : }
7512 : :
7513 : : /**
7514 : : * Create DR action template based on a provided sequence of flow actions.
7515 : : *
7516 : : * @param[in] dev
7517 : : * Pointer to the rte_eth_dev structure.
7518 : : * @param[in] at
7519 : : * Pointer to flow actions template to be updated.
7520 : : * @param[out] action_types
7521 : : * Action types array to be filled.
7522 : : * @param[out] tmpl_flags
7523 : : * Template DR flags to be filled.
7524 : : *
7525 : : * @return
7526 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
7527 : : */
7528 : : static int
7529 : 0 : flow_hw_parse_flow_actions_to_dr_actions(struct rte_eth_dev *dev,
7530 : : struct rte_flow_actions_template *at,
7531 : : enum mlx5dr_action_type action_types[MLX5_HW_MAX_ACTS],
7532 : : uint32_t *tmpl_flags __rte_unused)
7533 : : {
7534 : : unsigned int i;
7535 : : uint16_t curr_off;
7536 : : enum mlx5dr_action_type reformat_act_type = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2;
7537 : : uint16_t reformat_off = UINT16_MAX;
7538 : : uint16_t mhdr_off = UINT16_MAX;
7539 : : uint16_t recom_off = UINT16_MAX;
7540 : 0 : uint16_t cnt_off = UINT16_MAX;
7541 : : enum mlx5dr_action_type recom_type = MLX5DR_ACTION_TYP_LAST;
7542 : : int ret;
7543 : :
7544 [ # # ]: 0 : for (i = 0, curr_off = 0; at->actions[i].type != RTE_FLOW_ACTION_TYPE_END; ++i) {
7545 : : const struct rte_flow_action_raw_encap *raw_encap_data;
7546 : : size_t data_size;
7547 : : enum mlx5dr_action_type type;
7548 : :
7549 [ # # ]: 0 : if (curr_off >= MLX5_HW_MAX_ACTS)
7550 : 0 : goto err_actions_num;
7551 [ # # # # : 0 : switch ((int)at->actions[i].type) {
# # # # #
# # # # #
# # ]
7552 : : case RTE_FLOW_ACTION_TYPE_VOID:
7553 : : break;
7554 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT_LIST:
7555 : 0 : ret = flow_hw_template_actions_list(at, i, action_types,
7556 : : &curr_off, &cnt_off);
7557 [ # # ]: 0 : if (ret)
7558 : 0 : return ret;
7559 : : break;
7560 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT:
7561 : 0 : ret = flow_hw_dr_actions_template_handle_shared
7562 : 0 : (at->masks[i].type, i, action_types,
7563 : : &curr_off, &cnt_off, at);
7564 [ # # ]: 0 : if (ret)
7565 : 0 : return ret;
7566 : : break;
7567 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7568 : : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7569 : : case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7570 : : case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7571 : : MLX5_ASSERT(reformat_off == UINT16_MAX);
7572 : 0 : reformat_off = curr_off++;
7573 : 0 : reformat_act_type = mlx5_hw_dr_action_types[at->actions[i].type];
7574 : 0 : break;
7575 : 0 : case RTE_FLOW_ACTION_TYPE_IPV6_EXT_PUSH:
7576 : : MLX5_ASSERT(recom_off == UINT16_MAX);
7577 : : recom_type = MLX5DR_ACTION_TYP_PUSH_IPV6_ROUTE_EXT;
7578 : 0 : recom_off = curr_off++;
7579 : 0 : break;
7580 : 0 : case RTE_FLOW_ACTION_TYPE_IPV6_EXT_REMOVE:
7581 : : MLX5_ASSERT(recom_off == UINT16_MAX);
7582 : : recom_type = MLX5DR_ACTION_TYP_POP_IPV6_ROUTE_EXT;
7583 : 0 : recom_off = curr_off++;
7584 : 0 : break;
7585 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7586 : 0 : raw_encap_data = at->actions[i].conf;
7587 : 0 : data_size = raw_encap_data->size;
7588 [ # # ]: 0 : if (reformat_off != UINT16_MAX) {
7589 : : reformat_act_type = data_size < MLX5_ENCAPSULATION_DECISION_SIZE ?
7590 [ # # ]: 0 : MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2 :
7591 : : MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3;
7592 : : } else {
7593 : 0 : reformat_off = curr_off++;
7594 : : reformat_act_type = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;
7595 : : }
7596 : : break;
7597 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7598 : 0 : reformat_off = curr_off++;
7599 : : reformat_act_type = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2;
7600 : 0 : break;
7601 : 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
7602 [ # # ]: 0 : if (mhdr_off == UINT16_MAX) {
7603 : 0 : mhdr_off = curr_off++;
7604 : 0 : type = mlx5_hw_dr_action_types[at->actions[i].type];
7605 : 0 : action_types[mhdr_off] = type;
7606 : : }
7607 : : break;
7608 : 0 : case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7609 : 0 : type = mlx5_hw_dr_action_types[at->actions[i].type];
7610 : 0 : at->dr_off[i] = curr_off;
7611 : 0 : action_types[curr_off++] = type;
7612 : 0 : i += is_of_vlan_pcp_present(at->actions + i) ?
7613 [ # # ]: 0 : MLX5_HW_VLAN_PUSH_PCP_IDX :
7614 : : MLX5_HW_VLAN_PUSH_VID_IDX;
7615 : 0 : break;
7616 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
7617 : 0 : at->dr_off[i] = curr_off;
7618 : 0 : action_types[curr_off++] = MLX5DR_ACTION_TYP_ASO_METER;
7619 [ # # ]: 0 : if (curr_off >= MLX5_HW_MAX_ACTS)
7620 : 0 : goto err_actions_num;
7621 : : break;
7622 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
7623 : : case RTE_FLOW_ACTION_TYPE_COUNT:
7624 : : /*
7625 : : * Both AGE and COUNT action need counter, the first
7626 : : * one fills the action_types array, and the second only
7627 : : * saves the offset.
7628 : : */
7629 [ # # ]: 0 : if (cnt_off == UINT16_MAX) {
7630 : 0 : cnt_off = curr_off++;
7631 : 0 : action_types[cnt_off] = MLX5DR_ACTION_TYP_CTR;
7632 : : }
7633 : 0 : at->dr_off[i] = cnt_off;
7634 : 0 : break;
7635 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
7636 : 0 : at->dr_off[i] = curr_off;
7637 : 0 : action_types[curr_off++] = MLX5DR_ACTION_TYP_MISS;
7638 : 0 : break;
7639 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
7640 : 0 : *tmpl_flags |= MLX5DR_ACTION_TEMPLATE_FLAG_RELAXED_ORDER;
7641 : 0 : at->dr_off[i] = curr_off;
7642 : 0 : action_types[curr_off++] = MLX5DR_ACTION_TYP_JUMP_TO_MATCHER;
7643 : 0 : break;
7644 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_MIRROR:
7645 : 0 : at->dr_off[i] = curr_off;
7646 : 0 : action_types[curr_off++] = MLX5DR_ACTION_TYP_DEST_ARRAY;
7647 : 0 : break;
7648 : 0 : default:
7649 : 0 : type = mlx5_hw_dr_action_types[at->actions[i].type];
7650 : 0 : at->dr_off[i] = curr_off;
7651 : 0 : action_types[curr_off++] = type;
7652 : 0 : break;
7653 : : }
7654 : : }
7655 [ # # ]: 0 : if (curr_off >= MLX5_HW_MAX_ACTS)
7656 : 0 : goto err_actions_num;
7657 [ # # ]: 0 : if (mhdr_off != UINT16_MAX)
7658 : 0 : at->mhdr_off = mhdr_off;
7659 [ # # ]: 0 : if (reformat_off != UINT16_MAX) {
7660 : 0 : at->reformat_off = reformat_off;
7661 : 0 : action_types[reformat_off] = reformat_act_type;
7662 : : }
7663 [ # # ]: 0 : if (recom_off != UINT16_MAX) {
7664 : 0 : at->recom_off = recom_off;
7665 : 0 : action_types[recom_off] = recom_type;
7666 : : }
7667 : 0 : at->dr_actions_num = curr_off;
7668 : :
7669 : : /* Create srh flex parser for remove anchor. */
7670 [ # # ]: 0 : if ((recom_type == MLX5DR_ACTION_TYP_POP_IPV6_ROUTE_EXT ||
7671 [ # # ]: 0 : recom_type == MLX5DR_ACTION_TYP_PUSH_IPV6_ROUTE_EXT) &&
7672 : 0 : (ret = mlx5_alloc_srh_flex_parser(dev))) {
7673 : 0 : DRV_LOG(ERR, "Failed to create srv6 flex parser");
7674 : 0 : return ret;
7675 : : }
7676 : : return 0;
7677 : 0 : err_actions_num:
7678 : 0 : DRV_LOG(ERR, "Number of HW actions (%u) exceeded maximum (%u) allowed in template",
7679 : : curr_off, MLX5_HW_MAX_ACTS);
7680 : 0 : return -EINVAL;
7681 : : }
7682 : :
7683 : : static int
7684 : 0 : flow_hw_set_vlan_vid(struct rte_eth_dev *dev,
7685 : : struct rte_flow_action *ra,
7686 : : struct rte_flow_action *rm,
7687 : : struct rte_flow_action_modify_field *spec,
7688 : : struct rte_flow_action_modify_field *mask,
7689 : : int set_vlan_vid_ix,
7690 : : struct rte_flow_error *error)
7691 : : {
7692 [ # # ]: 0 : const bool masked = rm[set_vlan_vid_ix].conf &&
7693 : : (((const struct rte_flow_action_of_set_vlan_vid *)
7694 [ # # ]: 0 : rm[set_vlan_vid_ix].conf)->vlan_vid != 0);
7695 : 0 : const struct rte_flow_action_of_set_vlan_vid *conf =
7696 : 0 : ra[set_vlan_vid_ix].conf;
7697 : 0 : int width = mlx5_flow_item_field_width(dev, RTE_FLOW_FIELD_VLAN_ID, 0,
7698 : : NULL, error);
7699 : : MLX5_ASSERT(width);
7700 : 0 : *spec = (typeof(*spec)) {
7701 : : .operation = RTE_FLOW_MODIFY_SET,
7702 : : .dst = {
7703 : : .field = RTE_FLOW_FIELD_VLAN_ID,
7704 : : .level = 0, .offset = 0,
7705 : : },
7706 : : .src = {
7707 : : .field = RTE_FLOW_FIELD_VALUE,
7708 : : },
7709 : : .width = width,
7710 : : };
7711 : 0 : *mask = (typeof(*mask)) {
7712 : : .operation = RTE_FLOW_MODIFY_SET,
7713 : : .dst = {
7714 : : .field = RTE_FLOW_FIELD_VLAN_ID,
7715 : : .level = 0xff, .offset = 0xffffffff,
7716 : : },
7717 : : .src = {
7718 : : .field = RTE_FLOW_FIELD_VALUE,
7719 : : },
7720 : : .width = 0xffffffff,
7721 : : };
7722 [ # # ]: 0 : if (masked) {
7723 : 0 : uint32_t mask_val = 0xffffffff;
7724 : :
7725 [ # # ]: 0 : rte_memcpy(spec->src.value, &conf->vlan_vid, sizeof(conf->vlan_vid));
7726 [ # # ]: 0 : rte_memcpy(mask->src.value, &mask_val, sizeof(mask_val));
7727 : : }
7728 : 0 : ra[set_vlan_vid_ix].type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD;
7729 : 0 : ra[set_vlan_vid_ix].conf = spec;
7730 : 0 : rm[set_vlan_vid_ix].type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD;
7731 : 0 : rm[set_vlan_vid_ix].conf = mask;
7732 : 0 : return 0;
7733 : : }
7734 : :
7735 : : static __rte_always_inline int
7736 : : flow_hw_set_vlan_vid_construct(struct rte_eth_dev *dev,
7737 : : struct mlx5_modification_cmd *mhdr_cmd,
7738 : : struct mlx5_action_construct_data *act_data,
7739 : : const struct mlx5_hw_actions *hw_acts,
7740 : : const struct rte_flow_action *action)
7741 : : {
7742 : : struct rte_flow_error error;
7743 : 0 : rte_be16_t vid = ((const struct rte_flow_action_of_set_vlan_vid *)
7744 : 0 : action->conf)->vlan_vid;
7745 : 0 : int width = mlx5_flow_item_field_width(dev, RTE_FLOW_FIELD_VLAN_ID, 0,
7746 : : NULL, &error);
7747 [ # # # # : 0 : struct rte_flow_action_modify_field conf = {
# # # # #
# ]
7748 : : .operation = RTE_FLOW_MODIFY_SET,
7749 : : .dst = {
7750 : : .field = RTE_FLOW_FIELD_VLAN_ID,
7751 : : .level = 0, .offset = 0,
7752 : : },
7753 : : .src = {
7754 : : .field = RTE_FLOW_FIELD_VALUE,
7755 : : },
7756 : : .width = width,
7757 : : };
7758 : : struct rte_flow_action modify_action = {
7759 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
7760 : : .conf = &conf
7761 : : };
7762 : :
7763 : : rte_memcpy(conf.src.value, &vid, sizeof(vid));
7764 : : return flow_hw_modify_field_construct(mhdr_cmd, act_data, hw_acts, &modify_action);
7765 : : }
7766 : :
7767 : : static int
7768 : 0 : flow_hw_flex_item_acquire(struct rte_eth_dev *dev,
7769 : : struct rte_flow_item_flex_handle *handle,
7770 : : uint8_t *flex_item)
7771 : : {
7772 : 0 : int index = mlx5_flex_acquire_index(dev, handle, false);
7773 : :
7774 : : MLX5_ASSERT(index >= 0 && index < (int)(sizeof(uint32_t) * CHAR_BIT));
7775 [ # # ]: 0 : if (index < 0)
7776 : : return -1;
7777 [ # # ]: 0 : if (!(*flex_item & RTE_BIT32(index))) {
7778 : : /* Don't count same flex item again. */
7779 : 0 : if (mlx5_flex_acquire_index(dev, handle, true) != index)
7780 : : MLX5_ASSERT(false);
7781 : 0 : *flex_item |= (uint8_t)RTE_BIT32(index);
7782 : : }
7783 : : return 0;
7784 : : }
7785 : :
7786 : : static void
7787 : 0 : flow_hw_flex_item_release(struct rte_eth_dev *dev, uint8_t *flex_item)
7788 : : {
7789 [ # # ]: 0 : while (*flex_item) {
7790 : 0 : int index = rte_bsf32(*flex_item);
7791 : :
7792 : 0 : mlx5_flex_release_index(dev, index);
7793 : 0 : *flex_item &= ~(uint8_t)RTE_BIT32(index);
7794 : : }
7795 : 0 : }
7796 : : static __rte_always_inline void
7797 : : flow_hw_actions_template_replace_container(const
7798 : : struct rte_flow_action *actions,
7799 : : const
7800 : : struct rte_flow_action *masks,
7801 : : struct rte_flow_action *new_actions,
7802 : : struct rte_flow_action *new_masks,
7803 : : struct rte_flow_action **ra,
7804 : : struct rte_flow_action **rm,
7805 : : uint32_t act_num)
7806 : : {
7807 : 0 : memcpy(new_actions, actions, sizeof(actions[0]) * act_num);
7808 : : memcpy(new_masks, masks, sizeof(masks[0]) * act_num);
7809 : : *ra = (void *)(uintptr_t)new_actions;
7810 : : *rm = (void *)(uintptr_t)new_masks;
7811 : 0 : }
7812 : :
7813 : : /* Action template copies these actions in rte_flow_conv() */
7814 : :
7815 : : static const struct rte_flow_action rx_meta_copy_action = {
7816 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
7817 : : .conf = &(struct rte_flow_action_modify_field){
7818 : : .operation = RTE_FLOW_MODIFY_SET,
7819 : : .dst = {
7820 : : .field = (enum rte_flow_field_id)
7821 : : MLX5_RTE_FLOW_FIELD_META_REG,
7822 : : .tag_index = REG_B,
7823 : : },
7824 : : .src = {
7825 : : .field = (enum rte_flow_field_id)
7826 : : MLX5_RTE_FLOW_FIELD_META_REG,
7827 : : .tag_index = REG_C_1,
7828 : : },
7829 : : .width = 32,
7830 : : }
7831 : : };
7832 : :
7833 : : static const struct rte_flow_action rx_meta_copy_mask = {
7834 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
7835 : : .conf = &(struct rte_flow_action_modify_field){
7836 : : .operation = RTE_FLOW_MODIFY_SET,
7837 : : .dst = {
7838 : : .field = (enum rte_flow_field_id)
7839 : : MLX5_RTE_FLOW_FIELD_META_REG,
7840 : : .level = UINT8_MAX,
7841 : : .tag_index = UINT8_MAX,
7842 : : .offset = UINT32_MAX,
7843 : : },
7844 : : .src = {
7845 : : .field = (enum rte_flow_field_id)
7846 : : MLX5_RTE_FLOW_FIELD_META_REG,
7847 : : .level = UINT8_MAX,
7848 : : .tag_index = UINT8_MAX,
7849 : : .offset = UINT32_MAX,
7850 : : },
7851 : : .width = UINT32_MAX,
7852 : : }
7853 : : };
7854 : :
7855 : : static const struct rte_flow_action quota_color_inc_action = {
7856 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
7857 : : .conf = &(struct rte_flow_action_modify_field) {
7858 : : .operation = RTE_FLOW_MODIFY_ADD,
7859 : : .dst = {
7860 : : .field = RTE_FLOW_FIELD_METER_COLOR,
7861 : : .level = 0, .offset = 0
7862 : : },
7863 : : .src = {
7864 : : .field = RTE_FLOW_FIELD_VALUE,
7865 : : .level = 1,
7866 : : .offset = 0,
7867 : : },
7868 : : .width = 2
7869 : : }
7870 : : };
7871 : :
7872 : : static const struct rte_flow_action quota_color_inc_mask = {
7873 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
7874 : : .conf = &(struct rte_flow_action_modify_field) {
7875 : : .operation = RTE_FLOW_MODIFY_ADD,
7876 : : .dst = {
7877 : : .field = RTE_FLOW_FIELD_METER_COLOR,
7878 : : .level = UINT8_MAX,
7879 : : .tag_index = UINT8_MAX,
7880 : : .offset = UINT32_MAX,
7881 : : },
7882 : : .src = {
7883 : : .field = RTE_FLOW_FIELD_VALUE,
7884 : : .level = 3,
7885 : : .offset = 0
7886 : : },
7887 : : .width = UINT32_MAX
7888 : : }
7889 : : };
7890 : :
7891 : : /**
7892 : : * Create flow action template.
7893 : : *
7894 : : * @param[in] dev
7895 : : * Pointer to the rte_eth_dev structure.
7896 : : * @param[in] attr
7897 : : * Pointer to the action template attributes.
7898 : : * @param[in] actions
7899 : : * Associated actions (list terminated by the END action).
7900 : : * @param[in] masks
7901 : : * List of actions that marks which of the action's member is constant.
7902 : : * @param[in] nt_mode
7903 : : * Non template mode.
7904 : : * @param[out] error
7905 : : * Pointer to error structure.
7906 : : *
7907 : : * @return
7908 : : * Action template pointer on success, NULL otherwise and rte_errno is set.
7909 : : */
7910 : : static struct rte_flow_actions_template *
7911 : 0 : __flow_hw_actions_template_create(struct rte_eth_dev *dev,
7912 : : const struct rte_flow_actions_template_attr *attr,
7913 : : const struct rte_flow_action actions[],
7914 : : const struct rte_flow_action masks[],
7915 : : bool nt_mode,
7916 : : struct rte_flow_error *error)
7917 : : {
7918 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
7919 : : int len, act_len, mask_len;
7920 : : int orig_act_len;
7921 : : unsigned int act_num;
7922 : : unsigned int i;
7923 : : struct rte_flow_actions_template *at = NULL;
7924 : : uint16_t pos;
7925 : 0 : uint64_t action_flags = 0;
7926 : : struct rte_flow_action tmp_action[MLX5_HW_MAX_ACTS];
7927 : : struct rte_flow_action tmp_mask[MLX5_HW_MAX_ACTS];
7928 : : struct rte_flow_action *ra = (void *)(uintptr_t)actions;
7929 : : struct rte_flow_action *rm = (void *)(uintptr_t)masks;
7930 : : int set_vlan_vid_ix = -1;
7931 : 0 : struct rte_flow_action_modify_field set_vlan_vid_spec = {0, };
7932 : 0 : struct rte_flow_action_modify_field set_vlan_vid_mask = {0, };
7933 : : struct rte_flow_action mf_actions[MLX5_HW_MAX_ACTS];
7934 : : struct rte_flow_action mf_masks[MLX5_HW_MAX_ACTS];
7935 : : uint32_t expand_mf_num = 0;
7936 : 0 : uint16_t src_off[MLX5_HW_MAX_ACTS] = {0, };
7937 : 0 : enum mlx5dr_action_type action_types[MLX5_HW_MAX_ACTS] = { MLX5DR_ACTION_TYP_LAST };
7938 : 0 : uint32_t tmpl_flags = 0;
7939 : : int ret;
7940 : :
7941 [ # # # # ]: 0 : if (!nt_mode && mlx5_flow_hw_actions_validate(dev, attr, actions, masks,
7942 : : &action_flags, error))
7943 : : return NULL;
7944 [ # # ]: 0 : for (i = 0; ra[i].type != RTE_FLOW_ACTION_TYPE_END; ++i) {
7945 [ # # # ]: 0 : switch (ra[i].type) {
7946 : : /* OF_PUSH_VLAN *MUST* come before OF_SET_VLAN_VID */
7947 : 0 : case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7948 : 0 : i += is_of_vlan_pcp_present(ra + i) ?
7949 [ # # ]: 0 : MLX5_HW_VLAN_PUSH_PCP_IDX :
7950 : : MLX5_HW_VLAN_PUSH_VID_IDX;
7951 : 0 : break;
7952 : 0 : case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7953 : 0 : set_vlan_vid_ix = i;
7954 : 0 : break;
7955 : : default:
7956 : : break;
7957 : : }
7958 : : }
7959 : : /*
7960 : : * Count flow actions to allocate required space for storing DR offsets and to check
7961 : : * if temporary buffer would not be overrun.
7962 : : */
7963 : 0 : act_num = i + 1;
7964 [ # # ]: 0 : if (act_num >= MLX5_HW_MAX_ACTS) {
7965 : 0 : rte_flow_error_set(error, EINVAL,
7966 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL, "Too many actions");
7967 : 0 : return NULL;
7968 : : }
7969 [ # # ]: 0 : if (set_vlan_vid_ix != -1) {
7970 : : /* If temporary action buffer was not used, copy template actions to it */
7971 : : if (ra == actions)
7972 : : flow_hw_actions_template_replace_container(actions,
7973 : : masks,
7974 : : tmp_action,
7975 : : tmp_mask,
7976 : : &ra, &rm,
7977 : : act_num);
7978 : 0 : ret = flow_hw_set_vlan_vid(dev, ra, rm,
7979 : : &set_vlan_vid_spec, &set_vlan_vid_mask,
7980 : : set_vlan_vid_ix, error);
7981 [ # # ]: 0 : if (ret)
7982 : 0 : goto error;
7983 : 0 : action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
7984 : : }
7985 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_QUOTA) {
7986 : 0 : mf_actions[expand_mf_num] = quota_color_inc_action;
7987 : 0 : mf_masks[expand_mf_num] = quota_color_inc_mask;
7988 : : expand_mf_num++;
7989 : : }
7990 [ # # ]: 0 : if (priv->sh->config.dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS &&
7991 : 0 : priv->sh->config.dv_esw_en &&
7992 [ # # ]: 0 : !attr->transfer &&
7993 [ # # ]: 0 : (action_flags & (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS))) {
7994 : : /* Insert META copy */
7995 : 0 : mf_actions[expand_mf_num] = rx_meta_copy_action;
7996 : 0 : mf_masks[expand_mf_num] = rx_meta_copy_mask;
7997 : 0 : expand_mf_num++;
7998 : : }
7999 [ # # ]: 0 : if (expand_mf_num) {
8000 [ # # ]: 0 : if (act_num + expand_mf_num > MLX5_HW_MAX_ACTS) {
8001 : 0 : rte_flow_error_set(error, E2BIG,
8002 : : RTE_FLOW_ERROR_TYPE_ACTION,
8003 : : NULL, "cannot expand: too many actions");
8004 : 0 : return NULL;
8005 : : }
8006 [ # # ]: 0 : if (ra == actions)
8007 : : flow_hw_actions_template_replace_container(actions,
8008 : : masks,
8009 : : tmp_action,
8010 : : tmp_mask,
8011 : : &ra, &rm,
8012 : : act_num);
8013 : : /* Application should make sure only one Q/RSS exist in one rule. */
8014 : 0 : pos = flow_hw_template_expand_modify_field(ra, rm,
8015 : : mf_actions,
8016 : : mf_masks,
8017 : : action_flags,
8018 : : act_num,
8019 : : expand_mf_num);
8020 [ # # ]: 0 : if (pos == MLX5_HW_EXPAND_MH_FAILED) {
8021 : 0 : rte_flow_error_set(error, ENOMEM,
8022 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8023 : : NULL, "modify header expansion failed");
8024 : 0 : return NULL;
8025 : : }
8026 : : act_num += expand_mf_num;
8027 [ # # ]: 0 : for (i = pos + expand_mf_num; i < act_num; i++)
8028 : 0 : src_off[i] += expand_mf_num;
8029 : 0 : action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
8030 : : }
8031 : 0 : act_len = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, NULL, 0, ra, error);
8032 [ # # ]: 0 : if (act_len <= 0)
8033 : : return NULL;
8034 : 0 : len = RTE_ALIGN(act_len, 16);
8035 : 0 : mask_len = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, NULL, 0, rm, error);
8036 [ # # ]: 0 : if (mask_len <= 0)
8037 : : return NULL;
8038 : 0 : len += RTE_ALIGN(mask_len, 16);
8039 : 0 : len += RTE_ALIGN(act_num * sizeof(*at->dr_off), 16);
8040 : 0 : len += RTE_ALIGN(act_num * sizeof(*at->src_off), 16);
8041 : 0 : orig_act_len = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, NULL, 0, actions, error);
8042 [ # # ]: 0 : if (orig_act_len <= 0)
8043 : : return NULL;
8044 : 0 : len += RTE_ALIGN(orig_act_len, 16);
8045 : 0 : at = mlx5_malloc(MLX5_MEM_ZERO, len + sizeof(*at),
8046 : : RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
8047 [ # # ]: 0 : if (!at) {
8048 : 0 : rte_flow_error_set(error, ENOMEM,
8049 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8050 : : NULL,
8051 : : "cannot allocate action template");
8052 : 0 : return NULL;
8053 : : }
8054 : : /* Actions part is in the first part. */
8055 : 0 : at->attr = *attr;
8056 : 0 : at->actions = (struct rte_flow_action *)(at + 1);
8057 : 0 : act_len = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, at->actions,
8058 : : len, ra, error);
8059 [ # # ]: 0 : if (act_len <= 0)
8060 : 0 : goto error;
8061 : : /* Masks part is in the second part. */
8062 : 0 : at->masks = (struct rte_flow_action *)(((uint8_t *)at->actions) + act_len);
8063 : 0 : mask_len = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, at->masks,
8064 : 0 : len - act_len, rm, error);
8065 [ # # ]: 0 : if (mask_len <= 0)
8066 : 0 : goto error;
8067 : : /* DR actions offsets in the third part. */
8068 : 0 : at->dr_off = (uint16_t *)((uint8_t *)at->masks + mask_len);
8069 : 0 : at->src_off = RTE_PTR_ADD(at->dr_off,
8070 : : RTE_ALIGN(act_num * sizeof(*at->dr_off), 16));
8071 : : memcpy(at->src_off, src_off, act_num * sizeof(at->src_off[0]));
8072 : 0 : at->orig_actions = RTE_PTR_ADD(at->src_off,
8073 : : RTE_ALIGN(act_num * sizeof(*at->src_off), 16));
8074 : 0 : orig_act_len = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, at->orig_actions, orig_act_len,
8075 : : actions, error);
8076 [ # # ]: 0 : if (orig_act_len <= 0)
8077 : 0 : goto error;
8078 : 0 : at->actions_num = act_num;
8079 [ # # ]: 0 : for (i = 0; i < at->actions_num; ++i)
8080 : 0 : at->dr_off[i] = UINT16_MAX;
8081 : 0 : at->reformat_off = UINT16_MAX;
8082 : 0 : at->mhdr_off = UINT16_MAX;
8083 : 0 : at->recom_off = UINT16_MAX;
8084 [ # # ]: 0 : for (i = 0; actions->type != RTE_FLOW_ACTION_TYPE_END;
8085 : 0 : actions++, masks++, i++) {
8086 : : const struct rte_flow_action_modify_field *info;
8087 : :
8088 [ # # # ]: 0 : switch (actions->type) {
8089 : : /*
8090 : : * mlx5 PMD hacks indirect action index directly to the action conf.
8091 : : * The rte_flow_conv() function copies the content from conf pointer.
8092 : : * Need to restore the indirect action index from action conf here.
8093 : : */
8094 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT:
8095 : 0 : at->actions[i].conf = ra[i].conf;
8096 : 0 : at->masks[i].conf = rm[i].conf;
8097 : 0 : break;
8098 : 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
8099 : 0 : info = actions->conf;
8100 [ # # # # ]: 0 : if ((info->dst.field == RTE_FLOW_FIELD_FLEX_ITEM &&
8101 : 0 : flow_hw_flex_item_acquire(dev, info->dst.flex_handle,
8102 : 0 : &at->flex_item)) ||
8103 [ # # # # ]: 0 : (info->src.field == RTE_FLOW_FIELD_FLEX_ITEM &&
8104 : 0 : flow_hw_flex_item_acquire(dev, info->src.flex_handle,
8105 : : &at->flex_item)))
8106 : 0 : goto error;
8107 : : break;
8108 : : default:
8109 : : break;
8110 : : }
8111 : : }
8112 : 0 : ret = flow_hw_parse_flow_actions_to_dr_actions(dev, at, action_types, &tmpl_flags);
8113 [ # # ]: 0 : if (ret)
8114 : 0 : goto error;
8115 : 0 : at->action_flags = action_flags;
8116 : : /* In non template mode there is no need to create the dr template. */
8117 [ # # ]: 0 : if (nt_mode)
8118 : : return at;
8119 : 0 : at->tmpl = mlx5dr_action_template_create(action_types, tmpl_flags);
8120 [ # # ]: 0 : if (!at->tmpl) {
8121 : 0 : DRV_LOG(ERR, "Failed to create DR action template: %d", rte_errno);
8122 : 0 : goto error;
8123 : : }
8124 : 0 : rte_atomic_fetch_add_explicit(&at->refcnt, 1, rte_memory_order_relaxed);
8125 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->flow_hw_at, at, next);
8126 : 0 : return at;
8127 : 0 : error:
8128 : : if (at) {
8129 : 0 : mlx5_free(at);
8130 : : }
8131 : 0 : rte_flow_error_set(error, rte_errno,
8132 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8133 : : "Failed to create action template");
8134 : 0 : return NULL;
8135 : : }
8136 : :
8137 : : /**
8138 : : * Create flow action template.
8139 : : *
8140 : : * @param[in] dev
8141 : : * Pointer to the rte_eth_dev structure.
8142 : : * @param[in] attr
8143 : : * Pointer to the action template attributes.
8144 : : * @param[in] actions
8145 : : * Associated actions (list terminated by the END action).
8146 : : * @param[in] masks
8147 : : * List of actions that marks which of the action's member is constant.
8148 : : * @param[out] error
8149 : : * Pointer to error structure.
8150 : : *
8151 : : * @return
8152 : : * Action template pointer on success, NULL otherwise and rte_errno is set.
8153 : : */
8154 : : static struct rte_flow_actions_template *
8155 : 0 : flow_hw_actions_template_create(struct rte_eth_dev *dev,
8156 : : const struct rte_flow_actions_template_attr *attr,
8157 : : const struct rte_flow_action actions[],
8158 : : const struct rte_flow_action masks[],
8159 : : struct rte_flow_error *error)
8160 : : {
8161 : 0 : return __flow_hw_actions_template_create(dev, attr, actions, masks, false, error);
8162 : : }
8163 : :
8164 : : /**
8165 : : * Destroy flow action template.
8166 : : *
8167 : : * @param[in] dev
8168 : : * Pointer to the rte_eth_dev structure.
8169 : : * @param[in] template
8170 : : * Pointer to the action template to be destroyed.
8171 : : * @param[out] error
8172 : : * Pointer to error structure.
8173 : : *
8174 : : * @return
8175 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
8176 : : */
8177 : : static int
8178 : 0 : flow_hw_actions_template_destroy(struct rte_eth_dev *dev,
8179 : : struct rte_flow_actions_template *template,
8180 : : struct rte_flow_error *error __rte_unused)
8181 : : {
8182 : : uint64_t flag = MLX5_FLOW_ACTION_IPV6_ROUTING_REMOVE |
8183 : : MLX5_FLOW_ACTION_IPV6_ROUTING_PUSH;
8184 : :
8185 [ # # ]: 0 : if (rte_atomic_load_explicit(&template->refcnt, rte_memory_order_relaxed) > 1) {
8186 : 0 : DRV_LOG(WARNING, "Action template %p is still in use.",
8187 : : (void *)template);
8188 : 0 : return rte_flow_error_set(error, EBUSY,
8189 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8190 : : NULL,
8191 : : "action template is in use");
8192 : : }
8193 [ # # ]: 0 : if (template->action_flags & flag)
8194 : 0 : mlx5_free_srh_flex_parser(dev);
8195 [ # # ]: 0 : LIST_REMOVE(template, next);
8196 : 0 : flow_hw_flex_item_release(dev, &template->flex_item);
8197 [ # # ]: 0 : if (template->tmpl)
8198 : 0 : mlx5dr_action_template_destroy(template->tmpl);
8199 : 0 : mlx5_free(template);
8200 : 0 : return 0;
8201 : : }
8202 : :
8203 : : static struct rte_flow_item *
8204 : 0 : flow_hw_prepend_item(const struct rte_flow_item *items,
8205 : : const uint32_t nb_items,
8206 : : const struct rte_flow_item *new_item,
8207 : : struct rte_flow_error *error)
8208 : : {
8209 : : struct rte_flow_item *copied_items;
8210 : : size_t size;
8211 : :
8212 : : /* Allocate new array of items. */
8213 : 0 : size = sizeof(*copied_items) * (nb_items + 1);
8214 : 0 : copied_items = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
8215 [ # # ]: 0 : if (!copied_items) {
8216 : 0 : rte_flow_error_set(error, ENOMEM,
8217 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8218 : : NULL,
8219 : : "cannot allocate item template");
8220 : 0 : return NULL;
8221 : : }
8222 : : /* Put new item at the beginning and copy the rest. */
8223 : 0 : copied_items[0] = *new_item;
8224 [ # # ]: 0 : rte_memcpy(&copied_items[1], items, sizeof(*items) * nb_items);
8225 : : return copied_items;
8226 : : }
8227 : :
8228 : : static int
8229 : 0 : flow_hw_item_compare_field_validate(enum rte_flow_field_id arg_field,
8230 : : enum rte_flow_field_id base_field,
8231 : : struct rte_flow_error *error)
8232 : : {
8233 [ # # # ]: 0 : switch (arg_field) {
8234 : : case RTE_FLOW_FIELD_TAG:
8235 : : case RTE_FLOW_FIELD_META:
8236 : : case RTE_FLOW_FIELD_ESP_SEQ_NUM:
8237 : : break;
8238 : 0 : case RTE_FLOW_FIELD_RANDOM:
8239 [ # # ]: 0 : if (base_field == RTE_FLOW_FIELD_VALUE)
8240 : : return 0;
8241 : 0 : return rte_flow_error_set(error, EINVAL,
8242 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8243 : : NULL,
8244 : : "compare random is supported only with immediate value");
8245 : 0 : default:
8246 : 0 : return rte_flow_error_set(error, ENOTSUP,
8247 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8248 : : NULL,
8249 : : "compare item argument field is not supported");
8250 : : }
8251 [ # # ]: 0 : switch (base_field) {
8252 : : case RTE_FLOW_FIELD_TAG:
8253 : : case RTE_FLOW_FIELD_META:
8254 : : case RTE_FLOW_FIELD_VALUE:
8255 : : case RTE_FLOW_FIELD_ESP_SEQ_NUM:
8256 : : break;
8257 : 0 : default:
8258 : 0 : return rte_flow_error_set(error, ENOTSUP,
8259 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8260 : : NULL,
8261 : : "compare item base field is not supported");
8262 : : }
8263 : : return 0;
8264 : : }
8265 : :
8266 : : static inline uint32_t
8267 : : flow_hw_item_compare_width_supported(enum rte_flow_field_id field)
8268 : : {
8269 [ # # # ]: 0 : switch (field) {
8270 : : case RTE_FLOW_FIELD_TAG:
8271 : : case RTE_FLOW_FIELD_META:
8272 : : case RTE_FLOW_FIELD_ESP_SEQ_NUM:
8273 : : return 32;
8274 : 0 : case RTE_FLOW_FIELD_RANDOM:
8275 : 0 : return 16;
8276 : : default:
8277 : : break;
8278 : : }
8279 : 0 : return 0;
8280 : : }
8281 : :
8282 : : static int
8283 : 0 : flow_hw_validate_item_compare(const struct rte_flow_item *item,
8284 : : struct rte_flow_error *error)
8285 : : {
8286 : 0 : const struct rte_flow_item_compare *comp_m = item->mask;
8287 : 0 : const struct rte_flow_item_compare *comp_v = item->spec;
8288 : : int ret;
8289 : :
8290 [ # # ]: 0 : if (unlikely(!comp_m))
8291 : 0 : return rte_flow_error_set(error, EINVAL,
8292 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8293 : : NULL,
8294 : : "compare item mask is missing");
8295 [ # # ]: 0 : if (comp_m->width != UINT32_MAX)
8296 : 0 : return rte_flow_error_set(error, EINVAL,
8297 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8298 : : NULL,
8299 : : "compare item only support full mask");
8300 : 0 : ret = flow_hw_item_compare_field_validate(comp_m->a.field,
8301 : 0 : comp_m->b.field, error);
8302 [ # # ]: 0 : if (ret < 0)
8303 : : return ret;
8304 [ # # ]: 0 : if (comp_v) {
8305 : : uint32_t width;
8306 : :
8307 [ # # ]: 0 : if (comp_v->operation != comp_m->operation ||
8308 [ # # ]: 0 : comp_v->a.field != comp_m->a.field ||
8309 [ # # ]: 0 : comp_v->b.field != comp_m->b.field)
8310 : 0 : return rte_flow_error_set(error, EINVAL,
8311 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8312 : : NULL,
8313 : : "compare item spec/mask not matching");
8314 : : width = flow_hw_item_compare_width_supported(comp_v->a.field);
8315 : : MLX5_ASSERT(width > 0);
8316 [ # # ]: 0 : if ((comp_v->width & comp_m->width) != width)
8317 : 0 : return rte_flow_error_set(error, EINVAL,
8318 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8319 : : NULL,
8320 : : "compare item only support full mask");
8321 : : }
8322 : : return 0;
8323 : : }
8324 : :
8325 : : static inline int
8326 : : mlx5_hw_validate_item_nsh(struct rte_eth_dev *dev,
8327 : : const struct rte_flow_item *item,
8328 : : struct rte_flow_error *error)
8329 : : {
8330 : 0 : return mlx5_flow_validate_item_nsh(dev, item, error);
8331 : : }
8332 : :
8333 : : static bool
8334 : : mlx5_hw_flow_tunnel_ip_check(uint64_t last_item, uint64_t *item_flags)
8335 : : {
8336 : : bool tunnel;
8337 : :
8338 : 0 : if (last_item == MLX5_FLOW_LAYER_OUTER_L3_IPV4 ||
8339 [ # # # # ]: 0 : last_item == MLX5_FLOW_LAYER_OUTER_L3_IPV6) {
8340 : : tunnel = true;
8341 : 0 : *item_flags |= MLX5_FLOW_LAYER_IPIP;
8342 [ # # # # ]: 0 : } else if (last_item == MLX5_FLOW_LAYER_OUTER_L3_IPV6 ||
8343 : : last_item == MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT) {
8344 : : tunnel = true;
8345 : 0 : *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
8346 : : } else {
8347 : : tunnel = false;
8348 : : }
8349 : : return tunnel;
8350 : : }
8351 : :
8352 : : const struct rte_flow_item_ipv4 hws_nic_ipv4_mask = {
8353 : : .hdr = {
8354 : : .version = 0xf,
8355 : : .ihl = 0xf,
8356 : : .type_of_service = 0xff,
8357 : : .total_length = RTE_BE16(0xffff),
8358 : : .packet_id = RTE_BE16(0xffff),
8359 : : .fragment_offset = RTE_BE16(0xffff),
8360 : : .time_to_live = 0xff,
8361 : : .next_proto_id = 0xff,
8362 : : .src_addr = RTE_BE32(0xffffffff),
8363 : : .dst_addr = RTE_BE32(0xffffffff),
8364 : : },
8365 : : };
8366 : :
8367 : : const struct rte_flow_item_ipv6 hws_nic_ipv6_mask = {
8368 : : .hdr = {
8369 : : .vtc_flow = RTE_BE32(0xffffffff),
8370 : : .payload_len = RTE_BE16(0xffff),
8371 : : .proto = 0xff,
8372 : : .hop_limits = 0xff,
8373 : : .src_addr = RTE_IPV6_MASK_FULL,
8374 : : .dst_addr = RTE_IPV6_MASK_FULL,
8375 : : },
8376 : : .has_frag_ext = 1,
8377 : : };
8378 : :
8379 : : const struct rte_flow_item_ecpri hws_nic_ecpri_mask = {
8380 : : .hdr = {
8381 : : .common = {
8382 : : .u32 = RTE_BE32(0xffffffff),
8383 : : },
8384 : : .dummy[0] = 0xffffffff,
8385 : : },
8386 : : };
8387 : :
8388 : :
8389 : : static int
8390 : 0 : flow_hw_validate_item_ptype(const struct rte_flow_item *item,
8391 : : struct rte_flow_error *error)
8392 : : {
8393 : 0 : const struct rte_flow_item_ptype *ptype = item->mask;
8394 : :
8395 : : /* HWS does not allow empty PTYPE mask */
8396 [ # # ]: 0 : if (!ptype)
8397 : 0 : return rte_flow_error_set(error, EINVAL,
8398 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8399 : : NULL, "empty ptype mask");
8400 [ # # ]: 0 : if (!(ptype->packet_type &
8401 : : (RTE_PTYPE_L2_MASK | RTE_PTYPE_L3_MASK | RTE_PTYPE_L4_MASK |
8402 : : RTE_PTYPE_INNER_L2_MASK | RTE_PTYPE_INNER_L3_MASK |
8403 : : RTE_PTYPE_INNER_L4_MASK)))
8404 : 0 : return rte_flow_error_set(error, ENOTSUP,
8405 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8406 : : NULL, "ptype mask not supported");
8407 : : return 0;
8408 : : }
8409 : :
8410 : : struct mlx5_hw_pattern_validation_ctx {
8411 : : const struct rte_flow_item *geneve_item;
8412 : : const struct rte_flow_item *flex_item;
8413 : : };
8414 : :
8415 : : static int
8416 : 0 : __flow_hw_pattern_validate(struct rte_eth_dev *dev,
8417 : : const struct rte_flow_pattern_template_attr *attr,
8418 : : const struct rte_flow_item items[],
8419 : : uint64_t *item_flags,
8420 : : bool nt_flow,
8421 : : struct rte_flow_error *error)
8422 : : {
8423 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
8424 : : const struct rte_flow_item *item;
8425 : : const struct rte_flow_item *gtp_item = NULL;
8426 : : const struct rte_flow_item *gre_item = NULL;
8427 : 0 : const struct rte_flow_attr flow_attr = {
8428 : 0 : .ingress = attr->ingress,
8429 : 0 : .egress = attr->egress,
8430 : 0 : .transfer = attr->transfer
8431 : : };
8432 : : int ret, tag_idx;
8433 : : uint32_t tag_bitmap = 0;
8434 : : uint64_t last_item = 0;
8435 : :
8436 [ # # ]: 0 : if (!mlx5_hw_ctx_validate(dev, error))
8437 : 0 : return -rte_errno;
8438 [ # # ]: 0 : if (!attr->ingress && !attr->egress && !attr->transfer)
8439 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ATTR, NULL,
8440 : : "at least one of the direction attributes"
8441 : : " must be specified");
8442 [ # # ]: 0 : if (priv->sh->config.dv_esw_en) {
8443 : : MLX5_ASSERT(priv->master || priv->representor);
8444 [ # # ]: 0 : if (priv->master) {
8445 [ # # ]: 0 : if ((attr->ingress && attr->egress) ||
8446 [ # # ]: 0 : (attr->ingress && attr->transfer) ||
8447 [ # # ]: 0 : (attr->egress && attr->transfer))
8448 : 0 : return rte_flow_error_set(error, EINVAL,
8449 : : RTE_FLOW_ERROR_TYPE_ATTR, NULL,
8450 : : "only one direction attribute at once"
8451 : : " can be used on transfer proxy port");
8452 : : } else {
8453 [ # # ]: 0 : if (attr->transfer)
8454 : 0 : return rte_flow_error_set(error, EINVAL,
8455 : : RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER, NULL,
8456 : : "transfer attribute cannot be used with"
8457 : : " port representors");
8458 [ # # ]: 0 : if (attr->ingress && attr->egress)
8459 : 0 : return rte_flow_error_set(error, EINVAL,
8460 : : RTE_FLOW_ERROR_TYPE_ATTR, NULL,
8461 : : "ingress and egress direction attributes"
8462 : : " cannot be used at the same time on"
8463 : : " port representors");
8464 : : }
8465 : : } else {
8466 [ # # ]: 0 : if (attr->transfer)
8467 : 0 : return rte_flow_error_set(error, EINVAL,
8468 : : RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER, NULL,
8469 : : "transfer attribute cannot be used when"
8470 : : " E-Switch is disabled");
8471 : : }
8472 [ # # ]: 0 : for (item = items; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
8473 : 0 : bool tunnel = *item_flags & MLX5_FLOW_LAYER_TUNNEL;
8474 : :
8475 [ # # # # : 0 : switch ((int)item->type) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # #
# ]
8476 : 0 : case RTE_FLOW_ITEM_TYPE_PTYPE:
8477 : 0 : ret = flow_hw_validate_item_ptype(item, error);
8478 [ # # ]: 0 : if (ret)
8479 : 0 : return ret;
8480 : : last_item = MLX5_FLOW_ITEM_PTYPE;
8481 : : break;
8482 : 0 : case RTE_FLOW_ITEM_TYPE_TAG:
8483 : : {
8484 : 0 : const struct rte_flow_item_tag *tag =
8485 : : (const struct rte_flow_item_tag *)item->spec;
8486 : :
8487 [ # # ]: 0 : if (tag == NULL)
8488 : 0 : return rte_flow_error_set(error, EINVAL,
8489 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8490 : : NULL,
8491 : : "Tag spec is NULL");
8492 [ # # ]: 0 : if (tag->index >= MLX5_FLOW_HW_TAGS_MAX &&
8493 : : tag->index != RTE_PMD_MLX5_LINEAR_HASH_TAG_INDEX)
8494 : 0 : return rte_flow_error_set(error, EINVAL,
8495 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8496 : : NULL,
8497 : : "Invalid tag index");
8498 [ # # ]: 0 : tag_idx = flow_hw_get_reg_id(dev, RTE_FLOW_ITEM_TYPE_TAG, tag->index);
8499 [ # # ]: 0 : if (tag_idx == REG_NON)
8500 : 0 : return rte_flow_error_set(error, EINVAL,
8501 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8502 : : NULL,
8503 : : "Unsupported tag index");
8504 [ # # ]: 0 : if (tag_bitmap & (1 << tag_idx))
8505 : 0 : return rte_flow_error_set(error, EINVAL,
8506 : : RTE_FLOW_ERROR_TYPE_ITEM,
8507 : : NULL,
8508 : : "Duplicated tag index");
8509 : 0 : tag_bitmap |= 1 << tag_idx;
8510 : : last_item = MLX5_FLOW_ITEM_TAG;
8511 : 0 : break;
8512 : : }
8513 : 0 : case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
8514 : : {
8515 : 0 : const struct rte_flow_item_tag *tag =
8516 : : (const struct rte_flow_item_tag *)item->spec;
8517 : 0 : uint16_t regcs = (uint8_t)priv->sh->cdev->config.hca_attr.set_reg_c;
8518 : :
8519 [ # # ]: 0 : if (!((1 << (tag->index - REG_C_0)) & regcs))
8520 : 0 : return rte_flow_error_set(error, EINVAL,
8521 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8522 : : NULL,
8523 : : "Unsupported internal tag index");
8524 [ # # ]: 0 : if (tag_bitmap & (1 << tag->index))
8525 : 0 : return rte_flow_error_set(error, EINVAL,
8526 : : RTE_FLOW_ERROR_TYPE_ITEM,
8527 : : NULL,
8528 : : "Duplicated tag index");
8529 : 0 : tag_bitmap |= 1 << tag->index;
8530 : 0 : break;
8531 : : }
8532 : 0 : case RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT:
8533 [ # # # # ]: 0 : if (attr->ingress && priv->sh->config.repr_matching)
8534 : 0 : return rte_flow_error_set(error, EINVAL,
8535 : : RTE_FLOW_ERROR_TYPE_ITEM, NULL,
8536 : : "represented port item cannot be used"
8537 : : " when ingress attribute is set");
8538 [ # # ]: 0 : if (attr->egress)
8539 : 0 : return rte_flow_error_set(error, EINVAL,
8540 : : RTE_FLOW_ERROR_TYPE_ITEM, NULL,
8541 : : "represented port item cannot be used"
8542 : : " when egress attribute is set");
8543 : : last_item = MLX5_FLOW_ITEM_REPRESENTED_PORT;
8544 : : break;
8545 : 0 : case RTE_FLOW_ITEM_TYPE_META:
8546 : : /* ingress + group 0 is not supported */
8547 : 0 : *item_flags |= MLX5_FLOW_ITEM_METADATA;
8548 : 0 : break;
8549 : : case RTE_FLOW_ITEM_TYPE_METER_COLOR:
8550 : : {
8551 : : int reg = flow_hw_get_reg_id(dev,
8552 : : RTE_FLOW_ITEM_TYPE_METER_COLOR,
8553 : : 0);
8554 [ # # ]: 0 : if (reg == REG_NON)
8555 : 0 : return rte_flow_error_set(error, EINVAL,
8556 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8557 : : NULL,
8558 : : "Unsupported meter color register");
8559 [ # # ]: 0 : if (*item_flags &
8560 : : (MLX5_FLOW_ITEM_QUOTA | MLX5_FLOW_LAYER_ASO_CT))
8561 : 0 : return rte_flow_error_set
8562 : : (error, EINVAL,
8563 : : RTE_FLOW_ERROR_TYPE_ITEM, NULL, "Only one ASO item is supported");
8564 : : last_item = MLX5_FLOW_ITEM_METER_COLOR;
8565 : : break;
8566 : : }
8567 : 0 : case RTE_FLOW_ITEM_TYPE_AGGR_AFFINITY:
8568 : : {
8569 [ # # ]: 0 : if (!priv->sh->lag_rx_port_affinity_en)
8570 : 0 : return rte_flow_error_set(error, EINVAL,
8571 : : RTE_FLOW_ERROR_TYPE_ITEM, NULL,
8572 : : "Unsupported aggregated affinity with Older FW");
8573 [ # # # # : 0 : if ((attr->transfer && priv->fdb_def_rule) || attr->egress)
# # ]
8574 : 0 : return rte_flow_error_set(error, EINVAL,
8575 : : RTE_FLOW_ERROR_TYPE_ITEM, NULL,
8576 : : "Aggregated affinity item not supported"
8577 : : " with egress or transfer"
8578 : : " attribute");
8579 : : last_item = MLX5_FLOW_ITEM_AGGR_AFFINITY;
8580 : : break;
8581 : : }
8582 : 0 : case RTE_FLOW_ITEM_TYPE_GENEVE:
8583 : : last_item = MLX5_FLOW_LAYER_GENEVE;
8584 : 0 : break;
8585 : 0 : case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
8586 : : {
8587 : : last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
8588 : : /*
8589 : : * For non template the parser is internally created before
8590 : : * the flow creation.
8591 : : */
8592 [ # # ]: 0 : if (!nt_flow) {
8593 : 0 : ret = mlx5_flow_geneve_tlv_option_validate(priv, item,
8594 : : error);
8595 [ # # ]: 0 : if (ret < 0)
8596 : 0 : return ret;
8597 : : }
8598 : : break;
8599 : : }
8600 : 0 : case RTE_FLOW_ITEM_TYPE_COMPARE:
8601 : : {
8602 : : last_item = MLX5_FLOW_ITEM_COMPARE;
8603 : 0 : ret = flow_hw_validate_item_compare(item, error);
8604 [ # # ]: 0 : if (ret)
8605 : 0 : return ret;
8606 : : break;
8607 : : }
8608 : 0 : case RTE_FLOW_ITEM_TYPE_ETH:
8609 : 0 : ret = mlx5_flow_validate_item_eth(dev, item,
8610 : : *item_flags,
8611 : : true, error);
8612 [ # # ]: 0 : if (ret < 0)
8613 : 0 : return ret;
8614 [ # # ]: 0 : last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
8615 : : MLX5_FLOW_LAYER_OUTER_L2;
8616 : : break;
8617 : 0 : case RTE_FLOW_ITEM_TYPE_VLAN:
8618 : 0 : ret = mlx5_flow_dv_validate_item_vlan(item, *item_flags,
8619 : : dev, error);
8620 [ # # ]: 0 : if (ret < 0)
8621 : 0 : return ret;
8622 [ # # ]: 0 : last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
8623 : : MLX5_FLOW_LAYER_OUTER_VLAN;
8624 : : break;
8625 : : case RTE_FLOW_ITEM_TYPE_IPV4:
8626 : 0 : tunnel |= mlx5_hw_flow_tunnel_ip_check(last_item,
8627 : : item_flags);
8628 : 0 : ret = mlx5_flow_dv_validate_item_ipv4(dev, item,
8629 : : *item_flags,
8630 : : last_item, 0,
8631 : : &hws_nic_ipv4_mask,
8632 : : error);
8633 [ # # ]: 0 : if (ret)
8634 : 0 : return ret;
8635 [ # # ]: 0 : last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
8636 : : MLX5_FLOW_LAYER_OUTER_L3_IPV4;
8637 : : break;
8638 : : case RTE_FLOW_ITEM_TYPE_IPV6:
8639 : 0 : tunnel |= mlx5_hw_flow_tunnel_ip_check(last_item,
8640 : : item_flags);
8641 : 0 : ret = mlx5_flow_validate_item_ipv6(dev, item,
8642 : : *item_flags,
8643 : : last_item, 0,
8644 : : &hws_nic_ipv6_mask,
8645 : : error);
8646 [ # # ]: 0 : if (ret < 0)
8647 : 0 : return ret;
8648 [ # # ]: 0 : last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
8649 : : MLX5_FLOW_LAYER_OUTER_L3_IPV6;
8650 : : break;
8651 : 0 : case RTE_FLOW_ITEM_TYPE_UDP:
8652 : 0 : ret = mlx5_flow_validate_item_udp(dev, item,
8653 : : *item_flags,
8654 : : 0xff, error);
8655 [ # # ]: 0 : if (ret)
8656 : 0 : return ret;
8657 [ # # ]: 0 : last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
8658 : : MLX5_FLOW_LAYER_OUTER_L4_UDP;
8659 : : break;
8660 : 0 : case RTE_FLOW_ITEM_TYPE_TCP:
8661 : 0 : ret = mlx5_flow_validate_item_tcp
8662 : : (dev, item, *item_flags,
8663 : : 0xff, &nic_tcp_mask, error);
8664 [ # # ]: 0 : if (ret < 0)
8665 : 0 : return ret;
8666 [ # # ]: 0 : last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
8667 : : MLX5_FLOW_LAYER_OUTER_L4_TCP;
8668 : : break;
8669 : 0 : case RTE_FLOW_ITEM_TYPE_GTP:
8670 : : gtp_item = item;
8671 : 0 : ret = mlx5_flow_dv_validate_item_gtp(dev, gtp_item,
8672 : : *item_flags, error);
8673 [ # # ]: 0 : if (ret < 0)
8674 : 0 : return ret;
8675 : : last_item = MLX5_FLOW_LAYER_GTP;
8676 : : break;
8677 : 0 : case RTE_FLOW_ITEM_TYPE_GTP_PSC:
8678 : 0 : ret = mlx5_flow_dv_validate_item_gtp_psc(dev, item,
8679 : : last_item,
8680 : : gtp_item,
8681 : : false, error);
8682 [ # # ]: 0 : if (ret < 0)
8683 : 0 : return ret;
8684 : : last_item = MLX5_FLOW_LAYER_GTP_PSC;
8685 : : break;
8686 : 0 : case RTE_FLOW_ITEM_TYPE_VXLAN:
8687 : 0 : ret = mlx5_flow_validate_item_vxlan(dev, 0, item,
8688 : : *item_flags,
8689 : : false, error);
8690 [ # # ]: 0 : if (ret < 0)
8691 : 0 : return ret;
8692 : : last_item = MLX5_FLOW_LAYER_VXLAN;
8693 : : break;
8694 : 0 : case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
8695 : 0 : ret = mlx5_flow_validate_item_vxlan_gpe(item,
8696 : : *item_flags,
8697 : : dev, error);
8698 [ # # ]: 0 : if (ret < 0)
8699 : 0 : return ret;
8700 : : last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
8701 : : break;
8702 : 0 : case RTE_FLOW_ITEM_TYPE_MPLS:
8703 : 0 : ret = mlx5_flow_validate_item_mpls(dev, item,
8704 : : *item_flags,
8705 : : last_item, error);
8706 [ # # ]: 0 : if (ret < 0)
8707 : 0 : return ret;
8708 : : last_item = MLX5_FLOW_LAYER_MPLS;
8709 : : break;
8710 : 0 : case MLX5_RTE_FLOW_ITEM_TYPE_SQ:
8711 : : case RTE_FLOW_ITEM_TYPE_TX_QUEUE:
8712 : : last_item = MLX5_FLOW_ITEM_SQ;
8713 : 0 : break;
8714 : 0 : case RTE_FLOW_ITEM_TYPE_GRE:
8715 : 0 : ret = mlx5_flow_validate_item_gre(dev, item,
8716 : : *item_flags,
8717 : : 0xff, error);
8718 [ # # ]: 0 : if (ret < 0)
8719 : 0 : return ret;
8720 : : gre_item = item;
8721 : : last_item = MLX5_FLOW_LAYER_GRE;
8722 : : break;
8723 : 0 : case RTE_FLOW_ITEM_TYPE_GRE_KEY:
8724 [ # # ]: 0 : if (!(*item_flags & MLX5_FLOW_LAYER_GRE))
8725 : 0 : return rte_flow_error_set
8726 : : (error, EINVAL,
8727 : : RTE_FLOW_ERROR_TYPE_ITEM, item, "GRE item is missing");
8728 : 0 : ret = mlx5_flow_validate_item_gre_key
8729 : : (dev, item, *item_flags, gre_item, error);
8730 [ # # ]: 0 : if (ret < 0)
8731 : 0 : return ret;
8732 : : last_item = MLX5_FLOW_LAYER_GRE_KEY;
8733 : : break;
8734 : 0 : case RTE_FLOW_ITEM_TYPE_GRE_OPTION:
8735 [ # # ]: 0 : if (!(*item_flags & MLX5_FLOW_LAYER_GRE))
8736 : 0 : return rte_flow_error_set
8737 : : (error, EINVAL,
8738 : : RTE_FLOW_ERROR_TYPE_ITEM, item, "GRE item is missing");
8739 : 0 : ret = mlx5_flow_validate_item_gre_option(dev, item,
8740 : : *item_flags,
8741 : : &flow_attr,
8742 : : gre_item,
8743 : : error);
8744 [ # # ]: 0 : if (ret < 0)
8745 : 0 : return ret;
8746 : : last_item = MLX5_FLOW_LAYER_GRE;
8747 : : break;
8748 : 0 : case RTE_FLOW_ITEM_TYPE_NVGRE:
8749 : 0 : ret = mlx5_flow_validate_item_nvgre(dev, item,
8750 : : *item_flags, 0xff,
8751 : : error);
8752 [ # # ]: 0 : if (ret)
8753 : 0 : return ret;
8754 : : last_item = MLX5_FLOW_LAYER_NVGRE;
8755 : : break;
8756 : 0 : case RTE_FLOW_ITEM_TYPE_ICMP:
8757 : 0 : ret = mlx5_flow_validate_item_icmp(dev, item,
8758 : : *item_flags, 0xff,
8759 : : error);
8760 [ # # ]: 0 : if (ret < 0)
8761 : 0 : return ret;
8762 : : last_item = MLX5_FLOW_LAYER_ICMP;
8763 : : break;
8764 : 0 : case RTE_FLOW_ITEM_TYPE_ICMP6:
8765 : 0 : ret = mlx5_flow_validate_item_icmp6(dev, item,
8766 : : *item_flags, 0xff,
8767 : : error);
8768 [ # # ]: 0 : if (ret < 0)
8769 : 0 : return ret;
8770 : : last_item = MLX5_FLOW_LAYER_ICMP6;
8771 : : break;
8772 : 0 : case RTE_FLOW_ITEM_TYPE_ICMP6_ECHO_REQUEST:
8773 : : case RTE_FLOW_ITEM_TYPE_ICMP6_ECHO_REPLY:
8774 : 0 : ret = mlx5_flow_validate_item_icmp6_echo(dev, item,
8775 : : *item_flags,
8776 : : 0xff, error);
8777 [ # # ]: 0 : if (ret < 0)
8778 : 0 : return ret;
8779 : : last_item = MLX5_FLOW_LAYER_ICMP6;
8780 : : break;
8781 : 0 : case RTE_FLOW_ITEM_TYPE_CONNTRACK:
8782 [ # # ]: 0 : if (*item_flags &
8783 : : (MLX5_FLOW_ITEM_QUOTA | MLX5_FLOW_LAYER_ASO_CT))
8784 : 0 : return rte_flow_error_set
8785 : : (error, EINVAL,
8786 : : RTE_FLOW_ERROR_TYPE_ITEM, NULL, "Only one ASO item is supported");
8787 : 0 : ret = mlx5_flow_dv_validate_item_aso_ct(dev, item,
8788 : : item_flags,
8789 : : error);
8790 [ # # ]: 0 : if (ret < 0)
8791 : 0 : return ret;
8792 : : break;
8793 : 0 : case RTE_FLOW_ITEM_TYPE_QUOTA:
8794 [ # # ]: 0 : if (*item_flags &
8795 : : (MLX5_FLOW_ITEM_METER_COLOR |
8796 : : MLX5_FLOW_LAYER_ASO_CT))
8797 : 0 : return rte_flow_error_set
8798 : : (error, EINVAL,
8799 : : RTE_FLOW_ERROR_TYPE_ITEM, NULL, "Only one ASO item is supported");
8800 : : last_item = MLX5_FLOW_ITEM_QUOTA;
8801 : : break;
8802 : 0 : case RTE_FLOW_ITEM_TYPE_ESP:
8803 : 0 : ret = mlx5_flow_os_validate_item_esp(dev, item,
8804 : : *item_flags, 0xff,
8805 : : error);
8806 [ # # ]: 0 : if (ret < 0)
8807 : 0 : return ret;
8808 : : last_item = MLX5_FLOW_ITEM_ESP;
8809 : : break;
8810 : 0 : case RTE_FLOW_ITEM_TYPE_IPV6_ROUTING_EXT:
8811 : : last_item = tunnel ?
8812 [ # # ]: 0 : MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT :
8813 : : MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT;
8814 : : break;
8815 : 0 : case RTE_FLOW_ITEM_TYPE_FLEX: {
8816 : 0 : enum rte_flow_item_flex_tunnel_mode tunnel_mode = FLEX_TUNNEL_MODE_SINGLE;
8817 : :
8818 : 0 : ret = mlx5_flex_get_tunnel_mode(item, &tunnel_mode);
8819 [ # # ]: 0 : if (ret < 0)
8820 : 0 : return rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_ITEM,
8821 : : item, "Unable to get flex item mode");
8822 [ # # ]: 0 : if (tunnel_mode == FLEX_TUNNEL_MODE_TUNNEL)
8823 : : last_item = MLX5_FLOW_ITEM_FLEX_TUNNEL;
8824 : : else
8825 : : last_item = tunnel ?
8826 [ # # ]: 0 : MLX5_FLOW_ITEM_INNER_FLEX :
8827 : : MLX5_FLOW_ITEM_OUTER_FLEX;
8828 : 0 : break;
8829 : : }
8830 : 0 : case RTE_FLOW_ITEM_TYPE_RANDOM:
8831 : : last_item = MLX5_FLOW_ITEM_RANDOM;
8832 : 0 : break;
8833 : 0 : case RTE_FLOW_ITEM_TYPE_NSH:
8834 : : last_item = MLX5_FLOW_ITEM_NSH;
8835 : : ret = mlx5_hw_validate_item_nsh(dev, item, error);
8836 [ # # ]: 0 : if (ret < 0)
8837 : 0 : return ret;
8838 : : break;
8839 : : case RTE_FLOW_ITEM_TYPE_INTEGRITY:
8840 : : /*
8841 : : * Integrity flow item validation require access to
8842 : : * both item mask and spec.
8843 : : * Current HWS model allows item mask in pattern
8844 : : * template and item spec in flow rule.
8845 : : */
8846 : : break;
8847 : 0 : case RTE_FLOW_ITEM_TYPE_ECPRI:
8848 : 0 : ret = mlx5_flow_validate_item_ecpri(dev, item, *item_flags, last_item,
8849 : : RTE_ETHER_TYPE_ECPRI,
8850 : : &hws_nic_ecpri_mask, error);
8851 [ # # ]: 0 : if (ret < 0)
8852 : 0 : return ret;
8853 : 0 : *item_flags |= MLX5_FLOW_LAYER_ECPRI;
8854 : 0 : break;
8855 : : case RTE_FLOW_ITEM_TYPE_IB_BTH:
8856 : : case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
8857 : : case RTE_FLOW_ITEM_TYPE_VOID:
8858 : : case RTE_FLOW_ITEM_TYPE_END:
8859 : : break;
8860 : 0 : default:
8861 : 0 : return rte_flow_error_set(error, EINVAL,
8862 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8863 : : NULL,
8864 : : "Unsupported item type");
8865 : : }
8866 : 0 : *item_flags |= last_item;
8867 : : }
8868 : 0 : return 1 + RTE_PTR_DIFF(item, items) / sizeof(item[0]);
8869 : : }
8870 : :
8871 : : static int
8872 : 0 : flow_hw_pattern_validate(struct rte_eth_dev *dev,
8873 : : const struct rte_flow_pattern_template_attr *attr,
8874 : : const struct rte_flow_item items[],
8875 : : uint64_t *item_flags,
8876 : : struct rte_flow_error *error)
8877 : : {
8878 : 0 : return __flow_hw_pattern_validate(dev, attr, items, item_flags, false, error);
8879 : : }
8880 : :
8881 : : /*
8882 : : * Verify that the tested flow patterns fits STE size limit in HWS group.
8883 : : *
8884 : : *
8885 : : * Return values:
8886 : : * 0 : Tested patterns fit STE size limit
8887 : : * -EINVAL : Invalid parameters detected
8888 : : * -E2BIG : Tested patterns exceed STE size limit
8889 : : */
8890 : : static int
8891 : 0 : pattern_template_validate(struct rte_eth_dev *dev,
8892 : : struct rte_flow_pattern_template *pt[],
8893 : : uint32_t pt_num,
8894 : : struct rte_flow_error *error)
8895 : : {
8896 : 0 : struct mlx5_flow_template_table_cfg tbl_cfg = {
8897 : : .attr = {
8898 : : .nb_flows = 64,
8899 : : .insertion_type = RTE_FLOW_TABLE_INSERTION_TYPE_PATTERN,
8900 : : .hash_func = RTE_FLOW_TABLE_HASH_FUNC_DEFAULT,
8901 : : .flow_attr = {
8902 : : .group = 1,
8903 : 0 : .ingress = pt[0]->attr.ingress,
8904 : 0 : .egress = pt[0]->attr.egress,
8905 : 0 : .transfer = pt[0]->attr.transfer
8906 : : }
8907 : : }
8908 : : };
8909 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
8910 : : struct rte_flow_actions_template *action_template;
8911 : : struct rte_flow_template_table *tmpl_tbl;
8912 : : int ret;
8913 : :
8914 [ # # ]: 0 : if (pt[0]->attr.ingress) {
8915 : 0 : action_template =
8916 : 0 : priv->action_template_drop[MLX5DR_TABLE_TYPE_NIC_RX];
8917 [ # # ]: 0 : } else if (pt[0]->attr.egress) {
8918 : 0 : action_template =
8919 : 0 : priv->action_template_drop[MLX5DR_TABLE_TYPE_NIC_TX];
8920 [ # # ]: 0 : } else if (pt[0]->attr.transfer) {
8921 : 0 : action_template =
8922 : 0 : priv->action_template_drop[MLX5DR_TABLE_TYPE_FDB];
8923 : : } else {
8924 : : ret = EINVAL;
8925 : 0 : goto end;
8926 : : }
8927 : :
8928 [ # # ]: 0 : if (pt[0]->item_flags & MLX5_FLOW_ITEM_COMPARE)
8929 : 0 : tbl_cfg.attr.nb_flows = 1;
8930 : 0 : tmpl_tbl = flow_hw_table_create(dev, &tbl_cfg, pt, pt_num,
8931 : : &action_template, 1, error);
8932 [ # # ]: 0 : if (tmpl_tbl) {
8933 : : ret = 0;
8934 : 0 : flow_hw_table_destroy(dev, tmpl_tbl, error);
8935 : : } else {
8936 [ # # # ]: 0 : switch (rte_errno) {
8937 : : case E2BIG:
8938 : : ret = E2BIG;
8939 : : break;
8940 : : case ENOTSUP:
8941 : : ret = EINVAL;
8942 : : break;
8943 : : default:
8944 : : ret = 0;
8945 : : break;
8946 : : }
8947 : : }
8948 : : end:
8949 : : if (ret)
8950 : 0 : rte_flow_error_set(error, ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8951 : : NULL, "failed to validate pattern template");
8952 : 0 : return -ret;
8953 : : }
8954 : :
8955 : : /**
8956 : : * Create flow item template.
8957 : : *
8958 : : * @param[in] dev
8959 : : * Pointer to the rte_eth_dev structure.
8960 : : * @param[in] attr
8961 : : * Pointer to the item template attributes.
8962 : : * @param[in] items
8963 : : * The template item pattern.
8964 : : * @param[out] error
8965 : : * Pointer to error structure.
8966 : : *
8967 : : * @return
8968 : : * Item template pointer on success, NULL otherwise and rte_errno is set.
8969 : : */
8970 : : static struct rte_flow_pattern_template *
8971 : 0 : flow_hw_pattern_template_create(struct rte_eth_dev *dev,
8972 : : const struct rte_flow_pattern_template_attr *attr,
8973 : : const struct rte_flow_item items[],
8974 : : struct rte_flow_error *error)
8975 : : {
8976 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
8977 : : struct rte_flow_pattern_template *it;
8978 : : struct rte_flow_item *copied_items = NULL;
8979 : : const struct rte_flow_item *tmpl_items;
8980 : 0 : uint64_t orig_item_nb, item_flags = 0;
8981 : 0 : struct rte_flow_item port = {
8982 : : .type = RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT,
8983 : : .mask = &rte_flow_item_ethdev_mask,
8984 : : };
8985 : 0 : struct rte_flow_item_tag tag_v = {
8986 : : .data = 0,
8987 : : .index = REG_C_0,
8988 : : };
8989 : 0 : struct rte_flow_item_tag tag_m = {
8990 : : .data = flow_hw_tx_tag_regc_mask(dev),
8991 : : .index = 0xff,
8992 : : };
8993 : 0 : struct rte_flow_item tag = {
8994 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_TAG,
8995 : : .spec = &tag_v,
8996 : : .mask = &tag_m,
8997 : : .last = NULL
8998 : : };
8999 : : int it_items_size;
9000 : : unsigned int i = 0;
9001 : : int rc;
9002 : :
9003 : : /* Validate application items only */
9004 : : rc = flow_hw_pattern_validate(dev, attr, items, &item_flags, error);
9005 [ # # ]: 0 : if (rc < 0)
9006 : : return NULL;
9007 : 0 : orig_item_nb = rc;
9008 [ # # ]: 0 : if (priv->sh->config.dv_esw_en &&
9009 : : priv->sh->config.repr_matching &&
9010 [ # # ]: 0 : attr->ingress && !attr->egress && !attr->transfer) {
9011 : 0 : copied_items = flow_hw_prepend_item(items, orig_item_nb, &port, error);
9012 [ # # ]: 0 : if (!copied_items)
9013 : : return NULL;
9014 : : tmpl_items = copied_items;
9015 [ # # ]: 0 : } else if (priv->sh->config.dv_esw_en &&
9016 : : priv->sh->config.repr_matching &&
9017 [ # # ]: 0 : !attr->ingress && attr->egress && !attr->transfer) {
9018 [ # # ]: 0 : if (item_flags & MLX5_FLOW_ITEM_SQ) {
9019 : 0 : DRV_LOG(DEBUG, "Port %u omitting implicit REG_C_0 match for egress "
9020 : : "pattern template", dev->data->port_id);
9021 : : tmpl_items = items;
9022 : 0 : goto setup_pattern_template;
9023 : : }
9024 : 0 : copied_items = flow_hw_prepend_item(items, orig_item_nb, &tag, error);
9025 [ # # ]: 0 : if (!copied_items)
9026 : : return NULL;
9027 : : tmpl_items = copied_items;
9028 : : } else {
9029 : : tmpl_items = items;
9030 : : }
9031 : 0 : setup_pattern_template:
9032 : 0 : it = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*it), 0, SOCKET_ID_ANY);
9033 [ # # ]: 0 : if (!it) {
9034 : 0 : rte_flow_error_set(error, ENOMEM,
9035 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9036 : : NULL,
9037 : : "cannot allocate item template");
9038 : 0 : goto error;
9039 : : }
9040 : 0 : it->attr = *attr;
9041 : 0 : it->item_flags = item_flags;
9042 : 0 : it->orig_item_nb = orig_item_nb;
9043 : 0 : it_items_size = rte_flow_conv(RTE_FLOW_CONV_OP_PATTERN, NULL, 0, tmpl_items, error);
9044 [ # # ]: 0 : if (it_items_size <= 0) {
9045 : 0 : rte_flow_error_set(error, ENOMEM,
9046 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9047 : : NULL,
9048 : : "Failed to determine buffer size for pattern");
9049 : 0 : goto error;
9050 : : }
9051 : 0 : it_items_size = RTE_ALIGN(it_items_size, 16);
9052 : 0 : it->items = mlx5_malloc(MLX5_MEM_ZERO, it_items_size, 0, SOCKET_ID_ANY);
9053 [ # # ]: 0 : if (it->items == NULL) {
9054 : 0 : rte_flow_error_set(error, ENOMEM,
9055 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9056 : : NULL,
9057 : : "Cannot allocate memory for pattern");
9058 : 0 : goto error;
9059 : : }
9060 : 0 : rc = rte_flow_conv(RTE_FLOW_CONV_OP_PATTERN, it->items, it_items_size, tmpl_items, error);
9061 [ # # ]: 0 : if (rc <= 0) {
9062 : 0 : rte_flow_error_set(error, ENOMEM,
9063 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9064 : : NULL,
9065 : : "Failed to store pattern");
9066 : 0 : goto error;
9067 : : }
9068 : 0 : it->mt = mlx5dr_match_template_create(tmpl_items, attr->relaxed_matching);
9069 [ # # ]: 0 : if (!it->mt) {
9070 : 0 : rte_flow_error_set(error, rte_errno,
9071 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9072 : : NULL,
9073 : : "cannot create match template");
9074 : 0 : goto error;
9075 : : }
9076 [ # # ]: 0 : if (copied_items) {
9077 [ # # ]: 0 : if (attr->ingress)
9078 : 0 : it->implicit_port = true;
9079 [ # # ]: 0 : else if (attr->egress)
9080 : 0 : it->implicit_tag = true;
9081 : 0 : mlx5_free(copied_items);
9082 : : copied_items = NULL;
9083 : : }
9084 : : /* Either inner or outer, can't both. */
9085 [ # # ]: 0 : if (it->item_flags & (MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT |
9086 : : MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT)) {
9087 [ # # ]: 0 : if (((it->item_flags & MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT) &&
9088 [ # # ]: 0 : (it->item_flags & MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT)) ||
9089 : 0 : (mlx5_alloc_srh_flex_parser(dev))) {
9090 : 0 : rte_flow_error_set(error, rte_errno,
9091 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9092 : : "cannot create IPv6 routing extension support");
9093 : 0 : goto error;
9094 : : }
9095 : : }
9096 [ # # ]: 0 : if (it->item_flags & MLX5_FLOW_ITEM_FLEX) {
9097 [ # # ]: 0 : for (i = 0; items[i].type != RTE_FLOW_ITEM_TYPE_END; i++) {
9098 : 0 : const struct rte_flow_item_flex *spec = items[i].spec;
9099 : : struct rte_flow_item_flex_handle *handle;
9100 : :
9101 [ # # ]: 0 : if (items[i].type != RTE_FLOW_ITEM_TYPE_FLEX)
9102 : 0 : continue;
9103 : 0 : handle = spec->handle;
9104 [ # # ]: 0 : if (flow_hw_flex_item_acquire(dev, handle,
9105 : 0 : &it->flex_item)) {
9106 : 0 : rte_flow_error_set(error, EINVAL,
9107 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9108 : : NULL, "cannot create hw FLEX item");
9109 : 0 : goto error;
9110 : : }
9111 : : }
9112 : : }
9113 [ # # ]: 0 : if (it->item_flags & MLX5_FLOW_LAYER_GENEVE_OPT) {
9114 [ # # ]: 0 : for (i = 0; items[i].type != RTE_FLOW_ITEM_TYPE_END; i++) {
9115 : 0 : const struct rte_flow_item_geneve_opt *spec =
9116 : : items[i].spec;
9117 : :
9118 [ # # ]: 0 : if (items[i].type != RTE_FLOW_ITEM_TYPE_GENEVE_OPT)
9119 : 0 : continue;
9120 [ # # ]: 0 : if (mlx5_geneve_tlv_option_register(priv, spec,
9121 : 0 : &it->geneve_opt_mng)) {
9122 : 0 : rte_flow_error_set(error, EINVAL,
9123 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9124 : : NULL, "cannot register GENEVE TLV option");
9125 : 0 : goto error;
9126 : : }
9127 : : }
9128 : : }
9129 : 0 : rte_atomic_fetch_add_explicit(&it->refcnt, 1, rte_memory_order_relaxed);
9130 : 0 : rc = pattern_template_validate(dev, &it, 1, error);
9131 [ # # ]: 0 : if (rc)
9132 : 0 : goto error;
9133 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->flow_hw_itt, it, next);
9134 : 0 : return it;
9135 : 0 : error:
9136 [ # # ]: 0 : if (it) {
9137 [ # # ]: 0 : if (it->flex_item)
9138 : 0 : flow_hw_flex_item_release(dev, &it->flex_item);
9139 [ # # ]: 0 : if (it->geneve_opt_mng.nb_options)
9140 : 0 : mlx5_geneve_tlv_options_unregister(priv, &it->geneve_opt_mng);
9141 [ # # ]: 0 : if (it->mt)
9142 : 0 : claim_zero(mlx5dr_match_template_destroy(it->mt));
9143 : 0 : mlx5_free(it->items);
9144 : 0 : mlx5_free(it);
9145 : : }
9146 [ # # ]: 0 : if (copied_items)
9147 : 0 : mlx5_free(copied_items);
9148 : : return NULL;
9149 : : }
9150 : :
9151 : : /**
9152 : : * Destroy flow item template.
9153 : : *
9154 : : * @param[in] dev
9155 : : * Pointer to the rte_eth_dev structure.
9156 : : * @param[in] template
9157 : : * Pointer to the item template to be destroyed.
9158 : : * @param[out] error
9159 : : * Pointer to error structure.
9160 : : *
9161 : : * @return
9162 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
9163 : : */
9164 : : static int
9165 : 0 : flow_hw_pattern_template_destroy(struct rte_eth_dev *dev,
9166 : : struct rte_flow_pattern_template *template,
9167 : : struct rte_flow_error *error __rte_unused)
9168 : : {
9169 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
9170 : :
9171 [ # # ]: 0 : if (rte_atomic_load_explicit(&template->refcnt, rte_memory_order_relaxed) > 1) {
9172 : 0 : DRV_LOG(WARNING, "Item template %p is still in use.",
9173 : : (void *)template);
9174 : 0 : return rte_flow_error_set(error, EBUSY,
9175 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9176 : : NULL,
9177 : : "item template is in use");
9178 : : }
9179 [ # # ]: 0 : if (template->item_flags & (MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT |
9180 : : MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT))
9181 : 0 : mlx5_free_srh_flex_parser(dev);
9182 [ # # ]: 0 : LIST_REMOVE(template, next);
9183 : 0 : flow_hw_flex_item_release(dev, &template->flex_item);
9184 : 0 : mlx5_geneve_tlv_options_unregister(priv, &template->geneve_opt_mng);
9185 : 0 : claim_zero(mlx5dr_match_template_destroy(template->mt));
9186 : 0 : mlx5_free(template->items);
9187 : 0 : mlx5_free(template);
9188 : 0 : return 0;
9189 : : }
9190 : :
9191 : : /*
9192 : : * Get information about HWS pre-configurable resources.
9193 : : *
9194 : : * @param[in] dev
9195 : : * Pointer to the rte_eth_dev structure.
9196 : : * @param[out] port_info
9197 : : * Pointer to port information.
9198 : : * @param[out] queue_info
9199 : : * Pointer to queue information.
9200 : : * @param[out] error
9201 : : * Pointer to error structure.
9202 : : *
9203 : : * @return
9204 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
9205 : : */
9206 : : static int
9207 : 0 : flow_hw_info_get(struct rte_eth_dev *dev,
9208 : : struct rte_flow_port_info *port_info,
9209 : : struct rte_flow_queue_info *queue_info,
9210 : : struct rte_flow_error *error __rte_unused)
9211 : : {
9212 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
9213 : 0 : uint16_t port_id = dev->data->port_id;
9214 : : struct rte_mtr_capabilities mtr_cap;
9215 : : int ret;
9216 : :
9217 : : memset(port_info, 0, sizeof(*port_info));
9218 : : /* Queue size is unlimited from low-level. */
9219 : 0 : port_info->max_nb_queues = UINT32_MAX;
9220 : 0 : queue_info->max_size = UINT32_MAX;
9221 : :
9222 : : memset(&mtr_cap, 0, sizeof(struct rte_mtr_capabilities));
9223 : 0 : ret = rte_mtr_capabilities_get(port_id, &mtr_cap, NULL);
9224 [ # # ]: 0 : if (!ret)
9225 : 0 : port_info->max_nb_meters = mtr_cap.n_max;
9226 : 0 : port_info->max_nb_counters = priv->sh->hws_max_nb_counters;
9227 : 0 : port_info->max_nb_aging_objects = port_info->max_nb_counters;
9228 : 0 : return 0;
9229 : : }
9230 : :
9231 : : /**
9232 : : * Create group callback.
9233 : : *
9234 : : * @param[in] tool_ctx
9235 : : * Pointer to the hash list related context.
9236 : : * @param[in] cb_ctx
9237 : : * Pointer to the group creation context.
9238 : : *
9239 : : * @return
9240 : : * Group entry on success, NULL otherwise and rte_errno is set.
9241 : : */
9242 : : struct mlx5_list_entry *
9243 : 0 : flow_hw_grp_create_cb(void *tool_ctx, void *cb_ctx)
9244 : : {
9245 : : struct mlx5_dev_ctx_shared *sh = tool_ctx;
9246 : : struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9247 : 0 : struct rte_eth_dev *dev = ctx->dev;
9248 : 0 : struct rte_flow_attr *attr = (struct rte_flow_attr *)ctx->data;
9249 : 0 : uint32_t *specialize = (uint32_t *)ctx->data2;
9250 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
9251 : : bool unified_fdb = is_unified_fdb(priv);
9252 : 0 : struct mlx5dr_table_attr dr_tbl_attr = {0};
9253 : 0 : struct rte_flow_error *error = ctx->error;
9254 : : struct mlx5_flow_group *grp_data;
9255 : : struct mlx5dr_table *tbl = NULL;
9256 : : struct mlx5dr_action *jump;
9257 : : uint32_t hws_flags;
9258 : 0 : uint32_t idx = 0;
9259 [ # # # # : 0 : MKSTR(matcher_name, "%s_%s_%u_%u_matcher_list",
# # # # ]
9260 : : attr->transfer ? "FDB" : "NIC", attr->egress ? "egress" : "ingress",
9261 : : attr->group, idx);
9262 : :
9263 : 0 : grp_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_HW_GRP], &idx);
9264 [ # # ]: 0 : if (!grp_data) {
9265 : 0 : rte_flow_error_set(error, ENOMEM,
9266 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9267 : : NULL,
9268 : : "cannot allocate flow table data entry");
9269 : 0 : return NULL;
9270 : : }
9271 : 0 : dr_tbl_attr.level = attr->group;
9272 : 0 : dr_tbl_attr.type = get_mlx5dr_table_type(attr, *specialize, unified_fdb);
9273 : 0 : tbl = mlx5dr_table_create(priv->dr_ctx, &dr_tbl_attr);
9274 [ # # ]: 0 : if (!tbl)
9275 : 0 : goto error;
9276 : 0 : grp_data->tbl = tbl;
9277 [ # # ]: 0 : if (attr->group) {
9278 : 0 : hws_flags = mlx5_hw_act_dest_table_flag[dr_tbl_attr.type];
9279 : : /* For case of jump from FDB Tx to FDB Rx as it is supported now. */
9280 [ # # # # ]: 0 : if (priv->jump_fdb_rx_en &&
9281 : : dr_tbl_attr.type == MLX5DR_TABLE_TYPE_FDB_RX)
9282 : 0 : hws_flags |= MLX5DR_ACTION_FLAG_HWS_FDB_TX;
9283 : : /* Jump action be used by non-root table. */
9284 : 0 : jump = mlx5dr_action_create_dest_table
9285 : : (priv->dr_ctx, tbl,
9286 : : hws_flags);
9287 [ # # ]: 0 : if (!jump)
9288 : 0 : goto error;
9289 : 0 : grp_data->jump.hws_action = jump;
9290 : : /* Jump action be used by root table. */
9291 : 0 : jump = mlx5dr_action_create_dest_table
9292 : : (priv->dr_ctx, tbl,
9293 : : mlx5_hw_act_flag[MLX5_HW_ACTION_FLAG_ROOT]
9294 : 0 : [dr_tbl_attr.type]);
9295 [ # # ]: 0 : if (!jump)
9296 : 0 : goto error;
9297 : 0 : grp_data->jump.root_action = jump;
9298 : : }
9299 : :
9300 : 0 : grp_data->matchers = mlx5_list_create(matcher_name, sh, true,
9301 : : flow_matcher_create_cb,
9302 : : flow_matcher_match_cb,
9303 : : flow_matcher_remove_cb,
9304 : : flow_matcher_clone_cb,
9305 : : flow_matcher_clone_free_cb);
9306 : 0 : grp_data->dev = dev;
9307 : 0 : grp_data->idx = idx;
9308 : 0 : grp_data->group_id = attr->group;
9309 : 0 : grp_data->type = dr_tbl_attr.type;
9310 : 0 : return &grp_data->entry;
9311 : 0 : error:
9312 [ # # ]: 0 : if (grp_data->jump.root_action)
9313 : 0 : mlx5dr_action_destroy(grp_data->jump.root_action);
9314 [ # # ]: 0 : if (grp_data->jump.hws_action)
9315 : 0 : mlx5dr_action_destroy(grp_data->jump.hws_action);
9316 [ # # ]: 0 : if (tbl)
9317 : 0 : mlx5dr_table_destroy(tbl);
9318 [ # # ]: 0 : if (idx)
9319 : 0 : mlx5_ipool_free(sh->ipool[MLX5_IPOOL_HW_GRP], idx);
9320 : 0 : rte_flow_error_set(error, ENOMEM,
9321 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9322 : : NULL,
9323 : : "cannot allocate flow dr table");
9324 : 0 : return NULL;
9325 : : }
9326 : :
9327 : : /**
9328 : : * Remove group callback.
9329 : : *
9330 : : * @param[in] tool_ctx
9331 : : * Pointer to the hash list related context.
9332 : : * @param[in] entry
9333 : : * Pointer to the entry to be removed.
9334 : : */
9335 : : void
9336 : 0 : flow_hw_grp_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
9337 : : {
9338 : : struct mlx5_dev_ctx_shared *sh = tool_ctx;
9339 : : struct mlx5_flow_group *grp_data =
9340 : : container_of(entry, struct mlx5_flow_group, entry);
9341 : :
9342 : : MLX5_ASSERT(entry && sh);
9343 : : /* To use the wrapper glue functions instead. */
9344 [ # # ]: 0 : if (grp_data->jump.hws_action)
9345 : 0 : mlx5dr_action_destroy(grp_data->jump.hws_action);
9346 [ # # ]: 0 : if (grp_data->jump.root_action)
9347 : 0 : mlx5dr_action_destroy(grp_data->jump.root_action);
9348 : 0 : mlx5_list_destroy(grp_data->matchers);
9349 : 0 : mlx5dr_table_destroy(grp_data->tbl);
9350 : 0 : mlx5_ipool_free(sh->ipool[MLX5_IPOOL_HW_GRP], grp_data->idx);
9351 : 0 : }
9352 : :
9353 : : /**
9354 : : * Match group callback.
9355 : : *
9356 : : * @param[in] tool_ctx
9357 : : * Pointer to the hash list related context.
9358 : : * @param[in] entry
9359 : : * Pointer to the group to be matched.
9360 : : * @param[in] cb_ctx
9361 : : * Pointer to the group matching context.
9362 : : *
9363 : : * @return
9364 : : * 0 on matched, 1 on miss matched.
9365 : : */
9366 : : int
9367 : 0 : flow_hw_grp_match_cb(void *tool_ctx __rte_unused, struct mlx5_list_entry *entry,
9368 : : void *cb_ctx)
9369 : : {
9370 : : struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9371 : : struct mlx5_flow_group *grp_data =
9372 : : container_of(entry, struct mlx5_flow_group, entry);
9373 : 0 : struct rte_flow_attr *attr =
9374 : : (struct rte_flow_attr *)ctx->data;
9375 : :
9376 : 0 : return (grp_data->dev != ctx->dev) ||
9377 [ # # ]: 0 : (grp_data->group_id != attr->group) ||
9378 [ # # # # ]: 0 : ((grp_data->type < MLX5DR_TABLE_TYPE_FDB) &&
9379 [ # # ]: 0 : attr->transfer) ||
9380 [ # # ]: 0 : ((grp_data->type != MLX5DR_TABLE_TYPE_NIC_TX) &&
9381 [ # # # # ]: 0 : attr->egress) ||
9382 [ # # ]: 0 : ((grp_data->type != MLX5DR_TABLE_TYPE_NIC_RX) &&
9383 : : attr->ingress);
9384 : : }
9385 : :
9386 : : /**
9387 : : * Clone group entry callback.
9388 : : *
9389 : : * @param[in] tool_ctx
9390 : : * Pointer to the hash list related context.
9391 : : * @param[in] entry
9392 : : * Pointer to the group to be matched.
9393 : : * @param[in] cb_ctx
9394 : : * Pointer to the group matching context.
9395 : : *
9396 : : * @return
9397 : : * 0 on matched, 1 on miss matched.
9398 : : */
9399 : : struct mlx5_list_entry *
9400 : 0 : flow_hw_grp_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
9401 : : void *cb_ctx)
9402 : : {
9403 : : struct mlx5_dev_ctx_shared *sh = tool_ctx;
9404 : : struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9405 : : struct mlx5_flow_group *grp_data;
9406 : 0 : struct rte_flow_error *error = ctx->error;
9407 : 0 : uint32_t idx = 0;
9408 : :
9409 : 0 : grp_data = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_HW_GRP], &idx);
9410 [ # # ]: 0 : if (!grp_data) {
9411 : 0 : rte_flow_error_set(error, ENOMEM,
9412 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9413 : : NULL,
9414 : : "cannot allocate flow table data entry");
9415 : 0 : return NULL;
9416 : : }
9417 : : memcpy(grp_data, oentry, sizeof(*grp_data));
9418 : 0 : grp_data->idx = idx;
9419 : 0 : return &grp_data->entry;
9420 : : }
9421 : :
9422 : : /**
9423 : : * Free cloned group entry callback.
9424 : : *
9425 : : * @param[in] tool_ctx
9426 : : * Pointer to the hash list related context.
9427 : : * @param[in] entry
9428 : : * Pointer to the group to be freed.
9429 : : */
9430 : : void
9431 : 0 : flow_hw_grp_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
9432 : : {
9433 : : struct mlx5_dev_ctx_shared *sh = tool_ctx;
9434 : : struct mlx5_flow_group *grp_data =
9435 : : container_of(entry, struct mlx5_flow_group, entry);
9436 : :
9437 : 0 : mlx5_ipool_free(sh->ipool[MLX5_IPOOL_HW_GRP], grp_data->idx);
9438 : 0 : }
9439 : :
9440 : : /**
9441 : : * Create and cache a vport action for given @p dev port. vport actions
9442 : : * cache is used in HWS with FDB flows.
9443 : : *
9444 : : * This function does not create any function if proxy port for @p dev port
9445 : : * was not configured for HW Steering.
9446 : : *
9447 : : * This function assumes that E-Switch is enabled and PMD is running with
9448 : : * HW Steering configured.
9449 : : *
9450 : : * @param dev
9451 : : * Pointer to Ethernet device which will be the action destination.
9452 : : *
9453 : : * @return
9454 : : * 0 on success, positive value otherwise.
9455 : : */
9456 : : int
9457 : 0 : flow_hw_create_vport_action(struct rte_eth_dev *dev)
9458 : : {
9459 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
9460 : : struct rte_eth_dev *proxy_dev;
9461 : : struct mlx5_priv *proxy_priv;
9462 : 0 : uint16_t port_id = dev->data->port_id;
9463 : 0 : uint16_t proxy_port_id = port_id;
9464 : : int ret;
9465 : :
9466 : 0 : ret = mlx5_flow_pick_transfer_proxy(dev, &proxy_port_id, NULL);
9467 [ # # ]: 0 : if (ret)
9468 : : return ret;
9469 : 0 : proxy_dev = &rte_eth_devices[proxy_port_id];
9470 : 0 : proxy_priv = proxy_dev->data->dev_private;
9471 [ # # ]: 0 : if (!proxy_priv->hw_vport)
9472 : : return 0;
9473 [ # # ]: 0 : if (proxy_priv->hw_vport[port_id]) {
9474 : 0 : DRV_LOG(ERR, "port %u HWS vport action already created",
9475 : : port_id);
9476 : 0 : return -EINVAL;
9477 : : }
9478 [ # # ]: 0 : proxy_priv->hw_vport[port_id] = mlx5dr_action_create_dest_vport
9479 : : (proxy_priv->dr_ctx, priv->dev_port,
9480 : : is_unified_fdb(priv) ?
9481 : : (MLX5DR_ACTION_FLAG_HWS_FDB_RX |
9482 : : MLX5DR_ACTION_FLAG_HWS_FDB_TX |
9483 : : MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED) :
9484 : : MLX5DR_ACTION_FLAG_HWS_FDB);
9485 [ # # ]: 0 : if (!proxy_priv->hw_vport[port_id]) {
9486 : 0 : DRV_LOG(ERR, "port %u unable to create HWS vport action",
9487 : : port_id);
9488 : 0 : return -EINVAL;
9489 : : }
9490 : : return 0;
9491 : : }
9492 : :
9493 : : /**
9494 : : * Destroys the vport action associated with @p dev device
9495 : : * from actions' cache.
9496 : : *
9497 : : * This function does not destroy any action if there is no action cached
9498 : : * for @p dev or proxy port was not configured for HW Steering.
9499 : : *
9500 : : * This function assumes that E-Switch is enabled and PMD is running with
9501 : : * HW Steering configured.
9502 : : *
9503 : : * @param dev
9504 : : * Pointer to Ethernet device which will be the action destination.
9505 : : */
9506 : : void
9507 : 0 : flow_hw_destroy_vport_action(struct rte_eth_dev *dev)
9508 : : {
9509 : : struct rte_eth_dev *proxy_dev;
9510 : : struct mlx5_priv *proxy_priv;
9511 : 0 : uint16_t port_id = dev->data->port_id;
9512 : 0 : uint16_t proxy_port_id = port_id;
9513 : :
9514 [ # # ]: 0 : if (mlx5_flow_pick_transfer_proxy(dev, &proxy_port_id, NULL))
9515 : 0 : return;
9516 : 0 : proxy_dev = &rte_eth_devices[proxy_port_id];
9517 : 0 : proxy_priv = proxy_dev->data->dev_private;
9518 [ # # # # ]: 0 : if (!proxy_priv->hw_vport || !proxy_priv->hw_vport[port_id])
9519 : : return;
9520 : 0 : mlx5dr_action_destroy(proxy_priv->hw_vport[port_id]);
9521 : 0 : proxy_priv->hw_vport[port_id] = NULL;
9522 : : }
9523 : :
9524 : : static int
9525 : 0 : flow_hw_create_vport_actions(struct mlx5_priv *priv)
9526 : : {
9527 : : uint16_t port_id;
9528 : :
9529 : : MLX5_ASSERT(!priv->hw_vport);
9530 : : bool unified_fdb = is_unified_fdb(priv);
9531 : 0 : priv->hw_vport = mlx5_malloc(MLX5_MEM_ZERO,
9532 : : sizeof(*priv->hw_vport) * RTE_MAX_ETHPORTS,
9533 : : 0, SOCKET_ID_ANY);
9534 [ # # ]: 0 : if (!priv->hw_vport)
9535 : : return -ENOMEM;
9536 : 0 : DRV_LOG(DEBUG, "port %u :: creating vport actions", priv->dev_data->port_id);
9537 : 0 : DRV_LOG(DEBUG, "port %u :: domain_id=%u", priv->dev_data->port_id, priv->domain_id);
9538 [ # # ]: 0 : MLX5_ETH_FOREACH_DEV(port_id, NULL) {
9539 : 0 : struct mlx5_priv *port_priv = rte_eth_devices[port_id].data->dev_private;
9540 : :
9541 [ # # ]: 0 : if (!port_priv ||
9542 [ # # ]: 0 : port_priv->domain_id != priv->domain_id)
9543 : 0 : continue;
9544 : 0 : DRV_LOG(DEBUG, "port %u :: for port_id=%u, calling mlx5dr_action_create_dest_vport() with ibport=%u",
9545 : : priv->dev_data->port_id, port_id, port_priv->dev_port);
9546 [ # # ]: 0 : priv->hw_vport[port_id] = mlx5dr_action_create_dest_vport
9547 : : (priv->dr_ctx, port_priv->dev_port,
9548 : : unified_fdb ?
9549 : : (MLX5DR_ACTION_FLAG_HWS_FDB_RX |
9550 : : MLX5DR_ACTION_FLAG_HWS_FDB_TX |
9551 : : MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED) :
9552 : : MLX5DR_ACTION_FLAG_HWS_FDB);
9553 : 0 : DRV_LOG(DEBUG, "port %u :: priv->hw_vport[%u]=%p",
9554 : : priv->dev_data->port_id, port_id, (void *)priv->hw_vport[port_id]);
9555 [ # # ]: 0 : if (!priv->hw_vport[port_id])
9556 : : return -EINVAL;
9557 : : }
9558 : : return 0;
9559 : : }
9560 : :
9561 : : static void
9562 : 0 : flow_hw_free_vport_actions(struct mlx5_priv *priv)
9563 : : {
9564 : : uint16_t port_id;
9565 : :
9566 [ # # ]: 0 : if (!priv->hw_vport)
9567 : : return;
9568 [ # # ]: 0 : for (port_id = 0; port_id < RTE_MAX_ETHPORTS; ++port_id)
9569 [ # # ]: 0 : if (priv->hw_vport[port_id])
9570 : 0 : mlx5dr_action_destroy(priv->hw_vport[port_id]);
9571 : 0 : mlx5_free(priv->hw_vport);
9572 : 0 : priv->hw_vport = NULL;
9573 : : }
9574 : :
9575 : : #ifdef HAVE_MLX5DV_DR_ACTION_CREATE_DEST_ROOT_TABLE
9576 : : static __rte_always_inline void
9577 : : _create_send_to_kernel_actions(struct mlx5_priv *priv, int type)
9578 : : {
9579 : : int action_flag;
9580 : :
9581 : : action_flag = mlx5_hw_act_flag[1][type];
9582 : : priv->hw_send_to_kernel[type] =
9583 : : mlx5dr_action_create_dest_root(priv->dr_ctx,
9584 : : MLX5_HW_LOWEST_PRIO_ROOT,
9585 : : action_flag);
9586 : : if (!priv->hw_send_to_kernel[type])
9587 : : DRV_LOG(WARNING, "Unable to create HWS send to kernel action");
9588 : : }
9589 : : #endif
9590 : :
9591 : : static void
9592 : : flow_hw_create_send_to_kernel_actions(__rte_unused struct mlx5_priv *priv,
9593 : : __rte_unused bool is_proxy)
9594 : : {
9595 : : #ifdef HAVE_MLX5DV_DR_ACTION_CREATE_DEST_ROOT_TABLE
9596 : : int i, from, to;
9597 : : bool unified_fdb = is_unified_fdb(priv);
9598 : :
9599 : : for (i = MLX5DR_TABLE_TYPE_NIC_RX; i <= MLX5DR_TABLE_TYPE_NIC_TX; i++)
9600 : : _create_send_to_kernel_actions(priv, i);
9601 : :
9602 : : if (is_proxy) {
9603 : : from = unified_fdb ? MLX5DR_TABLE_TYPE_FDB_RX : MLX5DR_TABLE_TYPE_FDB;
9604 : : to = unified_fdb ? MLX5DR_TABLE_TYPE_FDB_UNIFIED : MLX5DR_TABLE_TYPE_FDB;
9605 : : for (i = from; i <= to; i++)
9606 : : _create_send_to_kernel_actions(priv, i);
9607 : : }
9608 : : #endif
9609 : : }
9610 : :
9611 : : static void
9612 : 0 : flow_hw_destroy_send_to_kernel_action(struct mlx5_priv *priv)
9613 : : {
9614 : : int i;
9615 : :
9616 [ # # ]: 0 : for (i = MLX5DR_TABLE_TYPE_NIC_RX; i < MLX5DR_TABLE_TYPE_MAX; i++) {
9617 [ # # ]: 0 : if (priv->hw_send_to_kernel[i]) {
9618 : 0 : mlx5dr_action_destroy(priv->hw_send_to_kernel[i]);
9619 : 0 : priv->hw_send_to_kernel[i] = NULL;
9620 : : }
9621 : : }
9622 : 0 : }
9623 : :
9624 : : static bool
9625 : : flow_hw_should_create_nat64_actions(struct mlx5_priv *priv)
9626 : : {
9627 : : int i;
9628 : :
9629 : : /* Check if all registers are available. */
9630 [ # # ]: 0 : for (i = 0; i < MLX5_FLOW_NAT64_REGS_MAX; ++i)
9631 [ # # ]: 0 : if (priv->sh->registers.nat64_regs[i] == REG_NON)
9632 : : return false;
9633 : :
9634 : : return true;
9635 : : }
9636 : :
9637 : : static void
9638 : 0 : flow_hw_destroy_nat64_actions(struct mlx5_priv *priv)
9639 : : {
9640 : : uint32_t i;
9641 : :
9642 [ # # ]: 0 : for (i = MLX5DR_TABLE_TYPE_NIC_RX; i < MLX5DR_TABLE_TYPE_MAX; i++) {
9643 [ # # ]: 0 : if (priv->action_nat64[i][RTE_FLOW_NAT64_6TO4]) {
9644 : 0 : (void)mlx5dr_action_destroy(priv->action_nat64[i][RTE_FLOW_NAT64_6TO4]);
9645 : 0 : priv->action_nat64[i][RTE_FLOW_NAT64_6TO4] = NULL;
9646 : : }
9647 [ # # ]: 0 : if (priv->action_nat64[i][RTE_FLOW_NAT64_4TO6]) {
9648 : 0 : (void)mlx5dr_action_destroy(priv->action_nat64[i][RTE_FLOW_NAT64_4TO6]);
9649 : 0 : priv->action_nat64[i][RTE_FLOW_NAT64_4TO6] = NULL;
9650 : : }
9651 : : }
9652 : 0 : }
9653 : :
9654 : : static int
9655 : 0 : _create_nat64_actions(struct mlx5_priv *priv,
9656 : : struct mlx5dr_action_nat64_attr *attr,
9657 : : int type,
9658 : : struct rte_flow_error *error)
9659 : : {
9660 : 0 : const uint32_t flags[MLX5DR_TABLE_TYPE_MAX] = {
9661 : : MLX5DR_ACTION_FLAG_HWS_RX | MLX5DR_ACTION_FLAG_SHARED,
9662 : : MLX5DR_ACTION_FLAG_HWS_TX | MLX5DR_ACTION_FLAG_SHARED,
9663 : : MLX5DR_ACTION_FLAG_HWS_FDB | MLX5DR_ACTION_FLAG_SHARED,
9664 : : MLX5DR_ACTION_FLAG_HWS_FDB_RX | MLX5DR_ACTION_FLAG_SHARED,
9665 : : MLX5DR_ACTION_FLAG_HWS_FDB_TX | MLX5DR_ACTION_FLAG_SHARED,
9666 : : MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED | MLX5DR_ACTION_FLAG_SHARED,
9667 : : };
9668 : : struct mlx5dr_action *act;
9669 : :
9670 : 0 : attr->flags = (enum mlx5dr_action_nat64_flags)
9671 : : (MLX5DR_ACTION_NAT64_V6_TO_V4 | MLX5DR_ACTION_NAT64_BACKUP_ADDR);
9672 : 0 : act = mlx5dr_action_create_nat64(priv->dr_ctx, attr, flags[type]);
9673 [ # # ]: 0 : if (!act)
9674 : 0 : return rte_flow_error_set(error, rte_errno,
9675 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9676 : : "Failed to create v6 to v4 action.");
9677 : 0 : priv->action_nat64[type][RTE_FLOW_NAT64_6TO4] = act;
9678 : 0 : attr->flags = (enum mlx5dr_action_nat64_flags)
9679 : : (MLX5DR_ACTION_NAT64_V4_TO_V6 | MLX5DR_ACTION_NAT64_BACKUP_ADDR);
9680 : 0 : act = mlx5dr_action_create_nat64(priv->dr_ctx, attr, flags[type]);
9681 [ # # ]: 0 : if (!act)
9682 : 0 : return rte_flow_error_set(error, rte_errno,
9683 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9684 : : "Failed to create v4 to v6 action.");
9685 : 0 : priv->action_nat64[type][RTE_FLOW_NAT64_4TO6] = act;
9686 : 0 : return 0;
9687 : : }
9688 : :
9689 : : static int
9690 : 0 : flow_hw_create_nat64_actions(struct mlx5_priv *priv, struct rte_flow_error *error)
9691 : : {
9692 : : struct mlx5dr_action_nat64_attr attr;
9693 : : uint8_t regs[MLX5_FLOW_NAT64_REGS_MAX];
9694 : : uint32_t i, from, to;
9695 : : int rc;
9696 : : bool unified_fdb = is_unified_fdb(priv);
9697 : :
9698 : 0 : attr.registers = regs;
9699 : : /* Try to use 3 registers by default. */
9700 : 0 : attr.num_of_registers = MLX5_FLOW_NAT64_REGS_MAX;
9701 [ # # ]: 0 : for (i = 0; i < MLX5_FLOW_NAT64_REGS_MAX; i++) {
9702 : : MLX5_ASSERT(priv->sh->registers.nat64_regs[i] != REG_NON);
9703 : 0 : regs[i] = mlx5_convert_reg_to_field(priv->sh->registers.nat64_regs[i]);
9704 : : }
9705 [ # # ]: 0 : for (i = MLX5DR_TABLE_TYPE_NIC_RX; i <= MLX5DR_TABLE_TYPE_NIC_TX; i++) {
9706 : 0 : rc = _create_nat64_actions(priv, &attr, i, error);
9707 [ # # ]: 0 : if (rc)
9708 : 0 : return rc;
9709 : : }
9710 [ # # ]: 0 : if (priv->sh->config.dv_esw_en) {
9711 [ # # ]: 0 : from = unified_fdb ? MLX5DR_TABLE_TYPE_FDB_RX :
9712 : : MLX5DR_TABLE_TYPE_FDB;
9713 [ # # ]: 0 : to = unified_fdb ? MLX5DR_TABLE_TYPE_FDB_UNIFIED :
9714 : : MLX5DR_TABLE_TYPE_FDB;
9715 : :
9716 [ # # ]: 0 : for (i = from; i <= to; i++) {
9717 : 0 : rc = _create_nat64_actions(priv, &attr, i, error);
9718 [ # # ]: 0 : if (rc)
9719 : 0 : return rc;
9720 : : }
9721 : : }
9722 : : return 0;
9723 : : }
9724 : :
9725 : : /**
9726 : : * Create an egress pattern template matching on source SQ.
9727 : : *
9728 : : * @param dev
9729 : : * Pointer to Ethernet device.
9730 : : * @param[out] error
9731 : : * Pointer to error structure.
9732 : : *
9733 : : * @return
9734 : : * Pointer to pattern template on success. NULL otherwise, and rte_errno is set.
9735 : : */
9736 : : static struct rte_flow_pattern_template *
9737 : 0 : flow_hw_create_tx_repr_sq_pattern_tmpl(struct rte_eth_dev *dev, struct rte_flow_error *error)
9738 : : {
9739 : 0 : struct rte_flow_pattern_template_attr attr = {
9740 : : .relaxed_matching = 0,
9741 : : .egress = 1,
9742 : : };
9743 : 0 : struct mlx5_rte_flow_item_sq sq_mask = {
9744 : : .queue = UINT32_MAX,
9745 : : };
9746 : 0 : struct rte_flow_item items[] = {
9747 : : {
9748 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_SQ,
9749 : : .mask = &sq_mask,
9750 : : },
9751 : : {
9752 : : .type = RTE_FLOW_ITEM_TYPE_END,
9753 : : },
9754 : : };
9755 : :
9756 : 0 : return flow_hw_pattern_template_create(dev, &attr, items, error);
9757 : : }
9758 : :
9759 : : static __rte_always_inline uint32_t
9760 : : flow_hw_tx_tag_regc_mask(struct rte_eth_dev *dev)
9761 : : {
9762 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
9763 : 0 : uint32_t mask = priv->sh->dv_regc0_mask;
9764 : :
9765 : : /* Mask is verified during device initialization. Sanity checking here. */
9766 : : MLX5_ASSERT(mask != 0);
9767 : : /*
9768 : : * Availability of sufficient number of bits in REG_C_0 is verified on initialization.
9769 : : * Sanity checking here.
9770 : : */
9771 : : MLX5_ASSERT(rte_popcount32(mask) >= rte_popcount32(priv->vport_meta_mask));
9772 : : return mask;
9773 : : }
9774 : :
9775 : : static __rte_always_inline uint32_t
9776 : : flow_hw_tx_tag_regc_value(struct rte_eth_dev *dev)
9777 : : {
9778 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
9779 : : uint32_t tag;
9780 : :
9781 : : /* Mask is verified during device initialization. Sanity checking here. */
9782 : : MLX5_ASSERT(priv->vport_meta_mask != 0);
9783 [ # # ]: 0 : tag = priv->vport_meta_tag >> (rte_bsf32(priv->vport_meta_mask));
9784 : : /*
9785 : : * Availability of sufficient number of bits in REG_C_0 is verified on initialization.
9786 : : * Sanity checking here.
9787 : : */
9788 : : MLX5_ASSERT((tag & priv->sh->dv_regc0_mask) == tag);
9789 : : return tag;
9790 : : }
9791 : :
9792 : : static void
9793 : : flow_hw_update_action_mask(struct rte_flow_action *action,
9794 : : struct rte_flow_action *mask,
9795 : : enum rte_flow_action_type type,
9796 : : void *conf_v,
9797 : : void *conf_m)
9798 : : {
9799 : 0 : action->type = type;
9800 : 0 : action->conf = conf_v;
9801 : 0 : mask->type = type;
9802 : 0 : mask->conf = conf_m;
9803 : : }
9804 : :
9805 : : /**
9806 : : * Create an egress actions template with MODIFY_FIELD action for setting unused REG_C_0 bits
9807 : : * to vport tag and JUMP action to group 1.
9808 : : *
9809 : : * If extended metadata mode is enabled, then MODIFY_FIELD action for copying software metadata
9810 : : * to REG_C_1 is added as well.
9811 : : *
9812 : : * @param dev
9813 : : * Pointer to Ethernet device.
9814 : : * @param[out] error
9815 : : * Pointer to error structure.
9816 : : *
9817 : : * @return
9818 : : * Pointer to actions template on success. NULL otherwise, and rte_errno is set.
9819 : : */
9820 : : static struct rte_flow_actions_template *
9821 : 0 : flow_hw_create_tx_repr_tag_jump_acts_tmpl(struct rte_eth_dev *dev,
9822 : : struct rte_flow_error *error)
9823 : : {
9824 [ # # ]: 0 : uint32_t tag_mask = flow_hw_tx_tag_regc_mask(dev);
9825 : 0 : uint32_t tag_value = flow_hw_tx_tag_regc_value(dev);
9826 : 0 : struct rte_flow_actions_template_attr attr = {
9827 : : .egress = 1,
9828 : : };
9829 [ # # ]: 0 : struct rte_flow_action_modify_field set_tag_v = {
9830 : : .operation = RTE_FLOW_MODIFY_SET,
9831 : : .dst = {
9832 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
9833 : : .tag_index = REG_C_0,
9834 : : .offset = rte_bsf32(tag_mask),
9835 : : },
9836 : : .src = {
9837 : : .field = RTE_FLOW_FIELD_VALUE,
9838 : : },
9839 : : .width = rte_popcount32(tag_mask),
9840 : : };
9841 : 0 : struct rte_flow_action_modify_field set_tag_m = {
9842 : : .operation = RTE_FLOW_MODIFY_SET,
9843 : : .dst = {
9844 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
9845 : : .level = UINT8_MAX,
9846 : : .tag_index = UINT8_MAX,
9847 : : .offset = UINT32_MAX,
9848 : : },
9849 : : .src = {
9850 : : .field = RTE_FLOW_FIELD_VALUE,
9851 : : },
9852 : : .width = UINT32_MAX,
9853 : : };
9854 : 0 : struct rte_flow_action_modify_field copy_metadata_v = {
9855 : : .operation = RTE_FLOW_MODIFY_SET,
9856 : : .dst = {
9857 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
9858 : : .tag_index = REG_C_1,
9859 : : },
9860 : : .src = {
9861 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
9862 : : .tag_index = REG_A,
9863 : : },
9864 : : .width = 32,
9865 : : };
9866 : 0 : struct rte_flow_action_modify_field copy_metadata_m = {
9867 : : .operation = RTE_FLOW_MODIFY_SET,
9868 : : .dst = {
9869 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
9870 : : .level = UINT8_MAX,
9871 : : .tag_index = UINT8_MAX,
9872 : : .offset = UINT32_MAX,
9873 : : },
9874 : : .src = {
9875 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
9876 : : .level = UINT8_MAX,
9877 : : .tag_index = UINT8_MAX,
9878 : : .offset = UINT32_MAX,
9879 : : },
9880 : : .width = UINT32_MAX,
9881 : : };
9882 : 0 : struct rte_flow_action_jump jump_v = {
9883 : : .group = MLX5_HW_LOWEST_USABLE_GROUP,
9884 : : };
9885 : 0 : struct rte_flow_action_jump jump_m = {
9886 : : .group = UINT32_MAX,
9887 : : };
9888 : 0 : struct rte_flow_action actions_v[4] = { { 0 } };
9889 [ # # ]: 0 : struct rte_flow_action actions_m[4] = { { 0 } };
9890 : : unsigned int idx = 0;
9891 : :
9892 : : rte_memcpy(set_tag_v.src.value, &tag_value, sizeof(tag_value));
9893 : : rte_memcpy(set_tag_m.src.value, &tag_mask, sizeof(tag_mask));
9894 : : flow_hw_update_action_mask(&actions_v[idx], &actions_m[idx],
9895 : : RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
9896 : : &set_tag_v, &set_tag_m);
9897 : : idx++;
9898 [ # # ]: 0 : if (MLX5_SH(dev)->config.dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS) {
9899 : : flow_hw_update_action_mask(&actions_v[idx], &actions_m[idx],
9900 : : RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
9901 : : ©_metadata_v, ©_metadata_m);
9902 : : idx++;
9903 : : }
9904 : : flow_hw_update_action_mask(&actions_v[idx], &actions_m[idx], RTE_FLOW_ACTION_TYPE_JUMP,
9905 : : &jump_v, &jump_m);
9906 : 0 : idx++;
9907 : : flow_hw_update_action_mask(&actions_v[idx], &actions_m[idx], RTE_FLOW_ACTION_TYPE_END,
9908 : : NULL, NULL);
9909 : : idx++;
9910 : : MLX5_ASSERT(idx <= RTE_DIM(actions_v));
9911 : 0 : return flow_hw_actions_template_create(dev, &attr, actions_v, actions_m, error);
9912 : : }
9913 : :
9914 : : static void
9915 : 0 : flow_hw_cleanup_tx_repr_tagging(struct rte_eth_dev *dev)
9916 : : {
9917 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
9918 : :
9919 [ # # ]: 0 : if (priv->hw_tx_repr_tagging_tbl) {
9920 : 0 : flow_hw_table_destroy(dev, priv->hw_tx_repr_tagging_tbl, NULL);
9921 : 0 : priv->hw_tx_repr_tagging_tbl = NULL;
9922 : : }
9923 [ # # ]: 0 : if (priv->hw_tx_repr_tagging_at) {
9924 : 0 : flow_hw_actions_template_destroy(dev, priv->hw_tx_repr_tagging_at, NULL);
9925 : 0 : priv->hw_tx_repr_tagging_at = NULL;
9926 : : }
9927 [ # # ]: 0 : if (priv->hw_tx_repr_tagging_pt) {
9928 : 0 : flow_hw_pattern_template_destroy(dev, priv->hw_tx_repr_tagging_pt, NULL);
9929 : 0 : priv->hw_tx_repr_tagging_pt = NULL;
9930 : : }
9931 : 0 : }
9932 : :
9933 : : /**
9934 : : * Setup templates and table used to create default Tx flow rules. These default rules
9935 : : * allow for matching Tx representor traffic using a vport tag placed in unused bits of
9936 : : * REG_C_0 register.
9937 : : *
9938 : : * @param dev
9939 : : * Pointer to Ethernet device.
9940 : : * @param[out] error
9941 : : * Pointer to error structure.
9942 : : *
9943 : : * @return
9944 : : * 0 on success, negative errno value otherwise.
9945 : : */
9946 : : static int
9947 : 0 : flow_hw_setup_tx_repr_tagging(struct rte_eth_dev *dev, struct rte_flow_error *error)
9948 : : {
9949 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
9950 : 0 : struct rte_flow_template_table_attr attr = {
9951 : : .flow_attr = {
9952 : : .group = 0,
9953 : : .priority = MLX5_HW_LOWEST_PRIO_ROOT,
9954 : : .egress = 1,
9955 : : },
9956 : : .nb_flows = MLX5_HW_CTRL_FLOW_NB_RULES,
9957 : : };
9958 : 0 : struct mlx5_flow_template_table_cfg cfg = {
9959 : : .attr = attr,
9960 : : .external = false,
9961 : : };
9962 : :
9963 : : MLX5_ASSERT(priv->sh->config.dv_esw_en);
9964 : : MLX5_ASSERT(priv->sh->config.repr_matching);
9965 : 0 : priv->hw_tx_repr_tagging_pt =
9966 : 0 : flow_hw_create_tx_repr_sq_pattern_tmpl(dev, error);
9967 [ # # ]: 0 : if (!priv->hw_tx_repr_tagging_pt)
9968 : 0 : goto err;
9969 : 0 : priv->hw_tx_repr_tagging_at =
9970 : 0 : flow_hw_create_tx_repr_tag_jump_acts_tmpl(dev, error);
9971 [ # # ]: 0 : if (!priv->hw_tx_repr_tagging_at)
9972 : 0 : goto err;
9973 : 0 : priv->hw_tx_repr_tagging_tbl = flow_hw_table_create(dev, &cfg,
9974 : : &priv->hw_tx_repr_tagging_pt, 1,
9975 : : &priv->hw_tx_repr_tagging_at, 1,
9976 : : error);
9977 [ # # ]: 0 : if (!priv->hw_tx_repr_tagging_tbl)
9978 : 0 : goto err;
9979 : : return 0;
9980 : 0 : err:
9981 : 0 : flow_hw_cleanup_tx_repr_tagging(dev);
9982 : 0 : return -rte_errno;
9983 : : }
9984 : :
9985 : : static uint32_t
9986 : : flow_hw_esw_mgr_regc_marker_mask(struct rte_eth_dev *dev)
9987 : : {
9988 : 0 : uint32_t mask = MLX5_SH(dev)->dv_regc0_mask;
9989 : :
9990 : : /* Mask is verified during device initialization. */
9991 : : MLX5_ASSERT(mask != 0);
9992 : : return mask;
9993 : : }
9994 : :
9995 : : static uint32_t
9996 : : flow_hw_esw_mgr_regc_marker(struct rte_eth_dev *dev)
9997 : : {
9998 : 0 : uint32_t mask = MLX5_SH(dev)->dv_regc0_mask;
9999 : :
10000 : : /* Mask is verified during device initialization. */
10001 : : MLX5_ASSERT(mask != 0);
10002 : 0 : return RTE_BIT32(rte_bsf32(mask));
10003 : : }
10004 : :
10005 : : /**
10006 : : * Creates a flow pattern template used to match on E-Switch Manager.
10007 : : * This template is used to set up a table for SQ miss default flow.
10008 : : *
10009 : : * @param dev
10010 : : * Pointer to Ethernet device.
10011 : : * @param error
10012 : : * Pointer to error structure.
10013 : : *
10014 : : * @return
10015 : : * Pointer to flow pattern template on success, NULL otherwise.
10016 : : */
10017 : : static struct rte_flow_pattern_template *
10018 : 0 : flow_hw_create_ctrl_esw_mgr_pattern_template(struct rte_eth_dev *dev,
10019 : : struct rte_flow_error *error)
10020 : : {
10021 : 0 : struct rte_flow_pattern_template_attr attr = {
10022 : : .relaxed_matching = 0,
10023 : : .transfer = 1,
10024 : : };
10025 : 0 : struct rte_flow_item_ethdev port_spec = {
10026 : : .port_id = MLX5_REPRESENTED_PORT_ESW_MGR,
10027 : : };
10028 : 0 : struct rte_flow_item_ethdev port_mask = {
10029 : : .port_id = UINT16_MAX,
10030 : : };
10031 : 0 : struct mlx5_rte_flow_item_sq sq_mask = {
10032 : : .queue = UINT32_MAX,
10033 : : };
10034 : 0 : struct rte_flow_item items[] = {
10035 : : {
10036 : : .type = RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT,
10037 : : .spec = &port_spec,
10038 : : .mask = &port_mask,
10039 : : },
10040 : : {
10041 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_SQ,
10042 : : .mask = &sq_mask,
10043 : : },
10044 : : {
10045 : : .type = RTE_FLOW_ITEM_TYPE_END,
10046 : : },
10047 : : };
10048 : :
10049 : 0 : return flow_hw_pattern_template_create(dev, &attr, items, error);
10050 : : }
10051 : :
10052 : : /**
10053 : : * Creates a flow pattern template used to match REG_C_0 and a SQ.
10054 : : * Matching on REG_C_0 is set up to match on all bits usable by user-space.
10055 : : * If traffic was sent from E-Switch Manager, then all usable bits will be set to 0,
10056 : : * except the least significant bit, which will be set to 1.
10057 : : *
10058 : : * This template is used to set up a table for SQ miss default flow.
10059 : : *
10060 : : * @param dev
10061 : : * Pointer to Ethernet device.
10062 : : * @param error
10063 : : * Pointer to error structure.
10064 : : *
10065 : : * @return
10066 : : * Pointer to flow pattern template on success, NULL otherwise.
10067 : : */
10068 : : static struct rte_flow_pattern_template *
10069 : 0 : flow_hw_create_ctrl_regc_sq_pattern_template(struct rte_eth_dev *dev,
10070 : : struct rte_flow_error *error)
10071 : : {
10072 : 0 : struct rte_flow_pattern_template_attr attr = {
10073 : : .relaxed_matching = 0,
10074 : : .transfer = 1,
10075 : : };
10076 : 0 : struct rte_flow_item_tag reg_c0_spec = {
10077 : : .index = (uint8_t)REG_C_0,
10078 : : };
10079 : 0 : struct rte_flow_item_tag reg_c0_mask = {
10080 : : .index = 0xff,
10081 : : .data = flow_hw_esw_mgr_regc_marker_mask(dev),
10082 : : };
10083 : 0 : struct mlx5_rte_flow_item_sq queue_mask = {
10084 : : .queue = UINT32_MAX,
10085 : : };
10086 : 0 : struct rte_flow_item items[] = {
10087 : : {
10088 : : .type = (enum rte_flow_item_type)
10089 : : MLX5_RTE_FLOW_ITEM_TYPE_TAG,
10090 : : .spec = ®_c0_spec,
10091 : : .mask = ®_c0_mask,
10092 : : },
10093 : : {
10094 : : .type = (enum rte_flow_item_type)
10095 : : MLX5_RTE_FLOW_ITEM_TYPE_SQ,
10096 : : .mask = &queue_mask,
10097 : : },
10098 : : {
10099 : : .type = RTE_FLOW_ITEM_TYPE_END,
10100 : : },
10101 : : };
10102 : :
10103 : 0 : return flow_hw_pattern_template_create(dev, &attr, items, error);
10104 : : }
10105 : :
10106 : : /**
10107 : : * Creates a flow pattern template with unmasked represented port matching.
10108 : : * This template is used to set up a table for default transfer flows
10109 : : * directing packets to group 1.
10110 : : *
10111 : : * @param dev
10112 : : * Pointer to Ethernet device.
10113 : : * @param error
10114 : : * Pointer to error structure.
10115 : : *
10116 : : * @return
10117 : : * Pointer to flow pattern template on success, NULL otherwise.
10118 : : */
10119 : : static struct rte_flow_pattern_template *
10120 : 0 : flow_hw_create_ctrl_port_pattern_template(struct rte_eth_dev *dev,
10121 : : struct rte_flow_error *error)
10122 : : {
10123 : 0 : struct rte_flow_pattern_template_attr attr = {
10124 : : .relaxed_matching = 0,
10125 : : .transfer = 1,
10126 : : };
10127 : 0 : struct rte_flow_item_ethdev port_mask = {
10128 : : .port_id = UINT16_MAX,
10129 : : };
10130 : 0 : struct rte_flow_item items[] = {
10131 : : {
10132 : : .type = RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT,
10133 : : .mask = &port_mask,
10134 : : },
10135 : : {
10136 : : .type = RTE_FLOW_ITEM_TYPE_END,
10137 : : },
10138 : : };
10139 : :
10140 : 0 : return flow_hw_pattern_template_create(dev, &attr, items, error);
10141 : : }
10142 : :
10143 : : /*
10144 : : * Creating a flow pattern template with all ETH packets matching.
10145 : : * This template is used to set up a table for default Tx copy (Tx metadata
10146 : : * to REG_C_1) flow rule usage.
10147 : : *
10148 : : * @param dev
10149 : : * Pointer to Ethernet device.
10150 : : * @param error
10151 : : * Pointer to error structure.
10152 : : *
10153 : : * @return
10154 : : * Pointer to flow pattern template on success, NULL otherwise.
10155 : : */
10156 : : static struct rte_flow_pattern_template *
10157 : 0 : flow_hw_create_tx_default_mreg_copy_pattern_template(struct rte_eth_dev *dev,
10158 : : struct rte_flow_error *error)
10159 : : {
10160 : 0 : struct rte_flow_pattern_template_attr tx_pa_attr = {
10161 : : .relaxed_matching = 0,
10162 : : .egress = 1,
10163 : : };
10164 : 0 : struct rte_flow_item_eth promisc = {
10165 : : .hdr.dst_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
10166 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
10167 : : .hdr.ether_type = 0,
10168 : : };
10169 : 0 : struct rte_flow_item eth_all[] = {
10170 : : [0] = {
10171 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
10172 : : .spec = &promisc,
10173 : : .mask = &promisc,
10174 : : },
10175 : : [1] = {
10176 : : .type = RTE_FLOW_ITEM_TYPE_END,
10177 : : },
10178 : : };
10179 : :
10180 : 0 : return flow_hw_pattern_template_create(dev, &tx_pa_attr, eth_all, error);
10181 : : }
10182 : :
10183 : : /*
10184 : : * Creating a flow pattern template with all LACP packets matching, only for NIC
10185 : : * ingress domain.
10186 : : *
10187 : : * @param dev
10188 : : * Pointer to Ethernet device.
10189 : : * @param error
10190 : : * Pointer to error structure.
10191 : : *
10192 : : * @return
10193 : : * Pointer to flow pattern template on success, NULL otherwise.
10194 : : */
10195 : : static struct rte_flow_pattern_template *
10196 : 0 : flow_hw_create_lacp_rx_pattern_template(struct rte_eth_dev *dev, struct rte_flow_error *error)
10197 : : {
10198 : 0 : struct rte_flow_pattern_template_attr pa_attr = {
10199 : : .relaxed_matching = 0,
10200 : : .ingress = 1,
10201 : : };
10202 : 0 : struct rte_flow_item_eth lacp_mask = {
10203 : : .dst.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
10204 : : .src.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
10205 : : .type = 0xFFFF,
10206 : : };
10207 : 0 : struct rte_flow_item eth_all[] = {
10208 : : [0] = {
10209 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
10210 : : .mask = &lacp_mask,
10211 : : },
10212 : : [1] = {
10213 : : .type = RTE_FLOW_ITEM_TYPE_END,
10214 : : },
10215 : : };
10216 : 0 : return flow_hw_pattern_template_create(dev, &pa_attr, eth_all, error);
10217 : : }
10218 : :
10219 : : /**
10220 : : * Creates a flow actions template with modify field action and masked jump action.
10221 : : * Modify field action sets the least significant bit of REG_C_0 (usable by user-space)
10222 : : * to 1, meaning that packet was originated from E-Switch Manager. Jump action
10223 : : * transfers steering to group 1.
10224 : : *
10225 : : * @param dev
10226 : : * Pointer to Ethernet device.
10227 : : * @param error
10228 : : * Pointer to error structure.
10229 : : *
10230 : : * @return
10231 : : * Pointer to flow actions template on success, NULL otherwise.
10232 : : */
10233 : : static struct rte_flow_actions_template *
10234 : 0 : flow_hw_create_ctrl_regc_jump_actions_template(struct rte_eth_dev *dev,
10235 : : struct rte_flow_error *error)
10236 : : {
10237 [ # # ]: 0 : uint32_t marker_mask = flow_hw_esw_mgr_regc_marker_mask(dev);
10238 : 0 : uint32_t marker_bits = flow_hw_esw_mgr_regc_marker(dev);
10239 : 0 : struct rte_flow_actions_template_attr attr = {
10240 : : .transfer = 1,
10241 : : };
10242 [ # # ]: 0 : struct rte_flow_action_modify_field set_reg_v = {
10243 : : .operation = RTE_FLOW_MODIFY_SET,
10244 : : .dst = {
10245 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
10246 : : .tag_index = REG_C_0,
10247 : : },
10248 : : .src = {
10249 : : .field = RTE_FLOW_FIELD_VALUE,
10250 : : },
10251 : : .width = rte_popcount32(marker_mask),
10252 : : };
10253 : 0 : struct rte_flow_action_modify_field set_reg_m = {
10254 : : .operation = RTE_FLOW_MODIFY_SET,
10255 : : .dst = {
10256 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
10257 : : .level = UINT8_MAX,
10258 : : .tag_index = UINT8_MAX,
10259 : : .offset = UINT32_MAX,
10260 : : },
10261 : : .src = {
10262 : : .field = RTE_FLOW_FIELD_VALUE,
10263 : : },
10264 : : .width = UINT32_MAX,
10265 : : };
10266 : 0 : struct rte_flow_action_jump jump_v = {
10267 : : .group = MLX5_HW_LOWEST_USABLE_GROUP,
10268 : : };
10269 : 0 : struct rte_flow_action_jump jump_m = {
10270 : : .group = UINT32_MAX,
10271 : : };
10272 : 0 : struct rte_flow_action actions_v[] = {
10273 : : {
10274 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
10275 : : .conf = &set_reg_v,
10276 : : },
10277 : : {
10278 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
10279 : : .conf = &jump_v,
10280 : : },
10281 : : {
10282 : : .type = RTE_FLOW_ACTION_TYPE_END,
10283 : : }
10284 : : };
10285 : 0 : struct rte_flow_action actions_m[] = {
10286 : : {
10287 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
10288 : : .conf = &set_reg_m,
10289 : : },
10290 : : {
10291 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
10292 : : .conf = &jump_m,
10293 : : },
10294 : : {
10295 : : .type = RTE_FLOW_ACTION_TYPE_END,
10296 : : }
10297 : : };
10298 : :
10299 [ # # ]: 0 : set_reg_v.dst.offset = rte_bsf32(marker_mask);
10300 : : rte_memcpy(set_reg_v.src.value, &marker_bits, sizeof(marker_bits));
10301 : : rte_memcpy(set_reg_m.src.value, &marker_mask, sizeof(marker_mask));
10302 : 0 : return flow_hw_actions_template_create(dev, &attr, actions_v, actions_m, error);
10303 : : }
10304 : :
10305 : : /**
10306 : : * Creates a flow actions template with an unmasked JUMP action. Flows
10307 : : * based on this template will perform a jump to some group. This template
10308 : : * is used to set up tables for control flows.
10309 : : *
10310 : : * @param dev
10311 : : * Pointer to Ethernet device.
10312 : : * @param group
10313 : : * Destination group for this action template.
10314 : : * @param error
10315 : : * Pointer to error structure.
10316 : : *
10317 : : * @return
10318 : : * Pointer to flow actions template on success, NULL otherwise.
10319 : : */
10320 : : static struct rte_flow_actions_template *
10321 : 0 : flow_hw_create_ctrl_jump_actions_template(struct rte_eth_dev *dev,
10322 : : uint32_t group,
10323 : : struct rte_flow_error *error)
10324 : : {
10325 : 0 : struct rte_flow_actions_template_attr attr = {
10326 : : .transfer = 1,
10327 : : };
10328 : 0 : struct rte_flow_action_jump jump_v = {
10329 : : .group = group,
10330 : : };
10331 : 0 : struct rte_flow_action_jump jump_m = {
10332 : : .group = UINT32_MAX,
10333 : : };
10334 : 0 : struct rte_flow_action actions_v[] = {
10335 : : {
10336 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
10337 : : .conf = &jump_v,
10338 : : },
10339 : : {
10340 : : .type = RTE_FLOW_ACTION_TYPE_END,
10341 : : }
10342 : : };
10343 : 0 : struct rte_flow_action actions_m[] = {
10344 : : {
10345 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
10346 : : .conf = &jump_m,
10347 : : },
10348 : : {
10349 : : .type = RTE_FLOW_ACTION_TYPE_END,
10350 : : }
10351 : : };
10352 : :
10353 : 0 : return flow_hw_actions_template_create(dev, &attr, actions_v,
10354 : : actions_m, error);
10355 : : }
10356 : :
10357 : : /**
10358 : : * Creates a flow action template with a unmasked REPRESENTED_PORT action.
10359 : : * It is used to create control flow tables.
10360 : : *
10361 : : * @param dev
10362 : : * Pointer to Ethernet device.
10363 : : * @param error
10364 : : * Pointer to error structure.
10365 : : *
10366 : : * @return
10367 : : * Pointer to flow action template on success, NULL otherwise.
10368 : : */
10369 : : static struct rte_flow_actions_template *
10370 : 0 : flow_hw_create_ctrl_port_actions_template(struct rte_eth_dev *dev,
10371 : : struct rte_flow_error *error)
10372 : : {
10373 : 0 : struct rte_flow_actions_template_attr attr = {
10374 : : .transfer = 1,
10375 : : };
10376 : 0 : struct rte_flow_action_ethdev port_v = {
10377 : : .port_id = 0,
10378 : : };
10379 : 0 : struct rte_flow_action actions_v[] = {
10380 : : {
10381 : : .type = RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT,
10382 : : .conf = &port_v,
10383 : : },
10384 : : {
10385 : : .type = RTE_FLOW_ACTION_TYPE_END,
10386 : : }
10387 : : };
10388 : 0 : struct rte_flow_action_ethdev port_m = {
10389 : : .port_id = 0,
10390 : : };
10391 : 0 : struct rte_flow_action actions_m[] = {
10392 : : {
10393 : : .type = RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT,
10394 : : .conf = &port_m,
10395 : : },
10396 : : {
10397 : : .type = RTE_FLOW_ACTION_TYPE_END,
10398 : : }
10399 : : };
10400 : :
10401 : 0 : return flow_hw_actions_template_create(dev, &attr, actions_v, actions_m, error);
10402 : : }
10403 : :
10404 : : /*
10405 : : * Creating an actions template to use header modify action for register
10406 : : * copying. This template is used to set up a table for copy flow.
10407 : : *
10408 : : * @param dev
10409 : : * Pointer to Ethernet device.
10410 : : * @param error
10411 : : * Pointer to error structure.
10412 : : *
10413 : : * @return
10414 : : * Pointer to flow actions template on success, NULL otherwise.
10415 : : */
10416 : : static struct rte_flow_actions_template *
10417 : 0 : flow_hw_create_tx_default_mreg_copy_actions_template(struct rte_eth_dev *dev,
10418 : : struct rte_flow_error *error)
10419 : : {
10420 : 0 : struct rte_flow_actions_template_attr tx_act_attr = {
10421 : : .egress = 1,
10422 : : };
10423 : 0 : const struct rte_flow_action_modify_field mreg_action = {
10424 : : .operation = RTE_FLOW_MODIFY_SET,
10425 : : .dst = {
10426 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
10427 : : .tag_index = REG_C_1,
10428 : : },
10429 : : .src = {
10430 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
10431 : : .tag_index = REG_A,
10432 : : },
10433 : : .width = 32,
10434 : : };
10435 : 0 : const struct rte_flow_action_modify_field mreg_mask = {
10436 : : .operation = RTE_FLOW_MODIFY_SET,
10437 : : .dst = {
10438 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
10439 : : .level = UINT8_MAX,
10440 : : .tag_index = UINT8_MAX,
10441 : : .offset = UINT32_MAX,
10442 : : },
10443 : : .src = {
10444 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
10445 : : .level = UINT8_MAX,
10446 : : .tag_index = UINT8_MAX,
10447 : : .offset = UINT32_MAX,
10448 : : },
10449 : : .width = UINT32_MAX,
10450 : : };
10451 : 0 : const struct rte_flow_action_jump jump_action = {
10452 : : .group = 1,
10453 : : };
10454 : 0 : const struct rte_flow_action_jump jump_mask = {
10455 : : .group = UINT32_MAX,
10456 : : };
10457 : 0 : const struct rte_flow_action actions[] = {
10458 : : [0] = {
10459 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
10460 : : .conf = &mreg_action,
10461 : : },
10462 : : [1] = {
10463 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
10464 : : .conf = &jump_action,
10465 : : },
10466 : : [2] = {
10467 : : .type = RTE_FLOW_ACTION_TYPE_END,
10468 : : },
10469 : : };
10470 : 0 : const struct rte_flow_action masks[] = {
10471 : : [0] = {
10472 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
10473 : : .conf = &mreg_mask,
10474 : : },
10475 : : [1] = {
10476 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
10477 : : .conf = &jump_mask,
10478 : : },
10479 : : [2] = {
10480 : : .type = RTE_FLOW_ACTION_TYPE_END,
10481 : : },
10482 : : };
10483 : :
10484 : 0 : return flow_hw_actions_template_create(dev, &tx_act_attr, actions,
10485 : : masks, error);
10486 : : }
10487 : :
10488 : : /*
10489 : : * Creating an actions template to use default miss to re-route packets to the
10490 : : * kernel driver stack.
10491 : : * On root table, only DEFAULT_MISS action can be used.
10492 : : *
10493 : : * @param dev
10494 : : * Pointer to Ethernet device.
10495 : : * @param error
10496 : : * Pointer to error structure.
10497 : : *
10498 : : * @return
10499 : : * Pointer to flow actions template on success, NULL otherwise.
10500 : : */
10501 : : static struct rte_flow_actions_template *
10502 : 0 : flow_hw_create_lacp_rx_actions_template(struct rte_eth_dev *dev, struct rte_flow_error *error)
10503 : : {
10504 : 0 : struct rte_flow_actions_template_attr act_attr = {
10505 : : .ingress = 1,
10506 : : };
10507 : 0 : const struct rte_flow_action actions[] = {
10508 : : [0] = {
10509 : : .type = (enum rte_flow_action_type)
10510 : : MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS,
10511 : : },
10512 : : [1] = {
10513 : : .type = RTE_FLOW_ACTION_TYPE_END,
10514 : : },
10515 : : };
10516 : :
10517 : 0 : return flow_hw_actions_template_create(dev, &act_attr, actions, actions, error);
10518 : : }
10519 : :
10520 : : /**
10521 : : * Creates a control flow table used to transfer traffic from E-Switch Manager
10522 : : * and TX queues from group 0 to group 1.
10523 : : *
10524 : : * @param dev
10525 : : * Pointer to Ethernet device.
10526 : : * @param it
10527 : : * Pointer to flow pattern template.
10528 : : * @param at
10529 : : * Pointer to flow actions template.
10530 : : * @param error
10531 : : * Pointer to error structure.
10532 : : *
10533 : : * @return
10534 : : * Pointer to flow table on success, NULL otherwise.
10535 : : */
10536 : : static struct rte_flow_template_table*
10537 : 0 : flow_hw_create_ctrl_sq_miss_root_table(struct rte_eth_dev *dev,
10538 : : struct rte_flow_pattern_template *it,
10539 : : struct rte_flow_actions_template *at,
10540 : : struct rte_flow_error *error)
10541 : : {
10542 : 0 : struct rte_flow_template_table_attr attr = {
10543 : : .flow_attr = {
10544 : : .group = 0,
10545 : : .priority = MLX5_HW_LOWEST_PRIO_ROOT,
10546 : : .ingress = 0,
10547 : : .egress = 0,
10548 : : .transfer = 1,
10549 : : },
10550 : : .nb_flows = MLX5_HW_CTRL_FLOW_NB_RULES,
10551 : : };
10552 : 0 : struct mlx5_flow_template_table_cfg cfg = {
10553 : : .attr = attr,
10554 : : .external = false,
10555 : : };
10556 : :
10557 : 0 : return flow_hw_table_create(dev, &cfg, &it, 1, &at, 1, error);
10558 : : }
10559 : :
10560 : :
10561 : : /**
10562 : : * Creates a control flow table used to transfer traffic from E-Switch Manager
10563 : : * and TX queues from group 0 to group 1.
10564 : : *
10565 : : * @param dev
10566 : : * Pointer to Ethernet device.
10567 : : * @param it
10568 : : * Pointer to flow pattern template.
10569 : : * @param at
10570 : : * Pointer to flow actions template.
10571 : : * @param error
10572 : : * Pointer to error structure.
10573 : : *
10574 : : * @return
10575 : : * Pointer to flow table on success, NULL otherwise.
10576 : : */
10577 : : static struct rte_flow_template_table*
10578 : 0 : flow_hw_create_ctrl_sq_miss_table(struct rte_eth_dev *dev,
10579 : : struct rte_flow_pattern_template *it,
10580 : : struct rte_flow_actions_template *at,
10581 : : struct rte_flow_error *error)
10582 : : {
10583 : 0 : struct rte_flow_template_table_attr attr = {
10584 : : .flow_attr = {
10585 : : .group = 1,
10586 : : .priority = MLX5_HW_LOWEST_PRIO_NON_ROOT,
10587 : : .ingress = 0,
10588 : : .egress = 0,
10589 : : .transfer = 1,
10590 : : },
10591 : : .nb_flows = MLX5_HW_CTRL_FLOW_NB_RULES,
10592 : : };
10593 : 0 : struct mlx5_flow_template_table_cfg cfg = {
10594 : : .attr = attr,
10595 : : .external = false,
10596 : : };
10597 : :
10598 : 0 : return flow_hw_table_create(dev, &cfg, &it, 1, &at, 1, error);
10599 : : }
10600 : :
10601 : : /*
10602 : : * Creating the default Tx metadata copy table on NIC Tx group 0.
10603 : : *
10604 : : * @param dev
10605 : : * Pointer to Ethernet device.
10606 : : * @param pt
10607 : : * Pointer to flow pattern template.
10608 : : * @param at
10609 : : * Pointer to flow actions template.
10610 : : * @param error
10611 : : * Pointer to error structure.
10612 : : *
10613 : : * @return
10614 : : * Pointer to flow table on success, NULL otherwise.
10615 : : */
10616 : : static struct rte_flow_template_table*
10617 : 0 : flow_hw_create_tx_default_mreg_copy_table(struct rte_eth_dev *dev,
10618 : : struct rte_flow_pattern_template *pt,
10619 : : struct rte_flow_actions_template *at,
10620 : : struct rte_flow_error *error)
10621 : : {
10622 : 0 : struct rte_flow_template_table_attr tx_tbl_attr = {
10623 : : .flow_attr = {
10624 : : .group = 0, /* Root */
10625 : : .priority = MLX5_HW_LOWEST_PRIO_ROOT,
10626 : : .egress = 1,
10627 : : },
10628 : : .nb_flows = 1, /* One default flow rule for all. */
10629 : : };
10630 : 0 : struct mlx5_flow_template_table_cfg tx_tbl_cfg = {
10631 : : .attr = tx_tbl_attr,
10632 : : .external = false,
10633 : : };
10634 : :
10635 : 0 : return flow_hw_table_create(dev, &tx_tbl_cfg, &pt, 1, &at, 1, error);
10636 : : }
10637 : :
10638 : : /**
10639 : : * Creates a control flow table used to transfer traffic
10640 : : * from group 0 to group 1.
10641 : : *
10642 : : * @param dev
10643 : : * Pointer to Ethernet device.
10644 : : * @param it
10645 : : * Pointer to flow pattern template.
10646 : : * @param at
10647 : : * Pointer to flow actions template.
10648 : : * @param error
10649 : : * Pointer to error structure.
10650 : : *
10651 : : * @return
10652 : : * Pointer to flow table on success, NULL otherwise.
10653 : : */
10654 : : static struct rte_flow_template_table *
10655 : 0 : flow_hw_create_ctrl_jump_table(struct rte_eth_dev *dev,
10656 : : struct rte_flow_pattern_template *it,
10657 : : struct rte_flow_actions_template *at,
10658 : : struct rte_flow_error *error)
10659 : : {
10660 : 0 : struct rte_flow_template_table_attr attr = {
10661 : : .flow_attr = {
10662 : : .group = 0,
10663 : : .priority = 0,
10664 : : .ingress = 0,
10665 : : .egress = 0,
10666 : : .transfer = 1,
10667 : : },
10668 : : .nb_flows = MLX5_HW_CTRL_FLOW_NB_RULES,
10669 : : };
10670 : 0 : struct mlx5_flow_template_table_cfg cfg = {
10671 : : .attr = attr,
10672 : : .external = false,
10673 : : };
10674 : :
10675 : 0 : return flow_hw_table_create(dev, &cfg, &it, 1, &at, 1, error);
10676 : : }
10677 : :
10678 : : /**
10679 : : * Cleans up all template tables and pattern, and actions templates used for
10680 : : * FDB control flow rules.
10681 : : *
10682 : : * @param dev
10683 : : * Pointer to Ethernet device.
10684 : : */
10685 : : static void
10686 : 0 : flow_hw_cleanup_ctrl_fdb_tables(struct rte_eth_dev *dev)
10687 : : {
10688 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
10689 : : struct mlx5_flow_hw_ctrl_fdb *hw_ctrl_fdb;
10690 : :
10691 [ # # ]: 0 : if (!priv->hw_ctrl_fdb)
10692 : : return;
10693 : : hw_ctrl_fdb = priv->hw_ctrl_fdb;
10694 : : /* Clean up templates used for LACP default miss table. */
10695 [ # # ]: 0 : if (hw_ctrl_fdb->hw_lacp_rx_tbl)
10696 : 0 : claim_zero(flow_hw_table_destroy(dev, hw_ctrl_fdb->hw_lacp_rx_tbl, NULL));
10697 [ # # ]: 0 : if (hw_ctrl_fdb->lacp_rx_actions_tmpl)
10698 : 0 : claim_zero(flow_hw_actions_template_destroy(dev, hw_ctrl_fdb->lacp_rx_actions_tmpl,
10699 : : NULL));
10700 [ # # ]: 0 : if (hw_ctrl_fdb->lacp_rx_items_tmpl)
10701 : 0 : claim_zero(flow_hw_pattern_template_destroy(dev, hw_ctrl_fdb->lacp_rx_items_tmpl,
10702 : : NULL));
10703 : : /* Clean up templates used for default Tx metadata copy. */
10704 [ # # ]: 0 : if (hw_ctrl_fdb->hw_tx_meta_cpy_tbl)
10705 : 0 : claim_zero(flow_hw_table_destroy(dev, hw_ctrl_fdb->hw_tx_meta_cpy_tbl, NULL));
10706 [ # # ]: 0 : if (hw_ctrl_fdb->tx_meta_actions_tmpl)
10707 : 0 : claim_zero(flow_hw_actions_template_destroy(dev, hw_ctrl_fdb->tx_meta_actions_tmpl,
10708 : : NULL));
10709 [ # # ]: 0 : if (hw_ctrl_fdb->tx_meta_items_tmpl)
10710 : 0 : claim_zero(flow_hw_pattern_template_destroy(dev, hw_ctrl_fdb->tx_meta_items_tmpl,
10711 : : NULL));
10712 : : /* Clean up templates used for default FDB jump rule. */
10713 [ # # ]: 0 : if (hw_ctrl_fdb->hw_esw_zero_tbl)
10714 : 0 : claim_zero(flow_hw_table_destroy(dev, hw_ctrl_fdb->hw_esw_zero_tbl, NULL));
10715 [ # # ]: 0 : if (hw_ctrl_fdb->jump_one_actions_tmpl)
10716 : 0 : claim_zero(flow_hw_actions_template_destroy(dev, hw_ctrl_fdb->jump_one_actions_tmpl,
10717 : : NULL));
10718 [ # # ]: 0 : if (hw_ctrl_fdb->port_items_tmpl)
10719 : 0 : claim_zero(flow_hw_pattern_template_destroy(dev, hw_ctrl_fdb->port_items_tmpl,
10720 : : NULL));
10721 : : /* Clean up templates used for default SQ miss flow rules - non-root table. */
10722 [ # # ]: 0 : if (hw_ctrl_fdb->hw_esw_sq_miss_tbl)
10723 : 0 : claim_zero(flow_hw_table_destroy(dev, hw_ctrl_fdb->hw_esw_sq_miss_tbl, NULL));
10724 [ # # ]: 0 : if (hw_ctrl_fdb->regc_sq_items_tmpl)
10725 : 0 : claim_zero(flow_hw_pattern_template_destroy(dev, hw_ctrl_fdb->regc_sq_items_tmpl,
10726 : : NULL));
10727 [ # # ]: 0 : if (hw_ctrl_fdb->port_actions_tmpl)
10728 : 0 : claim_zero(flow_hw_actions_template_destroy(dev, hw_ctrl_fdb->port_actions_tmpl,
10729 : : NULL));
10730 : : /* Clean up templates used for default SQ miss flow rules - root table. */
10731 [ # # ]: 0 : if (hw_ctrl_fdb->hw_esw_sq_miss_root_tbl)
10732 : 0 : claim_zero(flow_hw_table_destroy(dev, hw_ctrl_fdb->hw_esw_sq_miss_root_tbl, NULL));
10733 [ # # ]: 0 : if (hw_ctrl_fdb->regc_jump_actions_tmpl)
10734 : 0 : claim_zero(flow_hw_actions_template_destroy(dev,
10735 : : hw_ctrl_fdb->regc_jump_actions_tmpl, NULL));
10736 [ # # ]: 0 : if (hw_ctrl_fdb->esw_mgr_items_tmpl)
10737 : 0 : claim_zero(flow_hw_pattern_template_destroy(dev, hw_ctrl_fdb->esw_mgr_items_tmpl,
10738 : : NULL));
10739 : : /* Clean up templates structure for FDB control flow rules. */
10740 : 0 : mlx5_free(hw_ctrl_fdb);
10741 : 0 : priv->hw_ctrl_fdb = NULL;
10742 : : }
10743 : :
10744 : : /*
10745 : : * Create a table on the root group to for the LACP traffic redirecting.
10746 : : *
10747 : : * @param dev
10748 : : * Pointer to Ethernet device.
10749 : : * @param it
10750 : : * Pointer to flow pattern template.
10751 : : * @param at
10752 : : * Pointer to flow actions template.
10753 : : *
10754 : : * @return
10755 : : * Pointer to flow table on success, NULL otherwise.
10756 : : */
10757 : : static struct rte_flow_template_table *
10758 : 0 : flow_hw_create_lacp_rx_table(struct rte_eth_dev *dev,
10759 : : struct rte_flow_pattern_template *it,
10760 : : struct rte_flow_actions_template *at,
10761 : : struct rte_flow_error *error)
10762 : : {
10763 : 0 : struct rte_flow_template_table_attr attr = {
10764 : : .flow_attr = {
10765 : : .group = 0,
10766 : : .priority = 0,
10767 : : .ingress = 1,
10768 : : .egress = 0,
10769 : : .transfer = 0,
10770 : : },
10771 : : .nb_flows = 1,
10772 : : };
10773 : 0 : struct mlx5_flow_template_table_cfg cfg = {
10774 : : .attr = attr,
10775 : : .external = false,
10776 : : };
10777 : :
10778 : 0 : return flow_hw_table_create(dev, &cfg, &it, 1, &at, 1, error);
10779 : : }
10780 : :
10781 : : /**
10782 : : * Creates a set of flow tables used to create control flows used
10783 : : * when E-Switch is engaged.
10784 : : *
10785 : : * @param dev
10786 : : * Pointer to Ethernet device.
10787 : : * @param error
10788 : : * Pointer to error structure.
10789 : : *
10790 : : * @return
10791 : : * 0 on success, negative values otherwise
10792 : : */
10793 : : static int
10794 : 0 : flow_hw_create_ctrl_tables(struct rte_eth_dev *dev, struct rte_flow_error *error)
10795 : : {
10796 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
10797 : : struct mlx5_flow_hw_ctrl_fdb *hw_ctrl_fdb;
10798 : 0 : uint32_t xmeta = priv->sh->config.dv_xmeta_en;
10799 : 0 : uint32_t repr_matching = priv->sh->config.repr_matching;
10800 : 0 : uint32_t fdb_def_rule = priv->sh->config.fdb_def_rule;
10801 : :
10802 : : MLX5_ASSERT(priv->hw_ctrl_fdb == NULL);
10803 : 0 : hw_ctrl_fdb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*hw_ctrl_fdb), 0, SOCKET_ID_ANY);
10804 [ # # ]: 0 : if (!hw_ctrl_fdb) {
10805 : 0 : DRV_LOG(ERR, "port %u failed to allocate memory for FDB control flow templates",
10806 : : dev->data->port_id);
10807 : 0 : rte_errno = ENOMEM;
10808 : 0 : goto err;
10809 : : }
10810 : 0 : priv->hw_ctrl_fdb = hw_ctrl_fdb;
10811 [ # # ]: 0 : if (fdb_def_rule) {
10812 : : /* Create templates and table for default SQ miss flow rules - root table. */
10813 : 0 : hw_ctrl_fdb->esw_mgr_items_tmpl =
10814 : 0 : flow_hw_create_ctrl_esw_mgr_pattern_template(dev, error);
10815 [ # # ]: 0 : if (!hw_ctrl_fdb->esw_mgr_items_tmpl) {
10816 : 0 : DRV_LOG(ERR, "port %u failed to create E-Switch Manager item"
10817 : : " template for control flows", dev->data->port_id);
10818 : 0 : goto err;
10819 : : }
10820 : 0 : hw_ctrl_fdb->regc_jump_actions_tmpl =
10821 : 0 : flow_hw_create_ctrl_regc_jump_actions_template(dev, error);
10822 [ # # ]: 0 : if (!hw_ctrl_fdb->regc_jump_actions_tmpl) {
10823 : 0 : DRV_LOG(ERR, "port %u failed to create REG_C set and jump action template"
10824 : : " for control flows", dev->data->port_id);
10825 : 0 : goto err;
10826 : : }
10827 : 0 : hw_ctrl_fdb->hw_esw_sq_miss_root_tbl =
10828 : 0 : flow_hw_create_ctrl_sq_miss_root_table
10829 : : (dev, hw_ctrl_fdb->esw_mgr_items_tmpl,
10830 : : hw_ctrl_fdb->regc_jump_actions_tmpl, error);
10831 [ # # ]: 0 : if (!hw_ctrl_fdb->hw_esw_sq_miss_root_tbl) {
10832 : 0 : DRV_LOG(ERR, "port %u failed to create table for default sq miss (root table)"
10833 : : " for control flows", dev->data->port_id);
10834 : 0 : goto err;
10835 : : }
10836 : : /* Create templates and table for default SQ miss flow rules - non-root table. */
10837 : 0 : hw_ctrl_fdb->regc_sq_items_tmpl =
10838 : 0 : flow_hw_create_ctrl_regc_sq_pattern_template(dev, error);
10839 [ # # ]: 0 : if (!hw_ctrl_fdb->regc_sq_items_tmpl) {
10840 : 0 : DRV_LOG(ERR, "port %u failed to create SQ item template for"
10841 : : " control flows", dev->data->port_id);
10842 : 0 : goto err;
10843 : : }
10844 : 0 : hw_ctrl_fdb->port_actions_tmpl =
10845 : 0 : flow_hw_create_ctrl_port_actions_template(dev, error);
10846 [ # # ]: 0 : if (!hw_ctrl_fdb->port_actions_tmpl) {
10847 : 0 : DRV_LOG(ERR, "port %u failed to create port action template"
10848 : : " for control flows", dev->data->port_id);
10849 : 0 : goto err;
10850 : : }
10851 : 0 : hw_ctrl_fdb->hw_esw_sq_miss_tbl =
10852 : 0 : flow_hw_create_ctrl_sq_miss_table
10853 : : (dev, hw_ctrl_fdb->regc_sq_items_tmpl,
10854 : : hw_ctrl_fdb->port_actions_tmpl, error);
10855 [ # # ]: 0 : if (!hw_ctrl_fdb->hw_esw_sq_miss_tbl) {
10856 : 0 : DRV_LOG(ERR, "port %u failed to create table for default sq miss (non-root table)"
10857 : : " for control flows", dev->data->port_id);
10858 : 0 : goto err;
10859 : : }
10860 : : /* Create templates and table for default FDB jump flow rules. */
10861 : 0 : hw_ctrl_fdb->port_items_tmpl =
10862 : 0 : flow_hw_create_ctrl_port_pattern_template(dev, error);
10863 [ # # ]: 0 : if (!hw_ctrl_fdb->port_items_tmpl) {
10864 : 0 : DRV_LOG(ERR, "port %u failed to create SQ item template for"
10865 : : " control flows", dev->data->port_id);
10866 : 0 : goto err;
10867 : : }
10868 : 0 : hw_ctrl_fdb->jump_one_actions_tmpl =
10869 : 0 : flow_hw_create_ctrl_jump_actions_template
10870 : : (dev, MLX5_HW_LOWEST_USABLE_GROUP, error);
10871 [ # # ]: 0 : if (!hw_ctrl_fdb->jump_one_actions_tmpl) {
10872 : 0 : DRV_LOG(ERR, "port %u failed to create jump action template"
10873 : : " for control flows", dev->data->port_id);
10874 : 0 : goto err;
10875 : : }
10876 : 0 : hw_ctrl_fdb->hw_esw_zero_tbl = flow_hw_create_ctrl_jump_table
10877 : : (dev, hw_ctrl_fdb->port_items_tmpl,
10878 : : hw_ctrl_fdb->jump_one_actions_tmpl, error);
10879 [ # # ]: 0 : if (!hw_ctrl_fdb->hw_esw_zero_tbl) {
10880 : 0 : DRV_LOG(ERR, "port %u failed to create table for default jump to group 1"
10881 : : " for control flows", dev->data->port_id);
10882 : 0 : goto err;
10883 : : }
10884 : : }
10885 : : /* Create templates and table for default Tx metadata copy flow rule. */
10886 [ # # ]: 0 : if (!repr_matching && xmeta == MLX5_XMETA_MODE_META32_HWS) {
10887 : 0 : hw_ctrl_fdb->tx_meta_items_tmpl =
10888 : 0 : flow_hw_create_tx_default_mreg_copy_pattern_template(dev, error);
10889 [ # # ]: 0 : if (!hw_ctrl_fdb->tx_meta_items_tmpl) {
10890 : 0 : DRV_LOG(ERR, "port %u failed to Tx metadata copy pattern"
10891 : : " template for control flows", dev->data->port_id);
10892 : 0 : goto err;
10893 : : }
10894 : 0 : hw_ctrl_fdb->tx_meta_actions_tmpl =
10895 : 0 : flow_hw_create_tx_default_mreg_copy_actions_template(dev, error);
10896 [ # # ]: 0 : if (!hw_ctrl_fdb->tx_meta_actions_tmpl) {
10897 : 0 : DRV_LOG(ERR, "port %u failed to Tx metadata copy actions"
10898 : : " template for control flows", dev->data->port_id);
10899 : 0 : goto err;
10900 : : }
10901 : 0 : hw_ctrl_fdb->hw_tx_meta_cpy_tbl =
10902 : 0 : flow_hw_create_tx_default_mreg_copy_table
10903 : : (dev, hw_ctrl_fdb->tx_meta_items_tmpl,
10904 : : hw_ctrl_fdb->tx_meta_actions_tmpl, error);
10905 [ # # ]: 0 : if (!hw_ctrl_fdb->hw_tx_meta_cpy_tbl) {
10906 : 0 : DRV_LOG(ERR, "port %u failed to create table for default"
10907 : : " Tx metadata copy flow rule", dev->data->port_id);
10908 : 0 : goto err;
10909 : : }
10910 : : }
10911 : : /* Create LACP default miss table. */
10912 [ # # # # : 0 : if (!priv->sh->config.lacp_by_user && priv->pf_bond >= 0 && priv->master) {
# # ]
10913 : 0 : hw_ctrl_fdb->lacp_rx_items_tmpl =
10914 : 0 : flow_hw_create_lacp_rx_pattern_template(dev, error);
10915 [ # # ]: 0 : if (!hw_ctrl_fdb->lacp_rx_items_tmpl) {
10916 : 0 : DRV_LOG(ERR, "port %u failed to create pattern template"
10917 : : " for LACP Rx traffic", dev->data->port_id);
10918 : 0 : goto err;
10919 : : }
10920 : 0 : hw_ctrl_fdb->lacp_rx_actions_tmpl =
10921 : 0 : flow_hw_create_lacp_rx_actions_template(dev, error);
10922 [ # # ]: 0 : if (!hw_ctrl_fdb->lacp_rx_actions_tmpl) {
10923 : 0 : DRV_LOG(ERR, "port %u failed to create actions template"
10924 : : " for LACP Rx traffic", dev->data->port_id);
10925 : 0 : goto err;
10926 : : }
10927 : 0 : hw_ctrl_fdb->hw_lacp_rx_tbl = flow_hw_create_lacp_rx_table
10928 : : (dev, hw_ctrl_fdb->lacp_rx_items_tmpl,
10929 : : hw_ctrl_fdb->lacp_rx_actions_tmpl, error);
10930 [ # # ]: 0 : if (!hw_ctrl_fdb->hw_lacp_rx_tbl) {
10931 : 0 : DRV_LOG(ERR, "port %u failed to create template table for"
10932 : : " for LACP Rx traffic", dev->data->port_id);
10933 : 0 : goto err;
10934 : : }
10935 : : }
10936 : : return 0;
10937 : :
10938 : 0 : err:
10939 : 0 : flow_hw_cleanup_ctrl_fdb_tables(dev);
10940 : 0 : return -EINVAL;
10941 : : }
10942 : :
10943 : : static void
10944 : 0 : flow_hw_ct_mng_destroy(struct rte_eth_dev *dev,
10945 : : struct mlx5_aso_ct_pools_mng *ct_mng)
10946 : : {
10947 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
10948 : :
10949 : 0 : mlx5_aso_ct_queue_uninit(priv->sh, ct_mng);
10950 : 0 : mlx5_free(ct_mng);
10951 : 0 : }
10952 : :
10953 : : static void
10954 : 0 : flow_hw_ct_pool_destroy(struct rte_eth_dev *dev,
10955 : : struct mlx5_aso_ct_pool *pool)
10956 : : {
10957 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
10958 : :
10959 [ # # ]: 0 : if (pool->dr_action)
10960 : 0 : mlx5dr_action_destroy(pool->dr_action);
10961 [ # # ]: 0 : if (!priv->shared_host) {
10962 [ # # ]: 0 : if (pool->devx_obj)
10963 : 0 : claim_zero(mlx5_devx_cmd_destroy(pool->devx_obj));
10964 [ # # ]: 0 : if (pool->cts)
10965 : 0 : mlx5_ipool_destroy(pool->cts);
10966 : : }
10967 : 0 : mlx5_free(pool);
10968 : 0 : }
10969 : :
10970 : : static struct mlx5_aso_ct_pool *
10971 : 0 : flow_hw_ct_pool_create(struct rte_eth_dev *dev,
10972 : : uint32_t nb_conn_tracks)
10973 : : {
10974 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
10975 : : struct mlx5_aso_ct_pool *pool;
10976 : : struct mlx5_devx_obj *obj;
10977 : : uint32_t nb_cts = rte_align32pow2(nb_conn_tracks);
10978 : : uint32_t log_obj_size = rte_log2_u32(nb_cts);
10979 : 0 : struct mlx5_indexed_pool_config cfg = {
10980 : : .size = sizeof(struct mlx5_aso_ct_action),
10981 : : .trunk_size = 1 << 12,
10982 : : .per_core_cache = 1 << 13,
10983 : : .need_lock = 1,
10984 : 0 : .release_mem_en = !!priv->sh->config.reclaim_mode,
10985 : : .malloc = mlx5_malloc,
10986 : : .free = mlx5_free,
10987 : : .type = "mlx5_hw_ct_action",
10988 : : };
10989 : : int reg_id;
10990 : : uint32_t flags = 0;
10991 : :
10992 : 0 : pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
10993 [ # # ]: 0 : if (!pool) {
10994 : 0 : rte_errno = ENOMEM;
10995 : 0 : return NULL;
10996 : : }
10997 [ # # ]: 0 : if (!priv->shared_host) {
10998 : : /*
10999 : : * No need for local cache if CT number is a small number. Since
11000 : : * flow insertion rate will be very limited in that case. Here let's
11001 : : * set the number to less than default trunk size 4K.
11002 : : */
11003 [ # # ]: 0 : if (nb_cts <= cfg.trunk_size) {
11004 : 0 : cfg.per_core_cache = 0;
11005 : 0 : cfg.trunk_size = nb_cts;
11006 [ # # ]: 0 : } else if (nb_cts <= MLX5_HW_IPOOL_SIZE_THRESHOLD) {
11007 : 0 : cfg.per_core_cache = MLX5_HW_IPOOL_CACHE_MIN;
11008 : : }
11009 : 0 : cfg.max_idx = nb_cts;
11010 : 0 : pool->cts = mlx5_ipool_create(&cfg);
11011 [ # # ]: 0 : if (!pool->cts)
11012 : 0 : goto err;
11013 : 0 : obj = mlx5_devx_cmd_create_conn_track_offload_obj(priv->sh->cdev->ctx,
11014 : 0 : priv->sh->cdev->pdn,
11015 : : log_obj_size);
11016 [ # # ]: 0 : if (!obj) {
11017 : 0 : rte_errno = ENODATA;
11018 : 0 : DRV_LOG(ERR, "Failed to create conn_track_offload_obj using DevX.");
11019 : 0 : goto err;
11020 : : }
11021 : 0 : pool->devx_obj = obj;
11022 : : } else {
11023 : : struct rte_eth_dev *host_dev = priv->shared_host;
11024 : 0 : struct mlx5_priv *host_priv = host_dev->data->dev_private;
11025 : :
11026 : 0 : pool->devx_obj = host_priv->hws_ctpool->devx_obj;
11027 : 0 : pool->cts = host_priv->hws_ctpool->cts;
11028 : : MLX5_ASSERT(pool->cts);
11029 : : MLX5_ASSERT(!nb_conn_tracks);
11030 : : }
11031 : 0 : reg_id = mlx5_flow_get_reg_id(dev, MLX5_ASO_CONNTRACK, 0, NULL);
11032 : : flags |= MLX5DR_ACTION_FLAG_HWS_RX | MLX5DR_ACTION_FLAG_HWS_TX;
11033 [ # # # # ]: 0 : if (priv->sh->config.dv_esw_en && priv->master) {
11034 : 0 : flags |= ((is_unified_fdb(priv)) ?
11035 : : (MLX5DR_ACTION_FLAG_HWS_FDB_RX |
11036 : : MLX5DR_ACTION_FLAG_HWS_FDB_TX |
11037 [ # # ]: 0 : MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED) :
11038 : : MLX5DR_ACTION_FLAG_HWS_FDB);
11039 : : }
11040 : 0 : pool->dr_action = mlx5dr_action_create_aso_ct(priv->dr_ctx,
11041 : 0 : (struct mlx5dr_devx_obj *)pool->devx_obj,
11042 : 0 : reg_id - REG_C_0, flags);
11043 [ # # ]: 0 : if (!pool->dr_action)
11044 : 0 : goto err;
11045 : 0 : pool->sq = priv->ct_mng->aso_sqs;
11046 : : /* Assign the last extra ASO SQ as public SQ. */
11047 : 0 : pool->shared_sq = &priv->ct_mng->aso_sqs[priv->nb_queue - 1];
11048 : 0 : return pool;
11049 : 0 : err:
11050 : 0 : flow_hw_ct_pool_destroy(dev, pool);
11051 : 0 : return NULL;
11052 : : }
11053 : :
11054 : : static int
11055 : 0 : mlx5_flow_ct_init(struct rte_eth_dev *dev,
11056 : : uint32_t nb_conn_tracks,
11057 : : uint16_t nb_queue)
11058 : : {
11059 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11060 : : uint32_t mem_size;
11061 : : int ret = -ENOMEM;
11062 : :
11063 [ # # ]: 0 : if (!priv->shared_host) {
11064 : 0 : mem_size = sizeof(struct mlx5_aso_sq) * nb_queue +
11065 : : sizeof(*priv->ct_mng);
11066 : 0 : priv->ct_mng = mlx5_malloc(MLX5_MEM_ZERO, mem_size,
11067 : : RTE_CACHE_LINE_SIZE,
11068 : : SOCKET_ID_ANY);
11069 [ # # ]: 0 : if (!priv->ct_mng)
11070 : 0 : goto err;
11071 : 0 : ret = mlx5_aso_ct_queue_init(priv->sh, priv->ct_mng,
11072 : : nb_queue);
11073 [ # # ]: 0 : if (ret)
11074 : 0 : goto err;
11075 : : }
11076 : 0 : priv->hws_ctpool = flow_hw_ct_pool_create(dev, nb_conn_tracks);
11077 [ # # ]: 0 : if (!priv->hws_ctpool)
11078 : 0 : goto err;
11079 : 0 : priv->sh->ct_aso_en = 1;
11080 : 0 : return 0;
11081 : :
11082 : 0 : err:
11083 [ # # ]: 0 : if (priv->hws_ctpool) {
11084 : 0 : flow_hw_ct_pool_destroy(dev, priv->hws_ctpool);
11085 : 0 : priv->hws_ctpool = NULL;
11086 : : }
11087 [ # # ]: 0 : if (priv->ct_mng) {
11088 : 0 : flow_hw_ct_mng_destroy(dev, priv->ct_mng);
11089 : 0 : priv->ct_mng = NULL;
11090 : : }
11091 : : return ret;
11092 : : }
11093 : :
11094 : : static void
11095 : 0 : flow_hw_destroy_vlan(struct rte_eth_dev *dev)
11096 : : {
11097 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11098 : : enum mlx5dr_table_type i;
11099 : :
11100 [ # # ]: 0 : for (i = MLX5DR_TABLE_TYPE_NIC_RX; i < MLX5DR_TABLE_TYPE_MAX; i++) {
11101 [ # # ]: 0 : if (priv->hw_pop_vlan[i]) {
11102 : 0 : mlx5dr_action_destroy(priv->hw_pop_vlan[i]);
11103 : 0 : priv->hw_pop_vlan[i] = NULL;
11104 : : }
11105 [ # # ]: 0 : if (priv->hw_push_vlan[i]) {
11106 : 0 : mlx5dr_action_destroy(priv->hw_push_vlan[i]);
11107 : 0 : priv->hw_push_vlan[i] = NULL;
11108 : : }
11109 : : }
11110 : 0 : }
11111 : :
11112 : : static int
11113 : 0 : _create_vlan(struct mlx5_priv *priv, enum mlx5dr_table_type type)
11114 : : {
11115 : 0 : const enum mlx5dr_action_flags flags[MLX5DR_TABLE_TYPE_MAX] = {
11116 : : MLX5DR_ACTION_FLAG_HWS_RX,
11117 : : MLX5DR_ACTION_FLAG_HWS_TX,
11118 : : MLX5DR_ACTION_FLAG_HWS_FDB,
11119 : : MLX5DR_ACTION_FLAG_HWS_FDB_RX,
11120 : : MLX5DR_ACTION_FLAG_HWS_FDB_TX,
11121 : : MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED,
11122 : : };
11123 : :
11124 : : /* rte_errno is set in the mlx5dr_action* functions. */
11125 : 0 : priv->hw_pop_vlan[type] =
11126 : 0 : mlx5dr_action_create_pop_vlan(priv->dr_ctx, flags[type]);
11127 [ # # ]: 0 : if (!priv->hw_pop_vlan[type])
11128 : 0 : return -rte_errno;
11129 : 0 : priv->hw_push_vlan[type] =
11130 : 0 : mlx5dr_action_create_push_vlan(priv->dr_ctx, flags[type]);
11131 [ # # ]: 0 : if (!priv->hw_push_vlan[type])
11132 : 0 : return -rte_errno;
11133 : : return 0;
11134 : : }
11135 : :
11136 : : static int
11137 : 0 : flow_hw_create_vlan(struct rte_eth_dev *dev)
11138 : : {
11139 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11140 : : enum mlx5dr_table_type i, from, to;
11141 : : int rc;
11142 : : bool unified_fdb = is_unified_fdb(priv);
11143 : :
11144 [ # # ]: 0 : for (i = MLX5DR_TABLE_TYPE_NIC_RX; i <= MLX5DR_TABLE_TYPE_NIC_TX; i++) {
11145 : 0 : rc = _create_vlan(priv, i);
11146 [ # # ]: 0 : if (rc)
11147 : 0 : return rc;
11148 : : }
11149 [ # # ]: 0 : from = unified_fdb ? MLX5DR_TABLE_TYPE_FDB_RX : MLX5DR_TABLE_TYPE_FDB;
11150 [ # # ]: 0 : to = unified_fdb ? MLX5DR_TABLE_TYPE_FDB_UNIFIED : MLX5DR_TABLE_TYPE_FDB;
11151 [ # # # # ]: 0 : if (priv->sh->config.dv_esw_en && priv->master) {
11152 [ # # ]: 0 : for (i = from; i <= to; i++) {
11153 : 0 : rc = _create_vlan(priv, i);
11154 [ # # ]: 0 : if (rc)
11155 : 0 : return rc;
11156 : : }
11157 : : }
11158 : : return 0;
11159 : : }
11160 : :
11161 : : static void
11162 : 0 : flow_hw_cleanup_ctrl_rx_tables(struct rte_eth_dev *dev)
11163 : : {
11164 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11165 : : unsigned int i;
11166 : : unsigned int j;
11167 : :
11168 [ # # ]: 0 : if (!priv->hw_ctrl_rx)
11169 : : return;
11170 [ # # ]: 0 : for (i = 0; i < MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_MAX; ++i) {
11171 [ # # ]: 0 : for (j = 0; j < MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX; ++j) {
11172 : 0 : struct rte_flow_template_table *tbl = priv->hw_ctrl_rx->tables[i][j].tbl;
11173 : 0 : struct rte_flow_pattern_template *pt = priv->hw_ctrl_rx->tables[i][j].pt;
11174 : :
11175 [ # # ]: 0 : if (tbl)
11176 : 0 : claim_zero(flow_hw_table_destroy(dev, tbl, NULL));
11177 [ # # ]: 0 : if (pt)
11178 : 0 : claim_zero(flow_hw_pattern_template_destroy(dev, pt, NULL));
11179 : : }
11180 : : }
11181 [ # # ]: 0 : for (i = 0; i < MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX; ++i) {
11182 : 0 : struct rte_flow_actions_template *at = priv->hw_ctrl_rx->rss[i];
11183 : :
11184 [ # # ]: 0 : if (at)
11185 : 0 : claim_zero(flow_hw_actions_template_destroy(dev, at, NULL));
11186 : : }
11187 : 0 : mlx5_free(priv->hw_ctrl_rx);
11188 : 0 : priv->hw_ctrl_rx = NULL;
11189 : : }
11190 : :
11191 : : static uint64_t
11192 : : flow_hw_ctrl_rx_rss_type_hash_types(const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
11193 : : {
11194 : : switch (rss_type) {
11195 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_NON_IP:
11196 : : return 0;
11197 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4:
11198 : : return RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_FRAG_IPV4 | RTE_ETH_RSS_NONFRAG_IPV4_OTHER;
11199 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_UDP:
11200 : : return RTE_ETH_RSS_NONFRAG_IPV4_UDP;
11201 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_TCP:
11202 : : return RTE_ETH_RSS_NONFRAG_IPV4_TCP;
11203 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6:
11204 : : return RTE_ETH_RSS_IPV6 | RTE_ETH_RSS_FRAG_IPV6 | RTE_ETH_RSS_NONFRAG_IPV6_OTHER;
11205 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_UDP:
11206 : : return RTE_ETH_RSS_NONFRAG_IPV6_UDP | RTE_ETH_RSS_IPV6_UDP_EX;
11207 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_TCP:
11208 : : return RTE_ETH_RSS_NONFRAG_IPV6_TCP | RTE_ETH_RSS_IPV6_TCP_EX;
11209 : : default:
11210 : : /* Should not reach here. */
11211 : : MLX5_ASSERT(false);
11212 : : return 0;
11213 : : }
11214 : : }
11215 : :
11216 : : static struct rte_flow_actions_template *
11217 : 0 : flow_hw_create_ctrl_rx_rss_template(struct rte_eth_dev *dev,
11218 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
11219 : : {
11220 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11221 : 0 : struct rte_flow_actions_template_attr attr = {
11222 : : .ingress = 1,
11223 : : };
11224 : : uint16_t queue[RTE_MAX_QUEUES_PER_PORT];
11225 : 0 : struct rte_flow_action_rss rss_conf = {
11226 : : .func = RTE_ETH_HASH_FUNCTION_DEFAULT,
11227 : : .level = 0,
11228 : : .types = 0,
11229 : 0 : .key_len = priv->rss_conf.rss_key_len,
11230 : 0 : .key = priv->rss_conf.rss_key,
11231 : 0 : .queue_num = priv->reta_idx_n,
11232 : : .queue = queue,
11233 : : };
11234 : 0 : struct rte_flow_action actions[] = {
11235 : : {
11236 : : .type = RTE_FLOW_ACTION_TYPE_RSS,
11237 : : .conf = &rss_conf,
11238 : : },
11239 : : {
11240 : : .type = RTE_FLOW_ACTION_TYPE_END,
11241 : : }
11242 : : };
11243 [ # # ]: 0 : struct rte_flow_action masks[] = {
11244 : : {
11245 : : .type = RTE_FLOW_ACTION_TYPE_RSS,
11246 : : .conf = &rss_conf,
11247 : : },
11248 : : {
11249 : : .type = RTE_FLOW_ACTION_TYPE_END,
11250 : : }
11251 : : };
11252 : : struct rte_flow_actions_template *at;
11253 : : struct rte_flow_error error;
11254 : : unsigned int i;
11255 : :
11256 : : MLX5_ASSERT(priv->reta_idx_n > 0 && priv->reta_idx);
11257 : : /* Select proper RSS hash types and based on that configure the actions template. */
11258 : 0 : rss_conf.types = flow_hw_ctrl_rx_rss_type_hash_types(rss_type);
11259 [ # # ]: 0 : if (rss_conf.types) {
11260 [ # # ]: 0 : for (i = 0; i < priv->reta_idx_n; ++i)
11261 : 0 : queue[i] = (*priv->reta_idx)[i];
11262 : : } else {
11263 : 0 : rss_conf.queue_num = 1;
11264 : 0 : queue[0] = (*priv->reta_idx)[0];
11265 : : }
11266 : : at = flow_hw_actions_template_create(dev, &attr, actions, masks, &error);
11267 [ # # ]: 0 : if (!at)
11268 [ # # ]: 0 : DRV_LOG(ERR,
11269 : : "Failed to create ctrl flow actions template: rte_errno(%d), type(%d): %s",
11270 : : rte_errno, error.type,
11271 : : error.message ? error.message : "(no stated reason)");
11272 : 0 : return at;
11273 : : }
11274 : :
11275 : : static uint32_t ctrl_rx_rss_priority_map[MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX] = {
11276 : : [MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_NON_IP] = MLX5_HW_CTRL_RX_PRIO_L2,
11277 : : [MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4] = MLX5_HW_CTRL_RX_PRIO_L3,
11278 : : [MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_UDP] = MLX5_HW_CTRL_RX_PRIO_L4,
11279 : : [MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_TCP] = MLX5_HW_CTRL_RX_PRIO_L4,
11280 : : [MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6] = MLX5_HW_CTRL_RX_PRIO_L3,
11281 : : [MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_UDP] = MLX5_HW_CTRL_RX_PRIO_L4,
11282 : : [MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_TCP] = MLX5_HW_CTRL_RX_PRIO_L4,
11283 : : };
11284 : :
11285 : : static uint32_t ctrl_rx_nb_flows_map[MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_MAX] = {
11286 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL] = 1,
11287 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL_MCAST] = 1,
11288 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST] = 1,
11289 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST_VLAN] = MLX5_MAX_VLAN_IDS,
11290 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST] = 1,
11291 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST_VLAN] = MLX5_MAX_VLAN_IDS,
11292 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST] = 1,
11293 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST_VLAN] = MLX5_MAX_VLAN_IDS,
11294 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC] = MLX5_MAX_UC_MAC_ADDRESSES,
11295 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN] =
11296 : : MLX5_MAX_UC_MAC_ADDRESSES * MLX5_MAX_VLAN_IDS,
11297 : : };
11298 : :
11299 : : static struct rte_flow_template_table_attr
11300 : : flow_hw_get_ctrl_rx_table_attr(enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type,
11301 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
11302 : : {
11303 : 0 : return (struct rte_flow_template_table_attr){
11304 : : .flow_attr = {
11305 : : .group = 0,
11306 : 0 : .priority = ctrl_rx_rss_priority_map[rss_type],
11307 : : .ingress = 1,
11308 : : },
11309 : 0 : .nb_flows = ctrl_rx_nb_flows_map[eth_pattern_type],
11310 : : };
11311 : : }
11312 : :
11313 : : static struct rte_flow_item
11314 : : flow_hw_get_ctrl_rx_eth_item(const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type)
11315 : : {
11316 : : struct rte_flow_item item = {
11317 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
11318 : : .mask = NULL,
11319 : : };
11320 : :
11321 : 0 : switch (eth_pattern_type) {
11322 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL:
11323 : : item.mask = &ctrl_rx_eth_promisc_mask;
11324 : : break;
11325 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL_MCAST:
11326 : : item.mask = &ctrl_rx_eth_mcast_mask;
11327 : 0 : break;
11328 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST:
11329 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST_VLAN:
11330 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC:
11331 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN:
11332 : : item.mask = &ctrl_rx_eth_dmac_mask;
11333 : 0 : break;
11334 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST:
11335 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST_VLAN:
11336 : : item.mask = &ctrl_rx_eth_ipv4_mcast_mask;
11337 : 0 : break;
11338 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST:
11339 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST_VLAN:
11340 : : item.mask = &ctrl_rx_eth_ipv6_mcast_mask;
11341 : 0 : break;
11342 : 0 : default:
11343 : : /* Should not reach here - ETH mask must be present. */
11344 : : item.type = RTE_FLOW_ITEM_TYPE_END;
11345 : : MLX5_ASSERT(false);
11346 : 0 : break;
11347 : : }
11348 : 0 : return item;
11349 : : }
11350 : :
11351 : : static struct rte_flow_item
11352 : : flow_hw_get_ctrl_rx_vlan_item(const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type)
11353 : : {
11354 : : struct rte_flow_item item = {
11355 : : .type = RTE_FLOW_ITEM_TYPE_VOID,
11356 : : .mask = NULL,
11357 : : };
11358 : :
11359 [ # # ]: 0 : switch (eth_pattern_type) {
11360 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST_VLAN:
11361 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST_VLAN:
11362 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST_VLAN:
11363 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN:
11364 : : item.type = RTE_FLOW_ITEM_TYPE_VLAN;
11365 : : item.mask = &rte_flow_item_vlan_mask;
11366 : 0 : break;
11367 : : default:
11368 : : /* Nothing to update. */
11369 : : break;
11370 : : }
11371 : 0 : return item;
11372 : : }
11373 : :
11374 : : static struct rte_flow_item
11375 : : flow_hw_get_ctrl_rx_l3_item(const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
11376 : : {
11377 : : struct rte_flow_item item = {
11378 : : .type = RTE_FLOW_ITEM_TYPE_VOID,
11379 : : .mask = NULL,
11380 : : };
11381 : :
11382 [ # # # ]: 0 : switch (rss_type) {
11383 : 0 : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4:
11384 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_UDP:
11385 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_TCP:
11386 : : item.type = RTE_FLOW_ITEM_TYPE_IPV4;
11387 : 0 : break;
11388 : 0 : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6:
11389 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_UDP:
11390 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_TCP:
11391 : : item.type = RTE_FLOW_ITEM_TYPE_IPV6;
11392 : 0 : break;
11393 : : default:
11394 : : /* Nothing to update. */
11395 : : break;
11396 : : }
11397 : 0 : return item;
11398 : : }
11399 : :
11400 : : static struct rte_flow_item
11401 : : flow_hw_get_ctrl_rx_l4_item(const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
11402 : : {
11403 : : struct rte_flow_item item = {
11404 : : .type = RTE_FLOW_ITEM_TYPE_VOID,
11405 : : .mask = NULL,
11406 : : };
11407 : :
11408 [ # # # ]: 0 : switch (rss_type) {
11409 : 0 : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_UDP:
11410 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_UDP:
11411 : : item.type = RTE_FLOW_ITEM_TYPE_UDP;
11412 : 0 : break;
11413 : 0 : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_TCP:
11414 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_TCP:
11415 : : item.type = RTE_FLOW_ITEM_TYPE_TCP;
11416 : 0 : break;
11417 : : default:
11418 : : /* Nothing to update. */
11419 : : break;
11420 : : }
11421 : 0 : return item;
11422 : : }
11423 : :
11424 : : static struct rte_flow_pattern_template *
11425 : 0 : flow_hw_create_ctrl_rx_pattern_template
11426 : : (struct rte_eth_dev *dev,
11427 : : const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type,
11428 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
11429 : : {
11430 : 0 : const struct rte_flow_pattern_template_attr attr = {
11431 : : .relaxed_matching = 0,
11432 : : .ingress = 1,
11433 : : };
11434 [ # # # # : 0 : struct rte_flow_item items[] = {
# # ]
11435 : : /* Matching patterns */
11436 : : flow_hw_get_ctrl_rx_eth_item(eth_pattern_type),
11437 : : flow_hw_get_ctrl_rx_vlan_item(eth_pattern_type),
11438 : : flow_hw_get_ctrl_rx_l3_item(rss_type),
11439 : : flow_hw_get_ctrl_rx_l4_item(rss_type),
11440 : : /* Terminate pattern */
11441 : : { .type = RTE_FLOW_ITEM_TYPE_END }
11442 : : };
11443 : :
11444 : 0 : return flow_hw_pattern_template_create(dev, &attr, items, NULL);
11445 : : }
11446 : :
11447 : : static int
11448 : 0 : flow_hw_create_ctrl_rx_tables(struct rte_eth_dev *dev)
11449 : : {
11450 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11451 : : unsigned int i;
11452 : : unsigned int j;
11453 : : int ret;
11454 : :
11455 : : MLX5_ASSERT(!priv->hw_ctrl_rx);
11456 : 0 : priv->hw_ctrl_rx = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*priv->hw_ctrl_rx),
11457 : : RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
11458 [ # # ]: 0 : if (!priv->hw_ctrl_rx) {
11459 : 0 : DRV_LOG(ERR, "Failed to allocate memory for Rx control flow tables");
11460 : 0 : rte_errno = ENOMEM;
11461 : 0 : return -rte_errno;
11462 : : }
11463 : : /* Create all pattern template variants. */
11464 [ # # ]: 0 : for (i = 0; i < MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_MAX; ++i) {
11465 : : enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type = i;
11466 : :
11467 [ # # ]: 0 : for (j = 0; j < MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX; ++j) {
11468 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type = j;
11469 : : struct rte_flow_template_table_attr attr;
11470 : : struct rte_flow_pattern_template *pt;
11471 : :
11472 : : attr = flow_hw_get_ctrl_rx_table_attr(eth_pattern_type, rss_type);
11473 : 0 : pt = flow_hw_create_ctrl_rx_pattern_template(dev, eth_pattern_type,
11474 : : rss_type);
11475 [ # # ]: 0 : if (!pt)
11476 : 0 : goto err;
11477 : 0 : priv->hw_ctrl_rx->tables[i][j].attr = attr;
11478 : 0 : priv->hw_ctrl_rx->tables[i][j].pt = pt;
11479 : : }
11480 : : }
11481 : : return 0;
11482 : : err:
11483 : 0 : ret = rte_errno;
11484 : 0 : flow_hw_cleanup_ctrl_rx_tables(dev);
11485 : 0 : rte_errno = ret;
11486 : 0 : return -ret;
11487 : : }
11488 : :
11489 : : void
11490 : 0 : mlx5_flow_hw_cleanup_ctrl_rx_templates(struct rte_eth_dev *dev)
11491 : : {
11492 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11493 : : struct mlx5_flow_hw_ctrl_rx *hw_ctrl_rx;
11494 : : unsigned int i;
11495 : : unsigned int j;
11496 : :
11497 [ # # ]: 0 : if (!priv->dr_ctx)
11498 : : return;
11499 [ # # ]: 0 : if (!priv->hw_ctrl_rx)
11500 : : return;
11501 : : hw_ctrl_rx = priv->hw_ctrl_rx;
11502 [ # # ]: 0 : for (i = 0; i < MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_MAX; ++i) {
11503 [ # # ]: 0 : for (j = 0; j < MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX; ++j) {
11504 : : struct mlx5_flow_hw_ctrl_rx_table *tmpls = &hw_ctrl_rx->tables[i][j];
11505 : :
11506 [ # # ]: 0 : if (tmpls->tbl) {
11507 : 0 : claim_zero(flow_hw_table_destroy(dev, tmpls->tbl, NULL));
11508 : 0 : tmpls->tbl = NULL;
11509 : : }
11510 : : }
11511 : : }
11512 [ # # ]: 0 : for (j = 0; j < MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX; ++j) {
11513 [ # # ]: 0 : if (hw_ctrl_rx->rss[j]) {
11514 : 0 : claim_zero(flow_hw_actions_template_destroy(dev, hw_ctrl_rx->rss[j], NULL));
11515 : 0 : hw_ctrl_rx->rss[j] = NULL;
11516 : : }
11517 : : }
11518 : : }
11519 : :
11520 : : /**
11521 : : * Copy the provided HWS configuration to a newly allocated buffer.
11522 : : *
11523 : : * @param[in] port_attr
11524 : : * Port configuration attributes.
11525 : : * @param[in] nb_queue
11526 : : * Number of queue.
11527 : : * @param[in] queue_attr
11528 : : * Array that holds attributes for each flow queue.
11529 : : * @param[in] nt_mode
11530 : : * Non template mode.
11531 : : *
11532 : : * @return
11533 : : * Pointer to copied HWS configuration is returned on success.
11534 : : * Otherwise, NULL is returned and rte_errno is set.
11535 : : */
11536 : : static struct mlx5_flow_hw_attr *
11537 : 0 : flow_hw_alloc_copy_config(const struct rte_flow_port_attr *port_attr,
11538 : : const uint16_t nb_queue,
11539 : : const struct rte_flow_queue_attr *queue_attr[],
11540 : : bool nt_mode,
11541 : : struct rte_flow_error *error)
11542 : : {
11543 : : struct mlx5_flow_hw_attr *hw_attr;
11544 : : size_t hw_attr_size;
11545 : : unsigned int i;
11546 : :
11547 : 0 : hw_attr_size = sizeof(*hw_attr) + nb_queue * sizeof(*hw_attr->queue_attr);
11548 : 0 : hw_attr = mlx5_malloc(MLX5_MEM_ZERO, hw_attr_size, 0, SOCKET_ID_ANY);
11549 [ # # ]: 0 : if (!hw_attr) {
11550 : 0 : rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11551 : : "Not enough memory to store configuration");
11552 : 0 : return NULL;
11553 : : }
11554 : 0 : memcpy(&hw_attr->port_attr, port_attr, sizeof(*port_attr));
11555 : 0 : hw_attr->nb_queue = nb_queue;
11556 : : /* Queue attributes are placed after the mlx5_flow_hw_attr. */
11557 : 0 : hw_attr->queue_attr = (struct rte_flow_queue_attr *)(hw_attr + 1);
11558 [ # # ]: 0 : for (i = 0; i < nb_queue; ++i)
11559 : 0 : memcpy(&hw_attr->queue_attr[i], queue_attr[i], sizeof(hw_attr->queue_attr[i]));
11560 : 0 : hw_attr->nt_mode = nt_mode;
11561 : 0 : return hw_attr;
11562 : : }
11563 : :
11564 : : /**
11565 : : * Compares the preserved HWS configuration with the provided one.
11566 : : *
11567 : : * @param[in] hw_attr
11568 : : * Pointer to preserved HWS configuration.
11569 : : * @param[in] new_pa
11570 : : * Port configuration attributes to compare.
11571 : : * @param[in] new_nbq
11572 : : * Number of queues to compare.
11573 : : * @param[in] new_qa
11574 : : * Array that holds attributes for each flow queue.
11575 : : *
11576 : : * @return
11577 : : * True if configurations are the same, false otherwise.
11578 : : */
11579 : : static bool
11580 : 0 : flow_hw_compare_config(const struct mlx5_flow_hw_attr *hw_attr,
11581 : : const struct rte_flow_port_attr *new_pa,
11582 : : const uint16_t new_nbq,
11583 : : const struct rte_flow_queue_attr *new_qa[])
11584 : : {
11585 : : const struct rte_flow_port_attr *old_pa = &hw_attr->port_attr;
11586 : 0 : const uint16_t old_nbq = hw_attr->nb_queue;
11587 : 0 : const struct rte_flow_queue_attr *old_qa = hw_attr->queue_attr;
11588 : : unsigned int i;
11589 : :
11590 [ # # ]: 0 : if (old_pa->nb_counters != new_pa->nb_counters ||
11591 [ # # ]: 0 : old_pa->nb_aging_objects != new_pa->nb_aging_objects ||
11592 [ # # ]: 0 : old_pa->nb_meters != new_pa->nb_meters ||
11593 [ # # ]: 0 : old_pa->nb_conn_tracks != new_pa->nb_conn_tracks ||
11594 [ # # ]: 0 : old_pa->flags != new_pa->flags)
11595 : : return false;
11596 [ # # ]: 0 : if (old_nbq != new_nbq)
11597 : : return false;
11598 [ # # ]: 0 : for (i = 0; i < old_nbq; ++i)
11599 [ # # ]: 0 : if (old_qa[i].size != new_qa[i]->size)
11600 : : return false;
11601 : : return true;
11602 : : }
11603 : :
11604 : : /*
11605 : : * No need to explicitly release drop action templates on port stop.
11606 : : * Drop action templates release with other action templates during
11607 : : * mlx5_dev_close -> flow_hw_resource_release -> flow_hw_actions_template_destroy
11608 : : */
11609 : : static void
11610 : 0 : flow_hw_action_template_drop_release(struct rte_eth_dev *dev)
11611 : : {
11612 : : int i;
11613 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11614 : :
11615 [ # # ]: 0 : for (i = 0; i < MLX5DR_TABLE_TYPE_MAX; i++) {
11616 [ # # ]: 0 : if (!priv->action_template_drop[i])
11617 : 0 : continue;
11618 : 0 : flow_hw_actions_template_destroy(dev,
11619 : : priv->action_template_drop[i],
11620 : : NULL);
11621 : 0 : priv->action_template_drop[i] = NULL;
11622 : : }
11623 : 0 : }
11624 : :
11625 : : static int
11626 : 0 : flow_hw_action_template_drop_init(struct rte_eth_dev *dev,
11627 : : struct rte_flow_error *error)
11628 : : {
11629 : : uint32_t i, from, to;
11630 : 0 : const struct rte_flow_action drop[2] = {
11631 : : [0] = { .type = RTE_FLOW_ACTION_TYPE_DROP },
11632 : : [1] = { .type = RTE_FLOW_ACTION_TYPE_END },
11633 : : };
11634 : : const struct rte_flow_action *actions = drop;
11635 : : const struct rte_flow_action *masks = drop;
11636 : 0 : const struct rte_flow_actions_template_attr attr[MLX5DR_TABLE_TYPE_MAX] = {
11637 : : [MLX5DR_TABLE_TYPE_NIC_RX] = { .ingress = 1 },
11638 : : [MLX5DR_TABLE_TYPE_NIC_TX] = { .egress = 1 },
11639 : : [MLX5DR_TABLE_TYPE_FDB] = { .transfer = 1 },
11640 : : [MLX5DR_TABLE_TYPE_FDB_RX] = { .transfer = 1 },
11641 : : [MLX5DR_TABLE_TYPE_FDB_TX] = { .transfer = 1 },
11642 : : [MLX5DR_TABLE_TYPE_FDB_UNIFIED] = { .transfer = 1 },
11643 : : };
11644 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11645 : :
11646 : : from = MLX5DR_TABLE_TYPE_NIC_RX;
11647 : : to = MLX5DR_TABLE_TYPE_NIC_TX;
11648 [ # # ]: 0 : for (i = from; i <= to; i++) {
11649 : 0 : priv->action_template_drop[i] =
11650 : 0 : flow_hw_actions_template_create(dev, &attr[i], actions, masks, error);
11651 [ # # ]: 0 : if (!priv->action_template_drop[i])
11652 : : return -1;
11653 : : }
11654 : :
11655 [ # # # # ]: 0 : if (!(priv->sh->config.dv_esw_en && priv->master))
11656 : : return 0;
11657 : :
11658 : : from = MLX5DR_TABLE_TYPE_FDB;
11659 [ # # ]: 0 : to = is_unified_fdb(priv) ? MLX5DR_TABLE_TYPE_FDB_UNIFIED : MLX5DR_TABLE_TYPE_FDB;
11660 [ # # ]: 0 : for (i = from; i <= to; i++) {
11661 : 0 : priv->action_template_drop[i] =
11662 : 0 : flow_hw_actions_template_create(dev, &attr[i], actions, masks, error);
11663 [ # # ]: 0 : if (!priv->action_template_drop[i])
11664 : : return -1;
11665 : : }
11666 : : return 0;
11667 : : }
11668 : :
11669 : : static void
11670 : 0 : __flow_hw_resource_release(struct rte_eth_dev *dev, bool ctx_close)
11671 : : {
11672 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11673 : : struct rte_flow_template_table *tbl, *temp_tbl;
11674 : : struct rte_flow_pattern_template *it, *temp_it;
11675 : : struct rte_flow_actions_template *at, *temp_at;
11676 : : struct mlx5_flow_group *grp, *temp_grp;
11677 : : uint32_t i;
11678 : :
11679 : 0 : flow_hw_rxq_flag_set(dev, false);
11680 : 0 : flow_hw_flush_all_ctrl_flows(dev);
11681 : 0 : flow_hw_cleanup_ctrl_fdb_tables(dev);
11682 : 0 : flow_hw_cleanup_tx_repr_tagging(dev);
11683 : 0 : flow_hw_cleanup_ctrl_rx_tables(dev);
11684 : 0 : flow_hw_action_template_drop_release(dev);
11685 : 0 : grp = LIST_FIRST(&priv->flow_hw_grp);
11686 [ # # ]: 0 : while (grp) {
11687 : 0 : temp_grp = LIST_NEXT(grp, next);
11688 : 0 : claim_zero(flow_hw_group_unset_miss_group(dev, grp, NULL));
11689 : : grp = temp_grp;
11690 : : }
11691 : 0 : tbl = LIST_FIRST(&priv->flow_hw_tbl_ongo);
11692 [ # # ]: 0 : while (tbl) {
11693 : 0 : temp_tbl = LIST_NEXT(tbl, next);
11694 : 0 : claim_zero(flow_hw_table_destroy(dev, tbl, NULL));
11695 : : tbl = temp_tbl;
11696 : : }
11697 : 0 : tbl = LIST_FIRST(&priv->flow_hw_tbl);
11698 [ # # ]: 0 : while (tbl) {
11699 : 0 : temp_tbl = LIST_NEXT(tbl, next);
11700 : 0 : claim_zero(flow_hw_table_destroy(dev, tbl, NULL));
11701 : : tbl = temp_tbl;
11702 : : }
11703 : 0 : it = LIST_FIRST(&priv->flow_hw_itt);
11704 [ # # ]: 0 : while (it) {
11705 : 0 : temp_it = LIST_NEXT(it, next);
11706 : 0 : claim_zero(flow_hw_pattern_template_destroy(dev, it, NULL));
11707 : : it = temp_it;
11708 : : }
11709 : 0 : at = LIST_FIRST(&priv->flow_hw_at);
11710 [ # # ]: 0 : while (at) {
11711 : 0 : temp_at = LIST_NEXT(at, next);
11712 : 0 : claim_zero(flow_hw_actions_template_destroy(dev, at, NULL));
11713 : : at = temp_at;
11714 : : }
11715 [ # # ]: 0 : for (i = 0; i < MLX5_HW_ACTION_FLAG_MAX; i++) {
11716 [ # # ]: 0 : if (priv->hw_drop[i])
11717 : 0 : mlx5dr_action_destroy(priv->hw_drop[i]);
11718 [ # # ]: 0 : if (priv->hw_tag[i])
11719 : 0 : mlx5dr_action_destroy(priv->hw_tag[i]);
11720 : : }
11721 [ # # ]: 0 : if (priv->hw_def_miss)
11722 : 0 : mlx5dr_action_destroy(priv->hw_def_miss);
11723 : 0 : flow_hw_destroy_nat64_actions(priv);
11724 : 0 : flow_hw_destroy_vlan(dev);
11725 : 0 : flow_hw_destroy_send_to_kernel_action(priv);
11726 : 0 : flow_hw_free_vport_actions(priv);
11727 [ # # ]: 0 : if (priv->acts_ipool) {
11728 : 0 : mlx5_ipool_destroy(priv->acts_ipool);
11729 : 0 : priv->acts_ipool = NULL;
11730 : : }
11731 [ # # ]: 0 : if (priv->hws_age_req)
11732 : 0 : mlx5_hws_age_pool_destroy(priv);
11733 [ # # # # ]: 0 : if (!priv->shared_host && priv->hws_cpool) {
11734 : 0 : mlx5_hws_cnt_pool_destroy(priv->sh, priv->hws_cpool);
11735 : 0 : priv->hws_cpool = NULL;
11736 : : }
11737 [ # # ]: 0 : if (priv->hws_ctpool) {
11738 : 0 : flow_hw_ct_pool_destroy(dev, priv->hws_ctpool);
11739 : 0 : priv->hws_ctpool = NULL;
11740 : : }
11741 [ # # ]: 0 : if (priv->ct_mng) {
11742 : 0 : flow_hw_ct_mng_destroy(dev, priv->ct_mng);
11743 : 0 : priv->ct_mng = NULL;
11744 : : }
11745 : 0 : mlx5_flow_quota_destroy(dev);
11746 [ # # ]: 0 : if (priv->hw_q) {
11747 [ # # ]: 0 : for (i = 0; i < priv->nb_queue; i++) {
11748 : 0 : struct mlx5_hw_q *hwq = &priv->hw_q[i];
11749 : 0 : rte_ring_free(hwq->indir_iq);
11750 : 0 : rte_ring_free(hwq->indir_cq);
11751 : 0 : rte_ring_free(hwq->flow_transfer_pending);
11752 : 0 : rte_ring_free(hwq->flow_transfer_completed);
11753 : : }
11754 : 0 : mlx5_free(priv->hw_q);
11755 : 0 : priv->hw_q = NULL;
11756 : : }
11757 [ # # ]: 0 : if (ctx_close) {
11758 [ # # ]: 0 : if (priv->dr_ctx) {
11759 : 0 : claim_zero(mlx5dr_context_close(priv->dr_ctx));
11760 : 0 : priv->dr_ctx = NULL;
11761 : : }
11762 : : }
11763 [ # # ]: 0 : if (priv->shared_host) {
11764 : 0 : struct mlx5_priv *host_priv = priv->shared_host->data->dev_private;
11765 : 0 : rte_atomic_fetch_sub_explicit(&host_priv->shared_refcnt, 1,
11766 : : rte_memory_order_relaxed);
11767 : 0 : priv->shared_host = NULL;
11768 : : }
11769 [ # # ]: 0 : if (priv->hw_attr) {
11770 : 0 : mlx5_free(priv->hw_attr);
11771 : 0 : priv->hw_attr = NULL;
11772 : : }
11773 : 0 : priv->nb_queue = 0;
11774 : 0 : }
11775 : :
11776 : : static __rte_always_inline struct rte_ring *
11777 : : mlx5_hwq_ring_create(uint16_t port_id, uint32_t queue, uint32_t size, const char *str)
11778 : : {
11779 : : char mz_name[RTE_MEMZONE_NAMESIZE];
11780 : :
11781 : : snprintf(mz_name, sizeof(mz_name), "port_%u_%s_%u", port_id, str, queue);
11782 : 0 : return rte_ring_create(mz_name, size, SOCKET_ID_ANY,
11783 : : RING_F_SP_ENQ | RING_F_SC_DEQ | RING_F_EXACT_SZ);
11784 : : }
11785 : :
11786 : : static int
11787 : 0 : flow_hw_validate_attributes(const struct rte_flow_port_attr *port_attr,
11788 : : uint16_t nb_queue,
11789 : : const struct rte_flow_queue_attr *queue_attr[],
11790 : : bool nt_mode, struct rte_flow_error *error)
11791 : : {
11792 : : uint32_t size;
11793 : : unsigned int i;
11794 : :
11795 [ # # ]: 0 : if (port_attr == NULL)
11796 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11797 : : "Port attributes must be non-NULL");
11798 : :
11799 [ # # ]: 0 : if (nb_queue == 0 && !nt_mode)
11800 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11801 : : "At least one flow queue is required");
11802 : :
11803 [ # # ]: 0 : if (queue_attr == NULL)
11804 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11805 : : "Queue attributes must be non-NULL");
11806 : :
11807 : 0 : size = queue_attr[0]->size;
11808 [ # # ]: 0 : for (i = 1; i < nb_queue; ++i) {
11809 [ # # ]: 0 : if (queue_attr[i]->size != size)
11810 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11811 : : NULL,
11812 : : "All flow queues must have the same size");
11813 : : }
11814 : :
11815 : : return 0;
11816 : : }
11817 : :
11818 : : /**
11819 : : * Configure port HWS resources.
11820 : : *
11821 : : * @param[in] dev
11822 : : * Pointer to the rte_eth_dev structure.
11823 : : * @param[in] port_attr
11824 : : * Port configuration attributes.
11825 : : * @param[in] nb_queue
11826 : : * Number of queue.
11827 : : * @param[in] queue_attr
11828 : : * Array that holds attributes for each flow queue.
11829 : : * @param[in] nt_mode
11830 : : * Non-template mode.
11831 : : * @param[out] error
11832 : : * Pointer to error structure.
11833 : : *
11834 : : * @return
11835 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
11836 : : */
11837 : : static int
11838 : 0 : __flow_hw_configure(struct rte_eth_dev *dev,
11839 : : const struct rte_flow_port_attr *port_attr,
11840 : : uint16_t nb_queue,
11841 : : const struct rte_flow_queue_attr *queue_attr[],
11842 : : bool nt_mode,
11843 : : struct rte_flow_error *error)
11844 : : {
11845 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11846 : : struct mlx5_priv *host_priv = NULL;
11847 : 0 : struct mlx5dr_context_attr dr_ctx_attr = {0};
11848 : : struct mlx5_hw_q *hw_q;
11849 : : struct mlx5_hw_q_job *job = NULL;
11850 : : uint32_t mem_size, i, j;
11851 : 0 : struct mlx5_indexed_pool_config cfg = {
11852 : : .size = sizeof(struct mlx5_action_construct_data),
11853 : : .trunk_size = 4096,
11854 : : .need_lock = 1,
11855 : 0 : .release_mem_en = !!priv->sh->config.reclaim_mode,
11856 : : .malloc = mlx5_malloc,
11857 : : .free = mlx5_free,
11858 : : .type = "mlx5_hw_action_construct_data",
11859 : : };
11860 : : /*
11861 : : * Adds one queue to be used by PMD.
11862 : : * The last queue will be used by the PMD.
11863 : : */
11864 : : uint16_t nb_q_updated = 0;
11865 : : struct rte_flow_queue_attr **_queue_attr = NULL;
11866 : 0 : struct rte_flow_queue_attr ctrl_queue_attr = {0};
11867 [ # # # # ]: 0 : bool is_proxy = !!(priv->sh->config.dv_esw_en && priv->master);
11868 : : bool unified_fdb = is_unified_fdb(priv);
11869 : : int ret = 0;
11870 : : uint32_t action_flags;
11871 : : bool strict_queue = false;
11872 : :
11873 : 0 : error->type = RTE_FLOW_ERROR_TYPE_NONE;
11874 [ # # ]: 0 : if (mlx5dr_rule_get_handle_size() != MLX5_DR_RULE_SIZE) {
11875 : 0 : rte_errno = EINVAL;
11876 : 0 : goto err;
11877 : : }
11878 [ # # ]: 0 : if (flow_hw_validate_attributes(port_attr, nb_queue, queue_attr, nt_mode, error))
11879 : 0 : return -rte_errno;
11880 : : /*
11881 : : * Calling rte_flow_configure() again is allowed if
11882 : : * provided configuration matches the initially provided one,
11883 : : * or previous configuration was default non template one.
11884 : : */
11885 [ # # ]: 0 : if (priv->dr_ctx) {
11886 : : MLX5_ASSERT(priv->hw_attr != NULL);
11887 [ # # ]: 0 : for (i = 0; i < priv->nb_queue; i++) {
11888 : 0 : hw_q = &priv->hw_q[i];
11889 : : /* Make sure all queues are empty. */
11890 [ # # ]: 0 : if (hw_q->size != hw_q->job_idx) {
11891 : 0 : rte_errno = EBUSY;
11892 : 0 : goto err;
11893 : : }
11894 : : }
11895 : : /* If previous configuration was not default non template mode config. */
11896 [ # # ]: 0 : if (!priv->hw_attr->nt_mode) {
11897 [ # # ]: 0 : if (flow_hw_compare_config(priv->hw_attr, port_attr, nb_queue, queue_attr))
11898 : : return 0;
11899 : : else
11900 : 0 : return rte_flow_error_set(error, ENOTSUP,
11901 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11902 : : "Changing HWS configuration attributes "
11903 : : "is not supported");
11904 : : }
11905 : : /* Reconfiguration, need to release all resources from previous allocation. */
11906 : 0 : __flow_hw_resource_release(dev, true);
11907 : : }
11908 : 0 : priv->hw_attr = flow_hw_alloc_copy_config(port_attr, nb_queue, queue_attr, nt_mode, error);
11909 [ # # ]: 0 : if (!priv->hw_attr) {
11910 : 0 : ret = -rte_errno;
11911 : 0 : goto err;
11912 : : }
11913 : 0 : ctrl_queue_attr.size = queue_attr[0]->size;
11914 : 0 : nb_q_updated = nb_queue + 1;
11915 : 0 : _queue_attr = mlx5_malloc(MLX5_MEM_ZERO,
11916 : : nb_q_updated *
11917 : : sizeof(struct rte_flow_queue_attr *),
11918 : : 64, SOCKET_ID_ANY);
11919 [ # # ]: 0 : if (!_queue_attr) {
11920 : 0 : rte_errno = ENOMEM;
11921 : 0 : goto err;
11922 : : }
11923 : :
11924 : 0 : memcpy(_queue_attr, queue_attr, sizeof(void *) * nb_queue);
11925 : 0 : _queue_attr[nb_queue] = &ctrl_queue_attr;
11926 : 0 : priv->acts_ipool = mlx5_ipool_create(&cfg);
11927 [ # # ]: 0 : if (!priv->acts_ipool)
11928 : 0 : goto err;
11929 : : /* Allocate the queue job descriptor LIFO. */
11930 : 0 : mem_size = sizeof(priv->hw_q[0]) * nb_q_updated;
11931 [ # # ]: 0 : for (i = 0; i < nb_q_updated; i++) {
11932 : 0 : mem_size += (sizeof(struct mlx5_hw_q_job *) +
11933 : 0 : sizeof(struct mlx5_hw_q_job)) * _queue_attr[i]->size;
11934 : : }
11935 : 0 : priv->hw_q = mlx5_malloc(MLX5_MEM_ZERO, mem_size,
11936 : : 64, SOCKET_ID_ANY);
11937 [ # # ]: 0 : if (!priv->hw_q) {
11938 : 0 : rte_errno = ENOMEM;
11939 : 0 : goto err;
11940 : : }
11941 [ # # ]: 0 : for (i = 0; i < nb_q_updated; i++) {
11942 : 0 : priv->hw_q[i].job_idx = _queue_attr[i]->size;
11943 : 0 : priv->hw_q[i].size = _queue_attr[i]->size;
11944 : 0 : priv->hw_q[i].ongoing_flow_ops = 0;
11945 [ # # ]: 0 : if (i == 0)
11946 : 0 : priv->hw_q[i].job = (struct mlx5_hw_q_job **)
11947 : 0 : &priv->hw_q[nb_q_updated];
11948 : : else
11949 : 0 : priv->hw_q[i].job = (struct mlx5_hw_q_job **)&job[_queue_attr[i - 1]->size];
11950 : 0 : job = (struct mlx5_hw_q_job *)
11951 : 0 : &priv->hw_q[i].job[_queue_attr[i]->size];
11952 [ # # ]: 0 : for (j = 0; j < _queue_attr[i]->size; j++)
11953 : 0 : priv->hw_q[i].job[j] = &job[j];
11954 : : /* Notice ring name length is limited. */
11955 : 0 : priv->hw_q[i].indir_cq = mlx5_hwq_ring_create
11956 : 0 : (dev->data->port_id, i, _queue_attr[i]->size, "indir_act_cq");
11957 [ # # ]: 0 : if (!priv->hw_q[i].indir_cq)
11958 : 0 : goto err;
11959 : 0 : priv->hw_q[i].indir_iq = mlx5_hwq_ring_create
11960 : 0 : (dev->data->port_id, i, _queue_attr[i]->size, "indir_act_iq");
11961 [ # # ]: 0 : if (!priv->hw_q[i].indir_iq)
11962 : 0 : goto err;
11963 : 0 : priv->hw_q[i].flow_transfer_pending = mlx5_hwq_ring_create
11964 : 0 : (dev->data->port_id, i, _queue_attr[i]->size, "tx_pending");
11965 [ # # ]: 0 : if (!priv->hw_q[i].flow_transfer_pending)
11966 : 0 : goto err;
11967 : 0 : priv->hw_q[i].flow_transfer_completed = mlx5_hwq_ring_create
11968 : 0 : (dev->data->port_id, i, _queue_attr[i]->size, "tx_done");
11969 [ # # ]: 0 : if (!priv->hw_q[i].flow_transfer_completed)
11970 : 0 : goto err;
11971 : : }
11972 : 0 : dr_ctx_attr.pd = priv->sh->cdev->pd;
11973 : 0 : dr_ctx_attr.queues = nb_q_updated;
11974 : : /* Assign initial value of STC numbers for representors. */
11975 [ # # ]: 0 : if (priv->representor)
11976 : 0 : dr_ctx_attr.initial_log_stc_memory = MLX5_REPR_STC_MEMORY_LOG;
11977 : : /* Queue size should all be the same. Take the first one. */
11978 : 0 : dr_ctx_attr.queue_size = _queue_attr[0]->size;
11979 [ # # ]: 0 : if (port_attr->flags & RTE_FLOW_PORT_FLAG_SHARE_INDIRECT) {
11980 : : struct rte_eth_dev *host_dev = NULL;
11981 : : uint16_t port_id;
11982 : :
11983 : : MLX5_ASSERT(rte_eth_dev_is_valid_port(port_attr->host_port_id));
11984 [ # # ]: 0 : if (is_proxy) {
11985 : 0 : DRV_LOG(ERR, "cross vHCA shared mode not supported "
11986 : : "for E-Switch confgiurations");
11987 : 0 : rte_errno = ENOTSUP;
11988 : 0 : goto err;
11989 : : }
11990 [ # # ]: 0 : MLX5_ETH_FOREACH_DEV(port_id, dev->device) {
11991 [ # # ]: 0 : if (port_id == port_attr->host_port_id) {
11992 : 0 : host_dev = &rte_eth_devices[port_id];
11993 : 0 : break;
11994 : : }
11995 : : }
11996 [ # # ]: 0 : if (!host_dev || host_dev == dev ||
11997 [ # # # # ]: 0 : !host_dev->data || !host_dev->data->dev_private) {
11998 : 0 : DRV_LOG(ERR, "Invalid cross vHCA host port %u",
11999 : : port_attr->host_port_id);
12000 : 0 : rte_errno = EINVAL;
12001 : 0 : goto err;
12002 : : }
12003 : : host_priv = host_dev->data->dev_private;
12004 [ # # ]: 0 : if (host_priv->sh->cdev->ctx == priv->sh->cdev->ctx) {
12005 : 0 : DRV_LOG(ERR, "Sibling ports %u and %u do not "
12006 : : "require cross vHCA sharing mode",
12007 : : dev->data->port_id, port_attr->host_port_id);
12008 : 0 : rte_errno = EINVAL;
12009 : 0 : goto err;
12010 : : }
12011 [ # # ]: 0 : if (host_priv->shared_host) {
12012 : 0 : DRV_LOG(ERR, "Host port %u is not the sharing base",
12013 : : port_attr->host_port_id);
12014 : 0 : rte_errno = EINVAL;
12015 : 0 : goto err;
12016 : : }
12017 [ # # ]: 0 : if (port_attr->nb_counters ||
12018 [ # # ]: 0 : port_attr->nb_aging_objects ||
12019 [ # # ]: 0 : port_attr->nb_meters ||
12020 [ # # ]: 0 : port_attr->nb_conn_tracks) {
12021 : 0 : DRV_LOG(ERR,
12022 : : "Object numbers on guest port must be zeros");
12023 : 0 : rte_errno = EINVAL;
12024 : 0 : goto err;
12025 : : }
12026 : 0 : dr_ctx_attr.shared_ibv_ctx = host_priv->sh->cdev->ctx;
12027 : 0 : priv->shared_host = host_dev;
12028 : 0 : rte_atomic_fetch_add_explicit(&host_priv->shared_refcnt, 1,
12029 : : rte_memory_order_relaxed);
12030 : : }
12031 : : /* Set backward compatibale mode to support non template RTE FLOW API.*/
12032 : 0 : dr_ctx_attr.bwc = true;
12033 : 0 : priv->dr_ctx = mlx5dr_context_open(priv->sh->cdev->ctx, &dr_ctx_attr);
12034 : : /* rte_errno has been updated by HWS layer. */
12035 [ # # ]: 0 : if (!priv->dr_ctx)
12036 : 0 : goto err;
12037 : 0 : priv->nb_queue = nb_q_updated;
12038 : 0 : ret = flow_hw_action_template_drop_init(dev, error);
12039 [ # # ]: 0 : if (ret)
12040 : 0 : goto err;
12041 : 0 : ret = flow_hw_create_ctrl_rx_tables(dev);
12042 [ # # ]: 0 : if (ret) {
12043 : 0 : rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12044 : : "Failed to set up Rx control flow templates");
12045 : 0 : goto err;
12046 : : }
12047 : : /* Initialize quotas */
12048 [ # # # # : 0 : if (port_attr->nb_quotas || (host_priv && host_priv->quota_ctx.devx_obj)) {
# # ]
12049 : 0 : ret = mlx5_flow_quota_init(dev, port_attr->nb_quotas);
12050 [ # # ]: 0 : if (ret) {
12051 : 0 : rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12052 : : "Failed to initialize quota.");
12053 : 0 : goto err;
12054 : : }
12055 : : }
12056 : : /* Initialize meter library*/
12057 [ # # # # : 0 : if (port_attr->nb_meters || (host_priv && host_priv->hws_mpool))
# # ]
12058 [ # # ]: 0 : if (mlx5_flow_meter_init(dev, port_attr->nb_meters, 0, 0, nb_q_updated))
12059 : 0 : goto err;
12060 : : /* Add global actions. */
12061 [ # # ]: 0 : for (i = 0; i < MLX5_HW_ACTION_FLAG_MAX; i++) {
12062 : : uint32_t act_flags = 0;
12063 : 0 : uint32_t tag_flags = mlx5_hw_act_flag[i][0];
12064 : :
12065 : 0 : act_flags = mlx5_hw_act_flag[i][MLX5DR_TABLE_TYPE_NIC_RX] |
12066 : 0 : mlx5_hw_act_flag[i][MLX5DR_TABLE_TYPE_NIC_TX];
12067 [ # # ]: 0 : if (is_proxy) {
12068 : : /* Tag action is valid only in FDB_Rx domain. */
12069 [ # # ]: 0 : if (unified_fdb) {
12070 : 0 : act_flags |=
12071 : 0 : (mlx5_hw_act_flag[i][MLX5DR_TABLE_TYPE_FDB_RX] |
12072 : 0 : mlx5_hw_act_flag[i][MLX5DR_TABLE_TYPE_FDB_TX] |
12073 : 0 : mlx5_hw_act_flag[i][MLX5DR_TABLE_TYPE_FDB_UNIFIED]);
12074 [ # # ]: 0 : if (i == MLX5_HW_ACTION_FLAG_NONE_ROOT)
12075 : 0 : tag_flags |= mlx5_hw_act_flag[i][MLX5DR_TABLE_TYPE_FDB_RX];
12076 : : } else {
12077 : 0 : act_flags |= mlx5_hw_act_flag[i][MLX5DR_TABLE_TYPE_FDB];
12078 [ # # ]: 0 : if (i == MLX5_HW_ACTION_FLAG_NONE_ROOT)
12079 : 0 : tag_flags |= mlx5_hw_act_flag[i][MLX5DR_TABLE_TYPE_FDB];
12080 : : }
12081 : : }
12082 : 0 : priv->hw_drop[i] = mlx5dr_action_create_dest_drop(priv->dr_ctx, act_flags);
12083 [ # # ]: 0 : if (!priv->hw_drop[i])
12084 : 0 : goto err;
12085 : 0 : priv->hw_tag[i] = mlx5dr_action_create_tag
12086 : : (priv->dr_ctx, tag_flags);
12087 [ # # ]: 0 : if (!priv->hw_tag[i])
12088 : 0 : goto err;
12089 : : }
12090 [ # # ]: 0 : if (priv->sh->config.dv_esw_en && priv->sh->config.repr_matching) {
12091 : 0 : ret = flow_hw_setup_tx_repr_tagging(dev, error);
12092 [ # # ]: 0 : if (ret)
12093 : 0 : goto err;
12094 : : }
12095 : : /*
12096 : : * DEFAULT_MISS action have different behaviors in different domains.
12097 : : * In FDB, it will steering the packets to the E-switch manager.
12098 : : * In NIC Rx root, it will steering the packet to the kernel driver stack.
12099 : : * An action with all bits set in the flag can be created and the HWS
12100 : : * layer will translate it properly when being used in different rules.
12101 : : */
12102 : : action_flags = MLX5DR_ACTION_FLAG_ROOT_RX | MLX5DR_ACTION_FLAG_HWS_RX |
12103 : : MLX5DR_ACTION_FLAG_ROOT_TX | MLX5DR_ACTION_FLAG_HWS_TX;
12104 [ # # ]: 0 : if (is_proxy) {
12105 [ # # ]: 0 : if (unified_fdb)
12106 : : action_flags |=
12107 : : (MLX5DR_ACTION_FLAG_ROOT_FDB |
12108 : : MLX5DR_ACTION_FLAG_HWS_FDB_RX |
12109 : : MLX5DR_ACTION_FLAG_HWS_FDB_TX |
12110 : : MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED);
12111 : : else
12112 : : action_flags |=
12113 : : (MLX5DR_ACTION_FLAG_ROOT_FDB |
12114 : : MLX5DR_ACTION_FLAG_HWS_FDB);
12115 : : }
12116 : 0 : priv->hw_def_miss = mlx5dr_action_create_default_miss(priv->dr_ctx, action_flags);
12117 [ # # ]: 0 : if (!priv->hw_def_miss)
12118 : 0 : goto err;
12119 [ # # ]: 0 : if (is_proxy) {
12120 : 0 : ret = flow_hw_create_vport_actions(priv);
12121 [ # # ]: 0 : if (ret) {
12122 : 0 : rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12123 : : NULL, "Failed to create vport actions.");
12124 : 0 : goto err;
12125 : : }
12126 : 0 : ret = flow_hw_create_ctrl_tables(dev, error);
12127 [ # # ]: 0 : if (ret) {
12128 : 0 : rte_errno = -ret;
12129 : 0 : goto err;
12130 : : }
12131 : : }
12132 : : if (!priv->shared_host)
12133 : : flow_hw_create_send_to_kernel_actions(priv, is_proxy);
12134 [ # # # # : 0 : if (port_attr->nb_conn_tracks || (host_priv && host_priv->hws_ctpool)) {
# # ]
12135 [ # # ]: 0 : if (mlx5_flow_ct_init(dev, port_attr->nb_conn_tracks, nb_q_updated))
12136 : 0 : goto err;
12137 : : }
12138 [ # # # # : 0 : if (port_attr->nb_counters || (host_priv && host_priv->hws_cpool)) {
# # ]
12139 [ # # ]: 0 : struct mlx5_hws_cnt_pool *hws_cpool = host_priv ? host_priv->hws_cpool : NULL;
12140 : :
12141 : 0 : ret = mlx5_hws_cnt_pool_create(dev, port_attr->nb_counters,
12142 : : nb_queue, hws_cpool, error);
12143 [ # # ]: 0 : if (ret)
12144 : 0 : goto err;
12145 : : }
12146 [ # # ]: 0 : if (port_attr->nb_aging_objects) {
12147 [ # # ]: 0 : if (port_attr->nb_counters == 0) {
12148 : : /*
12149 : : * Aging management uses counter. Number counters
12150 : : * requesting should take into account a counter for
12151 : : * each flow rules containing AGE without counter.
12152 : : */
12153 : 0 : DRV_LOG(ERR, "Port %u AGE objects are requested (%u) "
12154 : : "without counters requesting.",
12155 : : dev->data->port_id,
12156 : : port_attr->nb_aging_objects);
12157 : 0 : rte_errno = EINVAL;
12158 : 0 : goto err;
12159 : : }
12160 [ # # ]: 0 : if (port_attr->flags & RTE_FLOW_PORT_FLAG_SHARE_INDIRECT) {
12161 : 0 : DRV_LOG(ERR, "Aging is not supported "
12162 : : "in cross vHCA sharing mode");
12163 : : ret = -ENOTSUP;
12164 : 0 : goto err;
12165 : : }
12166 : 0 : strict_queue = !!(port_attr->flags & RTE_FLOW_PORT_FLAG_STRICT_QUEUE);
12167 : 0 : ret = mlx5_hws_age_pool_init(dev, port_attr->nb_aging_objects,
12168 : : nb_queue, strict_queue);
12169 [ # # ]: 0 : if (ret < 0)
12170 : 0 : goto err;
12171 : : }
12172 : 0 : ret = flow_hw_create_vlan(dev);
12173 [ # # ]: 0 : if (ret) {
12174 : 0 : rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12175 : : NULL, "Failed to VLAN actions.");
12176 : 0 : goto err;
12177 : : }
12178 [ # # ]: 0 : if (flow_hw_should_create_nat64_actions(priv)) {
12179 [ # # ]: 0 : if (flow_hw_create_nat64_actions(priv, error))
12180 : 0 : goto err;
12181 : : } else {
12182 : 0 : DRV_LOG(WARNING, "Cannot create NAT64 action on port %u, "
12183 : : "please check the FW version. NAT64 will not be supported.",
12184 : : dev->data->port_id);
12185 : : }
12186 : : if (_queue_attr)
12187 : 0 : mlx5_free(_queue_attr);
12188 [ # # ]: 0 : if (port_attr->flags & RTE_FLOW_PORT_FLAG_STRICT_QUEUE)
12189 : 0 : priv->hws_strict_queue = 1;
12190 : 0 : dev->flow_fp_ops = &mlx5_flow_hw_fp_ops;
12191 : 0 : return 0;
12192 : 0 : err:
12193 : 0 : __flow_hw_resource_release(dev, true);
12194 [ # # ]: 0 : if (_queue_attr)
12195 : 0 : mlx5_free(_queue_attr);
12196 : : /* Do not overwrite the internal errno information. */
12197 [ # # # # ]: 0 : if (ret && error->type != RTE_FLOW_ERROR_TYPE_NONE)
12198 : : return ret;
12199 : 0 : return rte_flow_error_set(error, rte_errno,
12200 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12201 : : "fail to configure port");
12202 : : }
12203 : :
12204 : : /**
12205 : : * Configure port HWS resources.
12206 : : *
12207 : : * @param[in] dev
12208 : : * Pointer to the rte_eth_dev structure.
12209 : : * @param[in] port_attr
12210 : : * Port configuration attributes.
12211 : : * @param[in] nb_queue
12212 : : * Number of queue.
12213 : : * @param[in] queue_attr
12214 : : * Array that holds attributes for each flow queue.
12215 : : * @param[out] error
12216 : : * Pointer to error structure.
12217 : : *
12218 : : * @return
12219 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
12220 : : */
12221 : : static int
12222 : 0 : flow_hw_configure(struct rte_eth_dev *dev,
12223 : : const struct rte_flow_port_attr *port_attr,
12224 : : uint16_t nb_queue,
12225 : : const struct rte_flow_queue_attr *queue_attr[],
12226 : : struct rte_flow_error *error)
12227 : : {
12228 : 0 : struct rte_flow_error shadow_error = {0, };
12229 : :
12230 [ # # ]: 0 : if (!error)
12231 : : error = &shadow_error;
12232 : 0 : return __flow_hw_configure(dev, port_attr, nb_queue, queue_attr, false, error);
12233 : : }
12234 : :
12235 : : /**
12236 : : * Release HWS resources.
12237 : : *
12238 : : * @param[in] dev
12239 : : * Pointer to the rte_eth_dev structure.
12240 : : */
12241 : : void
12242 : 0 : flow_hw_resource_release(struct rte_eth_dev *dev)
12243 : : {
12244 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12245 : :
12246 [ # # ]: 0 : if (!priv->dr_ctx)
12247 : : return;
12248 : 0 : __flow_hw_resource_release(dev, false);
12249 : : }
12250 : :
12251 : : /* Sets vport tag and mask, for given port, used in HWS rules. */
12252 : : void
12253 : 0 : flow_hw_set_port_info(struct rte_eth_dev *dev)
12254 : : {
12255 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12256 : 0 : uint16_t port_id = dev->data->port_id;
12257 : : struct flow_hw_port_info *info;
12258 : :
12259 : : MLX5_ASSERT(port_id < RTE_MAX_ETHPORTS);
12260 : 0 : info = &mlx5_flow_hw_port_infos[port_id];
12261 : 0 : info->regc_mask = priv->vport_meta_mask;
12262 [ # # ]: 0 : info->regc_value = priv->vport_meta_tag;
12263 [ # # ]: 0 : info->is_wire = mlx5_is_port_on_mpesw_device(priv) ? priv->mpesw_uplink : priv->master;
12264 : 0 : }
12265 : :
12266 : : /* Clears vport tag and mask used for HWS rules. */
12267 : : void
12268 : 0 : flow_hw_clear_port_info(struct rte_eth_dev *dev)
12269 : : {
12270 : 0 : uint16_t port_id = dev->data->port_id;
12271 : : struct flow_hw_port_info *info;
12272 : :
12273 : : MLX5_ASSERT(port_id < RTE_MAX_ETHPORTS);
12274 : 0 : info = &mlx5_flow_hw_port_infos[port_id];
12275 : 0 : info->regc_mask = 0;
12276 : 0 : info->regc_value = 0;
12277 : 0 : info->is_wire = 0;
12278 : 0 : }
12279 : :
12280 : : static int
12281 : 0 : flow_hw_conntrack_destroy(struct rte_eth_dev *dev,
12282 : : uint32_t idx,
12283 : : struct rte_flow_error *error)
12284 : : {
12285 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12286 : 0 : struct mlx5_aso_ct_pool *pool = priv->hws_ctpool;
12287 : : struct mlx5_aso_ct_action *ct;
12288 : :
12289 [ # # ]: 0 : if (priv->shared_host)
12290 : 0 : return rte_flow_error_set(error, ENOTSUP,
12291 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12292 : : NULL,
12293 : : "CT destruction is not allowed to guest port");
12294 : 0 : ct = mlx5_ipool_get(pool->cts, idx);
12295 [ # # ]: 0 : if (!ct) {
12296 : 0 : return rte_flow_error_set(error, EINVAL,
12297 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12298 : : NULL,
12299 : : "Invalid CT destruction index");
12300 : : }
12301 : 0 : rte_atomic_store_explicit(&ct->state, ASO_CONNTRACK_FREE,
12302 : : rte_memory_order_relaxed);
12303 : 0 : mlx5_ipool_free(pool->cts, idx);
12304 : 0 : return 0;
12305 : : }
12306 : :
12307 : : static int
12308 : 0 : flow_hw_conntrack_query(struct rte_eth_dev *dev, uint32_t queue, uint32_t idx,
12309 : : struct rte_flow_action_conntrack *profile,
12310 : : void *user_data, bool push,
12311 : : struct rte_flow_error *error)
12312 : : {
12313 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12314 : 0 : struct mlx5_aso_ct_pool *pool = priv->hws_ctpool;
12315 : : struct mlx5_aso_ct_action *ct;
12316 : :
12317 [ # # ]: 0 : if (priv->shared_host)
12318 : 0 : return rte_flow_error_set(error, ENOTSUP,
12319 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12320 : : NULL,
12321 : : "CT query is not allowed to guest port");
12322 : 0 : ct = mlx5_ipool_get(pool->cts, idx);
12323 [ # # ]: 0 : if (!ct) {
12324 : 0 : return rte_flow_error_set(error, EINVAL,
12325 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12326 : : NULL,
12327 : : "Invalid CT query index");
12328 : : }
12329 : 0 : profile->peer_port = ct->peer;
12330 : 0 : profile->is_original_dir = ct->is_original;
12331 [ # # ]: 0 : if (mlx5_aso_ct_query_by_wqe(priv->sh, queue, ct, profile, user_data, push))
12332 : 0 : return rte_flow_error_set(error, EIO,
12333 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12334 : : NULL,
12335 : : "Failed to query CT context");
12336 : : return 0;
12337 : : }
12338 : :
12339 : :
12340 : : static int
12341 : 0 : flow_hw_conntrack_update(struct rte_eth_dev *dev, uint32_t queue,
12342 : : const struct rte_flow_modify_conntrack *action_conf,
12343 : : uint32_t idx, void *user_data, bool push,
12344 : : struct rte_flow_error *error)
12345 : : {
12346 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12347 : 0 : struct mlx5_aso_ct_pool *pool = priv->hws_ctpool;
12348 : : struct mlx5_aso_ct_action *ct;
12349 : : const struct rte_flow_action_conntrack *new_prf;
12350 : : int ret = 0;
12351 : :
12352 [ # # ]: 0 : if (priv->shared_host)
12353 : 0 : return rte_flow_error_set(error, ENOTSUP,
12354 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12355 : : NULL,
12356 : : "CT update is not allowed to guest port");
12357 : 0 : ct = mlx5_ipool_get(pool->cts, idx);
12358 [ # # ]: 0 : if (!ct) {
12359 : 0 : return rte_flow_error_set(error, EINVAL,
12360 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12361 : : NULL,
12362 : : "Invalid CT update index");
12363 : : }
12364 : 0 : new_prf = &action_conf->new_ct;
12365 [ # # ]: 0 : if (action_conf->direction)
12366 : 0 : ct->is_original = !!new_prf->is_original_dir;
12367 [ # # ]: 0 : if (action_conf->state) {
12368 : : /* Only validate the profile when it needs to be updated. */
12369 : 0 : ret = mlx5_validate_action_ct(dev, new_prf, error);
12370 [ # # ]: 0 : if (ret)
12371 : : return ret;
12372 : 0 : ret = mlx5_aso_ct_update_by_wqe(priv->sh, queue, ct, new_prf,
12373 : : user_data, push);
12374 [ # # ]: 0 : if (ret)
12375 : 0 : return rte_flow_error_set(error, EIO,
12376 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12377 : : NULL,
12378 : : "Failed to send CT context update WQE");
12379 [ # # ]: 0 : if (queue != MLX5_HW_INV_QUEUE)
12380 : : return 0;
12381 : : /* Block until ready or a failure in synchronous mode. */
12382 : 0 : ret = mlx5_aso_ct_available(priv->sh, queue, ct);
12383 [ # # ]: 0 : if (ret)
12384 : 0 : rte_flow_error_set(error, rte_errno,
12385 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12386 : : NULL,
12387 : : "Timeout to get the CT update");
12388 : : }
12389 : : return ret;
12390 : : }
12391 : :
12392 : : static struct rte_flow_action_handle *
12393 : 0 : flow_hw_conntrack_create(struct rte_eth_dev *dev, uint32_t queue,
12394 : : const struct rte_flow_action_conntrack *pro,
12395 : : void *user_data, bool push,
12396 : : struct rte_flow_error *error)
12397 : : {
12398 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12399 : 0 : struct mlx5_aso_ct_pool *pool = priv->hws_ctpool;
12400 : : struct mlx5_aso_ct_action *ct;
12401 : 0 : uint32_t ct_idx = 0;
12402 : : int ret;
12403 : : bool async = !!(queue != MLX5_HW_INV_QUEUE);
12404 : :
12405 [ # # ]: 0 : if (priv->shared_host) {
12406 : 0 : rte_flow_error_set(error, ENOTSUP,
12407 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12408 : : NULL,
12409 : : "CT create is not allowed to guest port");
12410 : 0 : return NULL;
12411 : : }
12412 [ # # ]: 0 : if (!pool) {
12413 : 0 : rte_flow_error_set(error, EINVAL,
12414 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12415 : : "CT is not enabled");
12416 : 0 : return 0;
12417 : : }
12418 : 0 : ct = mlx5_ipool_zmalloc(pool->cts, &ct_idx);
12419 [ # # ]: 0 : if (!ct) {
12420 : 0 : rte_flow_error_set(error, rte_errno,
12421 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12422 : : "Failed to allocate CT object");
12423 : 0 : return 0;
12424 : : }
12425 : 0 : ct->offset = ct_idx - 1;
12426 : 0 : ct->is_original = !!pro->is_original_dir;
12427 : 0 : ct->peer = pro->peer_port;
12428 : 0 : ct->pool = pool;
12429 [ # # ]: 0 : if (mlx5_aso_ct_update_by_wqe(priv->sh, queue, ct, pro, user_data, push)) {
12430 : 0 : mlx5_ipool_free(pool->cts, ct_idx);
12431 : 0 : rte_flow_error_set(error, EBUSY,
12432 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12433 : : "Failed to update CT");
12434 : 0 : return 0;
12435 : : }
12436 [ # # ]: 0 : if (!async) {
12437 : 0 : ret = mlx5_aso_ct_available(priv->sh, queue, ct);
12438 [ # # ]: 0 : if (ret) {
12439 : 0 : mlx5_ipool_free(pool->cts, ct_idx);
12440 : 0 : rte_flow_error_set(error, rte_errno,
12441 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12442 : : NULL,
12443 : : "Timeout to get the CT update");
12444 : 0 : return 0;
12445 : : }
12446 : : }
12447 : 0 : return MLX5_INDIRECT_ACT_HWS_CT_GEN_IDX(ct_idx);
12448 : : }
12449 : :
12450 : : /**
12451 : : * Validate shared action.
12452 : : *
12453 : : * @param[in] dev
12454 : : * Pointer to the rte_eth_dev structure.
12455 : : * @param[in] queue
12456 : : * Which queue to be used.
12457 : : * @param[in] attr
12458 : : * Operation attribute.
12459 : : * @param[in] conf
12460 : : * Indirect action configuration.
12461 : : * @param[in] action
12462 : : * rte_flow action detail.
12463 : : * @param[in] user_data
12464 : : * Pointer to the user_data.
12465 : : * @param[out] error
12466 : : * Pointer to error structure.
12467 : : *
12468 : : * @return
12469 : : * 0 on success, otherwise negative errno value.
12470 : : */
12471 : : static int
12472 : 0 : flow_hw_action_handle_validate(struct rte_eth_dev *dev, uint32_t queue,
12473 : : const struct rte_flow_op_attr *attr,
12474 : : const struct rte_flow_indir_action_conf *conf,
12475 : : const struct rte_flow_action *action,
12476 : : void *user_data,
12477 : : struct rte_flow_error *error)
12478 : : {
12479 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12480 : :
12481 : : RTE_SET_USED(attr);
12482 : : RTE_SET_USED(queue);
12483 : : RTE_SET_USED(user_data);
12484 [ # # # # : 0 : switch (action->type) {
# # # ]
12485 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
12486 [ # # ]: 0 : if (!priv->hws_age_req) {
12487 [ # # ]: 0 : if (flow_hw_allocate_actions(dev, MLX5_FLOW_ACTION_AGE,
12488 : : error))
12489 : 0 : return rte_flow_error_set
12490 : : (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
12491 : : NULL, "aging pool not initialized");
12492 : : }
12493 : : break;
12494 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
12495 [ # # ]: 0 : if (!priv->hws_cpool) {
12496 [ # # ]: 0 : if (flow_hw_allocate_actions(dev, MLX5_FLOW_ACTION_COUNT,
12497 : : error))
12498 : 0 : return rte_flow_error_set
12499 : : (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
12500 : : NULL, "counters pool not initialized");
12501 : : }
12502 : : break;
12503 : 0 : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
12504 [ # # ]: 0 : if (priv->hws_ctpool == NULL) {
12505 [ # # ]: 0 : if (flow_hw_allocate_actions(dev, MLX5_FLOW_ACTION_CT,
12506 : : error))
12507 : 0 : return rte_flow_error_set
12508 : : (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
12509 : : NULL, "CT pool not initialized");
12510 : : }
12511 : 0 : return mlx5_validate_action_ct(dev, action->conf, error);
12512 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
12513 : 0 : return flow_hw_validate_action_meter_mark(dev, action, true, error);
12514 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
12515 : 0 : return flow_dv_action_validate(dev, conf, action, error);
12516 : : case RTE_FLOW_ACTION_TYPE_QUOTA:
12517 : : return 0;
12518 : 0 : default:
12519 : 0 : return rte_flow_error_set(error, ENOTSUP,
12520 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12521 : : "action type not supported");
12522 : : }
12523 : : return 0;
12524 : : }
12525 : :
12526 : : static __rte_always_inline bool
12527 : : flow_hw_action_push(const struct rte_flow_op_attr *attr)
12528 : : {
12529 [ # # # # : 0 : return attr ? !attr->postpone : true;
# # # # #
# # # #
# ]
12530 : : }
12531 : :
12532 : : static __rte_always_inline struct mlx5_hw_q_job *
12533 : : flow_hw_action_job_init(struct mlx5_priv *priv, uint32_t queue,
12534 : : const struct rte_flow_action_handle *handle,
12535 : : void *user_data, void *query_data,
12536 : : enum mlx5_hw_job_type type,
12537 : : enum mlx5_hw_indirect_type indirect_type,
12538 : : struct rte_flow_error *error)
12539 : : {
12540 : : struct mlx5_hw_q_job *job;
12541 : :
12542 [ # # # # : 0 : if (queue == MLX5_HW_INV_QUEUE)
# # # # #
# # # #
# ]
12543 [ # # # # : 0 : queue = CTRL_QUEUE_ID(priv);
# # # # #
# # # ]
12544 : : job = flow_hw_job_get(priv, queue);
12545 [ # # # # : 0 : if (!job) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # ]
12546 : 0 : rte_flow_error_set(error, ENOMEM,
12547 : : RTE_FLOW_ERROR_TYPE_ACTION_NUM, NULL,
12548 : : "Action destroy failed due to queue full.");
12549 : 0 : return NULL;
12550 : : }
12551 : 0 : job->type = type;
12552 : 0 : job->action = handle;
12553 : 0 : job->user_data = user_data;
12554 : 0 : job->query.user = query_data;
12555 [ # # # # : 0 : job->indirect_type = indirect_type;
# # # # #
# # # ]
12556 : 0 : return job;
12557 : : }
12558 : :
12559 : : struct mlx5_hw_q_job *
12560 [ # # ]: 0 : mlx5_flow_action_job_init(struct mlx5_priv *priv, uint32_t queue,
12561 : : const struct rte_flow_action_handle *handle,
12562 : : void *user_data, void *query_data,
12563 : : enum mlx5_hw_job_type type,
12564 : : struct rte_flow_error *error)
12565 : : {
12566 : 0 : return flow_hw_action_job_init(priv, queue, handle, user_data, query_data,
12567 : : type, MLX5_HW_INDIRECT_TYPE_LEGACY, error);
12568 : : }
12569 : :
12570 : : static __rte_always_inline void
12571 : : flow_hw_action_finalize(struct rte_eth_dev *dev, uint32_t queue,
12572 : : struct mlx5_hw_q_job *job,
12573 : : bool push, bool aso, bool status)
12574 : : {
12575 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12576 : :
12577 [ # # ]: 0 : if (queue == MLX5_HW_INV_QUEUE)
12578 : 0 : queue = CTRL_QUEUE_ID(priv);
12579 [ # # # # : 0 : if (likely(status)) {
# # # # #
# # # ]
12580 : : /* 1. add new job to a queue */
12581 [ # # # # : 0 : if (!aso)
# # # # #
# ]
12582 [ # # # # : 0 : rte_ring_enqueue(push ?
# # # # #
# # # #
# ]
12583 : 0 : priv->hw_q[queue].indir_cq :
12584 : 0 : priv->hw_q[queue].indir_iq,
12585 : : job);
12586 : : /* 2. send pending jobs */
12587 [ # # # # : 0 : if (push)
# # # # #
# # # #
# ]
12588 : 0 : __flow_hw_push_action(dev, queue);
12589 : : } else {
12590 : : flow_hw_job_put(priv, job, queue);
12591 : : }
12592 : : }
12593 : :
12594 : : /**
12595 : : * Create shared action.
12596 : : *
12597 : : * @param[in] dev
12598 : : * Pointer to the rte_eth_dev structure.
12599 : : * @param[in] queue
12600 : : * Which queue to be used.
12601 : : * @param[in] attr
12602 : : * Operation attribute.
12603 : : * @param[in] conf
12604 : : * Indirect action configuration.
12605 : : * @param[in] action
12606 : : * rte_flow action detail.
12607 : : * @param[in] user_data
12608 : : * Pointer to the user_data.
12609 : : * @param[out] error
12610 : : * Pointer to error structure.
12611 : : *
12612 : : * @return
12613 : : * Action handle on success, NULL otherwise and rte_errno is set.
12614 : : */
12615 : : static struct rte_flow_action_handle *
12616 : 0 : flow_hw_action_handle_create(struct rte_eth_dev *dev, uint32_t queue,
12617 : : const struct rte_flow_op_attr *attr,
12618 : : const struct rte_flow_indir_action_conf *conf,
12619 : : const struct rte_flow_action *action,
12620 : : void *user_data,
12621 : : struct rte_flow_error *error)
12622 : : {
12623 : : struct rte_flow_action_handle *handle = NULL;
12624 : : struct mlx5_hw_q_job *job = NULL;
12625 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
12626 : : const struct rte_flow_action_age *age;
12627 : : struct mlx5_aso_mtr *aso_mtr;
12628 : : cnt_id_t cnt_id;
12629 : : uint32_t age_idx;
12630 : : bool push = flow_hw_action_push(attr);
12631 : : bool aso = false;
12632 : 0 : bool force_job = action->type == RTE_FLOW_ACTION_TYPE_METER_MARK;
12633 : :
12634 [ # # ]: 0 : if (!mlx5_hw_ctx_validate(dev, error))
12635 : : return NULL;
12636 [ # # ]: 0 : if (attr || force_job) {
12637 : : job = flow_hw_action_job_init(priv, queue, NULL, user_data,
12638 : : NULL, MLX5_HW_Q_JOB_TYPE_CREATE,
12639 : : MLX5_HW_INDIRECT_TYPE_LEGACY, error);
12640 : : if (!job)
12641 : 0 : return NULL;
12642 : : }
12643 [ # # # # : 0 : switch (action->type) {
# # # ]
12644 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
12645 [ # # ]: 0 : if (priv->hws_strict_queue) {
12646 : 0 : struct mlx5_age_info *info = GET_PORT_AGE_INFO(priv);
12647 : :
12648 [ # # ]: 0 : if (queue >= info->hw_q_age->nb_rings) {
12649 : 0 : rte_flow_error_set(error, EINVAL,
12650 : : RTE_FLOW_ERROR_TYPE_ACTION,
12651 : : NULL,
12652 : : "Invalid queue ID for indirect AGE.");
12653 : 0 : rte_errno = EINVAL;
12654 : 0 : return NULL;
12655 : : }
12656 : : }
12657 : 0 : age = action->conf;
12658 : 0 : age_idx = mlx5_hws_age_action_create(priv, queue, true, age,
12659 : : 0, error);
12660 [ # # ]: 0 : if (age_idx == 0) {
12661 : 0 : rte_flow_error_set(error, ENODEV,
12662 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12663 : : "AGE are not configured!");
12664 : : } else {
12665 : 0 : age_idx = (MLX5_INDIRECT_ACTION_TYPE_AGE <<
12666 : : MLX5_INDIRECT_ACTION_TYPE_OFFSET) | age_idx;
12667 : 0 : handle =
12668 : 0 : (struct rte_flow_action_handle *)(uintptr_t)age_idx;
12669 : : }
12670 : : break;
12671 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
12672 [ # # ]: 0 : if (mlx5_hws_cnt_shared_get(priv->hws_cpool, &cnt_id, 0))
12673 : 0 : rte_flow_error_set(error, ENODEV,
12674 : : RTE_FLOW_ERROR_TYPE_ACTION,
12675 : : NULL,
12676 : : "counter are not configured!");
12677 : : else
12678 : 0 : handle = (struct rte_flow_action_handle *)
12679 : 0 : (uintptr_t)cnt_id;
12680 : : break;
12681 : 0 : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
12682 : : aso = true;
12683 : 0 : handle = flow_hw_conntrack_create(dev, queue, action->conf, job,
12684 : : push, error);
12685 : 0 : break;
12686 [ # # ]: 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
12687 : : aso = true;
12688 : : aso_mtr = flow_hw_meter_mark_alloc(dev, queue, action, job, push, error);
12689 : : if (!aso_mtr)
12690 : : break;
12691 : 0 : handle = (void *)(uintptr_t)job->action;
12692 : 0 : break;
12693 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
12694 : 0 : handle = flow_dv_action_create(dev, conf, action, error);
12695 : 0 : break;
12696 : 0 : case RTE_FLOW_ACTION_TYPE_QUOTA:
12697 : : aso = true;
12698 : 0 : handle = mlx5_quota_alloc(dev, queue, action->conf,
12699 : : job, push, error);
12700 : 0 : break;
12701 : 0 : default:
12702 : 0 : rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
12703 : : NULL, "action type not supported");
12704 : 0 : break;
12705 : : }
12706 [ # # ]: 0 : if (job && !force_job) {
12707 : 0 : job->action = handle;
12708 [ # # ]: 0 : flow_hw_action_finalize(dev, queue, job, push, aso,
12709 : : handle != NULL);
12710 : : }
12711 : : return handle;
12712 : : }
12713 : :
12714 : : static int
12715 : 0 : mlx5_flow_update_meter_mark(struct rte_eth_dev *dev, uint32_t queue,
12716 : : const struct rte_flow_update_meter_mark *upd_meter_mark,
12717 : : uint32_t idx, bool push,
12718 : : struct mlx5_hw_q_job *job, struct rte_flow_error *error)
12719 : : {
12720 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12721 : 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
12722 : : const struct rte_flow_action_meter_mark *meter_mark = &upd_meter_mark->meter_mark;
12723 : 0 : struct mlx5_aso_mtr *aso_mtr = mlx5_ipool_get(pool->idx_pool, idx);
12724 : : struct mlx5_flow_meter_info *fm;
12725 : :
12726 [ # # ]: 0 : if (!aso_mtr)
12727 : 0 : return rte_flow_error_set(error, EINVAL,
12728 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12729 : : NULL, "Invalid meter_mark update index");
12730 : : fm = &aso_mtr->fm;
12731 [ # # ]: 0 : if (upd_meter_mark->profile_valid)
12732 : 0 : fm->profile = (struct mlx5_flow_meter_profile *)
12733 : 0 : (meter_mark->profile);
12734 [ # # ]: 0 : if (upd_meter_mark->color_mode_valid)
12735 : 0 : fm->color_aware = meter_mark->color_mode;
12736 [ # # ]: 0 : if (upd_meter_mark->state_valid)
12737 : 0 : fm->is_enable = meter_mark->state;
12738 [ # # ]: 0 : aso_mtr->state = (queue == MLX5_HW_INV_QUEUE) ?
12739 : : ASO_METER_WAIT : ASO_METER_WAIT_ASYNC;
12740 : : /* Update ASO flow meter by wqe. */
12741 [ # # ]: 0 : if (mlx5_aso_meter_update_by_wqe(priv, queue,
12742 : : aso_mtr, &priv->mtr_bulk, job, push))
12743 : 0 : return rte_flow_error_set(error, EINVAL,
12744 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12745 : : NULL, "Unable to update ASO meter WQE");
12746 : : /* Wait for ASO object completion. */
12747 [ # # # # ]: 0 : if (queue == MLX5_HW_INV_QUEUE &&
12748 : 0 : mlx5_aso_mtr_wait(priv, aso_mtr, true))
12749 : 0 : return rte_flow_error_set(error, EINVAL,
12750 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12751 : : NULL, "Unable to wait for ASO meter CQE");
12752 : : return 0;
12753 : : }
12754 : :
12755 : : /**
12756 : : * Update shared action.
12757 : : *
12758 : : * @param[in] dev
12759 : : * Pointer to the rte_eth_dev structure.
12760 : : * @param[in] queue
12761 : : * Which queue to be used.
12762 : : * @param[in] attr
12763 : : * Operation attribute.
12764 : : * @param[in] handle
12765 : : * Action handle to be updated.
12766 : : * @param[in] update
12767 : : * Update value.
12768 : : * @param[in] user_data
12769 : : * Pointer to the user_data.
12770 : : * @param[out] error
12771 : : * Pointer to error structure.
12772 : : *
12773 : : * @return
12774 : : * 0 on success, negative value otherwise and rte_errno is set.
12775 : : */
12776 : : static int
12777 : 0 : flow_hw_action_handle_update(struct rte_eth_dev *dev, uint32_t queue,
12778 : : const struct rte_flow_op_attr *attr,
12779 : : struct rte_flow_action_handle *handle,
12780 : : const void *update,
12781 : : void *user_data,
12782 : : struct rte_flow_error *error)
12783 : : {
12784 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12785 : : const struct rte_flow_modify_conntrack *ct_conf =
12786 : : (const struct rte_flow_modify_conntrack *)update;
12787 : : struct mlx5_hw_q_job *job = NULL;
12788 : 0 : uint32_t act_idx = (uint32_t)(uintptr_t)handle;
12789 : 0 : uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
12790 [ # # ]: 0 : uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
12791 : : int ret = 0;
12792 : : bool push = flow_hw_action_push(attr);
12793 : : bool aso = false;
12794 : 0 : bool force_job = type == MLX5_INDIRECT_ACTION_TYPE_METER_MARK;
12795 : :
12796 [ # # ]: 0 : if (attr || force_job) {
12797 : : job = flow_hw_action_job_init(priv, queue, handle, user_data,
12798 : : NULL, MLX5_HW_Q_JOB_TYPE_UPDATE,
12799 : : MLX5_HW_INDIRECT_TYPE_LEGACY, error);
12800 : : if (!job)
12801 : 0 : return -rte_errno;
12802 : : }
12803 [ # # # # : 0 : switch (type) {
# # ]
12804 : 0 : case MLX5_INDIRECT_ACTION_TYPE_AGE:
12805 : 0 : ret = mlx5_hws_age_action_update(priv, idx, update, error);
12806 : 0 : break;
12807 : 0 : case MLX5_INDIRECT_ACTION_TYPE_CT:
12808 [ # # ]: 0 : if (ct_conf->state)
12809 : : aso = true;
12810 : 0 : ret = flow_hw_conntrack_update(dev, queue, update, idx,
12811 : : job, push, error);
12812 : 0 : break;
12813 : 0 : case MLX5_INDIRECT_ACTION_TYPE_METER_MARK:
12814 : : aso = true;
12815 : 0 : ret = mlx5_flow_update_meter_mark(dev, queue, update, idx, push,
12816 : : job, error);
12817 : 0 : break;
12818 : 0 : case MLX5_INDIRECT_ACTION_TYPE_RSS:
12819 : 0 : ret = flow_dv_action_update(dev, handle, update, error);
12820 : 0 : break;
12821 : 0 : case MLX5_INDIRECT_ACTION_TYPE_QUOTA:
12822 : : aso = true;
12823 : 0 : ret = mlx5_quota_query_update(dev, queue, handle, update, NULL,
12824 : : job, push, error);
12825 : 0 : break;
12826 : 0 : default:
12827 : : ret = -ENOTSUP;
12828 : 0 : rte_flow_error_set(error, ENOTSUP,
12829 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12830 : : "action type not supported");
12831 : 0 : break;
12832 : : }
12833 [ # # ]: 0 : if (job && !force_job)
12834 [ # # ]: 0 : flow_hw_action_finalize(dev, queue, job, push, aso, ret == 0);
12835 : : return ret;
12836 : : }
12837 : :
12838 : : /**
12839 : : * Destroy shared action.
12840 : : *
12841 : : * @param[in] dev
12842 : : * Pointer to the rte_eth_dev structure.
12843 : : * @param[in] queue
12844 : : * Which queue to be used.
12845 : : * @param[in] attr
12846 : : * Operation attribute.
12847 : : * @param[in] handle
12848 : : * Action handle to be destroyed.
12849 : : * @param[in] user_data
12850 : : * Pointer to the user_data.
12851 : : * @param[out] error
12852 : : * Pointer to error structure.
12853 : : *
12854 : : * @return
12855 : : * 0 on success, negative value otherwise and rte_errno is set.
12856 : : */
12857 : : static int
12858 : 0 : flow_hw_action_handle_destroy(struct rte_eth_dev *dev, uint32_t queue,
12859 : : const struct rte_flow_op_attr *attr,
12860 : : struct rte_flow_action_handle *handle,
12861 : : void *user_data,
12862 : : struct rte_flow_error *error)
12863 : : {
12864 : 0 : uint32_t act_idx = (uint32_t)(uintptr_t)handle;
12865 : 0 : uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
12866 : 0 : uint32_t age_idx = act_idx & MLX5_HWS_AGE_IDX_MASK;
12867 : : uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
12868 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12869 [ # # ]: 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
12870 : : struct mlx5_hw_q_job *job = NULL;
12871 : : struct mlx5_aso_mtr *aso_mtr;
12872 : : struct mlx5_flow_meter_info *fm;
12873 : : bool push = flow_hw_action_push(attr);
12874 : : bool aso = false;
12875 : : int ret = 0;
12876 : 0 : bool force_job = type == MLX5_INDIRECT_ACTION_TYPE_METER_MARK;
12877 : :
12878 [ # # ]: 0 : if (attr || force_job) {
12879 : : job = flow_hw_action_job_init(priv, queue, handle, user_data,
12880 : : NULL, MLX5_HW_Q_JOB_TYPE_DESTROY,
12881 : : MLX5_HW_INDIRECT_TYPE_LEGACY, error);
12882 : : if (!job)
12883 : 0 : return -rte_errno;
12884 : : }
12885 [ # # # # : 0 : switch (type) {
# # # ]
12886 : 0 : case MLX5_INDIRECT_ACTION_TYPE_AGE:
12887 : 0 : ret = mlx5_hws_age_action_destroy(priv, age_idx, error);
12888 : 0 : break;
12889 : 0 : case MLX5_INDIRECT_ACTION_TYPE_COUNT:
12890 [ # # ]: 0 : age_idx = mlx5_hws_cnt_age_get(priv->hws_cpool, act_idx);
12891 [ # # ]: 0 : if (age_idx != 0)
12892 : : /*
12893 : : * If this counter belongs to indirect AGE, here is the
12894 : : * time to update the AGE.
12895 : : */
12896 : : mlx5_hws_age_nb_cnt_decrease(priv, age_idx);
12897 [ # # ]: 0 : mlx5_hws_cnt_shared_put(priv->hws_cpool, &act_idx);
12898 : : break;
12899 : 0 : case MLX5_INDIRECT_ACTION_TYPE_CT:
12900 : 0 : ret = flow_hw_conntrack_destroy(dev, idx, error);
12901 : 0 : break;
12902 : 0 : case MLX5_INDIRECT_ACTION_TYPE_METER_MARK:
12903 : 0 : aso_mtr = mlx5_ipool_get(pool->idx_pool, idx);
12904 [ # # ]: 0 : if (!aso_mtr) {
12905 : : ret = -EINVAL;
12906 : 0 : rte_flow_error_set(error, EINVAL,
12907 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12908 : : NULL, "Invalid meter_mark destroy index");
12909 : 0 : break;
12910 : : }
12911 : : fm = &aso_mtr->fm;
12912 : 0 : fm->is_enable = 0;
12913 : : /* Update ASO flow meter by wqe. */
12914 [ # # ]: 0 : if (mlx5_aso_meter_update_by_wqe(priv, queue, aso_mtr,
12915 : : &priv->mtr_bulk, job, push)) {
12916 : : ret = -EINVAL;
12917 : 0 : rte_flow_error_set(error, EINVAL,
12918 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12919 : : NULL, "Unable to update ASO meter WQE");
12920 : 0 : break;
12921 : : }
12922 : : /* Wait for ASO object completion. */
12923 [ # # # # ]: 0 : if (queue == MLX5_HW_INV_QUEUE &&
12924 : 0 : mlx5_aso_mtr_wait(priv, aso_mtr, true)) {
12925 : : ret = -EINVAL;
12926 : 0 : rte_flow_error_set(error, EINVAL,
12927 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12928 : : NULL, "Unable to wait for ASO meter CQE");
12929 : 0 : break;
12930 : : }
12931 : : aso = true;
12932 : : break;
12933 : 0 : case MLX5_INDIRECT_ACTION_TYPE_RSS:
12934 : 0 : ret = flow_dv_action_destroy(dev, handle, error);
12935 : 0 : break;
12936 : : case MLX5_INDIRECT_ACTION_TYPE_QUOTA:
12937 : : break;
12938 : 0 : default:
12939 : : ret = -ENOTSUP;
12940 : 0 : rte_flow_error_set(error, ENOTSUP,
12941 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12942 : : "action type not supported");
12943 : 0 : break;
12944 : : }
12945 [ # # ]: 0 : if (job && !force_job)
12946 [ # # ]: 0 : flow_hw_action_finalize(dev, queue, job, push, aso, ret == 0);
12947 : : return ret;
12948 : : }
12949 : :
12950 : : static int
12951 : 0 : flow_hw_query_counter(const struct rte_eth_dev *dev, uint32_t counter,
12952 : : void *data, struct rte_flow_error *error)
12953 : : {
12954 : : struct mlx5_hws_cnt_pool *hpool;
12955 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
12956 : : struct mlx5_hws_cnt *cnt;
12957 : : struct rte_flow_query_count *qc = data;
12958 : : uint32_t iidx;
12959 : : uint64_t pkts, bytes;
12960 : :
12961 [ # # ]: 0 : if (!mlx5_hws_cnt_id_valid(counter))
12962 : 0 : return rte_flow_error_set(error, EINVAL,
12963 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12964 : : "counter are not available");
12965 [ # # ]: 0 : hpool = mlx5_hws_cnt_host_pool(priv->hws_cpool);
12966 : : iidx = mlx5_hws_cnt_iidx(hpool, counter);
12967 : 0 : cnt = &hpool->pool[iidx];
12968 : : __hws_cnt_query_raw(priv->hws_cpool, counter, &pkts, &bytes);
12969 : 0 : qc->hits_set = 1;
12970 : 0 : qc->bytes_set = 1;
12971 : 0 : qc->hits = pkts - cnt->reset.hits;
12972 : 0 : qc->bytes = bytes - cnt->reset.bytes;
12973 [ # # ]: 0 : if (qc->reset) {
12974 : 0 : cnt->reset.bytes = bytes;
12975 : 0 : cnt->reset.hits = pkts;
12976 : : }
12977 : : return 0;
12978 : : }
12979 : :
12980 : : /**
12981 : : * Query a flow rule AGE action for aging information.
12982 : : *
12983 : : * @param[in] dev
12984 : : * Pointer to Ethernet device.
12985 : : * @param[in] age_idx
12986 : : * Index of AGE action parameter.
12987 : : * @param[out] data
12988 : : * Data retrieved by the query.
12989 : : * @param[out] error
12990 : : * Perform verbose error reporting if not NULL.
12991 : : *
12992 : : * @return
12993 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
12994 : : */
12995 : : static int
12996 : 0 : flow_hw_query_age(const struct rte_eth_dev *dev, uint32_t age_idx, void *data,
12997 : : struct rte_flow_error *error)
12998 : : {
12999 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13000 : 0 : struct mlx5_age_info *age_info = GET_PORT_AGE_INFO(priv);
13001 : 0 : struct mlx5_indexed_pool *ipool = age_info->ages_ipool;
13002 : 0 : struct mlx5_hws_age_param *param = mlx5_ipool_get(ipool, age_idx);
13003 : : struct rte_flow_query_age *resp = data;
13004 : :
13005 [ # # # # ]: 0 : if (!param || !param->timeout)
13006 : 0 : return rte_flow_error_set(error, EINVAL,
13007 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13008 : : NULL, "age data not available");
13009 [ # # # ]: 0 : switch (rte_atomic_load_explicit(¶m->state, rte_memory_order_relaxed)) {
13010 : 0 : case HWS_AGE_AGED_OUT_REPORTED:
13011 : : case HWS_AGE_AGED_OUT_NOT_REPORTED:
13012 : 0 : resp->aged = 1;
13013 : 0 : break;
13014 : 0 : case HWS_AGE_CANDIDATE:
13015 : : case HWS_AGE_CANDIDATE_INSIDE_RING:
13016 : 0 : resp->aged = 0;
13017 : 0 : break;
13018 : : case HWS_AGE_FREE:
13019 : : /*
13020 : : * When state is FREE the flow itself should be invalid.
13021 : : * Fall-through.
13022 : : */
13023 : : default:
13024 : : MLX5_ASSERT(0);
13025 : : break;
13026 : : }
13027 : 0 : resp->sec_since_last_hit_valid = !resp->aged;
13028 [ # # ]: 0 : if (resp->sec_since_last_hit_valid)
13029 : 0 : resp->sec_since_last_hit = rte_atomic_load_explicit
13030 : : (¶m->sec_since_last_hit, rte_memory_order_relaxed);
13031 : : return 0;
13032 : : }
13033 : :
13034 : : static int
13035 : 0 : flow_hw_query(struct rte_eth_dev *dev, struct rte_flow *flow,
13036 : : const struct rte_flow_action *actions, void *data,
13037 : : struct rte_flow_error *error)
13038 : : {
13039 : : int ret = -EINVAL;
13040 : : struct rte_flow_hw *hw_flow = (struct rte_flow_hw *)flow;
13041 : : struct rte_flow_hw_aux *aux;
13042 : :
13043 [ # # ]: 0 : for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
13044 [ # # # # ]: 0 : switch (actions->type) {
13045 : : case RTE_FLOW_ACTION_TYPE_VOID:
13046 : : break;
13047 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
13048 [ # # ]: 0 : if (!(hw_flow->flags & MLX5_FLOW_HW_FLOW_FLAG_CNT_ID))
13049 : 0 : return rte_flow_error_set(error, EINVAL,
13050 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13051 : : "counter not defined in the rule");
13052 : 0 : ret = flow_hw_query_counter(dev, hw_flow->cnt_id, data,
13053 : : error);
13054 : 0 : break;
13055 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
13056 [ # # ]: 0 : if (!(hw_flow->flags & MLX5_FLOW_HW_FLOW_FLAG_AGE_IDX))
13057 : 0 : return rte_flow_error_set(error, EINVAL,
13058 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13059 : : "age data not available");
13060 [ # # ]: 0 : aux = mlx5_flow_hw_aux(dev->data->port_id, hw_flow);
13061 : 0 : ret = flow_hw_query_age(dev, mlx5_flow_hw_aux_get_age_idx(hw_flow, aux),
13062 : : data, error);
13063 : 0 : break;
13064 : 0 : default:
13065 : 0 : return rte_flow_error_set(error, ENOTSUP,
13066 : : RTE_FLOW_ERROR_TYPE_ACTION,
13067 : : actions,
13068 : : "action not supported");
13069 : : }
13070 : : }
13071 : : return ret;
13072 : : }
13073 : :
13074 : : /**
13075 : : * Validate indirect action.
13076 : : *
13077 : : * @param[in] dev
13078 : : * Pointer to the Ethernet device structure.
13079 : : * @param[in] conf
13080 : : * Shared action configuration.
13081 : : * @param[in] action
13082 : : * Action specification used to create indirect action.
13083 : : * @param[out] error
13084 : : * Perform verbose error reporting if not NULL. Initialized in case of
13085 : : * error only.
13086 : : *
13087 : : * @return
13088 : : * 0 on success, otherwise negative errno value.
13089 : : */
13090 : : static int
13091 : 0 : flow_hw_action_validate(struct rte_eth_dev *dev,
13092 : : const struct rte_flow_indir_action_conf *conf,
13093 : : const struct rte_flow_action *action,
13094 : : struct rte_flow_error *err)
13095 : : {
13096 : 0 : struct rte_flow_error shadow_error = {0, };
13097 : :
13098 [ # # ]: 0 : if (!err)
13099 : : err = &shadow_error;
13100 : 0 : return flow_hw_action_handle_validate(dev, MLX5_HW_INV_QUEUE, NULL,
13101 : : conf, action, NULL, err);
13102 : : }
13103 : :
13104 : : /**
13105 : : * Create indirect action.
13106 : : *
13107 : : * @param[in] dev
13108 : : * Pointer to the Ethernet device structure.
13109 : : * @param[in] conf
13110 : : * Shared action configuration.
13111 : : * @param[in] action
13112 : : * Action specification used to create indirect action.
13113 : : * @param[out] error
13114 : : * Perform verbose error reporting if not NULL. Initialized in case of
13115 : : * error only.
13116 : : *
13117 : : * @return
13118 : : * A valid shared action handle in case of success, NULL otherwise and
13119 : : * rte_errno is set.
13120 : : */
13121 : : static struct rte_flow_action_handle *
13122 : 0 : flow_hw_action_create(struct rte_eth_dev *dev,
13123 : : const struct rte_flow_indir_action_conf *conf,
13124 : : const struct rte_flow_action *action,
13125 : : struct rte_flow_error *err)
13126 : : {
13127 : 0 : return flow_hw_action_handle_create(dev, MLX5_HW_INV_QUEUE,
13128 : : NULL, conf, action, NULL, err);
13129 : : }
13130 : :
13131 : : /**
13132 : : * Destroy the indirect action.
13133 : : * Release action related resources on the NIC and the memory.
13134 : : * Lock free, (mutex should be acquired by caller).
13135 : : * Dispatcher for action type specific call.
13136 : : *
13137 : : * @param[in] dev
13138 : : * Pointer to the Ethernet device structure.
13139 : : * @param[in] handle
13140 : : * The indirect action object handle to be removed.
13141 : : * @param[out] error
13142 : : * Perform verbose error reporting if not NULL. Initialized in case of
13143 : : * error only.
13144 : : *
13145 : : * @return
13146 : : * 0 on success, otherwise negative errno value.
13147 : : */
13148 : : static int
13149 : 0 : flow_hw_action_destroy(struct rte_eth_dev *dev,
13150 : : struct rte_flow_action_handle *handle,
13151 : : struct rte_flow_error *error)
13152 : : {
13153 : 0 : return flow_hw_action_handle_destroy(dev, MLX5_HW_INV_QUEUE,
13154 : : NULL, handle, NULL, error);
13155 : : }
13156 : :
13157 : : /**
13158 : : * Updates in place shared action configuration.
13159 : : *
13160 : : * @param[in] dev
13161 : : * Pointer to the Ethernet device structure.
13162 : : * @param[in] handle
13163 : : * The indirect action object handle to be updated.
13164 : : * @param[in] update
13165 : : * Action specification used to modify the action pointed by *handle*.
13166 : : * *update* could be of same type with the action pointed by the *handle*
13167 : : * handle argument, or some other structures like a wrapper, depending on
13168 : : * the indirect action type.
13169 : : * @param[out] error
13170 : : * Perform verbose error reporting if not NULL. Initialized in case of
13171 : : * error only.
13172 : : *
13173 : : * @return
13174 : : * 0 on success, otherwise negative errno value.
13175 : : */
13176 : : static int
13177 : 0 : flow_hw_action_update(struct rte_eth_dev *dev,
13178 : : struct rte_flow_action_handle *handle,
13179 : : const void *update,
13180 : : struct rte_flow_error *err)
13181 : : {
13182 : 0 : return flow_hw_action_handle_update(dev, MLX5_HW_INV_QUEUE,
13183 : : NULL, handle, update, NULL, err);
13184 : : }
13185 : :
13186 : : static int
13187 : 0 : flow_hw_action_handle_query(struct rte_eth_dev *dev, uint32_t queue,
13188 : : const struct rte_flow_op_attr *attr,
13189 : : const struct rte_flow_action_handle *handle,
13190 : : void *data, void *user_data,
13191 : : struct rte_flow_error *error)
13192 : : {
13193 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13194 : : struct mlx5_hw_q_job *job = NULL;
13195 : 0 : uint32_t act_idx = (uint32_t)(uintptr_t)handle;
13196 : 0 : uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
13197 [ # # ]: 0 : uint32_t idx = MLX5_INDIRECT_ACTION_IDX_GET(handle);
13198 : : uint32_t age_idx = act_idx & MLX5_HWS_AGE_IDX_MASK;
13199 : : int ret;
13200 : : bool push = flow_hw_action_push(attr);
13201 : : bool aso = false;
13202 : :
13203 [ # # ]: 0 : if (attr) {
13204 : : job = flow_hw_action_job_init(priv, queue, handle, user_data,
13205 : : data, MLX5_HW_Q_JOB_TYPE_QUERY,
13206 : : MLX5_HW_INDIRECT_TYPE_LEGACY, error);
13207 : : if (!job)
13208 : 0 : return -rte_errno;
13209 : : }
13210 [ # # # # : 0 : switch (type) {
# ]
13211 : 0 : case MLX5_INDIRECT_ACTION_TYPE_AGE:
13212 : 0 : ret = flow_hw_query_age(dev, age_idx, data, error);
13213 : 0 : break;
13214 : 0 : case MLX5_INDIRECT_ACTION_TYPE_COUNT:
13215 : 0 : ret = flow_hw_query_counter(dev, act_idx, data, error);
13216 : 0 : break;
13217 : 0 : case MLX5_INDIRECT_ACTION_TYPE_CT:
13218 : : aso = true;
13219 [ # # ]: 0 : if (job)
13220 : 0 : job->query.user = data;
13221 : 0 : ret = flow_hw_conntrack_query(dev, queue, idx, data,
13222 : : job, push, error);
13223 : 0 : break;
13224 : 0 : case MLX5_INDIRECT_ACTION_TYPE_QUOTA:
13225 : : aso = true;
13226 : 0 : ret = mlx5_quota_query(dev, queue, handle, data,
13227 : : job, push, error);
13228 : 0 : break;
13229 : 0 : default:
13230 : : ret = -ENOTSUP;
13231 : 0 : rte_flow_error_set(error, ENOTSUP,
13232 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13233 : : "action type not supported");
13234 : 0 : break;
13235 : : }
13236 [ # # ]: 0 : if (job)
13237 [ # # ]: 0 : flow_hw_action_finalize(dev, queue, job, push, aso, ret == 0);
13238 : : return ret;
13239 : : }
13240 : :
13241 : : static int
13242 : 0 : flow_hw_async_action_handle_query_update
13243 : : (struct rte_eth_dev *dev, uint32_t queue,
13244 : : const struct rte_flow_op_attr *attr,
13245 : : struct rte_flow_action_handle *handle,
13246 : : const void *update, void *query,
13247 : : enum rte_flow_query_update_mode qu_mode,
13248 : : void *user_data, struct rte_flow_error *error)
13249 : : {
13250 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
13251 : : bool push = flow_hw_action_push(attr);
13252 : : bool aso = false;
13253 : : struct mlx5_hw_q_job *job = NULL;
13254 : : int ret = 0;
13255 : :
13256 [ # # ]: 0 : if (attr) {
13257 : : job = flow_hw_action_job_init(priv, queue, handle, user_data,
13258 : : query,
13259 : : MLX5_HW_Q_JOB_TYPE_UPDATE_QUERY,
13260 : : MLX5_HW_INDIRECT_TYPE_LEGACY, error);
13261 : : if (!job)
13262 : 0 : return -rte_errno;
13263 : : }
13264 [ # # ]: 0 : switch (MLX5_INDIRECT_ACTION_TYPE_GET(handle)) {
13265 : 0 : case MLX5_INDIRECT_ACTION_TYPE_QUOTA:
13266 [ # # ]: 0 : if (qu_mode != RTE_FLOW_QU_QUERY_FIRST) {
13267 : 0 : ret = rte_flow_error_set
13268 : : (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION_CONF,
13269 : : NULL, "quota action must query before update");
13270 : 0 : break;
13271 : : }
13272 : : aso = true;
13273 : 0 : ret = mlx5_quota_query_update(dev, queue, handle,
13274 : : update, query, job, push, error);
13275 : 0 : break;
13276 : 0 : default:
13277 : 0 : ret = rte_flow_error_set(error, ENOTSUP,
13278 : : RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, "update and query not supportred");
13279 : : }
13280 [ # # ]: 0 : if (job)
13281 [ # # ]: 0 : flow_hw_action_finalize(dev, queue, job, push, aso, ret == 0);
13282 : : return ret;
13283 : : }
13284 : :
13285 : : static int
13286 : 0 : flow_hw_action_query(struct rte_eth_dev *dev,
13287 : : const struct rte_flow_action_handle *handle, void *data,
13288 : : struct rte_flow_error *error)
13289 : : {
13290 : 0 : return flow_hw_action_handle_query(dev, MLX5_HW_INV_QUEUE, NULL,
13291 : : handle, data, NULL, error);
13292 : : }
13293 : :
13294 : : static int
13295 : 0 : flow_hw_action_query_update(struct rte_eth_dev *dev,
13296 : : struct rte_flow_action_handle *handle,
13297 : : const void *update, void *query,
13298 : : enum rte_flow_query_update_mode qu_mode,
13299 : : struct rte_flow_error *error)
13300 : : {
13301 : 0 : return flow_hw_async_action_handle_query_update(dev, MLX5_HW_INV_QUEUE,
13302 : : NULL, handle, update,
13303 : : query, qu_mode, NULL,
13304 : : error);
13305 : : }
13306 : :
13307 : : /**
13308 : : * Get aged-out flows of a given port on the given HWS flow queue.
13309 : : *
13310 : : * @param[in] dev
13311 : : * Pointer to the Ethernet device structure.
13312 : : * @param[in] queue_id
13313 : : * Flow queue to query. Ignored when RTE_FLOW_PORT_FLAG_STRICT_QUEUE not set.
13314 : : * @param[in, out] contexts
13315 : : * The address of an array of pointers to the aged-out flows contexts.
13316 : : * @param[in] nb_contexts
13317 : : * The length of context array pointers.
13318 : : * @param[out] error
13319 : : * Perform verbose error reporting if not NULL. Initialized in case of
13320 : : * error only.
13321 : : *
13322 : : * @return
13323 : : * if nb_contexts is 0, return the amount of all aged contexts.
13324 : : * if nb_contexts is not 0 , return the amount of aged flows reported
13325 : : * in the context array, otherwise negative errno value.
13326 : : */
13327 : : static int
13328 : 0 : flow_hw_get_q_aged_flows(struct rte_eth_dev *dev, uint32_t queue_id,
13329 : : void **contexts, uint32_t nb_contexts,
13330 : : struct rte_flow_error *error)
13331 : : {
13332 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13333 : 0 : struct mlx5_age_info *age_info = GET_PORT_AGE_INFO(priv);
13334 : : struct rte_ring *r;
13335 : : int nb_flows = 0;
13336 : :
13337 [ # # ]: 0 : if (nb_contexts && !contexts)
13338 : 0 : return rte_flow_error_set(error, EINVAL,
13339 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13340 : : NULL, "empty context");
13341 [ # # ]: 0 : if (!priv->hws_age_req)
13342 : 0 : return rte_flow_error_set(error, ENOENT,
13343 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13344 : : NULL, "No aging initialized");
13345 [ # # ]: 0 : if (priv->hws_strict_queue) {
13346 [ # # ]: 0 : if (queue_id >= age_info->hw_q_age->nb_rings)
13347 : 0 : return rte_flow_error_set(error, EINVAL,
13348 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13349 : : NULL, "invalid queue id");
13350 : 0 : r = age_info->hw_q_age->aged_lists[queue_id];
13351 : : } else {
13352 : 0 : r = age_info->hw_age.aged_list;
13353 : 0 : MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
13354 : : }
13355 [ # # ]: 0 : if (nb_contexts == 0)
13356 : 0 : return rte_ring_count(r);
13357 [ # # ]: 0 : while ((uint32_t)nb_flows < nb_contexts) {
13358 : : uint32_t age_idx;
13359 : :
13360 : : if (rte_ring_dequeue_elem(r, &age_idx, sizeof(uint32_t)) < 0)
13361 : : break;
13362 : : /* get the AGE context if the aged-out index is still valid. */
13363 : 0 : contexts[nb_flows] = mlx5_hws_age_context_get(priv, age_idx);
13364 [ # # ]: 0 : if (!contexts[nb_flows])
13365 : 0 : continue;
13366 : 0 : nb_flows++;
13367 : : }
13368 : : return nb_flows;
13369 : : }
13370 : :
13371 : : /**
13372 : : * Get aged-out flows.
13373 : : *
13374 : : * This function is relevant only if RTE_FLOW_PORT_FLAG_STRICT_QUEUE isn't set.
13375 : : *
13376 : : * @param[in] dev
13377 : : * Pointer to the Ethernet device structure.
13378 : : * @param[in] contexts
13379 : : * The address of an array of pointers to the aged-out flows contexts.
13380 : : * @param[in] nb_contexts
13381 : : * The length of context array pointers.
13382 : : * @param[out] error
13383 : : * Perform verbose error reporting if not NULL. Initialized in case of
13384 : : * error only.
13385 : : *
13386 : : * @return
13387 : : * how many contexts get in success, otherwise negative errno value.
13388 : : * if nb_contexts is 0, return the amount of all aged contexts.
13389 : : * if nb_contexts is not 0 , return the amount of aged flows reported
13390 : : * in the context array.
13391 : : */
13392 : : static int
13393 : 0 : flow_hw_get_aged_flows(struct rte_eth_dev *dev, void **contexts,
13394 : : uint32_t nb_contexts, struct rte_flow_error *error)
13395 : : {
13396 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13397 : :
13398 [ # # ]: 0 : if (priv->hws_strict_queue)
13399 : 0 : DRV_LOG(WARNING,
13400 : : "port %u get aged flows called in strict queue mode.",
13401 : : dev->data->port_id);
13402 : 0 : return flow_hw_get_q_aged_flows(dev, 0, contexts, nb_contexts, error);
13403 : : }
13404 : : /**
13405 : : * Initialization function for non template API which calls
13406 : : * flow_hw_configure with default values.
13407 : : * Configure non queues cause 1 queue is configured by default for inner usage.
13408 : : *
13409 : : * @param[in] dev
13410 : : * Pointer to the Ethernet device structure.
13411 : : * @param[out] error
13412 : : * Pointer to the error structure.
13413 : : *
13414 : : * @return
13415 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
13416 : : */
13417 : : int
13418 : 0 : flow_hw_init(struct rte_eth_dev *dev,
13419 : : struct rte_flow_error *error)
13420 : : {
13421 : 0 : const struct rte_flow_port_attr port_attr = {0};
13422 : 0 : const struct rte_flow_queue_attr queue_attr = {.size = MLX5_NT_DEFAULT_QUEUE_SIZE};
13423 : 0 : const struct rte_flow_queue_attr *attr_list = &queue_attr;
13424 : :
13425 : : /**
13426 : : * If user uses template and non template API:
13427 : : * User will call flow_hw_configure and non template
13428 : : * API will use the allocated actions.
13429 : : * Init function will not call flow_hw_configure.
13430 : : *
13431 : : * If user uses only non template API's:
13432 : : * Init function will call flow_hw_configure.
13433 : : * It will not allocate memory for actions.
13434 : : * When needed allocation, it will handle same as for SWS today,
13435 : : * meaning using bulk allocations and resize as needed.
13436 : : */
13437 : : /* Configure hws with default values. */
13438 : 0 : DRV_LOG(DEBUG, "Apply default configuration, zero number of queues, inner control queue size is %u",
13439 : : MLX5_NT_DEFAULT_QUEUE_SIZE);
13440 : 0 : return __flow_hw_configure(dev, &port_attr, 0, &attr_list, true, error);
13441 : : }
13442 : :
13443 : 0 : static int flow_hw_prepare(struct rte_eth_dev *dev,
13444 : : const struct rte_flow_action actions[] __rte_unused,
13445 : : enum mlx5_flow_type type,
13446 : : struct rte_flow_hw **flow,
13447 : : struct rte_flow_error *error)
13448 : : {
13449 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13450 : 0 : uint32_t idx = 0;
13451 : :
13452 : : /*
13453 : : * Notice pool idx size = (sizeof(struct rte_flow_hw)
13454 : : * + sizeof(struct rte_flow_nt2hws)) for HWS mode.
13455 : : */
13456 : 0 : *flow = mlx5_ipool_zmalloc(priv->flows[type], &idx);
13457 [ # # ]: 0 : if (!(*flow))
13458 : 0 : return rte_flow_error_set(error, ENOMEM,
13459 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13460 : : "cannot allocate flow memory");
13461 : : /* Allocating 2 structures in one pool slot, updating nt2hw pointer.*/
13462 : 0 : (*flow)->nt2hws = (struct rte_flow_nt2hws *)
13463 : 0 : ((uintptr_t)(*flow) + sizeof(struct rte_flow_hw));
13464 : 0 : (*flow)->idx = idx;
13465 : 0 : (*flow)->nt2hws->flow_aux = mlx5_malloc(MLX5_MEM_ZERO, sizeof(struct rte_flow_hw_aux),
13466 : 0 : RTE_CACHE_LINE_SIZE, rte_dev_numa_node(dev->device));
13467 [ # # ]: 0 : if (!(*flow)->nt2hws->flow_aux)
13468 : 0 : return rte_flow_error_set(error, ENOMEM,
13469 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13470 : : "cannot allocate flow aux memory");
13471 : : return 0;
13472 : : }
13473 : :
13474 : : static inline void
13475 : 0 : flow_hw_set_dv_fields(struct rte_flow_template_table_attr *table_attr, uint32_t fdb_unified_en,
13476 : : bool *root, uint8_t *ft_type, uint64_t *flags)
13477 : : {
13478 [ # # ]: 0 : if (table_attr->flow_attr.transfer)
13479 : 0 : *ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
13480 : : else
13481 : 0 : *ft_type = table_attr->flow_attr.egress ?
13482 : 0 : MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
13483 : : MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
13484 : 0 : uint32_t group = table_attr->flow_attr.group;
13485 : 0 : *root = group ? 0 : 1;
13486 : 0 : *flags = mlx5_hw_act_flag[!!group][get_mlx5dr_table_type(&table_attr->flow_attr,
13487 : : table_attr->specialize,
13488 : : fdb_unified_en)];
13489 : 0 : }
13490 : :
13491 : : static int
13492 : 0 : flow_hw_modify_hdr_resource_register
13493 : : (struct rte_eth_dev *dev,
13494 : : struct rte_flow_template_table *table,
13495 : : struct mlx5_hw_actions *hw_acts,
13496 : : struct rte_flow_hw *dev_flow,
13497 : : struct rte_flow_error *error)
13498 : : {
13499 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
13500 : : bool unified_fdb = is_unified_fdb(priv);
13501 : 0 : struct rte_flow_template_table_attr *table_attr = &table->cfg.attr;
13502 : 0 : struct mlx5_flow_dv_modify_hdr_resource *dv_resource_ptr = NULL;
13503 : : union {
13504 : : struct mlx5_flow_dv_modify_hdr_resource dv_resource;
13505 : : uint8_t data[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
13506 : : sizeof(struct mlx5_modification_cmd) * MLX5_MHDR_MAX_CMD];
13507 : : } dummy;
13508 : : int ret;
13509 : :
13510 [ # # ]: 0 : if (hw_acts->mhdr) {
13511 : 0 : dummy.dv_resource.actions_num = hw_acts->mhdr->mhdr_cmds_num;
13512 : 0 : memcpy(dummy.dv_resource.actions, hw_acts->mhdr->mhdr_cmds,
13513 : 0 : sizeof(struct mlx5_modification_cmd) * dummy.dv_resource.actions_num);
13514 : : } else {
13515 : : return 0;
13516 : : }
13517 : 0 : flow_hw_set_dv_fields(table_attr, unified_fdb,
13518 : : &dummy.dv_resource.root, &dummy.dv_resource.ft_type,
13519 : : &dummy.dv_resource.flags);
13520 : 0 : dummy.dv_resource.flags |= MLX5DR_ACTION_FLAG_SHARED;
13521 : 0 : ret = __flow_modify_hdr_resource_register(dev, &dummy.dv_resource,
13522 : : &dv_resource_ptr, error);
13523 [ # # ]: 0 : if (ret)
13524 : : return ret;
13525 : : MLX5_ASSERT(dv_resource_ptr);
13526 : 0 : dev_flow->nt2hws->modify_hdr = dv_resource_ptr;
13527 : : /* keep action for the rule construction. */
13528 : 0 : hw_acts->rule_acts[hw_acts->mhdr->pos].action = dv_resource_ptr->action;
13529 : : /* Bulk size is 1, so index is 1. */
13530 : 0 : dev_flow->res_idx = 1;
13531 : 0 : return 0;
13532 : : }
13533 : :
13534 : : static int
13535 : 0 : flow_hw_encap_decap_resource_register
13536 : : (struct rte_eth_dev *dev,
13537 : : struct rte_flow_template_table *table,
13538 : : struct mlx5_hw_actions *hw_acts,
13539 : : struct rte_flow_hw *dev_flow,
13540 : : struct rte_flow_error *error)
13541 : : {
13542 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
13543 : : bool unified_fdb = is_unified_fdb(priv);
13544 : 0 : struct rte_flow_template_table_attr *table_attr = &table->cfg.attr;
13545 : 0 : struct mlx5_flow_dv_encap_decap_resource *dv_resource_ptr = NULL;
13546 : : struct mlx5_flow_dv_encap_decap_resource dv_resource;
13547 : : struct mlx5_tbl_multi_pattern_ctx *mpctx = &table->mpctx;
13548 : : int ret;
13549 : : bool is_root;
13550 : : int ix;
13551 : :
13552 [ # # ]: 0 : if (hw_acts->encap_decap)
13553 : 0 : dv_resource.reformat_type = hw_acts->encap_decap->action_type;
13554 : : else
13555 : : return 0;
13556 : 0 : flow_hw_set_dv_fields(table_attr, unified_fdb, &is_root, &dv_resource.ft_type,
13557 : : &dv_resource.flags);
13558 [ # # ]: 0 : ix = mlx5_bwc_multi_pattern_reformat_to_index((enum mlx5dr_action_type)
13559 : : dv_resource.reformat_type);
13560 : : if (ix < 0)
13561 : 0 : return ix;
13562 [ # # ]: 0 : if (hw_acts->encap_decap->shared) {
13563 : 0 : dv_resource.size = hw_acts->encap_decap->data_size;
13564 : : MLX5_ASSERT(dv_resource.size <= MLX5_ENCAP_MAX_LEN);
13565 : 0 : memcpy(&dv_resource.buf, hw_acts->encap_decap->data, dv_resource.size);
13566 : 0 : dv_resource.flags |= MLX5DR_ACTION_FLAG_SHARED;
13567 : : } else {
13568 : 0 : typeof(mpctx->reformat[0]) *reformat = mpctx->reformat + ix;
13569 [ # # ]: 0 : if (!reformat->elements_num)
13570 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
13571 : : NULL, "No reformat action exist in the table.");
13572 : 0 : dv_resource.size = reformat->reformat_hdr->sz;
13573 : : MLX5_ASSERT(dv_resource.size <= MLX5_ENCAP_MAX_LEN);
13574 : 0 : memcpy(&dv_resource.buf, reformat->reformat_hdr->data, dv_resource.size);
13575 : : }
13576 : 0 : ret = __flow_encap_decap_resource_register(dev, &dv_resource, is_root,
13577 : : &dv_resource_ptr, error);
13578 [ # # ]: 0 : if (ret)
13579 : : return ret;
13580 : : MLX5_ASSERT(dv_resource_ptr);
13581 : 0 : dev_flow->nt2hws->rix_encap_decap = dv_resource_ptr->idx;
13582 : : /* keep action for the rule construction. */
13583 [ # # ]: 0 : if (hw_acts->encap_decap->shared)
13584 : 0 : hw_acts->rule_acts[hw_acts->encap_decap_pos].action = dv_resource_ptr->action;
13585 : : else
13586 : 0 : mpctx->segments[0].reformat_action[ix] = dv_resource_ptr->action;
13587 : : /* Bulk size is 1, so index is 1. */
13588 : 0 : dev_flow->res_idx = 1;
13589 : 0 : return 0;
13590 : : }
13591 : :
13592 : : static enum rte_flow_action_type
13593 : : flow_nta_get_indirect_action_type(const struct rte_flow_action *action)
13594 : : {
13595 [ # # ]: 0 : switch (MLX5_INDIRECT_ACTION_TYPE_GET(action->conf)) {
13596 : : case MLX5_INDIRECT_ACTION_TYPE_RSS:
13597 : : return RTE_FLOW_ACTION_TYPE_RSS;
13598 : : case MLX5_INDIRECT_ACTION_TYPE_AGE:
13599 : : return RTE_FLOW_ACTION_TYPE_AGE;
13600 : : case MLX5_INDIRECT_ACTION_TYPE_COUNT:
13601 : : return RTE_FLOW_ACTION_TYPE_COUNT;
13602 : : case MLX5_INDIRECT_ACTION_TYPE_CT:
13603 : : return RTE_FLOW_ACTION_TYPE_CONNTRACK;
13604 : : default:
13605 : : break;
13606 : : }
13607 : : return RTE_FLOW_ACTION_TYPE_END;
13608 : : }
13609 : :
13610 : : static void
13611 : : flow_nta_set_mh_mask_conf(const struct rte_flow_action_modify_field *action_conf,
13612 : : struct rte_flow_action_modify_field *mask_conf)
13613 : : {
13614 : : memset(mask_conf, 0xff, sizeof(*mask_conf));
13615 : 0 : mask_conf->operation = action_conf->operation;
13616 : 0 : mask_conf->dst.field = action_conf->dst.field;
13617 : 0 : mask_conf->src.field = action_conf->src.field;
13618 : : }
13619 : :
13620 : : union actions_conf {
13621 : : struct rte_flow_action_modify_field modify_field;
13622 : : struct rte_flow_action_raw_encap raw_encap;
13623 : : struct rte_flow_action_vxlan_encap vxlan_encap;
13624 : : struct rte_flow_action_nvgre_encap nvgre_encap;
13625 : : };
13626 : :
13627 : : static int
13628 : 0 : flow_nta_build_template_mask(const struct rte_flow_action actions[],
13629 : : struct rte_flow_action masks[MLX5_HW_MAX_ACTS],
13630 : : union actions_conf mask_conf[MLX5_HW_MAX_ACTS])
13631 : : {
13632 : : int i;
13633 : :
13634 [ # # # # ]: 0 : for (i = 0; i == 0 || actions[i - 1].type != RTE_FLOW_ACTION_TYPE_END; i++) {
13635 : 0 : const struct rte_flow_action *action = &actions[i];
13636 : 0 : struct rte_flow_action *mask = &masks[i];
13637 : 0 : union actions_conf *conf = &mask_conf[i];
13638 : :
13639 : 0 : mask->type = action->type;
13640 [ # # # # : 0 : switch (action->type) {
# # # ]
13641 : : case RTE_FLOW_ACTION_TYPE_INDIRECT:
13642 : 0 : mask->type = flow_nta_get_indirect_action_type(action);
13643 [ # # ]: 0 : if (!mask->type)
13644 : : return -EINVAL;
13645 : : break;
13646 : 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
13647 : 0 : flow_nta_set_mh_mask_conf(action->conf, (void *)conf);
13648 : 0 : mask->conf = conf;
13649 : 0 : break;
13650 : : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
13651 : : /* This mask will set this action as shared. */
13652 : : memset(conf, 0xff, sizeof(struct rte_flow_action_raw_encap));
13653 : 0 : mask->conf = conf;
13654 : 0 : break;
13655 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
13656 : : /* This mask will set this action as shared. */
13657 : 0 : conf->vxlan_encap.definition =
13658 : : ((const struct rte_flow_action_vxlan_encap *)
13659 : 0 : action->conf)->definition;
13660 : 0 : mask->conf = conf;
13661 : 0 : break;
13662 : 0 : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
13663 : : /* This mask will set this action as shared. */
13664 : 0 : conf->nvgre_encap.definition =
13665 : : ((const struct rte_flow_action_nvgre_encap *)
13666 : 0 : action->conf)->definition;
13667 : 0 : mask->conf = conf;
13668 : 0 : break;
13669 : : case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
13670 : : memset(conf, 0xff, sizeof(struct rte_flow_action_of_set_vlan_vid));
13671 : 0 : mask->conf = conf;
13672 : 0 : break;
13673 : : default:
13674 : : break;
13675 : : }
13676 : : }
13677 : : return 0;
13678 : : #undef NTA_CHECK_CONF_BUF_SIZE
13679 : : }
13680 : :
13681 : : static int
13682 : 0 : flow_hw_translate_flow_actions(struct rte_eth_dev *dev,
13683 : : const struct rte_flow_attr *attr,
13684 : : const struct rte_flow_action actions[],
13685 : : struct rte_flow_hw *flow,
13686 : : struct mlx5_flow_hw_action_params *ap,
13687 : : struct mlx5_hw_actions *hw_acts,
13688 : : uint64_t item_flags, uint64_t action_flags,
13689 : : bool external,
13690 : : struct rte_flow_error *error)
13691 : : {
13692 : : int ret = 0;
13693 : 0 : uint32_t src_group = 0;
13694 : : enum mlx5dr_table_type table_type;
13695 : : struct mlx5_flow_group grp;
13696 : : struct rte_flow_actions_template *at = NULL;
13697 : 0 : struct rte_flow_actions_template_attr template_attr = {
13698 : 0 : .egress = attr->egress,
13699 : 0 : .ingress = attr->ingress,
13700 : 0 : .transfer = attr->transfer,
13701 : : };
13702 : : struct rte_flow_action masks[MLX5_HW_MAX_ACTS];
13703 : : union actions_conf mask_conf[MLX5_HW_MAX_ACTS];
13704 : :
13705 : : RTE_SET_USED(action_flags);
13706 : : memset(masks, 0, sizeof(masks));
13707 : : memset(mask_conf, 0, sizeof(mask_conf));
13708 : : /* Only set the needed fields explicitly. */
13709 : 0 : struct mlx5_flow_workspace *wks = mlx5_flow_push_thread_workspace();
13710 : : struct rte_flow_template_table *table;
13711 : :
13712 : : /*
13713 : : * Notice All direct actions will be unmasked,
13714 : : * except for modify header and encap,
13715 : : * and therefore will be parsed as part of action construct.
13716 : : * Modify header is always shared in HWS,
13717 : : * encap is masked such that it will be treated as shared.
13718 : : * shared actions will be parsed as part of template translation
13719 : : * and not during action construct.
13720 : : */
13721 [ # # ]: 0 : if (!wks)
13722 : 0 : return rte_flow_error_set(error, ENOMEM,
13723 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13724 : : NULL,
13725 : : "failed to push flow workspace");
13726 : 0 : table = wks->table;
13727 : 0 : flow_nta_build_template_mask(actions, masks, mask_conf);
13728 : : /* The group in the attribute translation was done in advance. */
13729 : 0 : ret = __translate_group(dev, attr, external, attr->group, &src_group, error);
13730 [ # # ]: 0 : if (ret)
13731 : : return ret;
13732 [ # # ]: 0 : if (attr->transfer)
13733 : : table_type = MLX5DR_TABLE_TYPE_FDB;
13734 [ # # ]: 0 : else if (attr->egress)
13735 : : table_type = MLX5DR_TABLE_TYPE_NIC_TX;
13736 : : else
13737 : : table_type = MLX5DR_TABLE_TYPE_NIC_RX;
13738 : 0 : at = __flow_hw_actions_template_create(dev, &template_attr, actions, masks, true, error);
13739 [ # # ]: 0 : if (!at) {
13740 : 0 : ret = -rte_errno;
13741 : 0 : goto end;
13742 : : }
13743 : 0 : grp.group_id = src_group;
13744 : 0 : table->grp = &grp;
13745 : 0 : table->type = table_type;
13746 : 0 : table->cfg.external = external;
13747 : 0 : table->nb_action_templates = 1;
13748 : 0 : memcpy(&table->cfg.attr.flow_attr, attr, sizeof(*attr));
13749 : 0 : table->cfg.attr.flow_attr.group = src_group;
13750 : 0 : table->ats[0].action_template = at;
13751 : 0 : ret = __flow_hw_translate_actions_template(dev, &table->cfg, hw_acts, at,
13752 : : &table->mpctx, true, error);
13753 [ # # ]: 0 : if (ret)
13754 : 0 : goto end;
13755 : : /* handle bulk actions register. */
13756 : 0 : ret = flow_hw_encap_decap_resource_register(dev, table, hw_acts, flow, error);
13757 [ # # ]: 0 : if (ret)
13758 : 0 : goto end;
13759 : 0 : ret = flow_hw_modify_hdr_resource_register(dev, table, hw_acts, flow, error);
13760 [ # # ]: 0 : if (ret)
13761 : 0 : goto end;
13762 : 0 : table->ats[0].acts = *hw_acts;
13763 : 0 : ret = flow_hw_actions_construct(dev, flow, ap,
13764 : : &table->ats[0], item_flags, table,
13765 [ # # ]: 0 : actions, hw_acts->rule_acts, 0, error);
13766 [ # # ]: 0 : if (ret)
13767 : 0 : goto end;
13768 : 0 : goto end;
13769 : 0 : end:
13770 [ # # ]: 0 : if (ret)
13771 : : /* Make sure that there is no garbage in the actions. */
13772 : 0 : __flow_hw_action_template_destroy(dev, hw_acts);
13773 : : else
13774 : 0 : __flow_hw_act_data_flush(dev, hw_acts);
13775 [ # # ]: 0 : if (at)
13776 : 0 : mlx5_free(at);
13777 : 0 : mlx5_flow_pop_thread_workspace();
13778 : 0 : return ret;
13779 : : }
13780 : :
13781 : : static int
13782 : 0 : flow_hw_unregister_matcher(struct rte_eth_dev *dev,
13783 : : struct mlx5_flow_dv_matcher *matcher)
13784 : : {
13785 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13786 : 0 : struct mlx5_flow_group *group = matcher->group;
13787 : : int ret = 0;
13788 : :
13789 [ # # ]: 0 : if (group) {
13790 [ # # ]: 0 : if (matcher->matcher_object)
13791 : 0 : ret |= mlx5_list_unregister(group->matchers, &matcher->entry);
13792 : 0 : ret |= mlx5_hlist_unregister(priv->sh->groups, &group->entry);
13793 : : }
13794 : 0 : return ret;
13795 : : }
13796 : :
13797 : 0 : static int flow_hw_register_matcher(struct rte_eth_dev *dev,
13798 : : const struct rte_flow_attr *attr,
13799 : : const struct rte_flow_item items[],
13800 : : bool external,
13801 : : struct rte_flow_hw *flow,
13802 : : struct mlx5_flow_dv_matcher *matcher,
13803 : : struct rte_flow_error *error)
13804 : : {
13805 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13806 : 0 : struct rte_flow_error sub_error = {
13807 : : .type = RTE_FLOW_ERROR_TYPE_NONE,
13808 : : .cause = NULL,
13809 : : .message = NULL,
13810 : : };
13811 : 0 : struct rte_flow_attr flow_attr = *attr;
13812 : 0 : uint32_t specialize = 0; /* No unified FDB. */
13813 : 0 : struct mlx5_flow_cb_ctx ctx = {
13814 : : .dev = dev,
13815 : : .error = &sub_error,
13816 : : .data = &flow_attr,
13817 : : .data2 = &specialize,
13818 : : };
13819 : : void *items_ptr = &items;
13820 : 0 : struct mlx5_flow_cb_ctx matcher_ctx = {
13821 : : .error = &sub_error,
13822 : : .data = matcher,
13823 : : .data2 = items_ptr,
13824 : : };
13825 : : struct mlx5_list_entry *group_entry = NULL;
13826 : : struct mlx5_list_entry *matcher_entry = NULL;
13827 : : struct mlx5_flow_dv_matcher *resource;
13828 : : struct mlx5_list *matchers_list;
13829 : : struct mlx5_flow_group *flow_group;
13830 : : int ret;
13831 : :
13832 : :
13833 : 0 : matcher->crc = rte_raw_cksum((const void *)matcher->mask.buf,
13834 : : matcher->mask.size);
13835 : 0 : matcher->priority = attr->priority;
13836 : 0 : ret = __translate_group(dev, attr, external, attr->group, &flow_attr.group, error);
13837 [ # # ]: 0 : if (ret)
13838 : : return ret;
13839 : :
13840 : : /* Register the flow group. */
13841 : 0 : group_entry = mlx5_hlist_register(priv->sh->groups, flow_attr.group, &ctx);
13842 [ # # ]: 0 : if (!group_entry)
13843 : 0 : goto error;
13844 : : flow_group = container_of(group_entry, struct mlx5_flow_group, entry);
13845 : :
13846 : 0 : matchers_list = flow_group->matchers;
13847 : 0 : matcher->group = flow_group;
13848 : 0 : matcher_entry = mlx5_list_register(matchers_list, &matcher_ctx);
13849 [ # # ]: 0 : if (!matcher_entry)
13850 : 0 : goto error;
13851 : : resource = container_of(matcher_entry, typeof(*resource), entry);
13852 : 0 : flow->nt2hws->matcher = resource;
13853 : 0 : return 0;
13854 : :
13855 : 0 : error:
13856 [ # # ]: 0 : if (group_entry)
13857 : 0 : mlx5_hlist_unregister(priv->sh->groups, group_entry);
13858 [ # # ]: 0 : if (error) {
13859 [ # # ]: 0 : if (sub_error.type != RTE_FLOW_ERROR_TYPE_NONE)
13860 : : rte_memcpy(error, &sub_error, sizeof(sub_error));
13861 : : }
13862 : 0 : return rte_flow_error_set(error, rte_errno,
13863 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13864 : : NULL, "fail to register matcher");
13865 : : }
13866 : :
13867 : : static int
13868 : 0 : flow_hw_allocate_actions(struct rte_eth_dev *dev,
13869 : : uint64_t action_flags,
13870 : : struct rte_flow_error *error)
13871 : : {
13872 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13873 : : int ret;
13874 : : uint obj_num;
13875 : :
13876 : 0 : error->type = RTE_FLOW_ERROR_TYPE_NONE;
13877 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_AGE) {
13878 : : /* If no age objects were previously allocated. */
13879 [ # # ]: 0 : if (!priv->hws_age_req) {
13880 : : /* If no counters were previously allocated. */
13881 [ # # ]: 0 : if (!priv->hws_cpool) {
13882 : 0 : obj_num = MLX5_CNT_NT_MAX(priv);
13883 : 0 : ret = mlx5_hws_cnt_pool_create(dev, obj_num,
13884 : 0 : priv->nb_queue,
13885 : : NULL, error);
13886 [ # # ]: 0 : if (ret)
13887 : 0 : goto err;
13888 : : }
13889 : : /* Allocate same number of counters. */
13890 : 0 : ret = mlx5_hws_age_pool_init(dev, priv->hws_cpool->cfg.request_num,
13891 : 0 : priv->nb_queue, false);
13892 [ # # ]: 0 : if (ret)
13893 : 0 : goto err;
13894 : : }
13895 : : }
13896 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_COUNT) {
13897 : : /* If no counters were previously allocated. */
13898 [ # # ]: 0 : if (!priv->hws_cpool) {
13899 : 0 : obj_num = MLX5_CNT_NT_MAX(priv);
13900 : 0 : ret = mlx5_hws_cnt_pool_create(dev, obj_num,
13901 : 0 : priv->nb_queue, NULL,
13902 : : error);
13903 [ # # ]: 0 : if (ret)
13904 : 0 : goto err;
13905 : : }
13906 : : }
13907 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_CT) {
13908 : : /* If no CT were previously allocated. */
13909 [ # # ]: 0 : if (!priv->hws_ctpool) {
13910 : 0 : obj_num = MLX5_CT_NT_MAX(priv);
13911 : 0 : ret = mlx5_flow_ct_init(dev, obj_num, priv->nb_queue);
13912 [ # # ]: 0 : if (ret)
13913 : 0 : goto err;
13914 : : }
13915 : : }
13916 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_METER) {
13917 : : /* If no meters were previously allocated. */
13918 [ # # ]: 0 : if (!priv->hws_mpool) {
13919 : 0 : obj_num = MLX5_MTR_NT_MAX(priv);
13920 : 0 : ret = mlx5_flow_meter_init(dev, obj_num, 0, 0,
13921 : : priv->nb_queue);
13922 [ # # ]: 0 : if (ret)
13923 : 0 : goto err;
13924 : : }
13925 : : }
13926 : : return 0;
13927 : 0 : err:
13928 [ # # ]: 0 : if (ret && error->type != RTE_FLOW_ERROR_TYPE_NONE)
13929 : : return ret;
13930 : 0 : return rte_flow_error_set(error, ret,
13931 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13932 : : NULL, "fail to allocate actions");
13933 : : }
13934 : :
13935 : 0 : static int flow_hw_apply(const struct rte_flow_item items[],
13936 : : struct mlx5dr_rule_action rule_actions[],
13937 : : struct rte_flow_hw *flow,
13938 : : struct rte_flow_error *error)
13939 : : {
13940 : : struct mlx5dr_bwc_rule *rule = NULL;
13941 : :
13942 : 0 : rule = mlx5dr_bwc_rule_create((struct mlx5dr_bwc_matcher *)
13943 : 0 : flow->nt2hws->matcher->matcher_object,
13944 : : items, rule_actions);
13945 : 0 : flow->nt2hws->nt_rule = rule;
13946 [ # # ]: 0 : if (!rule) {
13947 : 0 : return rte_flow_error_set(error, EINVAL,
13948 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13949 : : NULL, "fail to create rte flow");
13950 : : }
13951 : : return 0;
13952 : : }
13953 : :
13954 : : #ifdef HAVE_MLX5_HWS_SUPPORT
13955 : : /**
13956 : : * Create a flow.
13957 : : *
13958 : : * @param[in] dev
13959 : : * Pointer to Ethernet device.
13960 : : * @param[in] type
13961 : : * Flow type.
13962 : : * @param[in] attr
13963 : : * Flow rule attributes.
13964 : : * @param[in] items
13965 : : * Pattern specification (list terminated by the END pattern item).
13966 : : * @param[in] actions
13967 : : * Associated actions (list terminated by the END action).
13968 : : * @param[in] external
13969 : : * This flow rule is created by request external to PMD.
13970 : : * @param[out] flow
13971 : : * Flow pointer
13972 : : * @param[out] error
13973 : : * Perform verbose error reporting if not NULL.
13974 : : *
13975 : : * @return
13976 : : * 0 on success, negative errno value otherwise and rte_errno set.
13977 : : */
13978 : : int
13979 : 0 : flow_hw_create_flow(struct rte_eth_dev *dev, enum mlx5_flow_type type,
13980 : : const struct rte_flow_attr *attr,
13981 : : const struct rte_flow_item items[],
13982 : : const struct rte_flow_action actions[],
13983 : : uint64_t item_flags, uint64_t action_flags, bool external,
13984 : : struct rte_flow_hw **flow, struct rte_flow_error *error)
13985 : : {
13986 : : int ret;
13987 : 0 : struct mlx5_hw_actions hw_act = { { NULL } };
13988 : : struct mlx5_flow_hw_action_params ap;
13989 : 0 : struct mlx5_flow_dv_matcher matcher = {
13990 : : .mask = {
13991 : : .size = sizeof(matcher.mask.buf),
13992 : : },
13993 : : };
13994 : : uint32_t tbl_type;
13995 : :
13996 : 0 : struct mlx5_flow_attr flow_attr = {
13997 : 0 : .port_id = dev->data->port_id,
13998 : 0 : .group = attr->group,
13999 : 0 : .priority = attr->priority,
14000 : : .rss_level = 0,
14001 : : .act_flags = action_flags,
14002 : : .tbl_type = 0,
14003 : : };
14004 : :
14005 [ # # ]: 0 : if (attr->transfer)
14006 : : tbl_type = MLX5DR_TABLE_TYPE_FDB;
14007 [ # # ]: 0 : else if (attr->egress)
14008 : : tbl_type = MLX5DR_TABLE_TYPE_NIC_TX;
14009 : : else
14010 : : tbl_type = MLX5DR_TABLE_TYPE_NIC_RX;
14011 : 0 : flow_attr.tbl_type = tbl_type;
14012 : :
14013 : : /* Allocate needed memory. */
14014 : 0 : ret = flow_hw_prepare(dev, actions, type, flow, error);
14015 [ # # ]: 0 : if (ret)
14016 : 0 : goto error;
14017 : :
14018 : : /* TODO TBD flow_hw_handle_tunnel_offload(). */
14019 : 0 : (*flow)->nt_rule = true;
14020 : 0 : (*flow)->nt2hws->matcher = &matcher;
14021 : 0 : ret = __flow_dv_translate_items_hws(items, &flow_attr, &matcher.mask.buf,
14022 : : MLX5_SET_MATCHER_HS_M, NULL,
14023 : : NULL, true, error);
14024 : :
14025 [ # # ]: 0 : if (ret)
14026 : 0 : goto error;
14027 : :
14028 [ # # # # ]: 0 : if (item_flags & MLX5_FLOW_LAYER_ECPRI && !mlx5_flex_parser_ecpri_exist(dev))
14029 [ # # ]: 0 : if (mlx5_flex_parser_ecpri_alloc(dev)) {
14030 : 0 : rte_flow_error_set(error, EIO,
14031 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14032 : : NULL,
14033 : : "failed to create Flex parser "
14034 : : "profile for ECPRI");
14035 : 0 : goto error;
14036 : : }
14037 : 0 : ret = flow_hw_register_matcher(dev, attr, items, external, *flow, &matcher, error);
14038 [ # # ]: 0 : if (ret) {
14039 [ # # ]: 0 : if (rte_errno == E2BIG)
14040 : 0 : rte_flow_error_set(error, E2BIG, RTE_FLOW_ERROR_TYPE_ITEM, NULL,
14041 : : "flow pattern is too big");
14042 : 0 : goto error;
14043 : : }
14044 : :
14045 : : /*
14046 : : * ASO allocation – iterating on actions list to allocate missing resources.
14047 : : * In the future when validate function in hws will be added,
14048 : : * The output actions bit mask instead of
14049 : : * looping on the actions array twice.
14050 : : */
14051 : 0 : ret = flow_hw_allocate_actions(dev, action_flags, error);
14052 [ # # ]: 0 : if (ret)
14053 : 0 : goto error;
14054 : :
14055 : : /* Note: the actions should be saved in the sub-flow rule itself for reference. */
14056 : 0 : ret = flow_hw_translate_flow_actions(dev, attr, actions, *flow, &ap, &hw_act,
14057 : : item_flags, action_flags, external, error);
14058 [ # # ]: 0 : if (ret)
14059 : 0 : goto error;
14060 : :
14061 : : /*
14062 : : * If the flow is external (from application) OR device is started,
14063 : : * OR mreg discover, then apply immediately.
14064 : : */
14065 [ # # # # ]: 0 : if (external || dev->data->dev_started ||
14066 [ # # ]: 0 : (attr->group == MLX5_FLOW_MREG_CP_TABLE_GROUP &&
14067 [ # # ]: 0 : attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR)) {
14068 : 0 : ret = flow_hw_apply(items, hw_act.rule_acts, *flow, error);
14069 [ # # ]: 0 : if (ret)
14070 : 0 : goto error;
14071 : : }
14072 : : ret = 0;
14073 : 0 : error:
14074 : : /*
14075 : : * Release memory allocated.
14076 : : * Cannot use __flow_hw_actions_release(dev, &hw_act);
14077 : : * since it destroys the actions as well.
14078 : : */
14079 [ # # ]: 0 : if (hw_act.encap_decap)
14080 : 0 : mlx5_free(hw_act.encap_decap);
14081 [ # # ]: 0 : if (hw_act.push_remove)
14082 : 0 : mlx5_free(hw_act.push_remove);
14083 [ # # ]: 0 : if (hw_act.mhdr)
14084 : 0 : mlx5_free(hw_act.mhdr);
14085 [ # # ]: 0 : if (ret) {
14086 : : /* release after actual error */
14087 [ # # # # ]: 0 : if ((*flow)->nt2hws && (*flow)->nt2hws->matcher)
14088 : 0 : flow_hw_unregister_matcher(dev, (*flow)->nt2hws->matcher);
14089 : : }
14090 : 0 : return ret;
14091 : : }
14092 : : #endif
14093 : :
14094 : : void
14095 : 0 : flow_hw_destroy(struct rte_eth_dev *dev, struct rte_flow_hw *flow)
14096 : : {
14097 : : int ret;
14098 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14099 : :
14100 [ # # # # ]: 0 : if (!flow || !flow->nt2hws)
14101 : : return;
14102 : :
14103 [ # # ]: 0 : if (flow->nt2hws->nt_rule) {
14104 : 0 : ret = mlx5dr_bwc_rule_destroy(flow->nt2hws->nt_rule);
14105 [ # # ]: 0 : if (ret)
14106 : 0 : DRV_LOG(ERR, "bwc rule destroy failed");
14107 : : }
14108 [ # # ]: 0 : flow->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_DESTROY;
14109 : : /* Notice this function does not handle shared/static actions. */
14110 : : hw_cmpl_flow_update_or_destroy(dev, flow, 0, NULL);
14111 : :
14112 : : /**
14113 : : * TODO: TBD - Release tunnel related memory allocations(mlx5_flow_tunnel_free)
14114 : : * – needed only if supporting tunnel offloads, notice update RX queue flags in SWS.
14115 : : */
14116 : :
14117 : : /**
14118 : : * Notice matcher destroy will take place when matcher's list is destroyed
14119 : : * , same as for DV.
14120 : : */
14121 [ # # ]: 0 : if (flow->nt2hws->flow_aux)
14122 : 0 : mlx5_free(flow->nt2hws->flow_aux);
14123 : :
14124 [ # # ]: 0 : if (flow->nt2hws->rix_encap_decap)
14125 : 0 : flow_encap_decap_resource_release(dev, flow->nt2hws->rix_encap_decap);
14126 [ # # ]: 0 : if (flow->nt2hws->modify_hdr) {
14127 : : MLX5_ASSERT(flow->nt2hws->modify_hdr->action);
14128 : 0 : mlx5_hlist_unregister(priv->sh->modify_cmds,
14129 : : &flow->nt2hws->modify_hdr->entry);
14130 : : }
14131 [ # # ]: 0 : if (flow->nt2hws->matcher)
14132 : 0 : flow_hw_unregister_matcher(dev, flow->nt2hws->matcher);
14133 [ # # ]: 0 : if (flow->nt2hws->sample_release_ctx != NULL) {
14134 : 0 : mlx5_nta_sample_mirror_entry_release(dev, flow->nt2hws->sample_release_ctx);
14135 : 0 : flow->nt2hws->sample_release_ctx = NULL;
14136 : : }
14137 : : }
14138 : :
14139 : : #ifdef HAVE_MLX5_HWS_SUPPORT
14140 : : /**
14141 : : * Destroy a flow.
14142 : : *
14143 : : * @param[in] dev
14144 : : * Pointer to Ethernet device.
14145 : : * @param[in] type
14146 : : * Flow type.
14147 : : * @param[in] flow_addr
14148 : : * Address of flow to destroy.
14149 : : */
14150 : : void
14151 : 0 : flow_hw_list_destroy(struct rte_eth_dev *dev, enum mlx5_flow_type type,
14152 : : uintptr_t flow_addr)
14153 : : {
14154 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14155 : 0 : struct rte_flow_hw *flow = (struct rte_flow_hw *)flow_addr;
14156 : : struct mlx5_nta_rss_flow_head head = { .slh_first = flow };
14157 : :
14158 [ # # # # : 0 : if (!flow || !flow->nt2hws || flow->nt2hws->chaned_flow)
# # ]
14159 : : return;
14160 : 0 : mlx5_flow_nta_del_copy_action(dev, flow->nt2hws->rix_mreg_copy);
14161 [ # # ]: 0 : while (!SLIST_EMPTY(&head)) {
14162 : : flow = SLIST_FIRST(&head);
14163 : 0 : SLIST_REMOVE_HEAD(&head, nt2hws->next);
14164 : 0 : flow_hw_destroy(dev, flow);
14165 : : /* Release flow memory by idx */
14166 : 0 : mlx5_ipool_free(priv->flows[type], flow->idx);
14167 : : }
14168 : : }
14169 : : #endif
14170 : :
14171 : : /**
14172 : : * Create a flow.
14173 : : *
14174 : : * @param[in] dev
14175 : : * Pointer to Ethernet device.
14176 : : * @param[in] type
14177 : : * Flow type.
14178 : : * @param[in] attr
14179 : : * Flow rule attributes.
14180 : : * @param[in] items
14181 : : * Pattern specification (list terminated by the END pattern item).
14182 : : * @param[in] actions
14183 : : * Associated actions (list terminated by the END action).
14184 : : * @param[in] external
14185 : : * This flow rule is created by request external to PMD.
14186 : : * @param[out] error
14187 : : * Perform verbose error reporting if not NULL.
14188 : : *
14189 : : * @return
14190 : : * A flow addr on success, 0 otherwise and rte_errno is set.
14191 : : */
14192 : 0 : static uintptr_t flow_hw_list_create(struct rte_eth_dev *dev,
14193 : : enum mlx5_flow_type type,
14194 : : const struct rte_flow_attr *attr,
14195 : : const struct rte_flow_item items[],
14196 : : const struct rte_flow_action actions[],
14197 : : bool external,
14198 : : struct rte_flow_error *error)
14199 : : {
14200 : : int ret;
14201 : : int split;
14202 : : int encap_idx;
14203 : 0 : uint32_t cpy_idx = 0;
14204 : 0 : int actions_n = 0;
14205 : 0 : struct rte_flow_hw *flow = NULL;
14206 : 0 : struct rte_flow_hw *prfx_flow = NULL;
14207 : 0 : const struct rte_flow_action *qrss = NULL;
14208 : 0 : const struct rte_flow_action *mark = NULL;
14209 : 0 : uint64_t item_flags = 0;
14210 : 0 : uint64_t action_flags = mlx5_flow_hw_action_flags_get(actions, &qrss, &mark,
14211 : : &encap_idx, &actions_n, error);
14212 : 0 : struct mlx5_flow_hw_split_resource resource = {
14213 : : .suffix = {
14214 : : .attr = attr,
14215 : : .items = items,
14216 : : .actions = actions,
14217 : : },
14218 : : };
14219 : 0 : struct rte_flow_error shadow_error = {0, };
14220 : 0 : const struct rte_flow_pattern_template_attr pattern_template_attr = {
14221 : : .relaxed_matching = 0,
14222 : 0 : .ingress = attr->ingress,
14223 : 0 : .egress = attr->egress,
14224 : 0 : .transfer = attr->transfer,
14225 : : };
14226 : :
14227 : : /* Validate application items only */
14228 : 0 : ret = __flow_hw_pattern_validate(dev, &pattern_template_attr, items,
14229 : : &item_flags, true, error);
14230 [ # # ]: 0 : if (ret < 0)
14231 : : return 0;
14232 : :
14233 : : RTE_SET_USED(encap_idx);
14234 [ # # ]: 0 : if (!error)
14235 : : error = &shadow_error;
14236 : 0 : split = mlx5_flow_nta_split_metadata(dev, attr, actions, qrss, action_flags,
14237 : : actions_n, external, &resource, error);
14238 [ # # ]: 0 : if (split < 0)
14239 : 0 : return split;
14240 : :
14241 : : /* Update the metadata copy table - MLX5_FLOW_MREG_CP_TABLE_GROUP */
14242 [ # # # # : 0 : if (((attr->ingress && attr->group != MLX5_FLOW_MREG_CP_TABLE_GROUP) ||
# # ]
14243 [ # # ]: 0 : attr->transfer) && external) {
14244 : 0 : ret = mlx5_flow_nta_update_copy_table(dev, &cpy_idx, mark,
14245 : : action_flags, error);
14246 [ # # ]: 0 : if (ret)
14247 : 0 : goto free;
14248 : : }
14249 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
14250 : 0 : flow = mlx5_nta_sample_flow_list_create(dev, type, attr, items, actions,
14251 : : item_flags, action_flags, error);
14252 [ # # ]: 0 : if (flow != NULL)
14253 : 0 : return (uintptr_t)flow;
14254 : 0 : goto free;
14255 : : }
14256 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_RSS) {
14257 : : const struct rte_flow_action_rss
14258 : 0 : *rss_conf = flow_nta_locate_rss(dev, actions, error);
14259 : 0 : flow = flow_nta_handle_rss(dev, attr, items, actions, rss_conf,
14260 : : item_flags, action_flags, external,
14261 : : type, error);
14262 [ # # ]: 0 : if (flow) {
14263 : 0 : flow->nt2hws->rix_mreg_copy = cpy_idx;
14264 : 0 : cpy_idx = 0;
14265 [ # # ]: 0 : if (!split)
14266 : 0 : return (uintptr_t)flow;
14267 : 0 : goto prefix_flow;
14268 : : }
14269 : 0 : goto free;
14270 : : }
14271 : : /* Create single flow. */
14272 : 0 : ret = flow_hw_create_flow(dev, type, resource.suffix.attr, resource.suffix.items,
14273 : : resource.suffix.actions, item_flags, action_flags,
14274 : : external, &flow, error);
14275 [ # # ]: 0 : if (ret)
14276 : 0 : goto free;
14277 [ # # ]: 0 : if (flow) {
14278 : 0 : flow->nt2hws->rix_mreg_copy = cpy_idx;
14279 : 0 : cpy_idx = 0;
14280 [ # # ]: 0 : if (!split)
14281 : 0 : return (uintptr_t)flow;
14282 : : /* Fall Through to prefix flow creation. */
14283 : : }
14284 : 0 : prefix_flow:
14285 : 0 : ret = flow_hw_create_flow(dev, type, attr, items, resource.prefix.actions,
14286 : : item_flags, action_flags, external, &prfx_flow, error);
14287 [ # # ]: 0 : if (ret)
14288 : 0 : goto free;
14289 [ # # ]: 0 : if (prfx_flow) {
14290 : 0 : prfx_flow->nt2hws->rix_mreg_copy = flow->nt2hws->rix_mreg_copy;
14291 : 0 : flow->nt2hws->chaned_flow = 1;
14292 : 0 : SLIST_INSERT_AFTER(prfx_flow, flow, nt2hws->next);
14293 : 0 : mlx5_flow_nta_split_resource_free(dev, &resource);
14294 : 0 : return (uintptr_t)prfx_flow;
14295 : : }
14296 : 0 : free:
14297 [ # # ]: 0 : if (prfx_flow)
14298 : 0 : flow_hw_list_destroy(dev, type, (uintptr_t)prfx_flow);
14299 [ # # ]: 0 : if (flow)
14300 : 0 : flow_hw_list_destroy(dev, type, (uintptr_t)flow);
14301 [ # # ]: 0 : if (cpy_idx)
14302 : 0 : mlx5_flow_nta_del_copy_action(dev, cpy_idx);
14303 [ # # ]: 0 : if (split > 0)
14304 : 0 : mlx5_flow_nta_split_resource_free(dev, &resource);
14305 : : return 0;
14306 : : }
14307 : :
14308 : : static void
14309 : 0 : mlx5_mirror_destroy_clone(struct rte_eth_dev *dev,
14310 : : struct mlx5_mirror_clone *clone)
14311 : : {
14312 [ # # # ]: 0 : switch (clone->type) {
14313 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
14314 : : case RTE_FLOW_ACTION_TYPE_QUEUE:
14315 : 0 : mlx5_hrxq_release(dev,
14316 : 0 : ((struct mlx5_hrxq *)(clone->action_ctx))->idx);
14317 : 0 : break;
14318 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP:
14319 : 0 : flow_hw_jump_release(dev, clone->action_ctx);
14320 : : break;
14321 : : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
14322 : : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
14323 : : case RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:
14324 : : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
14325 : : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
14326 : : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
14327 : : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
14328 : : default:
14329 : : break;
14330 : : }
14331 : 0 : }
14332 : :
14333 : : void
14334 [ # # ]: 0 : mlx5_hw_mirror_destroy(struct rte_eth_dev *dev, struct mlx5_mirror *mirror)
14335 : : {
14336 : : uint32_t i;
14337 : :
14338 : : mlx5_indirect_list_remove_entry(&mirror->indirect);
14339 [ # # ]: 0 : for (i = 0; i < mirror->clones_num; i++)
14340 : 0 : mlx5_mirror_destroy_clone(dev, &mirror->clone[i]);
14341 [ # # ]: 0 : if (mirror->mirror_action)
14342 : 0 : mlx5dr_action_destroy(mirror->mirror_action);
14343 : 0 : mlx5_free(mirror);
14344 : 0 : }
14345 : :
14346 : : static __rte_always_inline bool
14347 : : mlx5_mirror_terminal_action(const struct rte_flow_action *action)
14348 : : {
14349 : 0 : switch (action->type) {
14350 : : case RTE_FLOW_ACTION_TYPE_JUMP:
14351 : : case RTE_FLOW_ACTION_TYPE_RSS:
14352 : : case RTE_FLOW_ACTION_TYPE_QUEUE:
14353 : : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
14354 : : case RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:
14355 : : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
14356 : : case RTE_FLOW_ACTION_TYPE_DROP:
14357 : : return true;
14358 : : default:
14359 : : break;
14360 : : }
14361 : : return false;
14362 : : }
14363 : :
14364 : : static bool
14365 : 0 : mlx5_mirror_validate_sample_action(struct rte_eth_dev *dev,
14366 : : const struct rte_flow_attr *flow_attr,
14367 : : const struct rte_flow_action *action)
14368 : : {
14369 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14370 : : const struct rte_flow_action_ethdev *port = NULL;
14371 [ # # # # ]: 0 : bool is_proxy = MLX5_HW_PORT_IS_PROXY(priv);
14372 : :
14373 [ # # ]: 0 : if (!action)
14374 : : return false;
14375 [ # # # # : 0 : switch (action->type) {
# ]
14376 : 0 : case RTE_FLOW_ACTION_TYPE_QUEUE:
14377 : : case RTE_FLOW_ACTION_TYPE_RSS:
14378 [ # # ]: 0 : if (flow_attr->transfer)
14379 : : return false;
14380 : : break;
14381 : 0 : case RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:
14382 [ # # # # ]: 0 : if (!is_proxy || !flow_attr->transfer)
14383 : : return false;
14384 : 0 : port = action->conf;
14385 [ # # # # ]: 0 : if (!port || port->port_id != MLX5_REPRESENTED_PORT_ESW_MGR)
14386 : : return false;
14387 : : break;
14388 : 0 : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
14389 : : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
14390 : : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
14391 : : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
14392 : : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
14393 [ # # # # ]: 0 : if (!is_proxy || !flow_attr->transfer)
14394 : : return false;
14395 [ # # ]: 0 : if (action[0].type == RTE_FLOW_ACTION_TYPE_RAW_DECAP &&
14396 [ # # ]: 0 : action[1].type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP)
14397 : : return false;
14398 : : break;
14399 : : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
14400 : : case RTE_FLOW_ACTION_TYPE_JUMP:
14401 : : case RTE_FLOW_ACTION_TYPE_DROP:
14402 : : break;
14403 : : default:
14404 : : return false;
14405 : : }
14406 : 0 : return true;
14407 : : }
14408 : :
14409 : : /**
14410 : : * Valid mirror actions list includes one or two SAMPLE actions
14411 : : * followed by JUMP.
14412 : : *
14413 : : * @return
14414 : : * Number of mirrors *action* list was valid.
14415 : : * -EINVAL otherwise.
14416 : : */
14417 : : static int
14418 : 0 : mlx5_hw_mirror_actions_list_validate(struct rte_eth_dev *dev,
14419 : : const struct rte_flow_attr *flow_attr,
14420 : : const struct rte_flow_action *actions)
14421 : : {
14422 [ # # ]: 0 : if (actions[0].type == RTE_FLOW_ACTION_TYPE_SAMPLE) {
14423 : : int i = 1;
14424 : : bool valid;
14425 : 0 : const struct rte_flow_action_sample *sample = actions[0].conf;
14426 : 0 : valid = mlx5_mirror_validate_sample_action(dev, flow_attr,
14427 : 0 : sample->actions);
14428 [ # # ]: 0 : if (!valid)
14429 : : return -EINVAL;
14430 [ # # ]: 0 : if (actions[1].type == RTE_FLOW_ACTION_TYPE_SAMPLE) {
14431 : : i = 2;
14432 : 0 : sample = actions[1].conf;
14433 : 0 : valid = mlx5_mirror_validate_sample_action(dev, flow_attr,
14434 : 0 : sample->actions);
14435 [ # # ]: 0 : if (!valid)
14436 : : return -EINVAL;
14437 : : }
14438 [ # # ]: 0 : return mlx5_mirror_terminal_action(actions + i) ? i + 1 : -EINVAL;
14439 : : }
14440 : : return -EINVAL;
14441 : : }
14442 : :
14443 : : static int
14444 : 0 : mirror_format_tir(struct rte_eth_dev *dev,
14445 : : struct mlx5_mirror_clone *clone,
14446 : : const struct mlx5_flow_template_table_cfg *table_cfg,
14447 : : const struct rte_flow_action *action,
14448 : : struct mlx5dr_action_dest_attr *dest_attr,
14449 : : struct rte_flow_error *error)
14450 : : {
14451 : : uint32_t hws_flags;
14452 : : enum mlx5dr_table_type table_type;
14453 : : struct mlx5_hrxq *tir_ctx;
14454 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14455 : : bool unified_fdb = is_unified_fdb(priv);
14456 : :
14457 : 0 : table_type = get_mlx5dr_table_type(&table_cfg->attr.flow_attr, table_cfg->attr.specialize,
14458 : : unified_fdb);
14459 : 0 : hws_flags = mlx5_hw_act_flag[MLX5_HW_ACTION_FLAG_NONE_ROOT][table_type];
14460 : 0 : tir_ctx = flow_hw_tir_action_register(dev, hws_flags, action);
14461 [ # # ]: 0 : if (!tir_ctx)
14462 : 0 : return rte_flow_error_set(error, EINVAL,
14463 : : RTE_FLOW_ERROR_TYPE_ACTION,
14464 : : action, "failed to create QUEUE action for mirror clone");
14465 : 0 : dest_attr->dest = tir_ctx->action;
14466 : 0 : clone->action_ctx = tir_ctx;
14467 : 0 : return 0;
14468 : : }
14469 : :
14470 : : static int
14471 : 0 : mirror_format_jump(struct rte_eth_dev *dev,
14472 : : struct mlx5_mirror_clone *clone,
14473 : : const struct mlx5_flow_template_table_cfg *table_cfg,
14474 : : const struct rte_flow_action *action,
14475 : : struct mlx5dr_action_dest_attr *dest_attr,
14476 : : struct rte_flow_error *error)
14477 : : {
14478 : 0 : const struct rte_flow_action_jump *jump_conf = action->conf;
14479 : 0 : struct mlx5_hw_jump_action *jump = flow_hw_jump_action_register
14480 : : (dev, table_cfg,
14481 : 0 : jump_conf->group, error);
14482 : :
14483 [ # # ]: 0 : if (!jump)
14484 : 0 : return rte_flow_error_set(error, EINVAL,
14485 : : RTE_FLOW_ERROR_TYPE_ACTION,
14486 : : action, "failed to create JUMP action for mirror clone");
14487 : 0 : dest_attr->dest = jump->hws_action;
14488 : 0 : clone->action_ctx = jump;
14489 : 0 : return 0;
14490 : : }
14491 : :
14492 : : static int
14493 : : mirror_format_port(struct rte_eth_dev *dev,
14494 : : const struct rte_flow_action *action,
14495 : : struct mlx5dr_action_dest_attr *dest_attr,
14496 : : struct rte_flow_error __rte_unused *error)
14497 : : {
14498 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14499 : 0 : const struct rte_flow_action_ethdev *port_action = action->conf;
14500 : :
14501 : 0 : dest_attr->dest = priv->hw_vport[port_action->port_id];
14502 : : return 0;
14503 : : }
14504 : :
14505 : : static int
14506 : 0 : hw_mirror_clone_reformat(const struct rte_flow_action *actions,
14507 : : struct mlx5dr_action_dest_attr *dest_attr,
14508 : : enum mlx5dr_action_type *action_type,
14509 : : uint8_t *reformat_buf, bool decap)
14510 : : {
14511 : : int ret;
14512 : : const struct rte_flow_item *encap_item = NULL;
14513 : : const struct rte_flow_action_raw_encap *encap_conf = NULL;
14514 : : typeof(dest_attr->reformat) *reformat = &dest_attr->reformat;
14515 : :
14516 [ # # # # ]: 0 : switch (actions[0].type) {
14517 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
14518 : 0 : encap_conf = actions[0].conf;
14519 : 0 : break;
14520 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
14521 : 0 : encap_item = MLX5_CONST_ENCAP_ITEM(rte_flow_action_vxlan_encap,
14522 : : actions);
14523 : 0 : break;
14524 : 0 : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
14525 : 0 : encap_item = MLX5_CONST_ENCAP_ITEM(rte_flow_action_nvgre_encap,
14526 : : actions);
14527 : 0 : break;
14528 : : default:
14529 : : return -EINVAL;
14530 : : }
14531 : 0 : *action_type = decap ?
14532 [ # # ]: 0 : MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3 :
14533 : : MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;
14534 [ # # ]: 0 : if (encap_item) {
14535 : 0 : ret = flow_dv_convert_encap_data(encap_item, reformat_buf,
14536 : : &reformat->reformat_data_sz, NULL);
14537 [ # # ]: 0 : if (ret)
14538 : : return -EINVAL;
14539 : 0 : reformat->reformat_data = reformat_buf;
14540 : : } else {
14541 : 0 : reformat->reformat_data = (void *)(uintptr_t)encap_conf->data;
14542 : 0 : reformat->reformat_data_sz = encap_conf->size;
14543 : : }
14544 : : return 0;
14545 : : }
14546 : :
14547 : : static int
14548 : 0 : hw_mirror_format_clone(struct rte_eth_dev *dev,
14549 : : struct mlx5_mirror_clone *clone,
14550 : : const struct mlx5_flow_template_table_cfg *table_cfg,
14551 : : const struct rte_flow_action *actions,
14552 : : struct mlx5dr_action_dest_attr *dest_attr,
14553 : : uint8_t *reformat_buf, struct rte_flow_error *error)
14554 : : {
14555 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14556 : : int ret;
14557 : : uint32_t i;
14558 : : bool decap_seen = false;
14559 : :
14560 [ # # ]: 0 : for (i = 0; actions[i].type != RTE_FLOW_ACTION_TYPE_END; i++) {
14561 : 0 : dest_attr->action_type[i] = mlx5_hw_dr_action_types[actions[i].type];
14562 [ # # # # : 0 : switch (actions[i].type) {
# # # # ]
14563 : 0 : case RTE_FLOW_ACTION_TYPE_QUEUE:
14564 : : case RTE_FLOW_ACTION_TYPE_RSS:
14565 : 0 : ret = mirror_format_tir(dev, clone, table_cfg,
14566 : : &actions[i], dest_attr, error);
14567 [ # # ]: 0 : if (ret)
14568 : 0 : return ret;
14569 : : break;
14570 : 0 : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
14571 : : ret = mirror_format_port(dev, &actions[i],
14572 : : dest_attr, error);
14573 : : if (ret)
14574 : : return ret;
14575 : : break;
14576 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP:
14577 : 0 : ret = mirror_format_jump(dev, clone, table_cfg,
14578 : : &actions[i], dest_attr, error);
14579 [ # # ]: 0 : if (ret)
14580 : 0 : return ret;
14581 : : break;
14582 : 0 : case RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:
14583 : 0 : dest_attr->dest = priv->hw_def_miss;
14584 : 0 : break;
14585 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
14586 : : decap_seen = true;
14587 : 0 : break;
14588 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
14589 : : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
14590 : : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
14591 : 0 : ret = hw_mirror_clone_reformat(&actions[i], dest_attr,
14592 : : &dest_attr->action_type[i],
14593 : : reformat_buf, decap_seen);
14594 [ # # ]: 0 : if (ret < 0)
14595 : 0 : return rte_flow_error_set(error, EINVAL,
14596 : : RTE_FLOW_ERROR_TYPE_ACTION,
14597 : : &actions[i],
14598 : : "failed to create reformat action");
14599 : : break;
14600 : : case RTE_FLOW_ACTION_TYPE_DROP:
14601 : : break;
14602 : 0 : default:
14603 : 0 : return rte_flow_error_set(error, EINVAL,
14604 : : RTE_FLOW_ERROR_TYPE_ACTION,
14605 : : &actions[i], "unsupported sample action");
14606 : : }
14607 : 0 : clone->type = actions->type;
14608 : : }
14609 : 0 : dest_attr->action_type[i] = MLX5DR_ACTION_TYP_LAST;
14610 : 0 : return 0;
14611 : : }
14612 : :
14613 : : struct mlx5_mirror *
14614 : 0 : mlx5_hw_create_mirror(struct rte_eth_dev *dev,
14615 : : const struct mlx5_flow_template_table_cfg *table_cfg,
14616 : : const struct rte_flow_action *actions,
14617 : : struct rte_flow_error *error)
14618 : : {
14619 : : uint32_t hws_flags;
14620 : : int ret = 0, i, clones_num;
14621 : : struct mlx5_mirror *mirror;
14622 : : enum mlx5dr_table_type table_type;
14623 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
14624 : : bool unified_fdb = is_unified_fdb(priv);
14625 [ # # ]: 0 : const struct rte_flow_attr *flow_attr = &table_cfg->attr.flow_attr;
14626 : : uint8_t reformat_buf[MLX5_MIRROR_MAX_CLONES_NUM][MLX5_ENCAP_MAX_LEN];
14627 : : struct mlx5dr_action_dest_attr mirror_attr[MLX5_MIRROR_MAX_CLONES_NUM + 1];
14628 : : enum mlx5dr_action_type array_action_types[MLX5_MIRROR_MAX_CLONES_NUM + 1]
14629 : : [MLX5_MIRROR_MAX_SAMPLE_ACTIONS_LEN + 1];
14630 : :
14631 : : memset(mirror_attr, 0, sizeof(mirror_attr));
14632 : : memset(array_action_types, 0, sizeof(array_action_types));
14633 : 0 : table_type = get_mlx5dr_table_type(flow_attr, table_cfg->attr.specialize, unified_fdb);
14634 : 0 : hws_flags = mlx5_hw_act_flag[MLX5_HW_ACTION_FLAG_NONE_ROOT][table_type];
14635 : 0 : clones_num = mlx5_hw_mirror_actions_list_validate(dev, flow_attr,
14636 : : actions);
14637 [ # # ]: 0 : if (clones_num < 0) {
14638 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14639 : : actions, "Invalid mirror list format");
14640 : 0 : return NULL;
14641 : : }
14642 : 0 : mirror = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mirror),
14643 : : 0, SOCKET_ID_ANY);
14644 [ # # ]: 0 : if (!mirror) {
14645 : 0 : rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_ACTION,
14646 : : actions, "Failed to allocate mirror context");
14647 : 0 : return NULL;
14648 : : }
14649 : :
14650 : 0 : mirror->indirect.type = MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR;
14651 : 0 : mirror->clones_num = clones_num;
14652 [ # # ]: 0 : for (i = 0; i < clones_num; i++) {
14653 : : const struct rte_flow_action *clone_actions;
14654 : :
14655 : 0 : mirror_attr[i].action_type = array_action_types[i];
14656 [ # # ]: 0 : if (actions[i].type == RTE_FLOW_ACTION_TYPE_SAMPLE) {
14657 : 0 : const struct rte_flow_action_sample *sample = actions[i].conf;
14658 : :
14659 : 0 : clone_actions = sample->actions;
14660 : : } else {
14661 : : clone_actions = &actions[i];
14662 : : }
14663 : 0 : ret = hw_mirror_format_clone(dev, &mirror->clone[i], table_cfg,
14664 : : clone_actions, &mirror_attr[i],
14665 : 0 : reformat_buf[i], error);
14666 : :
14667 [ # # ]: 0 : if (ret)
14668 : 0 : goto error;
14669 : : }
14670 : 0 : hws_flags |= MLX5DR_ACTION_FLAG_SHARED;
14671 : 0 : mirror->mirror_action = mlx5dr_action_create_dest_array(priv->dr_ctx,
14672 : : clones_num,
14673 : : mirror_attr,
14674 : : hws_flags);
14675 [ # # ]: 0 : if (!mirror->mirror_action) {
14676 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14677 : : actions, "Failed to create HWS mirror action");
14678 : 0 : goto error;
14679 : : }
14680 : : return mirror;
14681 : 0 : error:
14682 : 0 : mlx5_hw_mirror_destroy(dev, mirror);
14683 : 0 : return NULL;
14684 : : }
14685 : :
14686 : : static struct rte_flow_action_list_handle *
14687 : 0 : mlx5_hw_mirror_handle_create(struct rte_eth_dev *dev,
14688 : : const struct mlx5_flow_template_table_cfg *table_cfg,
14689 : : const struct rte_flow_action *actions,
14690 : : struct rte_flow_error *error)
14691 : : {
14692 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14693 : 0 : struct mlx5_mirror *mirror = mlx5_hw_create_mirror(dev, table_cfg, actions, error);
14694 : :
14695 [ # # ]: 0 : if (mirror)
14696 [ # # ]: 0 : mlx5_indirect_list_add_entry(&priv->indirect_list_head, &mirror->indirect);
14697 : 0 : return (struct rte_flow_action_list_handle *)mirror;
14698 : : }
14699 : :
14700 : : void
14701 : 0 : mlx5_destroy_legacy_indirect(__rte_unused struct rte_eth_dev *dev,
14702 : : struct mlx5_indirect_list *ptr)
14703 : : {
14704 : : struct mlx5_indlst_legacy *obj = (typeof(obj))ptr;
14705 : :
14706 : : switch (obj->legacy_type) {
14707 : : case RTE_FLOW_ACTION_TYPE_METER_MARK:
14708 : : break; /* ASO meters were released in mlx5_flow_meter_flush() */
14709 : : default:
14710 : : break;
14711 : : }
14712 : 0 : mlx5_free(obj);
14713 : 0 : }
14714 : :
14715 : : static struct rte_flow_action_list_handle *
14716 : 0 : mlx5_create_legacy_indlst(struct rte_eth_dev *dev, uint32_t queue,
14717 : : const struct rte_flow_op_attr *attr,
14718 : : const struct rte_flow_indir_action_conf *conf,
14719 : : const struct rte_flow_action *actions,
14720 : : void *user_data, struct rte_flow_error *error)
14721 : : {
14722 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14723 : 0 : struct mlx5_indlst_legacy *indlst_obj = mlx5_malloc(MLX5_MEM_ZERO,
14724 : : sizeof(*indlst_obj),
14725 : : 0, SOCKET_ID_ANY);
14726 : :
14727 [ # # ]: 0 : if (!indlst_obj)
14728 : : return NULL;
14729 : 0 : indlst_obj->handle = flow_hw_action_handle_create(dev, queue, attr, conf,
14730 : : actions, user_data,
14731 : : error);
14732 [ # # ]: 0 : if (!indlst_obj->handle) {
14733 : 0 : mlx5_free(indlst_obj);
14734 : 0 : return NULL;
14735 : : }
14736 : 0 : indlst_obj->legacy_type = actions[0].type;
14737 : 0 : indlst_obj->indirect.type = MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY;
14738 [ # # ]: 0 : mlx5_indirect_list_add_entry(&priv->indirect_list_head, &indlst_obj->indirect);
14739 : 0 : return (struct rte_flow_action_list_handle *)indlst_obj;
14740 : : }
14741 : :
14742 : : static __rte_always_inline enum mlx5_indirect_list_type
14743 : : flow_hw_inlist_type_get(const struct rte_flow_action *actions)
14744 : : {
14745 [ # # # # ]: 0 : switch (actions[0].type) {
14746 : : case RTE_FLOW_ACTION_TYPE_SAMPLE:
14747 : : return MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR;
14748 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
14749 : 0 : return actions[1].type == RTE_FLOW_ACTION_TYPE_END ?
14750 : 0 : MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY :
14751 : : MLX5_INDIRECT_ACTION_LIST_TYPE_ERR;
14752 : : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
14753 : : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
14754 : : return MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT;
14755 : : default:
14756 : : break;
14757 : : }
14758 : : return MLX5_INDIRECT_ACTION_LIST_TYPE_ERR;
14759 : : }
14760 : :
14761 : : static struct rte_flow_action_list_handle*
14762 : 0 : mlx5_hw_decap_encap_handle_create(struct rte_eth_dev *dev,
14763 : : const struct mlx5_flow_template_table_cfg *table_cfg,
14764 : : const struct rte_flow_action *actions,
14765 : : struct rte_flow_error *error)
14766 : : {
14767 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14768 : : const struct rte_flow_attr *flow_attr = &table_cfg->attr.flow_attr;
14769 : : const struct rte_flow_action *encap = NULL;
14770 : : const struct rte_flow_action *decap = NULL;
14771 : 0 : struct rte_flow_indir_action_conf indirect_conf = {
14772 : 0 : .ingress = flow_attr->ingress,
14773 : 0 : .egress = flow_attr->egress,
14774 : 0 : .transfer = flow_attr->transfer,
14775 : : };
14776 : : struct mlx5_hw_encap_decap_action *handle;
14777 : : uint64_t action_flags = 0;
14778 : :
14779 : : /*
14780 : : * Allow
14781 : : * 1. raw_decap / raw_encap / end
14782 : : * 2. raw_encap / end
14783 : : * 3. raw_decap / end
14784 : : */
14785 [ # # ]: 0 : while (actions->type != RTE_FLOW_ACTION_TYPE_END) {
14786 [ # # ]: 0 : if (actions->type == RTE_FLOW_ACTION_TYPE_RAW_DECAP) {
14787 [ # # ]: 0 : if (action_flags) {
14788 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14789 : : actions, "Invalid indirect action list sequence");
14790 : 0 : return NULL;
14791 : : }
14792 : : action_flags |= MLX5_FLOW_ACTION_DECAP;
14793 : : decap = actions;
14794 [ # # ]: 0 : } else if (actions->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
14795 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_ENCAP) {
14796 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14797 : : actions, "Invalid indirect action list sequence");
14798 : 0 : return NULL;
14799 : : }
14800 : 0 : action_flags |= MLX5_FLOW_ACTION_ENCAP;
14801 : : encap = actions;
14802 : : } else {
14803 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14804 : : actions, "Invalid indirect action type in list");
14805 : 0 : return NULL;
14806 : : }
14807 : 0 : actions++;
14808 : : }
14809 [ # # ]: 0 : if (!decap && !encap) {
14810 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14811 : : actions, "Invalid indirect action combinations");
14812 : 0 : return NULL;
14813 : : }
14814 : 0 : handle = mlx5_reformat_action_create(dev, &indirect_conf, encap, decap, error);
14815 [ # # ]: 0 : if (!handle) {
14816 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14817 : : actions, "Failed to create HWS decap_encap action");
14818 : 0 : return NULL;
14819 : : }
14820 : 0 : handle->indirect.type = MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT;
14821 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->indirect_list_head, &handle->indirect, entry);
14822 : 0 : return (struct rte_flow_action_list_handle *)handle;
14823 : : }
14824 : :
14825 : : static struct rte_flow_action_list_handle *
14826 [ # # ]: 0 : flow_hw_async_action_list_handle_create(struct rte_eth_dev *dev, uint32_t queue,
14827 : : const struct rte_flow_op_attr *attr,
14828 : : const struct rte_flow_indir_action_conf *conf,
14829 : : const struct rte_flow_action *actions,
14830 : : void *user_data,
14831 : : struct rte_flow_error *error)
14832 : : {
14833 : : struct mlx5_hw_q_job *job = NULL;
14834 : : bool push = flow_hw_action_push(attr);
14835 : : enum mlx5_indirect_list_type list_type;
14836 : : struct rte_flow_action_list_handle *handle;
14837 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14838 : 0 : struct mlx5_flow_template_table_cfg table_cfg = {
14839 : : .external = true,
14840 : : .attr = {
14841 : : .flow_attr = {
14842 : 0 : .ingress = conf->ingress,
14843 : 0 : .egress = conf->egress,
14844 : 0 : .transfer = conf->transfer
14845 : : }
14846 : : }
14847 : : };
14848 : :
14849 [ # # ]: 0 : if (!mlx5_hw_ctx_validate(dev, error))
14850 : : return NULL;
14851 [ # # ]: 0 : if (!actions) {
14852 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14853 : : NULL, "No action list");
14854 : 0 : return NULL;
14855 : : }
14856 : : list_type = flow_hw_inlist_type_get(actions);
14857 [ # # ]: 0 : if (list_type == MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY) {
14858 : : /*
14859 : : * Legacy indirect actions already have
14860 : : * async resources management. No need to do it twice.
14861 : : */
14862 : 0 : handle = mlx5_create_legacy_indlst(dev, queue, attr, conf,
14863 : : actions, user_data, error);
14864 : 0 : goto end;
14865 : : }
14866 [ # # ]: 0 : if (attr) {
14867 : : job = flow_hw_action_job_init(priv, queue, NULL, user_data,
14868 : : NULL, MLX5_HW_Q_JOB_TYPE_CREATE,
14869 : : MLX5_HW_INDIRECT_TYPE_LIST, error);
14870 : : if (!job)
14871 : 0 : return NULL;
14872 : : }
14873 [ # # # ]: 0 : switch (list_type) {
14874 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR:
14875 : : /*
14876 : : * Mirror action is only supported in HWS group. Setting group to
14877 : : * non-zero will ensure that the action resources are allocated correctly.
14878 : : */
14879 : 0 : table_cfg.attr.flow_attr.group = 1;
14880 : 0 : handle = mlx5_hw_mirror_handle_create(dev, &table_cfg,
14881 : : actions, error);
14882 : 0 : break;
14883 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT:
14884 : 0 : handle = mlx5_hw_decap_encap_handle_create(dev, &table_cfg,
14885 : : actions, error);
14886 : 0 : break;
14887 : 0 : default:
14888 : : handle = NULL;
14889 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14890 : : actions, "Invalid list");
14891 : : }
14892 [ # # ]: 0 : if (job) {
14893 : 0 : job->action = handle;
14894 [ # # ]: 0 : flow_hw_action_finalize(dev, queue, job, push, false,
14895 : : handle != NULL);
14896 : : }
14897 : 0 : end:
14898 : : return handle;
14899 : : }
14900 : :
14901 : : static struct rte_flow_action_list_handle *
14902 : 0 : flow_hw_action_list_handle_create(struct rte_eth_dev *dev,
14903 : : const struct rte_flow_indir_action_conf *conf,
14904 : : const struct rte_flow_action *actions,
14905 : : struct rte_flow_error *error)
14906 : : {
14907 : 0 : return flow_hw_async_action_list_handle_create(dev, MLX5_HW_INV_QUEUE,
14908 : : NULL, conf, actions,
14909 : : NULL, error);
14910 : : }
14911 : :
14912 : : static int
14913 [ # # ]: 0 : flow_hw_async_action_list_handle_destroy
14914 : : (struct rte_eth_dev *dev, uint32_t queue,
14915 : : const struct rte_flow_op_attr *attr,
14916 : : struct rte_flow_action_list_handle *handle,
14917 : : void *user_data, struct rte_flow_error *error)
14918 : : {
14919 : : int ret = 0;
14920 : : struct mlx5_hw_q_job *job = NULL;
14921 : : bool push = flow_hw_action_push(attr);
14922 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
14923 : : enum mlx5_indirect_list_type type =
14924 : : mlx5_get_indirect_list_type((void *)handle);
14925 : :
14926 [ # # ]: 0 : if (type == MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY) {
14927 : : struct mlx5_indlst_legacy *legacy = (typeof(legacy))handle;
14928 : :
14929 : 0 : ret = flow_hw_action_handle_destroy(dev, queue, attr,
14930 : : legacy->handle,
14931 : : user_data, error);
14932 : : mlx5_indirect_list_remove_entry(&legacy->indirect);
14933 : 0 : goto end;
14934 : : }
14935 [ # # ]: 0 : if (attr) {
14936 : : job = flow_hw_action_job_init(priv, queue, NULL, user_data,
14937 : : NULL, MLX5_HW_Q_JOB_TYPE_DESTROY,
14938 : : MLX5_HW_INDIRECT_TYPE_LIST, error);
14939 : : if (!job)
14940 : 0 : return rte_errno;
14941 : : }
14942 [ # # # ]: 0 : switch (type) {
14943 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR:
14944 : 0 : mlx5_hw_mirror_destroy(dev, (struct mlx5_mirror *)handle);
14945 : 0 : break;
14946 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT:
14947 [ # # ]: 0 : LIST_REMOVE(&((struct mlx5_hw_encap_decap_action *)handle)->indirect,
14948 : : entry);
14949 : 0 : mlx5_reformat_action_destroy(dev, handle, error);
14950 : 0 : break;
14951 : 0 : default:
14952 : 0 : ret = rte_flow_error_set(error, EINVAL,
14953 : : RTE_FLOW_ERROR_TYPE_ACTION,
14954 : : NULL, "Invalid indirect list handle");
14955 : : }
14956 [ # # ]: 0 : if (job) {
14957 : : flow_hw_action_finalize(dev, queue, job, push, false, true);
14958 : : }
14959 : 0 : end:
14960 : : return ret;
14961 : : }
14962 : :
14963 : : static int
14964 : 0 : flow_hw_action_list_handle_destroy(struct rte_eth_dev *dev,
14965 : : struct rte_flow_action_list_handle *handle,
14966 : : struct rte_flow_error *error)
14967 : : {
14968 : 0 : return flow_hw_async_action_list_handle_destroy(dev, MLX5_HW_INV_QUEUE,
14969 : : NULL, handle, NULL,
14970 : : error);
14971 : : }
14972 : :
14973 : : static int
14974 [ # # ]: 0 : flow_hw_async_action_list_handle_query_update
14975 : : (struct rte_eth_dev *dev, uint32_t queue_id,
14976 : : const struct rte_flow_op_attr *attr,
14977 : : const struct rte_flow_action_list_handle *handle,
14978 : : const void **update, void **query,
14979 : : enum rte_flow_query_update_mode mode,
14980 : : void *user_data, struct rte_flow_error *error)
14981 : : {
14982 : : enum mlx5_indirect_list_type type =
14983 : : mlx5_get_indirect_list_type((const void *)handle);
14984 : :
14985 [ # # ]: 0 : if (type == MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY) {
14986 : : struct mlx5_indlst_legacy *legacy = (void *)(uintptr_t)handle;
14987 : :
14988 [ # # ]: 0 : if (update && query)
14989 : 0 : return flow_hw_async_action_handle_query_update
14990 : : (dev, queue_id, attr, legacy->handle,
14991 : : update, query, mode, user_data, error);
14992 [ # # # # ]: 0 : else if (update && update[0])
14993 : 0 : return flow_hw_action_handle_update(dev, queue_id, attr,
14994 : : legacy->handle, update[0],
14995 : : user_data, error);
14996 [ # # # # ]: 0 : else if (query && query[0])
14997 : 0 : return flow_hw_action_handle_query(dev, queue_id, attr,
14998 : 0 : legacy->handle, query[0],
14999 : : user_data, error);
15000 : : else
15001 : 0 : return rte_flow_error_set(error, EINVAL,
15002 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15003 : : NULL, "invalid legacy handle query_update parameters");
15004 : : }
15005 : : return -ENOTSUP;
15006 : : }
15007 : :
15008 : : static int
15009 : 0 : flow_hw_action_list_handle_query_update(struct rte_eth_dev *dev,
15010 : : const struct rte_flow_action_list_handle *handle,
15011 : : const void **update, void **query,
15012 : : enum rte_flow_query_update_mode mode,
15013 : : struct rte_flow_error *error)
15014 : : {
15015 : 0 : return flow_hw_async_action_list_handle_query_update
15016 : : (dev, MLX5_HW_INV_QUEUE, NULL, handle,
15017 : : update, query, mode, NULL, error);
15018 : : }
15019 : :
15020 : : static int
15021 : 0 : flow_hw_calc_table_hash(struct rte_eth_dev *dev,
15022 : : const struct rte_flow_template_table *table,
15023 : : const struct rte_flow_item pattern[],
15024 : : uint8_t pattern_template_index,
15025 : : uint32_t *hash, struct rte_flow_error *error)
15026 : : {
15027 : : const struct rte_flow_item *items;
15028 : : struct mlx5_flow_hw_pattern_params pp;
15029 : : int res;
15030 : :
15031 : 0 : items = flow_hw_get_rule_items(dev, table, pattern,
15032 : : pattern_template_index,
15033 : : &pp);
15034 : 0 : res = mlx5dr_rule_hash_calculate(mlx5_table_matcher(table), items,
15035 : : pattern_template_index,
15036 : : MLX5DR_RULE_HASH_CALC_MODE_RAW,
15037 : : hash);
15038 [ # # ]: 0 : if (res)
15039 : 0 : return rte_flow_error_set(error, res,
15040 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15041 : : NULL,
15042 : : "hash could not be calculated");
15043 : : return 0;
15044 : : }
15045 : :
15046 : : static int
15047 : 0 : flow_hw_calc_encap_hash(struct rte_eth_dev *dev,
15048 : : const struct rte_flow_item pattern[],
15049 : : enum rte_flow_encap_hash_field dest_field,
15050 : : uint8_t *hash,
15051 : : struct rte_flow_error *error)
15052 : : {
15053 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
15054 : : struct mlx5dr_crc_encap_entropy_hash_fields data;
15055 : 0 : enum mlx5dr_crc_encap_entropy_hash_size res_size =
15056 : : dest_field == RTE_FLOW_ENCAP_HASH_FIELD_SRC_PORT ?
15057 : 0 : MLX5DR_CRC_ENCAP_ENTROPY_HASH_SIZE_16 :
15058 : : MLX5DR_CRC_ENCAP_ENTROPY_HASH_SIZE_8;
15059 : : int res;
15060 : :
15061 : : memset(&data, 0, sizeof(struct mlx5dr_crc_encap_entropy_hash_fields));
15062 : :
15063 [ # # ]: 0 : for (; pattern->type != RTE_FLOW_ITEM_TYPE_END; pattern++) {
15064 [ # # # # : 0 : switch (pattern->type) {
# # # # ]
15065 : 0 : case RTE_FLOW_ITEM_TYPE_IPV4:
15066 : 0 : data.dst.ipv4_addr =
15067 : 0 : ((const struct rte_flow_item_ipv4 *)(pattern->spec))->hdr.dst_addr;
15068 : 0 : data.src.ipv4_addr =
15069 : 0 : ((const struct rte_flow_item_ipv4 *)(pattern->spec))->hdr.src_addr;
15070 : 0 : break;
15071 : 0 : case RTE_FLOW_ITEM_TYPE_IPV6:
15072 : : memcpy(data.dst.ipv6_addr,
15073 : 0 : &((const struct rte_flow_item_ipv6 *)(pattern->spec))->hdr.dst_addr,
15074 : : sizeof(data.dst.ipv6_addr));
15075 : : memcpy(data.src.ipv6_addr,
15076 : : &((const struct rte_flow_item_ipv6 *)(pattern->spec))->hdr.src_addr,
15077 : : sizeof(data.src.ipv6_addr));
15078 : : break;
15079 : 0 : case RTE_FLOW_ITEM_TYPE_UDP:
15080 : 0 : data.next_protocol = IPPROTO_UDP;
15081 : 0 : data.dst_port =
15082 : 0 : ((const struct rte_flow_item_udp *)(pattern->spec))->hdr.dst_port;
15083 : 0 : data.src_port =
15084 : 0 : ((const struct rte_flow_item_udp *)(pattern->spec))->hdr.src_port;
15085 : 0 : break;
15086 : 0 : case RTE_FLOW_ITEM_TYPE_TCP:
15087 : 0 : data.next_protocol = IPPROTO_TCP;
15088 : 0 : data.dst_port =
15089 : 0 : ((const struct rte_flow_item_tcp *)(pattern->spec))->hdr.dst_port;
15090 : 0 : data.src_port =
15091 : 0 : ((const struct rte_flow_item_tcp *)(pattern->spec))->hdr.src_port;
15092 : 0 : break;
15093 : 0 : case RTE_FLOW_ITEM_TYPE_ICMP:
15094 : 0 : data.next_protocol = IPPROTO_ICMP;
15095 : 0 : break;
15096 : 0 : case RTE_FLOW_ITEM_TYPE_ICMP6:
15097 : 0 : data.next_protocol = IPPROTO_ICMPV6;
15098 : 0 : break;
15099 : 0 : case RTE_FLOW_ITEM_TYPE_GRE:
15100 : 0 : data.next_protocol = IPPROTO_GRE;
15101 : 0 : break;
15102 : : default:
15103 : : break;
15104 : : }
15105 : : }
15106 : 0 : res = mlx5dr_crc_encap_entropy_hash_calc(priv->dr_ctx, &data, hash, res_size);
15107 [ # # ]: 0 : if (res)
15108 : 0 : return rte_flow_error_set(error, res,
15109 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15110 : : NULL, "error while calculating encap hash");
15111 : : return 0;
15112 : : }
15113 : :
15114 : : static int
15115 : 0 : flow_hw_table_resize_multi_pattern_actions(struct rte_eth_dev *dev,
15116 : : struct rte_flow_template_table *table,
15117 : : uint32_t nb_flows,
15118 : : struct rte_flow_error *error)
15119 : : {
15120 : 0 : struct mlx5_multi_pattern_segment *segment = table->mpctx.segments;
15121 : : uint32_t bulk_size;
15122 : : int i, ret;
15123 : :
15124 : : /**
15125 : : * Segment always allocates Modify Header Argument Objects number in
15126 : : * powers of 2.
15127 : : * On resize, PMD adds minimal required argument objects number.
15128 : : * For example, if table size was 10, it allocated 16 argument objects.
15129 : : * Resize to 15 will not add new objects.
15130 : : */
15131 : 0 : for (i = 1;
15132 [ # # # # ]: 0 : i < MLX5_MAX_TABLE_RESIZE_NUM && segment->capacity;
15133 : 0 : i++, segment++) {
15134 : : /* keep the devtools/checkpatches.sh happy */
15135 : : }
15136 [ # # ]: 0 : if (i == MLX5_MAX_TABLE_RESIZE_NUM)
15137 : 0 : return rte_flow_error_set(error, EINVAL,
15138 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15139 : : table, "too many resizes");
15140 [ # # ]: 0 : if (segment->head_index - 1 >= nb_flows)
15141 : : return 0;
15142 [ # # ]: 0 : bulk_size = rte_align32pow2(nb_flows - segment->head_index + 1);
15143 : 0 : ret = mlx5_tbl_multi_pattern_process(dev, table, segment,
15144 : : rte_log2_u32(bulk_size),
15145 : : error);
15146 [ # # ]: 0 : if (ret)
15147 : 0 : return rte_flow_error_set(error, EINVAL,
15148 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15149 : : table, "too many resizes");
15150 : : return i;
15151 : : }
15152 : :
15153 : : static int
15154 : 0 : flow_hw_table_resize(struct rte_eth_dev *dev,
15155 : : struct rte_flow_template_table *table,
15156 : : uint32_t nb_flows,
15157 : : struct rte_flow_error *error)
15158 : : {
15159 : : struct mlx5dr_action_template *at[MLX5_HW_TBL_MAX_ACTION_TEMPLATE];
15160 : : struct mlx5dr_match_template *mt[MLX5_HW_TBL_MAX_ITEM_TEMPLATE];
15161 : 0 : struct mlx5dr_matcher_attr matcher_attr = table->matcher_attr;
15162 : 0 : struct mlx5dr_action_jump_to_matcher_attr jump_attr = {
15163 : : .type = MLX5DR_ACTION_JUMP_TO_MATCHER_BY_INDEX,
15164 : : .matcher = NULL,
15165 : : };
15166 : : struct mlx5_multi_pattern_segment *segment = NULL;
15167 : : struct mlx5dr_matcher *matcher = NULL;
15168 : : struct mlx5dr_action *jump = NULL;
15169 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
15170 : 0 : uint32_t i, selector = table->matcher_selector;
15171 : 0 : uint32_t other_selector = (selector + 1) & 1;
15172 : : int ret;
15173 : :
15174 [ # # ]: 0 : if (!rte_flow_template_table_resizable(dev->data->port_id, &table->cfg.attr))
15175 : 0 : return rte_flow_error_set(error, EINVAL,
15176 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15177 : : table, "no resizable attribute");
15178 [ # # ]: 0 : if (table->matcher_info[other_selector].matcher)
15179 : 0 : return rte_flow_error_set(error, EINVAL,
15180 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15181 : : table, "last table resize was not completed");
15182 [ # # ]: 0 : if (nb_flows <= table->cfg.attr.nb_flows)
15183 : 0 : return rte_flow_error_set(error, EINVAL,
15184 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15185 : : table, "shrinking table is not supported");
15186 : 0 : ret = mlx5_ipool_resize(table->flow, nb_flows, error);
15187 [ # # ]: 0 : if (ret)
15188 : : return ret;
15189 : : /*
15190 : : * A resizable matcher doesn't support rule update. In this case, the ipool
15191 : : * for the resource is not created and there is no need to resize it.
15192 : : */
15193 : : MLX5_ASSERT(!table->resource);
15194 [ # # ]: 0 : if (mlx5_is_multi_pattern_active(&table->mpctx)) {
15195 : 0 : ret = flow_hw_table_resize_multi_pattern_actions(dev, table, nb_flows, error);
15196 [ # # ]: 0 : if (ret < 0)
15197 : : return ret;
15198 [ # # ]: 0 : if (ret > 0)
15199 : 0 : segment = table->mpctx.segments + ret;
15200 : : }
15201 [ # # ]: 0 : for (i = 0; i < table->nb_item_templates; i++)
15202 : 0 : mt[i] = table->its[i]->mt;
15203 [ # # ]: 0 : for (i = 0; i < table->nb_action_templates; i++)
15204 : 0 : at[i] = table->ats[i].action_template->tmpl;
15205 : : nb_flows = rte_align32pow2(nb_flows);
15206 : 0 : matcher_attr.rule.num_log = rte_log2_u32(nb_flows);
15207 : 0 : matcher = mlx5dr_matcher_create(table->grp->tbl, mt,
15208 : : table->nb_item_templates, at,
15209 : : table->nb_action_templates,
15210 : : &matcher_attr);
15211 [ # # ]: 0 : if (!matcher) {
15212 : 0 : ret = rte_flow_error_set(error, rte_errno,
15213 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15214 : : table, "failed to create new matcher");
15215 : 0 : goto error;
15216 : : }
15217 [ # # ]: 0 : if (matcher_attr.isolated) {
15218 : 0 : jump_attr.matcher = matcher;
15219 : 0 : jump = mlx5dr_action_create_jump_to_matcher(priv->dr_ctx, &jump_attr,
15220 : 0 : mlx5_hw_act_flag[!!table->cfg.attr.flow_attr.group][table->type]);
15221 [ # # ]: 0 : if (!jump) {
15222 : 0 : ret = rte_flow_error_set(error, rte_errno,
15223 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15224 : : table, "failed to create jump to matcher action");
15225 : 0 : goto error;
15226 : : }
15227 : : }
15228 : 0 : rte_rwlock_write_lock(&table->matcher_replace_rwlk);
15229 : 0 : ret = mlx5dr_matcher_resize_set_target
15230 : : (table->matcher_info[selector].matcher, matcher);
15231 [ # # ]: 0 : if (ret) {
15232 : : rte_rwlock_write_unlock(&table->matcher_replace_rwlk);
15233 : 0 : ret = rte_flow_error_set(error, rte_errno,
15234 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15235 : : table, "failed to initiate matcher swap");
15236 : 0 : goto error;
15237 : : }
15238 : 0 : table->cfg.attr.nb_flows = nb_flows;
15239 : 0 : table->matcher_info[other_selector].matcher = matcher;
15240 : 0 : table->matcher_info[other_selector].jump = jump;
15241 : 0 : table->matcher_selector = other_selector;
15242 : 0 : rte_atomic_store_explicit(&table->matcher_info[other_selector].refcnt,
15243 : : 0, rte_memory_order_relaxed);
15244 : : rte_rwlock_write_unlock(&table->matcher_replace_rwlk);
15245 : 0 : return 0;
15246 : 0 : error:
15247 [ # # ]: 0 : if (segment)
15248 : 0 : mlx5_destroy_multi_pattern_segment(segment);
15249 [ # # ]: 0 : if (jump)
15250 : 0 : mlx5dr_action_destroy(jump);
15251 [ # # ]: 0 : if (matcher) {
15252 : 0 : ret = mlx5dr_matcher_destroy(matcher);
15253 : 0 : return rte_flow_error_set(error, rte_errno,
15254 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15255 : : table, "failed to destroy new matcher");
15256 : : }
15257 : : return ret;
15258 : : }
15259 : :
15260 : : static int
15261 : 0 : flow_hw_table_resize_complete(__rte_unused struct rte_eth_dev *dev,
15262 : : struct rte_flow_template_table *table,
15263 : : struct rte_flow_error *error)
15264 : : {
15265 : : int ret;
15266 : 0 : uint32_t selector = table->matcher_selector;
15267 : 0 : uint32_t other_selector = (selector + 1) & 1;
15268 : : struct mlx5_matcher_info *matcher_info = &table->matcher_info[other_selector];
15269 : : uint32_t matcher_refcnt;
15270 : :
15271 [ # # ]: 0 : if (!rte_flow_template_table_resizable(dev->data->port_id, &table->cfg.attr))
15272 : 0 : return rte_flow_error_set(error, EINVAL,
15273 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15274 : : table, "no resizable attribute");
15275 : 0 : matcher_refcnt = rte_atomic_load_explicit(&matcher_info->refcnt,
15276 : : rte_memory_order_relaxed);
15277 [ # # # # ]: 0 : if (!matcher_info->matcher || matcher_refcnt)
15278 : 0 : return rte_flow_error_set(error, EBUSY,
15279 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15280 : : table, "cannot complete table resize");
15281 [ # # ]: 0 : if (matcher_info->jump)
15282 : 0 : mlx5dr_action_destroy(matcher_info->jump);
15283 : 0 : ret = mlx5dr_matcher_destroy(matcher_info->matcher);
15284 [ # # ]: 0 : if (ret)
15285 : 0 : return rte_flow_error_set(error, rte_errno,
15286 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15287 : : table, "failed to destroy retired matcher");
15288 : 0 : matcher_info->matcher = NULL;
15289 : 0 : return 0;
15290 : : }
15291 : :
15292 : : static int
15293 : 0 : flow_hw_update_resized(struct rte_eth_dev *dev, uint32_t queue,
15294 : : const struct rte_flow_op_attr *attr,
15295 : : struct rte_flow *flow, void *user_data,
15296 : : struct rte_flow_error *error)
15297 : : {
15298 : : int ret;
15299 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
15300 : : struct rte_flow_hw *hw_flow = (struct rte_flow_hw *)flow;
15301 : 0 : struct rte_flow_template_table *table = hw_flow->table;
15302 [ # # ]: 0 : struct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(dev->data->port_id, hw_flow);
15303 : 0 : uint32_t table_selector = table->matcher_selector;
15304 : 0 : uint32_t rule_selector = aux->matcher_selector;
15305 : : uint32_t other_selector;
15306 : : struct mlx5dr_matcher *other_matcher;
15307 : 0 : struct mlx5dr_rule_attr rule_attr = {
15308 : : .queue_id = queue,
15309 : 0 : .burst = attr->postpone,
15310 : : };
15311 : :
15312 : : MLX5_ASSERT(hw_flow->flags & MLX5_FLOW_HW_FLOW_FLAG_MATCHER_SELECTOR);
15313 : : /**
15314 : : * mlx5dr_matcher_resize_rule_move() accepts original table matcher -
15315 : : * the one that was used BEFORE table resize.
15316 : : * Since the function is called AFTER table resize,
15317 : : * `table->matcher_selector` always points to the new matcher and
15318 : : * `aux->matcher_selector` points to a matcher used to create the flow.
15319 : : */
15320 : : other_selector = rule_selector == table_selector ?
15321 [ # # ]: 0 : (rule_selector + 1) & 1 : rule_selector;
15322 : 0 : other_matcher = table->matcher_info[other_selector].matcher;
15323 [ # # ]: 0 : if (!other_matcher)
15324 : 0 : return rte_flow_error_set(error, EINVAL,
15325 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
15326 : : "no active table resize");
15327 : 0 : hw_flow->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_MOVE;
15328 : 0 : hw_flow->user_data = user_data;
15329 : 0 : rule_attr.user_data = hw_flow;
15330 [ # # ]: 0 : if (rule_selector == table_selector) {
15331 : 0 : struct rte_ring *ring = !attr->postpone ?
15332 [ # # ]: 0 : priv->hw_q[queue].flow_transfer_completed :
15333 : 0 : priv->hw_q[queue].flow_transfer_pending;
15334 : 0 : rte_ring_enqueue(ring, hw_flow);
15335 : : flow_hw_q_inc_flow_ops(priv, queue);
15336 : 0 : return 0;
15337 : : }
15338 : 0 : ret = mlx5dr_matcher_resize_rule_move(other_matcher,
15339 : 0 : (struct mlx5dr_rule *)hw_flow->rule,
15340 : : &rule_attr);
15341 [ # # ]: 0 : if (ret) {
15342 : 0 : return rte_flow_error_set(error, rte_errno,
15343 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
15344 : : "flow transfer failed");
15345 : : }
15346 : : flow_hw_q_inc_flow_ops(priv, queue);
15347 : 0 : return 0;
15348 : : }
15349 : :
15350 : : /**
15351 : : * Internal validation function. For validating both actions and items.
15352 : : *
15353 : : * @param[in] dev
15354 : : * Pointer to the rte_eth_dev structure.
15355 : : * @param[in] attr
15356 : : * Pointer to the flow attributes.
15357 : : * @param[in] items
15358 : : * Pointer to the list of items.
15359 : : * @param[in] actions
15360 : : * Pointer to the list of actions.
15361 : : * @param[in] external
15362 : : * This flow rule is created by request external to PMD.
15363 : : * @param[in] hairpin
15364 : : * Number of hairpin TX actions, 0 means classic flow.
15365 : : * @param[out] error
15366 : : * Pointer to the error structure.
15367 : : *
15368 : : * @return
15369 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
15370 : : */
15371 : : static int
15372 : 0 : flow_hw_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
15373 : : const struct rte_flow_item items[],
15374 : : const struct rte_flow_action actions[] __rte_unused,
15375 : : bool external, int hairpin __rte_unused,
15376 : : struct rte_flow_error *error)
15377 : : {
15378 : 0 : const struct rte_flow_pattern_template_attr pattern_template_attr = {
15379 : : .relaxed_matching = 0,
15380 : 0 : .ingress = attr->ingress,
15381 : 0 : .egress = attr->egress,
15382 : 0 : .transfer = attr->transfer,
15383 : : };
15384 : 0 : uint64_t item_flags = 0;
15385 : : int ret = 0;
15386 : :
15387 [ # # ]: 0 : if (external) {
15388 : : /* Validate application items only */
15389 : 0 : ret = __flow_hw_pattern_validate(dev, &pattern_template_attr, items,
15390 : : &item_flags, true, error);
15391 [ # # ]: 0 : if (ret < 0)
15392 : 0 : return -rte_errno;
15393 : : }
15394 : : return 0;
15395 : : }
15396 : :
15397 : : const struct mlx5_flow_driver_ops mlx5_flow_hw_drv_ops = {
15398 : : .list_create = flow_hw_list_create,
15399 : : .list_destroy = flow_hw_list_destroy,
15400 : : .validate = flow_hw_validate,
15401 : : .info_get = flow_hw_info_get,
15402 : : .configure = flow_hw_configure,
15403 : : .pattern_validate = flow_hw_pattern_validate,
15404 : : .pattern_template_create = flow_hw_pattern_template_create,
15405 : : .pattern_template_destroy = flow_hw_pattern_template_destroy,
15406 : : .actions_validate = flow_hw_actions_validate,
15407 : : .actions_template_create = flow_hw_actions_template_create,
15408 : : .actions_template_destroy = flow_hw_actions_template_destroy,
15409 : : .template_table_create = flow_hw_template_table_create,
15410 : : .template_table_destroy = flow_hw_table_destroy,
15411 : : .table_resize = flow_hw_table_resize,
15412 : : .group_set_miss_actions = mlx5_flow_hw_group_set_miss_actions,
15413 : : .async_flow_create = flow_hw_async_flow_create,
15414 : : .async_flow_create_by_index = flow_hw_async_flow_create_by_index,
15415 : : .async_flow_update = flow_hw_async_flow_update,
15416 : : .async_flow_destroy = flow_hw_async_flow_destroy,
15417 : : .flow_update_resized = flow_hw_update_resized,
15418 : : .table_resize_complete = flow_hw_table_resize_complete,
15419 : : .pull = flow_hw_pull,
15420 : : .push = flow_hw_push,
15421 : : .async_action_create = flow_hw_action_handle_create,
15422 : : .async_action_destroy = flow_hw_action_handle_destroy,
15423 : : .async_action_update = flow_hw_action_handle_update,
15424 : : .async_action_query_update = flow_hw_async_action_handle_query_update,
15425 : : .async_action_query = flow_hw_action_handle_query,
15426 : : .action_validate = flow_hw_action_validate,
15427 : : .action_create = flow_hw_action_create,
15428 : : .action_destroy = flow_hw_action_destroy,
15429 : : .action_update = flow_hw_action_update,
15430 : : .action_query = flow_hw_action_query,
15431 : : .action_query_update = flow_hw_action_query_update,
15432 : : .action_list_handle_create = flow_hw_action_list_handle_create,
15433 : : .action_list_handle_destroy = flow_hw_action_list_handle_destroy,
15434 : : .action_list_handle_query_update =
15435 : : flow_hw_action_list_handle_query_update,
15436 : : .async_action_list_handle_create =
15437 : : flow_hw_async_action_list_handle_create,
15438 : : .async_action_list_handle_destroy =
15439 : : flow_hw_async_action_list_handle_destroy,
15440 : : .async_action_list_handle_query_update =
15441 : : flow_hw_async_action_list_handle_query_update,
15442 : : .query = flow_hw_query,
15443 : : .get_aged_flows = flow_hw_get_aged_flows,
15444 : : .get_q_aged_flows = flow_hw_get_q_aged_flows,
15445 : : .item_create = flow_dv_item_create,
15446 : : .item_release = flow_dv_item_release,
15447 : : .flow_calc_table_hash = flow_hw_calc_table_hash,
15448 : : .flow_calc_encap_hash = flow_hw_calc_encap_hash,
15449 : : };
15450 : :
15451 : : /**
15452 : : * Creates a control flow using flow template API on @p proxy_dev device,
15453 : : * on behalf of @p owner_dev device.
15454 : : *
15455 : : * This function uses locks internally to synchronize access to the
15456 : : * flow queue.
15457 : : *
15458 : : * Created flow is stored in private list associated with @p proxy_dev device.
15459 : : *
15460 : : * @param owner_dev
15461 : : * Pointer to Ethernet device on behalf of which flow is created.
15462 : : * @param proxy_dev
15463 : : * Pointer to Ethernet device on which flow is created.
15464 : : * @param table
15465 : : * Pointer to flow table.
15466 : : * @param items
15467 : : * Pointer to flow rule items.
15468 : : * @param item_template_idx
15469 : : * Index of an item template associated with @p table.
15470 : : * @param actions
15471 : : * Pointer to flow rule actions.
15472 : : * @param action_template_idx
15473 : : * Index of an action template associated with @p table.
15474 : : * @param info
15475 : : * Additional info about control flow rule.
15476 : : * @param external
15477 : : * External ctrl flow.
15478 : : *
15479 : : * @return
15480 : : * 0 on success, negative errno value otherwise and rte_errno set.
15481 : : */
15482 : : static __rte_unused int
15483 : 0 : flow_hw_create_ctrl_flow(struct rte_eth_dev *owner_dev,
15484 : : struct rte_eth_dev *proxy_dev,
15485 : : struct rte_flow_template_table *table,
15486 : : struct rte_flow_item items[],
15487 : : uint8_t item_template_idx,
15488 : : struct rte_flow_action actions[],
15489 : : uint8_t action_template_idx,
15490 : : struct mlx5_ctrl_flow_info *info,
15491 : : bool external)
15492 : : {
15493 : 0 : struct mlx5_priv *priv = proxy_dev->data->dev_private;
15494 : 0 : uint32_t queue = CTRL_QUEUE_ID(priv);
15495 : 0 : struct rte_flow_op_attr op_attr = {
15496 : : .postpone = 0,
15497 : : };
15498 : : struct rte_flow *flow = NULL;
15499 : : struct mlx5_ctrl_flow_entry *entry = NULL;
15500 : : int ret;
15501 : :
15502 : 0 : rte_spinlock_lock(&priv->hw_ctrl_lock);
15503 : 0 : entry = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_SYS, sizeof(*entry),
15504 : : 0, SOCKET_ID_ANY);
15505 [ # # ]: 0 : if (!entry) {
15506 : 0 : DRV_LOG(ERR, "port %u not enough memory to create control flows",
15507 : : proxy_dev->data->port_id);
15508 : 0 : rte_errno = ENOMEM;
15509 : : ret = -rte_errno;
15510 : 0 : goto error;
15511 : : }
15512 : 0 : flow = flow_hw_async_flow_create(proxy_dev, queue, &op_attr, table,
15513 : : items, item_template_idx,
15514 : : actions, action_template_idx,
15515 : : NULL, NULL);
15516 [ # # ]: 0 : if (!flow) {
15517 : 0 : DRV_LOG(ERR, "port %u failed to enqueue create control"
15518 : : " flow operation", proxy_dev->data->port_id);
15519 : 0 : ret = -rte_errno;
15520 : 0 : goto error;
15521 : : }
15522 : 0 : ret = __flow_hw_pull_comp(proxy_dev, queue, NULL);
15523 [ # # ]: 0 : if (ret) {
15524 : 0 : DRV_LOG(ERR, "port %u failed to insert control flow",
15525 : : proxy_dev->data->port_id);
15526 : 0 : rte_errno = EINVAL;
15527 : : ret = -rte_errno;
15528 : 0 : goto error;
15529 : : }
15530 : 0 : entry->owner_dev = owner_dev;
15531 : 0 : entry->flow = flow;
15532 [ # # ]: 0 : if (info)
15533 : 0 : entry->info = *info;
15534 : : else
15535 : 0 : entry->info.type = MLX5_CTRL_FLOW_TYPE_GENERAL;
15536 [ # # ]: 0 : if (external)
15537 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->hw_ext_ctrl_flows, entry, next);
15538 : : else
15539 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->hw_ctrl_flows, entry, next);
15540 : : rte_spinlock_unlock(&priv->hw_ctrl_lock);
15541 : 0 : return 0;
15542 : 0 : error:
15543 [ # # ]: 0 : if (entry)
15544 : 0 : mlx5_free(entry);
15545 : : rte_spinlock_unlock(&priv->hw_ctrl_lock);
15546 : 0 : return ret;
15547 : : }
15548 : :
15549 : : /**
15550 : : * Destroys a control flow @p flow using flow template API on @p dev device.
15551 : : *
15552 : : * This function uses locks internally to synchronize access to the
15553 : : * flow queue.
15554 : : *
15555 : : * If the @p flow is stored on any private list/pool, then caller must free up
15556 : : * the relevant resources.
15557 : : *
15558 : : * @param dev
15559 : : * Pointer to Ethernet device.
15560 : : * @param flow
15561 : : * Pointer to flow rule.
15562 : : *
15563 : : * @return
15564 : : * 0 on success, non-zero value otherwise.
15565 : : */
15566 : : static int
15567 : 0 : flow_hw_destroy_ctrl_flow(struct rte_eth_dev *dev, struct rte_flow *flow)
15568 : : {
15569 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
15570 : 0 : uint32_t queue = CTRL_QUEUE_ID(priv);
15571 : 0 : struct rte_flow_op_attr op_attr = {
15572 : : .postpone = 0,
15573 : : };
15574 : : int ret;
15575 : :
15576 : 0 : rte_spinlock_lock(&priv->hw_ctrl_lock);
15577 : 0 : ret = flow_hw_async_flow_destroy(dev, queue, &op_attr, flow, NULL, NULL);
15578 [ # # ]: 0 : if (ret) {
15579 : 0 : DRV_LOG(ERR, "port %u failed to enqueue destroy control"
15580 : : " flow operation", dev->data->port_id);
15581 : 0 : goto exit;
15582 : : }
15583 : 0 : ret = __flow_hw_pull_comp(dev, queue, NULL);
15584 [ # # ]: 0 : if (ret) {
15585 : 0 : DRV_LOG(ERR, "port %u failed to destroy control flow",
15586 : : dev->data->port_id);
15587 : 0 : rte_errno = EINVAL;
15588 : : ret = -rte_errno;
15589 : 0 : goto exit;
15590 : : }
15591 : 0 : exit:
15592 : : rte_spinlock_unlock(&priv->hw_ctrl_lock);
15593 : 0 : return ret;
15594 : : }
15595 : :
15596 : : /**
15597 : : * Destroys control flows created on behalf of @p owner device on @p dev device.
15598 : : *
15599 : : * @param dev
15600 : : * Pointer to Ethernet device on which control flows were created.
15601 : : * @param owner
15602 : : * Pointer to Ethernet device owning control flows.
15603 : : *
15604 : : * @return
15605 : : * 0 on success, otherwise negative error code is returned and
15606 : : * rte_errno is set.
15607 : : */
15608 : : static int
15609 : 0 : flow_hw_flush_ctrl_flows_owned_by(struct rte_eth_dev *dev, struct rte_eth_dev *owner)
15610 : : {
15611 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
15612 : : struct mlx5_ctrl_flow_entry *cf;
15613 : : struct mlx5_ctrl_flow_entry *cf_next;
15614 : : int ret;
15615 : :
15616 : 0 : cf = LIST_FIRST(&priv->hw_ctrl_flows);
15617 [ # # ]: 0 : while (cf != NULL) {
15618 : 0 : cf_next = LIST_NEXT(cf, next);
15619 [ # # ]: 0 : if (cf->owner_dev == owner) {
15620 : 0 : ret = flow_hw_destroy_ctrl_flow(dev, cf->flow);
15621 [ # # ]: 0 : if (ret) {
15622 : 0 : rte_errno = ret;
15623 : 0 : return -ret;
15624 : : }
15625 [ # # ]: 0 : LIST_REMOVE(cf, next);
15626 : 0 : mlx5_free(cf);
15627 : : }
15628 : : cf = cf_next;
15629 : : }
15630 : : return 0;
15631 : : }
15632 : :
15633 : : /**
15634 : : * Destroys control flows created for @p owner_dev device.
15635 : : *
15636 : : * @param owner_dev
15637 : : * Pointer to Ethernet device owning control flows.
15638 : : *
15639 : : * @return
15640 : : * 0 on success, otherwise negative error code is returned and
15641 : : * rte_errno is set.
15642 : : */
15643 : : int
15644 : 0 : mlx5_flow_hw_flush_ctrl_flows(struct rte_eth_dev *owner_dev)
15645 : : {
15646 : 0 : struct mlx5_priv *owner_priv = owner_dev->data->dev_private;
15647 : : struct rte_eth_dev *proxy_dev;
15648 : 0 : uint16_t owner_port_id = owner_dev->data->port_id;
15649 : 0 : uint16_t proxy_port_id = owner_dev->data->port_id;
15650 : : int ret;
15651 : :
15652 : : /* Flush all flows created by this port for itself. */
15653 : 0 : ret = flow_hw_flush_ctrl_flows_owned_by(owner_dev, owner_dev);
15654 [ # # ]: 0 : if (ret)
15655 : : return ret;
15656 : : /* Flush all flows created for this port on proxy port. */
15657 [ # # ]: 0 : if (owner_priv->sh->config.dv_esw_en) {
15658 : 0 : ret = rte_flow_pick_transfer_proxy(owner_port_id, &proxy_port_id, NULL);
15659 [ # # ]: 0 : if (ret == -ENODEV) {
15660 : 0 : DRV_LOG(DEBUG, "Unable to find transfer proxy port for port %u. It was "
15661 : : "probably closed. Control flows were cleared.",
15662 : : owner_port_id);
15663 : 0 : rte_errno = 0;
15664 : 0 : return 0;
15665 [ # # ]: 0 : } else if (ret) {
15666 : 0 : DRV_LOG(ERR, "Unable to find proxy port for port %u (ret = %d)",
15667 : : owner_port_id, ret);
15668 : 0 : return ret;
15669 : : }
15670 : 0 : proxy_dev = &rte_eth_devices[proxy_port_id];
15671 : : } else {
15672 : : proxy_dev = owner_dev;
15673 : : }
15674 : 0 : return flow_hw_flush_ctrl_flows_owned_by(proxy_dev, owner_dev);
15675 : : }
15676 : :
15677 : : /**
15678 : : * Destroys all control flows created on @p dev device.
15679 : : *
15680 : : * @param owner_dev
15681 : : * Pointer to Ethernet device.
15682 : : *
15683 : : * @return
15684 : : * 0 on success, otherwise negative error code is returned and
15685 : : * rte_errno is set.
15686 : : */
15687 : : static int
15688 : 0 : flow_hw_flush_all_ctrl_flows(struct rte_eth_dev *dev)
15689 : : {
15690 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
15691 : : struct mlx5_ctrl_flow_entry *cf;
15692 : : struct mlx5_ctrl_flow_entry *cf_next;
15693 : : int ret;
15694 : :
15695 : 0 : cf = LIST_FIRST(&priv->hw_ctrl_flows);
15696 [ # # ]: 0 : while (cf != NULL) {
15697 : 0 : cf_next = LIST_NEXT(cf, next);
15698 : 0 : ret = flow_hw_destroy_ctrl_flow(dev, cf->flow);
15699 [ # # ]: 0 : if (ret) {
15700 : 0 : rte_errno = ret;
15701 : 0 : return -ret;
15702 : : }
15703 [ # # ]: 0 : LIST_REMOVE(cf, next);
15704 : 0 : mlx5_free(cf);
15705 : : cf = cf_next;
15706 : : }
15707 : 0 : cf = LIST_FIRST(&priv->hw_ext_ctrl_flows);
15708 [ # # ]: 0 : while (cf != NULL) {
15709 : 0 : cf_next = LIST_NEXT(cf, next);
15710 : 0 : ret = flow_hw_destroy_ctrl_flow(dev, cf->flow);
15711 [ # # ]: 0 : if (ret) {
15712 : 0 : rte_errno = ret;
15713 : 0 : return -ret;
15714 : : }
15715 [ # # ]: 0 : LIST_REMOVE(cf, next);
15716 : 0 : mlx5_free(cf);
15717 : : cf = cf_next;
15718 : : }
15719 : : return 0;
15720 : : }
15721 : :
15722 : : int
15723 : 0 : mlx5_flow_hw_esw_create_sq_miss_flow(struct rte_eth_dev *dev, uint32_t sqn, bool external)
15724 : : {
15725 : 0 : uint16_t port_id = dev->data->port_id;
15726 : 0 : struct rte_flow_item_ethdev esw_mgr_spec = {
15727 : : .port_id = MLX5_REPRESENTED_PORT_ESW_MGR,
15728 : : };
15729 : 0 : struct rte_flow_item_ethdev esw_mgr_mask = {
15730 : : .port_id = MLX5_REPRESENTED_PORT_ESW_MGR,
15731 : : };
15732 : 0 : struct rte_flow_item_tag reg_c0_spec = {
15733 : : .index = (uint8_t)REG_C_0,
15734 : : .data = flow_hw_esw_mgr_regc_marker(dev),
15735 : : };
15736 : 0 : struct rte_flow_item_tag reg_c0_mask = {
15737 : : .index = 0xff,
15738 : : .data = flow_hw_esw_mgr_regc_marker_mask(dev),
15739 : : };
15740 : 0 : struct mlx5_rte_flow_item_sq sq_spec = {
15741 : : .queue = sqn,
15742 : : };
15743 : 0 : struct rte_flow_action_ethdev port = {
15744 : : .port_id = port_id,
15745 : : };
15746 : 0 : struct rte_flow_item items[3] = { { 0 } };
15747 : 0 : struct rte_flow_action actions[3] = { { 0 } };
15748 : 0 : struct mlx5_ctrl_flow_info flow_info = {
15749 : : .type = MLX5_CTRL_FLOW_TYPE_SQ_MISS_ROOT,
15750 : : .esw_mgr_sq = sqn,
15751 : : };
15752 : : struct rte_eth_dev *proxy_dev;
15753 : : struct mlx5_priv *proxy_priv;
15754 : 0 : uint16_t proxy_port_id = dev->data->port_id;
15755 : : int ret;
15756 : :
15757 : 0 : ret = rte_flow_pick_transfer_proxy(port_id, &proxy_port_id, NULL);
15758 [ # # ]: 0 : if (ret) {
15759 : 0 : DRV_LOG(ERR, "Unable to pick transfer proxy port for port %u. Transfer proxy "
15760 : : "port must be present to create default SQ miss flows.",
15761 : : port_id);
15762 : 0 : return ret;
15763 : : }
15764 : 0 : proxy_dev = &rte_eth_devices[proxy_port_id];
15765 : 0 : proxy_priv = proxy_dev->data->dev_private;
15766 [ # # ]: 0 : if (!proxy_priv->dr_ctx) {
15767 : 0 : DRV_LOG(DEBUG, "Transfer proxy port (port %u) of port %u must be configured "
15768 : : "for HWS to create default SQ miss flows. Default flows will "
15769 : : "not be created.",
15770 : : proxy_port_id, port_id);
15771 : 0 : return 0;
15772 : : }
15773 [ # # ]: 0 : if (!proxy_priv->hw_ctrl_fdb ||
15774 [ # # ]: 0 : !proxy_priv->hw_ctrl_fdb->hw_esw_sq_miss_root_tbl ||
15775 [ # # ]: 0 : !proxy_priv->hw_ctrl_fdb->hw_esw_sq_miss_tbl) {
15776 : 0 : DRV_LOG(ERR, "Transfer proxy port (port %u) of port %u was configured, but "
15777 : : "default flow tables were not created.",
15778 : : proxy_port_id, port_id);
15779 : 0 : rte_errno = ENOMEM;
15780 : 0 : return -rte_errno;
15781 : : }
15782 : : /*
15783 : : * Create a root SQ miss flow rule - match E-Switch Manager and SQ,
15784 : : * and jump to group 1.
15785 : : */
15786 : 0 : items[0] = (struct rte_flow_item){
15787 : : .type = RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT,
15788 : : .spec = &esw_mgr_spec,
15789 : : .mask = &esw_mgr_mask,
15790 : : };
15791 : 0 : items[1] = (struct rte_flow_item){
15792 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_SQ,
15793 : : .spec = &sq_spec,
15794 : : };
15795 : 0 : items[2] = (struct rte_flow_item){
15796 : : .type = RTE_FLOW_ITEM_TYPE_END,
15797 : : };
15798 : 0 : actions[0] = (struct rte_flow_action){
15799 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
15800 : : };
15801 : 0 : actions[1] = (struct rte_flow_action){
15802 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
15803 : : };
15804 : 0 : actions[2] = (struct rte_flow_action) {
15805 : : .type = RTE_FLOW_ACTION_TYPE_END,
15806 : : };
15807 : 0 : ret = flow_hw_create_ctrl_flow(dev, proxy_dev,
15808 : : proxy_priv->hw_ctrl_fdb->hw_esw_sq_miss_root_tbl,
15809 : : items, 0, actions, 0, &flow_info, external);
15810 [ # # ]: 0 : if (ret) {
15811 : 0 : DRV_LOG(ERR, "Port %u failed to create root SQ miss flow rule for SQ %u, ret %d",
15812 : : port_id, sqn, ret);
15813 : 0 : return ret;
15814 : : }
15815 : : /*
15816 : : * Create a non-root SQ miss flow rule - match REG_C_0 marker and SQ,
15817 : : * and forward to port.
15818 : : */
15819 : 0 : items[0] = (struct rte_flow_item){
15820 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_TAG,
15821 : : .spec = ®_c0_spec,
15822 : : .mask = ®_c0_mask,
15823 : : };
15824 : 0 : items[1] = (struct rte_flow_item){
15825 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_SQ,
15826 : : .spec = &sq_spec,
15827 : : };
15828 : 0 : items[2] = (struct rte_flow_item){
15829 : : .type = RTE_FLOW_ITEM_TYPE_END,
15830 : : };
15831 : 0 : actions[0] = (struct rte_flow_action){
15832 : : .type = RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT,
15833 : : .conf = &port,
15834 : : };
15835 : 0 : actions[1] = (struct rte_flow_action){
15836 : : .type = RTE_FLOW_ACTION_TYPE_END,
15837 : : };
15838 : 0 : flow_info.type = MLX5_CTRL_FLOW_TYPE_SQ_MISS;
15839 : 0 : ret = flow_hw_create_ctrl_flow(dev, proxy_dev,
15840 : 0 : proxy_priv->hw_ctrl_fdb->hw_esw_sq_miss_tbl,
15841 : : items, 0, actions, 0, &flow_info, external);
15842 [ # # ]: 0 : if (ret) {
15843 : 0 : DRV_LOG(ERR, "Port %u failed to create HWS SQ miss flow rule for SQ %u, ret %d",
15844 : : port_id, sqn, ret);
15845 : 0 : return ret;
15846 : : }
15847 : : return 0;
15848 : : }
15849 : :
15850 : : static bool
15851 : : flow_hw_is_matching_sq_miss_flow(struct mlx5_ctrl_flow_entry *cf,
15852 : : struct rte_eth_dev *dev,
15853 : : uint32_t sqn)
15854 : : {
15855 : 0 : if (cf->owner_dev != dev)
15856 : : return false;
15857 [ # # # # ]: 0 : if (cf->info.type == MLX5_CTRL_FLOW_TYPE_SQ_MISS_ROOT && cf->info.esw_mgr_sq == sqn)
15858 : : return true;
15859 [ # # # # ]: 0 : if (cf->info.type == MLX5_CTRL_FLOW_TYPE_SQ_MISS && cf->info.esw_mgr_sq == sqn)
15860 : : return true;
15861 : : return false;
15862 : : }
15863 : :
15864 : : int
15865 : 0 : mlx5_flow_hw_esw_destroy_sq_miss_flow(struct rte_eth_dev *dev, uint32_t sqn)
15866 : : {
15867 : 0 : uint16_t port_id = dev->data->port_id;
15868 : 0 : uint16_t proxy_port_id = dev->data->port_id;
15869 : : struct rte_eth_dev *proxy_dev;
15870 : : struct mlx5_priv *proxy_priv;
15871 : : struct mlx5_ctrl_flow_entry *cf;
15872 : : struct mlx5_ctrl_flow_entry *cf_next;
15873 : : int ret;
15874 : :
15875 : 0 : ret = rte_flow_pick_transfer_proxy(port_id, &proxy_port_id, NULL);
15876 [ # # ]: 0 : if (ret) {
15877 : 0 : DRV_LOG(ERR, "Unable to pick transfer proxy port for port %u. Transfer proxy "
15878 : : "port must be present for default SQ miss flow rules to exist.",
15879 : : port_id);
15880 : 0 : return ret;
15881 : : }
15882 : 0 : proxy_dev = &rte_eth_devices[proxy_port_id];
15883 : 0 : proxy_priv = proxy_dev->data->dev_private;
15884 : : /* FDB default flow rules must be enabled. */
15885 : : MLX5_ASSERT(proxy_priv->sh->config.fdb_def_rule);
15886 [ # # ]: 0 : if (!proxy_priv->dr_ctx)
15887 : : return 0;
15888 [ # # ]: 0 : if (!proxy_priv->hw_ctrl_fdb ||
15889 [ # # ]: 0 : !proxy_priv->hw_ctrl_fdb->hw_esw_sq_miss_root_tbl ||
15890 [ # # ]: 0 : !proxy_priv->hw_ctrl_fdb->hw_esw_sq_miss_tbl)
15891 : : return 0;
15892 : 0 : cf = LIST_FIRST(&proxy_priv->hw_ctrl_flows);
15893 [ # # ]: 0 : while (cf != NULL) {
15894 [ # # ]: 0 : cf_next = LIST_NEXT(cf, next);
15895 : : if (flow_hw_is_matching_sq_miss_flow(cf, dev, sqn)) {
15896 : 0 : claim_zero(flow_hw_destroy_ctrl_flow(proxy_dev, cf->flow));
15897 [ # # ]: 0 : LIST_REMOVE(cf, next);
15898 : 0 : mlx5_free(cf);
15899 : : }
15900 : : cf = cf_next;
15901 : : }
15902 : : return 0;
15903 : : }
15904 : :
15905 : : int
15906 : 0 : mlx5_flow_hw_esw_create_default_jump_flow(struct rte_eth_dev *dev)
15907 : : {
15908 : 0 : uint16_t port_id = dev->data->port_id;
15909 : 0 : struct rte_flow_item_ethdev port_spec = {
15910 : : .port_id = port_id,
15911 : : };
15912 : 0 : struct rte_flow_item items[] = {
15913 : : {
15914 : : .type = RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT,
15915 : : .spec = &port_spec,
15916 : : },
15917 : : {
15918 : : .type = RTE_FLOW_ITEM_TYPE_END,
15919 : : },
15920 : : };
15921 : 0 : struct rte_flow_action_jump jump = {
15922 : : .group = 1,
15923 : : };
15924 : 0 : struct rte_flow_action actions[] = {
15925 : : {
15926 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
15927 : : .conf = &jump,
15928 : : },
15929 : : {
15930 : : .type = RTE_FLOW_ACTION_TYPE_END,
15931 : : }
15932 : : };
15933 : 0 : struct mlx5_ctrl_flow_info flow_info = {
15934 : : .type = MLX5_CTRL_FLOW_TYPE_DEFAULT_JUMP,
15935 : : };
15936 : : struct rte_eth_dev *proxy_dev;
15937 : : struct mlx5_priv *proxy_priv;
15938 : 0 : uint16_t proxy_port_id = dev->data->port_id;
15939 : : int ret;
15940 : :
15941 : 0 : ret = rte_flow_pick_transfer_proxy(port_id, &proxy_port_id, NULL);
15942 [ # # ]: 0 : if (ret) {
15943 : 0 : DRV_LOG(ERR, "Unable to pick transfer proxy port for port %u. Transfer proxy "
15944 : : "port must be present to create default FDB jump rule.",
15945 : : port_id);
15946 : 0 : return ret;
15947 : : }
15948 : 0 : proxy_dev = &rte_eth_devices[proxy_port_id];
15949 : 0 : proxy_priv = proxy_dev->data->dev_private;
15950 : : /* FDB default flow rules must be enabled. */
15951 : : MLX5_ASSERT(proxy_priv->sh->config.fdb_def_rule);
15952 [ # # ]: 0 : if (!proxy_priv->dr_ctx) {
15953 : 0 : DRV_LOG(DEBUG, "Transfer proxy port (port %u) of port %u must be configured "
15954 : : "for HWS to create default FDB jump rule. Default rule will "
15955 : : "not be created.",
15956 : : proxy_port_id, port_id);
15957 : 0 : return 0;
15958 : : }
15959 [ # # # # ]: 0 : if (!proxy_priv->hw_ctrl_fdb || !proxy_priv->hw_ctrl_fdb->hw_esw_zero_tbl) {
15960 : 0 : DRV_LOG(ERR, "Transfer proxy port (port %u) of port %u was configured, but "
15961 : : "default flow tables were not created.",
15962 : : proxy_port_id, port_id);
15963 : 0 : rte_errno = EINVAL;
15964 : 0 : return -rte_errno;
15965 : : }
15966 : 0 : return flow_hw_create_ctrl_flow(dev, proxy_dev,
15967 : : proxy_priv->hw_ctrl_fdb->hw_esw_zero_tbl,
15968 : : items, 0, actions, 0, &flow_info, false);
15969 : : }
15970 : :
15971 : : int
15972 : 0 : mlx5_flow_hw_create_tx_default_mreg_copy_flow(struct rte_eth_dev *dev)
15973 : : {
15974 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
15975 : 0 : struct rte_flow_item_eth promisc = {
15976 : : .hdr.dst_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
15977 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
15978 : : .hdr.ether_type = 0,
15979 : : };
15980 : 0 : struct rte_flow_item eth_all[] = {
15981 : : [0] = {
15982 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
15983 : : .spec = &promisc,
15984 : : .mask = &promisc,
15985 : : },
15986 : : [1] = {
15987 : : .type = RTE_FLOW_ITEM_TYPE_END,
15988 : : },
15989 : : };
15990 : 0 : struct rte_flow_action_modify_field mreg_action = {
15991 : : .operation = RTE_FLOW_MODIFY_SET,
15992 : : .dst = {
15993 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
15994 : : .tag_index = REG_C_1,
15995 : : },
15996 : : .src = {
15997 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
15998 : : .tag_index = REG_A,
15999 : : },
16000 : : .width = 32,
16001 : : };
16002 : 0 : struct rte_flow_action copy_reg_action[] = {
16003 : : [0] = {
16004 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
16005 : : .conf = &mreg_action,
16006 : : },
16007 : : [1] = {
16008 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
16009 : : },
16010 : : [2] = {
16011 : : .type = RTE_FLOW_ACTION_TYPE_END,
16012 : : },
16013 : : };
16014 : 0 : struct mlx5_ctrl_flow_info flow_info = {
16015 : : .type = MLX5_CTRL_FLOW_TYPE_TX_META_COPY,
16016 : : };
16017 : :
16018 : : MLX5_ASSERT(priv->master);
16019 [ # # ]: 0 : if (!priv->dr_ctx ||
16020 [ # # ]: 0 : !priv->hw_ctrl_fdb ||
16021 [ # # ]: 0 : !priv->hw_ctrl_fdb->hw_tx_meta_cpy_tbl)
16022 : : return 0;
16023 : 0 : return flow_hw_create_ctrl_flow(dev, dev,
16024 : : priv->hw_ctrl_fdb->hw_tx_meta_cpy_tbl,
16025 : : eth_all, 0, copy_reg_action, 0, &flow_info, false);
16026 : : }
16027 : :
16028 : : int
16029 : 0 : mlx5_flow_hw_tx_repr_matching_flow(struct rte_eth_dev *dev, uint32_t sqn, bool external)
16030 : : {
16031 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16032 : 0 : struct mlx5_rte_flow_item_sq sq_spec = {
16033 : : .queue = sqn,
16034 : : };
16035 : 0 : struct rte_flow_item items[] = {
16036 : : {
16037 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_SQ,
16038 : : .spec = &sq_spec,
16039 : : },
16040 : : {
16041 : : .type = RTE_FLOW_ITEM_TYPE_END,
16042 : : },
16043 : : };
16044 : : /*
16045 : : * Allocate actions array suitable for all cases - extended metadata enabled or not.
16046 : : * With extended metadata there will be an additional MODIFY_FIELD action before JUMP.
16047 : : */
16048 : 0 : struct rte_flow_action actions[] = {
16049 : : { .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD },
16050 : : { .type = RTE_FLOW_ACTION_TYPE_JUMP },
16051 : : { .type = RTE_FLOW_ACTION_TYPE_END },
16052 : : { .type = RTE_FLOW_ACTION_TYPE_END },
16053 : : };
16054 : 0 : struct mlx5_ctrl_flow_info flow_info = {
16055 : : .type = MLX5_CTRL_FLOW_TYPE_TX_REPR_MATCH,
16056 : : .tx_repr_sq = sqn,
16057 : : };
16058 : :
16059 : : /* It is assumed that caller checked for representor matching. */
16060 : : MLX5_ASSERT(priv->sh->config.repr_matching);
16061 [ # # ]: 0 : if (!priv->dr_ctx) {
16062 : 0 : DRV_LOG(DEBUG, "Port %u must be configured for HWS, before creating "
16063 : : "default egress flow rules. Omitting creation.",
16064 : : dev->data->port_id);
16065 : 0 : return 0;
16066 : : }
16067 [ # # ]: 0 : if (!priv->hw_tx_repr_tagging_tbl) {
16068 : 0 : DRV_LOG(ERR, "Port %u is configured for HWS, but table for default "
16069 : : "egress flow rules does not exist.",
16070 : : dev->data->port_id);
16071 : 0 : rte_errno = EINVAL;
16072 : 0 : return -rte_errno;
16073 : : }
16074 : : /*
16075 : : * If extended metadata mode is enabled, then an additional MODIFY_FIELD action must be
16076 : : * placed before terminating JUMP action.
16077 : : */
16078 [ # # ]: 0 : if (priv->sh->config.dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS) {
16079 : 0 : actions[1].type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD;
16080 : 0 : actions[2].type = RTE_FLOW_ACTION_TYPE_JUMP;
16081 : : }
16082 : 0 : return flow_hw_create_ctrl_flow(dev, dev, priv->hw_tx_repr_tagging_tbl,
16083 : : items, 0, actions, 0, &flow_info, external);
16084 : : }
16085 : :
16086 : : int
16087 : 0 : mlx5_flow_hw_lacp_rx_flow(struct rte_eth_dev *dev)
16088 : : {
16089 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16090 : 0 : struct rte_flow_item_eth lacp_item = {
16091 : : .type = RTE_BE16(RTE_ETHER_TYPE_SLOW),
16092 : : };
16093 : 0 : struct rte_flow_item eth_lacp[] = {
16094 : : [0] = {
16095 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
16096 : : .spec = &lacp_item,
16097 : : .mask = &lacp_item,
16098 : : },
16099 : : [1] = {
16100 : : .type = RTE_FLOW_ITEM_TYPE_END,
16101 : : },
16102 : : };
16103 : 0 : struct rte_flow_action miss_action[] = {
16104 : : [0] = {
16105 : : .type = (enum rte_flow_action_type)
16106 : : MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS,
16107 : : },
16108 : : [1] = {
16109 : : .type = RTE_FLOW_ACTION_TYPE_END,
16110 : : },
16111 : : };
16112 : 0 : struct mlx5_ctrl_flow_info flow_info = {
16113 : : .type = MLX5_CTRL_FLOW_TYPE_LACP_RX,
16114 : : };
16115 : :
16116 [ # # # # : 0 : if (!priv->dr_ctx || !priv->hw_ctrl_fdb || !priv->hw_ctrl_fdb->hw_lacp_rx_tbl)
# # ]
16117 : : return 0;
16118 : 0 : return flow_hw_create_ctrl_flow(dev, dev,
16119 : : priv->hw_ctrl_fdb->hw_lacp_rx_tbl,
16120 : : eth_lacp, 0, miss_action, 0, &flow_info, false);
16121 : : }
16122 : :
16123 : : static uint32_t
16124 : : __calc_pattern_flags(const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type)
16125 : : {
16126 : : switch (eth_pattern_type) {
16127 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL:
16128 : : return MLX5_CTRL_PROMISCUOUS;
16129 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL_MCAST:
16130 : : return MLX5_CTRL_ALL_MULTICAST;
16131 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST:
16132 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST_VLAN:
16133 : : return MLX5_CTRL_BROADCAST;
16134 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST:
16135 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST_VLAN:
16136 : : return MLX5_CTRL_IPV4_MULTICAST;
16137 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST:
16138 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST_VLAN:
16139 : : return MLX5_CTRL_IPV6_MULTICAST;
16140 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC:
16141 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN:
16142 : : return MLX5_CTRL_DMAC;
16143 : : default:
16144 : : /* Should not reach here. */
16145 : : MLX5_ASSERT(false);
16146 : : return 0;
16147 : : }
16148 : : }
16149 : :
16150 : : static uint32_t
16151 : : __calc_vlan_flags(const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type)
16152 : : {
16153 [ # # ]: 0 : switch (eth_pattern_type) {
16154 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST_VLAN:
16155 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST_VLAN:
16156 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST_VLAN:
16157 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN:
16158 : : return MLX5_CTRL_VLAN_FILTER;
16159 : 0 : default:
16160 : 0 : return 0;
16161 : : }
16162 : : }
16163 : :
16164 : : static bool
16165 [ # # ]: 0 : eth_pattern_type_is_requested(const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type,
16166 : : uint32_t flags)
16167 : : {
16168 : : uint32_t pattern_flags = __calc_pattern_flags(eth_pattern_type);
16169 : : uint32_t vlan_flags = __calc_vlan_flags(eth_pattern_type);
16170 : 0 : bool pattern_requested = !!(pattern_flags & flags);
16171 [ # # # # ]: 0 : bool consider_vlan = vlan_flags || (MLX5_CTRL_VLAN_FILTER & flags);
16172 : 0 : bool vlan_requested = !!(vlan_flags & flags);
16173 : :
16174 [ # # ]: 0 : if (consider_vlan)
16175 : 0 : return pattern_requested && vlan_requested;
16176 : : else
16177 : : return pattern_requested;
16178 : : }
16179 : :
16180 : : static bool
16181 : : rss_type_is_requested(struct mlx5_priv *priv,
16182 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
16183 : : {
16184 : 0 : struct rte_flow_actions_template *at = priv->hw_ctrl_rx->rss[rss_type];
16185 : : unsigned int i;
16186 : :
16187 [ # # # # ]: 0 : for (i = 0; at->actions[i].type != RTE_FLOW_ACTION_TYPE_END; ++i) {
16188 [ # # # # ]: 0 : if (at->actions[i].type == RTE_FLOW_ACTION_TYPE_RSS) {
16189 : 0 : const struct rte_flow_action_rss *rss = at->actions[i].conf;
16190 : 0 : uint64_t rss_types = rss->types;
16191 : :
16192 [ # # # # ]: 0 : if ((rss_types & priv->rss_conf.rss_hf) != rss_types)
16193 : : return false;
16194 : : }
16195 : : }
16196 : : return true;
16197 : : }
16198 : :
16199 : : static const struct rte_flow_item_eth *
16200 : : __get_eth_spec(const enum mlx5_flow_ctrl_rx_eth_pattern_type pattern)
16201 : : {
16202 : 0 : switch (pattern) {
16203 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL:
16204 : : return &ctrl_rx_eth_promisc_spec;
16205 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL_MCAST:
16206 : 0 : return &ctrl_rx_eth_mcast_spec;
16207 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST:
16208 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST_VLAN:
16209 : 0 : return &ctrl_rx_eth_bcast_spec;
16210 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST:
16211 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST_VLAN:
16212 : 0 : return &ctrl_rx_eth_ipv4_mcast_spec;
16213 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST:
16214 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST_VLAN:
16215 : 0 : return &ctrl_rx_eth_ipv6_mcast_spec;
16216 : 0 : default:
16217 : : /* This case should not be reached. */
16218 : : MLX5_ASSERT(false);
16219 : 0 : return NULL;
16220 : : }
16221 : : }
16222 : :
16223 : : static int
16224 [ # # # # : 0 : __flow_hw_ctrl_flows_single(struct rte_eth_dev *dev,
# # ]
16225 : : struct rte_flow_template_table *tbl,
16226 : : const enum mlx5_flow_ctrl_rx_eth_pattern_type pattern_type,
16227 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
16228 : : {
16229 : : const struct rte_flow_item_eth *eth_spec = __get_eth_spec(pattern_type);
16230 : : struct rte_flow_item items[5];
16231 : 0 : struct rte_flow_action actions[] = {
16232 : : { .type = RTE_FLOW_ACTION_TYPE_RSS },
16233 : : { .type = RTE_FLOW_ACTION_TYPE_END },
16234 : : };
16235 : 0 : struct mlx5_ctrl_flow_info flow_info = {
16236 : : .type = MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS,
16237 : : };
16238 : :
16239 [ # # ]: 0 : if (!eth_spec)
16240 : : return -EINVAL;
16241 : : memset(items, 0, sizeof(items));
16242 : 0 : items[0] = (struct rte_flow_item){
16243 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
16244 : : .spec = eth_spec,
16245 : : };
16246 [ # # # ]: 0 : items[1] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_VOID };
16247 [ # # # ]: 0 : items[2] = flow_hw_get_ctrl_rx_l3_item(rss_type);
16248 : 0 : items[3] = flow_hw_get_ctrl_rx_l4_item(rss_type);
16249 : 0 : items[4] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_END };
16250 : : /* Without VLAN filtering, only a single flow rule must be created. */
16251 : 0 : return flow_hw_create_ctrl_flow(dev, dev, tbl, items, 0, actions, 0, &flow_info, false);
16252 : : }
16253 : :
16254 : : static int
16255 : 0 : __flow_hw_ctrl_flows_single_vlan(struct rte_eth_dev *dev,
16256 : : struct rte_flow_template_table *tbl,
16257 : : const enum mlx5_flow_ctrl_rx_eth_pattern_type pattern_type,
16258 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
16259 : : {
16260 [ # # # # : 0 : struct mlx5_priv *priv = dev->data->dev_private;
# # ]
16261 : : const struct rte_flow_item_eth *eth_spec = __get_eth_spec(pattern_type);
16262 : : struct rte_flow_item items[5];
16263 : 0 : struct rte_flow_action actions[] = {
16264 : : { .type = RTE_FLOW_ACTION_TYPE_RSS },
16265 : : { .type = RTE_FLOW_ACTION_TYPE_END },
16266 : : };
16267 : 0 : struct mlx5_ctrl_flow_info flow_info = {
16268 : : .type = MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS,
16269 : : };
16270 : : unsigned int i;
16271 : :
16272 [ # # ]: 0 : if (!eth_spec)
16273 : : return -EINVAL;
16274 : : memset(items, 0, sizeof(items));
16275 : 0 : items[0] = (struct rte_flow_item){
16276 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
16277 : : .spec = eth_spec,
16278 : : };
16279 : : /* Optional VLAN for now will be VOID - will be filled later. */
16280 [ # # # ]: 0 : items[1] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_VLAN };
16281 [ # # # ]: 0 : items[2] = flow_hw_get_ctrl_rx_l3_item(rss_type);
16282 : 0 : items[3] = flow_hw_get_ctrl_rx_l4_item(rss_type);
16283 : 0 : items[4] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_END };
16284 : : /* Since VLAN filtering is done, create a single flow rule for each registered vid. */
16285 [ # # ]: 0 : for (i = 0; i < priv->vlan_filter_n; ++i) {
16286 : 0 : uint16_t vlan = priv->vlan_filter[i];
16287 : 0 : struct rte_flow_item_vlan vlan_spec = {
16288 [ # # ]: 0 : .hdr.vlan_tci = rte_cpu_to_be_16(vlan),
16289 : : };
16290 : :
16291 : 0 : items[1].spec = &vlan_spec;
16292 [ # # ]: 0 : if (flow_hw_create_ctrl_flow(dev, dev,
16293 : : tbl, items, 0, actions, 0, &flow_info, false))
16294 : 0 : return -rte_errno;
16295 : : }
16296 : : return 0;
16297 : : }
16298 : :
16299 : : static int
16300 : 0 : __flow_hw_ctrl_flows_unicast_create(struct rte_eth_dev *dev,
16301 : : struct rte_flow_template_table *tbl,
16302 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type,
16303 : : const struct rte_ether_addr *addr)
16304 : : {
16305 : 0 : struct rte_flow_item_eth eth_spec = {
16306 : : .hdr.dst_addr = *addr,
16307 : : };
16308 : : struct rte_flow_item items[5];
16309 : 0 : struct rte_flow_action actions[] = {
16310 : : { .type = RTE_FLOW_ACTION_TYPE_RSS },
16311 : : { .type = RTE_FLOW_ACTION_TYPE_END },
16312 : : };
16313 [ # # # ]: 0 : struct mlx5_ctrl_flow_info flow_info = {
16314 : : .type = MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC,
16315 : : .uc = {
16316 : : .dmac = *addr,
16317 : : },
16318 : : };
16319 : :
16320 : : memset(items, 0, sizeof(items));
16321 : 0 : items[0] = (struct rte_flow_item){
16322 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
16323 : : .spec = ð_spec,
16324 : : };
16325 [ # # # ]: 0 : items[1] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_VOID };
16326 [ # # # ]: 0 : items[2] = flow_hw_get_ctrl_rx_l3_item(rss_type);
16327 : 0 : items[3] = flow_hw_get_ctrl_rx_l4_item(rss_type);
16328 : 0 : items[4] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_END };
16329 : :
16330 [ # # ]: 0 : if (flow_hw_create_ctrl_flow(dev, dev, tbl, items, 0, actions, 0, &flow_info, false))
16331 : 0 : return -rte_errno;
16332 : :
16333 : : return 0;
16334 : : }
16335 : :
16336 : : static int
16337 : 0 : __flow_hw_ctrl_flows_unicast(struct rte_eth_dev *dev,
16338 : : struct rte_flow_template_table *tbl,
16339 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
16340 : : {
16341 : : unsigned int i;
16342 : : int ret;
16343 : :
16344 [ # # ]: 0 : for (i = 0; i < MLX5_MAX_MAC_ADDRESSES; ++i) {
16345 [ # # ]: 0 : struct rte_ether_addr *mac = &dev->data->mac_addrs[i];
16346 : :
16347 [ # # ]: 0 : if (rte_is_zero_ether_addr(mac))
16348 : 0 : continue;
16349 : :
16350 : 0 : ret = __flow_hw_ctrl_flows_unicast_create(dev, tbl, rss_type, mac);
16351 [ # # ]: 0 : if (ret < 0)
16352 : 0 : return ret;
16353 : : }
16354 : : return 0;
16355 : : }
16356 : :
16357 : : static int
16358 : 0 : __flow_hw_ctrl_flows_unicast_vlan_create(struct rte_eth_dev *dev,
16359 : : struct rte_flow_template_table *tbl,
16360 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type,
16361 : : const struct rte_ether_addr *addr,
16362 : : const uint16_t vid)
16363 : : {
16364 : 0 : struct rte_flow_item_eth eth_spec = {
16365 : : .hdr.dst_addr = *addr,
16366 : : };
16367 : 0 : struct rte_flow_item_vlan vlan_spec = {
16368 [ # # ]: 0 : .tci = rte_cpu_to_be_16(vid),
16369 : : };
16370 : : struct rte_flow_item items[5];
16371 : 0 : struct rte_flow_action actions[] = {
16372 : : { .type = RTE_FLOW_ACTION_TYPE_RSS },
16373 : : { .type = RTE_FLOW_ACTION_TYPE_END },
16374 : : };
16375 [ # # # ]: 0 : struct mlx5_ctrl_flow_info flow_info = {
16376 : : .type = MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC_VLAN,
16377 : : .uc = {
16378 : : .dmac = *addr,
16379 : : .vlan = vid,
16380 : : },
16381 : : };
16382 : :
16383 : : memset(items, 0, sizeof(items));
16384 : 0 : items[0] = (struct rte_flow_item){
16385 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
16386 : : .spec = ð_spec,
16387 : : };
16388 [ # # # ]: 0 : items[1] = (struct rte_flow_item){
16389 : : .type = RTE_FLOW_ITEM_TYPE_VLAN,
16390 : : .spec = &vlan_spec,
16391 : : };
16392 [ # # # ]: 0 : items[2] = flow_hw_get_ctrl_rx_l3_item(rss_type);
16393 : 0 : items[3] = flow_hw_get_ctrl_rx_l4_item(rss_type);
16394 : 0 : items[4] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_END };
16395 : :
16396 [ # # ]: 0 : if (flow_hw_create_ctrl_flow(dev, dev, tbl, items, 0, actions, 0, &flow_info, false))
16397 : 0 : return -rte_errno;
16398 : :
16399 : : return 0;
16400 : : }
16401 : :
16402 : : static int
16403 : 0 : __flow_hw_ctrl_flows_unicast_vlan(struct rte_eth_dev *dev,
16404 : : struct rte_flow_template_table *tbl,
16405 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
16406 : : {
16407 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16408 : : unsigned int i;
16409 : : unsigned int j;
16410 : :
16411 [ # # ]: 0 : for (i = 0; i < MLX5_MAX_MAC_ADDRESSES; ++i) {
16412 [ # # ]: 0 : struct rte_ether_addr *mac = &dev->data->mac_addrs[i];
16413 : :
16414 [ # # ]: 0 : if (rte_is_zero_ether_addr(mac))
16415 : 0 : continue;
16416 : :
16417 [ # # ]: 0 : for (j = 0; j < priv->vlan_filter_n; ++j) {
16418 : 0 : uint16_t vlan = priv->vlan_filter[j];
16419 : : int ret;
16420 : :
16421 : 0 : ret = __flow_hw_ctrl_flows_unicast_vlan_create(dev, tbl, rss_type,
16422 : : mac, vlan);
16423 [ # # ]: 0 : if (ret < 0)
16424 : 0 : return ret;
16425 : : }
16426 : : }
16427 : : return 0;
16428 : : }
16429 : :
16430 : : static int
16431 : 0 : __flow_hw_ctrl_flows(struct rte_eth_dev *dev,
16432 : : struct rte_flow_template_table *tbl,
16433 : : const enum mlx5_flow_ctrl_rx_eth_pattern_type pattern_type,
16434 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
16435 : : {
16436 [ # # # # : 0 : switch (pattern_type) {
# ]
16437 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL:
16438 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL_MCAST:
16439 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST:
16440 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST:
16441 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST:
16442 : 0 : return __flow_hw_ctrl_flows_single(dev, tbl, pattern_type, rss_type);
16443 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST_VLAN:
16444 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST_VLAN:
16445 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST_VLAN:
16446 : 0 : return __flow_hw_ctrl_flows_single_vlan(dev, tbl, pattern_type, rss_type);
16447 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC:
16448 : 0 : return __flow_hw_ctrl_flows_unicast(dev, tbl, rss_type);
16449 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN:
16450 : 0 : return __flow_hw_ctrl_flows_unicast_vlan(dev, tbl, rss_type);
16451 : 0 : default:
16452 : : /* Should not reach here. */
16453 : : MLX5_ASSERT(false);
16454 : 0 : rte_errno = EINVAL;
16455 : 0 : return -EINVAL;
16456 : : }
16457 : : }
16458 : :
16459 : :
16460 : : int
16461 : 0 : mlx5_flow_hw_ctrl_flows(struct rte_eth_dev *dev, uint32_t flags)
16462 : : {
16463 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16464 : : struct mlx5_flow_hw_ctrl_rx *hw_ctrl_rx;
16465 : : unsigned int i;
16466 : : int j;
16467 : : int ret = 0;
16468 : :
16469 : : RTE_SET_USED(priv);
16470 : : RTE_SET_USED(flags);
16471 [ # # ]: 0 : if (!priv->dr_ctx) {
16472 : 0 : DRV_LOG(DEBUG, "port %u Control flow rules will not be created. "
16473 : : "HWS needs to be configured beforehand.",
16474 : : dev->data->port_id);
16475 : 0 : return 0;
16476 : : }
16477 [ # # ]: 0 : if (!priv->hw_ctrl_rx) {
16478 : 0 : DRV_LOG(ERR, "port %u Control flow rules templates were not created.",
16479 : : dev->data->port_id);
16480 : 0 : rte_errno = EINVAL;
16481 : 0 : return -rte_errno;
16482 : : }
16483 : : hw_ctrl_rx = priv->hw_ctrl_rx;
16484 [ # # ]: 0 : for (i = 0; i < MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_MAX; ++i) {
16485 : : const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type = i;
16486 : :
16487 [ # # ]: 0 : if (!eth_pattern_type_is_requested(eth_pattern_type, flags))
16488 : 0 : continue;
16489 [ # # ]: 0 : for (j = 0; j < MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX; ++j) {
16490 : 0 : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type = j;
16491 : : struct rte_flow_actions_template *at;
16492 : : struct mlx5_flow_hw_ctrl_rx_table *tmpls = &hw_ctrl_rx->tables[i][j];
16493 : 0 : const struct mlx5_flow_template_table_cfg cfg = {
16494 : : .attr = tmpls->attr,
16495 : : .external = 0,
16496 : : };
16497 : :
16498 [ # # ]: 0 : if (!hw_ctrl_rx->rss[rss_type]) {
16499 : 0 : at = flow_hw_create_ctrl_rx_rss_template(dev, rss_type);
16500 [ # # ]: 0 : if (!at)
16501 : 0 : return -rte_errno;
16502 : 0 : hw_ctrl_rx->rss[rss_type] = at;
16503 : : } else {
16504 : 0 : at = hw_ctrl_rx->rss[rss_type];
16505 : : }
16506 [ # # ]: 0 : if (!rss_type_is_requested(priv, rss_type))
16507 : 0 : continue;
16508 [ # # ]: 0 : if (!tmpls->tbl) {
16509 : 0 : tmpls->tbl = flow_hw_table_create(dev, &cfg,
16510 : : &tmpls->pt, 1, &at, 1, NULL);
16511 [ # # ]: 0 : if (!tmpls->tbl) {
16512 : 0 : DRV_LOG(ERR, "port %u Failed to create template table "
16513 : : "for control flow rules. Unable to create "
16514 : : "control flow rules.",
16515 : : dev->data->port_id);
16516 : 0 : return -rte_errno;
16517 : : }
16518 : : }
16519 : :
16520 : 0 : ret = __flow_hw_ctrl_flows(dev, tmpls->tbl, eth_pattern_type, rss_type);
16521 [ # # ]: 0 : if (ret) {
16522 : 0 : DRV_LOG(ERR, "port %u Failed to create control flow rule.",
16523 : : dev->data->port_id);
16524 : 0 : return ret;
16525 : : }
16526 : : }
16527 : : }
16528 : : return 0;
16529 : : }
16530 : :
16531 : : static int
16532 : 0 : mlx5_flow_hw_ctrl_flow_single(struct rte_eth_dev *dev,
16533 : : const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type,
16534 : : const struct rte_ether_addr *addr,
16535 : : const uint16_t vlan)
16536 : : {
16537 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16538 : : struct mlx5_flow_hw_ctrl_rx *hw_ctrl_rx;
16539 : : unsigned int j;
16540 : : int ret = 0;
16541 : :
16542 [ # # ]: 0 : if (!priv->dr_ctx) {
16543 : 0 : DRV_LOG(DEBUG, "port %u Control flow rules will not be created. "
16544 : : "HWS needs to be configured beforehand.",
16545 : : dev->data->port_id);
16546 : 0 : return 0;
16547 : : }
16548 [ # # ]: 0 : if (!priv->hw_ctrl_rx) {
16549 : 0 : DRV_LOG(ERR, "port %u Control flow rules templates were not created.",
16550 : : dev->data->port_id);
16551 : 0 : rte_errno = EINVAL;
16552 : 0 : return -rte_errno;
16553 : : }
16554 : : hw_ctrl_rx = priv->hw_ctrl_rx;
16555 : :
16556 : : /* TODO: this part should be somehow refactored. It's common with common flow creation. */
16557 [ # # ]: 0 : for (j = 0; j < MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX; ++j) {
16558 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type = j;
16559 : : const unsigned int pti = eth_pattern_type;
16560 : : struct rte_flow_actions_template *at;
16561 : : struct mlx5_flow_hw_ctrl_rx_table *tmpls = &hw_ctrl_rx->tables[pti][j];
16562 : 0 : const struct mlx5_flow_template_table_cfg cfg = {
16563 : : .attr = tmpls->attr,
16564 : : .external = 0,
16565 : : };
16566 : :
16567 [ # # ]: 0 : if (!hw_ctrl_rx->rss[rss_type]) {
16568 : 0 : at = flow_hw_create_ctrl_rx_rss_template(dev, rss_type);
16569 [ # # ]: 0 : if (!at)
16570 : 0 : return -rte_errno;
16571 : 0 : hw_ctrl_rx->rss[rss_type] = at;
16572 : : } else {
16573 : 0 : at = hw_ctrl_rx->rss[rss_type];
16574 : : }
16575 [ # # ]: 0 : if (!rss_type_is_requested(priv, rss_type))
16576 : 0 : continue;
16577 [ # # ]: 0 : if (!tmpls->tbl) {
16578 : 0 : tmpls->tbl = flow_hw_table_create(dev, &cfg,
16579 : : &tmpls->pt, 1, &at, 1, NULL);
16580 [ # # ]: 0 : if (!tmpls->tbl) {
16581 : 0 : DRV_LOG(ERR, "port %u Failed to create template table "
16582 : : "for control flow rules. Unable to create "
16583 : : "control flow rules.",
16584 : : dev->data->port_id);
16585 : 0 : return -rte_errno;
16586 : : }
16587 : : }
16588 : :
16589 : : MLX5_ASSERT(eth_pattern_type == MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC ||
16590 : : eth_pattern_type == MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN);
16591 : :
16592 [ # # ]: 0 : if (eth_pattern_type == MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC)
16593 : 0 : ret = __flow_hw_ctrl_flows_unicast_create(dev, tmpls->tbl, rss_type, addr);
16594 : : else
16595 : 0 : ret = __flow_hw_ctrl_flows_unicast_vlan_create(dev, tmpls->tbl, rss_type,
16596 : : addr, vlan);
16597 [ # # ]: 0 : if (ret) {
16598 : 0 : DRV_LOG(ERR, "port %u Failed to create unicast control flow rule.",
16599 : : dev->data->port_id);
16600 : 0 : return ret;
16601 : : }
16602 : : }
16603 : :
16604 : : return 0;
16605 : : }
16606 : :
16607 : : int
16608 : 0 : mlx5_flow_hw_ctrl_flow_dmac(struct rte_eth_dev *dev,
16609 : : const struct rte_ether_addr *addr)
16610 : : {
16611 : 0 : return mlx5_flow_hw_ctrl_flow_single(dev, MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC,
16612 : : addr, 0);
16613 : : }
16614 : :
16615 : :
16616 : : int
16617 : 0 : mlx5_flow_hw_ctrl_flow_dmac_destroy(struct rte_eth_dev *dev,
16618 : : const struct rte_ether_addr *addr)
16619 : : {
16620 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16621 : : struct mlx5_ctrl_flow_entry *entry;
16622 : : struct mlx5_ctrl_flow_entry *tmp;
16623 : : int ret;
16624 : :
16625 : : /*
16626 : : * HWS does not have automatic RSS flow expansion,
16627 : : * so each variant of the control flow rule is a separate entry in the list.
16628 : : * In that case, the whole list must be traversed.
16629 : : */
16630 : 0 : entry = LIST_FIRST(&priv->hw_ctrl_flows);
16631 [ # # ]: 0 : while (entry != NULL) {
16632 : 0 : tmp = LIST_NEXT(entry, next);
16633 : :
16634 [ # # # # ]: 0 : if (entry->info.type != MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC ||
16635 : : !rte_is_same_ether_addr(addr, &entry->info.uc.dmac)) {
16636 : : entry = tmp;
16637 : 0 : continue;
16638 : : }
16639 : :
16640 : 0 : ret = flow_hw_destroy_ctrl_flow(dev, entry->flow);
16641 [ # # ]: 0 : LIST_REMOVE(entry, next);
16642 : 0 : mlx5_free(entry);
16643 [ # # ]: 0 : if (ret)
16644 : 0 : return ret;
16645 : :
16646 : : entry = tmp;
16647 : : }
16648 : : return 0;
16649 : : }
16650 : :
16651 : : int
16652 : 0 : mlx5_flow_hw_ctrl_flow_dmac_vlan(struct rte_eth_dev *dev,
16653 : : const struct rte_ether_addr *addr,
16654 : : const uint16_t vlan)
16655 : : {
16656 : 0 : return mlx5_flow_hw_ctrl_flow_single(dev, MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN,
16657 : : addr, vlan);
16658 : : }
16659 : :
16660 : : int
16661 : 0 : mlx5_flow_hw_ctrl_flow_dmac_vlan_destroy(struct rte_eth_dev *dev,
16662 : : const struct rte_ether_addr *addr,
16663 : : const uint16_t vlan)
16664 : : {
16665 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16666 : : struct mlx5_ctrl_flow_entry *entry;
16667 : : struct mlx5_ctrl_flow_entry *tmp;
16668 : : int ret;
16669 : :
16670 : : /*
16671 : : * HWS does not have automatic RSS flow expansion,
16672 : : * so each variant of the control flow rule is a separate entry in the list.
16673 : : * In that case, the whole list must be traversed.
16674 : : */
16675 : 0 : entry = LIST_FIRST(&priv->hw_ctrl_flows);
16676 [ # # ]: 0 : while (entry != NULL) {
16677 : 0 : tmp = LIST_NEXT(entry, next);
16678 : :
16679 [ # # # # ]: 0 : if (entry->info.type != MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC_VLAN ||
16680 : 0 : !rte_is_same_ether_addr(addr, &entry->info.uc.dmac) ||
16681 [ # # ]: 0 : vlan != entry->info.uc.vlan) {
16682 : : entry = tmp;
16683 : 0 : continue;
16684 : : }
16685 : :
16686 : 0 : ret = flow_hw_destroy_ctrl_flow(dev, entry->flow);
16687 [ # # ]: 0 : LIST_REMOVE(entry, next);
16688 : 0 : mlx5_free(entry);
16689 [ # # ]: 0 : if (ret)
16690 : 0 : return ret;
16691 : :
16692 : : entry = tmp;
16693 : : }
16694 : : return 0;
16695 : : }
16696 : :
16697 : : struct mlx5_ecpri_parser_profile *
16698 : 0 : flow_hw_get_ecpri_parser_profile(void *dr_ctx)
16699 : : {
16700 : : uint16_t port_id;
16701 : : bool found = false;
16702 : : struct mlx5_priv *priv;
16703 : :
16704 [ # # ]: 0 : MLX5_ETH_FOREACH_DEV(port_id, NULL) {
16705 : 0 : priv = rte_eth_devices[port_id].data->dev_private;
16706 [ # # ]: 0 : if (priv->dr_ctx == dr_ctx) {
16707 : : found = true;
16708 : : break;
16709 : : }
16710 : : }
16711 [ # # ]: 0 : if (found)
16712 : 0 : return &priv->sh->ecpri_parser;
16713 : 0 : rte_errno = ENODEV;
16714 : 0 : return NULL;
16715 : : }
16716 : :
16717 : :
16718 : : static __rte_always_inline uint32_t
16719 : : mlx5_reformat_domain_to_tbl_type(const struct rte_flow_indir_action_conf *domain,
16720 : : bool fdb_unified_en)
16721 : : {
16722 : : uint32_t tbl_type;
16723 : :
16724 [ # # ]: 0 : if (domain->transfer)
16725 : : tbl_type = (fdb_unified_en ?
16726 : : (MLX5DR_ACTION_FLAG_HWS_FDB_RX |
16727 : : MLX5DR_ACTION_FLAG_HWS_FDB_TX |
16728 [ # # ]: 0 : MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED) :
16729 : : MLX5DR_ACTION_FLAG_HWS_FDB);
16730 [ # # ]: 0 : else if (domain->egress)
16731 : : tbl_type = MLX5DR_ACTION_FLAG_HWS_TX;
16732 [ # # ]: 0 : else if (domain->ingress)
16733 : : tbl_type = MLX5DR_ACTION_FLAG_HWS_RX;
16734 : : else
16735 : : tbl_type = UINT32_MAX;
16736 : : return tbl_type;
16737 : : }
16738 : :
16739 : : static struct mlx5_hw_encap_decap_action *
16740 : 0 : __mlx5_reformat_create(struct rte_eth_dev *dev,
16741 : : const struct rte_flow_action_raw_encap *encap_conf,
16742 : : const struct rte_flow_indir_action_conf *domain,
16743 : : enum mlx5dr_action_type type)
16744 : : {
16745 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
16746 : : struct mlx5_hw_encap_decap_action *handle;
16747 : : struct mlx5dr_action_reformat_header hdr;
16748 : : uint32_t flags;
16749 : : bool unified_fdb = is_unified_fdb(priv);
16750 : :
16751 : : flags = mlx5_reformat_domain_to_tbl_type(domain, unified_fdb);
16752 : 0 : flags |= (uint32_t)MLX5DR_ACTION_FLAG_SHARED;
16753 [ # # ]: 0 : if (flags == UINT32_MAX) {
16754 : 0 : DRV_LOG(ERR, "Reformat: invalid indirect action configuration");
16755 : 0 : return NULL;
16756 : : }
16757 : : /* Allocate new list entry. */
16758 : 0 : handle = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*handle), 0, SOCKET_ID_ANY);
16759 [ # # ]: 0 : if (!handle) {
16760 : 0 : DRV_LOG(ERR, "Reformat: failed to allocate reformat entry");
16761 : 0 : return NULL;
16762 : : }
16763 : 0 : handle->action_type = type;
16764 [ # # ]: 0 : hdr.sz = encap_conf ? encap_conf->size : 0;
16765 [ # # ]: 0 : hdr.data = encap_conf ? encap_conf->data : NULL;
16766 : 0 : handle->action = mlx5dr_action_create_reformat(priv->dr_ctx,
16767 : : type, 1, &hdr, 0, flags);
16768 [ # # ]: 0 : if (!handle->action) {
16769 : 0 : DRV_LOG(ERR, "Reformat: failed to create reformat action");
16770 : 0 : mlx5_free(handle);
16771 : 0 : return NULL;
16772 : : }
16773 : : return handle;
16774 : : }
16775 : :
16776 : : /**
16777 : : * Create mlx5 reformat action.
16778 : : *
16779 : : * @param[in] dev
16780 : : * Pointer to rte_eth_dev structure.
16781 : : * @param[in] conf
16782 : : * Pointer to the indirect action parameters.
16783 : : * @param[in] encap_action
16784 : : * Pointer to the raw_encap action configuration.
16785 : : * @param[in] decap_action
16786 : : * Pointer to the raw_decap action configuration.
16787 : : * @param[out] error
16788 : : * Pointer to error structure.
16789 : : *
16790 : : * @return
16791 : : * A valid shared action handle in case of success, NULL otherwise and
16792 : : * rte_errno is set.
16793 : : */
16794 : : struct mlx5_hw_encap_decap_action*
16795 : 0 : mlx5_reformat_action_create(struct rte_eth_dev *dev,
16796 : : const struct rte_flow_indir_action_conf *conf,
16797 : : const struct rte_flow_action *encap_action,
16798 : : const struct rte_flow_action *decap_action,
16799 : : struct rte_flow_error *error)
16800 : : {
16801 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16802 : : struct mlx5_hw_encap_decap_action *handle;
16803 : : const struct rte_flow_action_raw_encap *encap = NULL;
16804 : : const struct rte_flow_action_raw_decap *decap = NULL;
16805 : : enum mlx5dr_action_type type = MLX5DR_ACTION_TYP_LAST;
16806 : :
16807 : : MLX5_ASSERT(!encap_action || encap_action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP);
16808 : : MLX5_ASSERT(!decap_action || decap_action->type == RTE_FLOW_ACTION_TYPE_RAW_DECAP);
16809 [ # # ]: 0 : if (priv->sh->config.dv_flow_en != 2) {
16810 : 0 : rte_flow_error_set(error, ENOTSUP,
16811 : : RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
16812 : : "Reformat: hardware does not support");
16813 : 0 : return NULL;
16814 : : }
16815 [ # # # # ]: 0 : if (!conf || (conf->transfer + conf->egress + conf->ingress != 1)) {
16816 : 0 : rte_flow_error_set(error, EINVAL,
16817 : : RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
16818 : : "Reformat: domain should be specified");
16819 : 0 : return NULL;
16820 : : }
16821 [ # # # # : 0 : if ((encap_action && !encap_action->conf) || (decap_action && !decap_action->conf)) {
# # # # ]
16822 : 0 : rte_flow_error_set(error, EINVAL,
16823 : : RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
16824 : : "Reformat: missed action configuration");
16825 : 0 : return NULL;
16826 : : }
16827 [ # # ]: 0 : if (encap_action && !decap_action) {
16828 : 0 : encap = (const struct rte_flow_action_raw_encap *)encap_action->conf;
16829 [ # # ]: 0 : if (!encap->size || encap->size > MLX5_ENCAP_MAX_LEN ||
16830 : : encap->size < MLX5_ENCAPSULATION_DECISION_SIZE) {
16831 : 0 : rte_flow_error_set(error, EINVAL,
16832 : : RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
16833 : : "Reformat: Invalid encap length");
16834 : 0 : return NULL;
16835 : : }
16836 : : type = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;
16837 [ # # ]: 0 : } else if (decap_action && !encap_action) {
16838 : 0 : decap = (const struct rte_flow_action_raw_decap *)decap_action->conf;
16839 [ # # ]: 0 : if (!decap->size || decap->size < MLX5_ENCAPSULATION_DECISION_SIZE) {
16840 : 0 : rte_flow_error_set(error, EINVAL,
16841 : : RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
16842 : : "Reformat: Invalid decap length");
16843 : 0 : return NULL;
16844 : : }
16845 : : type = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2;
16846 [ # # ]: 0 : } else if (encap_action && decap_action) {
16847 : 0 : decap = (const struct rte_flow_action_raw_decap *)decap_action->conf;
16848 : 0 : encap = (const struct rte_flow_action_raw_encap *)encap_action->conf;
16849 [ # # ]: 0 : if (decap->size < MLX5_ENCAPSULATION_DECISION_SIZE &&
16850 [ # # # # ]: 0 : encap->size >= MLX5_ENCAPSULATION_DECISION_SIZE &&
16851 : : encap->size <= MLX5_ENCAP_MAX_LEN) {
16852 : : type = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3;
16853 [ # # ]: 0 : } else if (decap->size >= MLX5_ENCAPSULATION_DECISION_SIZE &&
16854 [ # # ]: 0 : encap->size < MLX5_ENCAPSULATION_DECISION_SIZE) {
16855 : : type = MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2;
16856 : : } else {
16857 : 0 : rte_flow_error_set(error, EINVAL,
16858 : : RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
16859 : : "Reformat: Invalid decap & encap length");
16860 : 0 : return NULL;
16861 : : }
16862 [ # # ]: 0 : } else if (!encap_action && !decap_action) {
16863 : 0 : rte_flow_error_set(error, EINVAL,
16864 : : RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
16865 : : "Reformat: Invalid decap & encap configurations");
16866 : 0 : return NULL;
16867 : : }
16868 [ # # ]: 0 : if (!priv->dr_ctx) {
16869 : 0 : rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
16870 : : encap_action, "Reformat: HWS not supported");
16871 : 0 : return NULL;
16872 : : }
16873 : 0 : handle = __mlx5_reformat_create(dev, encap, conf, type);
16874 [ # # ]: 0 : if (!handle) {
16875 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
16876 : : "Reformat: failed to create indirect action");
16877 : 0 : return NULL;
16878 : : }
16879 : : return handle;
16880 : : }
16881 : :
16882 : : /**
16883 : : * Destroy the indirect reformat action.
16884 : : * Release action related resources on the NIC and the memory.
16885 : : * Lock free, (mutex should be acquired by caller).
16886 : : *
16887 : : * @param[in] dev
16888 : : * Pointer to the Ethernet device structure.
16889 : : * @param[in] handle
16890 : : * The indirect action list handle to be removed.
16891 : : * @param[out] error
16892 : : * Perform verbose error reporting if not NULL. Initialized in case of
16893 : : * error only.
16894 : : *
16895 : : * @return
16896 : : * 0 on success, otherwise negative errno value.
16897 : : */
16898 : : int
16899 : 0 : mlx5_reformat_action_destroy(struct rte_eth_dev *dev,
16900 : : struct rte_flow_action_list_handle *handle,
16901 : : struct rte_flow_error *error)
16902 : : {
16903 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16904 : : struct mlx5_hw_encap_decap_action *action;
16905 : :
16906 : : action = (struct mlx5_hw_encap_decap_action *)handle;
16907 [ # # # # ]: 0 : if (!priv->dr_ctx || !action)
16908 : 0 : return rte_flow_error_set(error, ENOTSUP,
16909 : : RTE_FLOW_ERROR_TYPE_ACTION, handle,
16910 : : "Reformat: invalid action handle");
16911 : 0 : mlx5dr_action_destroy(action->action);
16912 : 0 : mlx5_free(handle);
16913 : 0 : return 0;
16914 : : }
16915 : :
16916 : : static bool
16917 : 0 : flow_hw_is_item_masked(const struct rte_flow_item *item)
16918 : : {
16919 : : const uint8_t *byte;
16920 : : int size;
16921 : : int i;
16922 : :
16923 [ # # ]: 0 : if (item->mask == NULL)
16924 : : return false;
16925 : :
16926 [ # # ]: 0 : switch ((int)item->type) {
16927 : : case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
16928 : : size = sizeof(struct rte_flow_item_tag);
16929 : : break;
16930 : : case MLX5_RTE_FLOW_ITEM_TYPE_SQ:
16931 : : size = sizeof(struct mlx5_rte_flow_item_sq);
16932 : : break;
16933 : 0 : default:
16934 : 0 : size = rte_flow_conv(RTE_FLOW_CONV_OP_ITEM_MASK, NULL, 0, item, NULL);
16935 : : /*
16936 : : * Pattern template items are passed to this function.
16937 : : * These items were already validated, so error is not expected.
16938 : : * Also, if mask is NULL, then spec size is bigger than 0 always.
16939 : : */
16940 : : MLX5_ASSERT(size > 0);
16941 : : }
16942 : :
16943 : 0 : byte = (const uint8_t *)item->mask;
16944 [ # # ]: 0 : for (i = 0; i < size; ++i)
16945 [ # # ]: 0 : if (byte[i])
16946 : : return true;
16947 : :
16948 : : return false;
16949 : : }
16950 : :
16951 : : static int
16952 : 0 : flow_hw_validate_rule_pattern(struct rte_eth_dev *dev,
16953 : : const struct rte_flow_template_table *table,
16954 : : const uint8_t pattern_template_idx,
16955 : : const struct rte_flow_item items[],
16956 : : struct rte_flow_error *error)
16957 : : {
16958 : : const struct rte_flow_pattern_template *pt;
16959 : : const struct rte_flow_item *pt_item;
16960 : :
16961 [ # # ]: 0 : if (pattern_template_idx >= table->nb_item_templates)
16962 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
16963 : : "Pattern template index out of range");
16964 : :
16965 : 0 : pt = table->its[pattern_template_idx];
16966 : 0 : pt_item = pt->items;
16967 : :
16968 : : /* If any item was prepended, skip it. */
16969 [ # # ]: 0 : if (pt->implicit_port || pt->implicit_tag)
16970 : 0 : pt_item++;
16971 : :
16972 [ # # ]: 0 : for (; pt_item->type != RTE_FLOW_ITEM_TYPE_END; pt_item++, items++) {
16973 [ # # ]: 0 : if (pt_item->type != items->type)
16974 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM,
16975 : : items, "Item type does not match the template");
16976 : :
16977 : : /*
16978 : : * Assumptions:
16979 : : * - Currently mlx5dr layer contains info on which fields in masks are supported.
16980 : : * - This info is not exposed to PMD directly.
16981 : : * - Because of that, it is assumed that since pattern template is correct,
16982 : : * then, items' masks in pattern template have nonzero values only in
16983 : : * supported fields.
16984 : : * This is known, because a temporary mlx5dr matcher is created during pattern
16985 : : * template creation to validate the template.
16986 : : * - As a result, it is safe to look for nonzero bytes in mask to determine if
16987 : : * item spec is needed in a flow rule.
16988 : : */
16989 [ # # ]: 0 : if (!flow_hw_is_item_masked(pt_item))
16990 : 0 : continue;
16991 : :
16992 [ # # ]: 0 : if (items->spec == NULL)
16993 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
16994 : : items, "Item spec is required");
16995 : :
16996 [ # # # ]: 0 : switch (items->type) {
16997 : : const struct rte_flow_item_ethdev *ethdev;
16998 : : const struct rte_flow_item_tx_queue *tx_queue;
16999 : : struct mlx5_txq_ctrl *txq;
17000 : :
17001 : 0 : case RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT:
17002 : : ethdev = items->spec;
17003 [ # # ]: 0 : if (flow_hw_validate_target_port_id(dev, ethdev->port_id)) {
17004 : 0 : return rte_flow_error_set(error, EINVAL,
17005 : : RTE_FLOW_ERROR_TYPE_ITEM_SPEC, items,
17006 : : "Invalid port");
17007 : : }
17008 : : break;
17009 : 0 : case RTE_FLOW_ITEM_TYPE_TX_QUEUE:
17010 : : tx_queue = items->spec;
17011 [ # # # # ]: 0 : if (mlx5_is_external_txq(dev, tx_queue->tx_queue))
17012 : 0 : continue;
17013 : 0 : txq = mlx5_txq_get(dev, tx_queue->tx_queue);
17014 [ # # ]: 0 : if (!txq)
17015 : 0 : return rte_flow_error_set(error, EINVAL,
17016 : : RTE_FLOW_ERROR_TYPE_ITEM_SPEC, items,
17017 : : "Invalid Tx queue");
17018 : 0 : mlx5_txq_release(dev, tx_queue->tx_queue);
17019 : : default:
17020 : : break;
17021 : : }
17022 : : }
17023 : :
17024 : : return 0;
17025 : : }
17026 : :
17027 : : static bool
17028 : 0 : flow_hw_valid_indirect_action_type(const struct rte_flow_action *user_action,
17029 : : const enum rte_flow_action_type expected_type)
17030 : : {
17031 : 0 : uint32_t user_indirect_type = MLX5_INDIRECT_ACTION_TYPE_GET(user_action->conf);
17032 : : uint32_t expected_indirect_type;
17033 : :
17034 [ # # # # : 0 : switch ((int)expected_type) {
# # # ]
17035 : : case RTE_FLOW_ACTION_TYPE_RSS:
17036 : : case MLX5_RTE_FLOW_ACTION_TYPE_RSS:
17037 : : expected_indirect_type = MLX5_INDIRECT_ACTION_TYPE_RSS;
17038 : : break;
17039 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
17040 : : case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
17041 : : expected_indirect_type = MLX5_INDIRECT_ACTION_TYPE_COUNT;
17042 : 0 : break;
17043 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
17044 : : expected_indirect_type = MLX5_INDIRECT_ACTION_TYPE_AGE;
17045 : 0 : break;
17046 : 0 : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
17047 : : expected_indirect_type = MLX5_INDIRECT_ACTION_TYPE_CT;
17048 : 0 : break;
17049 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
17050 : : case MLX5_RTE_FLOW_ACTION_TYPE_METER_MARK:
17051 : : expected_indirect_type = MLX5_INDIRECT_ACTION_TYPE_METER_MARK;
17052 : 0 : break;
17053 : 0 : case RTE_FLOW_ACTION_TYPE_QUOTA:
17054 : : expected_indirect_type = MLX5_INDIRECT_ACTION_TYPE_QUOTA;
17055 : 0 : break;
17056 : : default:
17057 : : return false;
17058 : : }
17059 : :
17060 : 0 : return user_indirect_type == expected_indirect_type;
17061 : : }
17062 : :
17063 : : static int
17064 : 0 : flow_hw_validate_rule_actions(struct rte_eth_dev *dev,
17065 : : const struct rte_flow_template_table *table,
17066 : : const uint8_t actions_template_idx,
17067 : : const struct rte_flow_action actions[],
17068 : : struct rte_flow_error *error)
17069 : : {
17070 : : const struct rte_flow_actions_template *at;
17071 : : const struct mlx5_hw_actions *hw_acts;
17072 : : const struct mlx5_action_construct_data *act_data;
17073 : : unsigned int idx;
17074 : :
17075 [ # # ]: 0 : if (actions_template_idx >= table->nb_action_templates)
17076 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17077 : : "Actions template index out of range");
17078 : :
17079 : 0 : at = table->ats[actions_template_idx].action_template;
17080 : : hw_acts = &table->ats[actions_template_idx].acts;
17081 : :
17082 [ # # ]: 0 : for (idx = 0; actions[idx].type != RTE_FLOW_ACTION_TYPE_END; ++idx) {
17083 : : const struct rte_flow_action *user_action = &actions[idx];
17084 : 0 : const struct rte_flow_action *tmpl_action = &at->orig_actions[idx];
17085 : :
17086 [ # # ]: 0 : if (user_action->type != tmpl_action->type)
17087 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
17088 : : user_action,
17089 : : "Action type does not match type specified in "
17090 : : "actions template");
17091 : : }
17092 : :
17093 : : /*
17094 : : * Only go through unmasked actions and check if configuration is provided.
17095 : : * Configuration of masked actions is ignored.
17096 : : */
17097 [ # # ]: 0 : LIST_FOREACH(act_data, &hw_acts->act_list, next) {
17098 : : const struct rte_flow_action *user_action;
17099 : :
17100 : 0 : user_action = &actions[act_data->action_src];
17101 : :
17102 : : /* Skip actions which do not require conf. */
17103 [ # # ]: 0 : switch ((int)act_data->type) {
17104 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
17105 : : case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
17106 : : case MLX5_RTE_FLOW_ACTION_TYPE_METER_MARK:
17107 : : case MLX5_RTE_FLOW_ACTION_TYPE_RSS:
17108 : 0 : continue;
17109 : : default:
17110 : : break;
17111 : : }
17112 : :
17113 [ # # ]: 0 : if (user_action->conf == NULL)
17114 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
17115 : : user_action,
17116 : : "Action requires configuration");
17117 : :
17118 [ # # # # : 0 : switch ((int)user_action->type) {
# # ]
17119 : : enum rte_flow_action_type expected_type;
17120 : : const struct rte_flow_action_ethdev *ethdev;
17121 : : const struct rte_flow_action_modify_field *mf;
17122 : :
17123 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT:
17124 : 0 : expected_type = act_data->indirect.expected_type;
17125 [ # # ]: 0 : if (!flow_hw_valid_indirect_action_type(user_action, expected_type))
17126 : 0 : return rte_flow_error_set(error, EINVAL,
17127 : : RTE_FLOW_ERROR_TYPE_ACTION_CONF,
17128 : : user_action,
17129 : : "Indirect action type does not match "
17130 : : "the type specified in the mask");
17131 : : break;
17132 : 0 : case RTE_FLOW_ACTION_TYPE_QUEUE:
17133 [ # # ]: 0 : if (mlx5_flow_validate_target_queue(dev, user_action, error))
17134 : 0 : return -rte_errno;
17135 : : break;
17136 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
17137 [ # # ]: 0 : if (mlx5_validate_action_rss(dev, user_action, error))
17138 : 0 : return -rte_errno;
17139 : : break;
17140 : 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
17141 : : /* TODO: Compare other fields if needed. */
17142 : : mf = user_action->conf;
17143 [ # # ]: 0 : if (mf->operation != act_data->modify_header.action.operation ||
17144 [ # # ]: 0 : mf->src.field != act_data->modify_header.action.src.field ||
17145 [ # # ]: 0 : mf->dst.field != act_data->modify_header.action.dst.field ||
17146 [ # # ]: 0 : mf->width != act_data->modify_header.action.width)
17147 : 0 : return rte_flow_error_set(error, EINVAL,
17148 : : RTE_FLOW_ERROR_TYPE_ACTION_CONF,
17149 : : user_action,
17150 : : "Modify field configuration does not "
17151 : : "match configuration from actions "
17152 : : "template");
17153 : : break;
17154 : 0 : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
17155 : : ethdev = user_action->conf;
17156 [ # # ]: 0 : if (flow_hw_validate_target_port_id(dev, ethdev->port_id)) {
17157 : 0 : return rte_flow_error_set(error, EINVAL,
17158 : : RTE_FLOW_ERROR_TYPE_ACTION_CONF,
17159 : : user_action, "Invalid port");
17160 : : }
17161 : : break;
17162 : : default:
17163 : : break;
17164 : : }
17165 : : }
17166 : :
17167 : : return 0;
17168 : : }
17169 : :
17170 : : static int
17171 : 0 : flow_hw_async_op_validate(struct rte_eth_dev *dev,
17172 : : const uint32_t queue,
17173 : : const struct rte_flow_template_table *table,
17174 : : struct rte_flow_error *error)
17175 : : {
17176 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
17177 : :
17178 : : MLX5_ASSERT(table != NULL);
17179 : :
17180 [ # # # # ]: 0 : if (table->cfg.external && queue >= priv->hw_attr->nb_queue)
17181 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17182 : : "Incorrect queue");
17183 : :
17184 : : return 0;
17185 : : }
17186 : :
17187 : : /**
17188 : : * Validate user input for rte_flow_async_create() implementation.
17189 : : *
17190 : : * If RTE_LIBRTE_MLX5_DEBUG macro is not defined, this function is a no-op.
17191 : : *
17192 : : * @param[in] dev
17193 : : * Pointer to the rte_eth_dev structure.
17194 : : * @param[in] queue
17195 : : * The queue to create the flow.
17196 : : * @param[in] table
17197 : : * Pointer to template table.
17198 : : * @param[in] rule_index
17199 : : * The item pattern flow follows from the table.
17200 : : * @param[in] items
17201 : : * Items with flow spec value.
17202 : : * @param[in] pattern_template_index
17203 : : * The item pattern flow follows from the table.
17204 : : * @param[in] actions
17205 : : * Action with flow spec value.
17206 : : * @param[in] action_template_index
17207 : : * The action pattern flow follows from the table.
17208 : : * @param[out] error
17209 : : * Pointer to error structure.
17210 : : *
17211 : : * @return
17212 : : * 0 if user input is valid.
17213 : : * Negative errno otherwise, rte_errno and error struct is populated.
17214 : : */
17215 : : static int
17216 : 0 : flow_hw_async_create_validate(struct rte_eth_dev *dev,
17217 : : const uint32_t queue,
17218 : : const struct rte_flow_template_table *table,
17219 : : enum rte_flow_table_insertion_type insertion_type,
17220 : : uint32_t rule_index,
17221 : : const struct rte_flow_item items[],
17222 : : const uint8_t pattern_template_index,
17223 : : const struct rte_flow_action actions[],
17224 : : const uint8_t action_template_index,
17225 : : struct rte_flow_error *error)
17226 : : {
17227 [ # # ]: 0 : if (flow_hw_async_op_validate(dev, queue, table, error))
17228 : 0 : return -rte_errno;
17229 : :
17230 [ # # ]: 0 : if (insertion_type != table->cfg.attr.insertion_type)
17231 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
17232 : : NULL, "Flow rule insertion type mismatch with table configuration");
17233 : :
17234 [ # # ]: 0 : if (table->cfg.attr.insertion_type != RTE_FLOW_TABLE_INSERTION_TYPE_PATTERN)
17235 [ # # ]: 0 : if (rule_index >= table->cfg.attr.nb_flows)
17236 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
17237 : : NULL, "Flow rule index exceeds table size");
17238 : :
17239 [ # # ]: 0 : if (table->cfg.attr.insertion_type != RTE_FLOW_TABLE_INSERTION_TYPE_INDEX)
17240 [ # # ]: 0 : if (flow_hw_validate_rule_pattern(dev, table, pattern_template_index, items, error))
17241 : 0 : return -rte_errno;
17242 : :
17243 [ # # ]: 0 : if (flow_hw_validate_rule_actions(dev, table, action_template_index, actions, error))
17244 : 0 : return -rte_errno;
17245 : :
17246 : : return 0;
17247 : : }
17248 : :
17249 : : /**
17250 : : * Validate user input for rte_flow_async_update() implementation.
17251 : : *
17252 : : * If RTE_LIBRTE_MLX5_DEBUG macro is not defined, this function is a no-op.
17253 : : *
17254 : : * @param[in] dev
17255 : : * Pointer to the rte_eth_dev structure.
17256 : : * @param[in] queue
17257 : : * The queue to create the flow.
17258 : : * @param[in] flow
17259 : : * Flow rule to be updated.
17260 : : * @param[in] actions
17261 : : * Action with flow spec value.
17262 : : * @param[in] action_template_index
17263 : : * The action pattern flow follows from the table.
17264 : : * @param[out] error
17265 : : * Pointer to error structure.
17266 : : *
17267 : : * @return
17268 : : * 0 if user input is valid.
17269 : : * Negative errno otherwise, rte_errno and error struct is set.
17270 : : */
17271 : : static int
17272 : 0 : flow_hw_async_update_validate(struct rte_eth_dev *dev,
17273 : : const uint32_t queue,
17274 : : const struct rte_flow_hw *flow,
17275 : : const struct rte_flow_action actions[],
17276 : : const uint8_t action_template_index,
17277 : : struct rte_flow_error *error)
17278 : : {
17279 [ # # ]: 0 : if (flow_hw_async_op_validate(dev, queue, flow->table, error))
17280 : 0 : return -rte_errno;
17281 : :
17282 [ # # ]: 0 : if (flow_hw_validate_rule_actions(dev, flow->table, action_template_index, actions, error))
17283 : 0 : return -rte_errno;
17284 : :
17285 : : return 0;
17286 : : }
17287 : :
17288 : : /**
17289 : : * Validate user input for rte_flow_async_destroy() implementation.
17290 : : *
17291 : : * If RTE_LIBRTE_MLX5_DEBUG macro is not defined, this function is a no-op.
17292 : : *
17293 : : * @param[in] dev
17294 : : * Pointer to the rte_eth_dev structure.
17295 : : * @param[in] queue
17296 : : * The queue to create the flow.
17297 : : * @param[in] flow
17298 : : * Flow rule to be destroyed.
17299 : : * @param[out] error
17300 : : * Pointer to error structure.
17301 : : *
17302 : : * @return
17303 : : * 0 if user input is valid.
17304 : : * Negative errno otherwise, rte_errno and error struct is set.
17305 : : */
17306 : : static int
17307 : : flow_hw_async_destroy_validate(struct rte_eth_dev *dev,
17308 : : const uint32_t queue,
17309 : : const struct rte_flow_hw *flow,
17310 : : struct rte_flow_error *error)
17311 : : {
17312 : : if (flow_hw_async_op_validate(dev, queue, flow->table, error))
17313 : : return -rte_errno;
17314 : :
17315 : : return 0;
17316 : : }
17317 : :
17318 : : static struct rte_flow_fp_ops mlx5_flow_hw_fp_ops = {
17319 : : .async_create = flow_hw_async_flow_create,
17320 : : .async_create_by_index = flow_hw_async_flow_create_by_index,
17321 : : .async_create_by_index_with_pattern = flow_hw_async_flow_create_by_index_with_pattern,
17322 : : .async_actions_update = flow_hw_async_flow_update,
17323 : : .async_destroy = flow_hw_async_flow_destroy,
17324 : : .push = flow_hw_push,
17325 : : .pull = flow_hw_pull,
17326 : : .async_action_handle_create = flow_hw_action_handle_create,
17327 : : .async_action_handle_destroy = flow_hw_action_handle_destroy,
17328 : : .async_action_handle_update = flow_hw_action_handle_update,
17329 : : .async_action_handle_query = flow_hw_action_handle_query,
17330 : : .async_action_handle_query_update = flow_hw_async_action_handle_query_update,
17331 : : .async_action_list_handle_create = flow_hw_async_action_list_handle_create,
17332 : : .async_action_list_handle_destroy = flow_hw_async_action_list_handle_destroy,
17333 : : .async_action_list_handle_query_update =
17334 : : flow_hw_async_action_list_handle_query_update,
17335 : : };
17336 : :
17337 : : #endif
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