Branch data Line data Source code
1 : : /* SPDX-License-Identifier: BSD-3-Clause
2 : : * Copyright (c) 2022 NVIDIA Corporation & Affiliates
3 : : */
4 : :
5 : : #include <rte_flow.h>
6 : : #include <rte_flow_driver.h>
7 : : #include <rte_stdatomic.h>
8 : :
9 : : #include <mlx5_malloc.h>
10 : :
11 : : #include "mlx5.h"
12 : : #include "mlx5_common.h"
13 : : #include "mlx5_defs.h"
14 : : #include "mlx5_flow.h"
15 : : #include "mlx5_flow_os.h"
16 : : #include "mlx5_rx.h"
17 : :
18 : : #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
19 : : #include "mlx5_hws_cnt.h"
20 : :
21 : : /** Fast path async flow API functions. */
22 : : static struct rte_flow_fp_ops mlx5_flow_hw_fp_ops;
23 : :
24 : : /*
25 : : * The default ipool threshold value indicates which per_core_cache
26 : : * value to set.
27 : : */
28 : : #define MLX5_HW_IPOOL_SIZE_THRESHOLD (1 << 19)
29 : : /* The default min local cache size. */
30 : : #define MLX5_HW_IPOOL_CACHE_MIN (1 << 9)
31 : :
32 : : /* Default push burst threshold. */
33 : : #define BURST_THR 32u
34 : :
35 : : /* Default queue to flush the flows. */
36 : : #define MLX5_DEFAULT_FLUSH_QUEUE 0
37 : :
38 : : /* Maximum number of rules in control flow tables. */
39 : : #define MLX5_HW_CTRL_FLOW_NB_RULES (4096)
40 : :
41 : : /* Lowest flow group usable by an application if group translation is done. */
42 : : #define MLX5_HW_LOWEST_USABLE_GROUP (1)
43 : :
44 : : /* Maximum group index usable by user applications for transfer flows. */
45 : : #define MLX5_HW_MAX_TRANSFER_GROUP (UINT32_MAX - 1)
46 : :
47 : : /* Maximum group index usable by user applications for egress flows. */
48 : : #define MLX5_HW_MAX_EGRESS_GROUP (UINT32_MAX - 1)
49 : :
50 : : /* Lowest priority for HW root table. */
51 : : #define MLX5_HW_LOWEST_PRIO_ROOT 15
52 : :
53 : : /* Lowest priority for HW non-root table. */
54 : : #define MLX5_HW_LOWEST_PRIO_NON_ROOT (UINT32_MAX)
55 : :
56 : : /* Priorities for Rx control flow rules. */
57 : : #define MLX5_HW_CTRL_RX_PRIO_L2 (MLX5_HW_LOWEST_PRIO_ROOT)
58 : : #define MLX5_HW_CTRL_RX_PRIO_L3 (MLX5_HW_LOWEST_PRIO_ROOT - 1)
59 : : #define MLX5_HW_CTRL_RX_PRIO_L4 (MLX5_HW_LOWEST_PRIO_ROOT - 2)
60 : :
61 : : #define MLX5_HW_VLAN_PUSH_TYPE_IDX 0
62 : : #define MLX5_HW_VLAN_PUSH_VID_IDX 1
63 : : #define MLX5_HW_VLAN_PUSH_PCP_IDX 2
64 : :
65 : : #define MLX5_MIRROR_MAX_CLONES_NUM 3
66 : : #define MLX5_MIRROR_MAX_SAMPLE_ACTIONS_LEN 4
67 : :
68 : : #define MLX5_HW_PORT_IS_PROXY(priv) \
69 : : (!!((priv)->sh->esw_mode && (priv)->master))
70 : :
71 : :
72 : : struct mlx5_indlst_legacy {
73 : : struct mlx5_indirect_list indirect;
74 : : struct rte_flow_action_handle *handle;
75 : : enum rte_flow_action_type legacy_type;
76 : : };
77 : :
78 : : #define MLX5_CONST_ENCAP_ITEM(encap_type, ptr) \
79 : : (((const struct encap_type *)(ptr))->definition)
80 : :
81 : : /**
82 : : * Returns the size of a struct with a following layout:
83 : : *
84 : : * @code{.c}
85 : : * struct rte_flow_hw {
86 : : * // rte_flow_hw fields
87 : : * uint8_t rule[mlx5dr_rule_get_handle_size()];
88 : : * };
89 : : * @endcode
90 : : *
91 : : * Such struct is used as a basic container for HW Steering flow rule.
92 : : */
93 : : static size_t
94 : : mlx5_flow_hw_entry_size(void)
95 : : {
96 : 0 : return sizeof(struct rte_flow_hw) + mlx5dr_rule_get_handle_size();
97 : : }
98 : :
99 : : /**
100 : : * Returns the size of "auxed" rte_flow_hw structure which is assumed to be laid out as follows:
101 : : *
102 : : * @code{.c}
103 : : * struct {
104 : : * struct rte_flow_hw {
105 : : * // rte_flow_hw fields
106 : : * uint8_t rule[mlx5dr_rule_get_handle_size()];
107 : : * } flow;
108 : : * struct rte_flow_hw_aux aux;
109 : : * };
110 : : * @endcode
111 : : *
112 : : * Such struct is used whenever rte_flow_hw_aux cannot be allocated separately from the rte_flow_hw
113 : : * e.g., when table is resizable.
114 : : */
115 : : static size_t
116 : : mlx5_flow_hw_auxed_entry_size(void)
117 : : {
118 : 0 : size_t rule_size = mlx5dr_rule_get_handle_size();
119 : :
120 : 0 : return sizeof(struct rte_flow_hw) + rule_size + sizeof(struct rte_flow_hw_aux);
121 : : }
122 : :
123 : : /**
124 : : * Returns a valid pointer to rte_flow_hw_aux associated with given rte_flow_hw
125 : : * depending on template table configuration.
126 : : */
127 : : static __rte_always_inline struct rte_flow_hw_aux *
128 : : mlx5_flow_hw_aux(uint16_t port_id, struct rte_flow_hw *flow)
129 : : {
130 : 0 : struct rte_flow_template_table *table = flow->table;
131 : :
132 [ # # # # : 0 : if (rte_flow_template_table_resizable(port_id, &table->cfg.attr)) {
# # # # #
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# ]
133 : 0 : size_t offset = sizeof(struct rte_flow_hw) + mlx5dr_rule_get_handle_size();
134 : :
135 : 0 : return RTE_PTR_ADD(flow, offset);
136 : : } else {
137 [ # # # # : 0 : return ((flow->nt_rule) ? flow->nt2hws->flow_aux : &table->flow_aux[flow->idx - 1]);
# # # # #
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# ]
138 : : }
139 : : }
140 : :
141 : : static __rte_always_inline void
142 : : mlx5_flow_hw_aux_set_age_idx(struct rte_flow_hw *flow,
143 : : struct rte_flow_hw_aux *aux,
144 : : uint32_t age_idx)
145 : : {
146 : : /*
147 : : * Only when creating a flow rule, the type will be set explicitly.
148 : : * Or else, it should be none in the rule update case.
149 : : */
150 [ # # # # : 0 : if (unlikely(flow->operation_type == MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE))
# # # # #
# # # # #
# # # # #
# ]
151 : 0 : aux->upd.age_idx = age_idx;
152 : : else
153 : 0 : aux->orig.age_idx = age_idx;
154 : : }
155 : :
156 : : static __rte_always_inline uint32_t
157 : : mlx5_flow_hw_aux_get_age_idx(struct rte_flow_hw *flow, struct rte_flow_hw_aux *aux)
158 : : {
159 [ # # # # : 0 : if (unlikely(flow->operation_type == MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE))
# # # # #
# # # ]
160 : 0 : return aux->upd.age_idx;
161 : : else
162 : 0 : return aux->orig.age_idx;
163 : : }
164 : :
165 : : static __rte_always_inline void
166 : : mlx5_flow_hw_aux_set_mtr_id(struct rte_flow_hw *flow,
167 : : struct rte_flow_hw_aux *aux,
168 : : uint32_t mtr_id)
169 : : {
170 [ # # # # : 0 : if (unlikely(flow->operation_type == MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE))
# # # # #
# ]
171 : 0 : aux->upd.mtr_id = mtr_id;
172 : : else
173 : 0 : aux->orig.mtr_id = mtr_id;
174 : : }
175 : :
176 : : static __rte_always_inline uint32_t
177 : : mlx5_flow_hw_aux_get_mtr_id(struct rte_flow_hw *flow, struct rte_flow_hw_aux *aux)
178 : : {
179 [ # # ]: 0 : if (unlikely(flow->operation_type == MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE))
180 : 0 : return aux->upd.mtr_id;
181 : : else
182 : 0 : return aux->orig.mtr_id;
183 : : }
184 : :
185 : : static __rte_always_inline struct mlx5_hw_q_job *
186 : : flow_hw_action_job_init(struct mlx5_priv *priv, uint32_t queue,
187 : : const struct rte_flow_action_handle *handle,
188 : : void *user_data, void *query_data,
189 : : enum mlx5_hw_job_type type,
190 : : enum mlx5_hw_indirect_type indirect_type,
191 : : struct rte_flow_error *error);
192 : : static void
193 : : flow_hw_age_count_release(struct mlx5_priv *priv, uint32_t queue, struct rte_flow_hw *flow,
194 : : struct rte_flow_error *error);
195 : :
196 : : static int
197 : : mlx5_tbl_multi_pattern_process(struct rte_eth_dev *dev,
198 : : struct rte_flow_template_table *tbl,
199 : : struct mlx5_multi_pattern_segment *segment,
200 : : uint32_t bulk_size,
201 : : struct rte_flow_error *error);
202 : : static void
203 : : mlx5_destroy_multi_pattern_segment(struct mlx5_multi_pattern_segment *segment);
204 : :
205 : : static __rte_always_inline enum mlx5_indirect_list_type
206 : : flow_hw_inlist_type_get(const struct rte_flow_action *actions);
207 : :
208 : : static int
209 : : flow_hw_allocate_actions(struct rte_eth_dev *dev,
210 : : uint64_t action_flags,
211 : : struct rte_flow_error *error);
212 : :
213 : : static int
214 : : flow_hw_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
215 : : const struct rte_flow_item items[],
216 : : const struct rte_flow_action actions[],
217 : : bool external __rte_unused, int hairpin __rte_unused,
218 : : struct rte_flow_error *error);
219 : :
220 : : bool
221 : 0 : mlx5_hw_ctx_validate(const struct rte_eth_dev *dev, struct rte_flow_error *error)
222 : : {
223 : 0 : const struct mlx5_priv *priv = dev->data->dev_private;
224 : :
225 [ # # ]: 0 : if (!priv->dr_ctx) {
226 : 0 : rte_flow_error_set(error, EINVAL,
227 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
228 : : "non-template flow engine was not configured");
229 : 0 : return false;
230 : : }
231 : : return true;
232 : : }
233 : :
234 : : static int
235 : : flow_hw_allocate_actions(struct rte_eth_dev *dev,
236 : : uint64_t action_flags,
237 : : struct rte_flow_error *error);
238 : :
239 : : static __rte_always_inline int
240 : : mlx5_multi_pattern_reformat_to_index(enum mlx5dr_action_type type)
241 : : {
242 : : switch (type) {
243 : : case MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2:
244 : : return 0;
245 : : case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2:
246 : : return 1;
247 : : case MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2:
248 : : return 2;
249 : : case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3:
250 : : return 3;
251 : : default:
252 : : break;
253 : : }
254 : : return -1;
255 : : }
256 : :
257 : : /* Include only supported reformat actions for BWC non template API. */
258 : : static __rte_always_inline int
259 : : mlx5_bwc_multi_pattern_reformat_to_index(enum mlx5dr_action_type type)
260 : : {
261 : 0 : switch (type) {
262 : : case MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2:
263 : : case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2:
264 : : case MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2:
265 : : case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3:
266 : : return mlx5_multi_pattern_reformat_to_index(type);
267 : : default:
268 : : break;
269 : : }
270 : : return -1;
271 : : }
272 : :
273 : : static __rte_always_inline enum mlx5dr_action_type
274 : : mlx5_multi_pattern_reformat_index_to_type(uint32_t ix)
275 : : {
276 : : switch (ix) {
277 : : case 0:
278 : : return MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2;
279 : : case 1:
280 : : return MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;
281 : : case 2:
282 : : return MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2;
283 : : case 3:
284 : : return MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3;
285 : : default:
286 : : break;
287 : : }
288 : : return MLX5DR_ACTION_TYP_MAX;
289 : : }
290 : :
291 : : static inline enum mlx5dr_table_type
292 : : get_mlx5dr_fdb_table_type(const struct rte_flow_attr *attr,
293 : : uint32_t specialize, bool fdb_unified_en)
294 : : {
295 [ # # # # ]: 0 : if (fdb_unified_en && !!attr->group) {
296 [ # # ]: 0 : if ((specialize & (RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_WIRE_ORIG |
297 : : RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_VPORT_ORIG)) == 0)
298 : : return MLX5DR_TABLE_TYPE_FDB_UNIFIED;
299 : : MLX5_ASSERT((specialize & (RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_WIRE_ORIG |
300 : : RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_VPORT_ORIG)) !=
301 : : (RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_WIRE_ORIG |
302 : : RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_VPORT_ORIG));
303 [ # # ]: 0 : if (specialize & RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_WIRE_ORIG)
304 : : return MLX5DR_TABLE_TYPE_FDB_RX;
305 [ # # ]: 0 : if (specialize & RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_VPORT_ORIG)
306 : 0 : return MLX5DR_TABLE_TYPE_FDB_TX;
307 : : }
308 : :
309 : : return MLX5DR_TABLE_TYPE_FDB;
310 : : }
311 : :
312 : : static inline enum mlx5dr_table_type
313 : 0 : get_mlx5dr_table_type(const struct rte_flow_attr *attr, uint32_t specialize,
314 : : bool fdb_unified_en)
315 : : {
316 : : enum mlx5dr_table_type type;
317 : :
318 [ # # ]: 0 : if (attr->transfer)
319 : : type = get_mlx5dr_fdb_table_type(attr, specialize, fdb_unified_en);
320 [ # # ]: 0 : else if (attr->egress)
321 : : type = MLX5DR_TABLE_TYPE_NIC_TX;
322 : : else
323 : : type = MLX5DR_TABLE_TYPE_NIC_RX;
324 : 0 : return type;
325 : : }
326 : :
327 : : /* Non template default queue size used for inner ctrl queue. */
328 : : #define MLX5_NT_DEFAULT_QUEUE_SIZE 32
329 : :
330 : : struct mlx5_mirror_clone {
331 : : enum rte_flow_action_type type;
332 : : void *action_ctx;
333 : : };
334 : :
335 : : struct mlx5_mirror {
336 : : struct mlx5_indirect_list indirect;
337 : : uint32_t clones_num;
338 : : struct mlx5dr_action *mirror_action;
339 : : struct mlx5_mirror_clone clone[MLX5_MIRROR_MAX_CLONES_NUM];
340 : : };
341 : :
342 : : static int flow_hw_flush_all_ctrl_flows(struct rte_eth_dev *dev);
343 : : static int flow_hw_translate_group(struct rte_eth_dev *dev,
344 : : const struct mlx5_flow_template_table_cfg *cfg,
345 : : uint32_t group,
346 : : uint32_t *table_group,
347 : : struct rte_flow_error *error);
348 : : static __rte_always_inline int
349 : : flow_hw_set_vlan_vid_construct(struct rte_eth_dev *dev,
350 : : struct mlx5_modification_cmd *mhdr_cmd,
351 : : struct mlx5_action_construct_data *act_data,
352 : : const struct mlx5_hw_actions *hw_acts,
353 : : const struct rte_flow_action *action);
354 : : static void
355 : : flow_hw_construct_quota(struct mlx5_priv *priv,
356 : : struct mlx5dr_rule_action *rule_act, uint32_t qid);
357 : :
358 : : static int
359 : : mlx5_flow_ct_init(struct rte_eth_dev *dev,
360 : : uint32_t nb_conn_tracks,
361 : : uint16_t nb_queue);
362 : :
363 : : static __rte_always_inline uint32_t flow_hw_tx_tag_regc_mask(struct rte_eth_dev *dev);
364 : : static __rte_always_inline uint32_t flow_hw_tx_tag_regc_value(struct rte_eth_dev *dev);
365 : :
366 : : static int flow_hw_async_create_validate(struct rte_eth_dev *dev,
367 : : const uint32_t queue,
368 : : const struct rte_flow_template_table *table,
369 : : enum rte_flow_table_insertion_type insertion_type,
370 : : const uint32_t rule_index,
371 : : const struct rte_flow_item items[],
372 : : const uint8_t pattern_template_index,
373 : : const struct rte_flow_action actions[],
374 : : const uint8_t action_template_index,
375 : : struct rte_flow_error *error);
376 : : static int flow_hw_async_update_validate(struct rte_eth_dev *dev,
377 : : const uint32_t queue,
378 : : const struct rte_flow_hw *flow,
379 : : const struct rte_flow_action actions[],
380 : : const uint8_t action_template_index,
381 : : struct rte_flow_error *error);
382 : : static int flow_hw_async_destroy_validate(struct rte_eth_dev *dev,
383 : : const uint32_t queue,
384 : : const struct rte_flow_hw *flow,
385 : : struct rte_flow_error *error);
386 : :
387 : : const struct mlx5_flow_driver_ops mlx5_flow_hw_drv_ops;
388 : :
389 : : /* DR action flags with different table. */
390 : : static uint32_t mlx5_hw_act_flag[MLX5_HW_ACTION_FLAG_MAX]
391 : : [MLX5DR_TABLE_TYPE_MAX] = {
392 : : {
393 : : MLX5DR_ACTION_FLAG_ROOT_RX,
394 : : MLX5DR_ACTION_FLAG_ROOT_TX,
395 : : MLX5DR_ACTION_FLAG_ROOT_FDB,
396 : : MLX5DR_ACTION_FLAG_ROOT_FDB,
397 : : MLX5DR_ACTION_FLAG_ROOT_FDB,
398 : : MLX5DR_ACTION_FLAG_ROOT_FDB,
399 : : },
400 : : {
401 : : MLX5DR_ACTION_FLAG_HWS_RX,
402 : : MLX5DR_ACTION_FLAG_HWS_TX,
403 : : MLX5DR_ACTION_FLAG_HWS_FDB,
404 : : MLX5DR_ACTION_FLAG_HWS_FDB_RX,
405 : : MLX5DR_ACTION_FLAG_HWS_FDB_TX,
406 : : MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED,
407 : : },
408 : : };
409 : :
410 : : /**
411 : : * Jump table flags.
412 : : * Can jump to FDB_RX table from FDB_RX or UNIFIED tables.
413 : : * Can jump to FDB_TX table from FDB_TX or UNIFIED tables.
414 : : * Can jump to UNIFIED table from all tables.
415 : : */
416 : : static uint32_t mlx5_hw_act_dest_table_flag[MLX5DR_TABLE_TYPE_MAX] = {
417 : : MLX5DR_ACTION_FLAG_HWS_RX,
418 : : MLX5DR_ACTION_FLAG_HWS_TX,
419 : : MLX5DR_ACTION_FLAG_HWS_FDB,
420 : : (MLX5DR_ACTION_FLAG_HWS_FDB_RX | MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED),
421 : : (MLX5DR_ACTION_FLAG_HWS_FDB_TX | MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED),
422 : : (MLX5DR_ACTION_FLAG_HWS_FDB_RX | MLX5DR_ACTION_FLAG_HWS_FDB_TX |
423 : : MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED),
424 : : };
425 : :
426 : : /* Ethernet item spec for promiscuous mode. */
427 : : static const struct rte_flow_item_eth ctrl_rx_eth_promisc_spec = {
428 : : .hdr.dst_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
429 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
430 : : .hdr.ether_type = 0,
431 : : };
432 : : /* Ethernet item mask for promiscuous mode. */
433 : : static const struct rte_flow_item_eth ctrl_rx_eth_promisc_mask = {
434 : : .hdr.dst_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
435 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
436 : : .hdr.ether_type = 0,
437 : : };
438 : :
439 : : /* Ethernet item spec for all multicast mode. */
440 : : static const struct rte_flow_item_eth ctrl_rx_eth_mcast_spec = {
441 : : .hdr.dst_addr.addr_bytes = { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 },
442 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
443 : : .hdr.ether_type = 0,
444 : : };
445 : : /* Ethernet item mask for all multicast mode. */
446 : : static const struct rte_flow_item_eth ctrl_rx_eth_mcast_mask = {
447 : : .hdr.dst_addr.addr_bytes = { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 },
448 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
449 : : .hdr.ether_type = 0,
450 : : };
451 : :
452 : : /* Ethernet item spec for IPv4 multicast traffic. */
453 : : static const struct rte_flow_item_eth ctrl_rx_eth_ipv4_mcast_spec = {
454 : : .hdr.dst_addr.addr_bytes = { 0x01, 0x00, 0x5e, 0x00, 0x00, 0x00 },
455 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
456 : : .hdr.ether_type = 0,
457 : : };
458 : : /* Ethernet item mask for IPv4 multicast traffic. */
459 : : static const struct rte_flow_item_eth ctrl_rx_eth_ipv4_mcast_mask = {
460 : : .hdr.dst_addr.addr_bytes = { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 },
461 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
462 : : .hdr.ether_type = 0,
463 : : };
464 : :
465 : : /* Ethernet item spec for IPv6 multicast traffic. */
466 : : static const struct rte_flow_item_eth ctrl_rx_eth_ipv6_mcast_spec = {
467 : : .hdr.dst_addr.addr_bytes = { 0x33, 0x33, 0x00, 0x00, 0x00, 0x00 },
468 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
469 : : .hdr.ether_type = 0,
470 : : };
471 : : /* Ethernet item mask for IPv6 multicast traffic. */
472 : : static const struct rte_flow_item_eth ctrl_rx_eth_ipv6_mcast_mask = {
473 : : .hdr.dst_addr.addr_bytes = { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 },
474 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
475 : : .hdr.ether_type = 0,
476 : : };
477 : :
478 : : /* Ethernet item mask for unicast traffic. */
479 : : static const struct rte_flow_item_eth ctrl_rx_eth_dmac_mask = {
480 : : .hdr.dst_addr.addr_bytes = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
481 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
482 : : .hdr.ether_type = 0,
483 : : };
484 : :
485 : : /* Ethernet item spec for broadcast. */
486 : : static const struct rte_flow_item_eth ctrl_rx_eth_bcast_spec = {
487 : : .hdr.dst_addr.addr_bytes = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
488 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
489 : : .hdr.ether_type = 0,
490 : : };
491 : :
492 : : static inline uint32_t
493 : : flow_hw_q_pending(struct mlx5_priv *priv, uint32_t queue)
494 : : {
495 : 0 : struct mlx5_hw_q *q = &priv->hw_q[queue];
496 : :
497 : : MLX5_ASSERT(q->size >= q->job_idx);
498 : 0 : return (q->size - q->job_idx) + q->ongoing_flow_ops;
499 : : }
500 : :
501 : : static inline void
502 : 0 : flow_hw_q_inc_flow_ops(struct mlx5_priv *priv, uint32_t queue)
503 : : {
504 : 0 : struct mlx5_hw_q *q = &priv->hw_q[queue];
505 : :
506 : 0 : q->ongoing_flow_ops++;
507 : 0 : }
508 : :
509 : : static inline void
510 : : flow_hw_q_dec_flow_ops(struct mlx5_priv *priv, uint32_t queue)
511 : : {
512 : 0 : struct mlx5_hw_q *q = &priv->hw_q[queue];
513 : :
514 : 0 : q->ongoing_flow_ops--;
515 : : }
516 : :
517 : : static inline enum mlx5dr_matcher_insert_mode
518 : : flow_hw_matcher_insert_mode_get(enum rte_flow_table_insertion_type insert_type)
519 : : {
520 : 0 : if (insert_type == RTE_FLOW_TABLE_INSERTION_TYPE_PATTERN)
521 : : return MLX5DR_MATCHER_INSERT_BY_HASH;
522 : : else
523 : 0 : return MLX5DR_MATCHER_INSERT_BY_INDEX;
524 : : }
525 : :
526 : : static inline enum mlx5dr_matcher_distribute_mode
527 : : flow_hw_matcher_distribute_mode_get(enum rte_flow_table_hash_func hash_func)
528 : : {
529 [ # # ]: 0 : if (hash_func == RTE_FLOW_TABLE_HASH_FUNC_LINEAR)
530 : : return MLX5DR_MATCHER_DISTRIBUTE_BY_LINEAR;
531 : : else
532 : 0 : return MLX5DR_MATCHER_DISTRIBUTE_BY_HASH;
533 : : }
534 : :
535 : : /**
536 : : * Set the hash fields according to the @p rss_desc information.
537 : : *
538 : : * @param[in] rss_desc
539 : : * Pointer to the mlx5_flow_rss_desc.
540 : : * @param[out] hash_fields
541 : : * Pointer to the RSS hash fields.
542 : : */
543 : : static void
544 : 0 : flow_hw_hashfields_set(struct mlx5_flow_rss_desc *rss_desc,
545 : : uint64_t *hash_fields)
546 : : {
547 : : uint64_t fields = 0;
548 : : int rss_inner = 0;
549 [ # # ]: 0 : uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
550 : :
551 : : #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
552 [ # # ]: 0 : if (rss_desc->level >= 2)
553 : : rss_inner = 1;
554 : : #endif
555 [ # # ]: 0 : if (rss_types & MLX5_IPV4_LAYER_TYPES) {
556 [ # # ]: 0 : if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
557 : : fields |= IBV_RX_HASH_SRC_IPV4;
558 [ # # ]: 0 : else if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
559 : : fields |= IBV_RX_HASH_DST_IPV4;
560 : : else
561 : : fields |= MLX5_IPV4_IBV_RX_HASH;
562 [ # # ]: 0 : } else if (rss_types & MLX5_IPV6_LAYER_TYPES) {
563 [ # # ]: 0 : if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
564 : : fields |= IBV_RX_HASH_SRC_IPV6;
565 [ # # ]: 0 : else if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
566 : : fields |= IBV_RX_HASH_DST_IPV6;
567 : : else
568 : : fields |= MLX5_IPV6_IBV_RX_HASH;
569 : : }
570 [ # # ]: 0 : if (rss_types & RTE_ETH_RSS_UDP) {
571 [ # # ]: 0 : if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
572 : 0 : fields |= IBV_RX_HASH_SRC_PORT_UDP;
573 [ # # ]: 0 : else if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
574 : 0 : fields |= IBV_RX_HASH_DST_PORT_UDP;
575 : : else
576 : 0 : fields |= MLX5_UDP_IBV_RX_HASH;
577 [ # # ]: 0 : } else if (rss_types & RTE_ETH_RSS_TCP) {
578 [ # # ]: 0 : if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
579 : 0 : fields |= IBV_RX_HASH_SRC_PORT_TCP;
580 [ # # ]: 0 : else if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
581 : 0 : fields |= IBV_RX_HASH_DST_PORT_TCP;
582 : : else
583 : 0 : fields |= MLX5_TCP_IBV_RX_HASH;
584 : : }
585 [ # # ]: 0 : if (rss_types & RTE_ETH_RSS_ESP)
586 : 0 : fields |= IBV_RX_HASH_IPSEC_SPI;
587 [ # # ]: 0 : if (rss_inner)
588 : 0 : fields |= IBV_RX_HASH_INNER;
589 : 0 : *hash_fields |= fields;
590 : 0 : }
591 : :
592 : : static uint64_t
593 : 0 : flow_hw_action_flags_get(const struct rte_flow_action actions[],
594 : : const struct rte_flow_action **qrss,
595 : : const struct rte_flow_action **mark,
596 : : int *encap_idx,
597 : : int *act_cnt,
598 : : struct rte_flow_error *error)
599 : : {
600 : : uint64_t action_flags = 0;
601 : : const struct rte_flow_action *action;
602 : : const struct rte_flow_action_raw_encap *raw_encap;
603 : : int raw_decap_idx = -1;
604 : : int action_idx;
605 : :
606 : 0 : *encap_idx = -1;
607 : : action_idx = 0;
608 [ # # ]: 0 : for (action = actions; action->type != RTE_FLOW_ACTION_TYPE_END; action++) {
609 : 0 : int type = (int)action->type;
610 [ # # # # : 0 : switch (type) {
# # # # #
# # # # #
# # # # #
# # # # #
# ]
611 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT:
612 [ # # # # : 0 : switch (MLX5_INDIRECT_ACTION_TYPE_GET(action->conf)) {
# # ]
613 : 0 : case MLX5_INDIRECT_ACTION_TYPE_RSS:
614 : 0 : goto rss;
615 : 0 : case MLX5_INDIRECT_ACTION_TYPE_AGE:
616 : 0 : goto age;
617 : 0 : case MLX5_INDIRECT_ACTION_TYPE_COUNT:
618 : 0 : goto count;
619 : 0 : case MLX5_INDIRECT_ACTION_TYPE_CT:
620 : 0 : goto ct;
621 : 0 : case MLX5_INDIRECT_ACTION_TYPE_METER_MARK:
622 : 0 : goto meter;
623 : 0 : default:
624 : 0 : goto error;
625 : : }
626 : : break;
627 : 0 : case RTE_FLOW_ACTION_TYPE_DROP:
628 : 0 : action_flags |= MLX5_FLOW_ACTION_DROP;
629 : 0 : break;
630 : 0 : case RTE_FLOW_ACTION_TYPE_FLAG:
631 : 0 : action_flags |= MLX5_FLOW_ACTION_FLAG;
632 : 0 : break;
633 : 0 : case RTE_FLOW_ACTION_TYPE_MARK:
634 : 0 : action_flags |= MLX5_FLOW_ACTION_MARK;
635 : 0 : *mark = action;
636 : 0 : break;
637 : 0 : case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
638 : 0 : action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
639 : 0 : break;
640 : 0 : case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
641 : 0 : action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
642 : 0 : break;
643 : 0 : case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
644 : 0 : action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
645 : 0 : break;
646 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP:
647 : 0 : action_flags |= MLX5_FLOW_ACTION_JUMP;
648 : 0 : break;
649 : 0 : case RTE_FLOW_ACTION_TYPE_QUEUE:
650 : 0 : action_flags |= MLX5_FLOW_ACTION_QUEUE;
651 : 0 : *qrss = action;
652 : 0 : break;
653 : : case RTE_FLOW_ACTION_TYPE_RSS:
654 : 0 : rss:
655 : 0 : action_flags |= MLX5_FLOW_ACTION_RSS;
656 : 0 : *qrss = action;
657 : 0 : break;
658 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
659 : : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
660 : 0 : action_flags |= MLX5_FLOW_ACTION_ENCAP;
661 : 0 : *encap_idx = action_idx;
662 : 0 : break;
663 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
664 : 0 : action_flags |= MLX5_FLOW_ACTION_ENCAP;
665 : 0 : raw_encap = action->conf;
666 [ # # ]: 0 : if (raw_encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
667 : 0 : *encap_idx = raw_decap_idx != -1 ?
668 [ # # ]: 0 : raw_decap_idx : action_idx;
669 : : break;
670 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
671 : : case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
672 : 0 : action_flags |= MLX5_FLOW_ACTION_DECAP;
673 : 0 : break;
674 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
675 : 0 : action_flags |= MLX5_FLOW_ACTION_DECAP;
676 : : raw_decap_idx = action_idx;
677 : 0 : break;
678 : 0 : case RTE_FLOW_ACTION_TYPE_SEND_TO_KERNEL:
679 : 0 : action_flags |= MLX5_FLOW_ACTION_SEND_TO_KERNEL;
680 : 0 : break;
681 : 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
682 : 0 : action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
683 : 0 : break;
684 : 0 : case RTE_FLOW_ACTION_TYPE_PORT_ID:
685 : : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
686 : 0 : action_flags |= MLX5_FLOW_ACTION_PORT_ID;
687 : 0 : break;
688 : : case RTE_FLOW_ACTION_TYPE_AGE:
689 : 0 : age:
690 : 0 : action_flags |= MLX5_FLOW_ACTION_AGE;
691 : 0 : break;
692 : : case RTE_FLOW_ACTION_TYPE_COUNT:
693 : 0 : count:
694 : 0 : action_flags |= MLX5_FLOW_ACTION_COUNT;
695 : 0 : break;
696 : : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
697 : 0 : ct:
698 : 0 : action_flags |= MLX5_FLOW_ACTION_CT;
699 : 0 : break;
700 : : case RTE_FLOW_ACTION_TYPE_METER_MARK:
701 : 0 : meter:
702 : 0 : action_flags |= MLX5_FLOW_ACTION_METER;
703 : 0 : break;
704 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
705 : 0 : action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
706 : 0 : break;
707 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
708 : 0 : action_flags |= MLX5_FLOW_ACTION_JUMP_TO_TABLE_INDEX;
709 : 0 : break;
710 : : case RTE_FLOW_ACTION_TYPE_VOID:
711 : : case RTE_FLOW_ACTION_TYPE_END:
712 : : break;
713 : 0 : default:
714 : 0 : goto error;
715 : : }
716 : 0 : action_idx++;
717 : : }
718 [ # # ]: 0 : if (*encap_idx == -1)
719 : 0 : *encap_idx = action_idx;
720 : 0 : action_idx++; /* The END action. */
721 : 0 : *act_cnt = action_idx;
722 : 0 : return action_flags;
723 : 0 : error:
724 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
725 : : action, "invalid flow action");
726 : 0 : return 0;
727 : : }
728 : :
729 : : /**
730 : : * Register destination table DR jump action.
731 : : *
732 : : * @param[in] dev
733 : : * Pointer to the rte_eth_dev structure.
734 : : * @param[in] table_attr
735 : : * Pointer to the flow attributes.
736 : : * @param[in] dest_group
737 : : * The destination group ID.
738 : : * @param[out] error
739 : : * Pointer to error structure.
740 : : *
741 : : * @return
742 : : * Table on success, NULL otherwise and rte_errno is set.
743 : : */
744 : : static struct mlx5_hw_jump_action *
745 : 0 : flow_hw_jump_action_register(struct rte_eth_dev *dev,
746 : : const struct mlx5_flow_template_table_cfg *cfg,
747 : : uint32_t dest_group,
748 : : struct rte_flow_error *error)
749 : : {
750 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
751 : 0 : struct rte_flow_attr jattr = cfg->attr.flow_attr;
752 : 0 : uint32_t specialize = cfg->attr.specialize;
753 : : struct mlx5_flow_group *grp;
754 : 0 : struct mlx5_flow_cb_ctx ctx = {
755 : : .dev = dev,
756 : : .error = error,
757 : : .data = &jattr,
758 : : .data2 = &specialize,
759 : : };
760 : : struct mlx5_list_entry *ge;
761 : : uint32_t target_group;
762 : :
763 : 0 : target_group = dest_group;
764 [ # # ]: 0 : if (flow_hw_translate_group(dev, cfg, dest_group, &target_group, error))
765 : : return NULL;
766 : 0 : jattr.group = target_group;
767 : 0 : ge = mlx5_hlist_register(priv->sh->flow_tbls, target_group, &ctx);
768 [ # # ]: 0 : if (!ge)
769 : : return NULL;
770 : : grp = container_of(ge, struct mlx5_flow_group, entry);
771 : 0 : return &grp->jump;
772 : : }
773 : :
774 : : /**
775 : : * Release jump action.
776 : : *
777 : : * @param[in] dev
778 : : * Pointer to the rte_eth_dev structure.
779 : : * @param[in] jump
780 : : * Pointer to the jump action.
781 : : */
782 : :
783 : : static void
784 : : flow_hw_jump_release(struct rte_eth_dev *dev, struct mlx5_hw_jump_action *jump)
785 : : {
786 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
787 : : struct mlx5_flow_group *grp;
788 : :
789 : 0 : grp = container_of(jump, struct mlx5_flow_group, jump);
790 : 0 : mlx5_hlist_unregister(priv->sh->flow_tbls, &grp->entry);
791 : 0 : }
792 : :
793 : : /**
794 : : * Register queue/RSS action.
795 : : *
796 : : * @param[in] dev
797 : : * Pointer to the rte_eth_dev structure.
798 : : * @param[in] hws_flags
799 : : * DR action flags.
800 : : * @param[in] action
801 : : * rte flow action.
802 : : * @param[in] item_flags
803 : : * Item flags for non template rule.
804 : : * @param[in] is_template
805 : : * True if it is a template rule.
806 : : *
807 : : * @return
808 : : * Table on success, NULL otherwise and rte_errno is set.
809 : : */
810 : : static inline struct mlx5_hrxq*
811 : 0 : flow_hw_tir_action_register(struct rte_eth_dev *dev,
812 : : uint32_t hws_flags,
813 : : const struct rte_flow_action *action)
814 : : {
815 : 0 : struct mlx5_flow_rss_desc rss_desc = {
816 : : .hws_flags = hws_flags,
817 : : };
818 : : struct mlx5_hrxq *hrxq;
819 : :
820 [ # # ]: 0 : if (action->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
821 : 0 : const struct rte_flow_action_queue *queue = action->conf;
822 : :
823 : 0 : rss_desc.const_q = &queue->index;
824 : 0 : rss_desc.queue_num = 1;
825 : : } else {
826 : 0 : const struct rte_flow_action_rss *rss = action->conf;
827 : :
828 : 0 : rss_desc.queue_num = rss->queue_num;
829 : 0 : rss_desc.const_q = rss->queue;
830 : 0 : memcpy(rss_desc.key,
831 [ # # ]: 0 : !rss->key ? rss_hash_default_key : rss->key,
832 : : MLX5_RSS_HASH_KEY_LEN);
833 : 0 : rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
834 [ # # ]: 0 : rss_desc.types = !rss->types ? RTE_ETH_RSS_IP : rss->types;
835 : 0 : rss_desc.symmetric_hash_function = MLX5_RSS_IS_SYMM(rss->func);
836 : 0 : flow_hw_hashfields_set(&rss_desc, &rss_desc.hash_fields);
837 : 0 : flow_dv_action_rss_l34_hash_adjust(rss->types,
838 : : &rss_desc.hash_fields);
839 [ # # ]: 0 : if (rss->level > 1) {
840 : 0 : rss_desc.hash_fields |= IBV_RX_HASH_INNER;
841 : 0 : rss_desc.tunnel = 1;
842 : : }
843 : : }
844 : 0 : hrxq = mlx5_hrxq_get(dev, &rss_desc);
845 : 0 : return hrxq;
846 : : }
847 : :
848 : : static __rte_always_inline int
849 : : flow_hw_ct_compile(struct rte_eth_dev *dev,
850 : : uint32_t queue, uint32_t idx,
851 : : struct mlx5dr_rule_action *rule_act)
852 : : {
853 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
854 : : struct mlx5_aso_ct_action *ct;
855 : :
856 : 0 : ct = mlx5_ipool_get(priv->hws_ctpool->cts, idx);
857 [ # # # # : 0 : if (!ct || (!priv->shared_host && mlx5_aso_ct_available(priv->sh, queue, ct)))
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # ]
858 : : return -1;
859 : 0 : rule_act->action = priv->hws_ctpool->dr_action;
860 : 0 : rule_act->aso_ct.offset = ct->offset;
861 : 0 : rule_act->aso_ct.direction = ct->is_original ?
862 : 0 : MLX5DR_ACTION_ASO_CT_DIRECTION_INITIATOR :
863 : : MLX5DR_ACTION_ASO_CT_DIRECTION_RESPONDER;
864 : : return 0;
865 : : }
866 : :
867 : : static void
868 : : flow_hw_template_destroy_reformat_action(struct mlx5_hw_encap_decap_action *encap_decap)
869 : : {
870 [ # # # # ]: 0 : if (encap_decap->action && !encap_decap->multi_pattern)
871 : 0 : mlx5dr_action_destroy(encap_decap->action);
872 : : }
873 : :
874 : : static void
875 : : flow_hw_template_destroy_mhdr_action(struct mlx5_hw_modify_header_action *mhdr)
876 : : {
877 [ # # # # ]: 0 : if (mhdr->action && !mhdr->multi_pattern)
878 : 0 : mlx5dr_action_destroy(mhdr->action);
879 : : }
880 : :
881 : : /**
882 : : * Destroy DR actions created by action template.
883 : : *
884 : : * For DR actions created during table creation's action translate.
885 : : * Need to destroy the DR action when destroying the table.
886 : : *
887 : : * @param[in] dev
888 : : * Pointer to the rte_eth_dev structure.
889 : : * @param[in] acts
890 : : * Pointer to the template HW steering DR actions.
891 : : */
892 : : static void
893 : 0 : __flow_hw_actions_release(struct rte_eth_dev *dev, struct mlx5_hw_actions *acts)
894 : : {
895 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
896 : :
897 [ # # ]: 0 : if (acts->mark)
898 [ # # ]: 0 : if (!(rte_atomic_fetch_sub_explicit(&priv->hws_mark_refcnt, 1,
899 : : rte_memory_order_relaxed) - 1))
900 : 0 : flow_hw_rxq_flag_set(dev, false);
901 : :
902 [ # # ]: 0 : if (acts->jump) {
903 : : struct mlx5_flow_group *grp;
904 : :
905 : 0 : grp = container_of
906 : : (acts->jump, struct mlx5_flow_group, jump);
907 : 0 : mlx5_hlist_unregister(priv->sh->flow_tbls, &grp->entry);
908 : 0 : acts->jump = NULL;
909 : : }
910 [ # # ]: 0 : if (acts->tir) {
911 : 0 : mlx5_hrxq_release(dev, acts->tir->idx);
912 : 0 : acts->tir = NULL;
913 : : }
914 [ # # ]: 0 : if (acts->encap_decap) {
915 : : flow_hw_template_destroy_reformat_action(acts->encap_decap);
916 : 0 : mlx5_free(acts->encap_decap);
917 : 0 : acts->encap_decap = NULL;
918 : : }
919 [ # # ]: 0 : if (acts->push_remove) {
920 [ # # ]: 0 : if (acts->push_remove->action)
921 : 0 : mlx5dr_action_destroy(acts->push_remove->action);
922 : 0 : mlx5_free(acts->push_remove);
923 : 0 : acts->push_remove = NULL;
924 : : }
925 [ # # ]: 0 : if (acts->mhdr) {
926 : : flow_hw_template_destroy_mhdr_action(acts->mhdr);
927 : 0 : mlx5_free(acts->mhdr);
928 : 0 : acts->mhdr = NULL;
929 : : }
930 [ # # ]: 0 : if (mlx5_hws_cnt_id_valid(acts->cnt_id)) {
931 [ # # ]: 0 : mlx5_hws_cnt_shared_put(priv->hws_cpool, &acts->cnt_id);
932 : 0 : acts->cnt_id = 0;
933 : : }
934 [ # # ]: 0 : if (acts->mtr_id) {
935 : 0 : mlx5_ipool_free(priv->hws_mpool->idx_pool, acts->mtr_id);
936 : 0 : acts->mtr_id = 0;
937 : : }
938 : 0 : }
939 : :
940 : : /**
941 : : * Release the action data back into the pool without destroy any action.
942 : : *
943 : : * @param[in] dev
944 : : * Pointer to the rte_eth_dev structure.
945 : : * @param[in] acts
946 : : * Pointer to the template HW steering DR actions.
947 : : */
948 : : static inline void
949 : 0 : __flow_hw_act_data_flush(struct rte_eth_dev *dev, struct mlx5_hw_actions *acts)
950 : : {
951 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
952 : : struct mlx5_action_construct_data *data;
953 : :
954 [ # # ]: 0 : while (!LIST_EMPTY(&acts->act_list)) {
955 : : data = LIST_FIRST(&acts->act_list);
956 [ # # ]: 0 : LIST_REMOVE(data, next);
957 : 0 : mlx5_ipool_free(priv->acts_ipool, data->idx);
958 : : }
959 : 0 : }
960 : :
961 : : /*
962 : : * Destroy DR actions created by action template.
963 : : *
964 : : * For DR actions created during table creation's action translate.
965 : : * Need to destroy the DR action when destroying the table.
966 : : *
967 : : * @param[in] dev
968 : : * Pointer to the rte_eth_dev structure.
969 : : * @param[in] acts
970 : : * Pointer to the template HW steering DR actions.
971 : : */
972 : : static void
973 : 0 : __flow_hw_action_template_destroy(struct rte_eth_dev *dev, struct mlx5_hw_actions *acts)
974 : : {
975 : 0 : __flow_hw_act_data_flush(dev, acts);
976 : 0 : __flow_hw_actions_release(dev, acts);
977 : 0 : }
978 : :
979 : : /**
980 : : * Append dynamic action to the dynamic action list.
981 : : *
982 : : * @param[in] priv
983 : : * Pointer to the port private data structure.
984 : : * @param[in] acts
985 : : * Pointer to the template HW steering DR actions.
986 : : * @param[in] type
987 : : * Action type.
988 : : * @param[in] action_src
989 : : * Offset of source rte flow action.
990 : : * @param[in] action_dst
991 : : * Offset of destination DR action.
992 : : *
993 : : * @return
994 : : * 0 on success, negative value otherwise and rte_errno is set.
995 : : */
996 : : static __rte_always_inline struct mlx5_action_construct_data *
997 : : __flow_hw_act_data_alloc(struct mlx5_priv *priv,
998 : : enum rte_flow_action_type type,
999 : : uint16_t action_src,
1000 : : uint16_t action_dst)
1001 : : {
1002 : : struct mlx5_action_construct_data *act_data;
1003 : 0 : uint32_t idx = 0;
1004 : :
1005 : 0 : act_data = mlx5_ipool_zmalloc(priv->acts_ipool, &idx);
1006 [ # # # # : 0 : if (!act_data)
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # #
# ]
1007 : : return NULL;
1008 : 0 : act_data->idx = idx;
1009 : 0 : act_data->type = type;
1010 : 0 : act_data->action_src = action_src;
1011 : 0 : act_data->action_dst = action_dst;
1012 : : return act_data;
1013 : : }
1014 : :
1015 : : /**
1016 : : * Append dynamic action to the dynamic action list.
1017 : : *
1018 : : * @param[in] priv
1019 : : * Pointer to the port private data structure.
1020 : : * @param[in] acts
1021 : : * Pointer to the template HW steering DR actions.
1022 : : * @param[in] type
1023 : : * Action type.
1024 : : * @param[in] action_src
1025 : : * Offset of source rte flow action.
1026 : : * @param[in] action_dst
1027 : : * Offset of destination DR action.
1028 : : *
1029 : : * @return
1030 : : * 0 on success, negative value otherwise and rte_errno is set.
1031 : : */
1032 : : static __rte_always_inline int
1033 : : __flow_hw_act_data_general_append(struct mlx5_priv *priv,
1034 : : struct mlx5_hw_actions *acts,
1035 : : enum rte_flow_action_type type,
1036 : : uint16_t action_src,
1037 : : uint16_t action_dst)
1038 : : {
1039 : : struct mlx5_action_construct_data *act_data;
1040 : :
1041 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1042 : : if (!act_data)
1043 : : return -1;
1044 [ # # # # : 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
# # # # #
# # # # #
# # # # #
# # # #
# ]
1045 : : return 0;
1046 : : }
1047 : :
1048 : : static __rte_always_inline int
1049 : : __flow_hw_act_data_indirect_append(struct mlx5_priv *priv,
1050 : : struct mlx5_hw_actions *acts,
1051 : : enum rte_flow_action_type type,
1052 : : enum rte_flow_action_type mask_type,
1053 : : uint16_t action_src,
1054 : : uint16_t action_dst)
1055 : : {
1056 : : struct mlx5_action_construct_data *act_data;
1057 : :
1058 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1059 : : if (!act_data)
1060 : : return -1;
1061 : 0 : act_data->indirect.expected_type = mask_type;
1062 [ # # ]: 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
1063 : : return 0;
1064 : : }
1065 : :
1066 : : static __rte_always_inline int
1067 : : flow_hw_act_data_indirect_list_append(struct mlx5_priv *priv,
1068 : : struct mlx5_hw_actions *acts,
1069 : : enum rte_flow_action_type type,
1070 : : uint16_t action_src, uint16_t action_dst,
1071 : : indirect_list_callback_t cb)
1072 : : {
1073 : : struct mlx5_action_construct_data *act_data;
1074 : :
1075 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1076 : : if (!act_data)
1077 : 0 : return -1;
1078 : 0 : act_data->indirect_list_cb = cb;
1079 [ # # # # : 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
# # ]
1080 : 0 : return 0;
1081 : : }
1082 : : /**
1083 : : * Append dynamic encap action to the dynamic action list.
1084 : : *
1085 : : * @param[in] priv
1086 : : * Pointer to the port private data structure.
1087 : : * @param[in] acts
1088 : : * Pointer to the template HW steering DR actions.
1089 : : * @param[in] type
1090 : : * Action type.
1091 : : * @param[in] action_src
1092 : : * Offset of source rte flow action.
1093 : : * @param[in] action_dst
1094 : : * Offset of destination DR action.
1095 : : * @param[in] len
1096 : : * Length of the data to be updated.
1097 : : *
1098 : : * @return
1099 : : * 0 on success, negative value otherwise and rte_errno is set.
1100 : : */
1101 : : static __rte_always_inline int
1102 : : __flow_hw_act_data_encap_append(struct mlx5_priv *priv,
1103 : : struct mlx5_hw_actions *acts,
1104 : : enum rte_flow_action_type type,
1105 : : uint16_t action_src,
1106 : : uint16_t action_dst,
1107 : : uint16_t len)
1108 : : {
1109 : : struct mlx5_action_construct_data *act_data;
1110 : :
1111 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1112 : : if (!act_data)
1113 : : return -1;
1114 : 0 : act_data->encap.len = len;
1115 [ # # ]: 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
1116 : : return 0;
1117 : : }
1118 : :
1119 : : /**
1120 : : * Append dynamic push action to the dynamic action list.
1121 : : *
1122 : : * @param[in] dev
1123 : : * Pointer to the port.
1124 : : * @param[in] acts
1125 : : * Pointer to the template HW steering DR actions.
1126 : : * @param[in] type
1127 : : * Action type.
1128 : : * @param[in] action_src
1129 : : * Offset of source rte flow action.
1130 : : * @param[in] action_dst
1131 : : * Offset of destination DR action.
1132 : : * @param[in] len
1133 : : * Length of the data to be updated.
1134 : : *
1135 : : * @return
1136 : : * Data pointer on success, NULL otherwise and rte_errno is set.
1137 : : */
1138 : : static __rte_always_inline void *
1139 : : __flow_hw_act_data_push_append(struct rte_eth_dev *dev,
1140 : : struct mlx5_hw_actions *acts,
1141 : : enum rte_flow_action_type type,
1142 : : uint16_t action_src,
1143 : : uint16_t action_dst,
1144 : : uint16_t len)
1145 : : {
1146 : : struct mlx5_action_construct_data *act_data;
1147 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1148 : :
1149 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1150 : : if (!act_data)
1151 : : return NULL;
1152 : 0 : act_data->ipv6_ext.len = len;
1153 [ # # ]: 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
1154 : : return act_data;
1155 : : }
1156 : :
1157 : : static __rte_always_inline int
1158 : : __flow_hw_act_data_hdr_modify_append(struct mlx5_priv *priv,
1159 : : struct mlx5_hw_actions *acts,
1160 : : enum rte_flow_action_type type,
1161 : : uint16_t action_src,
1162 : : uint16_t action_dst,
1163 : : const struct rte_flow_action_modify_field *mf,
1164 : : uint16_t mhdr_cmds_off,
1165 : : uint16_t mhdr_cmds_end,
1166 : : bool shared,
1167 : : struct field_modify_info *field,
1168 : : struct field_modify_info *dcopy,
1169 : : uint32_t *mask)
1170 : : {
1171 : : struct mlx5_action_construct_data *act_data;
1172 : :
1173 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1174 : : if (!act_data)
1175 : : return -1;
1176 : 0 : act_data->modify_header.action = *mf;
1177 : 0 : act_data->modify_header.mhdr_cmds_off = mhdr_cmds_off;
1178 : 0 : act_data->modify_header.mhdr_cmds_end = mhdr_cmds_end;
1179 : 0 : act_data->modify_header.shared = shared;
1180 [ # # ]: 0 : rte_memcpy(act_data->modify_header.field, field,
1181 : : sizeof(*field) * MLX5_ACT_MAX_MOD_FIELDS);
1182 [ # # ]: 0 : rte_memcpy(act_data->modify_header.dcopy, dcopy,
1183 : : sizeof(*dcopy) * MLX5_ACT_MAX_MOD_FIELDS);
1184 [ # # ]: 0 : rte_memcpy(act_data->modify_header.mask, mask,
1185 : : sizeof(*mask) * MLX5_ACT_MAX_MOD_FIELDS);
1186 [ # # ]: 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
1187 : : return 0;
1188 : : }
1189 : :
1190 : : /**
1191 : : * Append shared RSS action to the dynamic action list.
1192 : : *
1193 : : * @param[in] priv
1194 : : * Pointer to the port private data structure.
1195 : : * @param[in] acts
1196 : : * Pointer to the template HW steering DR actions.
1197 : : * @param[in] type
1198 : : * Action type.
1199 : : * @param[in] action_src
1200 : : * Offset of source rte flow action.
1201 : : * @param[in] action_dst
1202 : : * Offset of destination DR action.
1203 : : * @param[in] idx
1204 : : * Shared RSS index.
1205 : : * @param[in] rss
1206 : : * Pointer to the shared RSS info.
1207 : : *
1208 : : * @return
1209 : : * 0 on success, negative value otherwise and rte_errno is set.
1210 : : */
1211 : : static __rte_always_inline int
1212 : : __flow_hw_act_data_shared_rss_append(struct mlx5_priv *priv,
1213 : : struct mlx5_hw_actions *acts,
1214 : : enum rte_flow_action_type type,
1215 : : uint16_t action_src,
1216 : : uint16_t action_dst,
1217 : : uint32_t idx,
1218 : : struct mlx5_shared_action_rss *rss)
1219 : : {
1220 : : struct mlx5_action_construct_data *act_data;
1221 : :
1222 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1223 : : if (!act_data)
1224 : : return -1;
1225 : 0 : act_data->shared_rss.level = rss->origin.level;
1226 [ # # ]: 0 : act_data->shared_rss.types = !rss->origin.types ? RTE_ETH_RSS_IP :
1227 : : rss->origin.types;
1228 : 0 : act_data->shared_rss.idx = idx;
1229 : 0 : act_data->shared_rss.symmetric_hash_function =
1230 : 0 : MLX5_RSS_IS_SYMM(rss->origin.func);
1231 [ # # ]: 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
1232 : : return 0;
1233 : : }
1234 : :
1235 : : /**
1236 : : * Append shared counter action to the dynamic action list.
1237 : : *
1238 : : * @param[in] priv
1239 : : * Pointer to the port private data structure.
1240 : : * @param[in] acts
1241 : : * Pointer to the template HW steering DR actions.
1242 : : * @param[in] type
1243 : : * Action type.
1244 : : * @param[in] action_src
1245 : : * Offset of source rte flow action.
1246 : : * @param[in] action_dst
1247 : : * Offset of destination DR action.
1248 : : * @param[in] cnt_id
1249 : : * Shared counter id.
1250 : : *
1251 : : * @return
1252 : : * 0 on success, negative value otherwise and rte_errno is set.
1253 : : */
1254 : : static __rte_always_inline int
1255 : : __flow_hw_act_data_shared_cnt_append(struct mlx5_priv *priv,
1256 : : struct mlx5_hw_actions *acts,
1257 : : enum rte_flow_action_type type,
1258 : : uint16_t action_src,
1259 : : uint16_t action_dst,
1260 : : cnt_id_t cnt_id)
1261 : : {
1262 : : struct mlx5_action_construct_data *act_data;
1263 : :
1264 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1265 : : if (!act_data)
1266 : : return -1;
1267 : : act_data->type = type;
1268 : 0 : act_data->shared_counter.id = cnt_id;
1269 [ # # ]: 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
1270 : : return 0;
1271 : : }
1272 : :
1273 : : /**
1274 : : * Append shared meter_mark action to the dynamic action list.
1275 : : *
1276 : : * @param[in] priv
1277 : : * Pointer to the port private data structure.
1278 : : * @param[in] acts
1279 : : * Pointer to the template HW steering DR actions.
1280 : : * @param[in] type
1281 : : * Action type.
1282 : : * @param[in] action_src
1283 : : * Offset of source rte flow action.
1284 : : * @param[in] action_dst
1285 : : * Offset of destination DR action.
1286 : : * @param[in] mtr_id
1287 : : * Shared meter id.
1288 : : *
1289 : : * @return
1290 : : * 0 on success, negative value otherwise and rte_errno is set.
1291 : : */
1292 : : static __rte_always_inline int
1293 : : __flow_hw_act_data_shared_mtr_append(struct mlx5_priv *priv,
1294 : : struct mlx5_hw_actions *acts,
1295 : : enum rte_flow_action_type type,
1296 : : uint16_t action_src,
1297 : : uint16_t action_dst,
1298 : : cnt_id_t mtr_id)
1299 : : { struct mlx5_action_construct_data *act_data;
1300 : :
1301 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1302 : : if (!act_data)
1303 : : return -1;
1304 : : act_data->type = type;
1305 : 0 : act_data->shared_meter.id = mtr_id;
1306 [ # # ]: 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
1307 : : return 0;
1308 : : }
1309 : :
1310 : : /**
1311 : : * Translate shared indirect action.
1312 : : *
1313 : : * @param[in] dev
1314 : : * Pointer to the rte_eth_dev data structure.
1315 : : * @param[in] action
1316 : : * Pointer to the shared indirect rte_flow action.
1317 : : * @param[in] acts
1318 : : * Pointer to the template HW steering DR actions.
1319 : : * @param[in] action_src
1320 : : * Offset of source rte flow action.
1321 : : * @param[in] action_dst
1322 : : * Offset of destination DR action.
1323 : : *
1324 : : * @return
1325 : : * 0 on success, negative value otherwise and rte_errno is set.
1326 : : */
1327 : : static __rte_always_inline int
1328 : : flow_hw_shared_action_translate(struct rte_eth_dev *dev,
1329 : : const struct rte_flow_action *action,
1330 : : struct mlx5_hw_actions *acts,
1331 : : uint16_t action_src,
1332 : : uint16_t action_dst)
1333 : : {
1334 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1335 : : struct mlx5_shared_action_rss *shared_rss;
1336 : 0 : uint32_t act_idx = (uint32_t)(uintptr_t)action->conf;
1337 : 0 : uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
1338 : 0 : uint32_t idx = act_idx &
1339 : : ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
1340 : :
1341 : 0 : switch (type) {
1342 : 0 : case MLX5_INDIRECT_ACTION_TYPE_RSS:
1343 : 0 : shared_rss = mlx5_ipool_get
1344 : 0 : (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
1345 [ # # ]: 0 : if (!shared_rss || __flow_hw_act_data_shared_rss_append
1346 : : (priv, acts,
1347 : : (enum rte_flow_action_type)MLX5_RTE_FLOW_ACTION_TYPE_RSS,
1348 : : action_src, action_dst, idx, shared_rss)) {
1349 : 0 : DRV_LOG(WARNING, "Indirect RSS action index %d translate failed", act_idx);
1350 : : return -1;
1351 : : }
1352 : : break;
1353 : 0 : case MLX5_INDIRECT_ACTION_TYPE_COUNT:
1354 : : if (__flow_hw_act_data_shared_cnt_append(priv, acts,
1355 : : (enum rte_flow_action_type)
1356 : : MLX5_RTE_FLOW_ACTION_TYPE_COUNT,
1357 : : action_src, action_dst, act_idx)) {
1358 : 0 : DRV_LOG(WARNING, "Indirect count action translate failed");
1359 : : return -1;
1360 : : }
1361 : : break;
1362 : : case MLX5_INDIRECT_ACTION_TYPE_AGE:
1363 : : /* Not supported, prevent by validate function. */
1364 : : MLX5_ASSERT(0);
1365 : : break;
1366 : 0 : case MLX5_INDIRECT_ACTION_TYPE_CT:
1367 : : if (flow_hw_ct_compile(dev, MLX5_HW_INV_QUEUE,
1368 : : idx, &acts->rule_acts[action_dst])) {
1369 : 0 : DRV_LOG(WARNING, "Indirect CT action translate failed");
1370 : : return -1;
1371 : : }
1372 : : break;
1373 : 0 : case MLX5_INDIRECT_ACTION_TYPE_METER_MARK:
1374 : : if (__flow_hw_act_data_shared_mtr_append(priv, acts,
1375 : : (enum rte_flow_action_type)
1376 : : MLX5_RTE_FLOW_ACTION_TYPE_METER_MARK,
1377 : : action_src, action_dst, idx)) {
1378 : 0 : DRV_LOG(WARNING, "Indirect meter mark action translate failed");
1379 : : return -1;
1380 : : }
1381 : : break;
1382 : 0 : case MLX5_INDIRECT_ACTION_TYPE_QUOTA:
1383 : : flow_hw_construct_quota(priv, &acts->rule_acts[action_dst], idx);
1384 : : break;
1385 : 0 : default:
1386 : 0 : DRV_LOG(WARNING, "Unsupported shared action type:%d", type);
1387 : : break;
1388 : : }
1389 : : return 0;
1390 : : }
1391 : :
1392 : : static __rte_always_inline bool
1393 : : flow_hw_action_modify_field_is_shared(const struct rte_flow_action *action,
1394 : : const struct rte_flow_action *mask)
1395 : : {
1396 : : const struct rte_flow_action_modify_field *v = action->conf;
1397 : 0 : const struct rte_flow_action_modify_field *m = mask->conf;
1398 : :
1399 : 0 : if (v->src.field == RTE_FLOW_FIELD_VALUE) {
1400 : : uint32_t j;
1401 : :
1402 [ # # ]: 0 : for (j = 0; j < RTE_DIM(m->src.value); ++j) {
1403 : : /*
1404 : : * Immediate value is considered to be masked
1405 : : * (and thus shared by all flow rules), if mask
1406 : : * is non-zero. Partial mask over immediate value
1407 : : * is not allowed.
1408 : : */
1409 [ # # ]: 0 : if (m->src.value[j])
1410 : : return true;
1411 : : }
1412 : : return false;
1413 : : }
1414 [ # # ]: 0 : if (v->src.field == RTE_FLOW_FIELD_POINTER)
1415 : 0 : return m->src.pvalue != NULL;
1416 : : /*
1417 : : * Source field types other than VALUE and
1418 : : * POINTER are always shared.
1419 : : */
1420 : : return true;
1421 : : }
1422 : :
1423 : : static __rte_always_inline bool
1424 : : flow_hw_should_insert_nop(const struct mlx5_hw_modify_header_action *mhdr,
1425 : : const struct mlx5_modification_cmd *cmd,
1426 : : const struct rte_flow_attr *attr)
1427 : : {
1428 : : struct mlx5_modification_cmd last_cmd = { { 0 } };
1429 : : struct mlx5_modification_cmd new_cmd = { { 0 } };
1430 : 0 : const uint32_t cmds_num = mhdr->mhdr_cmds_num;
1431 : : unsigned int last_type;
1432 : : bool should_insert = false;
1433 : :
1434 : : /*
1435 : : * Modify header action list does not require NOPs in root table,
1436 : : * because different type of underlying object is used:
1437 : : * - in root table - MODIFY_HEADER_CONTEXT (does not require NOPs),
1438 : : * - in non-root - either inline modify action or based on Modify Header Pattern
1439 : : * (which requires NOPs).
1440 : : */
1441 [ # # # # ]: 0 : if (attr->group == 0)
1442 : : return false;
1443 [ # # # # ]: 0 : if (cmds_num == 0)
1444 : : return false;
1445 : 0 : last_cmd = *(&mhdr->mhdr_cmds[cmds_num - 1]);
1446 [ # # # # ]: 0 : last_cmd.data0 = rte_be_to_cpu_32(last_cmd.data0);
1447 [ # # # # ]: 0 : last_cmd.data1 = rte_be_to_cpu_32(last_cmd.data1);
1448 : 0 : last_type = last_cmd.action_type;
1449 : 0 : new_cmd = *cmd;
1450 [ # # # # ]: 0 : new_cmd.data0 = rte_be_to_cpu_32(new_cmd.data0);
1451 [ # # # # ]: 0 : new_cmd.data1 = rte_be_to_cpu_32(new_cmd.data1);
1452 [ # # # # : 0 : switch (new_cmd.action_type) {
# # ]
1453 : 0 : case MLX5_MODIFICATION_TYPE_SET:
1454 : : case MLX5_MODIFICATION_TYPE_ADD:
1455 [ # # # # ]: 0 : if (last_type == MLX5_MODIFICATION_TYPE_SET ||
1456 : : last_type == MLX5_MODIFICATION_TYPE_ADD)
1457 : 0 : should_insert = new_cmd.field == last_cmd.field;
1458 : 0 : else if (last_type == MLX5_MODIFICATION_TYPE_COPY ||
1459 [ # # # # ]: 0 : last_type == MLX5_MODIFICATION_TYPE_ADD_FIELD)
1460 : 0 : should_insert = new_cmd.field == last_cmd.dst_field;
1461 : : else if (last_type == MLX5_MODIFICATION_TYPE_NOP)
1462 : : should_insert = false;
1463 : : else
1464 : : MLX5_ASSERT(false); /* Other types are not supported. */
1465 : : break;
1466 : 0 : case MLX5_MODIFICATION_TYPE_COPY:
1467 : : case MLX5_MODIFICATION_TYPE_ADD_FIELD:
1468 [ # # # # ]: 0 : if (last_type == MLX5_MODIFICATION_TYPE_SET ||
1469 : : last_type == MLX5_MODIFICATION_TYPE_ADD)
1470 [ # # # # ]: 0 : should_insert = (new_cmd.field == last_cmd.field ||
1471 [ # # # # ]: 0 : new_cmd.dst_field == last_cmd.field);
1472 : 0 : else if (last_type == MLX5_MODIFICATION_TYPE_COPY ||
1473 [ # # # # ]: 0 : last_type == MLX5_MODIFICATION_TYPE_ADD_FIELD)
1474 [ # # # # ]: 0 : should_insert = (new_cmd.field == last_cmd.dst_field ||
1475 [ # # # # ]: 0 : new_cmd.dst_field == last_cmd.dst_field);
1476 : : else if (last_type == MLX5_MODIFICATION_TYPE_NOP)
1477 : : should_insert = false;
1478 : : else
1479 : : MLX5_ASSERT(false); /* Other types are not supported. */
1480 : : break;
1481 : : default:
1482 : : /* Other action types should be rejected on AT validation. */
1483 : : MLX5_ASSERT(false);
1484 : : break;
1485 : : }
1486 : : return should_insert;
1487 : : }
1488 : :
1489 : : static __rte_always_inline int
1490 : : flow_hw_mhdr_cmd_nop_append(struct mlx5_hw_modify_header_action *mhdr)
1491 : : {
1492 : : struct mlx5_modification_cmd *nop;
1493 : : uint32_t num = mhdr->mhdr_cmds_num;
1494 : :
1495 [ # # # # ]: 0 : if (num + 1 >= MLX5_MHDR_MAX_CMD)
1496 : : return -ENOMEM;
1497 : 0 : nop = mhdr->mhdr_cmds + num;
1498 : : nop->data0 = 0;
1499 : : nop->action_type = MLX5_MODIFICATION_TYPE_NOP;
1500 : 0 : nop->data0 = rte_cpu_to_be_32(nop->data0);
1501 : 0 : nop->data1 = 0;
1502 : 0 : mhdr->mhdr_cmds_num = num + 1;
1503 : : return 0;
1504 : : }
1505 : :
1506 : : static __rte_always_inline int
1507 : : flow_hw_mhdr_cmd_append(struct mlx5_hw_modify_header_action *mhdr,
1508 : : struct mlx5_modification_cmd *cmd)
1509 : : {
1510 : 0 : uint32_t num = mhdr->mhdr_cmds_num;
1511 : :
1512 [ # # ]: 0 : if (num + 1 >= MLX5_MHDR_MAX_CMD)
1513 : : return -ENOMEM;
1514 : 0 : mhdr->mhdr_cmds[num] = *cmd;
1515 : 0 : mhdr->mhdr_cmds_num = num + 1;
1516 : : return 0;
1517 : : }
1518 : :
1519 : : static __rte_always_inline int
1520 : : flow_hw_converted_mhdr_cmds_append(struct mlx5_hw_modify_header_action *mhdr,
1521 : : struct mlx5_flow_dv_modify_hdr_resource *resource,
1522 : : const struct rte_flow_attr *attr)
1523 : : {
1524 : : uint32_t idx;
1525 : : int ret;
1526 : :
1527 [ # # ]: 0 : for (idx = 0; idx < resource->actions_num; ++idx) {
1528 : : struct mlx5_modification_cmd *src = &resource->actions[idx];
1529 : :
1530 [ # # ]: 0 : if (flow_hw_should_insert_nop(mhdr, src, attr)) {
1531 : : ret = flow_hw_mhdr_cmd_nop_append(mhdr);
1532 : : if (ret)
1533 : : return ret;
1534 : : }
1535 : : ret = flow_hw_mhdr_cmd_append(mhdr, src);
1536 : : if (ret)
1537 : : return ret;
1538 : : }
1539 : : return 0;
1540 : : }
1541 : :
1542 : : static __rte_always_inline void
1543 : : flow_hw_modify_field_init(struct mlx5_hw_modify_header_action *mhdr,
1544 : : struct rte_flow_actions_template *at)
1545 : : {
1546 : : memset(mhdr, 0, sizeof(*mhdr));
1547 : : /* Modify header action without any commands is shared by default. */
1548 : 0 : mhdr->shared = true;
1549 : 0 : mhdr->pos = at->mhdr_off;
1550 : : }
1551 : :
1552 : : static __rte_always_inline int
1553 : : flow_hw_modify_field_compile(struct rte_eth_dev *dev,
1554 : : const struct rte_flow_attr *attr,
1555 : : const struct rte_flow_action *action, /* Current action from AT. */
1556 : : const struct rte_flow_action *action_mask, /* Current mask from AT. */
1557 : : struct mlx5_hw_actions *acts,
1558 : : struct mlx5_hw_modify_header_action *mhdr,
1559 : : uint16_t src_pos,
1560 : : struct rte_flow_error *error)
1561 : : {
1562 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1563 : 0 : const struct rte_flow_action_modify_field *conf = action->conf;
1564 : : union {
1565 : : struct mlx5_flow_dv_modify_hdr_resource resource;
1566 : : uint8_t data[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
1567 : : sizeof(struct mlx5_modification_cmd) * MLX5_MHDR_MAX_CMD];
1568 : : } dummy;
1569 : : struct mlx5_flow_dv_modify_hdr_resource *resource;
1570 : 0 : struct rte_flow_item item = {
1571 : : .spec = NULL,
1572 : : .mask = NULL
1573 : : };
1574 : 0 : struct field_modify_info field[MLX5_ACT_MAX_MOD_FIELDS] = {
1575 : : {0, 0, MLX5_MODI_OUT_NONE} };
1576 : 0 : struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {
1577 : : {0, 0, MLX5_MODI_OUT_NONE} };
1578 : 0 : uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = { 0 };
1579 : 0 : uint32_t type, value = 0;
1580 : : uint16_t cmds_start, cmds_end;
1581 : : bool shared;
1582 : : int ret;
1583 : :
1584 : : /*
1585 : : * Modify header action is shared if previous modify_field actions
1586 : : * are shared and currently compiled action is shared.
1587 : : */
1588 : : shared = flow_hw_action_modify_field_is_shared(action, action_mask);
1589 : 0 : mhdr->shared &= shared;
1590 [ # # ]: 0 : if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
1591 : : conf->src.field == RTE_FLOW_FIELD_VALUE) {
1592 [ # # ]: 0 : type = conf->operation == RTE_FLOW_MODIFY_SET ? MLX5_MODIFICATION_TYPE_SET :
1593 : : MLX5_MODIFICATION_TYPE_ADD;
1594 : : /* For SET/ADD fill the destination field (field) first. */
1595 : 0 : mlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,
1596 : 0 : conf->width, dev,
1597 : : attr, error);
1598 : 0 : item.spec = conf->src.field == RTE_FLOW_FIELD_POINTER ?
1599 [ # # ]: 0 : (void *)(uintptr_t)conf->src.pvalue :
1600 : : (void *)(uintptr_t)&conf->src.value;
1601 [ # # ]: 0 : if (conf->dst.field == RTE_FLOW_FIELD_META ||
1602 [ # # ]: 0 : conf->dst.field == RTE_FLOW_FIELD_TAG ||
1603 [ # # ]: 0 : conf->dst.field == RTE_FLOW_FIELD_METER_COLOR ||
1604 : 0 : conf->dst.field == (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG) {
1605 : : uint8_t tag_index = flow_tag_index_get(&conf->dst);
1606 : :
1607 : 0 : value = *(const unaligned_uint32_t *)item.spec;
1608 [ # # # # ]: 0 : if (conf->dst.field == RTE_FLOW_FIELD_TAG &&
1609 : : tag_index == RTE_PMD_MLX5_LINEAR_HASH_TAG_INDEX)
1610 [ # # ]: 0 : value = rte_cpu_to_be_32(value << 16);
1611 : : else
1612 [ # # ]: 0 : value = rte_cpu_to_be_32(value);
1613 : 0 : item.spec = &value;
1614 [ # # ]: 0 : } else if (conf->dst.field == RTE_FLOW_FIELD_GTP_PSC_QFI ||
1615 : : conf->dst.field == RTE_FLOW_FIELD_GENEVE_OPT_TYPE) {
1616 : : /*
1617 : : * Both QFI and Geneve option type are passed as an uint8_t integer,
1618 : : * but it is accessed through a 2nd least significant byte of a 32-bit
1619 : : * field in modify header command.
1620 : : */
1621 : 0 : value = *(const uint8_t *)item.spec;
1622 [ # # ]: 0 : value = rte_cpu_to_be_32(value << 8);
1623 : 0 : item.spec = &value;
1624 [ # # ]: 0 : } else if (conf->dst.field == RTE_FLOW_FIELD_VXLAN_LAST_RSVD) {
1625 : 0 : value = *(const uint8_t *)item.spec << 24;
1626 [ # # ]: 0 : value = rte_cpu_to_be_32(value);
1627 : 0 : item.spec = &value;
1628 : : }
1629 : : } else {
1630 : 0 : type = conf->operation == RTE_FLOW_MODIFY_SET ?
1631 [ # # ]: 0 : MLX5_MODIFICATION_TYPE_COPY : MLX5_MODIFICATION_TYPE_ADD_FIELD;
1632 : : /* For COPY fill the destination field (dcopy) without mask. */
1633 : 0 : mlx5_flow_field_id_to_modify_info(&conf->dst, dcopy, NULL,
1634 : 0 : conf->width, dev,
1635 : : attr, error);
1636 : : /* Then construct the source field (field) with mask. */
1637 : 0 : mlx5_flow_field_id_to_modify_info(&conf->src, field, mask,
1638 : 0 : conf->width, dev,
1639 : : attr, error);
1640 : : }
1641 : 0 : item.mask = &mask;
1642 : : memset(&dummy, 0, sizeof(dummy));
1643 : : resource = &dummy.resource;
1644 : 0 : ret = flow_dv_convert_modify_action(&item, field, dcopy, resource, type, error);
1645 [ # # ]: 0 : if (ret)
1646 : : return ret;
1647 : : MLX5_ASSERT(resource->actions_num > 0);
1648 : : /*
1649 : : * If previous modify field action collide with this one, then insert NOP command.
1650 : : * This NOP command will not be a part of action's command range used to update commands
1651 : : * on rule creation.
1652 : : */
1653 [ # # ]: 0 : if (flow_hw_should_insert_nop(mhdr, &resource->actions[0], attr)) {
1654 : : ret = flow_hw_mhdr_cmd_nop_append(mhdr);
1655 : : if (ret)
1656 : 0 : return rte_flow_error_set(error, ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1657 : : NULL, "too many modify field operations specified");
1658 : : }
1659 : 0 : cmds_start = mhdr->mhdr_cmds_num;
1660 : : ret = flow_hw_converted_mhdr_cmds_append(mhdr, resource, attr);
1661 [ # # ]: 0 : if (ret)
1662 : 0 : return rte_flow_error_set(error, ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1663 : : NULL, "too many modify field operations specified");
1664 : :
1665 : 0 : cmds_end = mhdr->mhdr_cmds_num;
1666 [ # # ]: 0 : if (shared)
1667 : : return 0;
1668 : : ret = __flow_hw_act_data_hdr_modify_append(priv, acts, RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
1669 : 0 : src_pos, mhdr->pos, conf,
1670 : : cmds_start, cmds_end, shared,
1671 : : field, dcopy, mask);
1672 : : if (ret)
1673 : 0 : return rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1674 : : NULL, "not enough memory to store modify field metadata");
1675 : : return 0;
1676 : : }
1677 : :
1678 : : static uint32_t
1679 : 0 : flow_hw_count_nop_modify_field(struct mlx5_hw_modify_header_action *mhdr)
1680 : : {
1681 : : uint32_t i;
1682 : : uint32_t nops = 0;
1683 : :
1684 [ # # ]: 0 : for (i = 0; i < mhdr->mhdr_cmds_num; ++i) {
1685 : 0 : struct mlx5_modification_cmd cmd = mhdr->mhdr_cmds[i];
1686 : :
1687 [ # # ]: 0 : cmd.data0 = rte_be_to_cpu_32(cmd.data0);
1688 [ # # ]: 0 : if (cmd.action_type == MLX5_MODIFICATION_TYPE_NOP)
1689 : 0 : ++nops;
1690 : : }
1691 : 0 : return nops;
1692 : : }
1693 : :
1694 : : static int
1695 : 0 : flow_hw_validate_compiled_modify_field(struct rte_eth_dev *dev,
1696 : : const struct mlx5_flow_template_table_cfg *cfg,
1697 : : struct mlx5_hw_modify_header_action *mhdr,
1698 : : struct rte_flow_error *error)
1699 : : {
1700 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1701 : 0 : struct mlx5_hca_attr *hca_attr = &priv->sh->cdev->config.hca_attr;
1702 : :
1703 : : /*
1704 : : * Header modify pattern length limitation is only valid for HWS groups, i.e. groups > 0.
1705 : : * In group 0, MODIFY_FIELD actions are handled with header modify actions
1706 : : * managed by rdma-core.
1707 : : */
1708 [ # # ]: 0 : if (cfg->attr.flow_attr.group != 0 &&
1709 [ # # ]: 0 : mhdr->mhdr_cmds_num > hca_attr->max_header_modify_pattern_length) {
1710 : 0 : uint32_t nops = flow_hw_count_nop_modify_field(mhdr);
1711 : :
1712 : 0 : DRV_LOG(ERR, "Too many modify header commands generated from "
1713 : : "MODIFY_FIELD actions. "
1714 : : "Generated HW commands = %u (amount of NOP commands = %u). "
1715 : : "Maximum supported = %u.",
1716 : : mhdr->mhdr_cmds_num, nops,
1717 : : hca_attr->max_header_modify_pattern_length);
1718 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1719 : : "Number of MODIFY_FIELD actions exceeds maximum "
1720 : : "supported limit of actions");
1721 : : }
1722 : : return 0;
1723 : : }
1724 : :
1725 : : static int
1726 : 0 : flow_hw_represented_port_compile(struct rte_eth_dev *dev,
1727 : : const struct rte_flow_attr *attr,
1728 : : const struct rte_flow_action *action,
1729 : : const struct rte_flow_action *action_mask,
1730 : : struct mlx5_hw_actions *acts,
1731 : : uint16_t action_src, uint16_t action_dst,
1732 : : struct rte_flow_error *error)
1733 : : {
1734 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1735 : 0 : const struct rte_flow_action_ethdev *v = action->conf;
1736 : 0 : const struct rte_flow_action_ethdev *m = action_mask->conf;
1737 : : int ret;
1738 : :
1739 [ # # ]: 0 : if (!attr->group)
1740 : 0 : return rte_flow_error_set(error, EINVAL,
1741 : : RTE_FLOW_ERROR_TYPE_ATTR, NULL,
1742 : : "represented_port action cannot"
1743 : : " be used on group 0");
1744 [ # # ]: 0 : if (!attr->transfer)
1745 : 0 : return rte_flow_error_set(error, EINVAL,
1746 : : RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER,
1747 : : NULL,
1748 : : "represented_port action requires"
1749 : : " transfer attribute");
1750 [ # # ]: 0 : if (attr->ingress || attr->egress)
1751 : 0 : return rte_flow_error_set(error, EINVAL,
1752 : : RTE_FLOW_ERROR_TYPE_ATTR, NULL,
1753 : : "represented_port action cannot"
1754 : : " be used with direction attributes");
1755 [ # # ]: 0 : if (!priv->master)
1756 : 0 : return rte_flow_error_set(error, EINVAL,
1757 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1758 : : "represented_port action must"
1759 : : " be used on proxy port");
1760 [ # # # # ]: 0 : if (m && !!m->port_id) {
1761 : : struct mlx5_priv *port_priv;
1762 : :
1763 [ # # ]: 0 : if (!v)
1764 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
1765 : : action, "port index was not provided");
1766 : 0 : port_priv = mlx5_port_to_eswitch_info(v->port_id, false);
1767 [ # # ]: 0 : if (port_priv == NULL)
1768 : 0 : return rte_flow_error_set
1769 : : (error, EINVAL,
1770 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1771 : : "port does not exist or unable to"
1772 : : " obtain E-Switch info for port");
1773 : : MLX5_ASSERT(priv->hw_vport != NULL);
1774 [ # # ]: 0 : if (priv->hw_vport[v->port_id]) {
1775 : 0 : acts->rule_acts[action_dst].action =
1776 : : priv->hw_vport[v->port_id];
1777 : : } else {
1778 : 0 : return rte_flow_error_set
1779 : : (error, EINVAL,
1780 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1781 : : "cannot use represented_port action"
1782 : : " with this port");
1783 : : }
1784 : : } else {
1785 : : ret = __flow_hw_act_data_general_append
1786 : 0 : (priv, acts, action->type,
1787 : : action_src, action_dst);
1788 : : if (ret)
1789 : 0 : return rte_flow_error_set
1790 : : (error, ENOMEM,
1791 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1792 : : "not enough memory to store"
1793 : : " vport action");
1794 : : }
1795 : : return 0;
1796 : : }
1797 : :
1798 : : static __rte_always_inline int
1799 : : flow_hw_cnt_compile(struct rte_eth_dev *dev, uint32_t start_pos,
1800 : : struct mlx5_hw_actions *acts)
1801 : : {
1802 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1803 : : uint32_t pos = start_pos;
1804 : : cnt_id_t cnt_id;
1805 : : int ret;
1806 : :
1807 : 0 : ret = mlx5_hws_cnt_shared_get(priv->hws_cpool, &cnt_id, 0);
1808 : : if (ret != 0)
1809 : : return ret;
1810 : 0 : ret = mlx5_hws_cnt_pool_get_action_offset
1811 : : (priv->hws_cpool,
1812 : : cnt_id,
1813 : : &acts->rule_acts[pos].action,
1814 : : &acts->rule_acts[pos].counter.offset);
1815 : : if (ret != 0)
1816 : : return ret;
1817 : 0 : acts->cnt_id = cnt_id;
1818 : : return 0;
1819 : : }
1820 : :
1821 : : static __rte_always_inline bool
1822 : : is_of_vlan_pcp_present(const struct rte_flow_action *actions)
1823 : : {
1824 : : /*
1825 : : * Order of RTE VLAN push actions is
1826 : : * OF_PUSH_VLAN / OF_SET_VLAN_VID [ / OF_SET_VLAN_PCP ]
1827 : : */
1828 : 0 : return actions[MLX5_HW_VLAN_PUSH_PCP_IDX].type ==
1829 : : RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP;
1830 : : }
1831 : :
1832 : : static __rte_always_inline bool
1833 : : is_template_masked_push_vlan(const struct rte_flow_action_of_push_vlan *mask)
1834 : : {
1835 : : /*
1836 : : * In masked push VLAN template all RTE push actions are masked.
1837 : : */
1838 [ # # ]: 0 : return mask && mask->ethertype != 0;
1839 : : }
1840 : :
1841 : 0 : static rte_be32_t vlan_hdr_to_be32(const struct rte_flow_action *actions)
1842 : : {
1843 : : /*
1844 : : * OpenFlow Switch Specification defines 801.1q VID as 12+1 bits.
1845 : : */
1846 : : rte_be32_t type, vid, pcp;
1847 : : #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
1848 : : rte_be32_t vid_lo, vid_hi;
1849 : : #endif
1850 : :
1851 : 0 : type = ((const struct rte_flow_action_of_push_vlan *)
1852 : 0 : actions[MLX5_HW_VLAN_PUSH_TYPE_IDX].conf)->ethertype;
1853 : 0 : vid = ((const struct rte_flow_action_of_set_vlan_vid *)
1854 : 0 : actions[MLX5_HW_VLAN_PUSH_VID_IDX].conf)->vlan_vid;
1855 : : pcp = is_of_vlan_pcp_present(actions) ?
1856 : : ((const struct rte_flow_action_of_set_vlan_pcp *)
1857 [ # # # # ]: 0 : actions[MLX5_HW_VLAN_PUSH_PCP_IDX].conf)->vlan_pcp : 0;
1858 : : #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
1859 : 0 : vid_hi = vid & 0xff;
1860 : : vid_lo = vid >> 8;
1861 : 0 : return (((vid_lo << 8) | (pcp << 5) | vid_hi) << 16) | type;
1862 : : #else
1863 : : return (type << 16) | (pcp << 13) | vid;
1864 : : #endif
1865 : : }
1866 : :
1867 : : static __rte_always_inline struct mlx5_aso_mtr *
1868 : : flow_hw_meter_mark_alloc(struct rte_eth_dev *dev, uint32_t queue,
1869 : : const struct rte_flow_action *action,
1870 : : struct mlx5_hw_q_job *job, bool push,
1871 : : struct rte_flow_error *error)
1872 : : {
1873 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1874 : 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
1875 : 0 : const struct rte_flow_action_meter_mark *meter_mark = action->conf;
1876 : : struct mlx5_aso_mtr *aso_mtr;
1877 : : struct mlx5_flow_meter_info *fm;
1878 : 0 : uint32_t mtr_id = 0;
1879 : : uintptr_t handle = (uintptr_t)MLX5_INDIRECT_ACTION_TYPE_METER_MARK <<
1880 : : MLX5_INDIRECT_ACTION_TYPE_OFFSET;
1881 : :
1882 : 0 : if (priv->shared_host) {
1883 : 0 : rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1884 : : "Meter mark actions can only be created on the host port");
1885 : : return NULL;
1886 : : }
1887 [ # # # # : 0 : if (meter_mark->profile == NULL)
# # # # #
# # # #
# ]
1888 : : return NULL;
1889 : 0 : aso_mtr = mlx5_ipool_malloc(pool->idx_pool, &mtr_id);
1890 [ # # # # : 0 : if (!aso_mtr) {
# # # # #
# # # #
# ]
1891 : 0 : rte_flow_error_set(error, ENOMEM,
1892 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1893 : : NULL,
1894 : : "failed to allocate aso meter entry");
1895 [ # # # # : 0 : if (mtr_id)
# # # # #
# # # #
# ]
1896 : 0 : mlx5_ipool_free(pool->idx_pool, mtr_id);
1897 : : return NULL;
1898 : : }
1899 : : /* Fill the flow meter parameters. */
1900 : 0 : aso_mtr->type = ASO_METER_INDIRECT;
1901 : : fm = &aso_mtr->fm;
1902 : 0 : fm->meter_id = mtr_id;
1903 : 0 : fm->profile = (struct mlx5_flow_meter_profile *)(meter_mark->profile);
1904 : 0 : fm->is_enable = meter_mark->state;
1905 : 0 : fm->color_aware = meter_mark->color_mode;
1906 : 0 : aso_mtr->pool = pool;
1907 [ # # ]: 0 : aso_mtr->state = (queue == MLX5_HW_INV_QUEUE) ?
1908 : : ASO_METER_WAIT : ASO_METER_WAIT_ASYNC;
1909 : 0 : aso_mtr->offset = mtr_id - 1;
1910 [ # # # # : 0 : aso_mtr->init_color = fm->color_aware ? RTE_COLORS : RTE_COLOR_GREEN;
# # # # #
# # # #
# ]
1911 : 0 : job->action = (void *)(handle | mtr_id);
1912 : : /* Update ASO flow meter by wqe. */
1913 [ # # # # : 0 : if (mlx5_aso_meter_update_by_wqe(priv, queue, aso_mtr,
# # # # #
# # # #
# ]
1914 : : &priv->mtr_bulk, job, push)) {
1915 : 0 : mlx5_ipool_free(pool->idx_pool, mtr_id);
1916 : : return NULL;
1917 : : }
1918 : : /* Wait for ASO object completion. */
1919 [ # # # # : 0 : if (queue == MLX5_HW_INV_QUEUE &&
# # # # #
# # # # #
# # ]
1920 : 0 : mlx5_aso_mtr_wait(priv, aso_mtr, true)) {
1921 : 0 : mlx5_ipool_free(pool->idx_pool, mtr_id);
1922 : : return NULL;
1923 : : }
1924 : : return aso_mtr;
1925 : : }
1926 : :
1927 : : static __rte_always_inline int
1928 : : flow_hw_meter_mark_compile(struct rte_eth_dev *dev,
1929 : : uint16_t aso_mtr_pos,
1930 : : const struct rte_flow_action *action,
1931 : : struct mlx5dr_rule_action *acts,
1932 : : uint32_t *index,
1933 : : uint32_t queue,
1934 : : struct rte_flow_error *error)
1935 : : {
1936 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1937 : 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
1938 : : struct mlx5_aso_mtr *aso_mtr;
1939 : : struct mlx5_hw_q_job *job =
1940 : : flow_hw_action_job_init(priv, queue, NULL, NULL, NULL,
1941 : : MLX5_HW_Q_JOB_TYPE_CREATE,
1942 : : MLX5_HW_INDIRECT_TYPE_LEGACY, NULL);
1943 : :
1944 : : if (!job)
1945 : : return -1;
1946 : : aso_mtr = flow_hw_meter_mark_alloc(dev, queue, action, job,
1947 : : true, error);
1948 : : if (!aso_mtr) {
1949 : : flow_hw_job_put(priv, job, queue);
1950 : : return -1;
1951 : : }
1952 : :
1953 : : /* Compile METER_MARK action */
1954 : 0 : acts[aso_mtr_pos].action = pool->action;
1955 : 0 : acts[aso_mtr_pos].aso_meter.offset = aso_mtr->offset;
1956 : 0 : *index = aso_mtr->fm.meter_id;
1957 : : return 0;
1958 : : }
1959 : :
1960 : : static int
1961 : 0 : flow_hw_translate_indirect_mirror(__rte_unused struct rte_eth_dev *dev,
1962 : : __rte_unused const struct mlx5_action_construct_data *act_data,
1963 : : const struct rte_flow_action *action,
1964 : : struct mlx5dr_rule_action *dr_rule)
1965 : : {
1966 : 0 : const struct rte_flow_action_indirect_list *list_conf = action->conf;
1967 : 0 : const struct mlx5_mirror *mirror = (typeof(mirror))list_conf->handle;
1968 : :
1969 : 0 : dr_rule->action = mirror->mirror_action;
1970 : 0 : return 0;
1971 : : }
1972 : :
1973 : : /**
1974 : : * HWS mirror implemented as FW island.
1975 : : * The action does not support indirect list flow configuration.
1976 : : * If template handle was masked, use handle mirror action in flow rules.
1977 : : * Otherwise let flow rule specify mirror handle.
1978 : : */
1979 : : static int
1980 : 0 : hws_table_tmpl_translate_indirect_mirror(struct rte_eth_dev *dev,
1981 : : const struct rte_flow_action *action,
1982 : : const struct rte_flow_action *mask,
1983 : : struct mlx5_hw_actions *acts,
1984 : : uint16_t action_src, uint16_t action_dst)
1985 : : {
1986 : : int ret = 0;
1987 : 0 : const struct rte_flow_action_indirect_list *mask_conf = mask->conf;
1988 : :
1989 [ # # # # ]: 0 : if (mask_conf && mask_conf->handle) {
1990 : : /**
1991 : : * If mirror handle was masked, assign fixed DR5 mirror action.
1992 : : */
1993 : : flow_hw_translate_indirect_mirror(dev, NULL, action,
1994 : 0 : &acts->rule_acts[action_dst]);
1995 : : } else {
1996 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1997 : : ret = flow_hw_act_data_indirect_list_append
1998 : : (priv, acts, RTE_FLOW_ACTION_TYPE_INDIRECT_LIST,
1999 : : action_src, action_dst,
2000 : : flow_hw_translate_indirect_mirror);
2001 : : }
2002 : 0 : return ret;
2003 : : }
2004 : :
2005 : : static int
2006 : 0 : flow_hw_reformat_action(__rte_unused struct rte_eth_dev *dev,
2007 : : __rte_unused const struct mlx5_action_construct_data *data,
2008 : : const struct rte_flow_action *action,
2009 : : struct mlx5dr_rule_action *dr_rule)
2010 : : {
2011 : 0 : const struct rte_flow_action_indirect_list *indlst_conf = action->conf;
2012 : :
2013 : 0 : dr_rule->action = ((struct mlx5_hw_encap_decap_action *)
2014 : 0 : (indlst_conf->handle))->action;
2015 [ # # ]: 0 : if (!dr_rule->action)
2016 : 0 : return -EINVAL;
2017 : : return 0;
2018 : : }
2019 : :
2020 : : /**
2021 : : * Template conf must not be masked. If handle is masked, use the one in template,
2022 : : * otherwise update per flow rule.
2023 : : */
2024 : : static int
2025 : 0 : hws_table_tmpl_translate_indirect_reformat(struct rte_eth_dev *dev,
2026 : : const struct rte_flow_action *action,
2027 : : const struct rte_flow_action *mask,
2028 : : struct mlx5_hw_actions *acts,
2029 : : uint16_t action_src, uint16_t action_dst)
2030 : : {
2031 : : int ret = -1;
2032 : 0 : const struct rte_flow_action_indirect_list *mask_conf = mask->conf;
2033 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
2034 : :
2035 [ # # # # : 0 : if (mask_conf && mask_conf->handle && !mask_conf->conf)
# # ]
2036 : : /**
2037 : : * If handle was masked, assign fixed DR action.
2038 : : */
2039 : : ret = flow_hw_reformat_action(dev, NULL, action,
2040 [ # # ]: 0 : &acts->rule_acts[action_dst]);
2041 [ # # # # : 0 : else if (mask_conf && !mask_conf->handle && !mask_conf->conf)
# # ]
2042 : : ret = flow_hw_act_data_indirect_list_append
2043 : : (priv, acts, RTE_FLOW_ACTION_TYPE_INDIRECT_LIST,
2044 : : action_src, action_dst, flow_hw_reformat_action);
2045 : 0 : return ret;
2046 : : }
2047 : :
2048 : : static int
2049 : 0 : flow_dr_set_meter(struct mlx5_priv *priv,
2050 : : struct mlx5dr_rule_action *dr_rule,
2051 : : const struct rte_flow_action_indirect_list *action_conf)
2052 : : {
2053 : 0 : const struct mlx5_indlst_legacy *legacy_obj =
2054 : : (typeof(legacy_obj))action_conf->handle;
2055 : 0 : struct mlx5_aso_mtr_pool *mtr_pool = priv->hws_mpool;
2056 : 0 : uint32_t act_idx = (uint32_t)(uintptr_t)legacy_obj->handle;
2057 : 0 : uint32_t mtr_id = act_idx & (RTE_BIT32(MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
2058 : 0 : struct mlx5_aso_mtr *aso_mtr = mlx5_ipool_get(mtr_pool->idx_pool, mtr_id);
2059 : :
2060 [ # # ]: 0 : if (!aso_mtr)
2061 : : return -EINVAL;
2062 : 0 : dr_rule->action = mtr_pool->action;
2063 : 0 : dr_rule->aso_meter.offset = aso_mtr->offset;
2064 : 0 : return 0;
2065 : : }
2066 : :
2067 : : __rte_always_inline static void
2068 : : flow_dr_mtr_flow_color(struct mlx5dr_rule_action *dr_rule, enum rte_color init_color)
2069 : : {
2070 : 0 : dr_rule->aso_meter.init_color =
2071 : 0 : (enum mlx5dr_action_aso_meter_color)rte_col_2_mlx5_col(init_color);
2072 : 0 : }
2073 : :
2074 : : static int
2075 : 0 : flow_hw_translate_indirect_meter(struct rte_eth_dev *dev,
2076 : : const struct mlx5_action_construct_data *act_data,
2077 : : const struct rte_flow_action *action,
2078 : : struct mlx5dr_rule_action *dr_rule)
2079 : : {
2080 : : int ret;
2081 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
2082 : 0 : const struct rte_flow_action_indirect_list *action_conf = action->conf;
2083 : 0 : const struct rte_flow_indirect_update_flow_meter_mark **flow_conf =
2084 : : (typeof(flow_conf))action_conf->conf;
2085 : :
2086 : 0 : ret = flow_dr_set_meter(priv, dr_rule, action_conf);
2087 [ # # ]: 0 : if (ret)
2088 : : return ret;
2089 [ # # ]: 0 : if (!act_data->shared_meter.conf_masked) {
2090 [ # # # # : 0 : if (flow_conf && flow_conf[0] && flow_conf[0]->init_color < RTE_COLORS)
# # ]
2091 : : flow_dr_mtr_flow_color(dr_rule, flow_conf[0]->init_color);
2092 : : }
2093 : : return 0;
2094 : : }
2095 : :
2096 : : static int
2097 : 0 : hws_table_tmpl_translate_indirect_meter(struct rte_eth_dev *dev,
2098 : : const struct rte_flow_action *action,
2099 : : const struct rte_flow_action *mask,
2100 : : struct mlx5_hw_actions *acts,
2101 : : uint16_t action_src, uint16_t action_dst)
2102 : : {
2103 : : int ret;
2104 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
2105 : 0 : const struct rte_flow_action_indirect_list *action_conf = action->conf;
2106 : 0 : const struct rte_flow_action_indirect_list *mask_conf = mask->conf;
2107 [ # # # # ]: 0 : bool is_handle_masked = mask_conf && mask_conf->handle;
2108 [ # # # # : 0 : bool is_conf_masked = mask_conf && mask_conf->conf && mask_conf->conf[0];
# # ]
2109 : 0 : struct mlx5dr_rule_action *dr_rule = &acts->rule_acts[action_dst];
2110 : :
2111 [ # # ]: 0 : if (is_handle_masked) {
2112 : 0 : ret = flow_dr_set_meter(priv, dr_rule, action->conf);
2113 [ # # ]: 0 : if (ret)
2114 : : return ret;
2115 : : }
2116 [ # # ]: 0 : if (is_conf_masked) {
2117 : : const struct
2118 : 0 : rte_flow_indirect_update_flow_meter_mark **flow_conf =
2119 : : (typeof(flow_conf))action_conf->conf;
2120 : : flow_dr_mtr_flow_color(dr_rule,
2121 [ # # ]: 0 : flow_conf[0]->init_color);
2122 : : }
2123 [ # # ]: 0 : if (!is_handle_masked || !is_conf_masked) {
2124 : : struct mlx5_action_construct_data *act_data;
2125 : :
2126 : : ret = flow_hw_act_data_indirect_list_append
2127 : : (priv, acts, RTE_FLOW_ACTION_TYPE_INDIRECT_LIST,
2128 : : action_src, action_dst, flow_hw_translate_indirect_meter);
2129 : : if (ret)
2130 : 0 : return ret;
2131 : : act_data = LIST_FIRST(&acts->act_list);
2132 : 0 : act_data->shared_meter.conf_masked = is_conf_masked;
2133 : : }
2134 : : return 0;
2135 : : }
2136 : :
2137 : : static int
2138 : : hws_table_tmpl_translate_indirect_legacy(struct rte_eth_dev *dev,
2139 : : const struct rte_flow_action *action,
2140 : : const struct rte_flow_action *mask,
2141 : : struct mlx5_hw_actions *acts,
2142 : : uint16_t action_src, uint16_t action_dst)
2143 : : {
2144 : : int ret;
2145 : : const struct rte_flow_action_indirect_list *indlst_conf = action->conf;
2146 : : struct mlx5_indlst_legacy *indlst_obj = (typeof(indlst_obj))indlst_conf->handle;
2147 : 0 : uint32_t act_idx = (uint32_t)(uintptr_t)indlst_obj->handle;
2148 : 0 : uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
2149 : :
2150 : 0 : switch (type) {
2151 : 0 : case MLX5_INDIRECT_ACTION_TYPE_METER_MARK:
2152 : 0 : ret = hws_table_tmpl_translate_indirect_meter(dev, action, mask,
2153 : : acts, action_src,
2154 : : action_dst);
2155 : 0 : break;
2156 : : default:
2157 : : ret = -EINVAL;
2158 : : break;
2159 : : }
2160 : : return ret;
2161 : : }
2162 : :
2163 : : /*
2164 : : * template .. indirect_list handle Ht conf Ct ..
2165 : : * mask .. indirect_list handle Hm conf Cm ..
2166 : : *
2167 : : * PMD requires Ht != 0 to resolve handle type.
2168 : : * If Ht was masked (Hm != 0) DR5 action will be set according to Ht and will
2169 : : * not change. Otherwise, DR5 action will be resolved during flow rule build.
2170 : : * If Ct was masked (Cm != 0), table template processing updates base
2171 : : * indirect action configuration with Ct parameters.
2172 : : */
2173 : : static int
2174 : 0 : table_template_translate_indirect_list(struct rte_eth_dev *dev,
2175 : : const struct rte_flow_action *action,
2176 : : const struct rte_flow_action *mask,
2177 : : struct mlx5_hw_actions *acts,
2178 : : uint16_t action_src, uint16_t action_dst)
2179 : : {
2180 : : int ret = 0;
2181 : : enum mlx5_indirect_list_type type;
2182 : 0 : const struct rte_flow_action_indirect_list *list_conf = action->conf;
2183 : :
2184 [ # # # # ]: 0 : if (!list_conf || !list_conf->handle)
2185 : : return -EINVAL;
2186 : : type = mlx5_get_indirect_list_type(list_conf->handle);
2187 [ # # # # ]: 0 : switch (type) {
2188 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY:
2189 [ # # ]: 0 : ret = hws_table_tmpl_translate_indirect_legacy(dev, action, mask,
2190 : : acts, action_src,
2191 : : action_dst);
2192 : : break;
2193 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR:
2194 : 0 : ret = hws_table_tmpl_translate_indirect_mirror(dev, action, mask,
2195 : : acts, action_src,
2196 : : action_dst);
2197 : 0 : break;
2198 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT:
2199 [ # # ]: 0 : if (list_conf->conf)
2200 : : return -EINVAL;
2201 : 0 : ret = hws_table_tmpl_translate_indirect_reformat(dev, action, mask,
2202 : : acts, action_src,
2203 : : action_dst);
2204 : 0 : break;
2205 : : default:
2206 : : return -EINVAL;
2207 : : }
2208 : : return ret;
2209 : : }
2210 : :
2211 : : static void
2212 : : mlx5_set_reformat_header(struct mlx5dr_action_reformat_header *hdr,
2213 : : uint8_t *encap_data,
2214 : : size_t data_size)
2215 : : {
2216 : 0 : hdr->sz = data_size;
2217 : 0 : hdr->data = encap_data;
2218 : : }
2219 : :
2220 : : static int
2221 [ # # ]: 0 : mlx5_tbl_translate_reformat(struct mlx5_priv *priv,
2222 : : struct mlx5_hw_actions *acts,
2223 : : struct rte_flow_actions_template *at,
2224 : : const struct rte_flow_item *enc_item,
2225 : : const struct rte_flow_item *enc_item_m,
2226 : : uint8_t *encap_data, uint8_t *encap_data_m,
2227 : : struct mlx5_tbl_multi_pattern_ctx *mp_ctx,
2228 : : size_t data_size, uint16_t reformat_src,
2229 : : enum mlx5dr_action_type refmt_type,
2230 : : struct rte_flow_error *error)
2231 : : {
2232 : : int mp_reformat_ix = mlx5_multi_pattern_reformat_to_index(refmt_type);
2233 : : struct mlx5dr_action_reformat_header hdr;
2234 : : uint8_t buf[MLX5_ENCAP_MAX_LEN];
2235 : : bool shared_rfmt = false;
2236 : : int ret;
2237 : :
2238 : : MLX5_ASSERT(at->reformat_off != UINT16_MAX);
2239 [ # # ]: 0 : if (enc_item) {
2240 : : MLX5_ASSERT(!encap_data);
2241 : 0 : ret = flow_dv_convert_encap_data(enc_item, buf, &data_size, error);
2242 [ # # ]: 0 : if (ret)
2243 : : return ret;
2244 : : encap_data = buf;
2245 [ # # ]: 0 : if (enc_item_m)
2246 : : shared_rfmt = true;
2247 [ # # ]: 0 : } else if (encap_data && encap_data_m) {
2248 : : shared_rfmt = true;
2249 : : }
2250 : 0 : acts->encap_decap = mlx5_malloc(MLX5_MEM_ZERO,
2251 : : sizeof(*acts->encap_decap) + data_size,
2252 : : 0, SOCKET_ID_ANY);
2253 [ # # ]: 0 : if (!acts->encap_decap)
2254 : 0 : return rte_flow_error_set(error, ENOMEM,
2255 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2256 : : NULL, "no memory for reformat context");
2257 : 0 : acts->encap_decap_pos = at->reformat_off;
2258 : 0 : acts->encap_decap->data_size = data_size;
2259 : 0 : acts->encap_decap->action_type = refmt_type;
2260 [ # # ]: 0 : if (shared_rfmt || mp_reformat_ix < 0) {
2261 : : uint16_t reformat_ix = at->reformat_off;
2262 : : /*
2263 : : * This copy is only needed in non template mode.
2264 : : * In order to create the action later.
2265 : : */
2266 : 0 : memcpy(acts->encap_decap->data, encap_data, data_size);
2267 : 0 : acts->rule_acts[reformat_ix].reformat.data = acts->encap_decap->data;
2268 : 0 : acts->rule_acts[reformat_ix].reformat.offset = 0;
2269 : 0 : acts->encap_decap->shared = true;
2270 : : } else {
2271 : : uint32_t ix;
2272 : 0 : typeof(mp_ctx->reformat[0]) *reformat = mp_ctx->reformat +
2273 : : mp_reformat_ix;
2274 : : mlx5_set_reformat_header(&hdr, encap_data, data_size);
2275 : 0 : ix = reformat->elements_num++;
2276 : 0 : reformat->reformat_hdr[ix] = hdr;
2277 : 0 : acts->rule_acts[at->reformat_off].reformat.hdr_idx = ix;
2278 : 0 : acts->encap_decap->multi_pattern = 1;
2279 : 0 : ret = __flow_hw_act_data_encap_append
2280 : 0 : (priv, acts, (at->actions + reformat_src)->type,
2281 : : reformat_src, at->reformat_off, data_size);
2282 : : if (ret)
2283 : 0 : return -rte_errno;
2284 : : mlx5_multi_pattern_activate(mp_ctx);
2285 : : }
2286 : : return 0;
2287 : : }
2288 : :
2289 : : static int
2290 : 0 : mlx5_tbl_create_reformat_action(struct mlx5_priv *priv,
2291 : : const struct rte_flow_template_table_attr *table_attr,
2292 : : struct mlx5_hw_actions *acts,
2293 : : struct rte_flow_actions_template *at,
2294 : : uint8_t *encap_data,
2295 : : size_t data_size,
2296 : : enum mlx5dr_action_type refmt_type)
2297 : : {
2298 : 0 : const struct rte_flow_attr *attr = &table_attr->flow_attr;
2299 : : bool unified_fdb = is_unified_fdb(priv);
2300 : 0 : enum mlx5dr_table_type tbl_type = get_mlx5dr_table_type(attr, table_attr->specialize,
2301 : : unified_fdb);
2302 : : struct mlx5dr_action_reformat_header hdr;
2303 : :
2304 : : mlx5_set_reformat_header(&hdr, encap_data, data_size);
2305 : 0 : uint16_t reformat_ix = at->reformat_off;
2306 : 0 : uint32_t flags = mlx5_hw_act_flag[!!attr->group][tbl_type] |
2307 : : MLX5DR_ACTION_FLAG_SHARED;
2308 : :
2309 : 0 : acts->encap_decap->action = mlx5dr_action_create_reformat(priv->dr_ctx, refmt_type,
2310 : : 1, &hdr, 0, flags);
2311 [ # # ]: 0 : if (!acts->encap_decap->action)
2312 : 0 : return -rte_errno;
2313 : 0 : acts->rule_acts[reformat_ix].action = acts->encap_decap->action;
2314 : 0 : return 0;
2315 : : }
2316 : :
2317 : : static int
2318 : 0 : mlx5_tbl_translate_modify_header(struct rte_eth_dev *dev,
2319 : : const struct mlx5_flow_template_table_cfg *cfg,
2320 : : struct mlx5_hw_actions *acts,
2321 : : struct mlx5_tbl_multi_pattern_ctx *mp_ctx,
2322 : : struct mlx5_hw_modify_header_action *mhdr,
2323 : : struct rte_flow_error *error)
2324 : : {
2325 : 0 : uint16_t mhdr_ix = mhdr->pos;
2326 : : struct mlx5dr_action_mh_pattern pattern = {
2327 : 0 : .sz = sizeof(struct mlx5_modification_cmd) * mhdr->mhdr_cmds_num
2328 : : };
2329 : :
2330 [ # # ]: 0 : if (flow_hw_validate_compiled_modify_field(dev, cfg, mhdr, error)) {
2331 : : __flow_hw_action_template_destroy(dev, acts);
2332 : 0 : return -rte_errno;
2333 : : }
2334 : 0 : acts->mhdr = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*acts->mhdr),
2335 : : 0, SOCKET_ID_ANY);
2336 [ # # ]: 0 : if (!acts->mhdr)
2337 : 0 : return rte_flow_error_set(error, ENOMEM,
2338 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2339 : : NULL, "translate modify_header: no memory for modify header context");
2340 : : rte_memcpy(acts->mhdr, mhdr, sizeof(*mhdr));
2341 [ # # ]: 0 : if (!mhdr->shared) {
2342 : 0 : pattern.data = (__be64 *)acts->mhdr->mhdr_cmds;
2343 : : typeof(mp_ctx->mh) *mh = &mp_ctx->mh;
2344 : 0 : uint32_t idx = mh->elements_num;
2345 : 0 : mh->pattern[mh->elements_num++] = pattern;
2346 : 0 : acts->mhdr->multi_pattern = 1;
2347 : 0 : acts->rule_acts[mhdr_ix].modify_header.pattern_idx = idx;
2348 : : mlx5_multi_pattern_activate(mp_ctx);
2349 : : }
2350 : : return 0;
2351 : : }
2352 : :
2353 : : static int
2354 : 0 : mlx5_tbl_ensure_shared_modify_header(struct rte_eth_dev *dev,
2355 : : const struct mlx5_flow_template_table_cfg *cfg,
2356 : : struct mlx5_hw_actions *acts,
2357 : : struct rte_flow_error *error)
2358 : : {
2359 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
2360 : : bool unified_fdb = is_unified_fdb(priv);
2361 : : const struct rte_flow_template_table_attr *table_attr = &cfg->attr;
2362 : 0 : const struct rte_flow_attr *attr = &table_attr->flow_attr;
2363 : 0 : enum mlx5dr_table_type tbl_type = get_mlx5dr_table_type(attr, table_attr->specialize,
2364 : : unified_fdb);
2365 : 0 : struct mlx5dr_action_mh_pattern pattern = {
2366 : 0 : .sz = sizeof(struct mlx5_modification_cmd) * acts->mhdr->mhdr_cmds_num
2367 : : };
2368 : 0 : uint16_t mhdr_ix = acts->mhdr->pos;
2369 : 0 : uint32_t flags = mlx5_hw_act_flag[!!attr->group][tbl_type] | MLX5DR_ACTION_FLAG_SHARED;
2370 : :
2371 : 0 : pattern.data = (__be64 *)acts->mhdr->mhdr_cmds;
2372 : 0 : acts->mhdr->action = mlx5dr_action_create_modify_header(priv->dr_ctx, 1,
2373 : : &pattern, 0, flags);
2374 [ # # ]: 0 : if (!acts->mhdr->action)
2375 : 0 : return rte_flow_error_set(error, rte_errno,
2376 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2377 : : "translate modify_header: failed to create DR action");
2378 : 0 : acts->rule_acts[mhdr_ix].action = acts->mhdr->action;
2379 : 0 : return 0;
2380 : : }
2381 : :
2382 : : static int
2383 : 0 : mlx5_create_ipv6_ext_reformat(struct rte_eth_dev *dev,
2384 : : const struct mlx5_flow_template_table_cfg *cfg,
2385 : : struct mlx5_hw_actions *acts,
2386 : : struct rte_flow_actions_template *at,
2387 : : uint8_t *push_data, uint8_t *push_data_m,
2388 : : size_t push_size, uint16_t recom_src,
2389 : : enum mlx5dr_action_type recom_type)
2390 : : {
2391 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
2392 : : bool unified_fdb = is_unified_fdb(priv);
2393 : : const struct rte_flow_template_table_attr *table_attr = &cfg->attr;
2394 : 0 : const struct rte_flow_attr *attr = &table_attr->flow_attr;
2395 : : enum mlx5dr_table_type type =
2396 : 0 : get_mlx5dr_table_type(attr, table_attr->specialize, unified_fdb);
2397 : : struct mlx5_action_construct_data *act_data;
2398 : 0 : struct mlx5dr_action_reformat_header hdr = {0};
2399 : : uint32_t flag, bulk = 0;
2400 : :
2401 : 0 : flag = mlx5_hw_act_flag[!!attr->group][type];
2402 : 0 : acts->push_remove = mlx5_malloc(MLX5_MEM_ZERO,
2403 : : sizeof(*acts->push_remove) + push_size,
2404 : : 0, SOCKET_ID_ANY);
2405 [ # # ]: 0 : if (!acts->push_remove)
2406 : : return -ENOMEM;
2407 : :
2408 [ # # # ]: 0 : switch (recom_type) {
2409 : 0 : case MLX5DR_ACTION_TYP_PUSH_IPV6_ROUTE_EXT:
2410 [ # # ]: 0 : if (!push_data || !push_size)
2411 : 0 : goto err1;
2412 [ # # ]: 0 : if (!push_data_m) {
2413 [ # # ]: 0 : bulk = rte_log2_u32(table_attr->nb_flows);
2414 : : } else {
2415 : 0 : flag |= MLX5DR_ACTION_FLAG_SHARED;
2416 : 0 : acts->push_remove->shared = 1;
2417 : : }
2418 : 0 : acts->push_remove->data_size = push_size;
2419 : 0 : memcpy(acts->push_remove->data, push_data, push_size);
2420 : 0 : hdr.data = push_data;
2421 : 0 : hdr.sz = push_size;
2422 : 0 : break;
2423 : 0 : case MLX5DR_ACTION_TYP_POP_IPV6_ROUTE_EXT:
2424 : 0 : flag |= MLX5DR_ACTION_FLAG_SHARED;
2425 : 0 : acts->push_remove->shared = 1;
2426 : 0 : break;
2427 : : default:
2428 : : break;
2429 : : }
2430 : :
2431 : 0 : acts->push_remove->action =
2432 : 0 : mlx5dr_action_create_reformat_ipv6_ext(priv->dr_ctx,
2433 : : recom_type, &hdr, bulk, flag);
2434 [ # # ]: 0 : if (!acts->push_remove->action)
2435 : 0 : goto err1;
2436 : 0 : acts->rule_acts[at->recom_off].action = acts->push_remove->action;
2437 : 0 : acts->rule_acts[at->recom_off].ipv6_ext.header = acts->push_remove->data;
2438 : 0 : acts->rule_acts[at->recom_off].ipv6_ext.offset = 0;
2439 : 0 : acts->push_remove_pos = at->recom_off;
2440 [ # # ]: 0 : if (!acts->push_remove->shared) {
2441 : 0 : act_data = __flow_hw_act_data_push_append(dev, acts,
2442 : : RTE_FLOW_ACTION_TYPE_IPV6_EXT_PUSH,
2443 : : recom_src, at->recom_off, push_size);
2444 : : if (!act_data)
2445 : 0 : goto err;
2446 : : }
2447 : : return 0;
2448 : : err:
2449 [ # # ]: 0 : if (acts->push_remove->action)
2450 : 0 : mlx5dr_action_destroy(acts->push_remove->action);
2451 : 0 : err1:
2452 [ # # ]: 0 : if (acts->push_remove) {
2453 : 0 : mlx5_free(acts->push_remove);
2454 : 0 : acts->push_remove = NULL;
2455 : : }
2456 : : return -EINVAL;
2457 : : }
2458 : :
2459 : : /**
2460 : : * Translate rte_flow actions to DR action.
2461 : : *
2462 : : * As the action template has already indicated the actions. Translate
2463 : : * the rte_flow actions to DR action if possbile. So in flow create
2464 : : * stage we will save cycles from handing the actions' organizing.
2465 : : * For the actions with limited information, need to add these to a
2466 : : * list.
2467 : : *
2468 : : * @param[in] dev
2469 : : * Pointer to the rte_eth_dev structure.
2470 : : * @param[in] cfg
2471 : : * Pointer to the table configuration.
2472 : : * @param[in/out] acts
2473 : : * Pointer to the template HW steering DR actions.
2474 : : * @param[in] at
2475 : : * Action template.
2476 : : * @param[in] nt_mode
2477 : : * Non template rule translate.
2478 : : * @param[out] error
2479 : : * Pointer to error structure.
2480 : : *
2481 : : * @return
2482 : : * 0 on success, a negative errno otherwise and rte_errno is set.
2483 : : */
2484 : : static int
2485 : 0 : __flow_hw_translate_actions_template(struct rte_eth_dev *dev,
2486 : : const struct mlx5_flow_template_table_cfg *cfg,
2487 : : struct mlx5_hw_actions *acts,
2488 : : struct rte_flow_actions_template *at,
2489 : : struct mlx5_tbl_multi_pattern_ctx *mp_ctx,
2490 : : bool nt_mode,
2491 : : struct rte_flow_error *error)
2492 : : {
2493 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
2494 : 0 : struct mlx5_hca_attr *hca_attr = &priv->sh->cdev->config.hca_attr;
2495 : 0 : const struct rte_flow_template_table_attr *table_attr = &cfg->attr;
2496 : 0 : const struct rte_flow_attr *attr = &table_attr->flow_attr;
2497 : 0 : struct rte_flow_action *actions = at->actions;
2498 : 0 : struct rte_flow_action *masks = at->masks;
2499 : : enum mlx5dr_action_type refmt_type = MLX5DR_ACTION_TYP_LAST;
2500 : : enum mlx5dr_action_type recom_type = MLX5DR_ACTION_TYP_LAST;
2501 : : const struct rte_flow_action_raw_encap *raw_encap_data;
2502 : : const struct rte_flow_action_ipv6_ext_push *ipv6_ext_data;
2503 : : const struct rte_flow_item *enc_item = NULL, *enc_item_m = NULL;
2504 : : uint16_t reformat_src = 0, recom_src = 0;
2505 : : uint8_t *encap_data = NULL, *encap_data_m = NULL;
2506 : : uint8_t *push_data = NULL, *push_data_m = NULL;
2507 : : size_t data_size = 0, push_size = 0;
2508 : : struct mlx5_hw_modify_header_action mhdr = { 0 };
2509 : 0 : struct rte_flow_error sub_error = {
2510 : : .type = RTE_FLOW_ERROR_TYPE_NONE,
2511 : : .cause = NULL,
2512 : : .message = NULL,
2513 : : };
2514 : : bool actions_end = false;
2515 : : uint32_t type;
2516 : : bool reformat_used = false;
2517 : : bool recom_used = false;
2518 : : unsigned int of_vlan_offset;
2519 : : uint32_t ct_idx;
2520 : : int ret, err;
2521 : 0 : uint32_t target_grp = 0;
2522 : : bool unified_fdb = is_unified_fdb(priv);
2523 : :
2524 : : flow_hw_modify_field_init(&mhdr, at);
2525 : 0 : type = get_mlx5dr_table_type(attr, cfg->attr.specialize, unified_fdb);
2526 [ # # ]: 0 : for (; !actions_end; actions++, masks++) {
2527 : 0 : uint64_t pos = actions - at->actions;
2528 : 0 : uint16_t src_pos = pos - at->src_off[pos];
2529 : 0 : uint16_t dr_pos = at->dr_off[pos];
2530 : :
2531 [ # # # # : 0 : switch ((int)actions->type) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
2532 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT_LIST:
2533 [ # # ]: 0 : if (!attr->group) {
2534 : 0 : DRV_LOG(ERR, "Indirect action is not supported in root table.");
2535 : 0 : goto err;
2536 : : }
2537 : 0 : ret = table_template_translate_indirect_list
2538 : : (dev, actions, masks, acts, src_pos, dr_pos);
2539 [ # # ]: 0 : if (ret)
2540 : 0 : goto err;
2541 : : break;
2542 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT:
2543 [ # # ]: 0 : if (!attr->group) {
2544 : 0 : DRV_LOG(ERR, "Indirect action is not supported in root table.");
2545 : 0 : goto err;
2546 : : }
2547 [ # # # # ]: 0 : if (actions->conf && masks->conf) {
2548 [ # # # # : 0 : if (flow_hw_shared_action_translate
# # # ]
2549 : : (dev, actions, acts, src_pos, dr_pos))
2550 : 0 : goto err;
2551 : 0 : } else if (__flow_hw_act_data_indirect_append
2552 : : (priv, acts, RTE_FLOW_ACTION_TYPE_INDIRECT,
2553 : : masks->type, src_pos, dr_pos)){
2554 : 0 : goto err;
2555 : : }
2556 : : break;
2557 : : case RTE_FLOW_ACTION_TYPE_VOID:
2558 : : break;
2559 : 0 : case RTE_FLOW_ACTION_TYPE_DROP:
2560 : 0 : acts->rule_acts[dr_pos].action =
2561 : 0 : priv->hw_drop[!!attr->group];
2562 : 0 : break;
2563 : 0 : case RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:
2564 [ # # ]: 0 : if (!attr->group) {
2565 : 0 : DRV_LOG(ERR, "Port representor is not supported in root table.");
2566 : 0 : goto err;
2567 : : }
2568 : 0 : acts->rule_acts[dr_pos].action = priv->hw_def_miss;
2569 : 0 : break;
2570 : 0 : case RTE_FLOW_ACTION_TYPE_FLAG:
2571 : 0 : acts->mark = true;
2572 : 0 : acts->rule_acts[dr_pos].tag.value =
2573 : : mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
2574 : 0 : acts->rule_acts[dr_pos].action =
2575 : 0 : priv->hw_tag[!!attr->group];
2576 : 0 : rte_atomic_fetch_add_explicit(&priv->hws_mark_refcnt, 1,
2577 : : rte_memory_order_relaxed);
2578 : 0 : flow_hw_rxq_flag_set(dev, true);
2579 : 0 : break;
2580 : 0 : case RTE_FLOW_ACTION_TYPE_MARK:
2581 : 0 : acts->mark = true;
2582 [ # # ]: 0 : if (masks->conf &&
2583 : : ((const struct rte_flow_action_mark *)
2584 [ # # ]: 0 : masks->conf)->id)
2585 : 0 : acts->rule_acts[dr_pos].tag.value =
2586 : : mlx5_flow_mark_set
2587 : : (((const struct rte_flow_action_mark *)
2588 [ # # ]: 0 : (actions->conf))->id);
2589 : : else if (__flow_hw_act_data_general_append(priv, acts,
2590 : : actions->type,
2591 : : src_pos, dr_pos))
2592 : 0 : goto err;
2593 : 0 : acts->rule_acts[dr_pos].action =
2594 : 0 : priv->hw_tag[!!attr->group];
2595 : 0 : rte_atomic_fetch_add_explicit(&priv->hws_mark_refcnt, 1,
2596 : : rte_memory_order_relaxed);
2597 : 0 : flow_hw_rxq_flag_set(dev, true);
2598 : 0 : break;
2599 : 0 : case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
2600 : 0 : acts->rule_acts[dr_pos].action =
2601 : 0 : priv->hw_push_vlan[type];
2602 [ # # # # ]: 0 : if (is_template_masked_push_vlan(masks->conf))
2603 : 0 : acts->rule_acts[dr_pos].push_vlan.vlan_hdr =
2604 : : vlan_hdr_to_be32(actions);
2605 : : else if (__flow_hw_act_data_general_append
2606 : : (priv, acts, actions->type,
2607 : : src_pos, dr_pos))
2608 : 0 : goto err;
2609 : : of_vlan_offset = is_of_vlan_pcp_present(actions) ?
2610 [ # # ]: 0 : MLX5_HW_VLAN_PUSH_PCP_IDX :
2611 : : MLX5_HW_VLAN_PUSH_VID_IDX;
2612 : 0 : actions += of_vlan_offset;
2613 : 0 : masks += of_vlan_offset;
2614 : 0 : break;
2615 : 0 : case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
2616 : 0 : acts->rule_acts[dr_pos].action =
2617 : 0 : priv->hw_pop_vlan[type];
2618 : 0 : break;
2619 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP:
2620 [ # # ]: 0 : if (masks->conf &&
2621 : : ((const struct rte_flow_action_jump *)
2622 [ # # ]: 0 : masks->conf)->group) {
2623 : 0 : uint32_t jump_group =
2624 : : ((const struct rte_flow_action_jump *)
2625 : 0 : actions->conf)->group;
2626 : 0 : acts->jump = flow_hw_jump_action_register
2627 : : (dev, cfg, jump_group, &sub_error);
2628 [ # # ]: 0 : if (!acts->jump)
2629 : 0 : goto err;
2630 : 0 : acts->rule_acts[dr_pos].action = (!!attr->group) ?
2631 [ # # ]: 0 : acts->jump->hws_action :
2632 : : acts->jump->root_action;
2633 : : } else if (__flow_hw_act_data_general_append
2634 : : (priv, acts, actions->type,
2635 : : src_pos, dr_pos)){
2636 : 0 : goto err;
2637 : : }
2638 : : break;
2639 : 0 : case RTE_FLOW_ACTION_TYPE_QUEUE:
2640 [ # # ]: 0 : if (masks->conf &&
2641 : : ((const struct rte_flow_action_queue *)
2642 [ # # ]: 0 : masks->conf)->index) {
2643 : 0 : acts->tir = flow_hw_tir_action_register
2644 : 0 : (dev, mlx5_hw_act_flag[!!attr->group][type],
2645 : : actions);
2646 [ # # ]: 0 : if (!acts->tir)
2647 : 0 : goto err;
2648 : 0 : acts->rule_acts[dr_pos].action =
2649 : 0 : acts->tir->action;
2650 : : } else if (__flow_hw_act_data_general_append
2651 : : (priv, acts, actions->type,
2652 : : src_pos, dr_pos)) {
2653 : 0 : goto err;
2654 : : }
2655 : : break;
2656 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
2657 [ # # # # ]: 0 : if (actions->conf && masks->conf) {
2658 : 0 : acts->tir = flow_hw_tir_action_register
2659 : 0 : (dev, mlx5_hw_act_flag[!!attr->group][type],
2660 : : actions);
2661 [ # # ]: 0 : if (!acts->tir)
2662 : 0 : goto err;
2663 : 0 : acts->rule_acts[dr_pos].action =
2664 : 0 : acts->tir->action;
2665 : : } else if (__flow_hw_act_data_general_append
2666 : : (priv, acts, actions->type,
2667 : : src_pos, dr_pos)) {
2668 : 0 : goto err;
2669 : : }
2670 : : break;
2671 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
2672 : : MLX5_ASSERT(!reformat_used);
2673 : 0 : enc_item = MLX5_CONST_ENCAP_ITEM(rte_flow_action_vxlan_encap,
2674 : : actions->conf);
2675 [ # # ]: 0 : if (masks->conf)
2676 : 0 : enc_item_m = MLX5_CONST_ENCAP_ITEM(rte_flow_action_vxlan_encap,
2677 : : masks->conf);
2678 : : reformat_used = true;
2679 : : reformat_src = src_pos;
2680 : : refmt_type = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;
2681 : : break;
2682 : 0 : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
2683 : : MLX5_ASSERT(!reformat_used);
2684 : 0 : enc_item = MLX5_CONST_ENCAP_ITEM(rte_flow_action_nvgre_encap,
2685 : : actions->conf);
2686 [ # # ]: 0 : if (masks->conf)
2687 : 0 : enc_item_m = MLX5_CONST_ENCAP_ITEM(rte_flow_action_nvgre_encap,
2688 : : masks->conf);
2689 : : reformat_used = true;
2690 : : reformat_src = src_pos;
2691 : : refmt_type = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;
2692 : : break;
2693 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
2694 : 0 : raw_encap_data =
2695 : : (const struct rte_flow_action_raw_encap *)
2696 : : masks->conf;
2697 [ # # ]: 0 : if (raw_encap_data)
2698 : 0 : encap_data_m = raw_encap_data->data;
2699 : 0 : raw_encap_data =
2700 : : (const struct rte_flow_action_raw_encap *)
2701 : : actions->conf;
2702 : 0 : encap_data = raw_encap_data->data;
2703 : 0 : data_size = raw_encap_data->size;
2704 [ # # ]: 0 : if (reformat_used) {
2705 : : refmt_type = data_size <
2706 : : MLX5_ENCAPSULATION_DECISION_SIZE ?
2707 [ # # ]: 0 : MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2 :
2708 : : MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3;
2709 : : } else {
2710 : : reformat_used = true;
2711 : : refmt_type =
2712 : : MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;
2713 : : }
2714 : : reformat_src = src_pos;
2715 : : break;
2716 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
2717 : : case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
2718 : : MLX5_ASSERT(!reformat_used);
2719 : : reformat_used = true;
2720 : : refmt_type = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2;
2721 : 0 : break;
2722 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
2723 : : reformat_used = true;
2724 : : refmt_type = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2;
2725 : 0 : break;
2726 : 0 : case RTE_FLOW_ACTION_TYPE_IPV6_EXT_PUSH:
2727 [ # # ]: 0 : if (!hca_attr->flex.query_match_sample_info ||
2728 : 0 : !hca_attr->flex.parse_graph_anchor ||
2729 [ # # ]: 0 : !priv->sh->srh_flex_parser.flex.mapnum) {
2730 : 0 : DRV_LOG(ERR, "SRv6 anchor is not supported.");
2731 : 0 : goto err;
2732 : : }
2733 : : MLX5_ASSERT(!recom_used && !recom_type);
2734 : : recom_used = true;
2735 : : recom_type = MLX5DR_ACTION_TYP_PUSH_IPV6_ROUTE_EXT;
2736 : 0 : ipv6_ext_data =
2737 : : (const struct rte_flow_action_ipv6_ext_push *)masks->conf;
2738 [ # # ]: 0 : if (ipv6_ext_data)
2739 : 0 : push_data_m = ipv6_ext_data->data;
2740 : 0 : ipv6_ext_data =
2741 : : (const struct rte_flow_action_ipv6_ext_push *)actions->conf;
2742 [ # # ]: 0 : if (ipv6_ext_data) {
2743 : 0 : push_data = ipv6_ext_data->data;
2744 : 0 : push_size = ipv6_ext_data->size;
2745 : : }
2746 : : recom_src = src_pos;
2747 : : break;
2748 : 0 : case RTE_FLOW_ACTION_TYPE_IPV6_EXT_REMOVE:
2749 [ # # ]: 0 : if (!hca_attr->flex.query_match_sample_info ||
2750 : 0 : !hca_attr->flex.parse_graph_anchor ||
2751 [ # # ]: 0 : !priv->sh->srh_flex_parser.flex.mapnum) {
2752 : 0 : DRV_LOG(ERR, "SRv6 anchor is not supported.");
2753 : 0 : goto err;
2754 : : }
2755 : : recom_used = true;
2756 : : recom_type = MLX5DR_ACTION_TYP_POP_IPV6_ROUTE_EXT;
2757 : : break;
2758 : 0 : case RTE_FLOW_ACTION_TYPE_SEND_TO_KERNEL:
2759 : 0 : ret = flow_hw_translate_group(dev, cfg, attr->group,
2760 : : &target_grp, &sub_error);
2761 [ # # ]: 0 : if (ret)
2762 : 0 : goto err;
2763 [ # # ]: 0 : if (target_grp == 0) {
2764 : : __flow_hw_action_template_destroy(dev, acts);
2765 : 0 : rte_flow_error_set(&sub_error, ENOTSUP,
2766 : : RTE_FLOW_ERROR_TYPE_ACTION,
2767 : : NULL,
2768 : : "Send to kernel action on root table is not supported in HW steering mode");
2769 : 0 : goto err;
2770 : : }
2771 : 0 : acts->rule_acts[dr_pos].action = priv->hw_send_to_kernel[type];
2772 : 0 : break;
2773 [ # # ]: 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
2774 : : err = flow_hw_modify_field_compile(dev, attr, actions,
2775 : : masks, acts, &mhdr,
2776 : : src_pos, &sub_error);
2777 [ # # ]: 0 : if (err)
2778 : 0 : goto err;
2779 : : break;
2780 : 0 : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
2781 [ # # ]: 0 : if (flow_hw_represented_port_compile
2782 : : (dev, attr, actions,
2783 : : masks, acts, src_pos, dr_pos, &sub_error))
2784 : 0 : goto err;
2785 : : break;
2786 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
2787 : 0 : ret = flow_hw_translate_group(dev, cfg, attr->group,
2788 : : &target_grp, &sub_error);
2789 [ # # ]: 0 : if (ret)
2790 : 0 : goto err;
2791 [ # # ]: 0 : if (target_grp == 0) {
2792 : : __flow_hw_action_template_destroy(dev, acts);
2793 : 0 : rte_flow_error_set(&sub_error, ENOTSUP,
2794 : : RTE_FLOW_ERROR_TYPE_ACTION,
2795 : : NULL,
2796 : : "Age action on root table is not supported in HW steering mode");
2797 : 0 : goto err;
2798 : : }
2799 : 0 : if (__flow_hw_act_data_general_append(priv, acts,
2800 : : actions->type,
2801 : : src_pos,
2802 : : dr_pos))
2803 : 0 : goto err;
2804 : : break;
2805 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
2806 : 0 : ret = flow_hw_translate_group(dev, cfg, attr->group,
2807 : : &target_grp, &sub_error);
2808 [ # # ]: 0 : if (ret)
2809 : 0 : goto err;
2810 [ # # ]: 0 : if (target_grp == 0) {
2811 : : __flow_hw_action_template_destroy(dev, acts);
2812 : 0 : rte_flow_error_set(&sub_error, ENOTSUP,
2813 : : RTE_FLOW_ERROR_TYPE_ACTION,
2814 : : NULL,
2815 : : "Counter action on root table is not supported in HW steering mode");
2816 : 0 : goto err;
2817 : : }
2818 [ # # ]: 0 : if ((at->action_flags & MLX5_FLOW_ACTION_AGE) ||
2819 : : (at->action_flags & MLX5_FLOW_ACTION_INDIRECT_AGE))
2820 : : /*
2821 : : * When both COUNT and AGE are requested, it is
2822 : : * saved as AGE action which creates also the
2823 : : * counter.
2824 : : */
2825 : : break;
2826 [ # # ]: 0 : if (masks->conf &&
2827 : : ((const struct rte_flow_action_count *)
2828 [ # # ]: 0 : masks->conf)->id) {
2829 [ # # ]: 0 : err = flow_hw_cnt_compile(dev, dr_pos, acts);
2830 : : if (err)
2831 : 0 : goto err;
2832 : 0 : } else if (__flow_hw_act_data_general_append
2833 : : (priv, acts, actions->type,
2834 : : src_pos, dr_pos)) {
2835 : 0 : goto err;
2836 : : }
2837 : : break;
2838 : 0 : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
2839 [ # # ]: 0 : if (masks->conf) {
2840 : 0 : ct_idx = MLX5_INDIRECT_ACTION_IDX_GET(actions->conf);
2841 : : if (flow_hw_ct_compile(dev, MLX5_HW_INV_QUEUE, ct_idx,
2842 : 0 : &acts->rule_acts[dr_pos]))
2843 : 0 : goto err;
2844 : : } else if (__flow_hw_act_data_general_append
2845 : : (priv, acts, actions->type,
2846 : : src_pos, dr_pos)) {
2847 : 0 : goto err;
2848 : : }
2849 : : break;
2850 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
2851 [ # # # # ]: 0 : if (actions->conf && masks->conf &&
2852 : : ((const struct rte_flow_action_meter_mark *)
2853 [ # # ]: 0 : masks->conf)->profile) {
2854 : : err = flow_hw_meter_mark_compile(dev,
2855 : : dr_pos, actions,
2856 : 0 : acts->rule_acts,
2857 : : &acts->mtr_id,
2858 : : MLX5_HW_INV_QUEUE,
2859 : : &sub_error);
2860 : : if (err)
2861 : 0 : goto err;
2862 : : } else if (__flow_hw_act_data_general_append(priv, acts,
2863 : : actions->type,
2864 : : src_pos,
2865 : : dr_pos))
2866 : 0 : goto err;
2867 : : break;
2868 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
2869 : : /* Internal, can be skipped. */
2870 [ # # ]: 0 : if (!!attr->group) {
2871 : 0 : DRV_LOG(ERR, "DEFAULT MISS action is only"
2872 : : " supported in root table.");
2873 : 0 : goto err;
2874 : : }
2875 : 0 : acts->rule_acts[dr_pos].action = priv->hw_def_miss;
2876 : 0 : break;
2877 : 0 : case RTE_FLOW_ACTION_TYPE_NAT64:
2878 [ # # ]: 0 : if (masks->conf &&
2879 [ # # ]: 0 : ((const struct rte_flow_action_nat64 *)masks->conf)->type) {
2880 : 0 : const struct rte_flow_action_nat64 *nat64_c =
2881 : : (const struct rte_flow_action_nat64 *)actions->conf;
2882 : :
2883 : 0 : acts->rule_acts[dr_pos].action =
2884 : 0 : priv->action_nat64[type][nat64_c->type];
2885 : : } else if (__flow_hw_act_data_general_append(priv, acts,
2886 : : actions->type,
2887 : : src_pos, dr_pos))
2888 : 0 : goto err;
2889 : : break;
2890 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
2891 [ # # ]: 0 : if (masks->conf &&
2892 : : ((const struct rte_flow_action_jump_to_table_index *)
2893 [ # # ]: 0 : masks->conf)->table) {
2894 : 0 : struct rte_flow_template_table *jump_table =
2895 : : ((const struct rte_flow_action_jump_to_table_index *)
2896 : 0 : actions->conf)->table;
2897 : 0 : acts->rule_acts[dr_pos].jump_to_matcher.offset =
2898 : : ((const struct rte_flow_action_jump_to_table_index *)
2899 : 0 : actions->conf)->index;
2900 [ # # ]: 0 : if (likely(!rte_flow_template_table_resizable(dev->data->port_id,
2901 : : &jump_table->cfg.attr))) {
2902 : 0 : acts->rule_acts[dr_pos].action =
2903 : 0 : jump_table->matcher_info[0].jump;
2904 : : } else {
2905 : : uint32_t selector;
2906 : 0 : rte_rwlock_read_lock(&jump_table->matcher_replace_rwlk);
2907 : 0 : selector = jump_table->matcher_selector;
2908 : 0 : acts->rule_acts[dr_pos].action =
2909 : 0 : jump_table->matcher_info[selector].jump;
2910 : : rte_rwlock_read_unlock(&jump_table->matcher_replace_rwlk);
2911 : : }
2912 : : } else if (__flow_hw_act_data_general_append
2913 : : (priv, acts, actions->type,
2914 : : src_pos, dr_pos)){
2915 : 0 : goto err;
2916 : : }
2917 : : break;
2918 : 0 : case RTE_FLOW_ACTION_TYPE_END:
2919 : : actions_end = true;
2920 : 0 : break;
2921 : : default:
2922 : : break;
2923 : : }
2924 : : }
2925 [ # # ]: 0 : if (mhdr.pos != UINT16_MAX) {
2926 : 0 : ret = mlx5_tbl_translate_modify_header(dev, cfg, acts, mp_ctx, &mhdr, &sub_error);
2927 [ # # ]: 0 : if (ret)
2928 : 0 : goto err;
2929 [ # # # # ]: 0 : if (!nt_mode && mhdr.shared) {
2930 : 0 : ret = mlx5_tbl_ensure_shared_modify_header(dev, cfg, acts, &sub_error);
2931 [ # # ]: 0 : if (ret)
2932 : 0 : goto err;
2933 : : }
2934 : : }
2935 [ # # ]: 0 : if (reformat_used) {
2936 : 0 : ret = mlx5_tbl_translate_reformat(priv, acts, at,
2937 : : enc_item, enc_item_m,
2938 : : encap_data, encap_data_m,
2939 : : mp_ctx, data_size,
2940 : : reformat_src,
2941 : : refmt_type, &sub_error);
2942 [ # # ]: 0 : if (ret)
2943 : 0 : goto err;
2944 [ # # # # ]: 0 : if (!nt_mode && acts->encap_decap->shared) {
2945 : 0 : ret = mlx5_tbl_create_reformat_action(priv, table_attr, acts, at,
2946 : : encap_data, data_size,
2947 : : refmt_type);
2948 [ # # ]: 0 : if (ret)
2949 : 0 : goto err;
2950 : : }
2951 : : }
2952 [ # # ]: 0 : if (recom_used) {
2953 : : MLX5_ASSERT(at->recom_off != UINT16_MAX);
2954 : 0 : ret = mlx5_create_ipv6_ext_reformat(dev, cfg, acts, at, push_data,
2955 : : push_data_m, push_size, recom_src,
2956 : : recom_type);
2957 [ # # ]: 0 : if (ret)
2958 : 0 : goto err;
2959 : : }
2960 : : return 0;
2961 : 0 : err:
2962 : : /* If rte_errno was not initialized and reached error state. */
2963 [ # # ]: 0 : if (!rte_errno)
2964 : 0 : rte_errno = EINVAL;
2965 : 0 : err = rte_errno;
2966 : : __flow_hw_action_template_destroy(dev, acts);
2967 [ # # # # ]: 0 : if (error != NULL && sub_error.type != RTE_FLOW_ERROR_TYPE_NONE) {
2968 : : rte_memcpy(error, &sub_error, sizeof(sub_error));
2969 : 0 : return -EINVAL;
2970 : : }
2971 : 0 : return rte_flow_error_set(error, err,
2972 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2973 : : "fail to create rte table");
2974 : : }
2975 : :
2976 : : /**
2977 : : * Translate rte_flow actions to DR action.
2978 : : *
2979 : : * As the action template has already indicated the actions. Translate
2980 : : * the rte_flow actions to DR action if possible. So in flow create
2981 : : * stage we will save cycles from handing the actions' organizing.
2982 : : * For the actions with limited information, need to add these to a
2983 : : * list.
2984 : : *
2985 : : * @param[in] dev
2986 : : * Pointer to the rte_eth_dev structure.
2987 : : * @param[in] cfg
2988 : : * Pointer to the table configuration.
2989 : : * @param[in/out] acts
2990 : : * Pointer to the template HW steering DR actions.
2991 : : * @param[in] at
2992 : : * Action template.
2993 : : * @param[out] error
2994 : : * Pointer to error structure.
2995 : : *
2996 : : * @return
2997 : : * 0 on success, a negative errno otherwise and rte_errno is set.
2998 : : */
2999 : : static int
3000 : : flow_hw_translate_actions_template(struct rte_eth_dev *dev,
3001 : : const struct mlx5_flow_template_table_cfg *cfg,
3002 : : struct mlx5_hw_actions *acts,
3003 : : struct rte_flow_actions_template *at,
3004 : : struct mlx5_tbl_multi_pattern_ctx *mp_ctx,
3005 : : struct rte_flow_error *error)
3006 : : {
3007 : 0 : return __flow_hw_translate_actions_template(dev, cfg, acts, at, mp_ctx, false, error);
3008 : : }
3009 : :
3010 : : static __rte_always_inline struct mlx5dr_rule_action *
3011 : : flow_hw_get_dr_action_buffer(struct mlx5_priv *priv,
3012 : : struct rte_flow_template_table *table,
3013 : : uint8_t action_template_index,
3014 : : uint32_t queue)
3015 : : {
3016 : 0 : uint32_t offset = action_template_index * priv->nb_queue + queue;
3017 : :
3018 : 0 : return &table->rule_acts[offset].acts[0];
3019 : : }
3020 : :
3021 : : static void
3022 : 0 : flow_hw_populate_rule_acts_caches(struct rte_eth_dev *dev,
3023 : : struct rte_flow_template_table *table,
3024 : : uint8_t at_idx)
3025 : : {
3026 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
3027 : : uint32_t q;
3028 : :
3029 [ # # ]: 0 : for (q = 0; q < priv->nb_queue; ++q) {
3030 : : struct mlx5dr_rule_action *rule_acts =
3031 : 0 : flow_hw_get_dr_action_buffer(priv, table, at_idx, q);
3032 : :
3033 [ # # ]: 0 : rte_memcpy(rule_acts, table->ats[at_idx].acts.rule_acts,
3034 : : sizeof(table->ats[at_idx].acts.rule_acts));
3035 : : }
3036 : 0 : }
3037 : :
3038 : : /**
3039 : : * Translate rte_flow actions to DR action.
3040 : : *
3041 : : * @param[in] dev
3042 : : * Pointer to the rte_eth_dev structure.
3043 : : * @param[in] tbl
3044 : : * Pointer to the flow template table.
3045 : : * @param[out] error
3046 : : * Pointer to error structure.
3047 : : *
3048 : : * @return
3049 : : * 0 on success, negative value otherwise and rte_errno is set.
3050 : : */
3051 : : static int
3052 : 0 : flow_hw_translate_all_actions_templates(struct rte_eth_dev *dev,
3053 : : struct rte_flow_template_table *tbl,
3054 : : struct rte_flow_error *error)
3055 : : {
3056 : : int ret;
3057 : : uint32_t i;
3058 : :
3059 [ # # ]: 0 : for (i = 0; i < tbl->nb_action_templates; i++) {
3060 [ # # ]: 0 : if (flow_hw_translate_actions_template(dev, &tbl->cfg,
3061 : : &tbl->ats[i].acts,
3062 : : tbl->ats[i].action_template,
3063 : : &tbl->mpctx, error))
3064 : 0 : goto err;
3065 : 0 : flow_hw_populate_rule_acts_caches(dev, tbl, i);
3066 : : }
3067 [ # # ]: 0 : ret = mlx5_tbl_multi_pattern_process(dev, tbl, &tbl->mpctx.segments[0],
3068 : : rte_log2_u32(tbl->cfg.attr.nb_flows),
3069 : : error);
3070 [ # # ]: 0 : if (ret)
3071 : 0 : goto err;
3072 : : return 0;
3073 : : err:
3074 [ # # ]: 0 : while (i--)
3075 : 0 : __flow_hw_action_template_destroy(dev, &tbl->ats[i].acts);
3076 : : return -1;
3077 : : }
3078 : :
3079 : : /**
3080 : : * Get shared indirect action.
3081 : : *
3082 : : * @param[in] dev
3083 : : * Pointer to the rte_eth_dev data structure.
3084 : : * @param[in] act_data
3085 : : * Pointer to the recorded action construct data.
3086 : : * @param[in] item_flags
3087 : : * The matcher itme_flags used for RSS lookup.
3088 : : * @param[in] rule_act
3089 : : * Pointer to the shared action's destination rule DR action.
3090 : : *
3091 : : * @return
3092 : : * 0 on success, negative value otherwise and rte_errno is set.
3093 : : */
3094 : : static __rte_always_inline int
3095 : : flow_hw_shared_action_get(struct rte_eth_dev *dev,
3096 : : struct mlx5_action_construct_data *act_data,
3097 : : const uint64_t item_flags,
3098 : : struct mlx5dr_rule_action *rule_act)
3099 : : {
3100 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
3101 : 0 : struct mlx5_flow_rss_desc rss_desc = { 0 };
3102 : 0 : uint64_t hash_fields = 0;
3103 : : uint32_t hrxq_idx = 0;
3104 : : struct mlx5_hrxq *hrxq = NULL;
3105 : : int act_type = act_data->type;
3106 : :
3107 : : switch (act_type) {
3108 : : case MLX5_RTE_FLOW_ACTION_TYPE_RSS:
3109 : 0 : rss_desc.level = act_data->shared_rss.level;
3110 : 0 : rss_desc.types = act_data->shared_rss.types;
3111 : 0 : rss_desc.symmetric_hash_function = act_data->shared_rss.symmetric_hash_function;
3112 : 0 : flow_dv_hashfields_set(item_flags, &rss_desc, &hash_fields);
3113 : 0 : hrxq_idx = flow_dv_action_rss_hrxq_lookup
3114 : : (dev, act_data->shared_rss.idx, hash_fields);
3115 [ # # # # : 0 : if (hrxq_idx)
# # # # #
# # # # #
# # # # #
# ]
3116 : 0 : hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
3117 : : hrxq_idx);
3118 [ # # # # : 0 : if (hrxq) {
# # # # #
# # # # #
# # # # #
# ]
3119 : 0 : rule_act->action = hrxq->action;
3120 : : return 0;
3121 : : }
3122 : : break;
3123 : : default:
3124 : : DRV_LOG(WARNING, "Unsupported shared action type:%d",
3125 : : act_data->type);
3126 : : break;
3127 : : }
3128 : : return -1;
3129 : : }
3130 : :
3131 : : static void
3132 : 0 : flow_hw_construct_quota(struct mlx5_priv *priv,
3133 : : struct mlx5dr_rule_action *rule_act, uint32_t qid)
3134 : : {
3135 : 0 : rule_act->action = priv->quota_ctx.dr_action;
3136 : 0 : rule_act->aso_meter.offset = qid - 1;
3137 : 0 : rule_act->aso_meter.init_color =
3138 : : MLX5DR_ACTION_ASO_METER_COLOR_GREEN;
3139 : 0 : }
3140 : :
3141 : : /**
3142 : : * Construct shared indirect action.
3143 : : *
3144 : : * @param[in] dev
3145 : : * Pointer to the rte_eth_dev data structure.
3146 : : * @param[in] queue
3147 : : * The flow creation queue index.
3148 : : * @param[in] action
3149 : : * Pointer to the shared indirect rte_flow action.
3150 : : * @param[in] table
3151 : : * Pointer to the flow table.
3152 : : * @param[in] item_flags
3153 : : * Item flags.
3154 : : * @param[in] action_flags
3155 : : * Actions bit-map detected in this template.
3156 : : * @param[in, out] flow
3157 : : * Pointer to the flow containing the counter.
3158 : : * @param[in] rule_act
3159 : : * Pointer to the shared action's destination rule DR action.
3160 : : *
3161 : : * @return
3162 : : * 0 on success, negative value otherwise and rte_errno is set.
3163 : : */
3164 : : static __rte_always_inline int
3165 : : flow_hw_shared_action_construct(struct rte_eth_dev *dev, uint32_t queue,
3166 : : const struct rte_flow_action *action,
3167 : : struct rte_flow_template_table *table __rte_unused,
3168 : : const uint64_t item_flags, uint64_t action_flags,
3169 : : struct rte_flow_hw *flow,
3170 : : struct mlx5dr_rule_action *rule_act)
3171 : : {
3172 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
3173 : 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
3174 : : struct mlx5_action_construct_data act_data;
3175 : : struct mlx5_shared_action_rss *shared_rss;
3176 : : struct mlx5_aso_mtr *aso_mtr;
3177 : : struct mlx5_age_info *age_info;
3178 : : struct mlx5_hws_age_param *param;
3179 : : struct rte_flow_hw_aux *aux;
3180 : 0 : uint32_t act_idx = (uint32_t)(uintptr_t)action->conf;
3181 : 0 : uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
3182 : 0 : uint32_t idx = act_idx &
3183 : : ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
3184 : : cnt_id_t age_cnt;
3185 : :
3186 : : memset(&act_data, 0, sizeof(act_data));
3187 [ # # # # : 0 : switch (type) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3188 : 0 : case MLX5_INDIRECT_ACTION_TYPE_RSS:
3189 : 0 : act_data.type = MLX5_RTE_FLOW_ACTION_TYPE_RSS;
3190 : 0 : shared_rss = mlx5_ipool_get
3191 : 0 : (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
3192 [ # # # # : 0 : if (!shared_rss)
# # # # #
# ]
3193 : : return -1;
3194 : 0 : act_data.shared_rss.idx = idx;
3195 : 0 : act_data.shared_rss.level = shared_rss->origin.level;
3196 : 0 : act_data.shared_rss.types = !shared_rss->origin.types ?
3197 [ # # # # : 0 : RTE_ETH_RSS_IP :
# # # # #
# ]
3198 : : shared_rss->origin.types;
3199 : 0 : act_data.shared_rss.symmetric_hash_function =
3200 : 0 : MLX5_RSS_IS_SYMM(shared_rss->origin.func);
3201 : :
3202 : : if (flow_hw_shared_action_get
3203 : : (dev, &act_data, item_flags, rule_act))
3204 : : return -1;
3205 : : break;
3206 : 0 : case MLX5_INDIRECT_ACTION_TYPE_COUNT:
3207 : 0 : if (mlx5_hws_cnt_pool_get_action_offset(priv->hws_cpool,
3208 : : act_idx,
3209 : : &rule_act->action,
3210 : : &rule_act->counter.offset))
3211 : : return -1;
3212 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_CNT_ID;
3213 : 0 : flow->cnt_id = act_idx;
3214 : : break;
3215 : 0 : case MLX5_INDIRECT_ACTION_TYPE_AGE:
3216 : 0 : aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
3217 : : /*
3218 : : * Save the index with the indirect type, to recognize
3219 : : * it in flow destroy.
3220 : : */
3221 : : mlx5_flow_hw_aux_set_age_idx(flow, aux, act_idx);
3222 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_AGE_IDX;
3223 [ # # # # : 0 : if (action_flags & MLX5_FLOW_ACTION_INDIRECT_COUNT)
# # # # #
# ]
3224 : : /*
3225 : : * The mutual update for idirect AGE & COUNT will be
3226 : : * performed later after we have ID for both of them.
3227 : : */
3228 : : break;
3229 : 0 : age_info = GET_PORT_AGE_INFO(priv);
3230 : 0 : param = mlx5_ipool_get(age_info->ages_ipool, idx);
3231 [ # # # # : 0 : if (param == NULL)
# # # # #
# ]
3232 : : return -1;
3233 [ # # # # : 0 : if (action_flags & MLX5_FLOW_ACTION_COUNT) {
# # # # #
# ]
3234 [ # # # # : 0 : if (mlx5_hws_cnt_pool_get(priv->hws_cpool,
# # # # #
# # # # #
# # # # #
# ]
3235 : : ¶m->queue_id, &age_cnt,
3236 : : idx) < 0)
3237 : : return -1;
3238 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_CNT_ID;
3239 : 0 : flow->cnt_id = age_cnt;
3240 : 0 : param->nb_cnts++;
3241 : : } else {
3242 : : /*
3243 : : * Get the counter of this indirect AGE or create one
3244 : : * if doesn't exist.
3245 : : */
3246 : : age_cnt = mlx5_hws_age_cnt_get(priv, param, idx);
3247 [ # # # # : 0 : if (age_cnt == 0)
# # # # #
# ]
3248 : : return -1;
3249 : : }
3250 : 0 : if (mlx5_hws_cnt_pool_get_action_offset(priv->hws_cpool,
3251 : : age_cnt, &rule_act->action,
3252 : : &rule_act->counter.offset))
3253 : : return -1;
3254 : : break;
3255 : : case MLX5_INDIRECT_ACTION_TYPE_CT:
3256 : : if (flow_hw_ct_compile(dev, queue, idx, rule_act))
3257 : : return -1;
3258 : : break;
3259 : 0 : case MLX5_INDIRECT_ACTION_TYPE_METER_MARK:
3260 : : /* Find ASO object. */
3261 : 0 : aso_mtr = mlx5_ipool_get(pool->idx_pool, idx);
3262 [ # # # # : 0 : if (!aso_mtr)
# # # # #
# ]
3263 : : return -1;
3264 : 0 : rule_act->action = pool->action;
3265 : 0 : rule_act->aso_meter.offset = aso_mtr->offset;
3266 : : break;
3267 : 0 : case MLX5_INDIRECT_ACTION_TYPE_QUOTA:
3268 : 0 : flow_hw_construct_quota(priv, rule_act, idx);
3269 : : break;
3270 : 0 : default:
3271 : 0 : DRV_LOG(WARNING, "Unsupported shared action type:%d", type);
3272 : : break;
3273 : : }
3274 : : return 0;
3275 : : }
3276 : :
3277 : : static __rte_always_inline int
3278 : : flow_hw_mhdr_cmd_is_nop(const struct mlx5_modification_cmd *cmd)
3279 : : {
3280 : : struct mlx5_modification_cmd cmd_he = {
3281 : 0 : .data0 = rte_be_to_cpu_32(cmd->data0),
3282 : : .data1 = 0,
3283 : : };
3284 : :
3285 : 0 : return cmd_he.action_type == MLX5_MODIFICATION_TYPE_NOP;
3286 : : }
3287 : :
3288 : : /**
3289 : : * Construct flow action array.
3290 : : *
3291 : : * For action template contains dynamic actions, these actions need to
3292 : : * be updated according to the rte_flow action during flow creation.
3293 : : *
3294 : : * @param[in] dev
3295 : : * Pointer to the rte_eth_dev structure.
3296 : : * @param[in] job
3297 : : * Pointer to job descriptor.
3298 : : * @param[in] hw_acts
3299 : : * Pointer to translated actions from template.
3300 : : * @param[in] it_idx
3301 : : * Item template index the action template refer to.
3302 : : * @param[in] actions
3303 : : * Array of rte_flow action need to be checked.
3304 : : * @param[in] rule_acts
3305 : : * Array of DR rule actions to be used during flow creation..
3306 : : * @param[in] acts_num
3307 : : * Pointer to the real acts_num flow has.
3308 : : *
3309 : : * @return
3310 : : * 0 on success, negative value otherwise and rte_errno is set.
3311 : : */
3312 : : static __rte_always_inline int
3313 : : flow_hw_modify_field_construct(struct mlx5_modification_cmd *mhdr_cmd,
3314 : : struct mlx5_action_construct_data *act_data,
3315 : : const struct mlx5_hw_actions *hw_acts,
3316 : : const struct rte_flow_action *action)
3317 : : {
3318 : 0 : const struct rte_flow_action_modify_field *mhdr_action = action->conf;
3319 : 0 : uint8_t values[16] = { 0 };
3320 : : unaligned_uint32_t *value_p;
3321 : : uint32_t i;
3322 : : struct field_modify_info *field;
3323 : :
3324 [ # # # # : 0 : if (!hw_acts->mhdr)
# # # # #
# ]
3325 : : return -1;
3326 [ # # # # : 0 : if (hw_acts->mhdr->shared || act_data->modify_header.shared)
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3327 : : return 0;
3328 : : MLX5_ASSERT(mhdr_action->operation == RTE_FLOW_MODIFY_SET ||
3329 : : mhdr_action->operation == RTE_FLOW_MODIFY_ADD);
3330 [ # # # # : 0 : if (mhdr_action->src.field != RTE_FLOW_FIELD_VALUE &&
# # # # #
# ]
3331 : : mhdr_action->src.field != RTE_FLOW_FIELD_POINTER)
3332 : : return 0;
3333 [ # # # # : 0 : if (mhdr_action->src.field == RTE_FLOW_FIELD_VALUE)
# # # # #
# ]
3334 [ # # # # : 0 : rte_memcpy(values, &mhdr_action->src.value, sizeof(values));
# # # # #
# ]
3335 : : else
3336 [ # # # # : 0 : rte_memcpy(values, mhdr_action->src.pvalue, sizeof(values));
# # # # #
# ]
3337 [ # # # # : 0 : if (mhdr_action->dst.field == RTE_FLOW_FIELD_META ||
# # # # #
# ]
3338 [ # # # # : 0 : mhdr_action->dst.field == RTE_FLOW_FIELD_TAG ||
# # # # #
# ]
3339 [ # # # # : 0 : mhdr_action->dst.field == RTE_FLOW_FIELD_METER_COLOR ||
# # # # #
# ]
3340 : : mhdr_action->dst.field == (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG) {
3341 : 0 : uint8_t tag_index = flow_tag_index_get(&mhdr_action->dst);
3342 : :
3343 : : value_p = (unaligned_uint32_t *)values;
3344 [ # # # # : 0 : if (mhdr_action->dst.field == RTE_FLOW_FIELD_TAG &&
# # # # #
# # # # #
# # # # #
# ]
3345 : : tag_index == RTE_PMD_MLX5_LINEAR_HASH_TAG_INDEX)
3346 [ # # # # : 0 : *value_p = rte_cpu_to_be_32(*value_p << 16);
# # # # #
# ]
3347 : : else
3348 [ # # # # : 0 : *value_p = rte_cpu_to_be_32(*value_p);
# # # # #
# ]
3349 [ # # # # : 0 : } else if (mhdr_action->dst.field == RTE_FLOW_FIELD_GTP_PSC_QFI ||
# # # # #
# ]
3350 : : mhdr_action->dst.field == RTE_FLOW_FIELD_GENEVE_OPT_TYPE) {
3351 : : uint32_t tmp;
3352 : :
3353 : : /*
3354 : : * Both QFI and Geneve option type are passed as an uint8_t integer,
3355 : : * but it is accessed through a 2nd least significant byte of a 32-bit
3356 : : * field in modify header command.
3357 : : */
3358 : 0 : tmp = values[0];
3359 : : value_p = (unaligned_uint32_t *)values;
3360 [ # # # # : 0 : *value_p = rte_cpu_to_be_32(tmp << 8);
# # # # #
# ]
3361 : : }
3362 : 0 : i = act_data->modify_header.mhdr_cmds_off;
3363 : 0 : field = act_data->modify_header.field;
3364 : : do {
3365 : : uint32_t off_b;
3366 : : uint32_t mask;
3367 : : uint32_t data;
3368 : : const uint8_t *mask_src;
3369 : :
3370 [ # # # # : 0 : if (i >= act_data->modify_header.mhdr_cmds_end)
# # # # #
# # # # #
# # # # #
# ]
3371 : : return -1;
3372 [ # # # # : 0 : if (flow_hw_mhdr_cmd_is_nop(&mhdr_cmd[i])) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3373 : 0 : ++i;
3374 : 0 : continue;
3375 : : }
3376 : 0 : mask_src = (const uint8_t *)act_data->modify_header.mask;
3377 : 0 : mask = flow_dv_fetch_field(mask_src + field->offset, field->size);
3378 [ # # # # : 0 : if (!mask) {
# # # # #
# # # # #
# # # # #
# ]
3379 : 0 : ++field;
3380 : 0 : continue;
3381 : : }
3382 : 0 : off_b = rte_bsf32(mask);
3383 : 0 : data = flow_dv_fetch_field(values + field->offset, field->size);
3384 : : /*
3385 : : * IPv6 DSCP uses OUT_IPV6_TRAFFIC_CLASS as ID but it starts from 2
3386 : : * bits left. Shift the data left for IPv6 DSCP
3387 : : */
3388 [ # # # # : 0 : if (field->id == MLX5_MODI_OUT_IPV6_TRAFFIC_CLASS &&
# # # # #
# # # #
# ]
3389 [ # # # # : 0 : mhdr_action->dst.field == RTE_FLOW_FIELD_IPV6_DSCP)
# # ]
3390 : 0 : data <<= MLX5_IPV6_HDR_DSCP_SHIFT;
3391 : 0 : data = (data & mask) >> off_b;
3392 [ # # # # : 0 : mhdr_cmd[i++].data1 = rte_cpu_to_be_32(data);
# # # # #
# # # # #
# # # # #
# ]
3393 : 0 : ++field;
3394 [ # # # # : 0 : } while (field->size);
# # # # #
# # # # #
# # # # #
# ]
3395 : : return 0;
3396 : : }
3397 : :
3398 : : /**
3399 : : * Release any actions allocated for the flow rule during actions construction.
3400 : : *
3401 : : * @param[in] flow
3402 : : * Pointer to flow structure.
3403 : : */
3404 : : static void
3405 : 0 : flow_hw_release_actions(struct rte_eth_dev *dev,
3406 : : uint32_t queue,
3407 : : struct rte_flow_hw *flow)
3408 : : {
3409 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
3410 : 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
3411 : 0 : struct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
3412 : :
3413 [ # # ]: 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_FATE_JUMP)
3414 : 0 : flow_hw_jump_release(dev, flow->jump);
3415 [ # # ]: 0 : else if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_FATE_HRXQ)
3416 : 0 : mlx5_hrxq_obj_release(dev, flow->hrxq);
3417 [ # # ]: 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_CNT_ID)
3418 : 0 : flow_hw_age_count_release(priv, queue, flow, NULL);
3419 [ # # ]: 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_MTR_ID)
3420 : 0 : mlx5_ipool_free(pool->idx_pool, mlx5_flow_hw_aux_get_mtr_id(flow, aux));
3421 : 0 : }
3422 : :
3423 : : /**
3424 : : * Construct flow action array.
3425 : : *
3426 : : * For action template contains dynamic actions, these actions need to
3427 : : * be updated according to the rte_flow action during flow creation.
3428 : : *
3429 : : * @param[in] dev
3430 : : * Pointer to the rte_eth_dev structure.
3431 : : * @param[in] flow
3432 : : * Pointer to flow structure.
3433 : : * @param[in] ap
3434 : : * Pointer to container for temporarily constructed actions' parameters.
3435 : : * @param[in] hw_acts
3436 : : * Pointer to translated actions from template.
3437 : : * @param[in] items_flags
3438 : : * Item flags.
3439 : : * @param[in] table
3440 : : * Pointer to the template table.
3441 : : * @param[in] actions
3442 : : * Array of rte_flow action need to be checked.
3443 : : * @param[in] rule_acts
3444 : : * Array of DR rule actions to be used during flow creation..
3445 : : * @param[in] acts_num
3446 : : * Pointer to the real acts_num flow has.
3447 : : *
3448 : : * @return
3449 : : * 0 on success, negative value otherwise and rte_errno is set.
3450 : : */
3451 : : static __rte_always_inline int
3452 : : flow_hw_actions_construct(struct rte_eth_dev *dev,
3453 : : struct rte_flow_hw *flow,
3454 : : struct mlx5_flow_hw_action_params *ap,
3455 : : const struct mlx5_hw_action_template *hw_at,
3456 : : uint64_t item_flags,
3457 : : struct rte_flow_template_table *table,
3458 : : const struct rte_flow_action actions[],
3459 : : struct mlx5dr_rule_action *rule_acts,
3460 : : uint32_t queue,
3461 : : struct rte_flow_error *error)
3462 : : {
3463 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
3464 : 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
3465 : : struct mlx5_action_construct_data *act_data;
3466 : 0 : const struct rte_flow_actions_template *at = hw_at->action_template;
3467 : : const struct mlx5_hw_actions *hw_acts = &hw_at->acts;
3468 : : const struct rte_flow_action *action;
3469 : : const struct rte_flow_action_raw_encap *raw_encap_data;
3470 : : const struct rte_flow_action_ipv6_ext_push *ipv6_push;
3471 : : const struct rte_flow_item *enc_item = NULL;
3472 : : const struct rte_flow_action_ethdev *port_action = NULL;
3473 : : const struct rte_flow_action_age *age = NULL;
3474 : : const struct rte_flow_action_nat64 *nat64_c = NULL;
3475 : 0 : struct rte_flow_attr attr = {
3476 : : .ingress = 1,
3477 : : };
3478 : : uint32_t ft_flag;
3479 : : int ret;
3480 : 0 : size_t encap_len = 0;
3481 : : uint32_t age_idx = 0;
3482 : : uint32_t mtr_idx = 0;
3483 : : struct mlx5_aso_mtr *aso_mtr;
3484 : : struct mlx5_multi_pattern_segment *mp_segment = NULL;
3485 : : struct rte_flow_hw_aux *aux;
3486 : :
3487 : 0 : attr.group = table->grp->group_id;
3488 : 0 : ft_flag = mlx5_hw_act_flag[!!table->grp->group_id][table->type];
3489 : 0 : if (table->type >= MLX5DR_TABLE_TYPE_FDB && table->type < MLX5DR_TABLE_TYPE_MAX) {
3490 : 0 : attr.transfer = 1;
3491 : : attr.ingress = 1;
3492 [ # # # # : 0 : } else if (table->type == MLX5DR_TABLE_TYPE_NIC_TX) {
# # # # #
# ]
3493 : 0 : attr.egress = 1;
3494 : 0 : attr.ingress = 0;
3495 : : } else {
3496 : : attr.ingress = 1;
3497 : : }
3498 [ # # # # : 0 : if (hw_acts->mhdr && hw_acts->mhdr->mhdr_cmds_num > 0 && !hw_acts->mhdr->shared) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3499 : 0 : uint16_t pos = hw_acts->mhdr->pos;
3500 : :
3501 : 0 : mp_segment = mlx5_multi_pattern_segment_find(table, flow->res_idx);
3502 [ # # # # : 0 : if (!mp_segment || !mp_segment->mhdr_action)
# # # # #
# # # # #
# # # # #
# ]
3503 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3504 : : NULL, "No modify header action found");
3505 : 0 : rule_acts[pos].action = mp_segment->mhdr_action;
3506 : : /* offset is relative to DR action */
3507 : 0 : rule_acts[pos].modify_header.offset =
3508 : 0 : flow->res_idx - mp_segment->head_index;
3509 : 0 : rule_acts[pos].modify_header.data =
3510 : 0 : (uint8_t *)ap->mhdr_cmd;
3511 : : MLX5_ASSERT(hw_acts->mhdr->mhdr_cmds_num <= MLX5_MHDR_MAX_CMD);
3512 : 0 : rte_memcpy(ap->mhdr_cmd, hw_acts->mhdr->mhdr_cmds,
3513 [ # # # # : 0 : sizeof(*ap->mhdr_cmd) * hw_acts->mhdr->mhdr_cmds_num);
# # # # #
# ]
3514 : : }
3515 [ # # # # : 0 : LIST_FOREACH(act_data, &hw_acts->act_list, next) {
# # # # #
# ]
3516 : : uint32_t jump_group;
3517 : : uint32_t tag;
3518 : : struct mlx5_hw_jump_action *jump;
3519 : : struct mlx5_hrxq *hrxq;
3520 : : uint32_t ct_idx;
3521 : : cnt_id_t cnt_id;
3522 : : uint32_t *cnt_queue;
3523 : : uint32_t mtr_id;
3524 : : struct rte_flow_template_table *jump_table;
3525 : :
3526 : 0 : action = &actions[act_data->action_src];
3527 : : /*
3528 : : * action template construction replaces
3529 : : * OF_SET_VLAN_VID with MODIFY_FIELD
3530 : : */
3531 : 0 : if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)
3532 : : MLX5_ASSERT(act_data->type ==
3533 : : RTE_FLOW_ACTION_TYPE_MODIFY_FIELD);
3534 : : else
3535 : : MLX5_ASSERT(action->type ==
3536 : : RTE_FLOW_ACTION_TYPE_INDIRECT ||
3537 : : (int)action->type == act_data->type);
3538 [ # # # # : 0 : switch ((int)act_data->type) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3539 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT_LIST:
3540 : 0 : act_data->indirect_list_cb(dev, act_data, action,
3541 : 0 : &rule_acts[act_data->action_dst]);
3542 : 0 : break;
3543 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT:
3544 : 0 : if (flow_hw_shared_action_construct
3545 : : (dev, queue, action, table,
3546 : 0 : item_flags, at->action_flags, flow,
3547 [ # # # # : 0 : &rule_acts[act_data->action_dst]))
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3548 : 0 : goto error;
3549 : : break;
3550 : : case RTE_FLOW_ACTION_TYPE_VOID:
3551 : : break;
3552 : 0 : case RTE_FLOW_ACTION_TYPE_MARK:
3553 : 0 : tag = mlx5_flow_mark_set
3554 : : (((const struct rte_flow_action_mark *)
3555 : 0 : (action->conf))->id);
3556 : 0 : rule_acts[act_data->action_dst].tag.value = tag;
3557 : 0 : break;
3558 : 0 : case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
3559 : 0 : rule_acts[act_data->action_dst].push_vlan.vlan_hdr =
3560 : 0 : vlan_hdr_to_be32(action);
3561 : 0 : break;
3562 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP:
3563 : 0 : jump_group = ((const struct rte_flow_action_jump *)
3564 : 0 : action->conf)->group;
3565 : 0 : jump = flow_hw_jump_action_register
3566 : 0 : (dev, &table->cfg, jump_group, NULL);
3567 [ # # # # : 0 : if (!jump)
# # # # #
# ]
3568 : 0 : goto error;
3569 : 0 : rule_acts[act_data->action_dst].action =
3570 [ # # # # : 0 : (!!attr.group) ? jump->hws_action : jump->root_action;
# # # # #
# ]
3571 : 0 : flow->jump = jump;
3572 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_FATE_JUMP;
3573 : 0 : break;
3574 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
3575 : : case RTE_FLOW_ACTION_TYPE_QUEUE:
3576 : 0 : hrxq = flow_hw_tir_action_register(dev, ft_flag, action);
3577 [ # # # # : 0 : if (!hrxq)
# # # # #
# ]
3578 : 0 : goto error;
3579 : 0 : rule_acts[act_data->action_dst].action = hrxq->action;
3580 : 0 : flow->hrxq = hrxq;
3581 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_FATE_HRXQ;
3582 : 0 : break;
3583 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_RSS:
3584 : 0 : if (flow_hw_shared_action_get
3585 : : (dev, act_data, item_flags,
3586 : 0 : &rule_acts[act_data->action_dst]))
3587 : 0 : goto error;
3588 : : break;
3589 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
3590 : 0 : enc_item = ((const struct rte_flow_action_vxlan_encap *)
3591 : 0 : action->conf)->definition;
3592 [ # # # # : 0 : if (flow_dv_convert_encap_data(enc_item, ap->encap_data, &encap_len, NULL))
# # # # #
# ]
3593 : 0 : goto error;
3594 : : break;
3595 : 0 : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
3596 : 0 : enc_item = ((const struct rte_flow_action_nvgre_encap *)
3597 : 0 : action->conf)->definition;
3598 [ # # # # : 0 : if (flow_dv_convert_encap_data(enc_item, ap->encap_data, &encap_len, NULL))
# # # # #
# ]
3599 : 0 : goto error;
3600 : : break;
3601 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
3602 : 0 : raw_encap_data =
3603 : : (const struct rte_flow_action_raw_encap *)
3604 : : action->conf;
3605 : : MLX5_ASSERT(raw_encap_data->size == act_data->encap.len);
3606 [ # # # # : 0 : if (unlikely(act_data->encap.len > MLX5_ENCAP_MAX_LEN))
# # # # #
# ]
3607 : : return -1;
3608 [ # # # # : 0 : rte_memcpy(ap->encap_data, raw_encap_data->data, act_data->encap.len);
# # # # #
# ]
3609 : : break;
3610 : 0 : case RTE_FLOW_ACTION_TYPE_IPV6_EXT_PUSH:
3611 : 0 : ipv6_push =
3612 : : (const struct rte_flow_action_ipv6_ext_push *)action->conf;
3613 : : MLX5_ASSERT(ipv6_push->size == act_data->ipv6_ext.len);
3614 [ # # # # : 0 : if (unlikely(act_data->ipv6_ext.len > MLX5_PUSH_MAX_LEN))
# # # # #
# ]
3615 : : return -1;
3616 [ # # # # : 0 : rte_memcpy(ap->ipv6_push_data, ipv6_push->data,
# # # # #
# ]
3617 : : act_data->ipv6_ext.len);
3618 : : break;
3619 : 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
3620 [ # # # # : 0 : if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)
# # # # #
# ]
3621 : 0 : ret = flow_hw_set_vlan_vid_construct(dev, ap->mhdr_cmd,
3622 : : act_data,
3623 : : hw_acts,
3624 : : action);
3625 : : else
3626 [ # # # # : 0 : ret = flow_hw_modify_field_construct(ap->mhdr_cmd,
# # # # #
# ]
3627 : : act_data,
3628 : : hw_acts,
3629 : : action);
3630 [ # # # # : 0 : if (ret)
# # # # #
# ]
3631 : 0 : goto error;
3632 : : break;
3633 : 0 : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
3634 : 0 : port_action = action->conf;
3635 [ # # # # : 0 : if (!priv->hw_vport[port_action->port_id])
# # # # #
# ]
3636 : 0 : goto error;
3637 : 0 : rule_acts[act_data->action_dst].action =
3638 : : priv->hw_vport[port_action->port_id];
3639 : 0 : break;
3640 : 0 : case RTE_FLOW_ACTION_TYPE_QUOTA:
3641 : 0 : flow_hw_construct_quota(priv,
3642 : 0 : rule_acts + act_data->action_dst,
3643 : : act_data->shared_meter.id);
3644 : 0 : break;
3645 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
3646 : 0 : aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
3647 : 0 : age = action->conf;
3648 : : /*
3649 : : * First, create the AGE parameter, then create its
3650 : : * counter later:
3651 : : * Regular counter - in next case.
3652 : : * Indirect counter - update it after the loop.
3653 : : */
3654 : 0 : age_idx = mlx5_hws_age_action_create(priv, queue, 0,
3655 : : age,
3656 : : flow->res_idx,
3657 : : error);
3658 [ # # # # : 0 : if (age_idx == 0)
# # # # #
# ]
3659 : 0 : goto error;
3660 : : mlx5_flow_hw_aux_set_age_idx(flow, aux, age_idx);
3661 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_AGE_IDX;
3662 [ # # # # : 0 : if (at->action_flags & MLX5_FLOW_ACTION_INDIRECT_COUNT)
# # # # #
# ]
3663 : : /*
3664 : : * When AGE uses indirect counter, no need to
3665 : : * create counter but need to update it with the
3666 : : * AGE parameter, will be done after the loop.
3667 : : */
3668 : : break;
3669 : : /* Fall-through. */
3670 : : case RTE_FLOW_ACTION_TYPE_COUNT:
3671 : : cnt_queue = mlx5_hws_cnt_get_queue(priv, &queue);
3672 : : ret = mlx5_hws_cnt_pool_get(priv->hws_cpool, cnt_queue, &cnt_id, age_idx);
3673 [ # # # # : 0 : if (ret != 0) {
# # # # #
# ]
3674 : 0 : rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_ACTION,
3675 : : action, "Failed to allocate flow counter");
3676 : 0 : goto error;
3677 : : }
3678 : 0 : ret = mlx5_hws_cnt_pool_get_action_offset
3679 : : (priv->hws_cpool,
3680 : : cnt_id,
3681 : : &rule_acts[act_data->action_dst].action,
3682 : 0 : &rule_acts[act_data->action_dst].counter.offset
3683 : : );
3684 : : if (ret != 0)
3685 : : goto error;
3686 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_CNT_ID;
3687 : 0 : flow->cnt_id = cnt_id;
3688 : 0 : break;
3689 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
3690 : 0 : ret = mlx5_hws_cnt_pool_get_action_offset
3691 : : (priv->hws_cpool,
3692 : : act_data->shared_counter.id,
3693 : : &rule_acts[act_data->action_dst].action,
3694 : 0 : &rule_acts[act_data->action_dst].counter.offset
3695 : : );
3696 : : if (ret != 0)
3697 : : goto error;
3698 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_CNT_ID;
3699 : 0 : flow->cnt_id = act_data->shared_counter.id;
3700 : 0 : break;
3701 : 0 : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
3702 : 0 : ct_idx = MLX5_INDIRECT_ACTION_IDX_GET(action->conf);
3703 : 0 : if (flow_hw_ct_compile(dev, queue, ct_idx,
3704 : 0 : &rule_acts[act_data->action_dst]))
3705 : 0 : goto error;
3706 : : break;
3707 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_METER_MARK:
3708 : 0 : mtr_id = act_data->shared_meter.id &
3709 : : ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
3710 : : /* Find ASO object. */
3711 : 0 : aso_mtr = mlx5_ipool_get(pool->idx_pool, mtr_id);
3712 [ # # # # : 0 : if (!aso_mtr)
# # # # #
# ]
3713 : 0 : goto error;
3714 : 0 : rule_acts[act_data->action_dst].action =
3715 : 0 : pool->action;
3716 : 0 : rule_acts[act_data->action_dst].aso_meter.offset =
3717 : 0 : aso_mtr->offset;
3718 : 0 : break;
3719 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
3720 : : /*
3721 : : * Allocate meter directly will slow down flow
3722 : : * insertion rate.
3723 : : */
3724 : : ret = flow_hw_meter_mark_compile(dev,
3725 : 0 : act_data->action_dst, action,
3726 : : rule_acts, &mtr_idx, MLX5_HW_INV_QUEUE, error);
3727 : : if (ret != 0)
3728 : 0 : goto error;
3729 : 0 : aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
3730 : : mlx5_flow_hw_aux_set_mtr_id(flow, aux, mtr_idx);
3731 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_MTR_ID;
3732 : 0 : break;
3733 : 0 : case RTE_FLOW_ACTION_TYPE_NAT64:
3734 : 0 : nat64_c = action->conf;
3735 : : MLX5_ASSERT(table->type < MLX5DR_TABLE_TYPE_MAX);
3736 : 0 : rule_acts[act_data->action_dst].action =
3737 : 0 : priv->action_nat64[table->type][nat64_c->type];
3738 : 0 : break;
3739 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
3740 : 0 : jump_table = ((const struct rte_flow_action_jump_to_table_index *)
3741 : 0 : action->conf)->table;
3742 [ # # # # : 0 : if (likely(!rte_flow_template_table_resizable(dev->data->port_id,
# # # # #
# ]
3743 : : &table->cfg.attr))) {
3744 : 0 : rule_acts[act_data->action_dst].action =
3745 : 0 : jump_table->matcher_info[0].jump;
3746 : : } else {
3747 : : uint32_t selector;
3748 : 0 : rte_rwlock_read_lock(&table->matcher_replace_rwlk);
3749 : 0 : selector = table->matcher_selector;
3750 : 0 : rule_acts[act_data->action_dst].action =
3751 : 0 : jump_table->matcher_info[selector].jump;
3752 : 0 : rte_rwlock_read_unlock(&table->matcher_replace_rwlk);
3753 : : }
3754 : 0 : rule_acts[act_data->action_dst].jump_to_matcher.offset =
3755 : : ((const struct rte_flow_action_jump_to_table_index *)
3756 : 0 : action->conf)->index;
3757 : 0 : break;
3758 : : default:
3759 : : break;
3760 : : }
3761 : : }
3762 [ # # # # : 0 : if (at->action_flags & MLX5_FLOW_ACTION_INDIRECT_COUNT) {
# # # # #
# ]
3763 : : /* If indirect count is used, then CNT_ID flag should be set. */
3764 : : MLX5_ASSERT(flow->flags & MLX5_FLOW_HW_FLOW_FLAG_CNT_ID);
3765 [ # # # # : 0 : if (at->action_flags & MLX5_FLOW_ACTION_INDIRECT_AGE) {
# # # # #
# ]
3766 : : /* If indirect AGE is used, then AGE_IDX flag should be set. */
3767 : : MLX5_ASSERT(flow->flags & MLX5_FLOW_HW_FLOW_FLAG_AGE_IDX);
3768 : 0 : aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
3769 : 0 : age_idx = mlx5_flow_hw_aux_get_age_idx(flow, aux) &
3770 : : MLX5_HWS_AGE_IDX_MASK;
3771 [ # # # # : 0 : if (mlx5_hws_cnt_age_get(priv->hws_cpool, flow->cnt_id) != age_idx)
# # # # #
# # # # #
# # # # #
# ]
3772 : : /*
3773 : : * This is first use of this indirect counter
3774 : : * for this indirect AGE, need to increase the
3775 : : * number of counters.
3776 : : */
3777 : : mlx5_hws_age_nb_cnt_increase(priv, age_idx);
3778 : : }
3779 : : /*
3780 : : * Update this indirect counter the indirect/direct AGE in which
3781 : : * using it.
3782 : : */
3783 [ # # # # : 0 : mlx5_hws_cnt_age_set(priv->hws_cpool, flow->cnt_id, age_idx);
# # # # #
# ]
3784 : : }
3785 [ # # # # : 0 : if (hw_acts->encap_decap && !hw_acts->encap_decap->shared) {
# # # # #
# # # # #
# # # # #
# ]
3786 [ # # # # : 0 : int ix = mlx5_multi_pattern_reformat_to_index(hw_acts->encap_decap->action_type);
# # # # #
# ]
3787 : 0 : struct mlx5dr_rule_action *ra = &rule_acts[hw_acts->encap_decap_pos];
3788 : :
3789 [ # # # # : 0 : if (ix < 0)
# # # # #
# ]
3790 : 0 : goto error;
3791 [ # # # # : 0 : if (!mp_segment)
# # # # #
# ]
3792 : 0 : mp_segment = mlx5_multi_pattern_segment_find(table, flow->res_idx);
3793 [ # # # # : 0 : if (!mp_segment || !mp_segment->reformat_action[ix])
# # # # #
# # # # #
# # # # #
# ]
3794 : 0 : goto error;
3795 : 0 : ra->action = mp_segment->reformat_action[ix];
3796 : : /* reformat offset is relative to selected DR action */
3797 : 0 : ra->reformat.offset = flow->res_idx - mp_segment->head_index;
3798 : 0 : ra->reformat.data = ap->encap_data;
3799 : : }
3800 [ # # # # : 0 : if (hw_acts->push_remove && !hw_acts->push_remove->shared) {
# # # # #
# # # # #
# # # # #
# ]
3801 : 0 : rule_acts[hw_acts->push_remove_pos].ipv6_ext.offset =
3802 : 0 : flow->res_idx - 1;
3803 : 0 : rule_acts[hw_acts->push_remove_pos].ipv6_ext.header = ap->ipv6_push_data;
3804 : : }
3805 [ # # # # : 0 : if (mlx5_hws_cnt_id_valid(hw_acts->cnt_id)) {
# # # # #
# ]
3806 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_CNT_ID;
3807 : 0 : flow->cnt_id = hw_acts->cnt_id;
3808 : : }
3809 : : return 0;
3810 : :
3811 : 0 : error:
3812 : 0 : flow_hw_release_actions(dev, queue, flow);
3813 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3814 : : NULL, "Action construction failed");
3815 : : }
3816 : :
3817 : : static const struct rte_flow_item *
3818 : 0 : flow_hw_get_rule_items(struct rte_eth_dev *dev,
3819 : : const struct rte_flow_template_table *table,
3820 : : const struct rte_flow_item items[],
3821 : : uint8_t pattern_template_index,
3822 : : struct mlx5_flow_hw_pattern_params *pp)
3823 : : {
3824 : 0 : struct rte_flow_pattern_template *pt = table->its[pattern_template_index];
3825 : :
3826 : : /* Only one implicit item can be added to flow rule pattern. */
3827 : : MLX5_ASSERT(!pt->implicit_port || !pt->implicit_tag);
3828 : : /* At least one item was allocated in pattern params for items. */
3829 : : MLX5_ASSERT(MLX5_HW_MAX_ITEMS >= 1);
3830 [ # # ]: 0 : if (pt->implicit_port) {
3831 [ # # ]: 0 : if (pt->orig_item_nb + 1 > MLX5_HW_MAX_ITEMS) {
3832 : 0 : rte_errno = ENOMEM;
3833 : 0 : return NULL;
3834 : : }
3835 : : /* Set up represented port item in pattern params. */
3836 : 0 : pp->port_spec = (struct rte_flow_item_ethdev){
3837 : 0 : .port_id = dev->data->port_id,
3838 : : };
3839 : 0 : pp->items[0] = (struct rte_flow_item){
3840 : : .type = RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT,
3841 : 0 : .spec = &pp->port_spec,
3842 : : };
3843 [ # # ]: 0 : rte_memcpy(&pp->items[1], items, sizeof(*items) * pt->orig_item_nb);
3844 : 0 : return pp->items;
3845 [ # # ]: 0 : } else if (pt->implicit_tag) {
3846 [ # # ]: 0 : if (pt->orig_item_nb + 1 > MLX5_HW_MAX_ITEMS) {
3847 : 0 : rte_errno = ENOMEM;
3848 : 0 : return NULL;
3849 : : }
3850 : : /* Set up tag item in pattern params. */
3851 : 0 : pp->tag_spec = (struct rte_flow_item_tag){
3852 : : .data = flow_hw_tx_tag_regc_value(dev),
3853 : : };
3854 : 0 : pp->items[0] = (struct rte_flow_item){
3855 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_TAG,
3856 : 0 : .spec = &pp->tag_spec,
3857 : : };
3858 : 0 : rte_memcpy(&pp->items[1], items, sizeof(*items) * pt->orig_item_nb);
3859 : 0 : return pp->items;
3860 : : } else {
3861 : : return items;
3862 : : }
3863 : : }
3864 : :
3865 : : /**
3866 : : * Enqueue HW steering flow creation.
3867 : : *
3868 : : * The flow will be applied to the HW only if the postpone bit is not set or
3869 : : * the extra push function is called.
3870 : : * The flow creation status should be checked from dequeue result.
3871 : : *
3872 : : * @param[in] dev
3873 : : * Pointer to the rte_eth_dev structure.
3874 : : * @param[in] queue
3875 : : * The queue to create the flow.
3876 : : * @param[in] attr
3877 : : * Pointer to the flow operation attributes.
3878 : : * @param[in] table
3879 : : * Pointer to the template table.
3880 : : * @param[in] insertion_type
3881 : : * Insertion type for flow rules.
3882 : : * @param[in] rule_index
3883 : : * The item pattern flow follows from the table.
3884 : : * @param[in] items
3885 : : * Items with flow spec value.
3886 : : * @param[in] pattern_template_index
3887 : : * The item pattern flow follows from the table.
3888 : : * @param[in] actions
3889 : : * Action with flow spec value.
3890 : : * @param[in] action_template_index
3891 : : * The action pattern flow follows from the table.
3892 : : * @param[in] user_data
3893 : : * Pointer to the user_data.
3894 : : * @param[out] error
3895 : : * Pointer to error structure.
3896 : : *
3897 : : * @return
3898 : : * Flow pointer on success, NULL otherwise and rte_errno is set.
3899 : : */
3900 : : static __rte_always_inline struct rte_flow *
3901 : : flow_hw_async_flow_create_generic(struct rte_eth_dev *dev,
3902 : : uint32_t queue,
3903 : : const struct rte_flow_op_attr *attr,
3904 : : struct rte_flow_template_table *table,
3905 : : enum rte_flow_table_insertion_type insertion_type,
3906 : : uint32_t rule_index,
3907 : : const struct rte_flow_item items[],
3908 : : uint8_t pattern_template_index,
3909 : : const struct rte_flow_action actions[],
3910 : : uint8_t action_template_index,
3911 : : void *user_data,
3912 : : struct rte_flow_error *error)
3913 : : {
3914 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
3915 : 0 : struct mlx5dr_rule_attr rule_attr = {
3916 : : .queue_id = queue,
3917 : : .user_data = user_data,
3918 : 0 : .burst = attr->postpone,
3919 : : };
3920 : : struct mlx5dr_rule_action *rule_acts;
3921 : : struct rte_flow_hw *flow = NULL;
3922 : : const struct rte_flow_item *rule_items;
3923 : 0 : struct rte_flow_error sub_error = { 0 };
3924 : 0 : uint32_t flow_idx = 0;
3925 : 0 : uint32_t res_idx = 0;
3926 : : int ret;
3927 : :
3928 : 0 : if (mlx5_fp_debug_enabled()) {
3929 [ # # # # : 0 : if (flow_hw_async_create_validate(dev, queue, table, insertion_type, rule_index,
# # ]
3930 : : items, pattern_template_index, actions, action_template_index, error))
3931 : : return NULL;
3932 : : }
3933 : 0 : flow = mlx5_ipool_malloc(table->flow, &flow_idx);
3934 [ # # # # : 0 : if (!flow) {
# # ]
3935 : 0 : rte_errno = ENOMEM;
3936 : 0 : goto error;
3937 : : }
3938 : : rule_acts = flow_hw_get_dr_action_buffer(priv, table, action_template_index, queue);
3939 : : /*
3940 : : * Set the table here in order to know the destination table
3941 : : * when free the flow afterward.
3942 : : */
3943 : 0 : flow->table = table;
3944 : 0 : flow->mt_idx = pattern_template_index;
3945 : 0 : flow->idx = flow_idx;
3946 [ # # # # : 0 : if (table->resource) {
# # ]
3947 : 0 : mlx5_ipool_malloc(table->resource, &res_idx);
3948 [ # # # # : 0 : if (!res_idx) {
# # ]
3949 : 0 : rte_errno = ENOMEM;
3950 : 0 : goto error;
3951 : : }
3952 : 0 : flow->res_idx = res_idx;
3953 : : } else {
3954 : 0 : flow->res_idx = flow_idx;
3955 : : }
3956 : 0 : flow->flags = 0;
3957 : : /*
3958 : : * Set the flow operation type here in order to know if the flow memory
3959 : : * should be freed or not when get the result from dequeue.
3960 : : */
3961 : 0 : flow->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_CREATE;
3962 : 0 : flow->user_data = user_data;
3963 : 0 : rule_attr.user_data = flow;
3964 : : /*
3965 : : * Indexed pool returns 1-based indices, but mlx5dr expects 0-based indices
3966 : : * for rule insertion hints.
3967 : : */
3968 [ # # # # ]: 0 : flow->rule_idx = (rule_index == UINT32_MAX) ? flow->res_idx - 1 : rule_index;
3969 : 0 : rule_attr.rule_idx = flow->rule_idx;
3970 : : /*
3971 : : * Construct the flow actions based on the input actions.
3972 : : * The implicitly appended action is always fixed, like metadata
3973 : : * copy action from FDB to NIC Rx.
3974 : : * No need to copy and contrust a new "actions" list based on the
3975 : : * user's input, in order to save the cost.
3976 : : */
3977 [ # # # # : 0 : if (flow_hw_actions_construct(dev, flow, &priv->hw_q[queue].ap,
# # ]
3978 : 0 : &table->ats[action_template_index],
3979 [ # # # # : 0 : table->its[pattern_template_index]->item_flags,
# # ]
3980 : : flow->table, actions,
3981 : : rule_acts, queue, &sub_error))
3982 : 0 : goto error;
3983 : 0 : rule_items = flow_hw_get_rule_items(dev, table, items,
3984 : 0 : pattern_template_index, &priv->hw_q[queue].pp);
3985 [ # # # # : 0 : if (!rule_items)
# # ]
3986 : 0 : goto error;
3987 [ # # # # : 0 : if (likely(!rte_flow_template_table_resizable(dev->data->port_id, &table->cfg.attr))) {
# # ]
3988 : 0 : ret = mlx5dr_rule_create(table->matcher_info[0].matcher,
3989 : : pattern_template_index, rule_items,
3990 : : action_template_index, rule_acts,
3991 : : &rule_attr,
3992 : 0 : (struct mlx5dr_rule *)flow->rule);
3993 : : } else {
3994 : 0 : struct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
3995 : : uint32_t selector;
3996 : :
3997 : 0 : flow->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_CREATE;
3998 : 0 : rte_rwlock_read_lock(&table->matcher_replace_rwlk);
3999 : 0 : selector = table->matcher_selector;
4000 : 0 : ret = mlx5dr_rule_create(table->matcher_info[selector].matcher,
4001 : : pattern_template_index, rule_items,
4002 : : action_template_index, rule_acts,
4003 : : &rule_attr,
4004 : 0 : (struct mlx5dr_rule *)flow->rule);
4005 : 0 : rte_rwlock_read_unlock(&table->matcher_replace_rwlk);
4006 : 0 : aux->matcher_selector = selector;
4007 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_MATCHER_SELECTOR;
4008 : : }
4009 [ # # # # : 0 : if (likely(!ret)) {
# # ]
4010 : 0 : flow_hw_q_inc_flow_ops(priv, queue);
4011 : 0 : return (struct rte_flow *)flow;
4012 : : }
4013 : 0 : error:
4014 [ # # # # : 0 : if (table->resource && res_idx)
# # # # #
# # # ]
4015 : 0 : mlx5_ipool_free(table->resource, res_idx);
4016 [ # # # # : 0 : if (flow_idx)
# # ]
4017 : 0 : mlx5_ipool_free(table->flow, flow_idx);
4018 [ # # # # : 0 : if (sub_error.cause != RTE_FLOW_ERROR_TYPE_NONE && error != NULL)
# # # # #
# # # ]
4019 : 0 : *error = sub_error;
4020 : : else
4021 : 0 : rte_flow_error_set(error, rte_errno,
4022 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4023 : : "fail to create rte flow");
4024 : : return NULL;
4025 : : }
4026 : :
4027 : : static struct rte_flow *
4028 : 0 : flow_hw_async_flow_create(struct rte_eth_dev *dev,
4029 : : uint32_t queue,
4030 : : const struct rte_flow_op_attr *attr,
4031 : : struct rte_flow_template_table *table,
4032 : : const struct rte_flow_item items[],
4033 : : uint8_t pattern_template_index,
4034 : : const struct rte_flow_action actions[],
4035 : : uint8_t action_template_index,
4036 : : void *user_data,
4037 : : struct rte_flow_error *error)
4038 : : {
4039 : : uint32_t rule_index = UINT32_MAX;
4040 : :
4041 [ # # ]: 0 : return flow_hw_async_flow_create_generic(dev, queue, attr, table,
4042 : : RTE_FLOW_TABLE_INSERTION_TYPE_PATTERN, rule_index,
4043 : : items, pattern_template_index, actions, action_template_index,
4044 : : user_data, error);
4045 : : }
4046 : :
4047 : : static struct rte_flow *
4048 : 0 : flow_hw_async_flow_create_by_index(struct rte_eth_dev *dev,
4049 : : uint32_t queue,
4050 : : const struct rte_flow_op_attr *attr,
4051 : : struct rte_flow_template_table *table,
4052 : : uint32_t rule_index,
4053 : : const struct rte_flow_action actions[],
4054 : : uint8_t action_template_index,
4055 : : void *user_data,
4056 : : struct rte_flow_error *error)
4057 : : {
4058 : 0 : struct rte_flow_item items[] = {{.type = RTE_FLOW_ITEM_TYPE_END,}};
4059 : : uint8_t pattern_template_index = 0;
4060 : :
4061 [ # # ]: 0 : return flow_hw_async_flow_create_generic(dev, queue, attr, table,
4062 : : RTE_FLOW_TABLE_INSERTION_TYPE_INDEX, rule_index,
4063 : : items, pattern_template_index, actions, action_template_index,
4064 : : user_data, error);
4065 : : }
4066 : :
4067 : : static struct rte_flow *
4068 : 0 : flow_hw_async_flow_create_by_index_with_pattern(struct rte_eth_dev *dev,
4069 : : uint32_t queue,
4070 : : const struct rte_flow_op_attr *attr,
4071 : : struct rte_flow_template_table *table,
4072 : : uint32_t rule_index,
4073 : : const struct rte_flow_item items[],
4074 : : uint8_t pattern_template_index,
4075 : : const struct rte_flow_action actions[],
4076 : : uint8_t action_template_index,
4077 : : void *user_data,
4078 : : struct rte_flow_error *error)
4079 : : {
4080 [ # # ]: 0 : return flow_hw_async_flow_create_generic(dev, queue, attr, table,
4081 : : RTE_FLOW_TABLE_INSERTION_TYPE_INDEX_WITH_PATTERN, rule_index,
4082 : : items, pattern_template_index, actions, action_template_index,
4083 : : user_data, error);
4084 : : }
4085 : :
4086 : : /**
4087 : : * Enqueue HW steering flow update.
4088 : : *
4089 : : * The flow will be applied to the HW only if the postpone bit is not set or
4090 : : * the extra push function is called.
4091 : : * The flow destruction status should be checked from dequeue result.
4092 : : *
4093 : : * @param[in] dev
4094 : : * Pointer to the rte_eth_dev structure.
4095 : : * @param[in] queue
4096 : : * The queue to destroy the flow.
4097 : : * @param[in] attr
4098 : : * Pointer to the flow operation attributes.
4099 : : * @param[in] flow
4100 : : * Pointer to the flow to be destroyed.
4101 : : * @param[in] actions
4102 : : * Action with flow spec value.
4103 : : * @param[in] action_template_index
4104 : : * The action pattern flow follows from the table.
4105 : : * @param[in] user_data
4106 : : * Pointer to the user_data.
4107 : : * @param[out] error
4108 : : * Pointer to error structure.
4109 : : *
4110 : : * @return
4111 : : * 0 on success, negative value otherwise and rte_errno is set.
4112 : : */
4113 : : static int
4114 : 0 : flow_hw_async_flow_update(struct rte_eth_dev *dev,
4115 : : uint32_t queue,
4116 : : const struct rte_flow_op_attr *attr,
4117 : : struct rte_flow *flow,
4118 : : const struct rte_flow_action actions[],
4119 : : uint8_t action_template_index,
4120 : : void *user_data,
4121 : : struct rte_flow_error *error)
4122 : : {
4123 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4124 : 0 : struct mlx5dr_rule_attr rule_attr = {
4125 : : .queue_id = queue,
4126 : : .user_data = user_data,
4127 : 0 : .burst = attr->postpone,
4128 : : };
4129 : : struct mlx5dr_rule_action *rule_acts;
4130 : : struct rte_flow_hw *of = (struct rte_flow_hw *)flow;
4131 : : struct rte_flow_hw *nf;
4132 : : struct rte_flow_hw_aux *aux;
4133 : 0 : struct rte_flow_template_table *table = of->table;
4134 : 0 : uint32_t res_idx = 0;
4135 : : int ret;
4136 : :
4137 [ # # ]: 0 : if (mlx5_fp_debug_enabled()) {
4138 [ # # ]: 0 : if (flow_hw_async_update_validate(dev, queue, of, actions, action_template_index,
4139 : : error))
4140 : 0 : return -rte_errno;
4141 : : }
4142 : 0 : aux = mlx5_flow_hw_aux(dev->data->port_id, of);
4143 [ # # ]: 0 : nf = &aux->upd_flow;
4144 : : memset(nf, 0, sizeof(struct rte_flow_hw));
4145 : 0 : rule_acts = flow_hw_get_dr_action_buffer(priv, table, action_template_index, queue);
4146 : : /*
4147 : : * Set the table here in order to know the destination table
4148 : : * when free the flow afterwards.
4149 : : */
4150 : 0 : nf->table = table;
4151 : 0 : nf->mt_idx = of->mt_idx;
4152 : 0 : nf->idx = of->idx;
4153 [ # # ]: 0 : if (table->resource) {
4154 : 0 : mlx5_ipool_malloc(table->resource, &res_idx);
4155 [ # # ]: 0 : if (!res_idx) {
4156 : 0 : rte_errno = ENOMEM;
4157 : 0 : goto error;
4158 : : }
4159 : 0 : nf->res_idx = res_idx;
4160 : : } else {
4161 : 0 : nf->res_idx = of->res_idx;
4162 : : }
4163 : 0 : nf->flags = 0;
4164 : : /* Indicate the construction function to set the proper fields. */
4165 : 0 : nf->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE;
4166 : : /*
4167 : : * Indexed pool returns 1-based indices, but mlx5dr expects 0-based indices
4168 : : * for rule insertion hints.
4169 : : * If there is only one STE, the update will be atomic by nature.
4170 : : */
4171 : 0 : nf->rule_idx = nf->res_idx - 1;
4172 : 0 : rule_attr.rule_idx = nf->rule_idx;
4173 : : /*
4174 : : * Construct the flow actions based on the input actions.
4175 : : * The implicitly appended action is always fixed, like metadata
4176 : : * copy action from FDB to NIC Rx.
4177 : : * No need to copy and contrust a new "actions" list based on the
4178 : : * user's input, in order to save the cost.
4179 : : */
4180 [ # # ]: 0 : if (flow_hw_actions_construct(dev, nf, &priv->hw_q[queue].ap,
4181 : 0 : &table->ats[action_template_index],
4182 [ # # ]: 0 : table->its[nf->mt_idx]->item_flags,
4183 : : table, actions,
4184 : : rule_acts, queue, error)) {
4185 : 0 : rte_errno = EINVAL;
4186 : 0 : goto error;
4187 : : }
4188 : : /*
4189 : : * Set the flow operation type here in order to know if the flow memory
4190 : : * should be freed or not when get the result from dequeue.
4191 : : */
4192 : 0 : of->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE;
4193 : 0 : of->user_data = user_data;
4194 : 0 : of->flags |= MLX5_FLOW_HW_FLOW_FLAG_UPD_FLOW;
4195 : 0 : rule_attr.user_data = of;
4196 : 0 : ret = mlx5dr_rule_action_update((struct mlx5dr_rule *)of->rule,
4197 : : action_template_index, rule_acts, &rule_attr);
4198 [ # # ]: 0 : if (likely(!ret)) {
4199 : 0 : flow_hw_q_inc_flow_ops(priv, queue);
4200 : 0 : return 0;
4201 : : }
4202 : 0 : error:
4203 [ # # # # ]: 0 : if (table->resource && res_idx)
4204 : 0 : mlx5_ipool_free(table->resource, res_idx);
4205 : 0 : return rte_flow_error_set(error, rte_errno,
4206 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4207 : : "fail to update rte flow");
4208 : : }
4209 : :
4210 : : /**
4211 : : * Enqueue HW steering flow destruction.
4212 : : *
4213 : : * The flow will be applied to the HW only if the postpone bit is not set or
4214 : : * the extra push function is called.
4215 : : * The flow destruction status should be checked from dequeue result.
4216 : : *
4217 : : * @param[in] dev
4218 : : * Pointer to the rte_eth_dev structure.
4219 : : * @param[in] queue
4220 : : * The queue to destroy the flow.
4221 : : * @param[in] attr
4222 : : * Pointer to the flow operation attributes.
4223 : : * @param[in] flow
4224 : : * Pointer to the flow to be destroyed.
4225 : : * @param[in] user_data
4226 : : * Pointer to the user_data.
4227 : : * @param[out] error
4228 : : * Pointer to error structure.
4229 : : *
4230 : : * @return
4231 : : * 0 on success, negative value otherwise and rte_errno is set.
4232 : : */
4233 : : static int
4234 : 0 : flow_hw_async_flow_destroy(struct rte_eth_dev *dev,
4235 : : uint32_t queue,
4236 : : const struct rte_flow_op_attr *attr,
4237 : : struct rte_flow *flow,
4238 : : void *user_data,
4239 : : struct rte_flow_error *error)
4240 : : {
4241 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4242 : 0 : struct mlx5dr_rule_attr rule_attr = {
4243 : : .queue_id = queue,
4244 : : .user_data = user_data,
4245 : 0 : .burst = attr->postpone,
4246 : : };
4247 : : struct rte_flow_hw *fh = (struct rte_flow_hw *)flow;
4248 : 0 : bool resizable = rte_flow_template_table_resizable(dev->data->port_id,
4249 : 0 : &fh->table->cfg.attr);
4250 : : int ret;
4251 : :
4252 : : if (mlx5_fp_debug_enabled()) {
4253 : : if (flow_hw_async_destroy_validate(dev, queue, fh, error))
4254 : : return -rte_errno;
4255 : : }
4256 [ # # ]: 0 : fh->operation_type = !resizable ?
4257 : : MLX5_FLOW_HW_FLOW_OP_TYPE_DESTROY :
4258 : : MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_DESTROY;
4259 : 0 : fh->user_data = user_data;
4260 : 0 : rule_attr.user_data = fh;
4261 : 0 : rule_attr.rule_idx = fh->rule_idx;
4262 : 0 : ret = mlx5dr_rule_destroy((struct mlx5dr_rule *)fh->rule, &rule_attr);
4263 [ # # ]: 0 : if (ret) {
4264 : 0 : return rte_flow_error_set(error, rte_errno,
4265 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4266 : : "fail to destroy rte flow");
4267 : : }
4268 : : flow_hw_q_inc_flow_ops(priv, queue);
4269 : 0 : return 0;
4270 : : }
4271 : :
4272 : : /**
4273 : : * Release the AGE and counter for given flow.
4274 : : *
4275 : : * @param[in] priv
4276 : : * Pointer to the port private data structure.
4277 : : * @param[in] queue
4278 : : * The queue to release the counter.
4279 : : * @param[in, out] flow
4280 : : * Pointer to the flow containing the counter.
4281 : : * @param[out] error
4282 : : * Pointer to error structure.
4283 : : */
4284 : : static void
4285 : 0 : flow_hw_age_count_release(struct mlx5_priv *priv, uint32_t queue,
4286 : : struct rte_flow_hw *flow,
4287 : : struct rte_flow_error *error)
4288 : : {
4289 : 0 : struct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(priv->dev_data->port_id, flow);
4290 : : uint32_t *cnt_queue;
4291 : 0 : uint32_t age_idx = aux->orig.age_idx;
4292 : :
4293 : : MLX5_ASSERT(flow->flags & MLX5_FLOW_HW_FLOW_FLAG_CNT_ID);
4294 [ # # # # ]: 0 : if (mlx5_hws_cnt_is_shared(priv->hws_cpool, flow->cnt_id)) {
4295 [ # # # # ]: 0 : if ((flow->flags & MLX5_FLOW_HW_FLOW_FLAG_AGE_IDX) &&
4296 : : !mlx5_hws_age_is_indirect(age_idx)) {
4297 : : /* Remove this AGE parameter from indirect counter. */
4298 : : mlx5_hws_cnt_age_set(priv->hws_cpool, flow->cnt_id, 0);
4299 : : /* Release the AGE parameter. */
4300 : 0 : mlx5_hws_age_action_destroy(priv, age_idx, error);
4301 : : }
4302 : 0 : return;
4303 : : }
4304 : : cnt_queue = mlx5_hws_cnt_get_queue(priv, &queue);
4305 : : /* Put the counter first to reduce the race risk in BG thread. */
4306 [ # # ]: 0 : mlx5_hws_cnt_pool_put(priv->hws_cpool, cnt_queue, &flow->cnt_id);
4307 [ # # ]: 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_AGE_IDX) {
4308 [ # # ]: 0 : if (mlx5_hws_age_is_indirect(age_idx)) {
4309 : 0 : uint32_t idx = age_idx & MLX5_HWS_AGE_IDX_MASK;
4310 : :
4311 : : mlx5_hws_age_nb_cnt_decrease(priv, idx);
4312 : : } else {
4313 : : /* Release the AGE parameter. */
4314 : 0 : mlx5_hws_age_action_destroy(priv, age_idx, error);
4315 : : }
4316 : : }
4317 : : }
4318 : :
4319 : : static __rte_always_inline void
4320 : : flow_hw_pull_legacy_indirect_comp(struct rte_eth_dev *dev, struct mlx5_hw_q_job *job,
4321 : : uint32_t queue)
4322 : : {
4323 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4324 : : struct mlx5_aso_ct_action *aso_ct;
4325 : : struct mlx5_aso_mtr *aso_mtr;
4326 : : uint32_t type, idx;
4327 : :
4328 [ # # ]: 0 : if (MLX5_INDIRECT_ACTION_TYPE_GET(job->action) ==
4329 : : MLX5_INDIRECT_ACTION_TYPE_QUOTA) {
4330 : 0 : mlx5_quota_async_completion(dev, queue, job);
4331 [ # # ]: 0 : } else if (job->type == MLX5_HW_Q_JOB_TYPE_DESTROY) {
4332 : : type = MLX5_INDIRECT_ACTION_TYPE_GET(job->action);
4333 [ # # ]: 0 : if (type == MLX5_INDIRECT_ACTION_TYPE_METER_MARK) {
4334 : 0 : idx = MLX5_INDIRECT_ACTION_IDX_GET(job->action);
4335 : 0 : mlx5_ipool_free(priv->hws_mpool->idx_pool, idx);
4336 : : }
4337 [ # # ]: 0 : } else if (job->type == MLX5_HW_Q_JOB_TYPE_CREATE) {
4338 : : type = MLX5_INDIRECT_ACTION_TYPE_GET(job->action);
4339 [ # # ]: 0 : if (type == MLX5_INDIRECT_ACTION_TYPE_METER_MARK) {
4340 : 0 : idx = MLX5_INDIRECT_ACTION_IDX_GET(job->action);
4341 : 0 : aso_mtr = mlx5_ipool_get(priv->hws_mpool->idx_pool, idx);
4342 : 0 : aso_mtr->state = ASO_METER_READY;
4343 [ # # ]: 0 : } else if (type == MLX5_INDIRECT_ACTION_TYPE_CT) {
4344 : 0 : idx = MLX5_INDIRECT_ACTION_IDX_GET(job->action);
4345 : 0 : aso_ct = mlx5_ipool_get(priv->hws_ctpool->cts, idx);
4346 : 0 : aso_ct->state = ASO_CONNTRACK_READY;
4347 : : }
4348 [ # # ]: 0 : } else if (job->type == MLX5_HW_Q_JOB_TYPE_QUERY) {
4349 : : type = MLX5_INDIRECT_ACTION_TYPE_GET(job->action);
4350 [ # # ]: 0 : if (type == MLX5_INDIRECT_ACTION_TYPE_CT) {
4351 : 0 : idx = MLX5_INDIRECT_ACTION_IDX_GET(job->action);
4352 : 0 : aso_ct = mlx5_ipool_get(priv->hws_ctpool->cts, idx);
4353 : 0 : mlx5_aso_ct_obj_analyze(job->query.user,
4354 : 0 : job->query.hw);
4355 : 0 : aso_ct->state = ASO_CONNTRACK_READY;
4356 : : }
4357 : : }
4358 : : }
4359 : :
4360 : : static __rte_always_inline int
4361 : : mlx5_hw_pull_flow_transfer_comp(struct rte_eth_dev *dev,
4362 : : uint32_t queue, struct rte_flow_op_result res[],
4363 : : uint16_t n_res)
4364 : : {
4365 : : uint32_t size, i;
4366 : 0 : struct rte_flow_hw *flow = NULL;
4367 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4368 : 0 : struct rte_ring *ring = priv->hw_q[queue].flow_transfer_completed;
4369 : :
4370 : 0 : size = RTE_MIN(rte_ring_count(ring), n_res);
4371 [ # # ]: 0 : for (i = 0; i < size; i++) {
4372 [ # # # # : 0 : res[i].status = RTE_FLOW_OP_SUCCESS;
# ]
4373 : : rte_ring_dequeue(ring, (void **)&flow);
4374 : 0 : res[i].user_data = flow->user_data;
4375 : : flow_hw_q_dec_flow_ops(priv, queue);
4376 : : }
4377 : 0 : return (int)size;
4378 : : }
4379 : :
4380 : : static inline int
4381 : 0 : __flow_hw_pull_indir_action_comp(struct rte_eth_dev *dev,
4382 : : uint32_t queue,
4383 : : struct rte_flow_op_result res[],
4384 : : uint16_t n_res)
4385 : :
4386 : : {
4387 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4388 : 0 : struct rte_ring *r = priv->hw_q[queue].indir_cq;
4389 : 0 : void *user_data = NULL;
4390 : : int ret_comp, i;
4391 : :
4392 : 0 : ret_comp = (int)rte_ring_count(r);
4393 : 0 : if (ret_comp > n_res)
4394 : : ret_comp = n_res;
4395 [ # # ]: 0 : for (i = 0; i < ret_comp; i++) {
4396 : : rte_ring_dequeue(r, &user_data);
4397 : 0 : res[i].user_data = user_data;
4398 : 0 : res[i].status = RTE_FLOW_OP_SUCCESS;
4399 : : }
4400 [ # # ]: 0 : if (!priv->shared_host) {
4401 [ # # # # ]: 0 : if (ret_comp < n_res && priv->hws_mpool)
4402 : 0 : ret_comp += mlx5_aso_pull_completion(&priv->hws_mpool->sq[queue],
4403 : 0 : &res[ret_comp], n_res - ret_comp);
4404 [ # # # # ]: 0 : if (ret_comp < n_res && priv->hws_ctpool)
4405 : 0 : ret_comp += mlx5_aso_pull_completion(&priv->ct_mng->aso_sqs[queue],
4406 : 0 : &res[ret_comp], n_res - ret_comp);
4407 : : }
4408 [ # # # # ]: 0 : if (ret_comp < n_res && priv->quota_ctx.sq)
4409 : 0 : ret_comp += mlx5_aso_pull_completion(&priv->quota_ctx.sq[queue],
4410 : 0 : &res[ret_comp],
4411 : 0 : n_res - ret_comp);
4412 [ # # ]: 0 : for (i = 0; i < ret_comp; i++) {
4413 : 0 : struct mlx5_hw_q_job *job = (struct mlx5_hw_q_job *)res[i].user_data;
4414 : :
4415 : : /* Restore user data. */
4416 : 0 : res[i].user_data = job->user_data;
4417 [ # # ]: 0 : if (job->indirect_type == MLX5_HW_INDIRECT_TYPE_LEGACY)
4418 : : flow_hw_pull_legacy_indirect_comp(dev, job, queue);
4419 : : /*
4420 : : * Current PMD supports 2 indirect action list types - MIRROR and REFORMAT.
4421 : : * These indirect list types do not post WQE to create action.
4422 : : * Future indirect list types that do post WQE will add
4423 : : * completion handlers here.
4424 : : */
4425 : : flow_hw_job_put(priv, job, queue);
4426 : : }
4427 : 0 : return ret_comp;
4428 : : }
4429 : :
4430 : : static __rte_always_inline void
4431 : : hw_cmpl_flow_update_or_destroy(struct rte_eth_dev *dev,
4432 : : struct rte_flow_hw *flow,
4433 : : uint32_t queue, struct rte_flow_error *error)
4434 : : {
4435 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4436 : 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
4437 : 0 : struct rte_flow_template_table *table = flow->table;
4438 : : /* Release the original resource index in case of update. */
4439 : 0 : uint32_t res_idx = flow->res_idx;
4440 : :
4441 [ # # ]: 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAGS_ALL) {
4442 : 0 : struct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
4443 : :
4444 [ # # # # : 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_FATE_JUMP)
# # ]
4445 : 0 : flow_hw_jump_release(dev, flow->jump);
4446 [ # # # # : 0 : else if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_FATE_HRXQ)
# # ]
4447 : 0 : mlx5_hrxq_obj_release(dev, flow->hrxq);
4448 [ # # # # : 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_CNT_ID)
# # ]
4449 : 0 : flow_hw_age_count_release(priv, queue, flow, error);
4450 [ # # # # : 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_MTR_ID)
# # ]
4451 : 0 : mlx5_ipool_free(pool->idx_pool, aux->orig.mtr_id);
4452 [ # # # # : 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_UPD_FLOW) {
# # ]
4453 [ # # # # : 0 : struct rte_flow_hw *upd_flow = &aux->upd_flow;
# # ]
4454 : :
4455 : : rte_memcpy(flow, upd_flow, offsetof(struct rte_flow_hw, rule));
4456 : 0 : aux->orig = aux->upd;
4457 : 0 : flow->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_CREATE;
4458 [ # # # # : 0 : if (!flow->nt_rule && table->resource)
# # # # #
# # # ]
4459 : 0 : mlx5_ipool_free(table->resource, res_idx);
4460 : : }
4461 : : }
4462 [ # # # # : 0 : if (flow->operation_type == MLX5_FLOW_HW_FLOW_OP_TYPE_DESTROY ||
# # ]
4463 : : flow->operation_type == MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_DESTROY) {
4464 [ # # # # : 0 : if (!flow->nt_rule) {
# # ]
4465 [ # # # # : 0 : if (table->resource)
# # ]
4466 : 0 : mlx5_ipool_free(table->resource, res_idx);
4467 : 0 : mlx5_ipool_free(table->flow, flow->idx);
4468 : : }
4469 : : }
4470 : : }
4471 : :
4472 : : static __rte_always_inline void
4473 : : hw_cmpl_resizable_tbl(struct rte_eth_dev *dev,
4474 : : struct rte_flow_hw *flow,
4475 : : uint32_t queue, enum rte_flow_op_status status,
4476 : : struct rte_flow_error *error)
4477 : : {
4478 : 0 : struct rte_flow_template_table *table = flow->table;
4479 : 0 : struct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
4480 : 0 : uint32_t selector = aux->matcher_selector;
4481 : 0 : uint32_t other_selector = (selector + 1) & 1;
4482 : :
4483 : : MLX5_ASSERT(flow->flags & MLX5_FLOW_HW_FLOW_FLAG_MATCHER_SELECTOR);
4484 [ # # # # ]: 0 : switch (flow->operation_type) {
4485 : 0 : case MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_CREATE:
4486 : 0 : rte_atomic_fetch_add_explicit
4487 : : (&table->matcher_info[selector].refcnt, 1,
4488 : : rte_memory_order_relaxed);
4489 : 0 : break;
4490 : 0 : case MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_DESTROY:
4491 [ # # ]: 0 : rte_atomic_fetch_sub_explicit
4492 : : (&table->matcher_info[selector].refcnt, 1,
4493 : : rte_memory_order_relaxed);
4494 : : hw_cmpl_flow_update_or_destroy(dev, flow, queue, error);
4495 : : break;
4496 : 0 : case MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_MOVE:
4497 [ # # ]: 0 : if (status == RTE_FLOW_OP_SUCCESS) {
4498 : 0 : rte_atomic_fetch_sub_explicit
4499 : : (&table->matcher_info[selector].refcnt, 1,
4500 : : rte_memory_order_relaxed);
4501 : 0 : rte_atomic_fetch_add_explicit
4502 : : (&table->matcher_info[other_selector].refcnt, 1,
4503 : : rte_memory_order_relaxed);
4504 : 0 : aux->matcher_selector = other_selector;
4505 : : }
4506 : : break;
4507 : : default:
4508 : : break;
4509 : : }
4510 : : }
4511 : :
4512 : : /**
4513 : : * Pull the enqueued flows.
4514 : : *
4515 : : * For flows enqueued from creation/destruction, the status should be
4516 : : * checked from the dequeue result.
4517 : : *
4518 : : * @param[in] dev
4519 : : * Pointer to the rte_eth_dev structure.
4520 : : * @param[in] queue
4521 : : * The queue to pull the result.
4522 : : * @param[in/out] res
4523 : : * Array to save the results.
4524 : : * @param[in] n_res
4525 : : * Available result with the array.
4526 : : * @param[out] error
4527 : : * Pointer to error structure.
4528 : : *
4529 : : * @return
4530 : : * Result number on success, negative value otherwise and rte_errno is set.
4531 : : */
4532 : : static int
4533 : 0 : flow_hw_pull(struct rte_eth_dev *dev,
4534 : : uint32_t queue,
4535 : : struct rte_flow_op_result res[],
4536 : : uint16_t n_res,
4537 : : struct rte_flow_error *error)
4538 : : {
4539 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4540 : : int ret, i;
4541 : :
4542 : : /* 1. Pull the flow completion. */
4543 : 0 : ret = mlx5dr_send_queue_poll(priv->dr_ctx, queue, res, n_res);
4544 [ # # ]: 0 : if (ret < 0)
4545 : 0 : return rte_flow_error_set(error, rte_errno,
4546 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4547 : : "fail to query flow queue");
4548 [ # # ]: 0 : for (i = 0; i < ret; i++) {
4549 : 0 : struct rte_flow_hw *flow = res[i].user_data;
4550 : :
4551 : : /* Restore user data. */
4552 : 0 : res[i].user_data = flow->user_data;
4553 [ # # # ]: 0 : switch (flow->operation_type) {
4554 : : case MLX5_FLOW_HW_FLOW_OP_TYPE_DESTROY:
4555 : : case MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE:
4556 : : hw_cmpl_flow_update_or_destroy(dev, flow, queue, error);
4557 : : break;
4558 : 0 : case MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_CREATE:
4559 : : case MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_DESTROY:
4560 : : case MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_MOVE:
4561 : 0 : hw_cmpl_resizable_tbl(dev, flow, queue, res[i].status, error);
4562 : : break;
4563 : : default:
4564 : : break;
4565 : : }
4566 : : flow_hw_q_dec_flow_ops(priv, queue);
4567 : : }
4568 : : /* 2. Pull indirect action comp. */
4569 [ # # ]: 0 : if (ret < n_res)
4570 : 0 : ret += __flow_hw_pull_indir_action_comp(dev, queue, &res[ret],
4571 : 0 : n_res - ret);
4572 [ # # ]: 0 : if (ret < n_res)
4573 : 0 : ret += mlx5_hw_pull_flow_transfer_comp(dev, queue, &res[ret],
4574 : 0 : n_res - ret);
4575 : :
4576 : : return ret;
4577 : : }
4578 : :
4579 : : static uint32_t
4580 : 0 : mlx5_hw_push_queue(struct rte_ring *pending_q, struct rte_ring *cmpl_q)
4581 : : {
4582 : 0 : void *job = NULL;
4583 : : uint32_t i, size = rte_ring_count(pending_q);
4584 : :
4585 [ # # ]: 0 : for (i = 0; i < size; i++) {
4586 : : rte_ring_dequeue(pending_q, &job);
4587 [ # # # # : 0 : rte_ring_enqueue(cmpl_q, job);
# ]
4588 : : }
4589 : 0 : return size;
4590 : : }
4591 : :
4592 : : static inline uint32_t
4593 : 0 : __flow_hw_push_action(struct rte_eth_dev *dev,
4594 : : uint32_t queue)
4595 : : {
4596 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4597 : 0 : struct mlx5_hw_q *hw_q = &priv->hw_q[queue];
4598 : :
4599 : 0 : mlx5_hw_push_queue(hw_q->indir_iq, hw_q->indir_cq);
4600 : 0 : mlx5_hw_push_queue(hw_q->flow_transfer_pending,
4601 : : hw_q->flow_transfer_completed);
4602 [ # # ]: 0 : if (!priv->shared_host) {
4603 [ # # ]: 0 : if (priv->hws_ctpool)
4604 : 0 : mlx5_aso_push_wqe(priv->sh,
4605 : 0 : &priv->ct_mng->aso_sqs[queue]);
4606 [ # # ]: 0 : if (priv->hws_mpool)
4607 : 0 : mlx5_aso_push_wqe(priv->sh,
4608 : 0 : &priv->hws_mpool->sq[queue]);
4609 : : }
4610 : 0 : return flow_hw_q_pending(priv, queue);
4611 : : }
4612 : :
4613 : : static int
4614 : 0 : __flow_hw_push(struct rte_eth_dev *dev,
4615 : : uint32_t queue,
4616 : : struct rte_flow_error *error)
4617 : : {
4618 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4619 : : int ret, num;
4620 : :
4621 : 0 : num = __flow_hw_push_action(dev, queue);
4622 : 0 : ret = mlx5dr_send_queue_action(priv->dr_ctx, queue,
4623 : : MLX5DR_SEND_QUEUE_ACTION_DRAIN_ASYNC);
4624 [ # # ]: 0 : if (ret) {
4625 : 0 : rte_flow_error_set(error, rte_errno,
4626 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4627 : : "fail to push flows");
4628 : 0 : return ret;
4629 : : }
4630 : : return num;
4631 : : }
4632 : :
4633 : : /**
4634 : : * Push the enqueued flows to HW.
4635 : : *
4636 : : * Force apply all the enqueued flows to the HW.
4637 : : *
4638 : : * @param[in] dev
4639 : : * Pointer to the rte_eth_dev structure.
4640 : : * @param[in] queue
4641 : : * The queue to push the flow.
4642 : : * @param[out] error
4643 : : * Pointer to error structure.
4644 : : *
4645 : : * @return
4646 : : * 0 on success, negative value otherwise and rte_errno is set.
4647 : : */
4648 : : static int
4649 : 0 : flow_hw_push(struct rte_eth_dev *dev,
4650 : : uint32_t queue, struct rte_flow_error *error)
4651 : : {
4652 : 0 : int ret = __flow_hw_push(dev, queue, error);
4653 : :
4654 : 0 : return ret >= 0 ? 0 : ret;
4655 : : }
4656 : :
4657 : : /**
4658 : : * Drain the enqueued flows' completion.
4659 : : *
4660 : : * @param[in] dev
4661 : : * Pointer to the rte_eth_dev structure.
4662 : : * @param[in] queue
4663 : : * The queue to pull the flow.
4664 : : * @param[out] error
4665 : : * Pointer to error structure.
4666 : : *
4667 : : * @return
4668 : : * 0 on success, negative value otherwise and rte_errno is set.
4669 : : */
4670 : : static int
4671 : 0 : __flow_hw_pull_comp(struct rte_eth_dev *dev,
4672 : : uint32_t queue, struct rte_flow_error *error)
4673 : : {
4674 : : struct rte_flow_op_result comp[BURST_THR];
4675 : : int ret, i, empty_loop = 0;
4676 : : uint32_t pending_rules;
4677 : :
4678 : 0 : ret = __flow_hw_push(dev, queue, error);
4679 [ # # ]: 0 : if (ret < 0)
4680 : : return ret;
4681 : 0 : pending_rules = ret;
4682 [ # # ]: 0 : while (pending_rules) {
4683 : 0 : ret = flow_hw_pull(dev, queue, comp, BURST_THR, error);
4684 [ # # ]: 0 : if (ret < 0)
4685 : : return -1;
4686 [ # # ]: 0 : if (!ret) {
4687 : 0 : rte_delay_us_sleep(MLX5_ASO_WQE_CQE_RESPONSE_DELAY);
4688 [ # # ]: 0 : if (++empty_loop > 5) {
4689 : 0 : DRV_LOG(WARNING, "No available dequeue %u, quit.", pending_rules);
4690 : 0 : break;
4691 : : }
4692 : 0 : continue;
4693 : : }
4694 [ # # ]: 0 : for (i = 0; i < ret; i++) {
4695 [ # # ]: 0 : if (comp[i].status == RTE_FLOW_OP_ERROR)
4696 : 0 : DRV_LOG(WARNING, "Flow flush get error CQE.");
4697 : : }
4698 : : /*
4699 : : * Indirect **SYNC** METER_MARK and CT actions do not
4700 : : * remove completion after WQE post.
4701 : : * That implementation avoids HW timeout.
4702 : : * The completion is removed before the following WQE post.
4703 : : * However, HWS queue updates do not reflect that behaviour.
4704 : : * Therefore, during port destruction sync queue may have
4705 : : * pending completions.
4706 : : */
4707 : 0 : pending_rules -= RTE_MIN(pending_rules, (uint32_t)ret);
4708 : : empty_loop = 0;
4709 : : }
4710 : : return 0;
4711 : : }
4712 : :
4713 : : /**
4714 : : * Flush created flows.
4715 : : *
4716 : : * @param[in] dev
4717 : : * Pointer to the rte_eth_dev structure.
4718 : : * @param[out] error
4719 : : * Pointer to error structure.
4720 : : *
4721 : : * @return
4722 : : * 0 on success, negative value otherwise and rte_errno is set.
4723 : : */
4724 : : int
4725 : 0 : flow_hw_q_flow_flush(struct rte_eth_dev *dev,
4726 : : struct rte_flow_error *error)
4727 : : {
4728 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4729 : 0 : struct mlx5_hw_q *hw_q = &priv->hw_q[MLX5_DEFAULT_FLUSH_QUEUE];
4730 : : struct rte_flow_template_table *tbl;
4731 : : struct rte_flow_hw *flow;
4732 : 0 : struct rte_flow_op_attr attr = {
4733 : : .postpone = 0,
4734 : : };
4735 : : uint32_t pending_rules = 0;
4736 : : uint32_t queue;
4737 : : uint32_t fidx;
4738 : :
4739 : : /*
4740 : : * Ensure to push and dequeue all the enqueued flow
4741 : : * creation/destruction jobs in case user forgot to
4742 : : * dequeue. Or the enqueued created flows will be
4743 : : * leaked. The forgotten dequeues would also cause
4744 : : * flow flush get extra CQEs as expected and pending_rules
4745 : : * be minus value.
4746 : : */
4747 [ # # ]: 0 : for (queue = 0; queue < priv->nb_queue; queue++) {
4748 [ # # ]: 0 : if (__flow_hw_pull_comp(dev, queue, error))
4749 : : return -1;
4750 : : }
4751 : : /* Flush flow per-table from MLX5_DEFAULT_FLUSH_QUEUE. */
4752 [ # # ]: 0 : LIST_FOREACH(tbl, &priv->flow_hw_tbl, next) {
4753 [ # # ]: 0 : if (!tbl->cfg.external)
4754 : 0 : continue;
4755 [ # # ]: 0 : MLX5_IPOOL_FOREACH(tbl->flow, fidx, flow) {
4756 [ # # ]: 0 : if (flow_hw_async_flow_destroy(dev,
4757 : : MLX5_DEFAULT_FLUSH_QUEUE,
4758 : : &attr,
4759 : : (struct rte_flow *)flow,
4760 : : NULL,
4761 : : error))
4762 : : return -1;
4763 : 0 : pending_rules++;
4764 : : /* Drain completion with queue size. */
4765 [ # # ]: 0 : if (pending_rules >= hw_q->size) {
4766 [ # # ]: 0 : if (__flow_hw_pull_comp(dev,
4767 : : MLX5_DEFAULT_FLUSH_QUEUE,
4768 : : error))
4769 : : return -1;
4770 : : pending_rules = 0;
4771 : : }
4772 : : }
4773 : : }
4774 : : /* Drain left completion. */
4775 [ # # # # ]: 0 : if (pending_rules &&
4776 : 0 : __flow_hw_pull_comp(dev, MLX5_DEFAULT_FLUSH_QUEUE, error))
4777 : 0 : return -1;
4778 : : return 0;
4779 : : }
4780 : :
4781 : : static int
4782 : 0 : mlx5_tbl_multi_pattern_process(struct rte_eth_dev *dev,
4783 : : struct rte_flow_template_table *tbl,
4784 : : struct mlx5_multi_pattern_segment *segment,
4785 : : uint32_t bulk_size,
4786 : : struct rte_flow_error *error)
4787 : : {
4788 : : int ret = 0;
4789 : : uint32_t i;
4790 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4791 : : bool unified_fdb = is_unified_fdb(priv);
4792 : : struct mlx5_tbl_multi_pattern_ctx *mpctx = &tbl->mpctx;
4793 : : const struct rte_flow_template_table_attr *table_attr = &tbl->cfg.attr;
4794 : 0 : const struct rte_flow_attr *attr = &table_attr->flow_attr;
4795 : : enum mlx5dr_table_type type =
4796 : 0 : get_mlx5dr_table_type(attr, table_attr->specialize, unified_fdb);
4797 : 0 : uint32_t flags = mlx5_hw_act_flag[!!attr->group][type];
4798 : : struct mlx5dr_action *dr_action = NULL;
4799 : :
4800 [ # # ]: 0 : for (i = 0; i < MLX5_MULTIPATTERN_ENCAP_NUM; i++) {
4801 [ # # ]: 0 : typeof(mpctx->reformat[0]) *reformat = mpctx->reformat + i;
4802 : : enum mlx5dr_action_type reformat_type =
4803 : : mlx5_multi_pattern_reformat_index_to_type(i);
4804 : :
4805 [ # # ]: 0 : if (!reformat->elements_num)
4806 : 0 : continue;
4807 : : dr_action = reformat_type == MLX5DR_ACTION_TYP_INSERT_HEADER ?
4808 : : mlx5dr_action_create_insert_header
4809 : : (priv->dr_ctx, reformat->elements_num,
4810 : : reformat->insert_hdr, bulk_size, flags) :
4811 : 0 : mlx5dr_action_create_reformat
4812 : : (priv->dr_ctx, reformat_type, reformat->elements_num,
4813 : 0 : reformat->reformat_hdr, bulk_size, flags);
4814 [ # # ]: 0 : if (!dr_action) {
4815 : 0 : ret = rte_flow_error_set(error, rte_errno,
4816 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4817 : : NULL,
4818 : : "failed to create multi-pattern encap action");
4819 : 0 : goto error;
4820 : : }
4821 : 0 : segment->reformat_action[i] = dr_action;
4822 : : }
4823 [ # # ]: 0 : if (mpctx->mh.elements_num) {
4824 : : typeof(mpctx->mh) *mh = &mpctx->mh;
4825 : 0 : dr_action = mlx5dr_action_create_modify_header
4826 : 0 : (priv->dr_ctx, mpctx->mh.elements_num, mh->pattern,
4827 : : bulk_size, flags);
4828 [ # # ]: 0 : if (!dr_action) {
4829 : 0 : ret = rte_flow_error_set(error, rte_errno,
4830 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4831 : : NULL, "failed to create multi-pattern header modify action");
4832 : 0 : goto error;
4833 : : }
4834 : 0 : segment->mhdr_action = dr_action;
4835 : : }
4836 [ # # ]: 0 : if (dr_action) {
4837 : 0 : segment->capacity = RTE_BIT32(bulk_size);
4838 [ # # ]: 0 : if (segment != &mpctx->segments[MLX5_MAX_TABLE_RESIZE_NUM - 1])
4839 : 0 : segment[1].head_index = segment->head_index + segment->capacity;
4840 : : }
4841 : : return 0;
4842 : 0 : error:
4843 : 0 : mlx5_destroy_multi_pattern_segment(segment);
4844 : 0 : return ret;
4845 : : }
4846 : :
4847 : : static int
4848 : 0 : mlx5_hw_build_template_table(struct rte_eth_dev *dev,
4849 : : uint8_t nb_action_templates,
4850 : : struct rte_flow_actions_template *action_templates[],
4851 : : struct mlx5dr_action_template *at[],
4852 : : struct rte_flow_template_table *tbl,
4853 : : struct rte_flow_error *error)
4854 : : {
4855 : : int ret;
4856 : : uint8_t i;
4857 : :
4858 [ # # ]: 0 : for (i = 0; i < nb_action_templates; i++) {
4859 : 0 : uint32_t refcnt = rte_atomic_fetch_add_explicit(&action_templates[i]->refcnt, 1,
4860 : : rte_memory_order_relaxed) + 1;
4861 : :
4862 [ # # ]: 0 : if (refcnt <= 1) {
4863 : 0 : rte_flow_error_set(error, EINVAL,
4864 : : RTE_FLOW_ERROR_TYPE_ACTION,
4865 : : &action_templates[i], "invalid AT refcount");
4866 : 0 : goto at_error;
4867 : : }
4868 : 0 : at[i] = action_templates[i]->tmpl;
4869 : 0 : tbl->ats[i].action_template = action_templates[i];
4870 : 0 : LIST_INIT(&tbl->ats[i].acts.act_list);
4871 : : /* do NOT translate table action if `dev` was not started */
4872 [ # # ]: 0 : if (!dev->data->dev_started)
4873 : 0 : continue;
4874 : 0 : ret = flow_hw_translate_actions_template(dev, &tbl->cfg,
4875 : : &tbl->ats[i].acts,
4876 : : action_templates[i],
4877 : : &tbl->mpctx, error);
4878 [ # # ]: 0 : if (ret) {
4879 : 0 : i++;
4880 : 0 : goto at_error;
4881 : : }
4882 : 0 : flow_hw_populate_rule_acts_caches(dev, tbl, i);
4883 : : }
4884 [ # # ]: 0 : tbl->nb_action_templates = nb_action_templates;
4885 [ # # ]: 0 : if (mlx5_is_multi_pattern_active(&tbl->mpctx)) {
4886 [ # # ]: 0 : ret = mlx5_tbl_multi_pattern_process(dev, tbl,
4887 : : &tbl->mpctx.segments[0],
4888 : : rte_log2_u32(tbl->cfg.attr.nb_flows),
4889 : : error);
4890 [ # # ]: 0 : if (ret)
4891 : 0 : goto at_error;
4892 : : }
4893 : : return 0;
4894 : :
4895 : : at_error:
4896 [ # # ]: 0 : while (i--) {
4897 : 0 : __flow_hw_action_template_destroy(dev, &tbl->ats[i].acts);
4898 : 0 : rte_atomic_fetch_sub_explicit(&action_templates[i]->refcnt,
4899 : : 1, rte_memory_order_relaxed);
4900 : : }
4901 : 0 : return rte_errno;
4902 : : }
4903 : :
4904 : : static bool
4905 : : flow_hw_validate_template_domain(const struct rte_flow_attr *table_attr,
4906 : : uint32_t ingress, uint32_t egress, uint32_t transfer)
4907 : : {
4908 : 0 : if (table_attr->ingress)
4909 : : return ingress != 0;
4910 [ # # # # ]: 0 : else if (table_attr->egress)
4911 : : return egress != 0;
4912 : : else
4913 : 0 : return transfer;
4914 : : }
4915 : :
4916 : : static bool
4917 : : flow_hw_validate_table_domain(const struct rte_flow_attr *table_attr)
4918 : : {
4919 : 0 : return table_attr->ingress + table_attr->egress + table_attr->transfer
4920 : : == 1;
4921 : : }
4922 : :
4923 : : /**
4924 : : * Create flow table.
4925 : : *
4926 : : * The input item and action templates will be binded to the table.
4927 : : * Flow memory will also be allocated. Matcher will be created based
4928 : : * on the item template. Action will be translated to the dedicated
4929 : : * DR action if possible.
4930 : : *
4931 : : * @param[in] dev
4932 : : * Pointer to the rte_eth_dev structure.
4933 : : * @param[in] table_cfg
4934 : : * Pointer to the table configuration.
4935 : : * @param[in] item_templates
4936 : : * Item template array to be binded to the table.
4937 : : * @param[in] nb_item_templates
4938 : : * Number of item template.
4939 : : * @param[in] action_templates
4940 : : * Action template array to be binded to the table.
4941 : : * @param[in] nb_action_templates
4942 : : * Number of action template.
4943 : : * @param[out] error
4944 : : * Pointer to error structure.
4945 : : *
4946 : : * @return
4947 : : * Table on success, NULL otherwise and rte_errno is set.
4948 : : */
4949 : : static struct rte_flow_template_table *
4950 : 0 : flow_hw_table_create(struct rte_eth_dev *dev,
4951 : : const struct mlx5_flow_template_table_cfg *table_cfg,
4952 : : struct rte_flow_pattern_template *item_templates[],
4953 : : uint8_t nb_item_templates,
4954 : : struct rte_flow_actions_template *action_templates[],
4955 : : uint8_t nb_action_templates,
4956 : : struct rte_flow_error *error)
4957 : : {
4958 : 0 : struct rte_flow_error sub_error = {
4959 : : .type = RTE_FLOW_ERROR_TYPE_NONE,
4960 : : .cause = NULL,
4961 : : .message = NULL,
4962 : : };
4963 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
4964 : : bool unified_fdb = is_unified_fdb(priv);
4965 : 0 : struct mlx5dr_matcher_attr matcher_attr = {0};
4966 : 0 : struct mlx5dr_action_jump_to_matcher_attr jump_attr = {
4967 : : .type = MLX5DR_ACTION_JUMP_TO_MATCHER_BY_INDEX,
4968 : : .matcher = NULL,
4969 : : };
4970 : : struct rte_flow_template_table *tbl = NULL;
4971 : : struct mlx5_flow_group *grp;
4972 : : struct mlx5dr_match_template *mt[MLX5_HW_TBL_MAX_ITEM_TEMPLATE];
4973 : : struct mlx5dr_action_template *at[MLX5_HW_TBL_MAX_ACTION_TEMPLATE];
4974 : 0 : const struct rte_flow_template_table_attr *attr = &table_cfg->attr;
4975 : 0 : struct rte_flow_attr flow_attr = attr->flow_attr;
4976 : 0 : uint32_t specialize = table_cfg->attr.specialize;
4977 : 0 : struct mlx5_flow_cb_ctx ctx = {
4978 : : .dev = dev,
4979 : : .error = &sub_error,
4980 : : .data = &flow_attr,
4981 : : .data2 = &specialize,
4982 : : };
4983 : 0 : struct mlx5_indexed_pool_config cfg = {
4984 : : .trunk_size = 1 << 12,
4985 : : .per_core_cache = 1 << 13,
4986 : : .need_lock = 1,
4987 : 0 : .release_mem_en = !!priv->sh->config.reclaim_mode,
4988 : : .malloc = mlx5_malloc,
4989 : : .free = mlx5_free,
4990 : : .type = "mlx5_hw_table_flow",
4991 : : };
4992 : : struct mlx5_list_entry *ge;
4993 : : uint32_t i = 0, max_tpl = MLX5_HW_TBL_MAX_ITEM_TEMPLATE;
4994 [ # # ]: 0 : uint32_t nb_flows = rte_align32pow2(attr->nb_flows);
4995 : 0 : bool port_started = !!dev->data->dev_started;
4996 : : bool rpool_needed;
4997 : : size_t tbl_mem_size;
4998 : : enum mlx5dr_table_type table_type;
4999 : : int err;
5000 : :
5001 [ # # ]: 0 : if (!flow_hw_validate_table_domain(&attr->flow_attr)) {
5002 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ATTR,
5003 : : NULL, "invalid table domain attributes");
5004 : 0 : return NULL;
5005 : : }
5006 [ # # ]: 0 : for (i = 0; i < nb_item_templates; i++) {
5007 : : const struct rte_flow_pattern_template_attr *pt_attr =
5008 : 0 : &item_templates[i]->attr;
5009 : : bool match = flow_hw_validate_template_domain(&attr->flow_attr,
5010 : 0 : pt_attr->ingress,
5011 : 0 : pt_attr->egress,
5012 [ # # ]: 0 : pt_attr->transfer);
5013 [ # # ]: 0 : if (!match) {
5014 : 0 : rte_flow_error_set(error, EINVAL,
5015 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5016 : : NULL, "pattern template domain does not match table");
5017 : 0 : return NULL;
5018 : : }
5019 [ # # # # ]: 0 : if (item_templates[i]->item_flags & MLX5_FLOW_LAYER_ECPRI &&
5020 : 0 : !mlx5_flex_parser_ecpri_exist(dev))
5021 [ # # ]: 0 : if (mlx5_flex_parser_ecpri_alloc(dev)) {
5022 : 0 : rte_flow_error_set(error, EIO,
5023 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5024 : : NULL,
5025 : : "failed to create Flex parser "
5026 : : "profile for ECPRI");
5027 : 0 : goto error;
5028 : : }
5029 : : }
5030 [ # # ]: 0 : for (i = 0; i < nb_action_templates; i++) {
5031 : 0 : const struct rte_flow_actions_template *at = action_templates[i];
5032 : : bool match = flow_hw_validate_template_domain(&attr->flow_attr,
5033 : 0 : at->attr.ingress,
5034 : 0 : at->attr.egress,
5035 [ # # ]: 0 : at->attr.transfer);
5036 [ # # ]: 0 : if (!match) {
5037 : 0 : rte_flow_error_set(error, EINVAL,
5038 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5039 : : NULL, "action template domain does not match table");
5040 : 0 : return NULL;
5041 : : }
5042 : : }
5043 : : /* HWS layer accepts only 1 item template with root table. */
5044 [ # # ]: 0 : if (!attr->flow_attr.group)
5045 : : max_tpl = 1;
5046 : 0 : cfg.max_idx = nb_flows;
5047 [ # # ]: 0 : cfg.size = !rte_flow_template_table_resizable(dev->data->port_id, attr) ?
5048 : : mlx5_flow_hw_entry_size() :
5049 : : mlx5_flow_hw_auxed_entry_size();
5050 : : /* For table has very limited flows, disable cache. */
5051 [ # # ]: 0 : if (nb_flows < cfg.trunk_size) {
5052 : 0 : cfg.per_core_cache = 0;
5053 : 0 : cfg.trunk_size = nb_flows;
5054 [ # # ]: 0 : } else if (nb_flows <= MLX5_HW_IPOOL_SIZE_THRESHOLD) {
5055 : 0 : cfg.per_core_cache = MLX5_HW_IPOOL_CACHE_MIN;
5056 : : }
5057 : : /* Check if we requires too many templates. */
5058 [ # # # # ]: 0 : if (nb_item_templates > max_tpl ||
5059 : : nb_action_templates > MLX5_HW_TBL_MAX_ACTION_TEMPLATE) {
5060 : 0 : rte_errno = EINVAL;
5061 : 0 : goto error;
5062 : : }
5063 : : /*
5064 : : * Amount of memory required for rte_flow_template_table struct:
5065 : : * - Size of the struct itself.
5066 : : * - VLA of DR rule action containers at the end =
5067 : : * number of actions templates * number of queues * size of DR rule actions container.
5068 : : */
5069 : : tbl_mem_size = sizeof(*tbl);
5070 : 0 : tbl_mem_size += nb_action_templates * priv->nb_queue * sizeof(tbl->rule_acts[0]);
5071 : : /* Allocate the table memory. */
5072 : 0 : tbl = mlx5_malloc(MLX5_MEM_ZERO, tbl_mem_size, RTE_CACHE_LINE_SIZE, rte_socket_id());
5073 [ # # ]: 0 : if (!tbl)
5074 : 0 : goto error;
5075 : 0 : tbl->cfg = *table_cfg;
5076 : : /* Allocate flow indexed pool. */
5077 : 0 : tbl->flow = mlx5_ipool_create(&cfg);
5078 [ # # ]: 0 : if (!tbl->flow)
5079 : 0 : goto error;
5080 : : /* Allocate table of auxiliary flow rule structs. */
5081 : 0 : tbl->flow_aux = mlx5_malloc(MLX5_MEM_ZERO, sizeof(struct rte_flow_hw_aux) * nb_flows,
5082 : 0 : RTE_CACHE_LINE_SIZE, rte_dev_numa_node(dev->device));
5083 [ # # ]: 0 : if (!tbl->flow_aux)
5084 : 0 : goto error;
5085 : : /* Register the flow group. */
5086 : 0 : ge = mlx5_hlist_register(priv->sh->groups, attr->flow_attr.group, &ctx);
5087 [ # # ]: 0 : if (!ge)
5088 : 0 : goto error;
5089 : : grp = container_of(ge, struct mlx5_flow_group, entry);
5090 : : /* Verify unified fdb sub domains consistency */
5091 : 0 : table_type = get_mlx5dr_table_type(&flow_attr, specialize, unified_fdb);
5092 [ # # ]: 0 : if (table_type != grp->type) {
5093 : 0 : DRV_LOG(ERR, "Table type (%u) does not match group id (%u) type (%u)",
5094 : : table_type, grp->group_id, grp->type);
5095 : 0 : rte_errno = EINVAL;
5096 : 0 : goto error;
5097 : : }
5098 : 0 : tbl->grp = grp;
5099 : : /* Prepare matcher information. */
5100 : 0 : matcher_attr.resizable = !!rte_flow_template_table_resizable
5101 : 0 : (dev->data->port_id, &table_cfg->attr);
5102 : 0 : matcher_attr.optimize_flow_src = MLX5DR_MATCHER_FLOW_SRC_ANY;
5103 : 0 : matcher_attr.priority = attr->flow_attr.priority;
5104 : 0 : matcher_attr.optimize_using_rule_idx = true;
5105 : 0 : matcher_attr.mode = MLX5DR_MATCHER_RESOURCE_MODE_RULE;
5106 [ # # ]: 0 : matcher_attr.insert_mode = flow_hw_matcher_insert_mode_get(attr->insertion_type);
5107 [ # # ]: 0 : if (matcher_attr.insert_mode == MLX5DR_MATCHER_INSERT_BY_INDEX) {
5108 [ # # ]: 0 : if (attr->insertion_type == RTE_FLOW_TABLE_INSERTION_TYPE_INDEX_WITH_PATTERN) {
5109 : 0 : matcher_attr.isolated = true;
5110 : 0 : matcher_attr.match_mode = MLX5DR_MATCHER_MATCH_MODE_DEFAULT;
5111 : : } else {
5112 : 0 : matcher_attr.isolated = false;
5113 : 0 : matcher_attr.match_mode = MLX5DR_MATCHER_MATCH_MODE_ALWAYS_HIT;
5114 : : }
5115 : : }
5116 [ # # ]: 0 : if (attr->hash_func == RTE_FLOW_TABLE_HASH_FUNC_CRC16) {
5117 : 0 : DRV_LOG(ERR, "16-bit checksum hash type is not supported");
5118 : 0 : rte_errno = ENOTSUP;
5119 : 0 : goto it_error;
5120 : : }
5121 [ # # ]: 0 : matcher_attr.distribute_mode = flow_hw_matcher_distribute_mode_get(attr->hash_func);
5122 : 0 : matcher_attr.rule.num_log = rte_log2_u32(nb_flows);
5123 : : /* Parse hints information. */
5124 [ # # ]: 0 : if (attr->specialize) {
5125 : : uint32_t val = RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_WIRE_ORIG |
5126 : : RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_VPORT_ORIG;
5127 : :
5128 [ # # ]: 0 : if ((attr->specialize & val) == val) {
5129 : 0 : DRV_LOG(ERR, "Invalid hint value %x",
5130 : : attr->specialize);
5131 : 0 : rte_errno = EINVAL;
5132 : 0 : goto it_error;
5133 : : }
5134 [ # # ]: 0 : if (attr->specialize &
5135 : : RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_WIRE_ORIG) {
5136 : 0 : matcher_attr.optimize_flow_src =
5137 : : MLX5DR_MATCHER_FLOW_SRC_WIRE;
5138 [ # # ]: 0 : } else if (attr->specialize &
5139 : : RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_VPORT_ORIG) {
5140 : 0 : matcher_attr.optimize_flow_src =
5141 : : MLX5DR_MATCHER_FLOW_SRC_VPORT;
5142 : : }
5143 : : }
5144 : : /* Build the item template. */
5145 [ # # ]: 0 : for (i = 0; i < nb_item_templates; i++) {
5146 : : uint32_t ret;
5147 : :
5148 [ # # # # ]: 0 : if ((flow_attr.ingress && !item_templates[i]->attr.ingress) ||
5149 [ # # # # ]: 0 : (flow_attr.egress && !item_templates[i]->attr.egress) ||
5150 [ # # # # ]: 0 : (flow_attr.transfer && !item_templates[i]->attr.transfer)) {
5151 : 0 : DRV_LOG(ERR, "pattern template and template table attribute mismatch");
5152 : 0 : rte_errno = EINVAL;
5153 : 0 : goto it_error;
5154 : : }
5155 [ # # ]: 0 : if (item_templates[i]->item_flags & MLX5_FLOW_ITEM_COMPARE)
5156 : 0 : matcher_attr.mode = MLX5DR_MATCHER_RESOURCE_MODE_HTABLE;
5157 : 0 : ret = rte_atomic_fetch_add_explicit(&item_templates[i]->refcnt, 1,
5158 : : rte_memory_order_relaxed) + 1;
5159 [ # # ]: 0 : if (ret <= 1) {
5160 : 0 : rte_errno = EINVAL;
5161 : 0 : goto it_error;
5162 : : }
5163 : 0 : mt[i] = item_templates[i]->mt;
5164 : 0 : tbl->its[i] = item_templates[i];
5165 : : }
5166 : 0 : tbl->nb_item_templates = nb_item_templates;
5167 : : /* Build the action template. */
5168 : 0 : err = mlx5_hw_build_template_table(dev, nb_action_templates,
5169 : : action_templates, at, tbl, &sub_error);
5170 [ # # ]: 0 : if (err) {
5171 : : i = nb_item_templates;
5172 : 0 : goto it_error;
5173 : : }
5174 : 0 : tbl->matcher_info[0].matcher = mlx5dr_matcher_create
5175 : 0 : (tbl->grp->tbl, mt, nb_item_templates, at, nb_action_templates, &matcher_attr);
5176 [ # # ]: 0 : if (!tbl->matcher_info[0].matcher)
5177 : 0 : goto at_error;
5178 : 0 : tbl->matcher_attr = matcher_attr;
5179 : 0 : tbl->type = table_type;
5180 [ # # ]: 0 : if (matcher_attr.isolated) {
5181 : 0 : jump_attr.matcher = tbl->matcher_info[0].matcher;
5182 : 0 : tbl->matcher_info[0].jump = mlx5dr_action_create_jump_to_matcher(priv->dr_ctx,
5183 : 0 : &jump_attr, mlx5_hw_act_flag[!!attr->flow_attr.group][tbl->type]);
5184 [ # # ]: 0 : if (!tbl->matcher_info[0].jump)
5185 : 0 : goto jtm_error;
5186 : : }
5187 : : /*
5188 : : * Only the matcher supports update and needs more than 1 WQE, an additional
5189 : : * index is needed. Or else the flow index can be reused.
5190 : : */
5191 [ # # # # ]: 0 : rpool_needed = mlx5dr_matcher_is_updatable(tbl->matcher_info[0].matcher) &&
5192 : 0 : mlx5dr_matcher_is_dependent(tbl->matcher_info[0].matcher);
5193 [ # # ]: 0 : if (rpool_needed) {
5194 : : /* Allocate rule indexed pool. */
5195 : 0 : cfg.size = 0;
5196 : 0 : cfg.type = "mlx5_hw_table_rule";
5197 : 0 : cfg.max_idx += priv->hw_q[0].size;
5198 : 0 : tbl->resource = mlx5_ipool_create(&cfg);
5199 [ # # ]: 0 : if (!tbl->resource)
5200 : 0 : goto res_error;
5201 : : }
5202 [ # # ]: 0 : if (port_started)
5203 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->flow_hw_tbl, tbl, next);
5204 : : else
5205 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->flow_hw_tbl_ongo, tbl, next);
5206 : : rte_rwlock_init(&tbl->matcher_replace_rwlk);
5207 : 0 : return tbl;
5208 : : res_error:
5209 [ # # ]: 0 : if (tbl->matcher_info[0].jump)
5210 : 0 : mlx5dr_action_destroy(tbl->matcher_info[0].jump);
5211 : 0 : jtm_error:
5212 [ # # ]: 0 : if (tbl->matcher_info[0].matcher)
5213 : 0 : (void)mlx5dr_matcher_destroy(tbl->matcher_info[0].matcher);
5214 : 0 : at_error:
5215 [ # # ]: 0 : for (i = 0; i < nb_action_templates; i++) {
5216 : 0 : __flow_hw_action_template_destroy(dev, &tbl->ats[i].acts);
5217 : 0 : rte_atomic_fetch_sub_explicit(&action_templates[i]->refcnt,
5218 : : 1, rte_memory_order_relaxed);
5219 : : }
5220 : : i = nb_item_templates;
5221 : : it_error:
5222 [ # # ]: 0 : while (i--)
5223 : 0 : rte_atomic_fetch_sub_explicit(&item_templates[i]->refcnt,
5224 : : 1, rte_memory_order_relaxed);
5225 : 0 : error:
5226 : 0 : err = rte_errno;
5227 [ # # ]: 0 : if (tbl) {
5228 [ # # ]: 0 : if (tbl->grp)
5229 : 0 : mlx5_hlist_unregister(priv->sh->groups,
5230 : : &tbl->grp->entry);
5231 [ # # ]: 0 : if (tbl->flow_aux)
5232 : 0 : mlx5_free(tbl->flow_aux);
5233 [ # # ]: 0 : if (tbl->flow)
5234 : 0 : mlx5_ipool_destroy(tbl->flow);
5235 : 0 : mlx5_free(tbl);
5236 : : }
5237 [ # # ]: 0 : if (error != NULL) {
5238 [ # # ]: 0 : if (sub_error.type == RTE_FLOW_ERROR_TYPE_NONE)
5239 : 0 : rte_flow_error_set(error, err, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5240 : : "Failed to create template table");
5241 : : else
5242 : : rte_memcpy(error, &sub_error, sizeof(sub_error));
5243 : : }
5244 : : return NULL;
5245 : : }
5246 : :
5247 : : /**
5248 : : * Update flow template table.
5249 : : *
5250 : : * @param[in] dev
5251 : : * Pointer to the rte_eth_dev structure.
5252 : : * @param[out] error
5253 : : * Pointer to error structure.
5254 : : *
5255 : : * @return
5256 : : * 0 on success, negative value otherwise and rte_errno is set.
5257 : : */
5258 : : int
5259 : 0 : flow_hw_table_update(struct rte_eth_dev *dev,
5260 : : struct rte_flow_error *error)
5261 : : {
5262 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
5263 : : struct rte_flow_template_table *tbl;
5264 : :
5265 [ # # ]: 0 : while ((tbl = LIST_FIRST(&priv->flow_hw_tbl_ongo)) != NULL) {
5266 [ # # ]: 0 : if (flow_hw_translate_all_actions_templates(dev, tbl, error))
5267 : : return -1;
5268 [ # # ]: 0 : LIST_REMOVE(tbl, next);
5269 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->flow_hw_tbl, tbl, next);
5270 : : }
5271 : : return 0;
5272 : : }
5273 : :
5274 : : static inline int
5275 : 0 : __translate_group(struct rte_eth_dev *dev,
5276 : : const struct rte_flow_attr *flow_attr,
5277 : : bool external,
5278 : : uint32_t group,
5279 : : uint32_t *table_group,
5280 : : struct rte_flow_error *error)
5281 : : {
5282 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
5283 : 0 : struct mlx5_sh_config *config = &priv->sh->config;
5284 : :
5285 [ # # ]: 0 : if (config->dv_esw_en &&
5286 [ # # # # ]: 0 : priv->fdb_def_rule &&
5287 [ # # ]: 0 : external &&
5288 : : flow_attr->transfer) {
5289 [ # # ]: 0 : if (group > MLX5_HW_MAX_TRANSFER_GROUP)
5290 : 0 : return rte_flow_error_set(error, EINVAL,
5291 : : RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5292 : : NULL,
5293 : : "group index not supported");
5294 : 0 : *table_group = group + 1;
5295 [ # # ]: 0 : } else if (config->dv_esw_en &&
5296 [ # # # # : 0 : (config->repr_matching || config->dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS) &&
# # ]
5297 [ # # ]: 0 : external &&
5298 : : flow_attr->egress) {
5299 : : /*
5300 : : * On E-Switch setups, default egress flow rules are inserted to allow
5301 : : * representor matching and/or preserving metadata across steering domains.
5302 : : * These flow rules are inserted in group 0 and this group is reserved by PMD
5303 : : * for these purposes.
5304 : : *
5305 : : * As a result, if representor matching or extended metadata mode is enabled,
5306 : : * group provided by the user must be incremented to avoid inserting flow rules
5307 : : * in group 0.
5308 : : */
5309 [ # # ]: 0 : if (group > MLX5_HW_MAX_EGRESS_GROUP)
5310 : 0 : return rte_flow_error_set(error, EINVAL,
5311 : : RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5312 : : NULL,
5313 : : "group index not supported");
5314 : 0 : *table_group = group + 1;
5315 : : } else {
5316 : 0 : *table_group = group;
5317 : : }
5318 : : return 0;
5319 : : }
5320 : :
5321 : : /**
5322 : : * Translates group index specified by the user in @p attr to internal
5323 : : * group index.
5324 : : *
5325 : : * Translation is done by incrementing group index, so group n becomes n + 1.
5326 : : *
5327 : : * @param[in] dev
5328 : : * Pointer to Ethernet device.
5329 : : * @param[in] cfg
5330 : : * Pointer to the template table configuration.
5331 : : * @param[in] group
5332 : : * Currently used group index (table group or jump destination).
5333 : : * @param[out] table_group
5334 : : * Pointer to output group index.
5335 : : * @param[out] error
5336 : : * Pointer to error structure.
5337 : : *
5338 : : * @return
5339 : : * 0 on success. Otherwise, returns negative error code, rte_errno is set
5340 : : * and error structure is filled.
5341 : : */
5342 : : static int
5343 : : flow_hw_translate_group(struct rte_eth_dev *dev,
5344 : : const struct mlx5_flow_template_table_cfg *cfg,
5345 : : uint32_t group,
5346 : : uint32_t *table_group,
5347 : : struct rte_flow_error *error)
5348 : : {
5349 : 0 : const struct rte_flow_attr *flow_attr = &cfg->attr.flow_attr;
5350 : :
5351 : 0 : return __translate_group(dev, flow_attr, cfg->external, group, table_group, error);
5352 : : }
5353 : :
5354 : : /**
5355 : : * Create flow table.
5356 : : *
5357 : : * This function is a wrapper over @ref flow_hw_table_create(), which translates parameters
5358 : : * provided by user to proper internal values.
5359 : : *
5360 : : * @param[in] dev
5361 : : * Pointer to Ethernet device.
5362 : : * @param[in] attr
5363 : : * Pointer to the table attributes.
5364 : : * @param[in] item_templates
5365 : : * Item template array to be binded to the table.
5366 : : * @param[in] nb_item_templates
5367 : : * Number of item templates.
5368 : : * @param[in] action_templates
5369 : : * Action template array to be binded to the table.
5370 : : * @param[in] nb_action_templates
5371 : : * Number of action templates.
5372 : : * @param[out] error
5373 : : * Pointer to error structure.
5374 : : *
5375 : : * @return
5376 : : * Table on success, Otherwise, returns negative error code, rte_errno is set
5377 : : * and error structure is filled.
5378 : : */
5379 : : static struct rte_flow_template_table *
5380 : 0 : flow_hw_template_table_create(struct rte_eth_dev *dev,
5381 : : const struct rte_flow_template_table_attr *attr,
5382 : : struct rte_flow_pattern_template *item_templates[],
5383 : : uint8_t nb_item_templates,
5384 : : struct rte_flow_actions_template *action_templates[],
5385 : : uint8_t nb_action_templates,
5386 : : struct rte_flow_error *error)
5387 : : {
5388 : 0 : struct mlx5_flow_template_table_cfg cfg = {
5389 : : .attr = *attr,
5390 : : .external = true,
5391 : : };
5392 : 0 : uint32_t group = attr->flow_attr.group;
5393 : :
5394 [ # # ]: 0 : if (flow_hw_translate_group(dev, &cfg, group, &cfg.attr.flow_attr.group, error))
5395 : : return NULL;
5396 [ # # # # ]: 0 : if (!cfg.attr.flow_attr.group &&
5397 : 0 : rte_flow_template_table_resizable(dev->data->port_id, attr)) {
5398 : 0 : rte_flow_error_set(error, EINVAL,
5399 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5400 : : "table cannot be resized: invalid group");
5401 : 0 : return NULL;
5402 : : }
5403 : 0 : return flow_hw_table_create(dev, &cfg, item_templates, nb_item_templates,
5404 : : action_templates, nb_action_templates, error);
5405 : : }
5406 : :
5407 : : static void
5408 : 0 : mlx5_destroy_multi_pattern_segment(struct mlx5_multi_pattern_segment *segment)
5409 : : {
5410 : : int i;
5411 : :
5412 [ # # ]: 0 : if (segment->mhdr_action)
5413 : 0 : mlx5dr_action_destroy(segment->mhdr_action);
5414 [ # # ]: 0 : for (i = 0; i < MLX5_MULTIPATTERN_ENCAP_NUM; i++) {
5415 [ # # ]: 0 : if (segment->reformat_action[i])
5416 : 0 : mlx5dr_action_destroy(segment->reformat_action[i]);
5417 : : }
5418 : 0 : segment->capacity = 0;
5419 : 0 : }
5420 : :
5421 : : static void
5422 : : flow_hw_destroy_table_multi_pattern_ctx(struct rte_flow_template_table *table)
5423 : : {
5424 : : int sx;
5425 : :
5426 [ # # ]: 0 : for (sx = 0; sx < MLX5_MAX_TABLE_RESIZE_NUM; sx++)
5427 : 0 : mlx5_destroy_multi_pattern_segment(table->mpctx.segments + sx);
5428 : : }
5429 : : /**
5430 : : * Destroy flow table.
5431 : : *
5432 : : * @param[in] dev
5433 : : * Pointer to the rte_eth_dev structure.
5434 : : * @param[in] table
5435 : : * Pointer to the table to be destroyed.
5436 : : * @param[out] error
5437 : : * Pointer to error structure.
5438 : : *
5439 : : * @return
5440 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
5441 : : */
5442 : : static int
5443 : 0 : flow_hw_table_destroy(struct rte_eth_dev *dev,
5444 : : struct rte_flow_template_table *table,
5445 : : struct rte_flow_error *error)
5446 : : {
5447 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
5448 : : int i;
5449 : 0 : uint32_t fidx = 1;
5450 : 0 : uint32_t ridx = 1;
5451 : :
5452 : : /* Build ipool allocated object bitmap. */
5453 [ # # ]: 0 : if (table->resource)
5454 : 0 : mlx5_ipool_flush_cache(table->resource);
5455 : 0 : mlx5_ipool_flush_cache(table->flow);
5456 : : /* Check if ipool has allocated objects. */
5457 [ # # # # ]: 0 : if (table->refcnt ||
5458 : 0 : mlx5_ipool_get_next(table->flow, &fidx) ||
5459 [ # # # # ]: 0 : (table->resource && mlx5_ipool_get_next(table->resource, &ridx))) {
5460 : 0 : DRV_LOG(WARNING, "Table %p is still in use.", (void *)table);
5461 : 0 : return rte_flow_error_set(error, EBUSY,
5462 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5463 : : NULL,
5464 : : "table is in use");
5465 : : }
5466 [ # # ]: 0 : LIST_REMOVE(table, next);
5467 [ # # ]: 0 : for (i = 0; i < table->nb_item_templates; i++)
5468 : 0 : rte_atomic_fetch_sub_explicit(&table->its[i]->refcnt,
5469 : : 1, rte_memory_order_relaxed);
5470 [ # # ]: 0 : for (i = 0; i < table->nb_action_templates; i++) {
5471 : 0 : __flow_hw_action_template_destroy(dev, &table->ats[i].acts);
5472 : 0 : rte_atomic_fetch_sub_explicit(&table->ats[i].action_template->refcnt,
5473 : : 1, rte_memory_order_relaxed);
5474 : : }
5475 : : flow_hw_destroy_table_multi_pattern_ctx(table);
5476 [ # # ]: 0 : if (table->matcher_info[0].jump)
5477 : 0 : mlx5dr_action_destroy(table->matcher_info[0].jump);
5478 [ # # ]: 0 : if (table->matcher_info[0].matcher)
5479 : 0 : mlx5dr_matcher_destroy(table->matcher_info[0].matcher);
5480 [ # # ]: 0 : if (table->matcher_info[1].jump)
5481 : 0 : mlx5dr_action_destroy(table->matcher_info[1].jump);
5482 [ # # ]: 0 : if (table->matcher_info[1].matcher)
5483 : 0 : mlx5dr_matcher_destroy(table->matcher_info[1].matcher);
5484 : 0 : mlx5_hlist_unregister(priv->sh->groups, &table->grp->entry);
5485 [ # # ]: 0 : if (table->resource)
5486 : 0 : mlx5_ipool_destroy(table->resource);
5487 : 0 : mlx5_free(table->flow_aux);
5488 : 0 : mlx5_ipool_destroy(table->flow);
5489 : 0 : mlx5_free(table);
5490 : 0 : return 0;
5491 : : }
5492 : :
5493 : : /**
5494 : : * Parse group's miss actions.
5495 : : *
5496 : : * @param[in] dev
5497 : : * Pointer to the rte_eth_dev structure.
5498 : : * @param[in] cfg
5499 : : * Pointer to the table_cfg structure.
5500 : : * @param[in] actions
5501 : : * Array of actions to perform on group miss. Supported types:
5502 : : * RTE_FLOW_ACTION_TYPE_JUMP, RTE_FLOW_ACTION_TYPE_VOID, RTE_FLOW_ACTION_TYPE_END.
5503 : : * @param[out] dst_group_id
5504 : : * Pointer to destination group id output. will be set to 0 if actions is END,
5505 : : * otherwise will be set to destination group id.
5506 : : * @param[out] error
5507 : : * Pointer to error structure.
5508 : : *
5509 : : * @return
5510 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
5511 : : */
5512 : :
5513 : : static int
5514 : 0 : flow_hw_group_parse_miss_actions(struct rte_eth_dev *dev,
5515 : : struct mlx5_flow_template_table_cfg *cfg,
5516 : : const struct rte_flow_action actions[],
5517 : : uint32_t *dst_group_id,
5518 : : struct rte_flow_error *error)
5519 : : {
5520 : : const struct rte_flow_action_jump *jump_conf;
5521 : 0 : uint32_t temp = 0;
5522 : : uint32_t i;
5523 : :
5524 [ # # ]: 0 : for (i = 0; actions[i].type != RTE_FLOW_ACTION_TYPE_END; i++) {
5525 [ # # # ]: 0 : switch (actions[i].type) {
5526 : 0 : case RTE_FLOW_ACTION_TYPE_VOID:
5527 : 0 : continue;
5528 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP:
5529 [ # # ]: 0 : if (temp)
5530 : 0 : return rte_flow_error_set(error, ENOTSUP,
5531 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, actions,
5532 : : "Miss actions can contain only a single JUMP");
5533 : :
5534 : 0 : jump_conf = (const struct rte_flow_action_jump *)actions[i].conf;
5535 [ # # ]: 0 : if (!jump_conf)
5536 : 0 : return rte_flow_error_set(error, EINVAL,
5537 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5538 : : jump_conf, "Jump conf must not be NULL");
5539 : :
5540 [ # # ]: 0 : if (flow_hw_translate_group(dev, cfg, jump_conf->group, &temp, error))
5541 : 0 : return -rte_errno;
5542 : :
5543 [ # # ]: 0 : if (!temp)
5544 : 0 : return rte_flow_error_set(error, EINVAL,
5545 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5546 : : "Failed to set group miss actions - Invalid target group");
5547 : : break;
5548 : 0 : default:
5549 : 0 : return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
5550 : : &actions[i], "Unsupported default miss action type");
5551 : : }
5552 : : }
5553 : :
5554 : 0 : *dst_group_id = temp;
5555 : 0 : return 0;
5556 : : }
5557 : :
5558 : : /**
5559 : : * Set group's miss group.
5560 : : *
5561 : : * @param[in] dev
5562 : : * Pointer to the rte_eth_dev structure.
5563 : : * @param[in] cfg
5564 : : * Pointer to the table_cfg structure.
5565 : : * @param[in] src_grp
5566 : : * Pointer to source group structure.
5567 : : * if NULL, a new group will be created based on group id from cfg->attr.flow_attr.group.
5568 : : * @param[in] dst_grp
5569 : : * Pointer to destination group structure.
5570 : : * @param[out] error
5571 : : * Pointer to error structure.
5572 : : *
5573 : : * @return
5574 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
5575 : : */
5576 : :
5577 : : static int
5578 : 0 : flow_hw_group_set_miss_group(struct rte_eth_dev *dev,
5579 : : struct mlx5_flow_template_table_cfg *cfg,
5580 : : struct mlx5_flow_group *src_grp,
5581 : : struct mlx5_flow_group *dst_grp,
5582 : : struct rte_flow_error *error)
5583 : : {
5584 : 0 : struct rte_flow_error sub_error = {
5585 : : .type = RTE_FLOW_ERROR_TYPE_NONE,
5586 : : .cause = NULL,
5587 : : .message = NULL,
5588 : : };
5589 : 0 : struct mlx5_flow_cb_ctx ctx = {
5590 : : .dev = dev,
5591 : : .error = &sub_error,
5592 : 0 : .data = &cfg->attr.flow_attr,
5593 : 0 : .data2 = &cfg->attr.specialize,
5594 : : };
5595 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
5596 : : struct mlx5_list_entry *ge;
5597 : : bool ref = false;
5598 : : int ret;
5599 : :
5600 [ # # ]: 0 : if (!dst_grp)
5601 : : return -EINVAL;
5602 : :
5603 : : /* If group doesn't exist - needs to be created. */
5604 [ # # ]: 0 : if (!src_grp) {
5605 : 0 : ge = mlx5_hlist_register(priv->sh->groups, cfg->attr.flow_attr.group, &ctx);
5606 [ # # ]: 0 : if (!ge)
5607 : 0 : return -rte_errno;
5608 : :
5609 : : src_grp = container_of(ge, struct mlx5_flow_group, entry);
5610 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->flow_hw_grp, src_grp, next);
5611 : : ref = true;
5612 [ # # ]: 0 : } else if (!src_grp->miss_group) {
5613 : : /* If group exists, but has no miss actions - need to increase ref_cnt. */
5614 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->flow_hw_grp, src_grp, next);
5615 : 0 : src_grp->entry.ref_cnt++;
5616 : : ref = true;
5617 : : }
5618 : :
5619 : 0 : ret = mlx5dr_table_set_default_miss(src_grp->tbl, dst_grp->tbl);
5620 [ # # ]: 0 : if (ret)
5621 : 0 : goto mlx5dr_error;
5622 : :
5623 : : /* If group existed and had old miss actions - ref_cnt is already correct.
5624 : : * However, need to reduce ref counter for old miss group.
5625 : : */
5626 [ # # ]: 0 : if (src_grp->miss_group)
5627 : 0 : mlx5_hlist_unregister(priv->sh->groups, &src_grp->miss_group->entry);
5628 : :
5629 : 0 : src_grp->miss_group = dst_grp;
5630 : 0 : return 0;
5631 : :
5632 : : mlx5dr_error:
5633 : : /* Reduce src_grp ref_cnt back & remove from grp list in case of mlx5dr error */
5634 [ # # ]: 0 : if (ref) {
5635 : 0 : mlx5_hlist_unregister(priv->sh->groups, &src_grp->entry);
5636 [ # # ]: 0 : LIST_REMOVE(src_grp, next);
5637 : : }
5638 : :
5639 : 0 : return rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5640 : : "Failed to set group miss actions");
5641 : : }
5642 : :
5643 : : /**
5644 : : * Unset group's miss group.
5645 : : *
5646 : : * @param[in] dev
5647 : : * Pointer to the rte_eth_dev structure.
5648 : : * @param[in] grp
5649 : : * Pointer to group structure.
5650 : : * @param[out] error
5651 : : * Pointer to error structure.
5652 : : *
5653 : : * @return
5654 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
5655 : : */
5656 : :
5657 : : static int
5658 : 0 : flow_hw_group_unset_miss_group(struct rte_eth_dev *dev,
5659 : : struct mlx5_flow_group *grp,
5660 : : struct rte_flow_error *error)
5661 : : {
5662 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
5663 : : int ret;
5664 : :
5665 : : /* If group doesn't exist - no need to change anything. */
5666 [ # # ]: 0 : if (!grp)
5667 : : return 0;
5668 : :
5669 : : /* If group exists, but miss actions is already default behavior -
5670 : : * no need to change anything.
5671 : : */
5672 [ # # ]: 0 : if (!grp->miss_group)
5673 : : return 0;
5674 : :
5675 : 0 : ret = mlx5dr_table_set_default_miss(grp->tbl, NULL);
5676 [ # # ]: 0 : if (ret)
5677 : 0 : return rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5678 : : "Failed to unset group miss actions");
5679 : :
5680 : 0 : mlx5_hlist_unregister(priv->sh->groups, &grp->miss_group->entry);
5681 : 0 : grp->miss_group = NULL;
5682 : :
5683 [ # # ]: 0 : LIST_REMOVE(grp, next);
5684 : 0 : mlx5_hlist_unregister(priv->sh->groups, &grp->entry);
5685 : :
5686 : 0 : return 0;
5687 : : }
5688 : :
5689 : : /**
5690 : : * Set group miss actions.
5691 : : *
5692 : : * @param[in] dev
5693 : : * Pointer to the rte_eth_dev structure.
5694 : : * @param[in] group_id
5695 : : * Group id.
5696 : : * @param[in] attr
5697 : : * Pointer to group attributes structure.
5698 : : * @param[in] actions
5699 : : * Array of actions to perform on group miss. Supported types:
5700 : : * RTE_FLOW_ACTION_TYPE_JUMP, RTE_FLOW_ACTION_TYPE_VOID, RTE_FLOW_ACTION_TYPE_END.
5701 : : * @param[out] error
5702 : : * Pointer to error structure.
5703 : : *
5704 : : * @return
5705 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
5706 : : */
5707 : :
5708 : : static int
5709 : 0 : flow_hw_group_set_miss_actions(struct rte_eth_dev *dev,
5710 : : uint32_t group_id,
5711 : : const struct rte_flow_group_attr *attr,
5712 : : const struct rte_flow_action actions[],
5713 : : struct rte_flow_error *error)
5714 : : {
5715 : 0 : struct rte_flow_error sub_error = {
5716 : : .type = RTE_FLOW_ERROR_TYPE_NONE,
5717 : : .cause = NULL,
5718 : : .message = NULL,
5719 : : };
5720 : 0 : struct mlx5_flow_template_table_cfg cfg = {
5721 : : .external = true,
5722 : : .attr = {
5723 : : .flow_attr = {
5724 : : .group = group_id,
5725 : 0 : .ingress = attr->ingress,
5726 : 0 : .egress = attr->egress,
5727 : 0 : .transfer = attr->transfer,
5728 : : },
5729 : : },
5730 : : };
5731 : 0 : struct mlx5_flow_cb_ctx ctx = {
5732 : : .dev = dev,
5733 : : .error = &sub_error,
5734 : : .data = &cfg.attr.flow_attr,
5735 : : .data2 = &cfg.attr.specialize,
5736 : : };
5737 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
5738 : : struct mlx5_flow_group *src_grp = NULL;
5739 : : struct mlx5_flow_group *dst_grp = NULL;
5740 : : struct mlx5_list_entry *ge;
5741 : 0 : uint32_t dst_group_id = 0;
5742 : : int ret;
5743 : :
5744 [ # # ]: 0 : if (flow_hw_translate_group(dev, &cfg, group_id, &group_id, error))
5745 : 0 : return -rte_errno;
5746 : :
5747 [ # # ]: 0 : if (!group_id)
5748 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5749 : : NULL, "Failed to set group miss actions - invalid group id");
5750 : :
5751 : 0 : ret = flow_hw_group_parse_miss_actions(dev, &cfg, actions, &dst_group_id, error);
5752 [ # # ]: 0 : if (ret)
5753 : 0 : return -rte_errno;
5754 : :
5755 [ # # ]: 0 : if (dst_group_id == group_id) {
5756 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5757 : : NULL, "Failed to set group miss actions - target group id must differ from group_id");
5758 : : }
5759 : :
5760 : 0 : cfg.attr.flow_attr.group = group_id;
5761 : 0 : ge = mlx5_hlist_lookup(priv->sh->groups, group_id, &ctx);
5762 [ # # ]: 0 : if (ge)
5763 : : src_grp = container_of(ge, struct mlx5_flow_group, entry);
5764 : :
5765 [ # # ]: 0 : if (dst_group_id) {
5766 : : /* Increase ref_cnt for new miss group. */
5767 : 0 : cfg.attr.flow_attr.group = dst_group_id;
5768 : 0 : ge = mlx5_hlist_register(priv->sh->groups, dst_group_id, &ctx);
5769 [ # # ]: 0 : if (!ge)
5770 : 0 : return -rte_errno;
5771 : :
5772 : : dst_grp = container_of(ge, struct mlx5_flow_group, entry);
5773 : :
5774 : 0 : cfg.attr.flow_attr.group = group_id;
5775 : 0 : ret = flow_hw_group_set_miss_group(dev, &cfg, src_grp, dst_grp, error);
5776 [ # # ]: 0 : if (ret)
5777 : 0 : goto error;
5778 : : } else {
5779 : 0 : return flow_hw_group_unset_miss_group(dev, src_grp, error);
5780 : : }
5781 : :
5782 : : return 0;
5783 : :
5784 : : error:
5785 : : if (dst_grp)
5786 : 0 : mlx5_hlist_unregister(priv->sh->groups, &dst_grp->entry);
5787 : 0 : return -rte_errno;
5788 : : }
5789 : :
5790 : : static bool
5791 : : flow_hw_modify_field_is_used(const struct rte_flow_action_modify_field *action,
5792 : : enum rte_flow_field_id field)
5793 : : {
5794 [ # # # # : 0 : return action->src.field == field || action->dst.field == field;
# # # # #
# # # # #
# # # # #
# # # # #
# # # # ]
5795 : : }
5796 : :
5797 : : static bool
5798 : : flow_hw_modify_field_is_geneve_opt(enum rte_flow_field_id field)
5799 : : {
5800 : : return field == RTE_FLOW_FIELD_GENEVE_OPT_TYPE ||
5801 : 0 : field == RTE_FLOW_FIELD_GENEVE_OPT_CLASS ||
5802 : : field == RTE_FLOW_FIELD_GENEVE_OPT_DATA;
5803 : : }
5804 : :
5805 : : static bool
5806 : 0 : flow_hw_modify_field_is_add_dst_valid(const struct rte_flow_action_modify_field *conf)
5807 : : {
5808 [ # # ]: 0 : if (conf->operation != RTE_FLOW_MODIFY_ADD)
5809 : : return true;
5810 [ # # ]: 0 : if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
5811 : : conf->src.field == RTE_FLOW_FIELD_VALUE)
5812 : : return true;
5813 [ # # ]: 0 : switch (conf->dst.field) {
5814 : : case RTE_FLOW_FIELD_IPV4_TTL:
5815 : : case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
5816 : : case RTE_FLOW_FIELD_TCP_SEQ_NUM:
5817 : : case RTE_FLOW_FIELD_TCP_ACK_NUM:
5818 : : case RTE_FLOW_FIELD_TAG:
5819 : : case RTE_FLOW_FIELD_META:
5820 : : case RTE_FLOW_FIELD_FLEX_ITEM:
5821 : : case RTE_FLOW_FIELD_TCP_DATA_OFFSET:
5822 : : case RTE_FLOW_FIELD_IPV4_IHL:
5823 : : case RTE_FLOW_FIELD_IPV4_TOTAL_LEN:
5824 : : case RTE_FLOW_FIELD_IPV6_PAYLOAD_LEN:
5825 : : return true;
5826 : : default:
5827 : : break;
5828 : : }
5829 : 0 : return false;
5830 : : }
5831 : :
5832 : : /**
5833 : : * Validate the level value for modify field action.
5834 : : *
5835 : : * @param[in] data
5836 : : * Pointer to the rte_flow_field_data structure either src or dst.
5837 : : * @param[in] inner_supported
5838 : : * Indicator whether inner should be supported.
5839 : : * @param[out] error
5840 : : * Pointer to error structure.
5841 : : *
5842 : : * @return
5843 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
5844 : : */
5845 : : static int
5846 : 0 : flow_hw_validate_modify_field_level(const struct rte_flow_field_data *data,
5847 : : bool inner_supported,
5848 : : struct rte_flow_error *error)
5849 : : {
5850 [ # # # # : 0 : switch ((int)data->field) {
# ]
5851 : : case RTE_FLOW_FIELD_START:
5852 : : case RTE_FLOW_FIELD_VLAN_TYPE:
5853 : : case RTE_FLOW_FIELD_RANDOM:
5854 : : case RTE_FLOW_FIELD_FLEX_ITEM:
5855 : : /*
5856 : : * Level shouldn't be valid since field isn't supported or
5857 : : * doesn't use 'level'.
5858 : : */
5859 : : break;
5860 : : case RTE_FLOW_FIELD_MARK:
5861 : : case RTE_FLOW_FIELD_META:
5862 : : case RTE_FLOW_FIELD_METER_COLOR:
5863 : : case RTE_FLOW_FIELD_HASH_RESULT:
5864 : : /* For meta data fields encapsulation level is don't-care. */
5865 : : break;
5866 : 0 : case RTE_FLOW_FIELD_TAG:
5867 : : case MLX5_RTE_FLOW_FIELD_META_REG:
5868 : : /*
5869 : : * The tag array for RTE_FLOW_FIELD_TAG type is provided using
5870 : : * 'tag_index' field. In old API, it was provided using 'level'
5871 : : * field and it is still supported for backwards compatibility.
5872 : : * Therefore, for meta tag field only, level is matter. It is
5873 : : * taken as tag index when 'tag_index' field isn't set, and
5874 : : * return error otherwise.
5875 : : */
5876 [ # # ]: 0 : if (data->level > 0) {
5877 [ # # ]: 0 : if (data->tag_index > 0)
5878 : 0 : return rte_flow_error_set(error, EINVAL,
5879 : : RTE_FLOW_ERROR_TYPE_ACTION,
5880 : : data,
5881 : : "tag array can be provided using 'level' or 'tag_index' fields, not both");
5882 : 0 : DRV_LOG(WARNING,
5883 : : "tag array provided in 'level' field instead of 'tag_index' field.");
5884 : : }
5885 : : break;
5886 : 0 : case RTE_FLOW_FIELD_MAC_DST:
5887 : : case RTE_FLOW_FIELD_MAC_SRC:
5888 : : case RTE_FLOW_FIELD_MAC_TYPE:
5889 : : case RTE_FLOW_FIELD_IPV4_IHL:
5890 : : case RTE_FLOW_FIELD_IPV4_TOTAL_LEN:
5891 : : case RTE_FLOW_FIELD_IPV4_DSCP:
5892 : : case RTE_FLOW_FIELD_IPV4_ECN:
5893 : : case RTE_FLOW_FIELD_IPV4_TTL:
5894 : : case RTE_FLOW_FIELD_IPV4_SRC:
5895 : : case RTE_FLOW_FIELD_IPV4_DST:
5896 : : case RTE_FLOW_FIELD_IPV6_TRAFFIC_CLASS:
5897 : : case RTE_FLOW_FIELD_IPV6_FLOW_LABEL:
5898 : : case RTE_FLOW_FIELD_IPV6_PAYLOAD_LEN:
5899 : : case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
5900 : : case RTE_FLOW_FIELD_IPV6_SRC:
5901 : : case RTE_FLOW_FIELD_IPV6_DST:
5902 : : case RTE_FLOW_FIELD_TCP_PORT_SRC:
5903 : : case RTE_FLOW_FIELD_TCP_PORT_DST:
5904 : : case RTE_FLOW_FIELD_TCP_FLAGS:
5905 : : case RTE_FLOW_FIELD_TCP_DATA_OFFSET:
5906 : : case RTE_FLOW_FIELD_UDP_PORT_SRC:
5907 : : case RTE_FLOW_FIELD_UDP_PORT_DST:
5908 [ # # ]: 0 : if (data->level > 2)
5909 : 0 : return rte_flow_error_set(error, ENOTSUP,
5910 : : RTE_FLOW_ERROR_TYPE_ACTION,
5911 : : data,
5912 : : "second inner header fields modification is not supported");
5913 [ # # ]: 0 : if (inner_supported)
5914 : : break;
5915 : : /* Fallthrough */
5916 : : case RTE_FLOW_FIELD_VLAN_ID:
5917 : : case RTE_FLOW_FIELD_IPV4_PROTO:
5918 : : case RTE_FLOW_FIELD_IPV6_PROTO:
5919 : : case RTE_FLOW_FIELD_IPV6_DSCP:
5920 : : case RTE_FLOW_FIELD_IPV6_ECN:
5921 : : case RTE_FLOW_FIELD_TCP_SEQ_NUM:
5922 : : case RTE_FLOW_FIELD_TCP_ACK_NUM:
5923 : : case RTE_FLOW_FIELD_ESP_PROTO:
5924 : : case RTE_FLOW_FIELD_ESP_SPI:
5925 : : case RTE_FLOW_FIELD_ESP_SEQ_NUM:
5926 : : case RTE_FLOW_FIELD_VXLAN_VNI:
5927 : : case RTE_FLOW_FIELD_VXLAN_LAST_RSVD:
5928 : : case RTE_FLOW_FIELD_GENEVE_VNI:
5929 : : case RTE_FLOW_FIELD_GENEVE_OPT_TYPE:
5930 : : case RTE_FLOW_FIELD_GENEVE_OPT_CLASS:
5931 : : case RTE_FLOW_FIELD_GENEVE_OPT_DATA:
5932 : : case RTE_FLOW_FIELD_GTP_TEID:
5933 : : case RTE_FLOW_FIELD_GTP_PSC_QFI:
5934 [ # # ]: 0 : if (data->level > 1)
5935 : 0 : return rte_flow_error_set(error, ENOTSUP,
5936 : : RTE_FLOW_ERROR_TYPE_ACTION,
5937 : : data,
5938 : : "inner header fields modification is not supported");
5939 : : break;
5940 : 0 : case RTE_FLOW_FIELD_MPLS:
5941 [ # # ]: 0 : if (data->level == 1)
5942 : 0 : return rte_flow_error_set(error, ENOTSUP,
5943 : : RTE_FLOW_ERROR_TYPE_ACTION,
5944 : : data,
5945 : : "outer MPLS header modification is not supported");
5946 [ # # ]: 0 : if (data->level > 2)
5947 : 0 : return rte_flow_error_set(error, ENOTSUP,
5948 : : RTE_FLOW_ERROR_TYPE_ACTION,
5949 : : data,
5950 : : "inner MPLS header modification is not supported");
5951 : : break;
5952 : 0 : case RTE_FLOW_FIELD_POINTER:
5953 : : case RTE_FLOW_FIELD_VALUE:
5954 : : default:
5955 : : MLX5_ASSERT(false);
5956 : : }
5957 : : return 0;
5958 : : }
5959 : :
5960 : : static int
5961 : 0 : flow_hw_validate_action_modify_field(struct rte_eth_dev *dev,
5962 : : const struct rte_flow_action *action,
5963 : : const struct rte_flow_action *mask,
5964 : : struct rte_flow_error *error)
5965 : : {
5966 : 0 : const struct rte_flow_action_modify_field *action_conf = action->conf;
5967 : 0 : const struct rte_flow_action_modify_field *mask_conf = mask->conf;
5968 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
5969 : 0 : struct mlx5_hca_attr *attr = &priv->sh->cdev->config.hca_attr;
5970 : : int ret;
5971 : :
5972 [ # # ]: 0 : if (!mask_conf)
5973 : 0 : return rte_flow_error_set(error, EINVAL,
5974 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
5975 : : "modify_field mask conf is missing");
5976 [ # # ]: 0 : if (action_conf->operation != mask_conf->operation)
5977 : 0 : return rte_flow_error_set(error, EINVAL,
5978 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
5979 : : "modify_field operation mask and template are not equal");
5980 [ # # ]: 0 : if (action_conf->dst.field != mask_conf->dst.field)
5981 : 0 : return rte_flow_error_set(error, EINVAL,
5982 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
5983 : : "destination field mask and template are not equal");
5984 : 0 : if (action_conf->dst.field == RTE_FLOW_FIELD_POINTER ||
5985 [ # # ]: 0 : action_conf->dst.field == RTE_FLOW_FIELD_VALUE ||
5986 : : action_conf->dst.field == RTE_FLOW_FIELD_HASH_RESULT)
5987 : 0 : return rte_flow_error_set(error, EINVAL,
5988 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
5989 : : "immediate value, pointer and hash result cannot be used as destination");
5990 : 0 : ret = flow_hw_validate_modify_field_level(&action_conf->dst, false, error);
5991 [ # # ]: 0 : if (ret)
5992 : : return ret;
5993 [ # # # # ]: 0 : if (action_conf->dst.field != RTE_FLOW_FIELD_FLEX_ITEM &&
5994 : : !flow_hw_modify_field_is_geneve_opt(action_conf->dst.field)) {
5995 [ # # ]: 0 : if (action_conf->dst.tag_index &&
5996 : : !flow_modify_field_support_tag_array(action_conf->dst.field))
5997 : 0 : return rte_flow_error_set(error, EINVAL,
5998 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
5999 : : "destination tag index is not supported");
6000 [ # # ]: 0 : if (action_conf->dst.class_id)
6001 : 0 : return rte_flow_error_set(error, EINVAL,
6002 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6003 : : "destination class id is not supported");
6004 : : }
6005 [ # # ]: 0 : if (mask_conf->dst.level != UINT8_MAX)
6006 : 0 : return rte_flow_error_set(error, EINVAL,
6007 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6008 : : "destination encapsulation level must be fully masked");
6009 [ # # ]: 0 : if (mask_conf->dst.offset != UINT32_MAX)
6010 : 0 : return rte_flow_error_set(error, EINVAL,
6011 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6012 : : "destination offset level must be fully masked");
6013 [ # # ]: 0 : if (action_conf->src.field != mask_conf->src.field)
6014 : 0 : return rte_flow_error_set(error, EINVAL,
6015 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6016 : : "destination field mask and template are not equal");
6017 [ # # ]: 0 : if (action_conf->src.field != RTE_FLOW_FIELD_POINTER &&
6018 : : action_conf->src.field != RTE_FLOW_FIELD_VALUE) {
6019 [ # # # # ]: 0 : if (action_conf->src.field != RTE_FLOW_FIELD_FLEX_ITEM &&
6020 : : !flow_hw_modify_field_is_geneve_opt(action_conf->src.field)) {
6021 [ # # ]: 0 : if (action_conf->src.tag_index &&
6022 : : !flow_modify_field_support_tag_array(action_conf->src.field))
6023 : 0 : return rte_flow_error_set(error, EINVAL,
6024 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6025 : : "source tag index is not supported");
6026 [ # # ]: 0 : if (action_conf->src.class_id)
6027 : 0 : return rte_flow_error_set(error, EINVAL,
6028 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6029 : : "source class id is not supported");
6030 : : }
6031 [ # # ]: 0 : if (mask_conf->src.level != UINT8_MAX)
6032 : 0 : return rte_flow_error_set(error, EINVAL,
6033 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6034 : : "source encapsulation level must be fully masked");
6035 [ # # ]: 0 : if (mask_conf->src.offset != UINT32_MAX)
6036 : 0 : return rte_flow_error_set(error, EINVAL,
6037 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6038 : : "source offset level must be fully masked");
6039 : 0 : ret = flow_hw_validate_modify_field_level(&action_conf->src, true, error);
6040 [ # # ]: 0 : if (ret)
6041 : : return ret;
6042 : : }
6043 [ # # ]: 0 : if ((action_conf->dst.field == RTE_FLOW_FIELD_TAG &&
6044 [ # # # # ]: 0 : action_conf->dst.tag_index >= MLX5_FLOW_HW_TAGS_MAX &&
6045 : 0 : action_conf->dst.tag_index != RTE_PMD_MLX5_LINEAR_HASH_TAG_INDEX) ||
6046 [ # # ]: 0 : (action_conf->src.field == RTE_FLOW_FIELD_TAG &&
6047 [ # # # # ]: 0 : action_conf->src.tag_index >= MLX5_FLOW_HW_TAGS_MAX &&
6048 : : action_conf->src.tag_index != RTE_PMD_MLX5_LINEAR_HASH_TAG_INDEX))
6049 : 0 : return rte_flow_error_set(error, EINVAL,
6050 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6051 : : "tag index is out of range");
6052 [ # # # # ]: 0 : if ((action_conf->dst.field == RTE_FLOW_FIELD_TAG &&
6053 [ # # # # ]: 0 : flow_hw_get_reg_id(dev, RTE_FLOW_ITEM_TYPE_TAG, action_conf->dst.tag_index) == REG_NON) ||
6054 [ # # ]: 0 : (action_conf->src.field == RTE_FLOW_FIELD_TAG &&
6055 [ # # ]: 0 : flow_hw_get_reg_id(dev, RTE_FLOW_ITEM_TYPE_TAG, action_conf->src.tag_index) == REG_NON))
6056 : 0 : return rte_flow_error_set(error, EINVAL,
6057 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6058 : : "tag index is out of range");
6059 [ # # ]: 0 : if (mask_conf->width != UINT32_MAX)
6060 : 0 : return rte_flow_error_set(error, EINVAL,
6061 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6062 : : "modify_field width field must be fully masked");
6063 [ # # ]: 0 : if (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_START))
6064 : 0 : return rte_flow_error_set(error, EINVAL,
6065 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6066 : : "modifying arbitrary place in a packet is not supported");
6067 [ # # ]: 0 : if (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_VLAN_TYPE))
6068 : 0 : return rte_flow_error_set(error, EINVAL,
6069 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6070 : : "modifying vlan_type is not supported");
6071 [ # # ]: 0 : if (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_RANDOM))
6072 : 0 : return rte_flow_error_set(error, EINVAL,
6073 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6074 : : "modifying random value is not supported");
6075 : : /**
6076 : : * Geneve VNI modification is supported only when Geneve header is
6077 : : * parsed natively. When GENEVE options are supported, they both Geneve
6078 : : * and options headers are parsed as a flex parser.
6079 : : */
6080 [ # # ]: 0 : if (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_GENEVE_VNI) &&
6081 [ # # ]: 0 : attr->geneve_tlv_opt)
6082 : 0 : return rte_flow_error_set(error, EINVAL,
6083 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6084 : : "modifying Geneve VNI is not supported when GENEVE opt is supported");
6085 [ # # # # ]: 0 : if (priv->tlv_options == NULL &&
6086 [ # # ]: 0 : (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_GENEVE_OPT_TYPE) ||
6087 [ # # ]: 0 : flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_GENEVE_OPT_CLASS) ||
6088 : : flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_GENEVE_OPT_DATA)))
6089 : 0 : return rte_flow_error_set(error, EINVAL,
6090 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6091 : : "modifying Geneve TLV option is supported only after parser configuration");
6092 : : /* Due to HW bug, tunnel MPLS header is read only. */
6093 [ # # ]: 0 : if (action_conf->dst.field == RTE_FLOW_FIELD_MPLS)
6094 : 0 : return rte_flow_error_set(error, EINVAL,
6095 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6096 : : "MPLS cannot be used as destination");
6097 : : /* ADD_FIELD is not supported for all the fields. */
6098 [ # # ]: 0 : if (!flow_hw_modify_field_is_add_dst_valid(action_conf))
6099 : 0 : return rte_flow_error_set(error, EINVAL,
6100 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6101 : : "invalid add_field destination");
6102 : : return 0;
6103 : : }
6104 : :
6105 : : static int
6106 : 0 : flow_hw_validate_action_port_representor(struct rte_eth_dev *dev __rte_unused,
6107 : : const struct rte_flow_actions_template_attr *attr,
6108 : : const struct rte_flow_action *action,
6109 : : const struct rte_flow_action *mask,
6110 : : struct rte_flow_error *error)
6111 : : {
6112 : : const struct rte_flow_action_ethdev *action_conf = NULL;
6113 : : const struct rte_flow_action_ethdev *mask_conf = NULL;
6114 : :
6115 : : /* If transfer is set, port has been validated as proxy port. */
6116 [ # # ]: 0 : if (!attr->transfer)
6117 : 0 : return rte_flow_error_set(error, EINVAL,
6118 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6119 : : "cannot use port_representor actions"
6120 : : " without an E-Switch");
6121 [ # # ]: 0 : if (!action || !mask)
6122 : 0 : return rte_flow_error_set(error, EINVAL,
6123 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6124 : : "actiona and mask configuration must be set");
6125 : 0 : action_conf = action->conf;
6126 : 0 : mask_conf = mask->conf;
6127 [ # # # # : 0 : if (!mask_conf || mask_conf->port_id != MLX5_REPRESENTED_PORT_ESW_MGR ||
# # ]
6128 [ # # ]: 0 : !action_conf || action_conf->port_id != MLX5_REPRESENTED_PORT_ESW_MGR)
6129 : 0 : return rte_flow_error_set(error, EINVAL,
6130 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6131 : : "only eswitch manager port 0xffff is"
6132 : : " supported");
6133 : : return 0;
6134 : : }
6135 : :
6136 : : static int
6137 : 0 : flow_hw_validate_target_port_id(struct rte_eth_dev *dev,
6138 : : uint16_t target_port_id)
6139 : : {
6140 : : struct mlx5_priv *port_priv;
6141 : : struct mlx5_priv *dev_priv;
6142 : :
6143 [ # # ]: 0 : if (target_port_id == MLX5_REPRESENTED_PORT_ESW_MGR)
6144 : : return 0;
6145 : :
6146 : 0 : port_priv = mlx5_port_to_eswitch_info(target_port_id, false);
6147 [ # # ]: 0 : if (!port_priv) {
6148 : 0 : rte_errno = EINVAL;
6149 : 0 : DRV_LOG(ERR, "Port %u Failed to obtain E-Switch info for port %u",
6150 : : dev->data->port_id, target_port_id);
6151 : 0 : return -rte_errno;
6152 : : }
6153 : :
6154 : 0 : dev_priv = mlx5_dev_to_eswitch_info(dev);
6155 [ # # ]: 0 : if (!dev_priv) {
6156 : 0 : rte_errno = EINVAL;
6157 : 0 : DRV_LOG(ERR, "Port %u Failed to obtain E-Switch info for transfer proxy",
6158 : : dev->data->port_id);
6159 : 0 : return -rte_errno;
6160 : : }
6161 : :
6162 [ # # ]: 0 : if (port_priv->domain_id != dev_priv->domain_id) {
6163 : 0 : rte_errno = EINVAL;
6164 : 0 : DRV_LOG(ERR, "Port %u Failed to obtain E-Switch info for transfer proxy",
6165 : : dev->data->port_id);
6166 : 0 : return -rte_errno;
6167 : : }
6168 : :
6169 : : return 0;
6170 : : }
6171 : :
6172 : : static int
6173 : 0 : flow_hw_validate_action_represented_port(struct rte_eth_dev *dev,
6174 : : const struct rte_flow_action *action,
6175 : : const struct rte_flow_action *mask,
6176 : : struct rte_flow_error *error)
6177 : : {
6178 : 0 : const struct rte_flow_action_ethdev *action_conf = action->conf;
6179 : 0 : const struct rte_flow_action_ethdev *mask_conf = mask->conf;
6180 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6181 : :
6182 [ # # ]: 0 : if (!priv->sh->config.dv_esw_en)
6183 : 0 : return rte_flow_error_set(error, EINVAL,
6184 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6185 : : "cannot use represented_port actions"
6186 : : " without an E-Switch");
6187 [ # # # # ]: 0 : if (mask_conf && mask_conf->port_id) {
6188 [ # # ]: 0 : if (!action_conf)
6189 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
6190 : : action, "port index was not provided");
6191 : :
6192 [ # # ]: 0 : if (flow_hw_validate_target_port_id(dev, action_conf->port_id))
6193 : 0 : return rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
6194 : : action, "port index is invalid");
6195 : : }
6196 : : return 0;
6197 : : }
6198 : :
6199 : : /**
6200 : : * Validate AGE action.
6201 : : *
6202 : : * @param[in] dev
6203 : : * Pointer to rte_eth_dev structure.
6204 : : * @param[in] action
6205 : : * Pointer to the indirect action.
6206 : : * @param[in] action_flags
6207 : : * Holds the actions detected until now.
6208 : : * @param[in] fixed_cnt
6209 : : * Indicator if this list has a fixed COUNT action.
6210 : : * @param[out] error
6211 : : * Pointer to error structure.
6212 : : *
6213 : : * @return
6214 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
6215 : : */
6216 : : static int
6217 : 0 : flow_hw_validate_action_age(struct rte_eth_dev *dev,
6218 : : const struct rte_flow_action *action,
6219 : : uint64_t action_flags, bool fixed_cnt,
6220 : : struct rte_flow_error *error)
6221 : : {
6222 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6223 : 0 : struct mlx5_age_info *age_info = GET_PORT_AGE_INFO(priv);
6224 : :
6225 [ # # ]: 0 : if (!priv->sh->cdev->config.devx)
6226 : 0 : return rte_flow_error_set(error, ENOTSUP,
6227 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6228 : : NULL, "AGE action not supported");
6229 [ # # ]: 0 : if (age_info->ages_ipool == NULL)
6230 : 0 : return rte_flow_error_set(error, EINVAL,
6231 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6232 : : "aging pool not initialized");
6233 [ # # ]: 0 : if ((action_flags & MLX5_FLOW_ACTION_AGE) ||
6234 : : (action_flags & MLX5_FLOW_ACTION_INDIRECT_AGE))
6235 : 0 : return rte_flow_error_set(error, EINVAL,
6236 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6237 : : "duplicate AGE actions set");
6238 [ # # ]: 0 : if (fixed_cnt)
6239 : 0 : return rte_flow_error_set(error, EINVAL,
6240 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6241 : : "AGE and fixed COUNT combination is not supported");
6242 : : return 0;
6243 : : }
6244 : :
6245 : : /**
6246 : : * Validate count action.
6247 : : *
6248 : : * @param[in] dev
6249 : : * Pointer to rte_eth_dev structure.
6250 : : * @param[in] action
6251 : : * Pointer to the indirect action.
6252 : : * @param[in] mask
6253 : : * Pointer to the indirect action mask.
6254 : : * @param[in] action_flags
6255 : : * Holds the actions detected until now.
6256 : : * @param[out] error
6257 : : * Pointer to error structure.
6258 : : *
6259 : : * @return
6260 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
6261 : : */
6262 : : static int
6263 : 0 : flow_hw_validate_action_count(struct rte_eth_dev *dev,
6264 : : const struct rte_flow_action *action,
6265 : : const struct rte_flow_action *mask,
6266 : : uint64_t action_flags,
6267 : : struct rte_flow_error *error)
6268 : : {
6269 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6270 : 0 : const struct rte_flow_action_count *count = mask->conf;
6271 : :
6272 [ # # ]: 0 : if (!priv->sh->cdev->config.devx)
6273 : 0 : return rte_flow_error_set(error, ENOTSUP,
6274 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6275 : : "count action not supported");
6276 [ # # ]: 0 : if (!priv->hws_cpool)
6277 : 0 : return rte_flow_error_set(error, EINVAL,
6278 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6279 : : "counters pool not initialized");
6280 [ # # ]: 0 : if ((action_flags & MLX5_FLOW_ACTION_COUNT) ||
6281 : : (action_flags & MLX5_FLOW_ACTION_INDIRECT_COUNT))
6282 : 0 : return rte_flow_error_set(error, EINVAL,
6283 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6284 : : "duplicate count actions set");
6285 [ # # # # : 0 : if (count && count->id && (action_flags & MLX5_FLOW_ACTION_AGE))
# # ]
6286 : 0 : return rte_flow_error_set(error, EINVAL,
6287 : : RTE_FLOW_ERROR_TYPE_ACTION, mask,
6288 : : "AGE and COUNT action shared by mask combination is not supported");
6289 : : return 0;
6290 : : }
6291 : :
6292 : : /**
6293 : : * Validate meter_mark action.
6294 : : *
6295 : : * @param[in] dev
6296 : : * Pointer to rte_eth_dev structure.
6297 : : * @param[in] action
6298 : : * Pointer to the indirect action.
6299 : : * @param[in] indirect
6300 : : * If true, then provided action was passed using an indirect action.
6301 : : * @param[out] error
6302 : : * Pointer to error structure.
6303 : : *
6304 : : * @return
6305 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
6306 : : */
6307 : : static int
6308 : 0 : flow_hw_validate_action_meter_mark(struct rte_eth_dev *dev,
6309 : : const struct rte_flow_action *action,
6310 : : bool indirect,
6311 : : struct rte_flow_error *error)
6312 : : {
6313 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6314 : :
6315 : : RTE_SET_USED(action);
6316 : :
6317 [ # # ]: 0 : if (!priv->sh->cdev->config.devx)
6318 : 0 : return rte_flow_error_set(error, ENOTSUP,
6319 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6320 : : "meter_mark action not supported");
6321 [ # # # # ]: 0 : if (!indirect && priv->shared_host)
6322 : 0 : return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, action,
6323 : : "meter_mark action can only be used on host port");
6324 [ # # ]: 0 : if (!priv->hws_mpool)
6325 : 0 : return rte_flow_error_set(error, EINVAL,
6326 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6327 : : "meter_mark pool not initialized");
6328 : : return 0;
6329 : : }
6330 : :
6331 : : /**
6332 : : * Validate indirect action.
6333 : : *
6334 : : * @param[in] dev
6335 : : * Pointer to rte_eth_dev structure.
6336 : : * @param[in] action
6337 : : * Pointer to the indirect action.
6338 : : * @param[in] mask
6339 : : * Pointer to the indirect action mask.
6340 : : * @param[in, out] action_flags
6341 : : * Holds the actions detected until now.
6342 : : * @param[in, out] fixed_cnt
6343 : : * Pointer to indicator if this list has a fixed COUNT action.
6344 : : * @param[out] error
6345 : : * Pointer to error structure.
6346 : : *
6347 : : * @return
6348 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
6349 : : */
6350 : : static int
6351 : 0 : flow_hw_validate_action_indirect(struct rte_eth_dev *dev,
6352 : : const struct rte_flow_action *action,
6353 : : const struct rte_flow_action *mask,
6354 : : uint64_t *action_flags, bool *fixed_cnt,
6355 : : struct rte_flow_error *error)
6356 : : {
6357 : : uint32_t type;
6358 : : int ret;
6359 : :
6360 [ # # ]: 0 : if (!mask)
6361 : 0 : return rte_flow_error_set(error, EINVAL,
6362 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6363 : : "Unable to determine indirect action type without a mask specified");
6364 : 0 : type = mask->type;
6365 [ # # # # : 0 : switch (type) {
# # # ]
6366 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
6367 : 0 : ret = flow_hw_validate_action_meter_mark(dev, mask, true, error);
6368 [ # # ]: 0 : if (ret < 0)
6369 : : return ret;
6370 : 0 : *action_flags |= MLX5_FLOW_ACTION_METER;
6371 : 0 : break;
6372 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
6373 : : /* TODO: Validation logic (same as flow_hw_actions_validate) */
6374 : 0 : *action_flags |= MLX5_FLOW_ACTION_RSS;
6375 : 0 : break;
6376 : 0 : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
6377 : : /* TODO: Validation logic (same as flow_hw_actions_validate) */
6378 : 0 : *action_flags |= MLX5_FLOW_ACTION_CT;
6379 : 0 : break;
6380 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
6381 [ # # # # ]: 0 : if (action->conf && mask->conf) {
6382 [ # # ]: 0 : if ((*action_flags & MLX5_FLOW_ACTION_AGE) ||
6383 : : (*action_flags & MLX5_FLOW_ACTION_INDIRECT_AGE))
6384 : : /*
6385 : : * AGE cannot use indirect counter which is
6386 : : * shared with enother flow rules.
6387 : : */
6388 : 0 : return rte_flow_error_set(error, EINVAL,
6389 : : RTE_FLOW_ERROR_TYPE_ACTION,
6390 : : NULL,
6391 : : "AGE and fixed COUNT combination is not supported");
6392 : 0 : *fixed_cnt = true;
6393 : : }
6394 : 0 : ret = flow_hw_validate_action_count(dev, action, mask,
6395 : : *action_flags, error);
6396 [ # # ]: 0 : if (ret < 0)
6397 : : return ret;
6398 : 0 : *action_flags |= MLX5_FLOW_ACTION_INDIRECT_COUNT;
6399 : 0 : break;
6400 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
6401 : 0 : ret = flow_hw_validate_action_age(dev, action, *action_flags,
6402 : 0 : *fixed_cnt, error);
6403 [ # # ]: 0 : if (ret < 0)
6404 : : return ret;
6405 : 0 : *action_flags |= MLX5_FLOW_ACTION_INDIRECT_AGE;
6406 : 0 : break;
6407 : 0 : case RTE_FLOW_ACTION_TYPE_QUOTA:
6408 : : /* TODO: add proper quota verification */
6409 : 0 : *action_flags |= MLX5_FLOW_ACTION_QUOTA;
6410 : 0 : break;
6411 : 0 : default:
6412 : 0 : DRV_LOG(WARNING, "Unsupported shared action type: %d", type);
6413 : 0 : return rte_flow_error_set(error, ENOTSUP,
6414 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, mask,
6415 : : "Unsupported indirect action type");
6416 : : }
6417 : : return 0;
6418 : : }
6419 : :
6420 : : /**
6421 : : * Validate ipv6_ext_push action.
6422 : : *
6423 : : * @param[in] dev
6424 : : * Pointer to rte_eth_dev structure.
6425 : : * @param[in] action
6426 : : * Pointer to the indirect action.
6427 : : * @param[out] error
6428 : : * Pointer to error structure.
6429 : : *
6430 : : * @return
6431 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
6432 : : */
6433 : : static int
6434 : 0 : flow_hw_validate_action_ipv6_ext_push(struct rte_eth_dev *dev __rte_unused,
6435 : : const struct rte_flow_action *action,
6436 : : struct rte_flow_error *error)
6437 : : {
6438 : 0 : const struct rte_flow_action_ipv6_ext_push *raw_push_data = action->conf;
6439 : :
6440 [ # # # # : 0 : if (!raw_push_data || !raw_push_data->size || !raw_push_data->data)
# # ]
6441 : 0 : return rte_flow_error_set(error, EINVAL,
6442 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6443 : : "invalid ipv6_ext_push data");
6444 [ # # # # ]: 0 : if (raw_push_data->type != IPPROTO_ROUTING ||
6445 : : raw_push_data->size > MLX5_PUSH_MAX_LEN)
6446 : 0 : return rte_flow_error_set(error, EINVAL,
6447 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6448 : : "Unsupported ipv6_ext_push type or length");
6449 : : return 0;
6450 : : }
6451 : :
6452 : : /**
6453 : : * Process `... / raw_decap / raw_encap / ...` actions sequence.
6454 : : * The PMD handles the sequence as a single encap or decap reformat action,
6455 : : * depending on the raw_encap configuration.
6456 : : *
6457 : : * The function assumes that the raw_decap / raw_encap location
6458 : : * in actions template list complies with relative HWS actions order:
6459 : : * for the required reformat configuration:
6460 : : * ENCAP configuration must appear before [JUMP|DROP|PORT]
6461 : : * DECAP configuration must appear at the template head.
6462 : : */
6463 : : static uint64_t
6464 : : mlx5_decap_encap_reformat_type(const struct rte_flow_action *actions,
6465 : : uint32_t encap_ind, uint64_t flags)
6466 : : {
6467 : 0 : const struct rte_flow_action_raw_encap *encap = actions[encap_ind].conf;
6468 : :
6469 [ # # ]: 0 : if ((flags & MLX5_FLOW_ACTION_DECAP) == 0)
6470 : : return MLX5_FLOW_ACTION_ENCAP;
6471 [ # # ]: 0 : if (actions[encap_ind - 1].type != RTE_FLOW_ACTION_TYPE_RAW_DECAP)
6472 : : return MLX5_FLOW_ACTION_ENCAP;
6473 : 0 : return encap->size >= MLX5_ENCAPSULATION_DECISION_SIZE ?
6474 [ # # ]: 0 : MLX5_FLOW_ACTION_ENCAP : MLX5_FLOW_ACTION_DECAP;
6475 : : }
6476 : :
6477 : : enum mlx5_hw_indirect_list_relative_position {
6478 : : MLX5_INDIRECT_LIST_POSITION_UNKNOWN = -1,
6479 : : MLX5_INDIRECT_LIST_POSITION_BEFORE_MH = 0,
6480 : : MLX5_INDIRECT_LIST_POSITION_AFTER_MH,
6481 : : };
6482 : :
6483 : : static enum mlx5_hw_indirect_list_relative_position
6484 : 0 : mlx5_hw_indirect_list_mh_position(const struct rte_flow_action *action)
6485 : : {
6486 : 0 : const struct rte_flow_action_indirect_list *conf = action->conf;
6487 [ # # # # ]: 0 : enum mlx5_indirect_list_type list_type = mlx5_get_indirect_list_type(conf->handle);
6488 : : enum mlx5_hw_indirect_list_relative_position pos = MLX5_INDIRECT_LIST_POSITION_UNKNOWN;
6489 : : const union {
6490 : : struct mlx5_indlst_legacy *legacy;
6491 : : struct mlx5_hw_encap_decap_action *reformat;
6492 : : struct rte_flow_action_list_handle *handle;
6493 : : } h = { .handle = conf->handle};
6494 : :
6495 [ # # # # ]: 0 : switch (list_type) {
6496 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY:
6497 [ # # # ]: 0 : switch (h.legacy->legacy_type) {
6498 : : case RTE_FLOW_ACTION_TYPE_AGE:
6499 : : case RTE_FLOW_ACTION_TYPE_COUNT:
6500 : : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
6501 : : case RTE_FLOW_ACTION_TYPE_METER_MARK:
6502 : : case RTE_FLOW_ACTION_TYPE_QUOTA:
6503 : : pos = MLX5_INDIRECT_LIST_POSITION_BEFORE_MH;
6504 : : break;
6505 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
6506 : : pos = MLX5_INDIRECT_LIST_POSITION_AFTER_MH;
6507 : 0 : break;
6508 : 0 : default:
6509 : : pos = MLX5_INDIRECT_LIST_POSITION_UNKNOWN;
6510 : 0 : break;
6511 : : }
6512 : : break;
6513 : : case MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR:
6514 : : pos = MLX5_INDIRECT_LIST_POSITION_AFTER_MH;
6515 : : break;
6516 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT:
6517 [ # # # ]: 0 : switch (h.reformat->action_type) {
6518 : : case MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2:
6519 : : case MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2:
6520 : : pos = MLX5_INDIRECT_LIST_POSITION_BEFORE_MH;
6521 : : break;
6522 : 0 : case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2:
6523 : : case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3:
6524 : : pos = MLX5_INDIRECT_LIST_POSITION_AFTER_MH;
6525 : 0 : break;
6526 : 0 : default:
6527 : : pos = MLX5_INDIRECT_LIST_POSITION_UNKNOWN;
6528 : 0 : break;
6529 : : }
6530 : : break;
6531 : 0 : default:
6532 : : pos = MLX5_INDIRECT_LIST_POSITION_UNKNOWN;
6533 : 0 : break;
6534 : : }
6535 : 0 : return pos;
6536 : : }
6537 : :
6538 : : #define MLX5_HW_EXPAND_MH_FAILED 0xffff
6539 : :
6540 : : static inline uint16_t
6541 : 0 : flow_hw_template_expand_modify_field(struct rte_flow_action actions[],
6542 : : struct rte_flow_action masks[],
6543 : : const struct rte_flow_action *mf_actions,
6544 : : const struct rte_flow_action *mf_masks,
6545 : : uint64_t flags, uint32_t act_num,
6546 : : uint32_t mf_num)
6547 : : {
6548 : : uint32_t i, tail;
6549 : :
6550 : : MLX5_ASSERT(actions && masks);
6551 : : MLX5_ASSERT(mf_num > 0);
6552 [ # # ]: 0 : if (flags & MLX5_FLOW_ACTION_MODIFY_FIELD) {
6553 : : /*
6554 : : * Application action template already has Modify Field.
6555 : : * It's location will be used in DR.
6556 : : * Expanded MF action can be added before the END.
6557 : : */
6558 : 0 : i = act_num - 1;
6559 : 0 : goto insert;
6560 : : }
6561 : : /**
6562 : : * Locate the first action positioned BEFORE the new MF.
6563 : : *
6564 : : * Search for a place to insert modify header
6565 : : * from the END action backwards:
6566 : : * 1. END is always present in actions array
6567 : : * 2. END location is always at action[act_num - 1]
6568 : : * 3. END always positioned AFTER modify field location
6569 : : *
6570 : : * Relative actions order is the same for RX, TX and FDB.
6571 : : *
6572 : : * Current actions order (draft-3)
6573 : : * @see action_order_arr[]
6574 : : */
6575 [ # # ]: 0 : for (i = act_num - 2; (int)i >= 0; i--) {
6576 : : enum mlx5_hw_indirect_list_relative_position pos;
6577 : 0 : enum rte_flow_action_type type = actions[i].type;
6578 : : uint64_t reformat_type;
6579 : :
6580 [ # # ]: 0 : if (type == RTE_FLOW_ACTION_TYPE_INDIRECT)
6581 : 0 : type = masks[i].type;
6582 [ # # # # ]: 0 : switch (type) {
6583 : : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
6584 : : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
6585 : : case RTE_FLOW_ACTION_TYPE_DROP:
6586 : : case RTE_FLOW_ACTION_TYPE_SEND_TO_KERNEL:
6587 : : case RTE_FLOW_ACTION_TYPE_JUMP:
6588 : : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
6589 : : case RTE_FLOW_ACTION_TYPE_QUEUE:
6590 : : case RTE_FLOW_ACTION_TYPE_RSS:
6591 : : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
6592 : : case RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:
6593 : : case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
6594 : : case RTE_FLOW_ACTION_TYPE_VOID:
6595 : : case RTE_FLOW_ACTION_TYPE_END:
6596 : : break;
6597 : : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
6598 : : reformat_type =
6599 : : mlx5_decap_encap_reformat_type(actions, i,
6600 : : flags);
6601 : : if (reformat_type == MLX5_FLOW_ACTION_DECAP) {
6602 : 0 : i++;
6603 : 0 : goto insert;
6604 : : }
6605 [ # # ]: 0 : if (actions[i - 1].type == RTE_FLOW_ACTION_TYPE_RAW_DECAP)
6606 : : i--;
6607 : : break;
6608 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT_LIST:
6609 : 0 : pos = mlx5_hw_indirect_list_mh_position(&actions[i]);
6610 [ # # ]: 0 : if (pos == MLX5_INDIRECT_LIST_POSITION_UNKNOWN)
6611 : : return MLX5_HW_EXPAND_MH_FAILED;
6612 [ # # ]: 0 : if (pos == MLX5_INDIRECT_LIST_POSITION_BEFORE_MH)
6613 : 0 : goto insert;
6614 : : break;
6615 : 0 : default:
6616 : 0 : i++; /* new MF inserted AFTER actions[i] */
6617 : 0 : goto insert;
6618 : : }
6619 : : }
6620 : : i = 0;
6621 : 0 : insert:
6622 : 0 : tail = act_num - i; /* num action to move */
6623 : 0 : memmove(actions + i + mf_num, actions + i, sizeof(actions[0]) * tail);
6624 : 0 : memcpy(actions + i, mf_actions, sizeof(actions[0]) * mf_num);
6625 : 0 : memmove(masks + i + mf_num, masks + i, sizeof(masks[0]) * tail);
6626 : : memcpy(masks + i, mf_masks, sizeof(masks[0]) * mf_num);
6627 : 0 : return i;
6628 : : }
6629 : :
6630 : : static int
6631 : 0 : flow_hw_validate_action_push_vlan(struct rte_eth_dev *dev,
6632 : : const
6633 : : struct rte_flow_actions_template_attr *attr,
6634 : : const struct rte_flow_action *action,
6635 : : const struct rte_flow_action *mask,
6636 : : struct rte_flow_error *error)
6637 : : {
6638 : : #define X_FIELD(ptr, t, f) (((ptr)->conf) && ((t *)((ptr)->conf))->f)
6639 : :
6640 : 0 : const bool masked_push =
6641 [ # # # # ]: 0 : X_FIELD(mask + MLX5_HW_VLAN_PUSH_TYPE_IDX,
6642 : : const struct rte_flow_action_of_push_vlan, ethertype);
6643 : : bool masked_param;
6644 : :
6645 : : /*
6646 : : * Mandatory actions order:
6647 : : * OF_PUSH_VLAN / OF_SET_VLAN_VID [ / OF_SET_VLAN_PCP ]
6648 : : */
6649 : : RTE_SET_USED(dev);
6650 : : RTE_SET_USED(attr);
6651 : : /* Check that mark matches OF_PUSH_VLAN */
6652 [ # # ]: 0 : if (mask[MLX5_HW_VLAN_PUSH_TYPE_IDX].type !=
6653 : : RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN)
6654 : 0 : return rte_flow_error_set(error, EINVAL,
6655 : : RTE_FLOW_ERROR_TYPE_ACTION,
6656 : : action, "OF_PUSH_VLAN: mask does not match");
6657 : : /* Check that the second template and mask items are SET_VLAN_VID */
6658 [ # # ]: 0 : if (action[MLX5_HW_VLAN_PUSH_VID_IDX].type !=
6659 : 0 : RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID ||
6660 [ # # ]: 0 : mask[MLX5_HW_VLAN_PUSH_VID_IDX].type !=
6661 : : RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)
6662 : 0 : return rte_flow_error_set(error, EINVAL,
6663 : : RTE_FLOW_ERROR_TYPE_ACTION,
6664 : : action, "OF_PUSH_VLAN: invalid actions order");
6665 [ # # # # ]: 0 : masked_param = X_FIELD(mask + MLX5_HW_VLAN_PUSH_VID_IDX,
6666 : : const struct rte_flow_action_of_set_vlan_vid,
6667 : : vlan_vid);
6668 : : /*
6669 : : * PMD requires OF_SET_VLAN_VID mask to must match OF_PUSH_VLAN
6670 : : */
6671 [ # # ]: 0 : if (masked_push ^ masked_param)
6672 : 0 : return rte_flow_error_set(error, EINVAL,
6673 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6674 : : "OF_SET_VLAN_VID: mask does not match OF_PUSH_VLAN");
6675 [ # # ]: 0 : if (is_of_vlan_pcp_present(action)) {
6676 [ # # ]: 0 : if (mask[MLX5_HW_VLAN_PUSH_PCP_IDX].type !=
6677 : : RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)
6678 : 0 : return rte_flow_error_set(error, EINVAL,
6679 : : RTE_FLOW_ERROR_TYPE_ACTION,
6680 : : action, "OF_SET_VLAN_PCP: missing mask configuration");
6681 [ # # # # ]: 0 : masked_param = X_FIELD(mask + MLX5_HW_VLAN_PUSH_PCP_IDX,
6682 : : const struct
6683 : : rte_flow_action_of_set_vlan_pcp,
6684 : : vlan_pcp);
6685 : : /*
6686 : : * PMD requires OF_SET_VLAN_PCP mask to must match OF_PUSH_VLAN
6687 : : */
6688 [ # # ]: 0 : if (masked_push ^ masked_param)
6689 : 0 : return rte_flow_error_set(error, EINVAL,
6690 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6691 : : "OF_SET_VLAN_PCP: mask does not match OF_PUSH_VLAN");
6692 : : }
6693 : : return 0;
6694 : : #undef X_FIELD
6695 : : }
6696 : :
6697 : : static int
6698 : 0 : flow_hw_validate_action_default_miss(struct rte_eth_dev *dev,
6699 : : const struct rte_flow_actions_template_attr *attr,
6700 : : uint64_t action_flags,
6701 : : struct rte_flow_error *error)
6702 : : {
6703 : : /*
6704 : : * The private DEFAULT_MISS action is used internally for LACP in control
6705 : : * flows. So this validation can be ignored. It can be kept right now since
6706 : : * the validation will be done only once.
6707 : : */
6708 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6709 : :
6710 [ # # ]: 0 : if (!attr->ingress || attr->egress || attr->transfer)
6711 : 0 : return rte_flow_error_set(error, EINVAL,
6712 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6713 : : "DEFAULT MISS is only supported in ingress.");
6714 [ # # ]: 0 : if (!priv->hw_def_miss)
6715 : 0 : return rte_flow_error_set(error, EINVAL,
6716 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6717 : : "DEFAULT MISS action does not exist.");
6718 [ # # ]: 0 : if (action_flags & MLX5_FLOW_FATE_ACTIONS)
6719 : 0 : return rte_flow_error_set(error, EINVAL,
6720 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6721 : : "DEFAULT MISS should be the only termination.");
6722 : : return 0;
6723 : : }
6724 : :
6725 : : static int
6726 : 0 : flow_hw_validate_action_nat64(struct rte_eth_dev *dev,
6727 : : const struct rte_flow_actions_template_attr *attr,
6728 : : const struct rte_flow_action *action,
6729 : : const struct rte_flow_action *mask,
6730 : : uint64_t action_flags,
6731 : : struct rte_flow_error *error)
6732 : : {
6733 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6734 : : const struct rte_flow_action_nat64 *nat64_c;
6735 : : enum rte_flow_nat64_type cov_type;
6736 : :
6737 : : RTE_SET_USED(action_flags);
6738 [ # # # # ]: 0 : if (mask->conf && ((const struct rte_flow_action_nat64 *)mask->conf)->type) {
6739 : 0 : nat64_c = (const struct rte_flow_action_nat64 *)action->conf;
6740 : 0 : cov_type = nat64_c->type;
6741 [ # # # # ]: 0 : if ((attr->ingress && !priv->action_nat64[MLX5DR_TABLE_TYPE_NIC_RX][cov_type]) ||
6742 [ # # # # ]: 0 : (attr->egress && !priv->action_nat64[MLX5DR_TABLE_TYPE_NIC_TX][cov_type]))
6743 : 0 : goto err_out;
6744 [ # # ]: 0 : if (attr->transfer) {
6745 [ # # ]: 0 : if (!is_unified_fdb(priv)) {
6746 [ # # ]: 0 : if (!priv->action_nat64[MLX5DR_TABLE_TYPE_FDB][cov_type])
6747 : 0 : goto err_out;
6748 : : } else {
6749 [ # # ]: 0 : if (!priv->action_nat64[MLX5DR_TABLE_TYPE_FDB_RX][cov_type] ||
6750 [ # # ]: 0 : !priv->action_nat64[MLX5DR_TABLE_TYPE_FDB_TX][cov_type] ||
6751 [ # # ]: 0 : !priv->action_nat64[MLX5DR_TABLE_TYPE_FDB_UNIFIED][cov_type])
6752 : 0 : goto err_out;
6753 : : }
6754 : : }
6755 : : } else {
6756 : : /*
6757 : : * Usually, the actions will be used on both directions. For non-masked actions,
6758 : : * both directions' actions will be checked.
6759 : : */
6760 [ # # ]: 0 : if (attr->ingress)
6761 [ # # ]: 0 : if (!priv->action_nat64[MLX5DR_TABLE_TYPE_NIC_RX][RTE_FLOW_NAT64_6TO4] ||
6762 [ # # ]: 0 : !priv->action_nat64[MLX5DR_TABLE_TYPE_NIC_RX][RTE_FLOW_NAT64_4TO6])
6763 : 0 : goto err_out;
6764 [ # # ]: 0 : if (attr->egress)
6765 [ # # ]: 0 : if (!priv->action_nat64[MLX5DR_TABLE_TYPE_NIC_TX][RTE_FLOW_NAT64_6TO4] ||
6766 [ # # ]: 0 : !priv->action_nat64[MLX5DR_TABLE_TYPE_NIC_TX][RTE_FLOW_NAT64_4TO6])
6767 : 0 : goto err_out;
6768 [ # # ]: 0 : if (attr->transfer) {
6769 [ # # ]: 0 : if (!is_unified_fdb(priv)) {
6770 : 0 : if (!priv->action_nat64[MLX5DR_TABLE_TYPE_FDB]
6771 [ # # ]: 0 : [RTE_FLOW_NAT64_6TO4] ||
6772 : : !priv->action_nat64[MLX5DR_TABLE_TYPE_FDB]
6773 [ # # ]: 0 : [RTE_FLOW_NAT64_4TO6])
6774 : 0 : goto err_out;
6775 : : } else {
6776 : 0 : if (!priv->action_nat64[MLX5DR_TABLE_TYPE_FDB_RX]
6777 [ # # ]: 0 : [RTE_FLOW_NAT64_6TO4] ||
6778 : : !priv->action_nat64[MLX5DR_TABLE_TYPE_FDB_RX]
6779 [ # # ]: 0 : [RTE_FLOW_NAT64_4TO6] ||
6780 : : !priv->action_nat64[MLX5DR_TABLE_TYPE_FDB_TX]
6781 [ # # ]: 0 : [RTE_FLOW_NAT64_6TO4] ||
6782 : : !priv->action_nat64[MLX5DR_TABLE_TYPE_FDB_TX]
6783 [ # # ]: 0 : [RTE_FLOW_NAT64_4TO6] ||
6784 : : !priv->action_nat64[MLX5DR_TABLE_TYPE_FDB_UNIFIED]
6785 [ # # ]: 0 : [RTE_FLOW_NAT64_6TO4] ||
6786 : : !priv->action_nat64[MLX5DR_TABLE_TYPE_FDB_UNIFIED]
6787 [ # # ]: 0 : [RTE_FLOW_NAT64_4TO6])
6788 : 0 : goto err_out;
6789 : : }
6790 : : }
6791 : : }
6792 : : return 0;
6793 : 0 : err_out:
6794 : 0 : return rte_flow_error_set(error, EOPNOTSUPP, RTE_FLOW_ERROR_TYPE_ACTION,
6795 : : NULL, "NAT64 action is not supported.");
6796 : : }
6797 : :
6798 : : static int
6799 : 0 : flow_hw_validate_action_jump(struct rte_eth_dev *dev,
6800 : : const struct rte_flow_actions_template_attr *attr,
6801 : : const struct rte_flow_action *action,
6802 : : const struct rte_flow_action *mask,
6803 : : struct rte_flow_error *error)
6804 : : {
6805 : 0 : const struct rte_flow_action_jump *m = mask->conf;
6806 : 0 : const struct rte_flow_action_jump *v = action->conf;
6807 : 0 : struct mlx5_flow_template_table_cfg cfg = {
6808 : : .external = true,
6809 : : .attr = {
6810 : : .flow_attr = {
6811 : 0 : .ingress = attr->ingress,
6812 : 0 : .egress = attr->egress,
6813 : 0 : .transfer = attr->transfer,
6814 : : },
6815 : : },
6816 : : };
6817 : 0 : uint32_t t_group = 0;
6818 : :
6819 [ # # # # ]: 0 : if (!m || !m->group)
6820 : : return 0;
6821 [ # # ]: 0 : if (!v)
6822 : 0 : return rte_flow_error_set(error, EINVAL,
6823 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6824 : : "Invalid jump action configuration");
6825 [ # # ]: 0 : if (flow_hw_translate_group(dev, &cfg, v->group, &t_group, error))
6826 : 0 : return -rte_errno;
6827 [ # # ]: 0 : if (t_group == 0)
6828 : 0 : return rte_flow_error_set(error, EINVAL,
6829 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6830 : : "Unsupported action - jump to root table");
6831 : : return 0;
6832 : : }
6833 : :
6834 : : static int
6835 : 0 : mlx5_flow_validate_action_jump_to_table_index(const struct rte_flow_action *action,
6836 : : const struct rte_flow_action *mask,
6837 : : struct rte_flow_error *error)
6838 : : {
6839 : 0 : const struct rte_flow_action_jump_to_table_index *m = mask->conf;
6840 : 0 : const struct rte_flow_action_jump_to_table_index *v = action->conf;
6841 : : struct mlx5dr_action *jump_action;
6842 : : uint32_t t_group = 0;
6843 : :
6844 [ # # # # ]: 0 : if (!m || !m->table)
6845 : : return 0;
6846 [ # # ]: 0 : if (!v)
6847 : 0 : return rte_flow_error_set(error, EINVAL,
6848 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6849 : : "Invalid jump to matcher action configuration");
6850 : 0 : t_group = v->table->grp->group_id;
6851 [ # # ]: 0 : if (t_group == 0)
6852 : 0 : return rte_flow_error_set(error, EINVAL,
6853 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6854 : : "Unsupported action - jump to root table");
6855 [ # # ]: 0 : if (likely(!rte_flow_template_table_resizable(0, &v->table->cfg.attr))) {
6856 : 0 : jump_action = v->table->matcher_info[0].jump;
6857 : : } else {
6858 : : uint32_t selector;
6859 : 0 : rte_rwlock_read_lock(&v->table->matcher_replace_rwlk);
6860 : 0 : selector = v->table->matcher_selector;
6861 : 0 : jump_action = v->table->matcher_info[selector].jump;
6862 : : rte_rwlock_read_unlock(&v->table->matcher_replace_rwlk);
6863 : : }
6864 [ # # ]: 0 : if (jump_action == NULL)
6865 : 0 : return rte_flow_error_set(error, EINVAL,
6866 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6867 : : "Unsupported action - table is not an rule array");
6868 : : return 0;
6869 : : }
6870 : :
6871 : : static int
6872 : 0 : mlx5_hw_validate_action_mark(struct rte_eth_dev *dev,
6873 : : const struct rte_flow_action *template_action,
6874 : : const struct rte_flow_action *template_mask,
6875 : : uint64_t action_flags,
6876 : : const struct rte_flow_actions_template_attr *template_attr,
6877 : : struct rte_flow_error *error)
6878 : : {
6879 : 0 : const struct rte_flow_action_mark *mark_mask = template_mask->conf;
6880 : : const struct rte_flow_action *action =
6881 [ # # # # ]: 0 : mark_mask && mark_mask->id ? template_action :
6882 : 0 : &(const struct rte_flow_action) {
6883 : : .type = RTE_FLOW_ACTION_TYPE_MARK,
6884 : 0 : .conf = &(const struct rte_flow_action_mark) {
6885 : : .id = MLX5_FLOW_MARK_MAX - 1
6886 : : }
6887 : : };
6888 : 0 : const struct rte_flow_attr attr = {
6889 : 0 : .ingress = template_attr->ingress,
6890 : 0 : .egress = template_attr->egress,
6891 : 0 : .transfer = template_attr->transfer
6892 : : };
6893 : :
6894 : 0 : return mlx5_flow_validate_action_mark(dev, action, action_flags,
6895 : : &attr, error);
6896 : : }
6897 : :
6898 : : static int
6899 : 0 : mlx5_hw_validate_action_queue(struct rte_eth_dev *dev,
6900 : : const struct rte_flow_action *template_action,
6901 : : const struct rte_flow_action *template_mask,
6902 : : const struct rte_flow_actions_template_attr *template_attr,
6903 : : uint64_t action_flags,
6904 : : struct rte_flow_error *error)
6905 : : {
6906 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6907 : 0 : const struct rte_flow_action_queue *queue_mask = template_mask->conf;
6908 : 0 : const struct rte_flow_attr attr = {
6909 : 0 : .ingress = template_attr->ingress,
6910 : 0 : .egress = template_attr->egress,
6911 : 0 : .transfer = template_attr->transfer
6912 : : };
6913 [ # # # # ]: 0 : bool masked = queue_mask != NULL && queue_mask->index;
6914 : :
6915 [ # # # # : 0 : if (template_attr->egress || (template_attr->transfer && !priv->jump_fdb_rx_en))
# # ]
6916 : 0 : return rte_flow_error_set(error, EINVAL,
6917 : : RTE_FLOW_ERROR_TYPE_ATTR, NULL,
6918 : : "QUEUE action supported for ingress only");
6919 [ # # ]: 0 : if (masked)
6920 : 0 : return mlx5_flow_validate_action_queue(template_action, action_flags, dev,
6921 : : &attr, error);
6922 : : else
6923 : : return 0;
6924 : : }
6925 : :
6926 : : static int
6927 : 0 : mlx5_hw_validate_action_rss(struct rte_eth_dev *dev,
6928 : : const struct rte_flow_action *template_action,
6929 : : const struct rte_flow_action *template_mask,
6930 : : const struct rte_flow_actions_template_attr *template_attr,
6931 : : __rte_unused uint64_t action_flags,
6932 : : struct rte_flow_error *error)
6933 : : {
6934 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6935 : 0 : const struct rte_flow_action_rss *mask = template_mask->conf;
6936 : :
6937 [ # # # # : 0 : if (template_attr->egress || (template_attr->transfer && !priv->jump_fdb_rx_en))
# # ]
6938 : 0 : return rte_flow_error_set(error, EINVAL,
6939 : : RTE_FLOW_ERROR_TYPE_ATTR, NULL,
6940 : : "RSS action supported for ingress only");
6941 [ # # ]: 0 : if (mask != NULL)
6942 : 0 : return mlx5_validate_action_rss(dev, template_action, error);
6943 : : else
6944 : : return 0;
6945 : : }
6946 : :
6947 : : static int
6948 : 0 : mlx5_hw_validate_action_l2_encap(struct rte_eth_dev *dev,
6949 : : const struct rte_flow_action *template_action,
6950 : : const struct rte_flow_action *template_mask,
6951 : : const struct rte_flow_actions_template_attr *template_attr,
6952 : : uint64_t action_flags,
6953 : : struct rte_flow_error *error)
6954 : : {
6955 : 0 : const struct rte_flow_action_vxlan_encap default_action_conf = {
6956 : : .definition = (struct rte_flow_item *)
6957 : 0 : (struct rte_flow_item [1]) {
6958 : : [0] = { .type = RTE_FLOW_ITEM_TYPE_END }
6959 : : }
6960 : : };
6961 : 0 : const struct rte_flow_action *action = template_mask->conf ?
6962 [ # # ]: 0 : template_action : &(const struct rte_flow_action) {
6963 : 0 : .type = template_mask->type,
6964 : : .conf = &default_action_conf
6965 : : };
6966 : 0 : const struct rte_flow_attr attr = {
6967 : 0 : .ingress = template_attr->ingress,
6968 : 0 : .egress = template_attr->egress,
6969 : 0 : .transfer = template_attr->transfer
6970 : : };
6971 : :
6972 : 0 : return mlx5_flow_dv_validate_action_l2_encap(dev, action_flags, action,
6973 : : &attr, error);
6974 : : }
6975 : :
6976 : : static int
6977 : 0 : mlx5_hw_validate_action_l2_decap(struct rte_eth_dev *dev,
6978 : : const struct rte_flow_action *template_action,
6979 : : const struct rte_flow_action *template_mask,
6980 : : const struct rte_flow_actions_template_attr *template_attr,
6981 : : uint64_t action_flags,
6982 : : struct rte_flow_error *error)
6983 : : {
6984 : 0 : const struct rte_flow_action_vxlan_encap default_action_conf = {
6985 : : .definition = (struct rte_flow_item *)
6986 : 0 : (struct rte_flow_item [1]) {
6987 : : [0] = { .type = RTE_FLOW_ITEM_TYPE_END }
6988 : : }
6989 : : };
6990 : 0 : const struct rte_flow_action *action = template_mask->conf ?
6991 [ # # ]: 0 : template_action : &(const struct rte_flow_action) {
6992 : 0 : .type = template_mask->type,
6993 : : .conf = &default_action_conf
6994 : : };
6995 : 0 : const struct rte_flow_attr attr = {
6996 : 0 : .ingress = template_attr->ingress,
6997 : 0 : .egress = template_attr->egress,
6998 : 0 : .transfer = template_attr->transfer
6999 : : };
7000 : : uint64_t item_flags =
7001 : 0 : action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
7002 [ # # ]: 0 : MLX5_FLOW_LAYER_VXLAN : 0;
7003 : :
7004 : 0 : return mlx5_flow_dv_validate_action_decap(dev, action_flags, action,
7005 : : item_flags, &attr, error);
7006 : : }
7007 : :
7008 : : static int
7009 : : mlx5_hw_validate_action_conntrack(struct rte_eth_dev *dev,
7010 : : const struct rte_flow_action *template_action,
7011 : : const struct rte_flow_action *template_mask,
7012 : : const struct rte_flow_actions_template_attr *template_attr,
7013 : : uint64_t action_flags,
7014 : : struct rte_flow_error *error)
7015 : : {
7016 : : RTE_SET_USED(template_action);
7017 : : RTE_SET_USED(template_mask);
7018 : : RTE_SET_USED(template_attr);
7019 : 0 : return mlx5_flow_dv_validate_action_aso_ct(dev, action_flags,
7020 : : MLX5_FLOW_LAYER_OUTER_L4_TCP,
7021 : : false, error);
7022 : : }
7023 : :
7024 : : static int
7025 : 0 : flow_hw_validate_action_raw_encap(const struct rte_flow_action *action,
7026 : : const struct rte_flow_action *mask,
7027 : : struct rte_flow_error *error)
7028 : : {
7029 : 0 : const struct rte_flow_action_raw_encap *mask_conf = mask->conf;
7030 : 0 : const struct rte_flow_action_raw_encap *action_conf = action->conf;
7031 : :
7032 [ # # # # ]: 0 : if (!mask_conf || !mask_conf->size)
7033 : 0 : return rte_flow_error_set(error, EINVAL,
7034 : : RTE_FLOW_ERROR_TYPE_ACTION, mask,
7035 : : "raw_encap: size must be masked");
7036 [ # # # # ]: 0 : if (!action_conf || !action_conf->size)
7037 : 0 : return rte_flow_error_set(error, EINVAL,
7038 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
7039 : : "raw_encap: invalid action configuration");
7040 [ # # # # ]: 0 : if (mask_conf->data && !action_conf->data)
7041 : 0 : return rte_flow_error_set(error, EINVAL,
7042 : : RTE_FLOW_ERROR_TYPE_ACTION,
7043 : : action, "raw_encap: masked data is missing");
7044 : : return 0;
7045 : : }
7046 : :
7047 : :
7048 : : static int
7049 : 0 : flow_hw_validate_action_raw_reformat(struct rte_eth_dev *dev,
7050 : : const struct rte_flow_action *template_action,
7051 : : const struct rte_flow_action *template_mask,
7052 : : const struct
7053 : : rte_flow_actions_template_attr *template_attr,
7054 : : uint64_t *action_flags,
7055 : : struct rte_flow_error *error)
7056 : : {
7057 : : const struct rte_flow_action *encap_action = NULL;
7058 : : const struct rte_flow_action *encap_mask = NULL;
7059 : : const struct rte_flow_action_raw_decap *raw_decap = NULL;
7060 : : const struct rte_flow_action_raw_encap *raw_encap = NULL;
7061 : 0 : const struct rte_flow_attr attr = {
7062 : 0 : .ingress = template_attr->ingress,
7063 : 0 : .egress = template_attr->egress,
7064 : 0 : .transfer = template_attr->transfer
7065 : : };
7066 : : uint64_t item_flags = 0;
7067 : 0 : int ret, actions_n = 0;
7068 : :
7069 [ # # ]: 0 : if (template_action->type == RTE_FLOW_ACTION_TYPE_RAW_DECAP) {
7070 : 0 : raw_decap = template_mask->conf ?
7071 [ # # ]: 0 : template_action->conf : &empty_decap;
7072 [ # # ]: 0 : if ((template_action + 1)->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7073 [ # # ]: 0 : if ((template_mask + 1)->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP)
7074 : 0 : return rte_flow_error_set(error, EINVAL,
7075 : : RTE_FLOW_ERROR_TYPE_ACTION,
7076 : 0 : template_mask + 1, "invalid mask type");
7077 : 0 : encap_action = template_action + 1;
7078 : 0 : encap_mask = template_mask + 1;
7079 : : }
7080 : : } else {
7081 : : encap_action = template_action;
7082 : : encap_mask = template_mask;
7083 : : }
7084 [ # # ]: 0 : if (encap_action) {
7085 : 0 : raw_encap = encap_action->conf;
7086 : 0 : ret = flow_hw_validate_action_raw_encap(encap_action,
7087 : : encap_mask, error);
7088 [ # # ]: 0 : if (ret)
7089 : : return ret;
7090 : : }
7091 : 0 : return mlx5_flow_dv_validate_action_raw_encap_decap(dev, raw_decap,
7092 : : raw_encap, &attr,
7093 : : action_flags,
7094 : : &actions_n,
7095 : : template_action,
7096 : : item_flags, error);
7097 : : }
7098 : :
7099 : :
7100 : :
7101 : : static int
7102 : 0 : mlx5_flow_hw_actions_validate(struct rte_eth_dev *dev,
7103 : : const struct rte_flow_actions_template_attr *attr,
7104 : : const struct rte_flow_action actions[],
7105 : : const struct rte_flow_action masks[],
7106 : : uint64_t *act_flags,
7107 : : struct rte_flow_error *error)
7108 : : {
7109 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
7110 : : const struct rte_flow_action_count *count_mask = NULL;
7111 : 0 : bool fixed_cnt = false;
7112 : 0 : uint64_t action_flags = 0;
7113 : : bool actions_end = false;
7114 : : uint16_t i;
7115 : : int ret;
7116 : : const struct rte_flow_action_ipv6_ext_remove *remove_data;
7117 : :
7118 [ # # ]: 0 : if (!mlx5_hw_ctx_validate(dev, error))
7119 : 0 : return -rte_errno;
7120 : : /* FDB actions are only valid to proxy port. */
7121 [ # # # # : 0 : if (attr->transfer && (!priv->sh->config.dv_esw_en || !priv->master))
# # ]
7122 : 0 : return rte_flow_error_set(error, EINVAL,
7123 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7124 : : NULL,
7125 : : "transfer actions are only valid to proxy port");
7126 [ # # ]: 0 : for (i = 0; !actions_end; ++i) {
7127 : 0 : const struct rte_flow_action *action = &actions[i];
7128 : 0 : const struct rte_flow_action *mask = &masks[i];
7129 : :
7130 : : MLX5_ASSERT(i < MLX5_HW_MAX_ACTS);
7131 [ # # ]: 0 : if (action->type != RTE_FLOW_ACTION_TYPE_INDIRECT &&
7132 [ # # ]: 0 : action->type != mask->type)
7133 : 0 : return rte_flow_error_set(error, ENOTSUP,
7134 : : RTE_FLOW_ERROR_TYPE_ACTION,
7135 : : action,
7136 : : "mask type does not match action type");
7137 [ # # # # : 0 : switch ((int)action->type) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # ]
7138 : : case RTE_FLOW_ACTION_TYPE_VOID:
7139 : 0 : break;
7140 : : case RTE_FLOW_ACTION_TYPE_INDIRECT_LIST:
7141 : : break;
7142 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT:
7143 : 0 : ret = flow_hw_validate_action_indirect(dev, action,
7144 : : mask,
7145 : : &action_flags,
7146 : : &fixed_cnt,
7147 : : error);
7148 [ # # ]: 0 : if (ret < 0)
7149 : 0 : return ret;
7150 : : break;
7151 : 0 : case RTE_FLOW_ACTION_TYPE_FLAG:
7152 : : /* TODO: Validation logic */
7153 : 0 : action_flags |= MLX5_FLOW_ACTION_FLAG;
7154 : 0 : break;
7155 : 0 : case RTE_FLOW_ACTION_TYPE_MARK:
7156 : 0 : ret = mlx5_hw_validate_action_mark(dev, action, mask,
7157 : : action_flags,
7158 : : attr, error);
7159 [ # # ]: 0 : if (ret)
7160 : 0 : return ret;
7161 : 0 : action_flags |= MLX5_FLOW_ACTION_MARK;
7162 : 0 : break;
7163 : 0 : case RTE_FLOW_ACTION_TYPE_DROP:
7164 : 0 : ret = mlx5_flow_validate_action_drop
7165 : : (dev, action_flags,
7166 : 0 : &(struct rte_flow_attr){.egress = attr->egress},
7167 : : error);
7168 [ # # ]: 0 : if (ret)
7169 : 0 : return ret;
7170 : 0 : action_flags |= MLX5_FLOW_ACTION_DROP;
7171 : 0 : break;
7172 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP:
7173 : : /* Only validate the jump to root table in template stage. */
7174 : 0 : ret = flow_hw_validate_action_jump(dev, attr, action, mask, error);
7175 [ # # ]: 0 : if (ret)
7176 : 0 : return ret;
7177 : 0 : action_flags |= MLX5_FLOW_ACTION_JUMP;
7178 : 0 : break;
7179 : : #ifdef HAVE_MLX5DV_DR_ACTION_CREATE_DEST_ROOT_TABLE
7180 : : case RTE_FLOW_ACTION_TYPE_SEND_TO_KERNEL: {
7181 : : bool res;
7182 : :
7183 : : if (priv->shared_host)
7184 : : return rte_flow_error_set(error, ENOTSUP,
7185 : : RTE_FLOW_ERROR_TYPE_ACTION,
7186 : : action,
7187 : : "action not supported in guest port");
7188 : : if (attr->ingress) {
7189 : : res = priv->hw_send_to_kernel[MLX5DR_TABLE_TYPE_NIC_RX];
7190 : : } else if (attr->egress) {
7191 : : res = priv->hw_send_to_kernel[MLX5DR_TABLE_TYPE_NIC_TX];
7192 : : } else {
7193 : : if (!is_unified_fdb(priv))
7194 : : res = priv->hw_send_to_kernel[MLX5DR_TABLE_TYPE_FDB];
7195 : : else
7196 : : res =
7197 : : priv->hw_send_to_kernel[MLX5DR_TABLE_TYPE_FDB_RX] &&
7198 : : priv->hw_send_to_kernel[MLX5DR_TABLE_TYPE_FDB_TX] &&
7199 : : priv->hw_send_to_kernel[MLX5DR_TABLE_TYPE_FDB_UNIFIED];
7200 : : }
7201 : : if (!res)
7202 : : return rte_flow_error_set(error, ENOTSUP,
7203 : : RTE_FLOW_ERROR_TYPE_ACTION,
7204 : : action,
7205 : : "action is not available");
7206 : :
7207 : : action_flags |= MLX5_FLOW_ACTION_SEND_TO_KERNEL;
7208 : : break;
7209 : : }
7210 : : #endif
7211 : 0 : case RTE_FLOW_ACTION_TYPE_QUEUE:
7212 : 0 : ret = mlx5_hw_validate_action_queue(dev, action, mask,
7213 : : attr, action_flags,
7214 : : error);
7215 [ # # ]: 0 : if (ret)
7216 : 0 : return ret;
7217 : 0 : action_flags |= MLX5_FLOW_ACTION_QUEUE;
7218 : 0 : break;
7219 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
7220 : 0 : ret = mlx5_hw_validate_action_rss(dev, action, mask,
7221 : : attr, action_flags,
7222 : : error);
7223 [ # # ]: 0 : if (ret)
7224 : 0 : return ret;
7225 : 0 : action_flags |= MLX5_FLOW_ACTION_RSS;
7226 : 0 : break;
7227 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7228 : : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7229 : 0 : ret = mlx5_hw_validate_action_l2_encap(dev, action, mask,
7230 : : attr, action_flags,
7231 : : error);
7232 [ # # ]: 0 : if (ret)
7233 : 0 : return ret;
7234 : 0 : action_flags |= MLX5_FLOW_ACTION_ENCAP;
7235 : 0 : break;
7236 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7237 : : case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7238 : 0 : ret = mlx5_hw_validate_action_l2_decap(dev, action, mask,
7239 : : attr, action_flags,
7240 : : error);
7241 [ # # ]: 0 : if (ret)
7242 : 0 : return ret;
7243 : 0 : action_flags |= MLX5_FLOW_ACTION_DECAP;
7244 : 0 : break;
7245 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7246 : : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7247 : 0 : ret = flow_hw_validate_action_raw_reformat(dev, action,
7248 : : mask, attr,
7249 : : &action_flags,
7250 : : error);
7251 [ # # ]: 0 : if (ret)
7252 : 0 : return ret;
7253 [ # # ]: 0 : if (action->type == RTE_FLOW_ACTION_TYPE_RAW_DECAP &&
7254 [ # # ]: 0 : (action + 1)->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7255 : 0 : action_flags |= MLX5_FLOW_XCAP_ACTIONS;
7256 : 0 : i++;
7257 : : }
7258 : : break;
7259 : 0 : case RTE_FLOW_ACTION_TYPE_IPV6_EXT_PUSH:
7260 : 0 : ret = flow_hw_validate_action_ipv6_ext_push(dev, action, error);
7261 [ # # ]: 0 : if (ret < 0)
7262 : 0 : return ret;
7263 : 0 : action_flags |= MLX5_FLOW_ACTION_IPV6_ROUTING_PUSH;
7264 : 0 : break;
7265 : 0 : case RTE_FLOW_ACTION_TYPE_IPV6_EXT_REMOVE:
7266 : 0 : remove_data = action->conf;
7267 : : /* Remove action must be shared. */
7268 [ # # # # ]: 0 : if (remove_data->type != IPPROTO_ROUTING || !mask) {
7269 : 0 : DRV_LOG(ERR, "Only supports shared IPv6 routing remove");
7270 : 0 : return -EINVAL;
7271 : : }
7272 : 0 : action_flags |= MLX5_FLOW_ACTION_IPV6_ROUTING_REMOVE;
7273 : 0 : break;
7274 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
7275 : 0 : ret = flow_hw_validate_action_meter_mark(dev, action, false, error);
7276 [ # # ]: 0 : if (ret < 0)
7277 : 0 : return ret;
7278 : 0 : action_flags |= MLX5_FLOW_ACTION_METER;
7279 : 0 : break;
7280 : 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
7281 : 0 : ret = flow_hw_validate_action_modify_field(dev, action, mask,
7282 : : error);
7283 [ # # ]: 0 : if (ret < 0)
7284 : 0 : return ret;
7285 : 0 : action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
7286 : 0 : break;
7287 : 0 : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
7288 : 0 : ret = flow_hw_validate_action_represented_port
7289 : : (dev, action, mask, error);
7290 [ # # ]: 0 : if (ret < 0)
7291 : 0 : return ret;
7292 : 0 : action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7293 : 0 : break;
7294 : 0 : case RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:
7295 : 0 : ret = flow_hw_validate_action_port_representor
7296 : : (dev, attr, action, mask, error);
7297 [ # # ]: 0 : if (ret < 0)
7298 : 0 : return ret;
7299 : 0 : action_flags |= MLX5_FLOW_ACTION_PORT_REPRESENTOR;
7300 : 0 : break;
7301 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
7302 [ # # # # ]: 0 : if (count_mask && count_mask->id)
7303 : 0 : fixed_cnt = true;
7304 : 0 : ret = flow_hw_validate_action_age(dev, action,
7305 : : action_flags,
7306 : : fixed_cnt, error);
7307 [ # # ]: 0 : if (ret < 0)
7308 : 0 : return ret;
7309 : 0 : action_flags |= MLX5_FLOW_ACTION_AGE;
7310 : 0 : break;
7311 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
7312 : 0 : ret = flow_hw_validate_action_count(dev, action, mask,
7313 : : action_flags,
7314 : : error);
7315 [ # # ]: 0 : if (ret < 0)
7316 : 0 : return ret;
7317 : 0 : count_mask = mask->conf;
7318 : 0 : action_flags |= MLX5_FLOW_ACTION_COUNT;
7319 : 0 : break;
7320 : 0 : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
7321 : 0 : ret = mlx5_hw_validate_action_conntrack(dev, action, mask,
7322 : : attr, action_flags,
7323 : : error);
7324 [ # # ]: 0 : if (ret)
7325 : 0 : return ret;
7326 : 0 : action_flags |= MLX5_FLOW_ACTION_CT;
7327 : 0 : break;
7328 : 0 : case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7329 : 0 : action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7330 : 0 : break;
7331 : 0 : case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7332 : 0 : action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7333 : 0 : break;
7334 : 0 : case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7335 : 0 : ret = flow_hw_validate_action_push_vlan
7336 : : (dev, attr, action, mask, error);
7337 [ # # ]: 0 : if (ret != 0)
7338 : 0 : return ret;
7339 : 0 : i += is_of_vlan_pcp_present(action) ?
7340 [ # # ]: 0 : MLX5_HW_VLAN_PUSH_PCP_IDX :
7341 : : MLX5_HW_VLAN_PUSH_VID_IDX;
7342 : 0 : action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7343 : 0 : break;
7344 : 0 : case RTE_FLOW_ACTION_TYPE_NAT64:
7345 : 0 : ret = flow_hw_validate_action_nat64(dev, attr, action, mask,
7346 : : action_flags, error);
7347 [ # # ]: 0 : if (ret != 0)
7348 : 0 : return ret;
7349 : 0 : action_flags |= MLX5_FLOW_ACTION_NAT64;
7350 : 0 : break;
7351 : 0 : case RTE_FLOW_ACTION_TYPE_END:
7352 : : actions_end = true;
7353 : 0 : break;
7354 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
7355 : 0 : ret = flow_hw_validate_action_default_miss(dev, attr,
7356 : : action_flags, error);
7357 [ # # ]: 0 : if (ret < 0)
7358 : 0 : return ret;
7359 : 0 : action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
7360 : 0 : break;
7361 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
7362 : 0 : ret = mlx5_flow_validate_action_jump_to_table_index(action, mask, error);
7363 [ # # ]: 0 : if (ret < 0)
7364 : 0 : return ret;
7365 : 0 : action_flags |= MLX5_FLOW_ACTION_JUMP_TO_TABLE_INDEX;
7366 : 0 : break;
7367 : 0 : default:
7368 : 0 : return rte_flow_error_set(error, ENOTSUP,
7369 : : RTE_FLOW_ERROR_TYPE_ACTION,
7370 : : action,
7371 : : "action not supported in template API");
7372 : : }
7373 : : }
7374 [ # # ]: 0 : if (act_flags != NULL)
7375 : 0 : *act_flags = action_flags;
7376 : : return 0;
7377 : : }
7378 : :
7379 : : static int
7380 : 0 : flow_hw_actions_validate(struct rte_eth_dev *dev,
7381 : : const struct rte_flow_actions_template_attr *attr,
7382 : : const struct rte_flow_action actions[],
7383 : : const struct rte_flow_action masks[],
7384 : : struct rte_flow_error *error)
7385 : : {
7386 : 0 : return mlx5_flow_hw_actions_validate(dev, attr, actions, masks, NULL, error);
7387 : : }
7388 : :
7389 : :
7390 : : static enum mlx5dr_action_type mlx5_hw_dr_action_types[] = {
7391 : : [RTE_FLOW_ACTION_TYPE_MARK] = MLX5DR_ACTION_TYP_TAG,
7392 : : [RTE_FLOW_ACTION_TYPE_FLAG] = MLX5DR_ACTION_TYP_TAG,
7393 : : [RTE_FLOW_ACTION_TYPE_DROP] = MLX5DR_ACTION_TYP_DROP,
7394 : : [RTE_FLOW_ACTION_TYPE_JUMP] = MLX5DR_ACTION_TYP_TBL,
7395 : : [RTE_FLOW_ACTION_TYPE_QUEUE] = MLX5DR_ACTION_TYP_TIR,
7396 : : [RTE_FLOW_ACTION_TYPE_RSS] = MLX5DR_ACTION_TYP_TIR,
7397 : : [RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP] = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2,
7398 : : [RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP] = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2,
7399 : : [RTE_FLOW_ACTION_TYPE_VXLAN_DECAP] = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2,
7400 : : [RTE_FLOW_ACTION_TYPE_NVGRE_DECAP] = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2,
7401 : : [RTE_FLOW_ACTION_TYPE_MODIFY_FIELD] = MLX5DR_ACTION_TYP_MODIFY_HDR,
7402 : : [RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT] = MLX5DR_ACTION_TYP_VPORT,
7403 : : [RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR] = MLX5DR_ACTION_TYP_MISS,
7404 : : [RTE_FLOW_ACTION_TYPE_CONNTRACK] = MLX5DR_ACTION_TYP_ASO_CT,
7405 : : [RTE_FLOW_ACTION_TYPE_OF_POP_VLAN] = MLX5DR_ACTION_TYP_POP_VLAN,
7406 : : [RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN] = MLX5DR_ACTION_TYP_PUSH_VLAN,
7407 : : [RTE_FLOW_ACTION_TYPE_SEND_TO_KERNEL] = MLX5DR_ACTION_TYP_DEST_ROOT,
7408 : : [RTE_FLOW_ACTION_TYPE_IPV6_EXT_PUSH] = MLX5DR_ACTION_TYP_PUSH_IPV6_ROUTE_EXT,
7409 : : [RTE_FLOW_ACTION_TYPE_IPV6_EXT_REMOVE] = MLX5DR_ACTION_TYP_POP_IPV6_ROUTE_EXT,
7410 : : [RTE_FLOW_ACTION_TYPE_NAT64] = MLX5DR_ACTION_TYP_NAT64,
7411 : : [RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX] = MLX5DR_ACTION_TYP_JUMP_TO_MATCHER,
7412 : : };
7413 : :
7414 : : static inline void
7415 : : action_template_set_type(struct rte_flow_actions_template *at,
7416 : : enum mlx5dr_action_type *action_types,
7417 : : unsigned int action_src, uint16_t *curr_off,
7418 : : enum mlx5dr_action_type type)
7419 : : {
7420 : 0 : at->dr_off[action_src] = *curr_off;
7421 : 0 : action_types[*curr_off] = type;
7422 : 0 : *curr_off = *curr_off + 1;
7423 : 0 : }
7424 : :
7425 : : static int
7426 : 0 : flow_hw_dr_actions_template_handle_shared(int type, uint32_t action_src,
7427 : : enum mlx5dr_action_type *action_types,
7428 : : uint16_t *curr_off, uint16_t *cnt_off,
7429 : : struct rte_flow_actions_template *at)
7430 : : {
7431 [ # # # # : 0 : switch (type) {
# ]
7432 : : case RTE_FLOW_ACTION_TYPE_RSS:
7433 : : action_template_set_type(at, action_types, action_src, curr_off,
7434 : : MLX5DR_ACTION_TYP_TIR);
7435 : : break;
7436 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
7437 : : case RTE_FLOW_ACTION_TYPE_COUNT:
7438 : : /*
7439 : : * Both AGE and COUNT action need counter, the first one fills
7440 : : * the action_types array, and the second only saves the offset.
7441 : : */
7442 [ # # ]: 0 : if (*cnt_off == UINT16_MAX) {
7443 : 0 : *cnt_off = *curr_off;
7444 : : action_template_set_type(at, action_types,
7445 : : action_src, curr_off,
7446 : : MLX5DR_ACTION_TYP_CTR);
7447 : : }
7448 : 0 : at->dr_off[action_src] = *cnt_off;
7449 : 0 : break;
7450 : : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
7451 : : action_template_set_type(at, action_types, action_src, curr_off,
7452 : : MLX5DR_ACTION_TYP_ASO_CT);
7453 : : break;
7454 : : case RTE_FLOW_ACTION_TYPE_QUOTA:
7455 : : case RTE_FLOW_ACTION_TYPE_METER_MARK:
7456 : : action_template_set_type(at, action_types, action_src, curr_off,
7457 : : MLX5DR_ACTION_TYP_ASO_METER);
7458 : : break;
7459 : 0 : default:
7460 : 0 : DRV_LOG(WARNING, "Unsupported shared action type: %d", type);
7461 : 0 : return -EINVAL;
7462 : : }
7463 : : return 0;
7464 : : }
7465 : :
7466 : :
7467 : : static int
7468 : 0 : flow_hw_template_actions_list(struct rte_flow_actions_template *at,
7469 : : unsigned int action_src,
7470 : : enum mlx5dr_action_type *action_types,
7471 : : uint16_t *curr_off, uint16_t *cnt_off)
7472 : : {
7473 : : int ret;
7474 : 0 : const struct rte_flow_action_indirect_list *indlst_conf = at->actions[action_src].conf;
7475 [ # # # # ]: 0 : enum mlx5_indirect_list_type list_type = mlx5_get_indirect_list_type(indlst_conf->handle);
7476 : : const union {
7477 : : struct mlx5_indlst_legacy *legacy;
7478 : : struct rte_flow_action_list_handle *handle;
7479 : : } indlst_obj = { .handle = indlst_conf->handle };
7480 : : enum mlx5dr_action_type type;
7481 : :
7482 [ # # # # ]: 0 : switch (list_type) {
7483 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY:
7484 : 0 : ret = flow_hw_dr_actions_template_handle_shared
7485 : 0 : (indlst_obj.legacy->legacy_type, action_src,
7486 : : action_types, curr_off, cnt_off, at);
7487 [ # # ]: 0 : if (ret)
7488 : 0 : return ret;
7489 : : break;
7490 : : case MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR:
7491 : : action_template_set_type(at, action_types, action_src, curr_off,
7492 : : MLX5DR_ACTION_TYP_DEST_ARRAY);
7493 : : break;
7494 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT:
7495 : 0 : type = ((struct mlx5_hw_encap_decap_action *)
7496 : : (indlst_conf->handle))->action_type;
7497 : : action_template_set_type(at, action_types, action_src, curr_off, type);
7498 : : break;
7499 : 0 : default:
7500 : 0 : DRV_LOG(ERR, "Unsupported indirect list type");
7501 : 0 : return -EINVAL;
7502 : : }
7503 : : return 0;
7504 : : }
7505 : :
7506 : : /**
7507 : : * Create DR action template based on a provided sequence of flow actions.
7508 : : *
7509 : : * @param[in] dev
7510 : : * Pointer to the rte_eth_dev structure.
7511 : : * @param[in] at
7512 : : * Pointer to flow actions template to be updated.
7513 : : * @param[out] action_types
7514 : : * Action types array to be filled.
7515 : : * @param[out] tmpl_flags
7516 : : * Template DR flags to be filled.
7517 : : *
7518 : : * @return
7519 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
7520 : : */
7521 : : static int
7522 : 0 : flow_hw_parse_flow_actions_to_dr_actions(struct rte_eth_dev *dev,
7523 : : struct rte_flow_actions_template *at,
7524 : : enum mlx5dr_action_type action_types[MLX5_HW_MAX_ACTS],
7525 : : uint32_t *tmpl_flags __rte_unused)
7526 : : {
7527 : : unsigned int i;
7528 : : uint16_t curr_off;
7529 : : enum mlx5dr_action_type reformat_act_type = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2;
7530 : : uint16_t reformat_off = UINT16_MAX;
7531 : : uint16_t mhdr_off = UINT16_MAX;
7532 : : uint16_t recom_off = UINT16_MAX;
7533 : 0 : uint16_t cnt_off = UINT16_MAX;
7534 : : enum mlx5dr_action_type recom_type = MLX5DR_ACTION_TYP_LAST;
7535 : : int ret;
7536 : :
7537 [ # # ]: 0 : for (i = 0, curr_off = 0; at->actions[i].type != RTE_FLOW_ACTION_TYPE_END; ++i) {
7538 : : const struct rte_flow_action_raw_encap *raw_encap_data;
7539 : : size_t data_size;
7540 : : enum mlx5dr_action_type type;
7541 : :
7542 [ # # ]: 0 : if (curr_off >= MLX5_HW_MAX_ACTS)
7543 : 0 : goto err_actions_num;
7544 [ # # # # : 0 : switch ((int)at->actions[i].type) {
# # # # #
# # # # #
# ]
7545 : : case RTE_FLOW_ACTION_TYPE_VOID:
7546 : : break;
7547 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT_LIST:
7548 : 0 : ret = flow_hw_template_actions_list(at, i, action_types,
7549 : : &curr_off, &cnt_off);
7550 [ # # ]: 0 : if (ret)
7551 : 0 : return ret;
7552 : : break;
7553 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT:
7554 : 0 : ret = flow_hw_dr_actions_template_handle_shared
7555 : 0 : (at->masks[i].type, i, action_types,
7556 : : &curr_off, &cnt_off, at);
7557 [ # # ]: 0 : if (ret)
7558 : 0 : return ret;
7559 : : break;
7560 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7561 : : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7562 : : case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7563 : : case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7564 : : MLX5_ASSERT(reformat_off == UINT16_MAX);
7565 : 0 : reformat_off = curr_off++;
7566 : 0 : reformat_act_type = mlx5_hw_dr_action_types[at->actions[i].type];
7567 : 0 : break;
7568 : 0 : case RTE_FLOW_ACTION_TYPE_IPV6_EXT_PUSH:
7569 : : MLX5_ASSERT(recom_off == UINT16_MAX);
7570 : : recom_type = MLX5DR_ACTION_TYP_PUSH_IPV6_ROUTE_EXT;
7571 : 0 : recom_off = curr_off++;
7572 : 0 : break;
7573 : 0 : case RTE_FLOW_ACTION_TYPE_IPV6_EXT_REMOVE:
7574 : : MLX5_ASSERT(recom_off == UINT16_MAX);
7575 : : recom_type = MLX5DR_ACTION_TYP_POP_IPV6_ROUTE_EXT;
7576 : 0 : recom_off = curr_off++;
7577 : 0 : break;
7578 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7579 : 0 : raw_encap_data = at->actions[i].conf;
7580 : 0 : data_size = raw_encap_data->size;
7581 [ # # ]: 0 : if (reformat_off != UINT16_MAX) {
7582 : : reformat_act_type = data_size < MLX5_ENCAPSULATION_DECISION_SIZE ?
7583 [ # # ]: 0 : MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2 :
7584 : : MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3;
7585 : : } else {
7586 : 0 : reformat_off = curr_off++;
7587 : : reformat_act_type = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;
7588 : : }
7589 : : break;
7590 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7591 : 0 : reformat_off = curr_off++;
7592 : : reformat_act_type = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2;
7593 : 0 : break;
7594 : 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
7595 [ # # ]: 0 : if (mhdr_off == UINT16_MAX) {
7596 : 0 : mhdr_off = curr_off++;
7597 : 0 : type = mlx5_hw_dr_action_types[at->actions[i].type];
7598 : 0 : action_types[mhdr_off] = type;
7599 : : }
7600 : : break;
7601 : 0 : case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7602 : 0 : type = mlx5_hw_dr_action_types[at->actions[i].type];
7603 : 0 : at->dr_off[i] = curr_off;
7604 : 0 : action_types[curr_off++] = type;
7605 : 0 : i += is_of_vlan_pcp_present(at->actions + i) ?
7606 [ # # ]: 0 : MLX5_HW_VLAN_PUSH_PCP_IDX :
7607 : : MLX5_HW_VLAN_PUSH_VID_IDX;
7608 : 0 : break;
7609 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
7610 : 0 : at->dr_off[i] = curr_off;
7611 : 0 : action_types[curr_off++] = MLX5DR_ACTION_TYP_ASO_METER;
7612 [ # # ]: 0 : if (curr_off >= MLX5_HW_MAX_ACTS)
7613 : 0 : goto err_actions_num;
7614 : : break;
7615 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
7616 : : case RTE_FLOW_ACTION_TYPE_COUNT:
7617 : : /*
7618 : : * Both AGE and COUNT action need counter, the first
7619 : : * one fills the action_types array, and the second only
7620 : : * saves the offset.
7621 : : */
7622 [ # # ]: 0 : if (cnt_off == UINT16_MAX) {
7623 : 0 : cnt_off = curr_off++;
7624 : 0 : action_types[cnt_off] = MLX5DR_ACTION_TYP_CTR;
7625 : : }
7626 : 0 : at->dr_off[i] = cnt_off;
7627 : 0 : break;
7628 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
7629 : 0 : at->dr_off[i] = curr_off;
7630 : 0 : action_types[curr_off++] = MLX5DR_ACTION_TYP_MISS;
7631 : 0 : break;
7632 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
7633 : 0 : *tmpl_flags |= MLX5DR_ACTION_TEMPLATE_FLAG_RELAXED_ORDER;
7634 : 0 : at->dr_off[i] = curr_off;
7635 : 0 : action_types[curr_off++] = MLX5DR_ACTION_TYP_JUMP_TO_MATCHER;
7636 : 0 : break;
7637 : 0 : default:
7638 : 0 : type = mlx5_hw_dr_action_types[at->actions[i].type];
7639 : 0 : at->dr_off[i] = curr_off;
7640 : 0 : action_types[curr_off++] = type;
7641 : 0 : break;
7642 : : }
7643 : : }
7644 [ # # ]: 0 : if (curr_off >= MLX5_HW_MAX_ACTS)
7645 : 0 : goto err_actions_num;
7646 [ # # ]: 0 : if (mhdr_off != UINT16_MAX)
7647 : 0 : at->mhdr_off = mhdr_off;
7648 [ # # ]: 0 : if (reformat_off != UINT16_MAX) {
7649 : 0 : at->reformat_off = reformat_off;
7650 : 0 : action_types[reformat_off] = reformat_act_type;
7651 : : }
7652 [ # # ]: 0 : if (recom_off != UINT16_MAX) {
7653 : 0 : at->recom_off = recom_off;
7654 : 0 : action_types[recom_off] = recom_type;
7655 : : }
7656 : 0 : at->dr_actions_num = curr_off;
7657 : :
7658 : : /* Create srh flex parser for remove anchor. */
7659 [ # # ]: 0 : if ((recom_type == MLX5DR_ACTION_TYP_POP_IPV6_ROUTE_EXT ||
7660 [ # # ]: 0 : recom_type == MLX5DR_ACTION_TYP_PUSH_IPV6_ROUTE_EXT) &&
7661 : 0 : (ret = mlx5_alloc_srh_flex_parser(dev))) {
7662 : 0 : DRV_LOG(ERR, "Failed to create srv6 flex parser");
7663 : 0 : return ret;
7664 : : }
7665 : : return 0;
7666 : 0 : err_actions_num:
7667 : 0 : DRV_LOG(ERR, "Number of HW actions (%u) exceeded maximum (%u) allowed in template",
7668 : : curr_off, MLX5_HW_MAX_ACTS);
7669 : 0 : return -EINVAL;
7670 : : }
7671 : :
7672 : : static int
7673 : 0 : flow_hw_set_vlan_vid(struct rte_eth_dev *dev,
7674 : : struct rte_flow_action *ra,
7675 : : struct rte_flow_action *rm,
7676 : : struct rte_flow_action_modify_field *spec,
7677 : : struct rte_flow_action_modify_field *mask,
7678 : : int set_vlan_vid_ix,
7679 : : struct rte_flow_error *error)
7680 : : {
7681 [ # # ]: 0 : const bool masked = rm[set_vlan_vid_ix].conf &&
7682 : : (((const struct rte_flow_action_of_set_vlan_vid *)
7683 [ # # ]: 0 : rm[set_vlan_vid_ix].conf)->vlan_vid != 0);
7684 : 0 : const struct rte_flow_action_of_set_vlan_vid *conf =
7685 : 0 : ra[set_vlan_vid_ix].conf;
7686 : 0 : int width = mlx5_flow_item_field_width(dev, RTE_FLOW_FIELD_VLAN_ID, 0,
7687 : : NULL, error);
7688 : : MLX5_ASSERT(width);
7689 : 0 : *spec = (typeof(*spec)) {
7690 : : .operation = RTE_FLOW_MODIFY_SET,
7691 : : .dst = {
7692 : : .field = RTE_FLOW_FIELD_VLAN_ID,
7693 : : .level = 0, .offset = 0,
7694 : : },
7695 : : .src = {
7696 : : .field = RTE_FLOW_FIELD_VALUE,
7697 : : },
7698 : : .width = width,
7699 : : };
7700 : 0 : *mask = (typeof(*mask)) {
7701 : : .operation = RTE_FLOW_MODIFY_SET,
7702 : : .dst = {
7703 : : .field = RTE_FLOW_FIELD_VLAN_ID,
7704 : : .level = 0xff, .offset = 0xffffffff,
7705 : : },
7706 : : .src = {
7707 : : .field = RTE_FLOW_FIELD_VALUE,
7708 : : },
7709 : : .width = 0xffffffff,
7710 : : };
7711 [ # # ]: 0 : if (masked) {
7712 : 0 : uint32_t mask_val = 0xffffffff;
7713 : :
7714 [ # # ]: 0 : rte_memcpy(spec->src.value, &conf->vlan_vid, sizeof(conf->vlan_vid));
7715 [ # # ]: 0 : rte_memcpy(mask->src.value, &mask_val, sizeof(mask_val));
7716 : : }
7717 : 0 : ra[set_vlan_vid_ix].type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD;
7718 : 0 : ra[set_vlan_vid_ix].conf = spec;
7719 : 0 : rm[set_vlan_vid_ix].type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD;
7720 : 0 : rm[set_vlan_vid_ix].conf = mask;
7721 : 0 : return 0;
7722 : : }
7723 : :
7724 : : static __rte_always_inline int
7725 : : flow_hw_set_vlan_vid_construct(struct rte_eth_dev *dev,
7726 : : struct mlx5_modification_cmd *mhdr_cmd,
7727 : : struct mlx5_action_construct_data *act_data,
7728 : : const struct mlx5_hw_actions *hw_acts,
7729 : : const struct rte_flow_action *action)
7730 : : {
7731 : : struct rte_flow_error error;
7732 : 0 : rte_be16_t vid = ((const struct rte_flow_action_of_set_vlan_vid *)
7733 : 0 : action->conf)->vlan_vid;
7734 : 0 : int width = mlx5_flow_item_field_width(dev, RTE_FLOW_FIELD_VLAN_ID, 0,
7735 : : NULL, &error);
7736 [ # # # # : 0 : struct rte_flow_action_modify_field conf = {
# # # # #
# ]
7737 : : .operation = RTE_FLOW_MODIFY_SET,
7738 : : .dst = {
7739 : : .field = RTE_FLOW_FIELD_VLAN_ID,
7740 : : .level = 0, .offset = 0,
7741 : : },
7742 : : .src = {
7743 : : .field = RTE_FLOW_FIELD_VALUE,
7744 : : },
7745 : : .width = width,
7746 : : };
7747 : : struct rte_flow_action modify_action = {
7748 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
7749 : : .conf = &conf
7750 : : };
7751 : :
7752 : : rte_memcpy(conf.src.value, &vid, sizeof(vid));
7753 : : return flow_hw_modify_field_construct(mhdr_cmd, act_data, hw_acts, &modify_action);
7754 : : }
7755 : :
7756 : : static int
7757 : 0 : flow_hw_flex_item_acquire(struct rte_eth_dev *dev,
7758 : : struct rte_flow_item_flex_handle *handle,
7759 : : uint8_t *flex_item)
7760 : : {
7761 : 0 : int index = mlx5_flex_acquire_index(dev, handle, false);
7762 : :
7763 : : MLX5_ASSERT(index >= 0 && index < (int)(sizeof(uint32_t) * CHAR_BIT));
7764 [ # # ]: 0 : if (index < 0)
7765 : : return -1;
7766 [ # # ]: 0 : if (!(*flex_item & RTE_BIT32(index))) {
7767 : : /* Don't count same flex item again. */
7768 : 0 : if (mlx5_flex_acquire_index(dev, handle, true) != index)
7769 : : MLX5_ASSERT(false);
7770 : 0 : *flex_item |= (uint8_t)RTE_BIT32(index);
7771 : : }
7772 : : return 0;
7773 : : }
7774 : :
7775 : : static void
7776 : 0 : flow_hw_flex_item_release(struct rte_eth_dev *dev, uint8_t *flex_item)
7777 : : {
7778 [ # # ]: 0 : while (*flex_item) {
7779 : 0 : int index = rte_bsf32(*flex_item);
7780 : :
7781 : 0 : mlx5_flex_release_index(dev, index);
7782 : 0 : *flex_item &= ~(uint8_t)RTE_BIT32(index);
7783 : : }
7784 : 0 : }
7785 : : static __rte_always_inline void
7786 : : flow_hw_actions_template_replace_container(const
7787 : : struct rte_flow_action *actions,
7788 : : const
7789 : : struct rte_flow_action *masks,
7790 : : struct rte_flow_action *new_actions,
7791 : : struct rte_flow_action *new_masks,
7792 : : struct rte_flow_action **ra,
7793 : : struct rte_flow_action **rm,
7794 : : uint32_t act_num)
7795 : : {
7796 : 0 : memcpy(new_actions, actions, sizeof(actions[0]) * act_num);
7797 : : memcpy(new_masks, masks, sizeof(masks[0]) * act_num);
7798 : : *ra = (void *)(uintptr_t)new_actions;
7799 : : *rm = (void *)(uintptr_t)new_masks;
7800 : 0 : }
7801 : :
7802 : : /* Action template copies these actions in rte_flow_conv() */
7803 : :
7804 : : static const struct rte_flow_action rx_meta_copy_action = {
7805 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
7806 : : .conf = &(struct rte_flow_action_modify_field){
7807 : : .operation = RTE_FLOW_MODIFY_SET,
7808 : : .dst = {
7809 : : .field = (enum rte_flow_field_id)
7810 : : MLX5_RTE_FLOW_FIELD_META_REG,
7811 : : .tag_index = REG_B,
7812 : : },
7813 : : .src = {
7814 : : .field = (enum rte_flow_field_id)
7815 : : MLX5_RTE_FLOW_FIELD_META_REG,
7816 : : .tag_index = REG_C_1,
7817 : : },
7818 : : .width = 32,
7819 : : }
7820 : : };
7821 : :
7822 : : static const struct rte_flow_action rx_meta_copy_mask = {
7823 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
7824 : : .conf = &(struct rte_flow_action_modify_field){
7825 : : .operation = RTE_FLOW_MODIFY_SET,
7826 : : .dst = {
7827 : : .field = (enum rte_flow_field_id)
7828 : : MLX5_RTE_FLOW_FIELD_META_REG,
7829 : : .level = UINT8_MAX,
7830 : : .tag_index = UINT8_MAX,
7831 : : .offset = UINT32_MAX,
7832 : : },
7833 : : .src = {
7834 : : .field = (enum rte_flow_field_id)
7835 : : MLX5_RTE_FLOW_FIELD_META_REG,
7836 : : .level = UINT8_MAX,
7837 : : .tag_index = UINT8_MAX,
7838 : : .offset = UINT32_MAX,
7839 : : },
7840 : : .width = UINT32_MAX,
7841 : : }
7842 : : };
7843 : :
7844 : : static const struct rte_flow_action quota_color_inc_action = {
7845 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
7846 : : .conf = &(struct rte_flow_action_modify_field) {
7847 : : .operation = RTE_FLOW_MODIFY_ADD,
7848 : : .dst = {
7849 : : .field = RTE_FLOW_FIELD_METER_COLOR,
7850 : : .level = 0, .offset = 0
7851 : : },
7852 : : .src = {
7853 : : .field = RTE_FLOW_FIELD_VALUE,
7854 : : .level = 1,
7855 : : .offset = 0,
7856 : : },
7857 : : .width = 2
7858 : : }
7859 : : };
7860 : :
7861 : : static const struct rte_flow_action quota_color_inc_mask = {
7862 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
7863 : : .conf = &(struct rte_flow_action_modify_field) {
7864 : : .operation = RTE_FLOW_MODIFY_ADD,
7865 : : .dst = {
7866 : : .field = RTE_FLOW_FIELD_METER_COLOR,
7867 : : .level = UINT8_MAX,
7868 : : .tag_index = UINT8_MAX,
7869 : : .offset = UINT32_MAX,
7870 : : },
7871 : : .src = {
7872 : : .field = RTE_FLOW_FIELD_VALUE,
7873 : : .level = 3,
7874 : : .offset = 0
7875 : : },
7876 : : .width = UINT32_MAX
7877 : : }
7878 : : };
7879 : :
7880 : : /**
7881 : : * Create flow action template.
7882 : : *
7883 : : * @param[in] dev
7884 : : * Pointer to the rte_eth_dev structure.
7885 : : * @param[in] attr
7886 : : * Pointer to the action template attributes.
7887 : : * @param[in] actions
7888 : : * Associated actions (list terminated by the END action).
7889 : : * @param[in] masks
7890 : : * List of actions that marks which of the action's member is constant.
7891 : : * @param[in] nt_mode
7892 : : * Non template mode.
7893 : : * @param[out] error
7894 : : * Pointer to error structure.
7895 : : *
7896 : : * @return
7897 : : * Action template pointer on success, NULL otherwise and rte_errno is set.
7898 : : */
7899 : : static struct rte_flow_actions_template *
7900 : 0 : __flow_hw_actions_template_create(struct rte_eth_dev *dev,
7901 : : const struct rte_flow_actions_template_attr *attr,
7902 : : const struct rte_flow_action actions[],
7903 : : const struct rte_flow_action masks[],
7904 : : bool nt_mode,
7905 : : struct rte_flow_error *error)
7906 : : {
7907 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
7908 : : int len, act_len, mask_len;
7909 : : int orig_act_len;
7910 : : unsigned int act_num;
7911 : : unsigned int i;
7912 : : struct rte_flow_actions_template *at = NULL;
7913 : : uint16_t pos;
7914 : 0 : uint64_t action_flags = 0;
7915 : : struct rte_flow_action tmp_action[MLX5_HW_MAX_ACTS];
7916 : : struct rte_flow_action tmp_mask[MLX5_HW_MAX_ACTS];
7917 : : struct rte_flow_action *ra = (void *)(uintptr_t)actions;
7918 : : struct rte_flow_action *rm = (void *)(uintptr_t)masks;
7919 : : int set_vlan_vid_ix = -1;
7920 : 0 : struct rte_flow_action_modify_field set_vlan_vid_spec = {0, };
7921 : 0 : struct rte_flow_action_modify_field set_vlan_vid_mask = {0, };
7922 : : struct rte_flow_action mf_actions[MLX5_HW_MAX_ACTS];
7923 : : struct rte_flow_action mf_masks[MLX5_HW_MAX_ACTS];
7924 : : uint32_t expand_mf_num = 0;
7925 : 0 : uint16_t src_off[MLX5_HW_MAX_ACTS] = {0, };
7926 : 0 : enum mlx5dr_action_type action_types[MLX5_HW_MAX_ACTS] = { MLX5DR_ACTION_TYP_LAST };
7927 : 0 : uint32_t tmpl_flags = 0;
7928 : : int ret;
7929 : :
7930 [ # # # # ]: 0 : if (!nt_mode && mlx5_flow_hw_actions_validate(dev, attr, actions, masks,
7931 : : &action_flags, error))
7932 : : return NULL;
7933 [ # # ]: 0 : for (i = 0; ra[i].type != RTE_FLOW_ACTION_TYPE_END; ++i) {
7934 [ # # # ]: 0 : switch (ra[i].type) {
7935 : : /* OF_PUSH_VLAN *MUST* come before OF_SET_VLAN_VID */
7936 : 0 : case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7937 : 0 : i += is_of_vlan_pcp_present(ra + i) ?
7938 [ # # ]: 0 : MLX5_HW_VLAN_PUSH_PCP_IDX :
7939 : : MLX5_HW_VLAN_PUSH_VID_IDX;
7940 : 0 : break;
7941 : 0 : case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7942 : 0 : set_vlan_vid_ix = i;
7943 : 0 : break;
7944 : : default:
7945 : : break;
7946 : : }
7947 : : }
7948 : : /*
7949 : : * Count flow actions to allocate required space for storing DR offsets and to check
7950 : : * if temporary buffer would not be overrun.
7951 : : */
7952 : 0 : act_num = i + 1;
7953 [ # # ]: 0 : if (act_num >= MLX5_HW_MAX_ACTS) {
7954 : 0 : rte_flow_error_set(error, EINVAL,
7955 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL, "Too many actions");
7956 : 0 : return NULL;
7957 : : }
7958 [ # # ]: 0 : if (set_vlan_vid_ix != -1) {
7959 : : /* If temporary action buffer was not used, copy template actions to it */
7960 : : if (ra == actions)
7961 : : flow_hw_actions_template_replace_container(actions,
7962 : : masks,
7963 : : tmp_action,
7964 : : tmp_mask,
7965 : : &ra, &rm,
7966 : : act_num);
7967 : 0 : ret = flow_hw_set_vlan_vid(dev, ra, rm,
7968 : : &set_vlan_vid_spec, &set_vlan_vid_mask,
7969 : : set_vlan_vid_ix, error);
7970 [ # # ]: 0 : if (ret)
7971 : 0 : goto error;
7972 : 0 : action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
7973 : : }
7974 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_QUOTA) {
7975 : 0 : mf_actions[expand_mf_num] = quota_color_inc_action;
7976 : 0 : mf_masks[expand_mf_num] = quota_color_inc_mask;
7977 : : expand_mf_num++;
7978 : : }
7979 [ # # ]: 0 : if (priv->sh->config.dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS &&
7980 : 0 : priv->sh->config.dv_esw_en &&
7981 [ # # ]: 0 : !attr->transfer &&
7982 [ # # ]: 0 : (action_flags & (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS))) {
7983 : : /* Insert META copy */
7984 : 0 : mf_actions[expand_mf_num] = rx_meta_copy_action;
7985 : 0 : mf_masks[expand_mf_num] = rx_meta_copy_mask;
7986 : 0 : expand_mf_num++;
7987 : : }
7988 [ # # ]: 0 : if (expand_mf_num) {
7989 [ # # ]: 0 : if (act_num + expand_mf_num > MLX5_HW_MAX_ACTS) {
7990 : 0 : rte_flow_error_set(error, E2BIG,
7991 : : RTE_FLOW_ERROR_TYPE_ACTION,
7992 : : NULL, "cannot expand: too many actions");
7993 : 0 : return NULL;
7994 : : }
7995 [ # # ]: 0 : if (ra == actions)
7996 : : flow_hw_actions_template_replace_container(actions,
7997 : : masks,
7998 : : tmp_action,
7999 : : tmp_mask,
8000 : : &ra, &rm,
8001 : : act_num);
8002 : : /* Application should make sure only one Q/RSS exist in one rule. */
8003 : 0 : pos = flow_hw_template_expand_modify_field(ra, rm,
8004 : : mf_actions,
8005 : : mf_masks,
8006 : : action_flags,
8007 : : act_num,
8008 : : expand_mf_num);
8009 [ # # ]: 0 : if (pos == MLX5_HW_EXPAND_MH_FAILED) {
8010 : 0 : rte_flow_error_set(error, ENOMEM,
8011 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8012 : : NULL, "modify header expansion failed");
8013 : 0 : return NULL;
8014 : : }
8015 : : act_num += expand_mf_num;
8016 [ # # ]: 0 : for (i = pos + expand_mf_num; i < act_num; i++)
8017 : 0 : src_off[i] += expand_mf_num;
8018 : 0 : action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
8019 : : }
8020 : 0 : act_len = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, NULL, 0, ra, error);
8021 [ # # ]: 0 : if (act_len <= 0)
8022 : : return NULL;
8023 : 0 : len = RTE_ALIGN(act_len, 16);
8024 : 0 : mask_len = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, NULL, 0, rm, error);
8025 [ # # ]: 0 : if (mask_len <= 0)
8026 : : return NULL;
8027 : 0 : len += RTE_ALIGN(mask_len, 16);
8028 : 0 : len += RTE_ALIGN(act_num * sizeof(*at->dr_off), 16);
8029 : 0 : len += RTE_ALIGN(act_num * sizeof(*at->src_off), 16);
8030 : 0 : orig_act_len = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, NULL, 0, actions, error);
8031 [ # # ]: 0 : if (orig_act_len <= 0)
8032 : : return NULL;
8033 : 0 : len += RTE_ALIGN(orig_act_len, 16);
8034 : 0 : at = mlx5_malloc(MLX5_MEM_ZERO, len + sizeof(*at),
8035 : 0 : RTE_CACHE_LINE_SIZE, rte_socket_id());
8036 [ # # ]: 0 : if (!at) {
8037 : 0 : rte_flow_error_set(error, ENOMEM,
8038 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8039 : : NULL,
8040 : : "cannot allocate action template");
8041 : 0 : return NULL;
8042 : : }
8043 : : /* Actions part is in the first part. */
8044 : 0 : at->attr = *attr;
8045 : 0 : at->actions = (struct rte_flow_action *)(at + 1);
8046 : 0 : act_len = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, at->actions,
8047 : : len, ra, error);
8048 [ # # ]: 0 : if (act_len <= 0)
8049 : 0 : goto error;
8050 : : /* Masks part is in the second part. */
8051 : 0 : at->masks = (struct rte_flow_action *)(((uint8_t *)at->actions) + act_len);
8052 : 0 : mask_len = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, at->masks,
8053 : 0 : len - act_len, rm, error);
8054 [ # # ]: 0 : if (mask_len <= 0)
8055 : 0 : goto error;
8056 : : /* DR actions offsets in the third part. */
8057 : 0 : at->dr_off = (uint16_t *)((uint8_t *)at->masks + mask_len);
8058 : 0 : at->src_off = RTE_PTR_ADD(at->dr_off,
8059 : : RTE_ALIGN(act_num * sizeof(*at->dr_off), 16));
8060 : : memcpy(at->src_off, src_off, act_num * sizeof(at->src_off[0]));
8061 : 0 : at->orig_actions = RTE_PTR_ADD(at->src_off,
8062 : : RTE_ALIGN(act_num * sizeof(*at->src_off), 16));
8063 : 0 : orig_act_len = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, at->orig_actions, orig_act_len,
8064 : : actions, error);
8065 [ # # ]: 0 : if (orig_act_len <= 0)
8066 : 0 : goto error;
8067 : 0 : at->actions_num = act_num;
8068 [ # # ]: 0 : for (i = 0; i < at->actions_num; ++i)
8069 : 0 : at->dr_off[i] = UINT16_MAX;
8070 : 0 : at->reformat_off = UINT16_MAX;
8071 : 0 : at->mhdr_off = UINT16_MAX;
8072 : 0 : at->recom_off = UINT16_MAX;
8073 [ # # ]: 0 : for (i = 0; actions->type != RTE_FLOW_ACTION_TYPE_END;
8074 : 0 : actions++, masks++, i++) {
8075 : : const struct rte_flow_action_modify_field *info;
8076 : :
8077 [ # # # ]: 0 : switch (actions->type) {
8078 : : /*
8079 : : * mlx5 PMD hacks indirect action index directly to the action conf.
8080 : : * The rte_flow_conv() function copies the content from conf pointer.
8081 : : * Need to restore the indirect action index from action conf here.
8082 : : */
8083 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT:
8084 : 0 : at->actions[i].conf = ra[i].conf;
8085 : 0 : at->masks[i].conf = rm[i].conf;
8086 : 0 : break;
8087 : 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
8088 : 0 : info = actions->conf;
8089 [ # # # # ]: 0 : if ((info->dst.field == RTE_FLOW_FIELD_FLEX_ITEM &&
8090 : 0 : flow_hw_flex_item_acquire(dev, info->dst.flex_handle,
8091 : 0 : &at->flex_item)) ||
8092 [ # # # # ]: 0 : (info->src.field == RTE_FLOW_FIELD_FLEX_ITEM &&
8093 : 0 : flow_hw_flex_item_acquire(dev, info->src.flex_handle,
8094 : : &at->flex_item)))
8095 : 0 : goto error;
8096 : : break;
8097 : : default:
8098 : : break;
8099 : : }
8100 : : }
8101 : 0 : ret = flow_hw_parse_flow_actions_to_dr_actions(dev, at, action_types, &tmpl_flags);
8102 [ # # ]: 0 : if (ret)
8103 : 0 : goto error;
8104 : 0 : at->action_flags = action_flags;
8105 : : /* In non template mode there is no need to create the dr template. */
8106 [ # # ]: 0 : if (nt_mode)
8107 : : return at;
8108 : 0 : at->tmpl = mlx5dr_action_template_create(action_types, tmpl_flags);
8109 [ # # ]: 0 : if (!at->tmpl) {
8110 : 0 : DRV_LOG(ERR, "Failed to create DR action template: %d", rte_errno);
8111 : 0 : goto error;
8112 : : }
8113 : 0 : rte_atomic_fetch_add_explicit(&at->refcnt, 1, rte_memory_order_relaxed);
8114 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->flow_hw_at, at, next);
8115 : 0 : return at;
8116 : 0 : error:
8117 : : if (at) {
8118 : 0 : mlx5_free(at);
8119 : : }
8120 : 0 : rte_flow_error_set(error, rte_errno,
8121 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8122 : : "Failed to create action template");
8123 : 0 : return NULL;
8124 : : }
8125 : :
8126 : : /**
8127 : : * Create flow action template.
8128 : : *
8129 : : * @param[in] dev
8130 : : * Pointer to the rte_eth_dev structure.
8131 : : * @param[in] attr
8132 : : * Pointer to the action template attributes.
8133 : : * @param[in] actions
8134 : : * Associated actions (list terminated by the END action).
8135 : : * @param[in] masks
8136 : : * List of actions that marks which of the action's member is constant.
8137 : : * @param[out] error
8138 : : * Pointer to error structure.
8139 : : *
8140 : : * @return
8141 : : * Action template pointer on success, NULL otherwise and rte_errno is set.
8142 : : */
8143 : : static struct rte_flow_actions_template *
8144 : 0 : flow_hw_actions_template_create(struct rte_eth_dev *dev,
8145 : : const struct rte_flow_actions_template_attr *attr,
8146 : : const struct rte_flow_action actions[],
8147 : : const struct rte_flow_action masks[],
8148 : : struct rte_flow_error *error)
8149 : : {
8150 : 0 : return __flow_hw_actions_template_create(dev, attr, actions, masks, false, error);
8151 : : }
8152 : :
8153 : : /**
8154 : : * Destroy flow action template.
8155 : : *
8156 : : * @param[in] dev
8157 : : * Pointer to the rte_eth_dev structure.
8158 : : * @param[in] template
8159 : : * Pointer to the action template to be destroyed.
8160 : : * @param[out] error
8161 : : * Pointer to error structure.
8162 : : *
8163 : : * @return
8164 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
8165 : : */
8166 : : static int
8167 : 0 : flow_hw_actions_template_destroy(struct rte_eth_dev *dev,
8168 : : struct rte_flow_actions_template *template,
8169 : : struct rte_flow_error *error __rte_unused)
8170 : : {
8171 : : uint64_t flag = MLX5_FLOW_ACTION_IPV6_ROUTING_REMOVE |
8172 : : MLX5_FLOW_ACTION_IPV6_ROUTING_PUSH;
8173 : :
8174 [ # # ]: 0 : if (rte_atomic_load_explicit(&template->refcnt, rte_memory_order_relaxed) > 1) {
8175 : 0 : DRV_LOG(WARNING, "Action template %p is still in use.",
8176 : : (void *)template);
8177 : 0 : return rte_flow_error_set(error, EBUSY,
8178 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8179 : : NULL,
8180 : : "action template is in use");
8181 : : }
8182 [ # # ]: 0 : if (template->action_flags & flag)
8183 : 0 : mlx5_free_srh_flex_parser(dev);
8184 [ # # ]: 0 : LIST_REMOVE(template, next);
8185 : 0 : flow_hw_flex_item_release(dev, &template->flex_item);
8186 [ # # ]: 0 : if (template->tmpl)
8187 : 0 : mlx5dr_action_template_destroy(template->tmpl);
8188 : 0 : mlx5_free(template);
8189 : 0 : return 0;
8190 : : }
8191 : :
8192 : : static struct rte_flow_item *
8193 : 0 : flow_hw_prepend_item(const struct rte_flow_item *items,
8194 : : const uint32_t nb_items,
8195 : : const struct rte_flow_item *new_item,
8196 : : struct rte_flow_error *error)
8197 : : {
8198 : : struct rte_flow_item *copied_items;
8199 : : size_t size;
8200 : :
8201 : : /* Allocate new array of items. */
8202 : 0 : size = sizeof(*copied_items) * (nb_items + 1);
8203 : 0 : copied_items = mlx5_malloc(MLX5_MEM_ZERO, size, 0, rte_socket_id());
8204 [ # # ]: 0 : if (!copied_items) {
8205 : 0 : rte_flow_error_set(error, ENOMEM,
8206 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8207 : : NULL,
8208 : : "cannot allocate item template");
8209 : 0 : return NULL;
8210 : : }
8211 : : /* Put new item at the beginning and copy the rest. */
8212 : 0 : copied_items[0] = *new_item;
8213 [ # # ]: 0 : rte_memcpy(&copied_items[1], items, sizeof(*items) * nb_items);
8214 : : return copied_items;
8215 : : }
8216 : :
8217 : : static int
8218 : 0 : flow_hw_item_compare_field_validate(enum rte_flow_field_id arg_field,
8219 : : enum rte_flow_field_id base_field,
8220 : : struct rte_flow_error *error)
8221 : : {
8222 [ # # # ]: 0 : switch (arg_field) {
8223 : : case RTE_FLOW_FIELD_TAG:
8224 : : case RTE_FLOW_FIELD_META:
8225 : : case RTE_FLOW_FIELD_ESP_SEQ_NUM:
8226 : : break;
8227 : 0 : case RTE_FLOW_FIELD_RANDOM:
8228 [ # # ]: 0 : if (base_field == RTE_FLOW_FIELD_VALUE)
8229 : : return 0;
8230 : 0 : return rte_flow_error_set(error, EINVAL,
8231 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8232 : : NULL,
8233 : : "compare random is supported only with immediate value");
8234 : 0 : default:
8235 : 0 : return rte_flow_error_set(error, ENOTSUP,
8236 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8237 : : NULL,
8238 : : "compare item argument field is not supported");
8239 : : }
8240 [ # # ]: 0 : switch (base_field) {
8241 : : case RTE_FLOW_FIELD_TAG:
8242 : : case RTE_FLOW_FIELD_META:
8243 : : case RTE_FLOW_FIELD_VALUE:
8244 : : case RTE_FLOW_FIELD_ESP_SEQ_NUM:
8245 : : break;
8246 : 0 : default:
8247 : 0 : return rte_flow_error_set(error, ENOTSUP,
8248 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8249 : : NULL,
8250 : : "compare item base field is not supported");
8251 : : }
8252 : : return 0;
8253 : : }
8254 : :
8255 : : static inline uint32_t
8256 : : flow_hw_item_compare_width_supported(enum rte_flow_field_id field)
8257 : : {
8258 [ # # # ]: 0 : switch (field) {
8259 : : case RTE_FLOW_FIELD_TAG:
8260 : : case RTE_FLOW_FIELD_META:
8261 : : case RTE_FLOW_FIELD_ESP_SEQ_NUM:
8262 : : return 32;
8263 : 0 : case RTE_FLOW_FIELD_RANDOM:
8264 : 0 : return 16;
8265 : : default:
8266 : : break;
8267 : : }
8268 : 0 : return 0;
8269 : : }
8270 : :
8271 : : static int
8272 : 0 : flow_hw_validate_item_compare(const struct rte_flow_item *item,
8273 : : struct rte_flow_error *error)
8274 : : {
8275 : 0 : const struct rte_flow_item_compare *comp_m = item->mask;
8276 : 0 : const struct rte_flow_item_compare *comp_v = item->spec;
8277 : : int ret;
8278 : :
8279 [ # # ]: 0 : if (unlikely(!comp_m))
8280 : 0 : return rte_flow_error_set(error, EINVAL,
8281 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8282 : : NULL,
8283 : : "compare item mask is missing");
8284 [ # # ]: 0 : if (comp_m->width != UINT32_MAX)
8285 : 0 : return rte_flow_error_set(error, EINVAL,
8286 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8287 : : NULL,
8288 : : "compare item only support full mask");
8289 : 0 : ret = flow_hw_item_compare_field_validate(comp_m->a.field,
8290 : 0 : comp_m->b.field, error);
8291 [ # # ]: 0 : if (ret < 0)
8292 : : return ret;
8293 [ # # ]: 0 : if (comp_v) {
8294 : : uint32_t width;
8295 : :
8296 [ # # ]: 0 : if (comp_v->operation != comp_m->operation ||
8297 [ # # ]: 0 : comp_v->a.field != comp_m->a.field ||
8298 [ # # ]: 0 : comp_v->b.field != comp_m->b.field)
8299 : 0 : return rte_flow_error_set(error, EINVAL,
8300 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8301 : : NULL,
8302 : : "compare item spec/mask not matching");
8303 : : width = flow_hw_item_compare_width_supported(comp_v->a.field);
8304 : : MLX5_ASSERT(width > 0);
8305 [ # # ]: 0 : if ((comp_v->width & comp_m->width) != width)
8306 : 0 : return rte_flow_error_set(error, EINVAL,
8307 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8308 : : NULL,
8309 : : "compare item only support full mask");
8310 : : }
8311 : : return 0;
8312 : : }
8313 : :
8314 : : static inline int
8315 : : mlx5_hw_validate_item_nsh(struct rte_eth_dev *dev,
8316 : : const struct rte_flow_item *item,
8317 : : struct rte_flow_error *error)
8318 : : {
8319 : 0 : return mlx5_flow_validate_item_nsh(dev, item, error);
8320 : : }
8321 : :
8322 : : static bool
8323 : : mlx5_hw_flow_tunnel_ip_check(uint64_t last_item, uint64_t *item_flags)
8324 : : {
8325 : : bool tunnel;
8326 : :
8327 [ # # # # ]: 0 : if (last_item == MLX5_FLOW_LAYER_OUTER_L3_IPV4) {
8328 : : tunnel = true;
8329 : 0 : *item_flags |= MLX5_FLOW_LAYER_IPIP;
8330 : 0 : } else if (last_item == MLX5_FLOW_LAYER_OUTER_L3_IPV6 ||
8331 [ # # # # ]: 0 : last_item == MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT) {
8332 : : tunnel = true;
8333 : 0 : *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
8334 : : } else {
8335 : : tunnel = false;
8336 : : }
8337 : : return tunnel;
8338 : : }
8339 : :
8340 : : const struct rte_flow_item_ipv4 hws_nic_ipv4_mask = {
8341 : : .hdr = {
8342 : : .version = 0xf,
8343 : : .ihl = 0xf,
8344 : : .type_of_service = 0xff,
8345 : : .total_length = RTE_BE16(0xffff),
8346 : : .packet_id = RTE_BE16(0xffff),
8347 : : .fragment_offset = RTE_BE16(0xffff),
8348 : : .time_to_live = 0xff,
8349 : : .next_proto_id = 0xff,
8350 : : .src_addr = RTE_BE32(0xffffffff),
8351 : : .dst_addr = RTE_BE32(0xffffffff),
8352 : : },
8353 : : };
8354 : :
8355 : : const struct rte_flow_item_ipv6 hws_nic_ipv6_mask = {
8356 : : .hdr = {
8357 : : .vtc_flow = RTE_BE32(0xffffffff),
8358 : : .payload_len = RTE_BE16(0xffff),
8359 : : .proto = 0xff,
8360 : : .hop_limits = 0xff,
8361 : : .src_addr = RTE_IPV6_MASK_FULL,
8362 : : .dst_addr = RTE_IPV6_MASK_FULL,
8363 : : },
8364 : : .has_frag_ext = 1,
8365 : : };
8366 : :
8367 : : const struct rte_flow_item_ecpri hws_nic_ecpri_mask = {
8368 : : .hdr = {
8369 : : .common = {
8370 : : .u32 = RTE_BE32(0xffffffff),
8371 : : },
8372 : : .dummy[0] = 0xffffffff,
8373 : : },
8374 : : };
8375 : :
8376 : :
8377 : : static int
8378 : 0 : flow_hw_validate_item_ptype(const struct rte_flow_item *item,
8379 : : struct rte_flow_error *error)
8380 : : {
8381 : 0 : const struct rte_flow_item_ptype *ptype = item->mask;
8382 : :
8383 : : /* HWS does not allow empty PTYPE mask */
8384 [ # # ]: 0 : if (!ptype)
8385 : 0 : return rte_flow_error_set(error, EINVAL,
8386 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8387 : : NULL, "empty ptype mask");
8388 [ # # ]: 0 : if (!(ptype->packet_type &
8389 : : (RTE_PTYPE_L2_MASK | RTE_PTYPE_L3_MASK | RTE_PTYPE_L4_MASK |
8390 : : RTE_PTYPE_INNER_L2_MASK | RTE_PTYPE_INNER_L3_MASK |
8391 : : RTE_PTYPE_INNER_L4_MASK)))
8392 : 0 : return rte_flow_error_set(error, ENOTSUP,
8393 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8394 : : NULL, "ptype mask not supported");
8395 : : return 0;
8396 : : }
8397 : :
8398 : : struct mlx5_hw_pattern_validation_ctx {
8399 : : const struct rte_flow_item *geneve_item;
8400 : : const struct rte_flow_item *flex_item;
8401 : : };
8402 : :
8403 : : static int
8404 : 0 : __flow_hw_pattern_validate(struct rte_eth_dev *dev,
8405 : : const struct rte_flow_pattern_template_attr *attr,
8406 : : const struct rte_flow_item items[],
8407 : : uint64_t *item_flags,
8408 : : bool nt_flow,
8409 : : struct rte_flow_error *error)
8410 : : {
8411 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
8412 : : const struct rte_flow_item *item;
8413 : : const struct rte_flow_item *gtp_item = NULL;
8414 : : const struct rte_flow_item *gre_item = NULL;
8415 : 0 : const struct rte_flow_attr flow_attr = {
8416 : 0 : .ingress = attr->ingress,
8417 : 0 : .egress = attr->egress,
8418 : 0 : .transfer = attr->transfer
8419 : : };
8420 : : int ret, tag_idx;
8421 : : uint32_t tag_bitmap = 0;
8422 : : uint64_t last_item = 0;
8423 : :
8424 [ # # ]: 0 : if (!mlx5_hw_ctx_validate(dev, error))
8425 : 0 : return -rte_errno;
8426 [ # # ]: 0 : if (!attr->ingress && !attr->egress && !attr->transfer)
8427 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ATTR, NULL,
8428 : : "at least one of the direction attributes"
8429 : : " must be specified");
8430 [ # # ]: 0 : if (priv->sh->config.dv_esw_en) {
8431 : : MLX5_ASSERT(priv->master || priv->representor);
8432 [ # # ]: 0 : if (priv->master) {
8433 [ # # ]: 0 : if ((attr->ingress && attr->egress) ||
8434 [ # # ]: 0 : (attr->ingress && attr->transfer) ||
8435 [ # # ]: 0 : (attr->egress && attr->transfer))
8436 : 0 : return rte_flow_error_set(error, EINVAL,
8437 : : RTE_FLOW_ERROR_TYPE_ATTR, NULL,
8438 : : "only one direction attribute at once"
8439 : : " can be used on transfer proxy port");
8440 : : } else {
8441 [ # # ]: 0 : if (attr->transfer)
8442 : 0 : return rte_flow_error_set(error, EINVAL,
8443 : : RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER, NULL,
8444 : : "transfer attribute cannot be used with"
8445 : : " port representors");
8446 [ # # ]: 0 : if (attr->ingress && attr->egress)
8447 : 0 : return rte_flow_error_set(error, EINVAL,
8448 : : RTE_FLOW_ERROR_TYPE_ATTR, NULL,
8449 : : "ingress and egress direction attributes"
8450 : : " cannot be used at the same time on"
8451 : : " port representors");
8452 : : }
8453 : : } else {
8454 [ # # ]: 0 : if (attr->transfer)
8455 : 0 : return rte_flow_error_set(error, EINVAL,
8456 : : RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER, NULL,
8457 : : "transfer attribute cannot be used when"
8458 : : " E-Switch is disabled");
8459 : : }
8460 [ # # ]: 0 : for (item = items; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
8461 : 0 : bool tunnel = *item_flags & MLX5_FLOW_LAYER_TUNNEL;
8462 : :
8463 [ # # # # : 0 : switch ((int)item->type) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # #
# ]
8464 : 0 : case RTE_FLOW_ITEM_TYPE_PTYPE:
8465 : 0 : ret = flow_hw_validate_item_ptype(item, error);
8466 [ # # ]: 0 : if (ret)
8467 : 0 : return ret;
8468 : : last_item = MLX5_FLOW_ITEM_PTYPE;
8469 : : break;
8470 : 0 : case RTE_FLOW_ITEM_TYPE_TAG:
8471 : : {
8472 : 0 : const struct rte_flow_item_tag *tag =
8473 : : (const struct rte_flow_item_tag *)item->spec;
8474 : :
8475 [ # # ]: 0 : if (tag == NULL)
8476 : 0 : return rte_flow_error_set(error, EINVAL,
8477 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8478 : : NULL,
8479 : : "Tag spec is NULL");
8480 [ # # ]: 0 : if (tag->index >= MLX5_FLOW_HW_TAGS_MAX &&
8481 : : tag->index != RTE_PMD_MLX5_LINEAR_HASH_TAG_INDEX)
8482 : 0 : return rte_flow_error_set(error, EINVAL,
8483 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8484 : : NULL,
8485 : : "Invalid tag index");
8486 [ # # ]: 0 : tag_idx = flow_hw_get_reg_id(dev, RTE_FLOW_ITEM_TYPE_TAG, tag->index);
8487 [ # # ]: 0 : if (tag_idx == REG_NON)
8488 : 0 : return rte_flow_error_set(error, EINVAL,
8489 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8490 : : NULL,
8491 : : "Unsupported tag index");
8492 [ # # ]: 0 : if (tag_bitmap & (1 << tag_idx))
8493 : 0 : return rte_flow_error_set(error, EINVAL,
8494 : : RTE_FLOW_ERROR_TYPE_ITEM,
8495 : : NULL,
8496 : : "Duplicated tag index");
8497 : 0 : tag_bitmap |= 1 << tag_idx;
8498 : : last_item = MLX5_FLOW_ITEM_TAG;
8499 : 0 : break;
8500 : : }
8501 : 0 : case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
8502 : : {
8503 : 0 : const struct rte_flow_item_tag *tag =
8504 : : (const struct rte_flow_item_tag *)item->spec;
8505 : 0 : uint16_t regcs = (uint8_t)priv->sh->cdev->config.hca_attr.set_reg_c;
8506 : :
8507 [ # # ]: 0 : if (!((1 << (tag->index - REG_C_0)) & regcs))
8508 : 0 : return rte_flow_error_set(error, EINVAL,
8509 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8510 : : NULL,
8511 : : "Unsupported internal tag index");
8512 [ # # ]: 0 : if (tag_bitmap & (1 << tag->index))
8513 : 0 : return rte_flow_error_set(error, EINVAL,
8514 : : RTE_FLOW_ERROR_TYPE_ITEM,
8515 : : NULL,
8516 : : "Duplicated tag index");
8517 : 0 : tag_bitmap |= 1 << tag->index;
8518 : 0 : break;
8519 : : }
8520 : 0 : case RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT:
8521 [ # # # # ]: 0 : if (attr->ingress && priv->sh->config.repr_matching)
8522 : 0 : return rte_flow_error_set(error, EINVAL,
8523 : : RTE_FLOW_ERROR_TYPE_ITEM, NULL,
8524 : : "represented port item cannot be used"
8525 : : " when ingress attribute is set");
8526 [ # # ]: 0 : if (attr->egress)
8527 : 0 : return rte_flow_error_set(error, EINVAL,
8528 : : RTE_FLOW_ERROR_TYPE_ITEM, NULL,
8529 : : "represented port item cannot be used"
8530 : : " when egress attribute is set");
8531 : : last_item = MLX5_FLOW_ITEM_REPRESENTED_PORT;
8532 : : break;
8533 : 0 : case RTE_FLOW_ITEM_TYPE_META:
8534 : : /* ingress + group 0 is not supported */
8535 : 0 : *item_flags |= MLX5_FLOW_ITEM_METADATA;
8536 : 0 : break;
8537 : : case RTE_FLOW_ITEM_TYPE_METER_COLOR:
8538 : : {
8539 : : int reg = flow_hw_get_reg_id(dev,
8540 : : RTE_FLOW_ITEM_TYPE_METER_COLOR,
8541 : : 0);
8542 [ # # ]: 0 : if (reg == REG_NON)
8543 : 0 : return rte_flow_error_set(error, EINVAL,
8544 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8545 : : NULL,
8546 : : "Unsupported meter color register");
8547 [ # # ]: 0 : if (*item_flags &
8548 : : (MLX5_FLOW_ITEM_QUOTA | MLX5_FLOW_LAYER_ASO_CT))
8549 : 0 : return rte_flow_error_set
8550 : : (error, EINVAL,
8551 : : RTE_FLOW_ERROR_TYPE_ITEM, NULL, "Only one ASO item is supported");
8552 : : last_item = MLX5_FLOW_ITEM_METER_COLOR;
8553 : : break;
8554 : : }
8555 : 0 : case RTE_FLOW_ITEM_TYPE_AGGR_AFFINITY:
8556 : : {
8557 [ # # ]: 0 : if (!priv->sh->lag_rx_port_affinity_en)
8558 : 0 : return rte_flow_error_set(error, EINVAL,
8559 : : RTE_FLOW_ERROR_TYPE_ITEM, NULL,
8560 : : "Unsupported aggregated affinity with Older FW");
8561 [ # # # # : 0 : if ((attr->transfer && priv->fdb_def_rule) || attr->egress)
# # ]
8562 : 0 : return rte_flow_error_set(error, EINVAL,
8563 : : RTE_FLOW_ERROR_TYPE_ITEM, NULL,
8564 : : "Aggregated affinity item not supported"
8565 : : " with egress or transfer"
8566 : : " attribute");
8567 : : last_item = MLX5_FLOW_ITEM_AGGR_AFFINITY;
8568 : : break;
8569 : : }
8570 : 0 : case RTE_FLOW_ITEM_TYPE_GENEVE:
8571 : : last_item = MLX5_FLOW_LAYER_GENEVE;
8572 : 0 : break;
8573 : 0 : case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
8574 : : {
8575 : : last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
8576 : : /*
8577 : : * For non template the parser is internally created before
8578 : : * the flow creation.
8579 : : */
8580 [ # # ]: 0 : if (!nt_flow) {
8581 : 0 : ret = mlx5_flow_geneve_tlv_option_validate(priv, item,
8582 : : error);
8583 [ # # ]: 0 : if (ret < 0)
8584 : 0 : return ret;
8585 : : }
8586 : : break;
8587 : : }
8588 : 0 : case RTE_FLOW_ITEM_TYPE_COMPARE:
8589 : : {
8590 : : last_item = MLX5_FLOW_ITEM_COMPARE;
8591 : 0 : ret = flow_hw_validate_item_compare(item, error);
8592 [ # # ]: 0 : if (ret)
8593 : 0 : return ret;
8594 : : break;
8595 : : }
8596 : 0 : case RTE_FLOW_ITEM_TYPE_ETH:
8597 : 0 : ret = mlx5_flow_validate_item_eth(dev, item,
8598 : : *item_flags,
8599 : : true, error);
8600 [ # # ]: 0 : if (ret < 0)
8601 : 0 : return ret;
8602 [ # # ]: 0 : last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
8603 : : MLX5_FLOW_LAYER_OUTER_L2;
8604 : : break;
8605 : 0 : case RTE_FLOW_ITEM_TYPE_VLAN:
8606 : 0 : ret = mlx5_flow_dv_validate_item_vlan(item, *item_flags,
8607 : : dev, error);
8608 [ # # ]: 0 : if (ret < 0)
8609 : 0 : return ret;
8610 [ # # ]: 0 : last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
8611 : : MLX5_FLOW_LAYER_OUTER_VLAN;
8612 : : break;
8613 : : case RTE_FLOW_ITEM_TYPE_IPV4:
8614 : 0 : tunnel |= mlx5_hw_flow_tunnel_ip_check(last_item,
8615 : : item_flags);
8616 : 0 : ret = mlx5_flow_dv_validate_item_ipv4(dev, item,
8617 : : *item_flags,
8618 : : last_item, 0,
8619 : : &hws_nic_ipv4_mask,
8620 : : error);
8621 [ # # ]: 0 : if (ret)
8622 : 0 : return ret;
8623 [ # # ]: 0 : last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
8624 : : MLX5_FLOW_LAYER_OUTER_L3_IPV4;
8625 : : break;
8626 : : case RTE_FLOW_ITEM_TYPE_IPV6:
8627 : 0 : tunnel |= mlx5_hw_flow_tunnel_ip_check(last_item,
8628 : : item_flags);
8629 : 0 : ret = mlx5_flow_validate_item_ipv6(dev, item,
8630 : : *item_flags,
8631 : : last_item, 0,
8632 : : &hws_nic_ipv6_mask,
8633 : : error);
8634 [ # # ]: 0 : if (ret < 0)
8635 : 0 : return ret;
8636 [ # # ]: 0 : last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
8637 : : MLX5_FLOW_LAYER_OUTER_L3_IPV6;
8638 : : break;
8639 : 0 : case RTE_FLOW_ITEM_TYPE_UDP:
8640 : 0 : ret = mlx5_flow_validate_item_udp(dev, item,
8641 : : *item_flags,
8642 : : 0xff, error);
8643 [ # # ]: 0 : if (ret)
8644 : 0 : return ret;
8645 [ # # ]: 0 : last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
8646 : : MLX5_FLOW_LAYER_OUTER_L4_UDP;
8647 : : break;
8648 : 0 : case RTE_FLOW_ITEM_TYPE_TCP:
8649 : 0 : ret = mlx5_flow_validate_item_tcp
8650 : : (dev, item, *item_flags,
8651 : : 0xff, &nic_tcp_mask, error);
8652 [ # # ]: 0 : if (ret < 0)
8653 : 0 : return ret;
8654 [ # # ]: 0 : last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
8655 : : MLX5_FLOW_LAYER_OUTER_L4_TCP;
8656 : : break;
8657 : 0 : case RTE_FLOW_ITEM_TYPE_GTP:
8658 : : gtp_item = item;
8659 : 0 : ret = mlx5_flow_dv_validate_item_gtp(dev, gtp_item,
8660 : : *item_flags, error);
8661 [ # # ]: 0 : if (ret < 0)
8662 : 0 : return ret;
8663 : : last_item = MLX5_FLOW_LAYER_GTP;
8664 : : break;
8665 : 0 : case RTE_FLOW_ITEM_TYPE_GTP_PSC:
8666 : 0 : ret = mlx5_flow_dv_validate_item_gtp_psc(dev, item,
8667 : : last_item,
8668 : : gtp_item,
8669 : : false, error);
8670 [ # # ]: 0 : if (ret < 0)
8671 : 0 : return ret;
8672 : : last_item = MLX5_FLOW_LAYER_GTP_PSC;
8673 : : break;
8674 : 0 : case RTE_FLOW_ITEM_TYPE_VXLAN:
8675 : 0 : ret = mlx5_flow_validate_item_vxlan(dev, 0, item,
8676 : : *item_flags,
8677 : : false, error);
8678 [ # # ]: 0 : if (ret < 0)
8679 : 0 : return ret;
8680 : : last_item = MLX5_FLOW_LAYER_VXLAN;
8681 : : break;
8682 : 0 : case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
8683 : 0 : ret = mlx5_flow_validate_item_vxlan_gpe(item,
8684 : : *item_flags,
8685 : : dev, error);
8686 [ # # ]: 0 : if (ret < 0)
8687 : 0 : return ret;
8688 : : last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
8689 : : break;
8690 : 0 : case RTE_FLOW_ITEM_TYPE_MPLS:
8691 : 0 : ret = mlx5_flow_validate_item_mpls(dev, item,
8692 : : *item_flags,
8693 : : last_item, error);
8694 [ # # ]: 0 : if (ret < 0)
8695 : 0 : return ret;
8696 : : last_item = MLX5_FLOW_LAYER_MPLS;
8697 : : break;
8698 : 0 : case MLX5_RTE_FLOW_ITEM_TYPE_SQ:
8699 : : case RTE_FLOW_ITEM_TYPE_TX_QUEUE:
8700 : : last_item = MLX5_FLOW_ITEM_SQ;
8701 : 0 : break;
8702 : 0 : case RTE_FLOW_ITEM_TYPE_GRE:
8703 : 0 : ret = mlx5_flow_validate_item_gre(dev, item,
8704 : : *item_flags,
8705 : : 0xff, error);
8706 [ # # ]: 0 : if (ret < 0)
8707 : 0 : return ret;
8708 : : gre_item = item;
8709 : : last_item = MLX5_FLOW_LAYER_GRE;
8710 : : break;
8711 : 0 : case RTE_FLOW_ITEM_TYPE_GRE_KEY:
8712 [ # # ]: 0 : if (!(*item_flags & MLX5_FLOW_LAYER_GRE))
8713 : 0 : return rte_flow_error_set
8714 : : (error, EINVAL,
8715 : : RTE_FLOW_ERROR_TYPE_ITEM, item, "GRE item is missing");
8716 : 0 : ret = mlx5_flow_validate_item_gre_key
8717 : : (dev, item, *item_flags, gre_item, error);
8718 [ # # ]: 0 : if (ret < 0)
8719 : 0 : return ret;
8720 : : last_item = MLX5_FLOW_LAYER_GRE_KEY;
8721 : : break;
8722 : 0 : case RTE_FLOW_ITEM_TYPE_GRE_OPTION:
8723 [ # # ]: 0 : if (!(*item_flags & MLX5_FLOW_LAYER_GRE))
8724 : 0 : return rte_flow_error_set
8725 : : (error, EINVAL,
8726 : : RTE_FLOW_ERROR_TYPE_ITEM, item, "GRE item is missing");
8727 : 0 : ret = mlx5_flow_validate_item_gre_option(dev, item,
8728 : : *item_flags,
8729 : : &flow_attr,
8730 : : gre_item,
8731 : : error);
8732 [ # # ]: 0 : if (ret < 0)
8733 : 0 : return ret;
8734 : : last_item = MLX5_FLOW_LAYER_GRE;
8735 : : break;
8736 : 0 : case RTE_FLOW_ITEM_TYPE_NVGRE:
8737 : 0 : ret = mlx5_flow_validate_item_nvgre(dev, item,
8738 : : *item_flags, 0xff,
8739 : : error);
8740 [ # # ]: 0 : if (ret)
8741 : 0 : return ret;
8742 : : last_item = MLX5_FLOW_LAYER_NVGRE;
8743 : : break;
8744 : 0 : case RTE_FLOW_ITEM_TYPE_ICMP:
8745 : 0 : ret = mlx5_flow_validate_item_icmp(dev, item,
8746 : : *item_flags, 0xff,
8747 : : error);
8748 [ # # ]: 0 : if (ret < 0)
8749 : 0 : return ret;
8750 : : last_item = MLX5_FLOW_LAYER_ICMP;
8751 : : break;
8752 : 0 : case RTE_FLOW_ITEM_TYPE_ICMP6:
8753 : 0 : ret = mlx5_flow_validate_item_icmp6(dev, item,
8754 : : *item_flags, 0xff,
8755 : : error);
8756 [ # # ]: 0 : if (ret < 0)
8757 : 0 : return ret;
8758 : : last_item = MLX5_FLOW_LAYER_ICMP6;
8759 : : break;
8760 : 0 : case RTE_FLOW_ITEM_TYPE_ICMP6_ECHO_REQUEST:
8761 : : case RTE_FLOW_ITEM_TYPE_ICMP6_ECHO_REPLY:
8762 : 0 : ret = mlx5_flow_validate_item_icmp6_echo(dev, item,
8763 : : *item_flags,
8764 : : 0xff, error);
8765 [ # # ]: 0 : if (ret < 0)
8766 : 0 : return ret;
8767 : : last_item = MLX5_FLOW_LAYER_ICMP6;
8768 : : break;
8769 : 0 : case RTE_FLOW_ITEM_TYPE_CONNTRACK:
8770 [ # # ]: 0 : if (*item_flags &
8771 : : (MLX5_FLOW_ITEM_QUOTA | MLX5_FLOW_LAYER_ASO_CT))
8772 : 0 : return rte_flow_error_set
8773 : : (error, EINVAL,
8774 : : RTE_FLOW_ERROR_TYPE_ITEM, NULL, "Only one ASO item is supported");
8775 : 0 : ret = mlx5_flow_dv_validate_item_aso_ct(dev, item,
8776 : : item_flags,
8777 : : error);
8778 [ # # ]: 0 : if (ret < 0)
8779 : 0 : return ret;
8780 : : break;
8781 : 0 : case RTE_FLOW_ITEM_TYPE_QUOTA:
8782 [ # # ]: 0 : if (*item_flags &
8783 : : (MLX5_FLOW_ITEM_METER_COLOR |
8784 : : MLX5_FLOW_LAYER_ASO_CT))
8785 : 0 : return rte_flow_error_set
8786 : : (error, EINVAL,
8787 : : RTE_FLOW_ERROR_TYPE_ITEM, NULL, "Only one ASO item is supported");
8788 : : last_item = MLX5_FLOW_ITEM_QUOTA;
8789 : : break;
8790 : 0 : case RTE_FLOW_ITEM_TYPE_ESP:
8791 : 0 : ret = mlx5_flow_os_validate_item_esp(dev, item,
8792 : : *item_flags, 0xff,
8793 : : error);
8794 [ # # ]: 0 : if (ret < 0)
8795 : 0 : return ret;
8796 : : last_item = MLX5_FLOW_ITEM_ESP;
8797 : : break;
8798 : 0 : case RTE_FLOW_ITEM_TYPE_IPV6_ROUTING_EXT:
8799 : : last_item = tunnel ?
8800 [ # # ]: 0 : MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT :
8801 : : MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT;
8802 : : break;
8803 : 0 : case RTE_FLOW_ITEM_TYPE_FLEX: {
8804 : 0 : enum rte_flow_item_flex_tunnel_mode tunnel_mode = FLEX_TUNNEL_MODE_SINGLE;
8805 : :
8806 : 0 : ret = mlx5_flex_get_tunnel_mode(item, &tunnel_mode);
8807 [ # # ]: 0 : if (ret < 0)
8808 : 0 : return rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_ITEM,
8809 : : item, "Unable to get flex item mode");
8810 [ # # ]: 0 : if (tunnel_mode == FLEX_TUNNEL_MODE_TUNNEL)
8811 : : last_item = MLX5_FLOW_ITEM_FLEX_TUNNEL;
8812 : : else
8813 : : last_item = tunnel ?
8814 [ # # ]: 0 : MLX5_FLOW_ITEM_INNER_FLEX :
8815 : : MLX5_FLOW_ITEM_OUTER_FLEX;
8816 : 0 : break;
8817 : : }
8818 : 0 : case RTE_FLOW_ITEM_TYPE_RANDOM:
8819 : : last_item = MLX5_FLOW_ITEM_RANDOM;
8820 : 0 : break;
8821 : 0 : case RTE_FLOW_ITEM_TYPE_NSH:
8822 : : last_item = MLX5_FLOW_ITEM_NSH;
8823 : : ret = mlx5_hw_validate_item_nsh(dev, item, error);
8824 [ # # ]: 0 : if (ret < 0)
8825 : 0 : return ret;
8826 : : break;
8827 : : case RTE_FLOW_ITEM_TYPE_INTEGRITY:
8828 : : /*
8829 : : * Integrity flow item validation require access to
8830 : : * both item mask and spec.
8831 : : * Current HWS model allows item mask in pattern
8832 : : * template and item spec in flow rule.
8833 : : */
8834 : : break;
8835 : 0 : case RTE_FLOW_ITEM_TYPE_ECPRI:
8836 : 0 : ret = mlx5_flow_validate_item_ecpri(dev, item, *item_flags, last_item,
8837 : : RTE_ETHER_TYPE_ECPRI,
8838 : : &hws_nic_ecpri_mask, error);
8839 [ # # ]: 0 : if (ret < 0)
8840 : 0 : return ret;
8841 : 0 : *item_flags |= MLX5_FLOW_LAYER_ECPRI;
8842 : 0 : break;
8843 : : case RTE_FLOW_ITEM_TYPE_IB_BTH:
8844 : : case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
8845 : : case RTE_FLOW_ITEM_TYPE_VOID:
8846 : : case RTE_FLOW_ITEM_TYPE_END:
8847 : : break;
8848 : 0 : default:
8849 : 0 : return rte_flow_error_set(error, EINVAL,
8850 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8851 : : NULL,
8852 : : "Unsupported item type");
8853 : : }
8854 : 0 : *item_flags |= last_item;
8855 : : }
8856 : 0 : return 1 + RTE_PTR_DIFF(item, items) / sizeof(item[0]);
8857 : : }
8858 : :
8859 : : static int
8860 : 0 : flow_hw_pattern_validate(struct rte_eth_dev *dev,
8861 : : const struct rte_flow_pattern_template_attr *attr,
8862 : : const struct rte_flow_item items[],
8863 : : uint64_t *item_flags,
8864 : : struct rte_flow_error *error)
8865 : : {
8866 : 0 : return __flow_hw_pattern_validate(dev, attr, items, item_flags, false, error);
8867 : : }
8868 : :
8869 : : /*
8870 : : * Verify that the tested flow patterns fits STE size limit in HWS group.
8871 : : *
8872 : : *
8873 : : * Return values:
8874 : : * 0 : Tested patterns fit STE size limit
8875 : : * -EINVAL : Invalid parameters detected
8876 : : * -E2BIG : Tested patterns exceed STE size limit
8877 : : */
8878 : : static int
8879 : 0 : pattern_template_validate(struct rte_eth_dev *dev,
8880 : : struct rte_flow_pattern_template *pt[],
8881 : : uint32_t pt_num,
8882 : : struct rte_flow_error *error)
8883 : : {
8884 : 0 : struct mlx5_flow_template_table_cfg tbl_cfg = {
8885 : : .attr = {
8886 : : .nb_flows = 64,
8887 : : .insertion_type = RTE_FLOW_TABLE_INSERTION_TYPE_PATTERN,
8888 : : .hash_func = RTE_FLOW_TABLE_HASH_FUNC_DEFAULT,
8889 : : .flow_attr = {
8890 : : .group = 1,
8891 : 0 : .ingress = pt[0]->attr.ingress,
8892 : 0 : .egress = pt[0]->attr.egress,
8893 : 0 : .transfer = pt[0]->attr.transfer
8894 : : }
8895 : : }
8896 : : };
8897 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
8898 : : struct rte_flow_actions_template *action_template;
8899 : : struct rte_flow_template_table *tmpl_tbl;
8900 : : int ret;
8901 : :
8902 [ # # ]: 0 : if (pt[0]->attr.ingress) {
8903 : 0 : action_template =
8904 : 0 : priv->action_template_drop[MLX5DR_TABLE_TYPE_NIC_RX];
8905 [ # # ]: 0 : } else if (pt[0]->attr.egress) {
8906 : 0 : action_template =
8907 : 0 : priv->action_template_drop[MLX5DR_TABLE_TYPE_NIC_TX];
8908 [ # # ]: 0 : } else if (pt[0]->attr.transfer) {
8909 : 0 : action_template =
8910 : 0 : priv->action_template_drop[MLX5DR_TABLE_TYPE_FDB];
8911 : : } else {
8912 : : ret = EINVAL;
8913 : 0 : goto end;
8914 : : }
8915 : :
8916 [ # # ]: 0 : if (pt[0]->item_flags & MLX5_FLOW_ITEM_COMPARE)
8917 : 0 : tbl_cfg.attr.nb_flows = 1;
8918 : 0 : tmpl_tbl = flow_hw_table_create(dev, &tbl_cfg, pt, pt_num,
8919 : : &action_template, 1, error);
8920 [ # # ]: 0 : if (tmpl_tbl) {
8921 : : ret = 0;
8922 : 0 : flow_hw_table_destroy(dev, tmpl_tbl, error);
8923 : : } else {
8924 [ # # # ]: 0 : switch (rte_errno) {
8925 : : case E2BIG:
8926 : : ret = E2BIG;
8927 : : break;
8928 : : case ENOTSUP:
8929 : : ret = EINVAL;
8930 : : break;
8931 : : default:
8932 : : ret = 0;
8933 : : break;
8934 : : }
8935 : : }
8936 : : end:
8937 : : if (ret)
8938 : 0 : rte_flow_error_set(error, ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8939 : : NULL, "failed to validate pattern template");
8940 : 0 : return -ret;
8941 : : }
8942 : :
8943 : : /**
8944 : : * Create flow item template.
8945 : : *
8946 : : * @param[in] dev
8947 : : * Pointer to the rte_eth_dev structure.
8948 : : * @param[in] attr
8949 : : * Pointer to the item template attributes.
8950 : : * @param[in] items
8951 : : * The template item pattern.
8952 : : * @param[out] error
8953 : : * Pointer to error structure.
8954 : : *
8955 : : * @return
8956 : : * Item template pointer on success, NULL otherwise and rte_errno is set.
8957 : : */
8958 : : static struct rte_flow_pattern_template *
8959 : 0 : flow_hw_pattern_template_create(struct rte_eth_dev *dev,
8960 : : const struct rte_flow_pattern_template_attr *attr,
8961 : : const struct rte_flow_item items[],
8962 : : struct rte_flow_error *error)
8963 : : {
8964 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
8965 : : struct rte_flow_pattern_template *it;
8966 : : struct rte_flow_item *copied_items = NULL;
8967 : : const struct rte_flow_item *tmpl_items;
8968 : 0 : uint64_t orig_item_nb, item_flags = 0;
8969 : 0 : struct rte_flow_item port = {
8970 : : .type = RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT,
8971 : : .mask = &rte_flow_item_ethdev_mask,
8972 : : };
8973 : 0 : struct rte_flow_item_tag tag_v = {
8974 : : .data = 0,
8975 : : .index = REG_C_0,
8976 : : };
8977 : 0 : struct rte_flow_item_tag tag_m = {
8978 : : .data = flow_hw_tx_tag_regc_mask(dev),
8979 : : .index = 0xff,
8980 : : };
8981 : 0 : struct rte_flow_item tag = {
8982 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_TAG,
8983 : : .spec = &tag_v,
8984 : : .mask = &tag_m,
8985 : : .last = NULL
8986 : : };
8987 : : int it_items_size;
8988 : : unsigned int i = 0;
8989 : : int rc;
8990 : :
8991 : : /* Validate application items only */
8992 : : rc = flow_hw_pattern_validate(dev, attr, items, &item_flags, error);
8993 [ # # ]: 0 : if (rc < 0)
8994 : : return NULL;
8995 : 0 : orig_item_nb = rc;
8996 [ # # # # ]: 0 : if (priv->sh->config.dv_esw_en &&
8997 : : priv->sh->config.repr_matching &&
8998 [ # # ]: 0 : attr->ingress && !attr->egress && !attr->transfer) {
8999 : 0 : copied_items = flow_hw_prepend_item(items, orig_item_nb, &port, error);
9000 [ # # ]: 0 : if (!copied_items)
9001 : : return NULL;
9002 : : tmpl_items = copied_items;
9003 [ # # # # ]: 0 : } else if (priv->sh->config.dv_esw_en &&
9004 : : priv->sh->config.repr_matching &&
9005 [ # # ]: 0 : !attr->ingress && attr->egress && !attr->transfer) {
9006 [ # # ]: 0 : if (item_flags & MLX5_FLOW_ITEM_SQ) {
9007 : 0 : DRV_LOG(DEBUG, "Port %u omitting implicit REG_C_0 match for egress "
9008 : : "pattern template", dev->data->port_id);
9009 : : tmpl_items = items;
9010 : 0 : goto setup_pattern_template;
9011 : : }
9012 : 0 : copied_items = flow_hw_prepend_item(items, orig_item_nb, &tag, error);
9013 [ # # ]: 0 : if (!copied_items)
9014 : : return NULL;
9015 : : tmpl_items = copied_items;
9016 : : } else {
9017 : : tmpl_items = items;
9018 : : }
9019 : 0 : setup_pattern_template:
9020 : 0 : it = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*it), 0, rte_socket_id());
9021 [ # # ]: 0 : if (!it) {
9022 : 0 : rte_flow_error_set(error, ENOMEM,
9023 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9024 : : NULL,
9025 : : "cannot allocate item template");
9026 : 0 : goto error;
9027 : : }
9028 : 0 : it->attr = *attr;
9029 : 0 : it->item_flags = item_flags;
9030 : 0 : it->orig_item_nb = orig_item_nb;
9031 : 0 : it_items_size = rte_flow_conv(RTE_FLOW_CONV_OP_PATTERN, NULL, 0, tmpl_items, error);
9032 [ # # ]: 0 : if (it_items_size <= 0) {
9033 : 0 : rte_flow_error_set(error, ENOMEM,
9034 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9035 : : NULL,
9036 : : "Failed to determine buffer size for pattern");
9037 : 0 : goto error;
9038 : : }
9039 : 0 : it_items_size = RTE_ALIGN(it_items_size, 16);
9040 : 0 : it->items = mlx5_malloc(MLX5_MEM_ZERO, it_items_size, 0, rte_dev_numa_node(dev->device));
9041 [ # # ]: 0 : if (it->items == NULL) {
9042 : 0 : rte_flow_error_set(error, ENOMEM,
9043 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9044 : : NULL,
9045 : : "Cannot allocate memory for pattern");
9046 : 0 : goto error;
9047 : : }
9048 : 0 : rc = rte_flow_conv(RTE_FLOW_CONV_OP_PATTERN, it->items, it_items_size, tmpl_items, error);
9049 [ # # ]: 0 : if (rc <= 0) {
9050 : 0 : rte_flow_error_set(error, ENOMEM,
9051 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9052 : : NULL,
9053 : : "Failed to store pattern");
9054 : 0 : goto error;
9055 : : }
9056 : 0 : it->mt = mlx5dr_match_template_create(tmpl_items, attr->relaxed_matching);
9057 [ # # ]: 0 : if (!it->mt) {
9058 : 0 : rte_flow_error_set(error, rte_errno,
9059 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9060 : : NULL,
9061 : : "cannot create match template");
9062 : 0 : goto error;
9063 : : }
9064 [ # # ]: 0 : if (copied_items) {
9065 [ # # ]: 0 : if (attr->ingress)
9066 : 0 : it->implicit_port = true;
9067 [ # # ]: 0 : else if (attr->egress)
9068 : 0 : it->implicit_tag = true;
9069 : 0 : mlx5_free(copied_items);
9070 : : copied_items = NULL;
9071 : : }
9072 : : /* Either inner or outer, can't both. */
9073 [ # # ]: 0 : if (it->item_flags & (MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT |
9074 : : MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT)) {
9075 [ # # ]: 0 : if (((it->item_flags & MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT) &&
9076 [ # # ]: 0 : (it->item_flags & MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT)) ||
9077 : 0 : (mlx5_alloc_srh_flex_parser(dev))) {
9078 : 0 : rte_flow_error_set(error, rte_errno,
9079 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9080 : : "cannot create IPv6 routing extension support");
9081 : 0 : goto error;
9082 : : }
9083 : : }
9084 [ # # ]: 0 : if (it->item_flags & MLX5_FLOW_ITEM_FLEX) {
9085 [ # # ]: 0 : for (i = 0; items[i].type != RTE_FLOW_ITEM_TYPE_END; i++) {
9086 : 0 : const struct rte_flow_item_flex *spec = items[i].spec;
9087 : : struct rte_flow_item_flex_handle *handle;
9088 : :
9089 [ # # ]: 0 : if (items[i].type != RTE_FLOW_ITEM_TYPE_FLEX)
9090 : 0 : continue;
9091 : 0 : handle = spec->handle;
9092 [ # # ]: 0 : if (flow_hw_flex_item_acquire(dev, handle,
9093 : 0 : &it->flex_item)) {
9094 : 0 : rte_flow_error_set(error, EINVAL,
9095 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9096 : : NULL, "cannot create hw FLEX item");
9097 : 0 : goto error;
9098 : : }
9099 : : }
9100 : : }
9101 [ # # ]: 0 : if (it->item_flags & MLX5_FLOW_LAYER_GENEVE_OPT) {
9102 [ # # ]: 0 : for (i = 0; items[i].type != RTE_FLOW_ITEM_TYPE_END; i++) {
9103 : 0 : const struct rte_flow_item_geneve_opt *spec =
9104 : : items[i].spec;
9105 : :
9106 [ # # ]: 0 : if (items[i].type != RTE_FLOW_ITEM_TYPE_GENEVE_OPT)
9107 : 0 : continue;
9108 [ # # ]: 0 : if (mlx5_geneve_tlv_option_register(priv, spec,
9109 : 0 : &it->geneve_opt_mng)) {
9110 : 0 : rte_flow_error_set(error, EINVAL,
9111 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9112 : : NULL, "cannot register GENEVE TLV option");
9113 : 0 : goto error;
9114 : : }
9115 : : }
9116 : : }
9117 : 0 : rte_atomic_fetch_add_explicit(&it->refcnt, 1, rte_memory_order_relaxed);
9118 : 0 : rc = pattern_template_validate(dev, &it, 1, error);
9119 [ # # ]: 0 : if (rc)
9120 : 0 : goto error;
9121 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->flow_hw_itt, it, next);
9122 : 0 : return it;
9123 : 0 : error:
9124 [ # # ]: 0 : if (it) {
9125 [ # # ]: 0 : if (it->flex_item)
9126 : 0 : flow_hw_flex_item_release(dev, &it->flex_item);
9127 [ # # ]: 0 : if (it->geneve_opt_mng.nb_options)
9128 : 0 : mlx5_geneve_tlv_options_unregister(priv, &it->geneve_opt_mng);
9129 [ # # ]: 0 : if (it->mt)
9130 : 0 : claim_zero(mlx5dr_match_template_destroy(it->mt));
9131 : 0 : mlx5_free(it->items);
9132 : 0 : mlx5_free(it);
9133 : : }
9134 [ # # ]: 0 : if (copied_items)
9135 : 0 : mlx5_free(copied_items);
9136 : : return NULL;
9137 : : }
9138 : :
9139 : : /**
9140 : : * Destroy flow item template.
9141 : : *
9142 : : * @param[in] dev
9143 : : * Pointer to the rte_eth_dev structure.
9144 : : * @param[in] template
9145 : : * Pointer to the item template to be destroyed.
9146 : : * @param[out] error
9147 : : * Pointer to error structure.
9148 : : *
9149 : : * @return
9150 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
9151 : : */
9152 : : static int
9153 : 0 : flow_hw_pattern_template_destroy(struct rte_eth_dev *dev,
9154 : : struct rte_flow_pattern_template *template,
9155 : : struct rte_flow_error *error __rte_unused)
9156 : : {
9157 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
9158 : :
9159 [ # # ]: 0 : if (rte_atomic_load_explicit(&template->refcnt, rte_memory_order_relaxed) > 1) {
9160 : 0 : DRV_LOG(WARNING, "Item template %p is still in use.",
9161 : : (void *)template);
9162 : 0 : return rte_flow_error_set(error, EBUSY,
9163 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9164 : : NULL,
9165 : : "item template is in use");
9166 : : }
9167 [ # # ]: 0 : if (template->item_flags & (MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT |
9168 : : MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT))
9169 : 0 : mlx5_free_srh_flex_parser(dev);
9170 [ # # ]: 0 : LIST_REMOVE(template, next);
9171 : 0 : flow_hw_flex_item_release(dev, &template->flex_item);
9172 : 0 : mlx5_geneve_tlv_options_unregister(priv, &template->geneve_opt_mng);
9173 : 0 : claim_zero(mlx5dr_match_template_destroy(template->mt));
9174 : 0 : mlx5_free(template->items);
9175 : 0 : mlx5_free(template);
9176 : 0 : return 0;
9177 : : }
9178 : :
9179 : : /*
9180 : : * Get information about HWS pre-configurable resources.
9181 : : *
9182 : : * @param[in] dev
9183 : : * Pointer to the rte_eth_dev structure.
9184 : : * @param[out] port_info
9185 : : * Pointer to port information.
9186 : : * @param[out] queue_info
9187 : : * Pointer to queue information.
9188 : : * @param[out] error
9189 : : * Pointer to error structure.
9190 : : *
9191 : : * @return
9192 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
9193 : : */
9194 : : static int
9195 : 0 : flow_hw_info_get(struct rte_eth_dev *dev,
9196 : : struct rte_flow_port_info *port_info,
9197 : : struct rte_flow_queue_info *queue_info,
9198 : : struct rte_flow_error *error __rte_unused)
9199 : : {
9200 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
9201 : 0 : uint16_t port_id = dev->data->port_id;
9202 : : struct rte_mtr_capabilities mtr_cap;
9203 : : int ret;
9204 : :
9205 : : memset(port_info, 0, sizeof(*port_info));
9206 : : /* Queue size is unlimited from low-level. */
9207 : 0 : port_info->max_nb_queues = UINT32_MAX;
9208 : 0 : queue_info->max_size = UINT32_MAX;
9209 : :
9210 : : memset(&mtr_cap, 0, sizeof(struct rte_mtr_capabilities));
9211 : 0 : ret = rte_mtr_capabilities_get(port_id, &mtr_cap, NULL);
9212 [ # # ]: 0 : if (!ret)
9213 : 0 : port_info->max_nb_meters = mtr_cap.n_max;
9214 : 0 : port_info->max_nb_counters = priv->sh->hws_max_nb_counters;
9215 : 0 : port_info->max_nb_aging_objects = port_info->max_nb_counters;
9216 : 0 : return 0;
9217 : : }
9218 : :
9219 : : /**
9220 : : * Create group callback.
9221 : : *
9222 : : * @param[in] tool_ctx
9223 : : * Pointer to the hash list related context.
9224 : : * @param[in] cb_ctx
9225 : : * Pointer to the group creation context.
9226 : : *
9227 : : * @return
9228 : : * Group entry on success, NULL otherwise and rte_errno is set.
9229 : : */
9230 : : struct mlx5_list_entry *
9231 : 0 : flow_hw_grp_create_cb(void *tool_ctx, void *cb_ctx)
9232 : : {
9233 : : struct mlx5_dev_ctx_shared *sh = tool_ctx;
9234 : : struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9235 : 0 : struct rte_eth_dev *dev = ctx->dev;
9236 : 0 : struct rte_flow_attr *attr = (struct rte_flow_attr *)ctx->data;
9237 : 0 : uint32_t *specialize = (uint32_t *)ctx->data2;
9238 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
9239 : : bool unified_fdb = is_unified_fdb(priv);
9240 : 0 : struct mlx5dr_table_attr dr_tbl_attr = {0};
9241 : 0 : struct rte_flow_error *error = ctx->error;
9242 : : struct mlx5_flow_group *grp_data;
9243 : : struct mlx5dr_table *tbl = NULL;
9244 : : struct mlx5dr_action *jump;
9245 : : uint32_t hws_flags;
9246 : 0 : uint32_t idx = 0;
9247 [ # # # # : 0 : MKSTR(matcher_name, "%s_%s_%u_%u_matcher_list",
# # # # ]
9248 : : attr->transfer ? "FDB" : "NIC", attr->egress ? "egress" : "ingress",
9249 : : attr->group, idx);
9250 : :
9251 : 0 : grp_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_HW_GRP], &idx);
9252 [ # # ]: 0 : if (!grp_data) {
9253 : 0 : rte_flow_error_set(error, ENOMEM,
9254 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9255 : : NULL,
9256 : : "cannot allocate flow table data entry");
9257 : 0 : return NULL;
9258 : : }
9259 : 0 : dr_tbl_attr.level = attr->group;
9260 : 0 : dr_tbl_attr.type = get_mlx5dr_table_type(attr, *specialize, unified_fdb);
9261 : 0 : tbl = mlx5dr_table_create(priv->dr_ctx, &dr_tbl_attr);
9262 [ # # ]: 0 : if (!tbl)
9263 : 0 : goto error;
9264 : 0 : grp_data->tbl = tbl;
9265 [ # # ]: 0 : if (attr->group) {
9266 : 0 : hws_flags = mlx5_hw_act_dest_table_flag[dr_tbl_attr.type];
9267 : : /* For case of jump from FDB Tx to FDB Rx as it is supported now. */
9268 [ # # # # ]: 0 : if (priv->jump_fdb_rx_en &&
9269 : : dr_tbl_attr.type == MLX5DR_TABLE_TYPE_FDB_RX)
9270 : 0 : hws_flags |= MLX5DR_ACTION_FLAG_HWS_FDB_TX;
9271 : : /* Jump action be used by non-root table. */
9272 : 0 : jump = mlx5dr_action_create_dest_table
9273 : : (priv->dr_ctx, tbl,
9274 : : hws_flags);
9275 [ # # ]: 0 : if (!jump)
9276 : 0 : goto error;
9277 : 0 : grp_data->jump.hws_action = jump;
9278 : : /* Jump action be used by root table. */
9279 : 0 : jump = mlx5dr_action_create_dest_table
9280 : : (priv->dr_ctx, tbl,
9281 : : mlx5_hw_act_flag[MLX5_HW_ACTION_FLAG_ROOT]
9282 : 0 : [dr_tbl_attr.type]);
9283 [ # # ]: 0 : if (!jump)
9284 : 0 : goto error;
9285 : 0 : grp_data->jump.root_action = jump;
9286 : : }
9287 : :
9288 : 0 : grp_data->matchers = mlx5_list_create(matcher_name, sh, true,
9289 : : flow_matcher_create_cb,
9290 : : flow_matcher_match_cb,
9291 : : flow_matcher_remove_cb,
9292 : : flow_matcher_clone_cb,
9293 : : flow_matcher_clone_free_cb);
9294 : 0 : grp_data->dev = dev;
9295 : 0 : grp_data->idx = idx;
9296 : 0 : grp_data->group_id = attr->group;
9297 : 0 : grp_data->type = dr_tbl_attr.type;
9298 : 0 : return &grp_data->entry;
9299 : 0 : error:
9300 [ # # ]: 0 : if (grp_data->jump.root_action)
9301 : 0 : mlx5dr_action_destroy(grp_data->jump.root_action);
9302 [ # # ]: 0 : if (grp_data->jump.hws_action)
9303 : 0 : mlx5dr_action_destroy(grp_data->jump.hws_action);
9304 [ # # ]: 0 : if (tbl)
9305 : 0 : mlx5dr_table_destroy(tbl);
9306 [ # # ]: 0 : if (idx)
9307 : 0 : mlx5_ipool_free(sh->ipool[MLX5_IPOOL_HW_GRP], idx);
9308 : 0 : rte_flow_error_set(error, ENOMEM,
9309 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9310 : : NULL,
9311 : : "cannot allocate flow dr table");
9312 : 0 : return NULL;
9313 : : }
9314 : :
9315 : : /**
9316 : : * Remove group callback.
9317 : : *
9318 : : * @param[in] tool_ctx
9319 : : * Pointer to the hash list related context.
9320 : : * @param[in] entry
9321 : : * Pointer to the entry to be removed.
9322 : : */
9323 : : void
9324 : 0 : flow_hw_grp_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
9325 : : {
9326 : : struct mlx5_dev_ctx_shared *sh = tool_ctx;
9327 : : struct mlx5_flow_group *grp_data =
9328 : : container_of(entry, struct mlx5_flow_group, entry);
9329 : :
9330 : : MLX5_ASSERT(entry && sh);
9331 : : /* To use the wrapper glue functions instead. */
9332 [ # # ]: 0 : if (grp_data->jump.hws_action)
9333 : 0 : mlx5dr_action_destroy(grp_data->jump.hws_action);
9334 [ # # ]: 0 : if (grp_data->jump.root_action)
9335 : 0 : mlx5dr_action_destroy(grp_data->jump.root_action);
9336 : 0 : mlx5_list_destroy(grp_data->matchers);
9337 : 0 : mlx5dr_table_destroy(grp_data->tbl);
9338 : 0 : mlx5_ipool_free(sh->ipool[MLX5_IPOOL_HW_GRP], grp_data->idx);
9339 : 0 : }
9340 : :
9341 : : /**
9342 : : * Match group callback.
9343 : : *
9344 : : * @param[in] tool_ctx
9345 : : * Pointer to the hash list related context.
9346 : : * @param[in] entry
9347 : : * Pointer to the group to be matched.
9348 : : * @param[in] cb_ctx
9349 : : * Pointer to the group matching context.
9350 : : *
9351 : : * @return
9352 : : * 0 on matched, 1 on miss matched.
9353 : : */
9354 : : int
9355 : 0 : flow_hw_grp_match_cb(void *tool_ctx __rte_unused, struct mlx5_list_entry *entry,
9356 : : void *cb_ctx)
9357 : : {
9358 : : struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9359 : : struct mlx5_flow_group *grp_data =
9360 : : container_of(entry, struct mlx5_flow_group, entry);
9361 : 0 : struct rte_flow_attr *attr =
9362 : : (struct rte_flow_attr *)ctx->data;
9363 : :
9364 : 0 : return (grp_data->dev != ctx->dev) ||
9365 [ # # ]: 0 : (grp_data->group_id != attr->group) ||
9366 [ # # # # ]: 0 : ((grp_data->type < MLX5DR_TABLE_TYPE_FDB) &&
9367 [ # # ]: 0 : attr->transfer) ||
9368 [ # # ]: 0 : ((grp_data->type != MLX5DR_TABLE_TYPE_NIC_TX) &&
9369 [ # # # # ]: 0 : attr->egress) ||
9370 [ # # ]: 0 : ((grp_data->type != MLX5DR_TABLE_TYPE_NIC_RX) &&
9371 : : attr->ingress);
9372 : : }
9373 : :
9374 : : /**
9375 : : * Clone group entry callback.
9376 : : *
9377 : : * @param[in] tool_ctx
9378 : : * Pointer to the hash list related context.
9379 : : * @param[in] entry
9380 : : * Pointer to the group to be matched.
9381 : : * @param[in] cb_ctx
9382 : : * Pointer to the group matching context.
9383 : : *
9384 : : * @return
9385 : : * 0 on matched, 1 on miss matched.
9386 : : */
9387 : : struct mlx5_list_entry *
9388 : 0 : flow_hw_grp_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
9389 : : void *cb_ctx)
9390 : : {
9391 : : struct mlx5_dev_ctx_shared *sh = tool_ctx;
9392 : : struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9393 : : struct mlx5_flow_group *grp_data;
9394 : 0 : struct rte_flow_error *error = ctx->error;
9395 : 0 : uint32_t idx = 0;
9396 : :
9397 : 0 : grp_data = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_HW_GRP], &idx);
9398 [ # # ]: 0 : if (!grp_data) {
9399 : 0 : rte_flow_error_set(error, ENOMEM,
9400 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9401 : : NULL,
9402 : : "cannot allocate flow table data entry");
9403 : 0 : return NULL;
9404 : : }
9405 : : memcpy(grp_data, oentry, sizeof(*grp_data));
9406 : 0 : grp_data->idx = idx;
9407 : 0 : return &grp_data->entry;
9408 : : }
9409 : :
9410 : : /**
9411 : : * Free cloned group entry callback.
9412 : : *
9413 : : * @param[in] tool_ctx
9414 : : * Pointer to the hash list related context.
9415 : : * @param[in] entry
9416 : : * Pointer to the group to be freed.
9417 : : */
9418 : : void
9419 : 0 : flow_hw_grp_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
9420 : : {
9421 : : struct mlx5_dev_ctx_shared *sh = tool_ctx;
9422 : : struct mlx5_flow_group *grp_data =
9423 : : container_of(entry, struct mlx5_flow_group, entry);
9424 : :
9425 : 0 : mlx5_ipool_free(sh->ipool[MLX5_IPOOL_HW_GRP], grp_data->idx);
9426 : 0 : }
9427 : :
9428 : : /**
9429 : : * Create and cache a vport action for given @p dev port. vport actions
9430 : : * cache is used in HWS with FDB flows.
9431 : : *
9432 : : * This function does not create any function if proxy port for @p dev port
9433 : : * was not configured for HW Steering.
9434 : : *
9435 : : * This function assumes that E-Switch is enabled and PMD is running with
9436 : : * HW Steering configured.
9437 : : *
9438 : : * @param dev
9439 : : * Pointer to Ethernet device which will be the action destination.
9440 : : *
9441 : : * @return
9442 : : * 0 on success, positive value otherwise.
9443 : : */
9444 : : int
9445 : 0 : flow_hw_create_vport_action(struct rte_eth_dev *dev)
9446 : : {
9447 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
9448 : : struct rte_eth_dev *proxy_dev;
9449 : : struct mlx5_priv *proxy_priv;
9450 : 0 : uint16_t port_id = dev->data->port_id;
9451 : 0 : uint16_t proxy_port_id = port_id;
9452 : : int ret;
9453 : :
9454 : 0 : ret = mlx5_flow_pick_transfer_proxy(dev, &proxy_port_id, NULL);
9455 [ # # ]: 0 : if (ret)
9456 : : return ret;
9457 : 0 : proxy_dev = &rte_eth_devices[proxy_port_id];
9458 : 0 : proxy_priv = proxy_dev->data->dev_private;
9459 [ # # ]: 0 : if (!proxy_priv->hw_vport)
9460 : : return 0;
9461 [ # # ]: 0 : if (proxy_priv->hw_vport[port_id]) {
9462 : 0 : DRV_LOG(ERR, "port %u HWS vport action already created",
9463 : : port_id);
9464 : 0 : return -EINVAL;
9465 : : }
9466 [ # # ]: 0 : proxy_priv->hw_vport[port_id] = mlx5dr_action_create_dest_vport
9467 : : (proxy_priv->dr_ctx, priv->dev_port,
9468 : : is_unified_fdb(priv) ?
9469 : : (MLX5DR_ACTION_FLAG_HWS_FDB_RX |
9470 : : MLX5DR_ACTION_FLAG_HWS_FDB_TX |
9471 : : MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED) :
9472 : : MLX5DR_ACTION_FLAG_HWS_FDB);
9473 [ # # ]: 0 : if (!proxy_priv->hw_vport[port_id]) {
9474 : 0 : DRV_LOG(ERR, "port %u unable to create HWS vport action",
9475 : : port_id);
9476 : 0 : return -EINVAL;
9477 : : }
9478 : : return 0;
9479 : : }
9480 : :
9481 : : /**
9482 : : * Destroys the vport action associated with @p dev device
9483 : : * from actions' cache.
9484 : : *
9485 : : * This function does not destroy any action if there is no action cached
9486 : : * for @p dev or proxy port was not configured for HW Steering.
9487 : : *
9488 : : * This function assumes that E-Switch is enabled and PMD is running with
9489 : : * HW Steering configured.
9490 : : *
9491 : : * @param dev
9492 : : * Pointer to Ethernet device which will be the action destination.
9493 : : */
9494 : : void
9495 : 0 : flow_hw_destroy_vport_action(struct rte_eth_dev *dev)
9496 : : {
9497 : : struct rte_eth_dev *proxy_dev;
9498 : : struct mlx5_priv *proxy_priv;
9499 : 0 : uint16_t port_id = dev->data->port_id;
9500 : 0 : uint16_t proxy_port_id = port_id;
9501 : :
9502 [ # # ]: 0 : if (mlx5_flow_pick_transfer_proxy(dev, &proxy_port_id, NULL))
9503 : 0 : return;
9504 : 0 : proxy_dev = &rte_eth_devices[proxy_port_id];
9505 : 0 : proxy_priv = proxy_dev->data->dev_private;
9506 [ # # # # ]: 0 : if (!proxy_priv->hw_vport || !proxy_priv->hw_vport[port_id])
9507 : : return;
9508 : 0 : mlx5dr_action_destroy(proxy_priv->hw_vport[port_id]);
9509 : 0 : proxy_priv->hw_vport[port_id] = NULL;
9510 : : }
9511 : :
9512 : : static int
9513 : 0 : flow_hw_create_vport_actions(struct mlx5_priv *priv)
9514 : : {
9515 : : uint16_t port_id;
9516 : :
9517 : : MLX5_ASSERT(!priv->hw_vport);
9518 : : bool unified_fdb = is_unified_fdb(priv);
9519 : 0 : priv->hw_vport = mlx5_malloc(MLX5_MEM_ZERO,
9520 : : sizeof(*priv->hw_vport) * RTE_MAX_ETHPORTS,
9521 : : 0, SOCKET_ID_ANY);
9522 [ # # ]: 0 : if (!priv->hw_vport)
9523 : : return -ENOMEM;
9524 : 0 : DRV_LOG(DEBUG, "port %u :: creating vport actions", priv->dev_data->port_id);
9525 : 0 : DRV_LOG(DEBUG, "port %u :: domain_id=%u", priv->dev_data->port_id, priv->domain_id);
9526 [ # # ]: 0 : MLX5_ETH_FOREACH_DEV(port_id, NULL) {
9527 : 0 : struct mlx5_priv *port_priv = rte_eth_devices[port_id].data->dev_private;
9528 : :
9529 [ # # ]: 0 : if (!port_priv ||
9530 [ # # ]: 0 : port_priv->domain_id != priv->domain_id)
9531 : 0 : continue;
9532 : 0 : DRV_LOG(DEBUG, "port %u :: for port_id=%u, calling mlx5dr_action_create_dest_vport() with ibport=%u",
9533 : : priv->dev_data->port_id, port_id, port_priv->dev_port);
9534 [ # # ]: 0 : priv->hw_vport[port_id] = mlx5dr_action_create_dest_vport
9535 : : (priv->dr_ctx, port_priv->dev_port,
9536 : : unified_fdb ?
9537 : : (MLX5DR_ACTION_FLAG_HWS_FDB_RX |
9538 : : MLX5DR_ACTION_FLAG_HWS_FDB_TX |
9539 : : MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED) :
9540 : : MLX5DR_ACTION_FLAG_HWS_FDB);
9541 : 0 : DRV_LOG(DEBUG, "port %u :: priv->hw_vport[%u]=%p",
9542 : : priv->dev_data->port_id, port_id, (void *)priv->hw_vport[port_id]);
9543 [ # # ]: 0 : if (!priv->hw_vport[port_id])
9544 : : return -EINVAL;
9545 : : }
9546 : : return 0;
9547 : : }
9548 : :
9549 : : static void
9550 : 0 : flow_hw_free_vport_actions(struct mlx5_priv *priv)
9551 : : {
9552 : : uint16_t port_id;
9553 : :
9554 [ # # ]: 0 : if (!priv->hw_vport)
9555 : : return;
9556 [ # # ]: 0 : for (port_id = 0; port_id < RTE_MAX_ETHPORTS; ++port_id)
9557 [ # # ]: 0 : if (priv->hw_vport[port_id])
9558 : 0 : mlx5dr_action_destroy(priv->hw_vport[port_id]);
9559 : 0 : mlx5_free(priv->hw_vport);
9560 : 0 : priv->hw_vport = NULL;
9561 : : }
9562 : :
9563 : : #ifdef HAVE_MLX5DV_DR_ACTION_CREATE_DEST_ROOT_TABLE
9564 : : static __rte_always_inline void
9565 : : _create_send_to_kernel_actions(struct mlx5_priv *priv, int type)
9566 : : {
9567 : : int action_flag;
9568 : :
9569 : : action_flag = mlx5_hw_act_flag[1][type];
9570 : : priv->hw_send_to_kernel[type] =
9571 : : mlx5dr_action_create_dest_root(priv->dr_ctx,
9572 : : MLX5_HW_LOWEST_PRIO_ROOT,
9573 : : action_flag);
9574 : : if (!priv->hw_send_to_kernel[type])
9575 : : DRV_LOG(WARNING, "Unable to create HWS send to kernel action");
9576 : : }
9577 : : #endif
9578 : :
9579 : : static void
9580 : : flow_hw_create_send_to_kernel_actions(__rte_unused struct mlx5_priv *priv,
9581 : : __rte_unused bool is_proxy)
9582 : : {
9583 : : #ifdef HAVE_MLX5DV_DR_ACTION_CREATE_DEST_ROOT_TABLE
9584 : : int i, from, to;
9585 : : bool unified_fdb = is_unified_fdb(priv);
9586 : :
9587 : : for (i = MLX5DR_TABLE_TYPE_NIC_RX; i <= MLX5DR_TABLE_TYPE_NIC_TX; i++)
9588 : : _create_send_to_kernel_actions(priv, i);
9589 : :
9590 : : if (is_proxy) {
9591 : : from = unified_fdb ? MLX5DR_TABLE_TYPE_FDB_RX : MLX5DR_TABLE_TYPE_FDB;
9592 : : to = unified_fdb ? MLX5DR_TABLE_TYPE_FDB_UNIFIED : MLX5DR_TABLE_TYPE_FDB;
9593 : : for (i = from; i <= to; i++)
9594 : : _create_send_to_kernel_actions(priv, i);
9595 : : }
9596 : : #endif
9597 : : }
9598 : :
9599 : : static void
9600 : 0 : flow_hw_destroy_send_to_kernel_action(struct mlx5_priv *priv)
9601 : : {
9602 : : int i;
9603 : :
9604 [ # # ]: 0 : for (i = MLX5DR_TABLE_TYPE_NIC_RX; i < MLX5DR_TABLE_TYPE_MAX; i++) {
9605 [ # # ]: 0 : if (priv->hw_send_to_kernel[i]) {
9606 : 0 : mlx5dr_action_destroy(priv->hw_send_to_kernel[i]);
9607 : 0 : priv->hw_send_to_kernel[i] = NULL;
9608 : : }
9609 : : }
9610 : 0 : }
9611 : :
9612 : : static bool
9613 : : flow_hw_should_create_nat64_actions(struct mlx5_priv *priv)
9614 : : {
9615 : : int i;
9616 : :
9617 : : /* Check if all registers are available. */
9618 [ # # ]: 0 : for (i = 0; i < MLX5_FLOW_NAT64_REGS_MAX; ++i)
9619 [ # # ]: 0 : if (priv->sh->registers.nat64_regs[i] == REG_NON)
9620 : : return false;
9621 : :
9622 : : return true;
9623 : : }
9624 : :
9625 : : static void
9626 : 0 : flow_hw_destroy_nat64_actions(struct mlx5_priv *priv)
9627 : : {
9628 : : uint32_t i;
9629 : :
9630 [ # # ]: 0 : for (i = MLX5DR_TABLE_TYPE_NIC_RX; i < MLX5DR_TABLE_TYPE_MAX; i++) {
9631 [ # # ]: 0 : if (priv->action_nat64[i][RTE_FLOW_NAT64_6TO4]) {
9632 : 0 : (void)mlx5dr_action_destroy(priv->action_nat64[i][RTE_FLOW_NAT64_6TO4]);
9633 : 0 : priv->action_nat64[i][RTE_FLOW_NAT64_6TO4] = NULL;
9634 : : }
9635 [ # # ]: 0 : if (priv->action_nat64[i][RTE_FLOW_NAT64_4TO6]) {
9636 : 0 : (void)mlx5dr_action_destroy(priv->action_nat64[i][RTE_FLOW_NAT64_4TO6]);
9637 : 0 : priv->action_nat64[i][RTE_FLOW_NAT64_4TO6] = NULL;
9638 : : }
9639 : : }
9640 : 0 : }
9641 : :
9642 : : static int
9643 : 0 : _create_nat64_actions(struct mlx5_priv *priv,
9644 : : struct mlx5dr_action_nat64_attr *attr,
9645 : : int type,
9646 : : struct rte_flow_error *error)
9647 : : {
9648 : 0 : const uint32_t flags[MLX5DR_TABLE_TYPE_MAX] = {
9649 : : MLX5DR_ACTION_FLAG_HWS_RX | MLX5DR_ACTION_FLAG_SHARED,
9650 : : MLX5DR_ACTION_FLAG_HWS_TX | MLX5DR_ACTION_FLAG_SHARED,
9651 : : MLX5DR_ACTION_FLAG_HWS_FDB | MLX5DR_ACTION_FLAG_SHARED,
9652 : : MLX5DR_ACTION_FLAG_HWS_FDB_RX | MLX5DR_ACTION_FLAG_SHARED,
9653 : : MLX5DR_ACTION_FLAG_HWS_FDB_TX | MLX5DR_ACTION_FLAG_SHARED,
9654 : : MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED | MLX5DR_ACTION_FLAG_SHARED,
9655 : : };
9656 : : struct mlx5dr_action *act;
9657 : :
9658 : 0 : attr->flags = (enum mlx5dr_action_nat64_flags)
9659 : : (MLX5DR_ACTION_NAT64_V6_TO_V4 | MLX5DR_ACTION_NAT64_BACKUP_ADDR);
9660 : 0 : act = mlx5dr_action_create_nat64(priv->dr_ctx, attr, flags[type]);
9661 [ # # ]: 0 : if (!act)
9662 : 0 : return rte_flow_error_set(error, rte_errno,
9663 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9664 : : "Failed to create v6 to v4 action.");
9665 : 0 : priv->action_nat64[type][RTE_FLOW_NAT64_6TO4] = act;
9666 : 0 : attr->flags = (enum mlx5dr_action_nat64_flags)
9667 : : (MLX5DR_ACTION_NAT64_V4_TO_V6 | MLX5DR_ACTION_NAT64_BACKUP_ADDR);
9668 : 0 : act = mlx5dr_action_create_nat64(priv->dr_ctx, attr, flags[type]);
9669 [ # # ]: 0 : if (!act)
9670 : 0 : return rte_flow_error_set(error, rte_errno,
9671 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9672 : : "Failed to create v4 to v6 action.");
9673 : 0 : priv->action_nat64[type][RTE_FLOW_NAT64_4TO6] = act;
9674 : 0 : return 0;
9675 : : }
9676 : :
9677 : : static int
9678 : 0 : flow_hw_create_nat64_actions(struct mlx5_priv *priv, struct rte_flow_error *error)
9679 : : {
9680 : : struct mlx5dr_action_nat64_attr attr;
9681 : : uint8_t regs[MLX5_FLOW_NAT64_REGS_MAX];
9682 : : uint32_t i, from, to;
9683 : : int rc;
9684 : : bool unified_fdb = is_unified_fdb(priv);
9685 : :
9686 : 0 : attr.registers = regs;
9687 : : /* Try to use 3 registers by default. */
9688 : 0 : attr.num_of_registers = MLX5_FLOW_NAT64_REGS_MAX;
9689 [ # # ]: 0 : for (i = 0; i < MLX5_FLOW_NAT64_REGS_MAX; i++) {
9690 : : MLX5_ASSERT(priv->sh->registers.nat64_regs[i] != REG_NON);
9691 : 0 : regs[i] = mlx5_convert_reg_to_field(priv->sh->registers.nat64_regs[i]);
9692 : : }
9693 [ # # ]: 0 : for (i = MLX5DR_TABLE_TYPE_NIC_RX; i <= MLX5DR_TABLE_TYPE_NIC_TX; i++) {
9694 : 0 : rc = _create_nat64_actions(priv, &attr, i, error);
9695 [ # # ]: 0 : if (rc)
9696 : 0 : return rc;
9697 : : }
9698 [ # # ]: 0 : if (priv->sh->config.dv_esw_en) {
9699 [ # # ]: 0 : from = unified_fdb ? MLX5DR_TABLE_TYPE_FDB_RX :
9700 : : MLX5DR_TABLE_TYPE_FDB;
9701 [ # # ]: 0 : to = unified_fdb ? MLX5DR_TABLE_TYPE_FDB_UNIFIED :
9702 : : MLX5DR_TABLE_TYPE_FDB;
9703 : :
9704 [ # # ]: 0 : for (i = from; i <= to; i++) {
9705 : 0 : rc = _create_nat64_actions(priv, &attr, i, error);
9706 [ # # ]: 0 : if (rc)
9707 : 0 : return rc;
9708 : : }
9709 : : }
9710 : : return 0;
9711 : : }
9712 : :
9713 : : /**
9714 : : * Create an egress pattern template matching on source SQ.
9715 : : *
9716 : : * @param dev
9717 : : * Pointer to Ethernet device.
9718 : : * @param[out] error
9719 : : * Pointer to error structure.
9720 : : *
9721 : : * @return
9722 : : * Pointer to pattern template on success. NULL otherwise, and rte_errno is set.
9723 : : */
9724 : : static struct rte_flow_pattern_template *
9725 : 0 : flow_hw_create_tx_repr_sq_pattern_tmpl(struct rte_eth_dev *dev, struct rte_flow_error *error)
9726 : : {
9727 : 0 : struct rte_flow_pattern_template_attr attr = {
9728 : : .relaxed_matching = 0,
9729 : : .egress = 1,
9730 : : };
9731 : 0 : struct mlx5_rte_flow_item_sq sq_mask = {
9732 : : .queue = UINT32_MAX,
9733 : : };
9734 : 0 : struct rte_flow_item items[] = {
9735 : : {
9736 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_SQ,
9737 : : .mask = &sq_mask,
9738 : : },
9739 : : {
9740 : : .type = RTE_FLOW_ITEM_TYPE_END,
9741 : : },
9742 : : };
9743 : :
9744 : 0 : return flow_hw_pattern_template_create(dev, &attr, items, error);
9745 : : }
9746 : :
9747 : : static __rte_always_inline uint32_t
9748 : : flow_hw_tx_tag_regc_mask(struct rte_eth_dev *dev)
9749 : : {
9750 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
9751 : 0 : uint32_t mask = priv->sh->dv_regc0_mask;
9752 : :
9753 : : /* Mask is verified during device initialization. Sanity checking here. */
9754 : : MLX5_ASSERT(mask != 0);
9755 : : /*
9756 : : * Availability of sufficient number of bits in REG_C_0 is verified on initialization.
9757 : : * Sanity checking here.
9758 : : */
9759 : : MLX5_ASSERT(rte_popcount32(mask) >= rte_popcount32(priv->vport_meta_mask));
9760 : : return mask;
9761 : : }
9762 : :
9763 : : static __rte_always_inline uint32_t
9764 : : flow_hw_tx_tag_regc_value(struct rte_eth_dev *dev)
9765 : : {
9766 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
9767 : : uint32_t tag;
9768 : :
9769 : : /* Mask is verified during device initialization. Sanity checking here. */
9770 : : MLX5_ASSERT(priv->vport_meta_mask != 0);
9771 [ # # ]: 0 : tag = priv->vport_meta_tag >> (rte_bsf32(priv->vport_meta_mask));
9772 : : /*
9773 : : * Availability of sufficient number of bits in REG_C_0 is verified on initialization.
9774 : : * Sanity checking here.
9775 : : */
9776 : : MLX5_ASSERT((tag & priv->sh->dv_regc0_mask) == tag);
9777 : : return tag;
9778 : : }
9779 : :
9780 : : static void
9781 : : flow_hw_update_action_mask(struct rte_flow_action *action,
9782 : : struct rte_flow_action *mask,
9783 : : enum rte_flow_action_type type,
9784 : : void *conf_v,
9785 : : void *conf_m)
9786 : : {
9787 : 0 : action->type = type;
9788 : 0 : action->conf = conf_v;
9789 : 0 : mask->type = type;
9790 : 0 : mask->conf = conf_m;
9791 : : }
9792 : :
9793 : : /**
9794 : : * Create an egress actions template with MODIFY_FIELD action for setting unused REG_C_0 bits
9795 : : * to vport tag and JUMP action to group 1.
9796 : : *
9797 : : * If extended metadata mode is enabled, then MODIFY_FIELD action for copying software metadata
9798 : : * to REG_C_1 is added as well.
9799 : : *
9800 : : * @param dev
9801 : : * Pointer to Ethernet device.
9802 : : * @param[out] error
9803 : : * Pointer to error structure.
9804 : : *
9805 : : * @return
9806 : : * Pointer to actions template on success. NULL otherwise, and rte_errno is set.
9807 : : */
9808 : : static struct rte_flow_actions_template *
9809 : 0 : flow_hw_create_tx_repr_tag_jump_acts_tmpl(struct rte_eth_dev *dev,
9810 : : struct rte_flow_error *error)
9811 : : {
9812 [ # # ]: 0 : uint32_t tag_mask = flow_hw_tx_tag_regc_mask(dev);
9813 : 0 : uint32_t tag_value = flow_hw_tx_tag_regc_value(dev);
9814 : 0 : struct rte_flow_actions_template_attr attr = {
9815 : : .egress = 1,
9816 : : };
9817 [ # # ]: 0 : struct rte_flow_action_modify_field set_tag_v = {
9818 : : .operation = RTE_FLOW_MODIFY_SET,
9819 : : .dst = {
9820 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
9821 : : .tag_index = REG_C_0,
9822 : : .offset = rte_bsf32(tag_mask),
9823 : : },
9824 : : .src = {
9825 : : .field = RTE_FLOW_FIELD_VALUE,
9826 : : },
9827 : : .width = rte_popcount32(tag_mask),
9828 : : };
9829 : 0 : struct rte_flow_action_modify_field set_tag_m = {
9830 : : .operation = RTE_FLOW_MODIFY_SET,
9831 : : .dst = {
9832 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
9833 : : .level = UINT8_MAX,
9834 : : .tag_index = UINT8_MAX,
9835 : : .offset = UINT32_MAX,
9836 : : },
9837 : : .src = {
9838 : : .field = RTE_FLOW_FIELD_VALUE,
9839 : : },
9840 : : .width = UINT32_MAX,
9841 : : };
9842 : 0 : struct rte_flow_action_modify_field copy_metadata_v = {
9843 : : .operation = RTE_FLOW_MODIFY_SET,
9844 : : .dst = {
9845 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
9846 : : .tag_index = REG_C_1,
9847 : : },
9848 : : .src = {
9849 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
9850 : : .tag_index = REG_A,
9851 : : },
9852 : : .width = 32,
9853 : : };
9854 : 0 : struct rte_flow_action_modify_field copy_metadata_m = {
9855 : : .operation = RTE_FLOW_MODIFY_SET,
9856 : : .dst = {
9857 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
9858 : : .level = UINT8_MAX,
9859 : : .tag_index = UINT8_MAX,
9860 : : .offset = UINT32_MAX,
9861 : : },
9862 : : .src = {
9863 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
9864 : : .level = UINT8_MAX,
9865 : : .tag_index = UINT8_MAX,
9866 : : .offset = UINT32_MAX,
9867 : : },
9868 : : .width = UINT32_MAX,
9869 : : };
9870 : 0 : struct rte_flow_action_jump jump_v = {
9871 : : .group = MLX5_HW_LOWEST_USABLE_GROUP,
9872 : : };
9873 : 0 : struct rte_flow_action_jump jump_m = {
9874 : : .group = UINT32_MAX,
9875 : : };
9876 : 0 : struct rte_flow_action actions_v[4] = { { 0 } };
9877 [ # # ]: 0 : struct rte_flow_action actions_m[4] = { { 0 } };
9878 : : unsigned int idx = 0;
9879 : :
9880 : : rte_memcpy(set_tag_v.src.value, &tag_value, sizeof(tag_value));
9881 : : rte_memcpy(set_tag_m.src.value, &tag_mask, sizeof(tag_mask));
9882 : : flow_hw_update_action_mask(&actions_v[idx], &actions_m[idx],
9883 : : RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
9884 : : &set_tag_v, &set_tag_m);
9885 : : idx++;
9886 [ # # ]: 0 : if (MLX5_SH(dev)->config.dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS) {
9887 : : flow_hw_update_action_mask(&actions_v[idx], &actions_m[idx],
9888 : : RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
9889 : : ©_metadata_v, ©_metadata_m);
9890 : : idx++;
9891 : : }
9892 : : flow_hw_update_action_mask(&actions_v[idx], &actions_m[idx], RTE_FLOW_ACTION_TYPE_JUMP,
9893 : : &jump_v, &jump_m);
9894 : 0 : idx++;
9895 : : flow_hw_update_action_mask(&actions_v[idx], &actions_m[idx], RTE_FLOW_ACTION_TYPE_END,
9896 : : NULL, NULL);
9897 : : idx++;
9898 : : MLX5_ASSERT(idx <= RTE_DIM(actions_v));
9899 : 0 : return flow_hw_actions_template_create(dev, &attr, actions_v, actions_m, error);
9900 : : }
9901 : :
9902 : : static void
9903 : 0 : flow_hw_cleanup_tx_repr_tagging(struct rte_eth_dev *dev)
9904 : : {
9905 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
9906 : :
9907 [ # # ]: 0 : if (priv->hw_tx_repr_tagging_tbl) {
9908 : 0 : flow_hw_table_destroy(dev, priv->hw_tx_repr_tagging_tbl, NULL);
9909 : 0 : priv->hw_tx_repr_tagging_tbl = NULL;
9910 : : }
9911 [ # # ]: 0 : if (priv->hw_tx_repr_tagging_at) {
9912 : 0 : flow_hw_actions_template_destroy(dev, priv->hw_tx_repr_tagging_at, NULL);
9913 : 0 : priv->hw_tx_repr_tagging_at = NULL;
9914 : : }
9915 [ # # ]: 0 : if (priv->hw_tx_repr_tagging_pt) {
9916 : 0 : flow_hw_pattern_template_destroy(dev, priv->hw_tx_repr_tagging_pt, NULL);
9917 : 0 : priv->hw_tx_repr_tagging_pt = NULL;
9918 : : }
9919 : 0 : }
9920 : :
9921 : : /**
9922 : : * Setup templates and table used to create default Tx flow rules. These default rules
9923 : : * allow for matching Tx representor traffic using a vport tag placed in unused bits of
9924 : : * REG_C_0 register.
9925 : : *
9926 : : * @param dev
9927 : : * Pointer to Ethernet device.
9928 : : * @param[out] error
9929 : : * Pointer to error structure.
9930 : : *
9931 : : * @return
9932 : : * 0 on success, negative errno value otherwise.
9933 : : */
9934 : : static int
9935 : 0 : flow_hw_setup_tx_repr_tagging(struct rte_eth_dev *dev, struct rte_flow_error *error)
9936 : : {
9937 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
9938 : 0 : struct rte_flow_template_table_attr attr = {
9939 : : .flow_attr = {
9940 : : .group = 0,
9941 : : .priority = MLX5_HW_LOWEST_PRIO_ROOT,
9942 : : .egress = 1,
9943 : : },
9944 : : .nb_flows = MLX5_HW_CTRL_FLOW_NB_RULES,
9945 : : };
9946 : 0 : struct mlx5_flow_template_table_cfg cfg = {
9947 : : .attr = attr,
9948 : : .external = false,
9949 : : };
9950 : :
9951 : : MLX5_ASSERT(priv->sh->config.dv_esw_en);
9952 : : MLX5_ASSERT(priv->sh->config.repr_matching);
9953 : 0 : priv->hw_tx_repr_tagging_pt =
9954 : 0 : flow_hw_create_tx_repr_sq_pattern_tmpl(dev, error);
9955 [ # # ]: 0 : if (!priv->hw_tx_repr_tagging_pt)
9956 : 0 : goto err;
9957 : 0 : priv->hw_tx_repr_tagging_at =
9958 : 0 : flow_hw_create_tx_repr_tag_jump_acts_tmpl(dev, error);
9959 [ # # ]: 0 : if (!priv->hw_tx_repr_tagging_at)
9960 : 0 : goto err;
9961 : 0 : priv->hw_tx_repr_tagging_tbl = flow_hw_table_create(dev, &cfg,
9962 : : &priv->hw_tx_repr_tagging_pt, 1,
9963 : : &priv->hw_tx_repr_tagging_at, 1,
9964 : : error);
9965 [ # # ]: 0 : if (!priv->hw_tx_repr_tagging_tbl)
9966 : 0 : goto err;
9967 : : return 0;
9968 : 0 : err:
9969 : 0 : flow_hw_cleanup_tx_repr_tagging(dev);
9970 : 0 : return -rte_errno;
9971 : : }
9972 : :
9973 : : static uint32_t
9974 : : flow_hw_esw_mgr_regc_marker_mask(struct rte_eth_dev *dev)
9975 : : {
9976 : 0 : uint32_t mask = MLX5_SH(dev)->dv_regc0_mask;
9977 : :
9978 : : /* Mask is verified during device initialization. */
9979 : : MLX5_ASSERT(mask != 0);
9980 : : return mask;
9981 : : }
9982 : :
9983 : : static uint32_t
9984 : : flow_hw_esw_mgr_regc_marker(struct rte_eth_dev *dev)
9985 : : {
9986 : 0 : uint32_t mask = MLX5_SH(dev)->dv_regc0_mask;
9987 : :
9988 : : /* Mask is verified during device initialization. */
9989 : : MLX5_ASSERT(mask != 0);
9990 : 0 : return RTE_BIT32(rte_bsf32(mask));
9991 : : }
9992 : :
9993 : : /**
9994 : : * Creates a flow pattern template used to match on E-Switch Manager.
9995 : : * This template is used to set up a table for SQ miss default flow.
9996 : : *
9997 : : * @param dev
9998 : : * Pointer to Ethernet device.
9999 : : * @param error
10000 : : * Pointer to error structure.
10001 : : *
10002 : : * @return
10003 : : * Pointer to flow pattern template on success, NULL otherwise.
10004 : : */
10005 : : static struct rte_flow_pattern_template *
10006 : 0 : flow_hw_create_ctrl_esw_mgr_pattern_template(struct rte_eth_dev *dev,
10007 : : struct rte_flow_error *error)
10008 : : {
10009 : 0 : struct rte_flow_pattern_template_attr attr = {
10010 : : .relaxed_matching = 0,
10011 : : .transfer = 1,
10012 : : };
10013 : 0 : struct rte_flow_item_ethdev port_spec = {
10014 : : .port_id = MLX5_REPRESENTED_PORT_ESW_MGR,
10015 : : };
10016 : 0 : struct rte_flow_item_ethdev port_mask = {
10017 : : .port_id = UINT16_MAX,
10018 : : };
10019 : 0 : struct mlx5_rte_flow_item_sq sq_mask = {
10020 : : .queue = UINT32_MAX,
10021 : : };
10022 : 0 : struct rte_flow_item items[] = {
10023 : : {
10024 : : .type = RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT,
10025 : : .spec = &port_spec,
10026 : : .mask = &port_mask,
10027 : : },
10028 : : {
10029 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_SQ,
10030 : : .mask = &sq_mask,
10031 : : },
10032 : : {
10033 : : .type = RTE_FLOW_ITEM_TYPE_END,
10034 : : },
10035 : : };
10036 : :
10037 : 0 : return flow_hw_pattern_template_create(dev, &attr, items, error);
10038 : : }
10039 : :
10040 : : /**
10041 : : * Creates a flow pattern template used to match REG_C_0 and a SQ.
10042 : : * Matching on REG_C_0 is set up to match on all bits usable by user-space.
10043 : : * If traffic was sent from E-Switch Manager, then all usable bits will be set to 0,
10044 : : * except the least significant bit, which will be set to 1.
10045 : : *
10046 : : * This template is used to set up a table for SQ miss default flow.
10047 : : *
10048 : : * @param dev
10049 : : * Pointer to Ethernet device.
10050 : : * @param error
10051 : : * Pointer to error structure.
10052 : : *
10053 : : * @return
10054 : : * Pointer to flow pattern template on success, NULL otherwise.
10055 : : */
10056 : : static struct rte_flow_pattern_template *
10057 : 0 : flow_hw_create_ctrl_regc_sq_pattern_template(struct rte_eth_dev *dev,
10058 : : struct rte_flow_error *error)
10059 : : {
10060 : 0 : struct rte_flow_pattern_template_attr attr = {
10061 : : .relaxed_matching = 0,
10062 : : .transfer = 1,
10063 : : };
10064 : 0 : struct rte_flow_item_tag reg_c0_spec = {
10065 : : .index = (uint8_t)REG_C_0,
10066 : : };
10067 : 0 : struct rte_flow_item_tag reg_c0_mask = {
10068 : : .index = 0xff,
10069 : : .data = flow_hw_esw_mgr_regc_marker_mask(dev),
10070 : : };
10071 : 0 : struct mlx5_rte_flow_item_sq queue_mask = {
10072 : : .queue = UINT32_MAX,
10073 : : };
10074 : 0 : struct rte_flow_item items[] = {
10075 : : {
10076 : : .type = (enum rte_flow_item_type)
10077 : : MLX5_RTE_FLOW_ITEM_TYPE_TAG,
10078 : : .spec = ®_c0_spec,
10079 : : .mask = ®_c0_mask,
10080 : : },
10081 : : {
10082 : : .type = (enum rte_flow_item_type)
10083 : : MLX5_RTE_FLOW_ITEM_TYPE_SQ,
10084 : : .mask = &queue_mask,
10085 : : },
10086 : : {
10087 : : .type = RTE_FLOW_ITEM_TYPE_END,
10088 : : },
10089 : : };
10090 : :
10091 : 0 : return flow_hw_pattern_template_create(dev, &attr, items, error);
10092 : : }
10093 : :
10094 : : /**
10095 : : * Creates a flow pattern template with unmasked represented port matching.
10096 : : * This template is used to set up a table for default transfer flows
10097 : : * directing packets to group 1.
10098 : : *
10099 : : * @param dev
10100 : : * Pointer to Ethernet device.
10101 : : * @param error
10102 : : * Pointer to error structure.
10103 : : *
10104 : : * @return
10105 : : * Pointer to flow pattern template on success, NULL otherwise.
10106 : : */
10107 : : static struct rte_flow_pattern_template *
10108 : 0 : flow_hw_create_ctrl_port_pattern_template(struct rte_eth_dev *dev,
10109 : : struct rte_flow_error *error)
10110 : : {
10111 : 0 : struct rte_flow_pattern_template_attr attr = {
10112 : : .relaxed_matching = 0,
10113 : : .transfer = 1,
10114 : : };
10115 : 0 : struct rte_flow_item_ethdev port_mask = {
10116 : : .port_id = UINT16_MAX,
10117 : : };
10118 : 0 : struct rte_flow_item items[] = {
10119 : : {
10120 : : .type = RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT,
10121 : : .mask = &port_mask,
10122 : : },
10123 : : {
10124 : : .type = RTE_FLOW_ITEM_TYPE_END,
10125 : : },
10126 : : };
10127 : :
10128 : 0 : return flow_hw_pattern_template_create(dev, &attr, items, error);
10129 : : }
10130 : :
10131 : : /*
10132 : : * Creating a flow pattern template with all ETH packets matching.
10133 : : * This template is used to set up a table for default Tx copy (Tx metadata
10134 : : * to REG_C_1) flow rule usage.
10135 : : *
10136 : : * @param dev
10137 : : * Pointer to Ethernet device.
10138 : : * @param error
10139 : : * Pointer to error structure.
10140 : : *
10141 : : * @return
10142 : : * Pointer to flow pattern template on success, NULL otherwise.
10143 : : */
10144 : : static struct rte_flow_pattern_template *
10145 : 0 : flow_hw_create_tx_default_mreg_copy_pattern_template(struct rte_eth_dev *dev,
10146 : : struct rte_flow_error *error)
10147 : : {
10148 : 0 : struct rte_flow_pattern_template_attr tx_pa_attr = {
10149 : : .relaxed_matching = 0,
10150 : : .egress = 1,
10151 : : };
10152 : 0 : struct rte_flow_item_eth promisc = {
10153 : : .hdr.dst_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
10154 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
10155 : : .hdr.ether_type = 0,
10156 : : };
10157 : 0 : struct rte_flow_item eth_all[] = {
10158 : : [0] = {
10159 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
10160 : : .spec = &promisc,
10161 : : .mask = &promisc,
10162 : : },
10163 : : [1] = {
10164 : : .type = RTE_FLOW_ITEM_TYPE_END,
10165 : : },
10166 : : };
10167 : :
10168 : 0 : return flow_hw_pattern_template_create(dev, &tx_pa_attr, eth_all, error);
10169 : : }
10170 : :
10171 : : /*
10172 : : * Creating a flow pattern template with all LACP packets matching, only for NIC
10173 : : * ingress domain.
10174 : : *
10175 : : * @param dev
10176 : : * Pointer to Ethernet device.
10177 : : * @param error
10178 : : * Pointer to error structure.
10179 : : *
10180 : : * @return
10181 : : * Pointer to flow pattern template on success, NULL otherwise.
10182 : : */
10183 : : static struct rte_flow_pattern_template *
10184 : 0 : flow_hw_create_lacp_rx_pattern_template(struct rte_eth_dev *dev, struct rte_flow_error *error)
10185 : : {
10186 : 0 : struct rte_flow_pattern_template_attr pa_attr = {
10187 : : .relaxed_matching = 0,
10188 : : .ingress = 1,
10189 : : };
10190 : 0 : struct rte_flow_item_eth lacp_mask = {
10191 : : .dst.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
10192 : : .src.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
10193 : : .type = 0xFFFF,
10194 : : };
10195 : 0 : struct rte_flow_item eth_all[] = {
10196 : : [0] = {
10197 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
10198 : : .mask = &lacp_mask,
10199 : : },
10200 : : [1] = {
10201 : : .type = RTE_FLOW_ITEM_TYPE_END,
10202 : : },
10203 : : };
10204 : 0 : return flow_hw_pattern_template_create(dev, &pa_attr, eth_all, error);
10205 : : }
10206 : :
10207 : : /**
10208 : : * Creates a flow actions template with modify field action and masked jump action.
10209 : : * Modify field action sets the least significant bit of REG_C_0 (usable by user-space)
10210 : : * to 1, meaning that packet was originated from E-Switch Manager. Jump action
10211 : : * transfers steering to group 1.
10212 : : *
10213 : : * @param dev
10214 : : * Pointer to Ethernet device.
10215 : : * @param error
10216 : : * Pointer to error structure.
10217 : : *
10218 : : * @return
10219 : : * Pointer to flow actions template on success, NULL otherwise.
10220 : : */
10221 : : static struct rte_flow_actions_template *
10222 : 0 : flow_hw_create_ctrl_regc_jump_actions_template(struct rte_eth_dev *dev,
10223 : : struct rte_flow_error *error)
10224 : : {
10225 [ # # ]: 0 : uint32_t marker_mask = flow_hw_esw_mgr_regc_marker_mask(dev);
10226 : 0 : uint32_t marker_bits = flow_hw_esw_mgr_regc_marker(dev);
10227 : 0 : struct rte_flow_actions_template_attr attr = {
10228 : : .transfer = 1,
10229 : : };
10230 [ # # ]: 0 : struct rte_flow_action_modify_field set_reg_v = {
10231 : : .operation = RTE_FLOW_MODIFY_SET,
10232 : : .dst = {
10233 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
10234 : : .tag_index = REG_C_0,
10235 : : },
10236 : : .src = {
10237 : : .field = RTE_FLOW_FIELD_VALUE,
10238 : : },
10239 : : .width = rte_popcount32(marker_mask),
10240 : : };
10241 : 0 : struct rte_flow_action_modify_field set_reg_m = {
10242 : : .operation = RTE_FLOW_MODIFY_SET,
10243 : : .dst = {
10244 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
10245 : : .level = UINT8_MAX,
10246 : : .tag_index = UINT8_MAX,
10247 : : .offset = UINT32_MAX,
10248 : : },
10249 : : .src = {
10250 : : .field = RTE_FLOW_FIELD_VALUE,
10251 : : },
10252 : : .width = UINT32_MAX,
10253 : : };
10254 : 0 : struct rte_flow_action_jump jump_v = {
10255 : : .group = MLX5_HW_LOWEST_USABLE_GROUP,
10256 : : };
10257 : 0 : struct rte_flow_action_jump jump_m = {
10258 : : .group = UINT32_MAX,
10259 : : };
10260 : 0 : struct rte_flow_action actions_v[] = {
10261 : : {
10262 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
10263 : : .conf = &set_reg_v,
10264 : : },
10265 : : {
10266 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
10267 : : .conf = &jump_v,
10268 : : },
10269 : : {
10270 : : .type = RTE_FLOW_ACTION_TYPE_END,
10271 : : }
10272 : : };
10273 : 0 : struct rte_flow_action actions_m[] = {
10274 : : {
10275 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
10276 : : .conf = &set_reg_m,
10277 : : },
10278 : : {
10279 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
10280 : : .conf = &jump_m,
10281 : : },
10282 : : {
10283 : : .type = RTE_FLOW_ACTION_TYPE_END,
10284 : : }
10285 : : };
10286 : :
10287 [ # # ]: 0 : set_reg_v.dst.offset = rte_bsf32(marker_mask);
10288 : : rte_memcpy(set_reg_v.src.value, &marker_bits, sizeof(marker_bits));
10289 : : rte_memcpy(set_reg_m.src.value, &marker_mask, sizeof(marker_mask));
10290 : 0 : return flow_hw_actions_template_create(dev, &attr, actions_v, actions_m, error);
10291 : : }
10292 : :
10293 : : /**
10294 : : * Creates a flow actions template with an unmasked JUMP action. Flows
10295 : : * based on this template will perform a jump to some group. This template
10296 : : * is used to set up tables for control flows.
10297 : : *
10298 : : * @param dev
10299 : : * Pointer to Ethernet device.
10300 : : * @param group
10301 : : * Destination group for this action template.
10302 : : * @param error
10303 : : * Pointer to error structure.
10304 : : *
10305 : : * @return
10306 : : * Pointer to flow actions template on success, NULL otherwise.
10307 : : */
10308 : : static struct rte_flow_actions_template *
10309 : 0 : flow_hw_create_ctrl_jump_actions_template(struct rte_eth_dev *dev,
10310 : : uint32_t group,
10311 : : struct rte_flow_error *error)
10312 : : {
10313 : 0 : struct rte_flow_actions_template_attr attr = {
10314 : : .transfer = 1,
10315 : : };
10316 : 0 : struct rte_flow_action_jump jump_v = {
10317 : : .group = group,
10318 : : };
10319 : 0 : struct rte_flow_action_jump jump_m = {
10320 : : .group = UINT32_MAX,
10321 : : };
10322 : 0 : struct rte_flow_action actions_v[] = {
10323 : : {
10324 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
10325 : : .conf = &jump_v,
10326 : : },
10327 : : {
10328 : : .type = RTE_FLOW_ACTION_TYPE_END,
10329 : : }
10330 : : };
10331 : 0 : struct rte_flow_action actions_m[] = {
10332 : : {
10333 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
10334 : : .conf = &jump_m,
10335 : : },
10336 : : {
10337 : : .type = RTE_FLOW_ACTION_TYPE_END,
10338 : : }
10339 : : };
10340 : :
10341 : 0 : return flow_hw_actions_template_create(dev, &attr, actions_v,
10342 : : actions_m, error);
10343 : : }
10344 : :
10345 : : /**
10346 : : * Creates a flow action template with a unmasked REPRESENTED_PORT action.
10347 : : * It is used to create control flow tables.
10348 : : *
10349 : : * @param dev
10350 : : * Pointer to Ethernet device.
10351 : : * @param error
10352 : : * Pointer to error structure.
10353 : : *
10354 : : * @return
10355 : : * Pointer to flow action template on success, NULL otherwise.
10356 : : */
10357 : : static struct rte_flow_actions_template *
10358 : 0 : flow_hw_create_ctrl_port_actions_template(struct rte_eth_dev *dev,
10359 : : struct rte_flow_error *error)
10360 : : {
10361 : 0 : struct rte_flow_actions_template_attr attr = {
10362 : : .transfer = 1,
10363 : : };
10364 : 0 : struct rte_flow_action_ethdev port_v = {
10365 : : .port_id = 0,
10366 : : };
10367 : 0 : struct rte_flow_action actions_v[] = {
10368 : : {
10369 : : .type = RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT,
10370 : : .conf = &port_v,
10371 : : },
10372 : : {
10373 : : .type = RTE_FLOW_ACTION_TYPE_END,
10374 : : }
10375 : : };
10376 : 0 : struct rte_flow_action_ethdev port_m = {
10377 : : .port_id = 0,
10378 : : };
10379 : 0 : struct rte_flow_action actions_m[] = {
10380 : : {
10381 : : .type = RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT,
10382 : : .conf = &port_m,
10383 : : },
10384 : : {
10385 : : .type = RTE_FLOW_ACTION_TYPE_END,
10386 : : }
10387 : : };
10388 : :
10389 : 0 : return flow_hw_actions_template_create(dev, &attr, actions_v, actions_m, error);
10390 : : }
10391 : :
10392 : : /*
10393 : : * Creating an actions template to use header modify action for register
10394 : : * copying. This template is used to set up a table for copy flow.
10395 : : *
10396 : : * @param dev
10397 : : * Pointer to Ethernet device.
10398 : : * @param error
10399 : : * Pointer to error structure.
10400 : : *
10401 : : * @return
10402 : : * Pointer to flow actions template on success, NULL otherwise.
10403 : : */
10404 : : static struct rte_flow_actions_template *
10405 : 0 : flow_hw_create_tx_default_mreg_copy_actions_template(struct rte_eth_dev *dev,
10406 : : struct rte_flow_error *error)
10407 : : {
10408 : 0 : struct rte_flow_actions_template_attr tx_act_attr = {
10409 : : .egress = 1,
10410 : : };
10411 : 0 : const struct rte_flow_action_modify_field mreg_action = {
10412 : : .operation = RTE_FLOW_MODIFY_SET,
10413 : : .dst = {
10414 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
10415 : : .tag_index = REG_C_1,
10416 : : },
10417 : : .src = {
10418 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
10419 : : .tag_index = REG_A,
10420 : : },
10421 : : .width = 32,
10422 : : };
10423 : 0 : const struct rte_flow_action_modify_field mreg_mask = {
10424 : : .operation = RTE_FLOW_MODIFY_SET,
10425 : : .dst = {
10426 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
10427 : : .level = UINT8_MAX,
10428 : : .tag_index = UINT8_MAX,
10429 : : .offset = UINT32_MAX,
10430 : : },
10431 : : .src = {
10432 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
10433 : : .level = UINT8_MAX,
10434 : : .tag_index = UINT8_MAX,
10435 : : .offset = UINT32_MAX,
10436 : : },
10437 : : .width = UINT32_MAX,
10438 : : };
10439 : 0 : const struct rte_flow_action_jump jump_action = {
10440 : : .group = 1,
10441 : : };
10442 : 0 : const struct rte_flow_action_jump jump_mask = {
10443 : : .group = UINT32_MAX,
10444 : : };
10445 : 0 : const struct rte_flow_action actions[] = {
10446 : : [0] = {
10447 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
10448 : : .conf = &mreg_action,
10449 : : },
10450 : : [1] = {
10451 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
10452 : : .conf = &jump_action,
10453 : : },
10454 : : [2] = {
10455 : : .type = RTE_FLOW_ACTION_TYPE_END,
10456 : : },
10457 : : };
10458 : 0 : const struct rte_flow_action masks[] = {
10459 : : [0] = {
10460 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
10461 : : .conf = &mreg_mask,
10462 : : },
10463 : : [1] = {
10464 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
10465 : : .conf = &jump_mask,
10466 : : },
10467 : : [2] = {
10468 : : .type = RTE_FLOW_ACTION_TYPE_END,
10469 : : },
10470 : : };
10471 : :
10472 : 0 : return flow_hw_actions_template_create(dev, &tx_act_attr, actions,
10473 : : masks, error);
10474 : : }
10475 : :
10476 : : /*
10477 : : * Creating an actions template to use default miss to re-route packets to the
10478 : : * kernel driver stack.
10479 : : * On root table, only DEFAULT_MISS action can be used.
10480 : : *
10481 : : * @param dev
10482 : : * Pointer to Ethernet device.
10483 : : * @param error
10484 : : * Pointer to error structure.
10485 : : *
10486 : : * @return
10487 : : * Pointer to flow actions template on success, NULL otherwise.
10488 : : */
10489 : : static struct rte_flow_actions_template *
10490 : 0 : flow_hw_create_lacp_rx_actions_template(struct rte_eth_dev *dev, struct rte_flow_error *error)
10491 : : {
10492 : 0 : struct rte_flow_actions_template_attr act_attr = {
10493 : : .ingress = 1,
10494 : : };
10495 : 0 : const struct rte_flow_action actions[] = {
10496 : : [0] = {
10497 : : .type = (enum rte_flow_action_type)
10498 : : MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS,
10499 : : },
10500 : : [1] = {
10501 : : .type = RTE_FLOW_ACTION_TYPE_END,
10502 : : },
10503 : : };
10504 : :
10505 : 0 : return flow_hw_actions_template_create(dev, &act_attr, actions, actions, error);
10506 : : }
10507 : :
10508 : : /**
10509 : : * Creates a control flow table used to transfer traffic from E-Switch Manager
10510 : : * and TX queues from group 0 to group 1.
10511 : : *
10512 : : * @param dev
10513 : : * Pointer to Ethernet device.
10514 : : * @param it
10515 : : * Pointer to flow pattern template.
10516 : : * @param at
10517 : : * Pointer to flow actions template.
10518 : : * @param error
10519 : : * Pointer to error structure.
10520 : : *
10521 : : * @return
10522 : : * Pointer to flow table on success, NULL otherwise.
10523 : : */
10524 : : static struct rte_flow_template_table*
10525 : 0 : flow_hw_create_ctrl_sq_miss_root_table(struct rte_eth_dev *dev,
10526 : : struct rte_flow_pattern_template *it,
10527 : : struct rte_flow_actions_template *at,
10528 : : struct rte_flow_error *error)
10529 : : {
10530 : 0 : struct rte_flow_template_table_attr attr = {
10531 : : .flow_attr = {
10532 : : .group = 0,
10533 : : .priority = MLX5_HW_LOWEST_PRIO_ROOT,
10534 : : .ingress = 0,
10535 : : .egress = 0,
10536 : : .transfer = 1,
10537 : : },
10538 : : .nb_flows = MLX5_HW_CTRL_FLOW_NB_RULES,
10539 : : };
10540 : 0 : struct mlx5_flow_template_table_cfg cfg = {
10541 : : .attr = attr,
10542 : : .external = false,
10543 : : };
10544 : :
10545 : 0 : return flow_hw_table_create(dev, &cfg, &it, 1, &at, 1, error);
10546 : : }
10547 : :
10548 : :
10549 : : /**
10550 : : * Creates a control flow table used to transfer traffic from E-Switch Manager
10551 : : * and TX queues from group 0 to group 1.
10552 : : *
10553 : : * @param dev
10554 : : * Pointer to Ethernet device.
10555 : : * @param it
10556 : : * Pointer to flow pattern template.
10557 : : * @param at
10558 : : * Pointer to flow actions template.
10559 : : * @param error
10560 : : * Pointer to error structure.
10561 : : *
10562 : : * @return
10563 : : * Pointer to flow table on success, NULL otherwise.
10564 : : */
10565 : : static struct rte_flow_template_table*
10566 : 0 : flow_hw_create_ctrl_sq_miss_table(struct rte_eth_dev *dev,
10567 : : struct rte_flow_pattern_template *it,
10568 : : struct rte_flow_actions_template *at,
10569 : : struct rte_flow_error *error)
10570 : : {
10571 : 0 : struct rte_flow_template_table_attr attr = {
10572 : : .flow_attr = {
10573 : : .group = 1,
10574 : : .priority = MLX5_HW_LOWEST_PRIO_NON_ROOT,
10575 : : .ingress = 0,
10576 : : .egress = 0,
10577 : : .transfer = 1,
10578 : : },
10579 : : .nb_flows = MLX5_HW_CTRL_FLOW_NB_RULES,
10580 : : };
10581 : 0 : struct mlx5_flow_template_table_cfg cfg = {
10582 : : .attr = attr,
10583 : : .external = false,
10584 : : };
10585 : :
10586 : 0 : return flow_hw_table_create(dev, &cfg, &it, 1, &at, 1, error);
10587 : : }
10588 : :
10589 : : /*
10590 : : * Creating the default Tx metadata copy table on NIC Tx group 0.
10591 : : *
10592 : : * @param dev
10593 : : * Pointer to Ethernet device.
10594 : : * @param pt
10595 : : * Pointer to flow pattern template.
10596 : : * @param at
10597 : : * Pointer to flow actions template.
10598 : : * @param error
10599 : : * Pointer to error structure.
10600 : : *
10601 : : * @return
10602 : : * Pointer to flow table on success, NULL otherwise.
10603 : : */
10604 : : static struct rte_flow_template_table*
10605 : 0 : flow_hw_create_tx_default_mreg_copy_table(struct rte_eth_dev *dev,
10606 : : struct rte_flow_pattern_template *pt,
10607 : : struct rte_flow_actions_template *at,
10608 : : struct rte_flow_error *error)
10609 : : {
10610 : 0 : struct rte_flow_template_table_attr tx_tbl_attr = {
10611 : : .flow_attr = {
10612 : : .group = 0, /* Root */
10613 : : .priority = MLX5_HW_LOWEST_PRIO_ROOT,
10614 : : .egress = 1,
10615 : : },
10616 : : .nb_flows = 1, /* One default flow rule for all. */
10617 : : };
10618 : 0 : struct mlx5_flow_template_table_cfg tx_tbl_cfg = {
10619 : : .attr = tx_tbl_attr,
10620 : : .external = false,
10621 : : };
10622 : :
10623 : 0 : return flow_hw_table_create(dev, &tx_tbl_cfg, &pt, 1, &at, 1, error);
10624 : : }
10625 : :
10626 : : /**
10627 : : * Creates a control flow table used to transfer traffic
10628 : : * from group 0 to group 1.
10629 : : *
10630 : : * @param dev
10631 : : * Pointer to Ethernet device.
10632 : : * @param it
10633 : : * Pointer to flow pattern template.
10634 : : * @param at
10635 : : * Pointer to flow actions template.
10636 : : * @param error
10637 : : * Pointer to error structure.
10638 : : *
10639 : : * @return
10640 : : * Pointer to flow table on success, NULL otherwise.
10641 : : */
10642 : : static struct rte_flow_template_table *
10643 : 0 : flow_hw_create_ctrl_jump_table(struct rte_eth_dev *dev,
10644 : : struct rte_flow_pattern_template *it,
10645 : : struct rte_flow_actions_template *at,
10646 : : struct rte_flow_error *error)
10647 : : {
10648 : 0 : struct rte_flow_template_table_attr attr = {
10649 : : .flow_attr = {
10650 : : .group = 0,
10651 : : .priority = 0,
10652 : : .ingress = 0,
10653 : : .egress = 0,
10654 : : .transfer = 1,
10655 : : },
10656 : : .nb_flows = MLX5_HW_CTRL_FLOW_NB_RULES,
10657 : : };
10658 : 0 : struct mlx5_flow_template_table_cfg cfg = {
10659 : : .attr = attr,
10660 : : .external = false,
10661 : : };
10662 : :
10663 : 0 : return flow_hw_table_create(dev, &cfg, &it, 1, &at, 1, error);
10664 : : }
10665 : :
10666 : : /**
10667 : : * Cleans up all template tables and pattern, and actions templates used for
10668 : : * FDB control flow rules.
10669 : : *
10670 : : * @param dev
10671 : : * Pointer to Ethernet device.
10672 : : */
10673 : : static void
10674 : 0 : flow_hw_cleanup_ctrl_fdb_tables(struct rte_eth_dev *dev)
10675 : : {
10676 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
10677 : : struct mlx5_flow_hw_ctrl_fdb *hw_ctrl_fdb;
10678 : :
10679 [ # # ]: 0 : if (!priv->hw_ctrl_fdb)
10680 : : return;
10681 : : hw_ctrl_fdb = priv->hw_ctrl_fdb;
10682 : : /* Clean up templates used for LACP default miss table. */
10683 [ # # ]: 0 : if (hw_ctrl_fdb->hw_lacp_rx_tbl)
10684 : 0 : claim_zero(flow_hw_table_destroy(dev, hw_ctrl_fdb->hw_lacp_rx_tbl, NULL));
10685 [ # # ]: 0 : if (hw_ctrl_fdb->lacp_rx_actions_tmpl)
10686 : 0 : claim_zero(flow_hw_actions_template_destroy(dev, hw_ctrl_fdb->lacp_rx_actions_tmpl,
10687 : : NULL));
10688 [ # # ]: 0 : if (hw_ctrl_fdb->lacp_rx_items_tmpl)
10689 : 0 : claim_zero(flow_hw_pattern_template_destroy(dev, hw_ctrl_fdb->lacp_rx_items_tmpl,
10690 : : NULL));
10691 : : /* Clean up templates used for default Tx metadata copy. */
10692 [ # # ]: 0 : if (hw_ctrl_fdb->hw_tx_meta_cpy_tbl)
10693 : 0 : claim_zero(flow_hw_table_destroy(dev, hw_ctrl_fdb->hw_tx_meta_cpy_tbl, NULL));
10694 [ # # ]: 0 : if (hw_ctrl_fdb->tx_meta_actions_tmpl)
10695 : 0 : claim_zero(flow_hw_actions_template_destroy(dev, hw_ctrl_fdb->tx_meta_actions_tmpl,
10696 : : NULL));
10697 [ # # ]: 0 : if (hw_ctrl_fdb->tx_meta_items_tmpl)
10698 : 0 : claim_zero(flow_hw_pattern_template_destroy(dev, hw_ctrl_fdb->tx_meta_items_tmpl,
10699 : : NULL));
10700 : : /* Clean up templates used for default FDB jump rule. */
10701 [ # # ]: 0 : if (hw_ctrl_fdb->hw_esw_zero_tbl)
10702 : 0 : claim_zero(flow_hw_table_destroy(dev, hw_ctrl_fdb->hw_esw_zero_tbl, NULL));
10703 [ # # ]: 0 : if (hw_ctrl_fdb->jump_one_actions_tmpl)
10704 : 0 : claim_zero(flow_hw_actions_template_destroy(dev, hw_ctrl_fdb->jump_one_actions_tmpl,
10705 : : NULL));
10706 [ # # ]: 0 : if (hw_ctrl_fdb->port_items_tmpl)
10707 : 0 : claim_zero(flow_hw_pattern_template_destroy(dev, hw_ctrl_fdb->port_items_tmpl,
10708 : : NULL));
10709 : : /* Clean up templates used for default SQ miss flow rules - non-root table. */
10710 [ # # ]: 0 : if (hw_ctrl_fdb->hw_esw_sq_miss_tbl)
10711 : 0 : claim_zero(flow_hw_table_destroy(dev, hw_ctrl_fdb->hw_esw_sq_miss_tbl, NULL));
10712 [ # # ]: 0 : if (hw_ctrl_fdb->regc_sq_items_tmpl)
10713 : 0 : claim_zero(flow_hw_pattern_template_destroy(dev, hw_ctrl_fdb->regc_sq_items_tmpl,
10714 : : NULL));
10715 [ # # ]: 0 : if (hw_ctrl_fdb->port_actions_tmpl)
10716 : 0 : claim_zero(flow_hw_actions_template_destroy(dev, hw_ctrl_fdb->port_actions_tmpl,
10717 : : NULL));
10718 : : /* Clean up templates used for default SQ miss flow rules - root table. */
10719 [ # # ]: 0 : if (hw_ctrl_fdb->hw_esw_sq_miss_root_tbl)
10720 : 0 : claim_zero(flow_hw_table_destroy(dev, hw_ctrl_fdb->hw_esw_sq_miss_root_tbl, NULL));
10721 [ # # ]: 0 : if (hw_ctrl_fdb->regc_jump_actions_tmpl)
10722 : 0 : claim_zero(flow_hw_actions_template_destroy(dev,
10723 : : hw_ctrl_fdb->regc_jump_actions_tmpl, NULL));
10724 [ # # ]: 0 : if (hw_ctrl_fdb->esw_mgr_items_tmpl)
10725 : 0 : claim_zero(flow_hw_pattern_template_destroy(dev, hw_ctrl_fdb->esw_mgr_items_tmpl,
10726 : : NULL));
10727 : : /* Clean up templates structure for FDB control flow rules. */
10728 : 0 : mlx5_free(hw_ctrl_fdb);
10729 : 0 : priv->hw_ctrl_fdb = NULL;
10730 : : }
10731 : :
10732 : : /*
10733 : : * Create a table on the root group to for the LACP traffic redirecting.
10734 : : *
10735 : : * @param dev
10736 : : * Pointer to Ethernet device.
10737 : : * @param it
10738 : : * Pointer to flow pattern template.
10739 : : * @param at
10740 : : * Pointer to flow actions template.
10741 : : *
10742 : : * @return
10743 : : * Pointer to flow table on success, NULL otherwise.
10744 : : */
10745 : : static struct rte_flow_template_table *
10746 : 0 : flow_hw_create_lacp_rx_table(struct rte_eth_dev *dev,
10747 : : struct rte_flow_pattern_template *it,
10748 : : struct rte_flow_actions_template *at,
10749 : : struct rte_flow_error *error)
10750 : : {
10751 : 0 : struct rte_flow_template_table_attr attr = {
10752 : : .flow_attr = {
10753 : : .group = 0,
10754 : : .priority = 0,
10755 : : .ingress = 1,
10756 : : .egress = 0,
10757 : : .transfer = 0,
10758 : : },
10759 : : .nb_flows = 1,
10760 : : };
10761 : 0 : struct mlx5_flow_template_table_cfg cfg = {
10762 : : .attr = attr,
10763 : : .external = false,
10764 : : };
10765 : :
10766 : 0 : return flow_hw_table_create(dev, &cfg, &it, 1, &at, 1, error);
10767 : : }
10768 : :
10769 : : /**
10770 : : * Creates a set of flow tables used to create control flows used
10771 : : * when E-Switch is engaged.
10772 : : *
10773 : : * @param dev
10774 : : * Pointer to Ethernet device.
10775 : : * @param error
10776 : : * Pointer to error structure.
10777 : : *
10778 : : * @return
10779 : : * 0 on success, negative values otherwise
10780 : : */
10781 : : static int
10782 : 0 : flow_hw_create_ctrl_tables(struct rte_eth_dev *dev, struct rte_flow_error *error)
10783 : : {
10784 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
10785 : : struct mlx5_flow_hw_ctrl_fdb *hw_ctrl_fdb;
10786 : 0 : uint32_t xmeta = priv->sh->config.dv_xmeta_en;
10787 : 0 : uint32_t repr_matching = priv->sh->config.repr_matching;
10788 : 0 : uint32_t fdb_def_rule = priv->sh->config.fdb_def_rule;
10789 : :
10790 : : MLX5_ASSERT(priv->hw_ctrl_fdb == NULL);
10791 : 0 : hw_ctrl_fdb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*hw_ctrl_fdb), 0, SOCKET_ID_ANY);
10792 [ # # ]: 0 : if (!hw_ctrl_fdb) {
10793 : 0 : DRV_LOG(ERR, "port %u failed to allocate memory for FDB control flow templates",
10794 : : dev->data->port_id);
10795 : 0 : rte_errno = ENOMEM;
10796 : 0 : goto err;
10797 : : }
10798 : 0 : priv->hw_ctrl_fdb = hw_ctrl_fdb;
10799 [ # # ]: 0 : if (fdb_def_rule) {
10800 : : /* Create templates and table for default SQ miss flow rules - root table. */
10801 : 0 : hw_ctrl_fdb->esw_mgr_items_tmpl =
10802 : 0 : flow_hw_create_ctrl_esw_mgr_pattern_template(dev, error);
10803 [ # # ]: 0 : if (!hw_ctrl_fdb->esw_mgr_items_tmpl) {
10804 : 0 : DRV_LOG(ERR, "port %u failed to create E-Switch Manager item"
10805 : : " template for control flows", dev->data->port_id);
10806 : 0 : goto err;
10807 : : }
10808 : 0 : hw_ctrl_fdb->regc_jump_actions_tmpl =
10809 : 0 : flow_hw_create_ctrl_regc_jump_actions_template(dev, error);
10810 [ # # ]: 0 : if (!hw_ctrl_fdb->regc_jump_actions_tmpl) {
10811 : 0 : DRV_LOG(ERR, "port %u failed to create REG_C set and jump action template"
10812 : : " for control flows", dev->data->port_id);
10813 : 0 : goto err;
10814 : : }
10815 : 0 : hw_ctrl_fdb->hw_esw_sq_miss_root_tbl =
10816 : 0 : flow_hw_create_ctrl_sq_miss_root_table
10817 : : (dev, hw_ctrl_fdb->esw_mgr_items_tmpl,
10818 : : hw_ctrl_fdb->regc_jump_actions_tmpl, error);
10819 [ # # ]: 0 : if (!hw_ctrl_fdb->hw_esw_sq_miss_root_tbl) {
10820 : 0 : DRV_LOG(ERR, "port %u failed to create table for default sq miss (root table)"
10821 : : " for control flows", dev->data->port_id);
10822 : 0 : goto err;
10823 : : }
10824 : : /* Create templates and table for default SQ miss flow rules - non-root table. */
10825 : 0 : hw_ctrl_fdb->regc_sq_items_tmpl =
10826 : 0 : flow_hw_create_ctrl_regc_sq_pattern_template(dev, error);
10827 [ # # ]: 0 : if (!hw_ctrl_fdb->regc_sq_items_tmpl) {
10828 : 0 : DRV_LOG(ERR, "port %u failed to create SQ item template for"
10829 : : " control flows", dev->data->port_id);
10830 : 0 : goto err;
10831 : : }
10832 : 0 : hw_ctrl_fdb->port_actions_tmpl =
10833 : 0 : flow_hw_create_ctrl_port_actions_template(dev, error);
10834 [ # # ]: 0 : if (!hw_ctrl_fdb->port_actions_tmpl) {
10835 : 0 : DRV_LOG(ERR, "port %u failed to create port action template"
10836 : : " for control flows", dev->data->port_id);
10837 : 0 : goto err;
10838 : : }
10839 : 0 : hw_ctrl_fdb->hw_esw_sq_miss_tbl =
10840 : 0 : flow_hw_create_ctrl_sq_miss_table
10841 : : (dev, hw_ctrl_fdb->regc_sq_items_tmpl,
10842 : : hw_ctrl_fdb->port_actions_tmpl, error);
10843 [ # # ]: 0 : if (!hw_ctrl_fdb->hw_esw_sq_miss_tbl) {
10844 : 0 : DRV_LOG(ERR, "port %u failed to create table for default sq miss (non-root table)"
10845 : : " for control flows", dev->data->port_id);
10846 : 0 : goto err;
10847 : : }
10848 : : /* Create templates and table for default FDB jump flow rules. */
10849 : 0 : hw_ctrl_fdb->port_items_tmpl =
10850 : 0 : flow_hw_create_ctrl_port_pattern_template(dev, error);
10851 [ # # ]: 0 : if (!hw_ctrl_fdb->port_items_tmpl) {
10852 : 0 : DRV_LOG(ERR, "port %u failed to create SQ item template for"
10853 : : " control flows", dev->data->port_id);
10854 : 0 : goto err;
10855 : : }
10856 : 0 : hw_ctrl_fdb->jump_one_actions_tmpl =
10857 : 0 : flow_hw_create_ctrl_jump_actions_template
10858 : : (dev, MLX5_HW_LOWEST_USABLE_GROUP, error);
10859 [ # # ]: 0 : if (!hw_ctrl_fdb->jump_one_actions_tmpl) {
10860 : 0 : DRV_LOG(ERR, "port %u failed to create jump action template"
10861 : : " for control flows", dev->data->port_id);
10862 : 0 : goto err;
10863 : : }
10864 : 0 : hw_ctrl_fdb->hw_esw_zero_tbl = flow_hw_create_ctrl_jump_table
10865 : : (dev, hw_ctrl_fdb->port_items_tmpl,
10866 : : hw_ctrl_fdb->jump_one_actions_tmpl, error);
10867 [ # # ]: 0 : if (!hw_ctrl_fdb->hw_esw_zero_tbl) {
10868 : 0 : DRV_LOG(ERR, "port %u failed to create table for default jump to group 1"
10869 : : " for control flows", dev->data->port_id);
10870 : 0 : goto err;
10871 : : }
10872 : : }
10873 : : /* Create templates and table for default Tx metadata copy flow rule. */
10874 [ # # ]: 0 : if (!repr_matching && xmeta == MLX5_XMETA_MODE_META32_HWS) {
10875 : 0 : hw_ctrl_fdb->tx_meta_items_tmpl =
10876 : 0 : flow_hw_create_tx_default_mreg_copy_pattern_template(dev, error);
10877 [ # # ]: 0 : if (!hw_ctrl_fdb->tx_meta_items_tmpl) {
10878 : 0 : DRV_LOG(ERR, "port %u failed to Tx metadata copy pattern"
10879 : : " template for control flows", dev->data->port_id);
10880 : 0 : goto err;
10881 : : }
10882 : 0 : hw_ctrl_fdb->tx_meta_actions_tmpl =
10883 : 0 : flow_hw_create_tx_default_mreg_copy_actions_template(dev, error);
10884 [ # # ]: 0 : if (!hw_ctrl_fdb->tx_meta_actions_tmpl) {
10885 : 0 : DRV_LOG(ERR, "port %u failed to Tx metadata copy actions"
10886 : : " template for control flows", dev->data->port_id);
10887 : 0 : goto err;
10888 : : }
10889 : 0 : hw_ctrl_fdb->hw_tx_meta_cpy_tbl =
10890 : 0 : flow_hw_create_tx_default_mreg_copy_table
10891 : : (dev, hw_ctrl_fdb->tx_meta_items_tmpl,
10892 : : hw_ctrl_fdb->tx_meta_actions_tmpl, error);
10893 [ # # ]: 0 : if (!hw_ctrl_fdb->hw_tx_meta_cpy_tbl) {
10894 : 0 : DRV_LOG(ERR, "port %u failed to create table for default"
10895 : : " Tx metadata copy flow rule", dev->data->port_id);
10896 : 0 : goto err;
10897 : : }
10898 : : }
10899 : : /* Create LACP default miss table. */
10900 [ # # # # : 0 : if (!priv->sh->config.lacp_by_user && priv->pf_bond >= 0 && priv->master) {
# # ]
10901 : 0 : hw_ctrl_fdb->lacp_rx_items_tmpl =
10902 : 0 : flow_hw_create_lacp_rx_pattern_template(dev, error);
10903 [ # # ]: 0 : if (!hw_ctrl_fdb->lacp_rx_items_tmpl) {
10904 : 0 : DRV_LOG(ERR, "port %u failed to create pattern template"
10905 : : " for LACP Rx traffic", dev->data->port_id);
10906 : 0 : goto err;
10907 : : }
10908 : 0 : hw_ctrl_fdb->lacp_rx_actions_tmpl =
10909 : 0 : flow_hw_create_lacp_rx_actions_template(dev, error);
10910 [ # # ]: 0 : if (!hw_ctrl_fdb->lacp_rx_actions_tmpl) {
10911 : 0 : DRV_LOG(ERR, "port %u failed to create actions template"
10912 : : " for LACP Rx traffic", dev->data->port_id);
10913 : 0 : goto err;
10914 : : }
10915 : 0 : hw_ctrl_fdb->hw_lacp_rx_tbl = flow_hw_create_lacp_rx_table
10916 : : (dev, hw_ctrl_fdb->lacp_rx_items_tmpl,
10917 : : hw_ctrl_fdb->lacp_rx_actions_tmpl, error);
10918 [ # # ]: 0 : if (!hw_ctrl_fdb->hw_lacp_rx_tbl) {
10919 : 0 : DRV_LOG(ERR, "port %u failed to create template table for"
10920 : : " for LACP Rx traffic", dev->data->port_id);
10921 : 0 : goto err;
10922 : : }
10923 : : }
10924 : : return 0;
10925 : :
10926 : 0 : err:
10927 : 0 : flow_hw_cleanup_ctrl_fdb_tables(dev);
10928 : 0 : return -EINVAL;
10929 : : }
10930 : :
10931 : : static void
10932 : 0 : flow_hw_ct_mng_destroy(struct rte_eth_dev *dev,
10933 : : struct mlx5_aso_ct_pools_mng *ct_mng)
10934 : : {
10935 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
10936 : :
10937 : 0 : mlx5_aso_ct_queue_uninit(priv->sh, ct_mng);
10938 : 0 : mlx5_free(ct_mng);
10939 : 0 : }
10940 : :
10941 : : static void
10942 : 0 : flow_hw_ct_pool_destroy(struct rte_eth_dev *dev,
10943 : : struct mlx5_aso_ct_pool *pool)
10944 : : {
10945 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
10946 : :
10947 [ # # ]: 0 : if (pool->dr_action)
10948 : 0 : mlx5dr_action_destroy(pool->dr_action);
10949 [ # # ]: 0 : if (!priv->shared_host) {
10950 [ # # ]: 0 : if (pool->devx_obj)
10951 : 0 : claim_zero(mlx5_devx_cmd_destroy(pool->devx_obj));
10952 [ # # ]: 0 : if (pool->cts)
10953 : 0 : mlx5_ipool_destroy(pool->cts);
10954 : : }
10955 : 0 : mlx5_free(pool);
10956 : 0 : }
10957 : :
10958 : : static struct mlx5_aso_ct_pool *
10959 : 0 : flow_hw_ct_pool_create(struct rte_eth_dev *dev,
10960 : : uint32_t nb_conn_tracks)
10961 : : {
10962 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
10963 : : struct mlx5_aso_ct_pool *pool;
10964 : : struct mlx5_devx_obj *obj;
10965 : : uint32_t nb_cts = rte_align32pow2(nb_conn_tracks);
10966 : : uint32_t log_obj_size = rte_log2_u32(nb_cts);
10967 : 0 : struct mlx5_indexed_pool_config cfg = {
10968 : : .size = sizeof(struct mlx5_aso_ct_action),
10969 : : .trunk_size = 1 << 12,
10970 : : .per_core_cache = 1 << 13,
10971 : : .need_lock = 1,
10972 : 0 : .release_mem_en = !!priv->sh->config.reclaim_mode,
10973 : : .malloc = mlx5_malloc,
10974 : : .free = mlx5_free,
10975 : : .type = "mlx5_hw_ct_action",
10976 : : };
10977 : : int reg_id;
10978 : : uint32_t flags = 0;
10979 : :
10980 : 0 : pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
10981 [ # # ]: 0 : if (!pool) {
10982 : 0 : rte_errno = ENOMEM;
10983 : 0 : return NULL;
10984 : : }
10985 [ # # ]: 0 : if (!priv->shared_host) {
10986 : : /*
10987 : : * No need for local cache if CT number is a small number. Since
10988 : : * flow insertion rate will be very limited in that case. Here let's
10989 : : * set the number to less than default trunk size 4K.
10990 : : */
10991 [ # # ]: 0 : if (nb_cts <= cfg.trunk_size) {
10992 : 0 : cfg.per_core_cache = 0;
10993 : 0 : cfg.trunk_size = nb_cts;
10994 [ # # ]: 0 : } else if (nb_cts <= MLX5_HW_IPOOL_SIZE_THRESHOLD) {
10995 : 0 : cfg.per_core_cache = MLX5_HW_IPOOL_CACHE_MIN;
10996 : : }
10997 : 0 : cfg.max_idx = nb_cts;
10998 : 0 : pool->cts = mlx5_ipool_create(&cfg);
10999 [ # # ]: 0 : if (!pool->cts)
11000 : 0 : goto err;
11001 : 0 : obj = mlx5_devx_cmd_create_conn_track_offload_obj(priv->sh->cdev->ctx,
11002 : 0 : priv->sh->cdev->pdn,
11003 : : log_obj_size);
11004 [ # # ]: 0 : if (!obj) {
11005 : 0 : rte_errno = ENODATA;
11006 : 0 : DRV_LOG(ERR, "Failed to create conn_track_offload_obj using DevX.");
11007 : 0 : goto err;
11008 : : }
11009 : 0 : pool->devx_obj = obj;
11010 : : } else {
11011 : : struct rte_eth_dev *host_dev = priv->shared_host;
11012 : 0 : struct mlx5_priv *host_priv = host_dev->data->dev_private;
11013 : :
11014 : 0 : pool->devx_obj = host_priv->hws_ctpool->devx_obj;
11015 : 0 : pool->cts = host_priv->hws_ctpool->cts;
11016 : : MLX5_ASSERT(pool->cts);
11017 : : MLX5_ASSERT(!nb_conn_tracks);
11018 : : }
11019 : 0 : reg_id = mlx5_flow_get_reg_id(dev, MLX5_ASO_CONNTRACK, 0, NULL);
11020 : : flags |= MLX5DR_ACTION_FLAG_HWS_RX | MLX5DR_ACTION_FLAG_HWS_TX;
11021 [ # # # # ]: 0 : if (priv->sh->config.dv_esw_en && priv->master) {
11022 : 0 : flags |= ((is_unified_fdb(priv)) ?
11023 : : (MLX5DR_ACTION_FLAG_HWS_FDB_RX |
11024 : : MLX5DR_ACTION_FLAG_HWS_FDB_TX |
11025 [ # # ]: 0 : MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED) :
11026 : : MLX5DR_ACTION_FLAG_HWS_FDB);
11027 : : }
11028 : 0 : pool->dr_action = mlx5dr_action_create_aso_ct(priv->dr_ctx,
11029 : 0 : (struct mlx5dr_devx_obj *)pool->devx_obj,
11030 : 0 : reg_id - REG_C_0, flags);
11031 [ # # ]: 0 : if (!pool->dr_action)
11032 : 0 : goto err;
11033 : 0 : pool->sq = priv->ct_mng->aso_sqs;
11034 : : /* Assign the last extra ASO SQ as public SQ. */
11035 : 0 : pool->shared_sq = &priv->ct_mng->aso_sqs[priv->nb_queue - 1];
11036 : 0 : return pool;
11037 : 0 : err:
11038 : 0 : flow_hw_ct_pool_destroy(dev, pool);
11039 : 0 : return NULL;
11040 : : }
11041 : :
11042 : : static int
11043 : 0 : mlx5_flow_ct_init(struct rte_eth_dev *dev,
11044 : : uint32_t nb_conn_tracks,
11045 : : uint16_t nb_queue)
11046 : : {
11047 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11048 : : uint32_t mem_size;
11049 : : int ret = -ENOMEM;
11050 : :
11051 [ # # ]: 0 : if (!priv->shared_host) {
11052 : 0 : mem_size = sizeof(struct mlx5_aso_sq) * nb_queue +
11053 : : sizeof(*priv->ct_mng);
11054 : 0 : priv->ct_mng = mlx5_malloc(MLX5_MEM_ZERO, mem_size,
11055 : : RTE_CACHE_LINE_SIZE,
11056 : : SOCKET_ID_ANY);
11057 [ # # ]: 0 : if (!priv->ct_mng)
11058 : 0 : goto err;
11059 : 0 : ret = mlx5_aso_ct_queue_init(priv->sh, priv->ct_mng,
11060 : : nb_queue);
11061 [ # # ]: 0 : if (ret)
11062 : 0 : goto err;
11063 : : }
11064 : 0 : priv->hws_ctpool = flow_hw_ct_pool_create(dev, nb_conn_tracks);
11065 [ # # ]: 0 : if (!priv->hws_ctpool)
11066 : 0 : goto err;
11067 : 0 : priv->sh->ct_aso_en = 1;
11068 : 0 : return 0;
11069 : :
11070 : 0 : err:
11071 [ # # ]: 0 : if (priv->hws_ctpool) {
11072 : 0 : flow_hw_ct_pool_destroy(dev, priv->hws_ctpool);
11073 : 0 : priv->hws_ctpool = NULL;
11074 : : }
11075 [ # # ]: 0 : if (priv->ct_mng) {
11076 : 0 : flow_hw_ct_mng_destroy(dev, priv->ct_mng);
11077 : 0 : priv->ct_mng = NULL;
11078 : : }
11079 : : return ret;
11080 : : }
11081 : :
11082 : : static void
11083 : 0 : flow_hw_destroy_vlan(struct rte_eth_dev *dev)
11084 : : {
11085 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11086 : : enum mlx5dr_table_type i;
11087 : :
11088 [ # # ]: 0 : for (i = MLX5DR_TABLE_TYPE_NIC_RX; i < MLX5DR_TABLE_TYPE_MAX; i++) {
11089 [ # # ]: 0 : if (priv->hw_pop_vlan[i]) {
11090 : 0 : mlx5dr_action_destroy(priv->hw_pop_vlan[i]);
11091 : 0 : priv->hw_pop_vlan[i] = NULL;
11092 : : }
11093 [ # # ]: 0 : if (priv->hw_push_vlan[i]) {
11094 : 0 : mlx5dr_action_destroy(priv->hw_push_vlan[i]);
11095 : 0 : priv->hw_push_vlan[i] = NULL;
11096 : : }
11097 : : }
11098 : 0 : }
11099 : :
11100 : : static int
11101 : 0 : _create_vlan(struct mlx5_priv *priv, enum mlx5dr_table_type type)
11102 : : {
11103 : 0 : const enum mlx5dr_action_flags flags[MLX5DR_TABLE_TYPE_MAX] = {
11104 : : MLX5DR_ACTION_FLAG_HWS_RX,
11105 : : MLX5DR_ACTION_FLAG_HWS_TX,
11106 : : MLX5DR_ACTION_FLAG_HWS_FDB,
11107 : : MLX5DR_ACTION_FLAG_HWS_FDB_RX,
11108 : : MLX5DR_ACTION_FLAG_HWS_FDB_TX,
11109 : : MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED,
11110 : : };
11111 : :
11112 : : /* rte_errno is set in the mlx5dr_action* functions. */
11113 : 0 : priv->hw_pop_vlan[type] =
11114 : 0 : mlx5dr_action_create_pop_vlan(priv->dr_ctx, flags[type]);
11115 [ # # ]: 0 : if (!priv->hw_pop_vlan[type])
11116 : 0 : return -rte_errno;
11117 : 0 : priv->hw_push_vlan[type] =
11118 : 0 : mlx5dr_action_create_push_vlan(priv->dr_ctx, flags[type]);
11119 [ # # ]: 0 : if (!priv->hw_push_vlan[type])
11120 : 0 : return -rte_errno;
11121 : : return 0;
11122 : : }
11123 : :
11124 : : static int
11125 : 0 : flow_hw_create_vlan(struct rte_eth_dev *dev)
11126 : : {
11127 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11128 : : enum mlx5dr_table_type i, from, to;
11129 : : int rc;
11130 : : bool unified_fdb = is_unified_fdb(priv);
11131 : :
11132 [ # # ]: 0 : for (i = MLX5DR_TABLE_TYPE_NIC_RX; i <= MLX5DR_TABLE_TYPE_NIC_TX; i++) {
11133 : 0 : rc = _create_vlan(priv, i);
11134 [ # # ]: 0 : if (rc)
11135 : 0 : return rc;
11136 : : }
11137 [ # # ]: 0 : from = unified_fdb ? MLX5DR_TABLE_TYPE_FDB_RX : MLX5DR_TABLE_TYPE_FDB;
11138 [ # # ]: 0 : to = unified_fdb ? MLX5DR_TABLE_TYPE_FDB_UNIFIED : MLX5DR_TABLE_TYPE_FDB;
11139 [ # # # # ]: 0 : if (priv->sh->config.dv_esw_en && priv->master) {
11140 [ # # ]: 0 : for (i = from; i <= to; i++) {
11141 : 0 : rc = _create_vlan(priv, i);
11142 [ # # ]: 0 : if (rc)
11143 : 0 : return rc;
11144 : : }
11145 : : }
11146 : : return 0;
11147 : : }
11148 : :
11149 : : static void
11150 : 0 : flow_hw_cleanup_ctrl_rx_tables(struct rte_eth_dev *dev)
11151 : : {
11152 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11153 : : unsigned int i;
11154 : : unsigned int j;
11155 : :
11156 [ # # ]: 0 : if (!priv->hw_ctrl_rx)
11157 : : return;
11158 [ # # ]: 0 : for (i = 0; i < MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_MAX; ++i) {
11159 [ # # ]: 0 : for (j = 0; j < MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX; ++j) {
11160 : 0 : struct rte_flow_template_table *tbl = priv->hw_ctrl_rx->tables[i][j].tbl;
11161 : 0 : struct rte_flow_pattern_template *pt = priv->hw_ctrl_rx->tables[i][j].pt;
11162 : :
11163 [ # # ]: 0 : if (tbl)
11164 : 0 : claim_zero(flow_hw_table_destroy(dev, tbl, NULL));
11165 [ # # ]: 0 : if (pt)
11166 : 0 : claim_zero(flow_hw_pattern_template_destroy(dev, pt, NULL));
11167 : : }
11168 : : }
11169 [ # # ]: 0 : for (i = 0; i < MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX; ++i) {
11170 : 0 : struct rte_flow_actions_template *at = priv->hw_ctrl_rx->rss[i];
11171 : :
11172 [ # # ]: 0 : if (at)
11173 : 0 : claim_zero(flow_hw_actions_template_destroy(dev, at, NULL));
11174 : : }
11175 : 0 : mlx5_free(priv->hw_ctrl_rx);
11176 : 0 : priv->hw_ctrl_rx = NULL;
11177 : : }
11178 : :
11179 : : static uint64_t
11180 : : flow_hw_ctrl_rx_rss_type_hash_types(const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
11181 : : {
11182 : : switch (rss_type) {
11183 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_NON_IP:
11184 : : return 0;
11185 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4:
11186 : : return RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_FRAG_IPV4 | RTE_ETH_RSS_NONFRAG_IPV4_OTHER;
11187 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_UDP:
11188 : : return RTE_ETH_RSS_NONFRAG_IPV4_UDP;
11189 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_TCP:
11190 : : return RTE_ETH_RSS_NONFRAG_IPV4_TCP;
11191 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6:
11192 : : return RTE_ETH_RSS_IPV6 | RTE_ETH_RSS_FRAG_IPV6 | RTE_ETH_RSS_NONFRAG_IPV6_OTHER;
11193 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_UDP:
11194 : : return RTE_ETH_RSS_NONFRAG_IPV6_UDP | RTE_ETH_RSS_IPV6_UDP_EX;
11195 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_TCP:
11196 : : return RTE_ETH_RSS_NONFRAG_IPV6_TCP | RTE_ETH_RSS_IPV6_TCP_EX;
11197 : : default:
11198 : : /* Should not reach here. */
11199 : : MLX5_ASSERT(false);
11200 : : return 0;
11201 : : }
11202 : : }
11203 : :
11204 : : static struct rte_flow_actions_template *
11205 : 0 : flow_hw_create_ctrl_rx_rss_template(struct rte_eth_dev *dev,
11206 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
11207 : : {
11208 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11209 : 0 : struct rte_flow_actions_template_attr attr = {
11210 : : .ingress = 1,
11211 : : };
11212 : : uint16_t queue[RTE_MAX_QUEUES_PER_PORT];
11213 : 0 : struct rte_flow_action_rss rss_conf = {
11214 : : .func = RTE_ETH_HASH_FUNCTION_DEFAULT,
11215 : : .level = 0,
11216 : : .types = 0,
11217 : 0 : .key_len = priv->rss_conf.rss_key_len,
11218 : 0 : .key = priv->rss_conf.rss_key,
11219 : 0 : .queue_num = priv->reta_idx_n,
11220 : : .queue = queue,
11221 : : };
11222 : 0 : struct rte_flow_action actions[] = {
11223 : : {
11224 : : .type = RTE_FLOW_ACTION_TYPE_RSS,
11225 : : .conf = &rss_conf,
11226 : : },
11227 : : {
11228 : : .type = RTE_FLOW_ACTION_TYPE_END,
11229 : : }
11230 : : };
11231 [ # # ]: 0 : struct rte_flow_action masks[] = {
11232 : : {
11233 : : .type = RTE_FLOW_ACTION_TYPE_RSS,
11234 : : .conf = &rss_conf,
11235 : : },
11236 : : {
11237 : : .type = RTE_FLOW_ACTION_TYPE_END,
11238 : : }
11239 : : };
11240 : : struct rte_flow_actions_template *at;
11241 : : struct rte_flow_error error;
11242 : : unsigned int i;
11243 : :
11244 : : MLX5_ASSERT(priv->reta_idx_n > 0 && priv->reta_idx);
11245 : : /* Select proper RSS hash types and based on that configure the actions template. */
11246 : 0 : rss_conf.types = flow_hw_ctrl_rx_rss_type_hash_types(rss_type);
11247 [ # # ]: 0 : if (rss_conf.types) {
11248 [ # # ]: 0 : for (i = 0; i < priv->reta_idx_n; ++i)
11249 : 0 : queue[i] = (*priv->reta_idx)[i];
11250 : : } else {
11251 : 0 : rss_conf.queue_num = 1;
11252 : 0 : queue[0] = (*priv->reta_idx)[0];
11253 : : }
11254 : : at = flow_hw_actions_template_create(dev, &attr, actions, masks, &error);
11255 [ # # ]: 0 : if (!at)
11256 [ # # ]: 0 : DRV_LOG(ERR,
11257 : : "Failed to create ctrl flow actions template: rte_errno(%d), type(%d): %s",
11258 : : rte_errno, error.type,
11259 : : error.message ? error.message : "(no stated reason)");
11260 : 0 : return at;
11261 : : }
11262 : :
11263 : : static uint32_t ctrl_rx_rss_priority_map[MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX] = {
11264 : : [MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_NON_IP] = MLX5_HW_CTRL_RX_PRIO_L2,
11265 : : [MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4] = MLX5_HW_CTRL_RX_PRIO_L3,
11266 : : [MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_UDP] = MLX5_HW_CTRL_RX_PRIO_L4,
11267 : : [MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_TCP] = MLX5_HW_CTRL_RX_PRIO_L4,
11268 : : [MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6] = MLX5_HW_CTRL_RX_PRIO_L3,
11269 : : [MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_UDP] = MLX5_HW_CTRL_RX_PRIO_L4,
11270 : : [MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_TCP] = MLX5_HW_CTRL_RX_PRIO_L4,
11271 : : };
11272 : :
11273 : : static uint32_t ctrl_rx_nb_flows_map[MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_MAX] = {
11274 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL] = 1,
11275 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL_MCAST] = 1,
11276 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST] = 1,
11277 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST_VLAN] = MLX5_MAX_VLAN_IDS,
11278 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST] = 1,
11279 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST_VLAN] = MLX5_MAX_VLAN_IDS,
11280 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST] = 1,
11281 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST_VLAN] = MLX5_MAX_VLAN_IDS,
11282 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC] = MLX5_MAX_UC_MAC_ADDRESSES,
11283 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN] =
11284 : : MLX5_MAX_UC_MAC_ADDRESSES * MLX5_MAX_VLAN_IDS,
11285 : : };
11286 : :
11287 : : static struct rte_flow_template_table_attr
11288 : : flow_hw_get_ctrl_rx_table_attr(enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type,
11289 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
11290 : : {
11291 : 0 : return (struct rte_flow_template_table_attr){
11292 : : .flow_attr = {
11293 : : .group = 0,
11294 : 0 : .priority = ctrl_rx_rss_priority_map[rss_type],
11295 : : .ingress = 1,
11296 : : },
11297 : 0 : .nb_flows = ctrl_rx_nb_flows_map[eth_pattern_type],
11298 : : };
11299 : : }
11300 : :
11301 : : static struct rte_flow_item
11302 : : flow_hw_get_ctrl_rx_eth_item(const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type)
11303 : : {
11304 : : struct rte_flow_item item = {
11305 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
11306 : : .mask = NULL,
11307 : : };
11308 : :
11309 : 0 : switch (eth_pattern_type) {
11310 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL:
11311 : : item.mask = &ctrl_rx_eth_promisc_mask;
11312 : : break;
11313 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL_MCAST:
11314 : : item.mask = &ctrl_rx_eth_mcast_mask;
11315 : 0 : break;
11316 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST:
11317 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST_VLAN:
11318 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC:
11319 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN:
11320 : : item.mask = &ctrl_rx_eth_dmac_mask;
11321 : 0 : break;
11322 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST:
11323 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST_VLAN:
11324 : : item.mask = &ctrl_rx_eth_ipv4_mcast_mask;
11325 : 0 : break;
11326 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST:
11327 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST_VLAN:
11328 : : item.mask = &ctrl_rx_eth_ipv6_mcast_mask;
11329 : 0 : break;
11330 : 0 : default:
11331 : : /* Should not reach here - ETH mask must be present. */
11332 : : item.type = RTE_FLOW_ITEM_TYPE_END;
11333 : : MLX5_ASSERT(false);
11334 : 0 : break;
11335 : : }
11336 : 0 : return item;
11337 : : }
11338 : :
11339 : : static struct rte_flow_item
11340 : : flow_hw_get_ctrl_rx_vlan_item(const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type)
11341 : : {
11342 : : struct rte_flow_item item = {
11343 : : .type = RTE_FLOW_ITEM_TYPE_VOID,
11344 : : .mask = NULL,
11345 : : };
11346 : :
11347 [ # # ]: 0 : switch (eth_pattern_type) {
11348 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST_VLAN:
11349 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST_VLAN:
11350 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST_VLAN:
11351 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN:
11352 : : item.type = RTE_FLOW_ITEM_TYPE_VLAN;
11353 : : item.mask = &rte_flow_item_vlan_mask;
11354 : 0 : break;
11355 : : default:
11356 : : /* Nothing to update. */
11357 : : break;
11358 : : }
11359 : 0 : return item;
11360 : : }
11361 : :
11362 : : static struct rte_flow_item
11363 : : flow_hw_get_ctrl_rx_l3_item(const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
11364 : : {
11365 : : struct rte_flow_item item = {
11366 : : .type = RTE_FLOW_ITEM_TYPE_VOID,
11367 : : .mask = NULL,
11368 : : };
11369 : :
11370 [ # # # ]: 0 : switch (rss_type) {
11371 : 0 : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4:
11372 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_UDP:
11373 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_TCP:
11374 : : item.type = RTE_FLOW_ITEM_TYPE_IPV4;
11375 : 0 : break;
11376 : 0 : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6:
11377 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_UDP:
11378 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_TCP:
11379 : : item.type = RTE_FLOW_ITEM_TYPE_IPV6;
11380 : 0 : break;
11381 : : default:
11382 : : /* Nothing to update. */
11383 : : break;
11384 : : }
11385 : 0 : return item;
11386 : : }
11387 : :
11388 : : static struct rte_flow_item
11389 : : flow_hw_get_ctrl_rx_l4_item(const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
11390 : : {
11391 : : struct rte_flow_item item = {
11392 : : .type = RTE_FLOW_ITEM_TYPE_VOID,
11393 : : .mask = NULL,
11394 : : };
11395 : :
11396 [ # # # ]: 0 : switch (rss_type) {
11397 : 0 : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_UDP:
11398 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_UDP:
11399 : : item.type = RTE_FLOW_ITEM_TYPE_UDP;
11400 : 0 : break;
11401 : 0 : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_TCP:
11402 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_TCP:
11403 : : item.type = RTE_FLOW_ITEM_TYPE_TCP;
11404 : 0 : break;
11405 : : default:
11406 : : /* Nothing to update. */
11407 : : break;
11408 : : }
11409 : 0 : return item;
11410 : : }
11411 : :
11412 : : static struct rte_flow_pattern_template *
11413 : 0 : flow_hw_create_ctrl_rx_pattern_template
11414 : : (struct rte_eth_dev *dev,
11415 : : const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type,
11416 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
11417 : : {
11418 : 0 : const struct rte_flow_pattern_template_attr attr = {
11419 : : .relaxed_matching = 0,
11420 : : .ingress = 1,
11421 : : };
11422 [ # # # # : 0 : struct rte_flow_item items[] = {
# # ]
11423 : : /* Matching patterns */
11424 : : flow_hw_get_ctrl_rx_eth_item(eth_pattern_type),
11425 : : flow_hw_get_ctrl_rx_vlan_item(eth_pattern_type),
11426 : : flow_hw_get_ctrl_rx_l3_item(rss_type),
11427 : : flow_hw_get_ctrl_rx_l4_item(rss_type),
11428 : : /* Terminate pattern */
11429 : : { .type = RTE_FLOW_ITEM_TYPE_END }
11430 : : };
11431 : :
11432 : 0 : return flow_hw_pattern_template_create(dev, &attr, items, NULL);
11433 : : }
11434 : :
11435 : : static int
11436 : 0 : flow_hw_create_ctrl_rx_tables(struct rte_eth_dev *dev)
11437 : : {
11438 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11439 : : unsigned int i;
11440 : : unsigned int j;
11441 : : int ret;
11442 : :
11443 : : MLX5_ASSERT(!priv->hw_ctrl_rx);
11444 : 0 : priv->hw_ctrl_rx = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*priv->hw_ctrl_rx),
11445 : 0 : RTE_CACHE_LINE_SIZE, rte_socket_id());
11446 [ # # ]: 0 : if (!priv->hw_ctrl_rx) {
11447 : 0 : DRV_LOG(ERR, "Failed to allocate memory for Rx control flow tables");
11448 : 0 : rte_errno = ENOMEM;
11449 : 0 : return -rte_errno;
11450 : : }
11451 : : /* Create all pattern template variants. */
11452 [ # # ]: 0 : for (i = 0; i < MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_MAX; ++i) {
11453 : : enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type = i;
11454 : :
11455 [ # # ]: 0 : for (j = 0; j < MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX; ++j) {
11456 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type = j;
11457 : : struct rte_flow_template_table_attr attr;
11458 : : struct rte_flow_pattern_template *pt;
11459 : :
11460 : : attr = flow_hw_get_ctrl_rx_table_attr(eth_pattern_type, rss_type);
11461 : 0 : pt = flow_hw_create_ctrl_rx_pattern_template(dev, eth_pattern_type,
11462 : : rss_type);
11463 [ # # ]: 0 : if (!pt)
11464 : 0 : goto err;
11465 : 0 : priv->hw_ctrl_rx->tables[i][j].attr = attr;
11466 : 0 : priv->hw_ctrl_rx->tables[i][j].pt = pt;
11467 : : }
11468 : : }
11469 : : return 0;
11470 : : err:
11471 : 0 : ret = rte_errno;
11472 : 0 : flow_hw_cleanup_ctrl_rx_tables(dev);
11473 : 0 : rte_errno = ret;
11474 : 0 : return -ret;
11475 : : }
11476 : :
11477 : : void
11478 : 0 : mlx5_flow_hw_cleanup_ctrl_rx_templates(struct rte_eth_dev *dev)
11479 : : {
11480 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11481 : : struct mlx5_flow_hw_ctrl_rx *hw_ctrl_rx;
11482 : : unsigned int i;
11483 : : unsigned int j;
11484 : :
11485 [ # # ]: 0 : if (!priv->dr_ctx)
11486 : : return;
11487 [ # # ]: 0 : if (!priv->hw_ctrl_rx)
11488 : : return;
11489 : : hw_ctrl_rx = priv->hw_ctrl_rx;
11490 [ # # ]: 0 : for (i = 0; i < MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_MAX; ++i) {
11491 [ # # ]: 0 : for (j = 0; j < MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX; ++j) {
11492 : : struct mlx5_flow_hw_ctrl_rx_table *tmpls = &hw_ctrl_rx->tables[i][j];
11493 : :
11494 [ # # ]: 0 : if (tmpls->tbl) {
11495 : 0 : claim_zero(flow_hw_table_destroy(dev, tmpls->tbl, NULL));
11496 : 0 : tmpls->tbl = NULL;
11497 : : }
11498 : : }
11499 : : }
11500 [ # # ]: 0 : for (j = 0; j < MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX; ++j) {
11501 [ # # ]: 0 : if (hw_ctrl_rx->rss[j]) {
11502 : 0 : claim_zero(flow_hw_actions_template_destroy(dev, hw_ctrl_rx->rss[j], NULL));
11503 : 0 : hw_ctrl_rx->rss[j] = NULL;
11504 : : }
11505 : : }
11506 : : }
11507 : :
11508 : : /**
11509 : : * Copy the provided HWS configuration to a newly allocated buffer.
11510 : : *
11511 : : * @param[in] port_attr
11512 : : * Port configuration attributes.
11513 : : * @param[in] nb_queue
11514 : : * Number of queue.
11515 : : * @param[in] queue_attr
11516 : : * Array that holds attributes for each flow queue.
11517 : : * @param[in] nt_mode
11518 : : * Non template mode.
11519 : : *
11520 : : * @return
11521 : : * Pointer to copied HWS configuration is returned on success.
11522 : : * Otherwise, NULL is returned and rte_errno is set.
11523 : : */
11524 : : static struct mlx5_flow_hw_attr *
11525 : 0 : flow_hw_alloc_copy_config(const struct rte_flow_port_attr *port_attr,
11526 : : const uint16_t nb_queue,
11527 : : const struct rte_flow_queue_attr *queue_attr[],
11528 : : bool nt_mode,
11529 : : struct rte_flow_error *error)
11530 : : {
11531 : : struct mlx5_flow_hw_attr *hw_attr;
11532 : : size_t hw_attr_size;
11533 : : unsigned int i;
11534 : :
11535 : 0 : hw_attr_size = sizeof(*hw_attr) + nb_queue * sizeof(*hw_attr->queue_attr);
11536 : 0 : hw_attr = mlx5_malloc(MLX5_MEM_ZERO, hw_attr_size, 0, SOCKET_ID_ANY);
11537 [ # # ]: 0 : if (!hw_attr) {
11538 : 0 : rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11539 : : "Not enough memory to store configuration");
11540 : 0 : return NULL;
11541 : : }
11542 : 0 : memcpy(&hw_attr->port_attr, port_attr, sizeof(*port_attr));
11543 : 0 : hw_attr->nb_queue = nb_queue;
11544 : : /* Queue attributes are placed after the mlx5_flow_hw_attr. */
11545 : 0 : hw_attr->queue_attr = (struct rte_flow_queue_attr *)(hw_attr + 1);
11546 [ # # ]: 0 : for (i = 0; i < nb_queue; ++i)
11547 : 0 : memcpy(&hw_attr->queue_attr[i], queue_attr[i], sizeof(hw_attr->queue_attr[i]));
11548 : 0 : hw_attr->nt_mode = nt_mode;
11549 : 0 : return hw_attr;
11550 : : }
11551 : :
11552 : : /**
11553 : : * Compares the preserved HWS configuration with the provided one.
11554 : : *
11555 : : * @param[in] hw_attr
11556 : : * Pointer to preserved HWS configuration.
11557 : : * @param[in] new_pa
11558 : : * Port configuration attributes to compare.
11559 : : * @param[in] new_nbq
11560 : : * Number of queues to compare.
11561 : : * @param[in] new_qa
11562 : : * Array that holds attributes for each flow queue.
11563 : : *
11564 : : * @return
11565 : : * True if configurations are the same, false otherwise.
11566 : : */
11567 : : static bool
11568 : 0 : flow_hw_compare_config(const struct mlx5_flow_hw_attr *hw_attr,
11569 : : const struct rte_flow_port_attr *new_pa,
11570 : : const uint16_t new_nbq,
11571 : : const struct rte_flow_queue_attr *new_qa[])
11572 : : {
11573 : : const struct rte_flow_port_attr *old_pa = &hw_attr->port_attr;
11574 : 0 : const uint16_t old_nbq = hw_attr->nb_queue;
11575 : 0 : const struct rte_flow_queue_attr *old_qa = hw_attr->queue_attr;
11576 : : unsigned int i;
11577 : :
11578 [ # # ]: 0 : if (old_pa->nb_counters != new_pa->nb_counters ||
11579 [ # # ]: 0 : old_pa->nb_aging_objects != new_pa->nb_aging_objects ||
11580 [ # # ]: 0 : old_pa->nb_meters != new_pa->nb_meters ||
11581 [ # # ]: 0 : old_pa->nb_conn_tracks != new_pa->nb_conn_tracks ||
11582 [ # # ]: 0 : old_pa->flags != new_pa->flags)
11583 : : return false;
11584 [ # # ]: 0 : if (old_nbq != new_nbq)
11585 : : return false;
11586 [ # # ]: 0 : for (i = 0; i < old_nbq; ++i)
11587 [ # # ]: 0 : if (old_qa[i].size != new_qa[i]->size)
11588 : : return false;
11589 : : return true;
11590 : : }
11591 : :
11592 : : /*
11593 : : * No need to explicitly release drop action templates on port stop.
11594 : : * Drop action templates release with other action templates during
11595 : : * mlx5_dev_close -> flow_hw_resource_release -> flow_hw_actions_template_destroy
11596 : : */
11597 : : static void
11598 : 0 : flow_hw_action_template_drop_release(struct rte_eth_dev *dev)
11599 : : {
11600 : : int i;
11601 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11602 : :
11603 [ # # ]: 0 : for (i = 0; i < MLX5DR_TABLE_TYPE_MAX; i++) {
11604 [ # # ]: 0 : if (!priv->action_template_drop[i])
11605 : 0 : continue;
11606 : 0 : flow_hw_actions_template_destroy(dev,
11607 : : priv->action_template_drop[i],
11608 : : NULL);
11609 : 0 : priv->action_template_drop[i] = NULL;
11610 : : }
11611 : 0 : }
11612 : :
11613 : : static int
11614 : 0 : flow_hw_action_template_drop_init(struct rte_eth_dev *dev,
11615 : : struct rte_flow_error *error)
11616 : : {
11617 : : uint32_t i, from, to;
11618 : 0 : const struct rte_flow_action drop[2] = {
11619 : : [0] = { .type = RTE_FLOW_ACTION_TYPE_DROP },
11620 : : [1] = { .type = RTE_FLOW_ACTION_TYPE_END },
11621 : : };
11622 : : const struct rte_flow_action *actions = drop;
11623 : : const struct rte_flow_action *masks = drop;
11624 : 0 : const struct rte_flow_actions_template_attr attr[MLX5DR_TABLE_TYPE_MAX] = {
11625 : : [MLX5DR_TABLE_TYPE_NIC_RX] = { .ingress = 1 },
11626 : : [MLX5DR_TABLE_TYPE_NIC_TX] = { .egress = 1 },
11627 : : [MLX5DR_TABLE_TYPE_FDB] = { .transfer = 1 },
11628 : : [MLX5DR_TABLE_TYPE_FDB_RX] = { .transfer = 1 },
11629 : : [MLX5DR_TABLE_TYPE_FDB_TX] = { .transfer = 1 },
11630 : : [MLX5DR_TABLE_TYPE_FDB_UNIFIED] = { .transfer = 1 },
11631 : : };
11632 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11633 : :
11634 : : from = MLX5DR_TABLE_TYPE_NIC_RX;
11635 : : to = MLX5DR_TABLE_TYPE_NIC_TX;
11636 [ # # ]: 0 : for (i = from; i <= to; i++) {
11637 : 0 : priv->action_template_drop[i] =
11638 : 0 : flow_hw_actions_template_create(dev, &attr[i], actions, masks, error);
11639 [ # # ]: 0 : if (!priv->action_template_drop[i])
11640 : : return -1;
11641 : : }
11642 : :
11643 [ # # # # ]: 0 : if (!(priv->sh->config.dv_esw_en && priv->master))
11644 : : return 0;
11645 : :
11646 : : from = MLX5DR_TABLE_TYPE_FDB;
11647 [ # # ]: 0 : to = is_unified_fdb(priv) ? MLX5DR_TABLE_TYPE_FDB_UNIFIED : MLX5DR_TABLE_TYPE_FDB;
11648 [ # # ]: 0 : for (i = from; i <= to; i++) {
11649 : 0 : priv->action_template_drop[i] =
11650 : 0 : flow_hw_actions_template_create(dev, &attr[i], actions, masks, error);
11651 [ # # ]: 0 : if (!priv->action_template_drop[i])
11652 : : return -1;
11653 : : }
11654 : : return 0;
11655 : : }
11656 : :
11657 : : static void
11658 : 0 : __flow_hw_resource_release(struct rte_eth_dev *dev, bool ctx_close)
11659 : : {
11660 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11661 : : struct rte_flow_template_table *tbl, *temp_tbl;
11662 : : struct rte_flow_pattern_template *it, *temp_it;
11663 : : struct rte_flow_actions_template *at, *temp_at;
11664 : : struct mlx5_flow_group *grp, *temp_grp;
11665 : : uint32_t i;
11666 : :
11667 : 0 : flow_hw_rxq_flag_set(dev, false);
11668 : 0 : flow_hw_flush_all_ctrl_flows(dev);
11669 : 0 : flow_hw_cleanup_ctrl_fdb_tables(dev);
11670 : 0 : flow_hw_cleanup_tx_repr_tagging(dev);
11671 : 0 : flow_hw_cleanup_ctrl_rx_tables(dev);
11672 : 0 : flow_hw_action_template_drop_release(dev);
11673 : 0 : grp = LIST_FIRST(&priv->flow_hw_grp);
11674 [ # # ]: 0 : while (grp) {
11675 : 0 : temp_grp = LIST_NEXT(grp, next);
11676 : 0 : claim_zero(flow_hw_group_unset_miss_group(dev, grp, NULL));
11677 : : grp = temp_grp;
11678 : : }
11679 : 0 : tbl = LIST_FIRST(&priv->flow_hw_tbl_ongo);
11680 [ # # ]: 0 : while (tbl) {
11681 : 0 : temp_tbl = LIST_NEXT(tbl, next);
11682 : 0 : claim_zero(flow_hw_table_destroy(dev, tbl, NULL));
11683 : : tbl = temp_tbl;
11684 : : }
11685 : 0 : tbl = LIST_FIRST(&priv->flow_hw_tbl);
11686 [ # # ]: 0 : while (tbl) {
11687 : 0 : temp_tbl = LIST_NEXT(tbl, next);
11688 : 0 : claim_zero(flow_hw_table_destroy(dev, tbl, NULL));
11689 : : tbl = temp_tbl;
11690 : : }
11691 : 0 : it = LIST_FIRST(&priv->flow_hw_itt);
11692 [ # # ]: 0 : while (it) {
11693 : 0 : temp_it = LIST_NEXT(it, next);
11694 : 0 : claim_zero(flow_hw_pattern_template_destroy(dev, it, NULL));
11695 : : it = temp_it;
11696 : : }
11697 : 0 : at = LIST_FIRST(&priv->flow_hw_at);
11698 [ # # ]: 0 : while (at) {
11699 : 0 : temp_at = LIST_NEXT(at, next);
11700 : 0 : claim_zero(flow_hw_actions_template_destroy(dev, at, NULL));
11701 : : at = temp_at;
11702 : : }
11703 [ # # ]: 0 : for (i = 0; i < MLX5_HW_ACTION_FLAG_MAX; i++) {
11704 [ # # ]: 0 : if (priv->hw_drop[i])
11705 : 0 : mlx5dr_action_destroy(priv->hw_drop[i]);
11706 [ # # ]: 0 : if (priv->hw_tag[i])
11707 : 0 : mlx5dr_action_destroy(priv->hw_tag[i]);
11708 : : }
11709 [ # # ]: 0 : if (priv->hw_def_miss)
11710 : 0 : mlx5dr_action_destroy(priv->hw_def_miss);
11711 : 0 : flow_hw_destroy_nat64_actions(priv);
11712 : 0 : flow_hw_destroy_vlan(dev);
11713 : 0 : flow_hw_destroy_send_to_kernel_action(priv);
11714 : 0 : flow_hw_free_vport_actions(priv);
11715 [ # # ]: 0 : if (priv->acts_ipool) {
11716 : 0 : mlx5_ipool_destroy(priv->acts_ipool);
11717 : 0 : priv->acts_ipool = NULL;
11718 : : }
11719 [ # # ]: 0 : if (priv->hws_age_req)
11720 : 0 : mlx5_hws_age_pool_destroy(priv);
11721 [ # # # # ]: 0 : if (!priv->shared_host && priv->hws_cpool) {
11722 : 0 : mlx5_hws_cnt_pool_destroy(priv->sh, priv->hws_cpool);
11723 : 0 : priv->hws_cpool = NULL;
11724 : : }
11725 [ # # ]: 0 : if (priv->hws_ctpool) {
11726 : 0 : flow_hw_ct_pool_destroy(dev, priv->hws_ctpool);
11727 : 0 : priv->hws_ctpool = NULL;
11728 : : }
11729 [ # # ]: 0 : if (priv->ct_mng) {
11730 : 0 : flow_hw_ct_mng_destroy(dev, priv->ct_mng);
11731 : 0 : priv->ct_mng = NULL;
11732 : : }
11733 : 0 : mlx5_flow_quota_destroy(dev);
11734 [ # # ]: 0 : if (priv->hw_q) {
11735 [ # # ]: 0 : for (i = 0; i < priv->nb_queue; i++) {
11736 : 0 : struct mlx5_hw_q *hwq = &priv->hw_q[i];
11737 : 0 : rte_ring_free(hwq->indir_iq);
11738 : 0 : rte_ring_free(hwq->indir_cq);
11739 : 0 : rte_ring_free(hwq->flow_transfer_pending);
11740 : 0 : rte_ring_free(hwq->flow_transfer_completed);
11741 : : }
11742 : 0 : mlx5_free(priv->hw_q);
11743 : 0 : priv->hw_q = NULL;
11744 : : }
11745 [ # # ]: 0 : if (ctx_close) {
11746 [ # # ]: 0 : if (priv->dr_ctx) {
11747 : 0 : claim_zero(mlx5dr_context_close(priv->dr_ctx));
11748 : 0 : priv->dr_ctx = NULL;
11749 : : }
11750 : : }
11751 [ # # ]: 0 : if (priv->shared_host) {
11752 : 0 : struct mlx5_priv *host_priv = priv->shared_host->data->dev_private;
11753 : 0 : rte_atomic_fetch_sub_explicit(&host_priv->shared_refcnt, 1,
11754 : : rte_memory_order_relaxed);
11755 : 0 : priv->shared_host = NULL;
11756 : : }
11757 [ # # ]: 0 : if (priv->hw_attr) {
11758 : 0 : mlx5_free(priv->hw_attr);
11759 : 0 : priv->hw_attr = NULL;
11760 : : }
11761 : 0 : priv->nb_queue = 0;
11762 : 0 : }
11763 : :
11764 : : static __rte_always_inline struct rte_ring *
11765 : : mlx5_hwq_ring_create(uint16_t port_id, uint32_t queue, uint32_t size, const char *str)
11766 : : {
11767 : : char mz_name[RTE_MEMZONE_NAMESIZE];
11768 : :
11769 : : snprintf(mz_name, sizeof(mz_name), "port_%u_%s_%u", port_id, str, queue);
11770 : 0 : return rte_ring_create(mz_name, size, SOCKET_ID_ANY,
11771 : : RING_F_SP_ENQ | RING_F_SC_DEQ | RING_F_EXACT_SZ);
11772 : : }
11773 : :
11774 : : static int
11775 : 0 : flow_hw_validate_attributes(const struct rte_flow_port_attr *port_attr,
11776 : : uint16_t nb_queue,
11777 : : const struct rte_flow_queue_attr *queue_attr[],
11778 : : bool nt_mode, struct rte_flow_error *error)
11779 : : {
11780 : : uint32_t size;
11781 : : unsigned int i;
11782 : :
11783 [ # # ]: 0 : if (port_attr == NULL)
11784 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11785 : : "Port attributes must be non-NULL");
11786 : :
11787 [ # # ]: 0 : if (nb_queue == 0 && !nt_mode)
11788 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11789 : : "At least one flow queue is required");
11790 : :
11791 [ # # ]: 0 : if (queue_attr == NULL)
11792 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11793 : : "Queue attributes must be non-NULL");
11794 : :
11795 : 0 : size = queue_attr[0]->size;
11796 [ # # ]: 0 : for (i = 1; i < nb_queue; ++i) {
11797 [ # # ]: 0 : if (queue_attr[i]->size != size)
11798 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11799 : : NULL,
11800 : : "All flow queues must have the same size");
11801 : : }
11802 : :
11803 : : return 0;
11804 : : }
11805 : :
11806 : : /**
11807 : : * Configure port HWS resources.
11808 : : *
11809 : : * @param[in] dev
11810 : : * Pointer to the rte_eth_dev structure.
11811 : : * @param[in] port_attr
11812 : : * Port configuration attributes.
11813 : : * @param[in] nb_queue
11814 : : * Number of queue.
11815 : : * @param[in] queue_attr
11816 : : * Array that holds attributes for each flow queue.
11817 : : * @param[in] nt_mode
11818 : : * Non-template mode.
11819 : : * @param[out] error
11820 : : * Pointer to error structure.
11821 : : *
11822 : : * @return
11823 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
11824 : : */
11825 : : static int
11826 : 0 : __flow_hw_configure(struct rte_eth_dev *dev,
11827 : : const struct rte_flow_port_attr *port_attr,
11828 : : uint16_t nb_queue,
11829 : : const struct rte_flow_queue_attr *queue_attr[],
11830 : : bool nt_mode,
11831 : : struct rte_flow_error *error)
11832 : : {
11833 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11834 : : struct mlx5_priv *host_priv = NULL;
11835 : 0 : struct mlx5dr_context_attr dr_ctx_attr = {0};
11836 : : struct mlx5_hw_q *hw_q;
11837 : : struct mlx5_hw_q_job *job = NULL;
11838 : : uint32_t mem_size, i, j;
11839 : 0 : struct mlx5_indexed_pool_config cfg = {
11840 : : .size = sizeof(struct mlx5_action_construct_data),
11841 : : .trunk_size = 4096,
11842 : : .need_lock = 1,
11843 : 0 : .release_mem_en = !!priv->sh->config.reclaim_mode,
11844 : : .malloc = mlx5_malloc,
11845 : : .free = mlx5_free,
11846 : : .type = "mlx5_hw_action_construct_data",
11847 : : };
11848 : : /*
11849 : : * Adds one queue to be used by PMD.
11850 : : * The last queue will be used by the PMD.
11851 : : */
11852 : : uint16_t nb_q_updated = 0;
11853 : : struct rte_flow_queue_attr **_queue_attr = NULL;
11854 : 0 : struct rte_flow_queue_attr ctrl_queue_attr = {0};
11855 [ # # # # ]: 0 : bool is_proxy = !!(priv->sh->config.dv_esw_en && priv->master);
11856 : : bool unified_fdb = is_unified_fdb(priv);
11857 : : int ret = 0;
11858 : : uint32_t action_flags;
11859 : : bool strict_queue = false;
11860 : :
11861 : 0 : error->type = RTE_FLOW_ERROR_TYPE_NONE;
11862 [ # # ]: 0 : if (mlx5dr_rule_get_handle_size() != MLX5_DR_RULE_SIZE) {
11863 : 0 : rte_errno = EINVAL;
11864 : 0 : goto err;
11865 : : }
11866 [ # # ]: 0 : if (flow_hw_validate_attributes(port_attr, nb_queue, queue_attr, nt_mode, error))
11867 : 0 : return -rte_errno;
11868 : : /*
11869 : : * Calling rte_flow_configure() again is allowed if
11870 : : * provided configuration matches the initially provided one,
11871 : : * or previous configuration was default non template one.
11872 : : */
11873 [ # # ]: 0 : if (priv->dr_ctx) {
11874 : : MLX5_ASSERT(priv->hw_attr != NULL);
11875 [ # # ]: 0 : for (i = 0; i < priv->nb_queue; i++) {
11876 : 0 : hw_q = &priv->hw_q[i];
11877 : : /* Make sure all queues are empty. */
11878 [ # # ]: 0 : if (hw_q->size != hw_q->job_idx) {
11879 : 0 : rte_errno = EBUSY;
11880 : 0 : goto err;
11881 : : }
11882 : : }
11883 : : /* If previous configuration was not default non template mode config. */
11884 [ # # ]: 0 : if (!priv->hw_attr->nt_mode) {
11885 [ # # ]: 0 : if (flow_hw_compare_config(priv->hw_attr, port_attr, nb_queue, queue_attr))
11886 : : return 0;
11887 : : else
11888 : 0 : return rte_flow_error_set(error, ENOTSUP,
11889 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11890 : : "Changing HWS configuration attributes "
11891 : : "is not supported");
11892 : : }
11893 : : /* Reconfiguration, need to release all resources from previous allocation. */
11894 : 0 : __flow_hw_resource_release(dev, true);
11895 : : }
11896 : 0 : priv->hw_attr = flow_hw_alloc_copy_config(port_attr, nb_queue, queue_attr, nt_mode, error);
11897 [ # # ]: 0 : if (!priv->hw_attr) {
11898 : 0 : ret = -rte_errno;
11899 : 0 : goto err;
11900 : : }
11901 : 0 : ctrl_queue_attr.size = queue_attr[0]->size;
11902 : 0 : nb_q_updated = nb_queue + 1;
11903 : 0 : _queue_attr = mlx5_malloc(MLX5_MEM_ZERO,
11904 : : nb_q_updated *
11905 : : sizeof(struct rte_flow_queue_attr *),
11906 : : 64, SOCKET_ID_ANY);
11907 [ # # ]: 0 : if (!_queue_attr) {
11908 : 0 : rte_errno = ENOMEM;
11909 : 0 : goto err;
11910 : : }
11911 : :
11912 : 0 : memcpy(_queue_attr, queue_attr, sizeof(void *) * nb_queue);
11913 : 0 : _queue_attr[nb_queue] = &ctrl_queue_attr;
11914 : 0 : priv->acts_ipool = mlx5_ipool_create(&cfg);
11915 [ # # ]: 0 : if (!priv->acts_ipool)
11916 : 0 : goto err;
11917 : : /* Allocate the queue job descriptor LIFO. */
11918 : 0 : mem_size = sizeof(priv->hw_q[0]) * nb_q_updated;
11919 [ # # ]: 0 : for (i = 0; i < nb_q_updated; i++) {
11920 : 0 : mem_size += (sizeof(struct mlx5_hw_q_job *) +
11921 : 0 : sizeof(struct mlx5_hw_q_job)) * _queue_attr[i]->size;
11922 : : }
11923 : 0 : priv->hw_q = mlx5_malloc(MLX5_MEM_ZERO, mem_size,
11924 : : 64, SOCKET_ID_ANY);
11925 [ # # ]: 0 : if (!priv->hw_q) {
11926 : 0 : rte_errno = ENOMEM;
11927 : 0 : goto err;
11928 : : }
11929 [ # # ]: 0 : for (i = 0; i < nb_q_updated; i++) {
11930 : 0 : priv->hw_q[i].job_idx = _queue_attr[i]->size;
11931 : 0 : priv->hw_q[i].size = _queue_attr[i]->size;
11932 : 0 : priv->hw_q[i].ongoing_flow_ops = 0;
11933 [ # # ]: 0 : if (i == 0)
11934 : 0 : priv->hw_q[i].job = (struct mlx5_hw_q_job **)
11935 : 0 : &priv->hw_q[nb_q_updated];
11936 : : else
11937 : 0 : priv->hw_q[i].job = (struct mlx5_hw_q_job **)&job[_queue_attr[i - 1]->size];
11938 : 0 : job = (struct mlx5_hw_q_job *)
11939 : 0 : &priv->hw_q[i].job[_queue_attr[i]->size];
11940 [ # # ]: 0 : for (j = 0; j < _queue_attr[i]->size; j++)
11941 : 0 : priv->hw_q[i].job[j] = &job[j];
11942 : : /* Notice ring name length is limited. */
11943 : 0 : priv->hw_q[i].indir_cq = mlx5_hwq_ring_create
11944 : 0 : (dev->data->port_id, i, _queue_attr[i]->size, "indir_act_cq");
11945 [ # # ]: 0 : if (!priv->hw_q[i].indir_cq)
11946 : 0 : goto err;
11947 : 0 : priv->hw_q[i].indir_iq = mlx5_hwq_ring_create
11948 : 0 : (dev->data->port_id, i, _queue_attr[i]->size, "indir_act_iq");
11949 [ # # ]: 0 : if (!priv->hw_q[i].indir_iq)
11950 : 0 : goto err;
11951 : 0 : priv->hw_q[i].flow_transfer_pending = mlx5_hwq_ring_create
11952 : 0 : (dev->data->port_id, i, _queue_attr[i]->size, "tx_pending");
11953 [ # # ]: 0 : if (!priv->hw_q[i].flow_transfer_pending)
11954 : 0 : goto err;
11955 : 0 : priv->hw_q[i].flow_transfer_completed = mlx5_hwq_ring_create
11956 : 0 : (dev->data->port_id, i, _queue_attr[i]->size, "tx_done");
11957 [ # # ]: 0 : if (!priv->hw_q[i].flow_transfer_completed)
11958 : 0 : goto err;
11959 : : }
11960 : 0 : dr_ctx_attr.pd = priv->sh->cdev->pd;
11961 : 0 : dr_ctx_attr.queues = nb_q_updated;
11962 : : /* Assign initial value of STC numbers for representors. */
11963 [ # # ]: 0 : if (priv->representor)
11964 : 0 : dr_ctx_attr.initial_log_stc_memory = MLX5_REPR_STC_MEMORY_LOG;
11965 : : /* Queue size should all be the same. Take the first one. */
11966 : 0 : dr_ctx_attr.queue_size = _queue_attr[0]->size;
11967 [ # # ]: 0 : if (port_attr->flags & RTE_FLOW_PORT_FLAG_SHARE_INDIRECT) {
11968 : : struct rte_eth_dev *host_dev = NULL;
11969 : : uint16_t port_id;
11970 : :
11971 : : MLX5_ASSERT(rte_eth_dev_is_valid_port(port_attr->host_port_id));
11972 [ # # ]: 0 : if (is_proxy) {
11973 : 0 : DRV_LOG(ERR, "cross vHCA shared mode not supported "
11974 : : "for E-Switch confgiurations");
11975 : 0 : rte_errno = ENOTSUP;
11976 : 0 : goto err;
11977 : : }
11978 [ # # ]: 0 : MLX5_ETH_FOREACH_DEV(port_id, dev->device) {
11979 [ # # ]: 0 : if (port_id == port_attr->host_port_id) {
11980 : 0 : host_dev = &rte_eth_devices[port_id];
11981 : 0 : break;
11982 : : }
11983 : : }
11984 [ # # ]: 0 : if (!host_dev || host_dev == dev ||
11985 [ # # # # ]: 0 : !host_dev->data || !host_dev->data->dev_private) {
11986 : 0 : DRV_LOG(ERR, "Invalid cross vHCA host port %u",
11987 : : port_attr->host_port_id);
11988 : 0 : rte_errno = EINVAL;
11989 : 0 : goto err;
11990 : : }
11991 : : host_priv = host_dev->data->dev_private;
11992 [ # # ]: 0 : if (host_priv->sh->cdev->ctx == priv->sh->cdev->ctx) {
11993 : 0 : DRV_LOG(ERR, "Sibling ports %u and %u do not "
11994 : : "require cross vHCA sharing mode",
11995 : : dev->data->port_id, port_attr->host_port_id);
11996 : 0 : rte_errno = EINVAL;
11997 : 0 : goto err;
11998 : : }
11999 [ # # ]: 0 : if (host_priv->shared_host) {
12000 : 0 : DRV_LOG(ERR, "Host port %u is not the sharing base",
12001 : : port_attr->host_port_id);
12002 : 0 : rte_errno = EINVAL;
12003 : 0 : goto err;
12004 : : }
12005 [ # # ]: 0 : if (port_attr->nb_counters ||
12006 [ # # ]: 0 : port_attr->nb_aging_objects ||
12007 [ # # ]: 0 : port_attr->nb_meters ||
12008 [ # # ]: 0 : port_attr->nb_conn_tracks) {
12009 : 0 : DRV_LOG(ERR,
12010 : : "Object numbers on guest port must be zeros");
12011 : 0 : rte_errno = EINVAL;
12012 : 0 : goto err;
12013 : : }
12014 : 0 : dr_ctx_attr.shared_ibv_ctx = host_priv->sh->cdev->ctx;
12015 : 0 : priv->shared_host = host_dev;
12016 : 0 : rte_atomic_fetch_add_explicit(&host_priv->shared_refcnt, 1,
12017 : : rte_memory_order_relaxed);
12018 : : }
12019 : : /* Set backward compatibale mode to support non template RTE FLOW API.*/
12020 : 0 : dr_ctx_attr.bwc = true;
12021 : 0 : priv->dr_ctx = mlx5dr_context_open(priv->sh->cdev->ctx, &dr_ctx_attr);
12022 : : /* rte_errno has been updated by HWS layer. */
12023 [ # # ]: 0 : if (!priv->dr_ctx)
12024 : 0 : goto err;
12025 : 0 : priv->nb_queue = nb_q_updated;
12026 : 0 : ret = flow_hw_action_template_drop_init(dev, error);
12027 [ # # ]: 0 : if (ret)
12028 : 0 : goto err;
12029 : 0 : ret = flow_hw_create_ctrl_rx_tables(dev);
12030 [ # # ]: 0 : if (ret) {
12031 : 0 : rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12032 : : "Failed to set up Rx control flow templates");
12033 : 0 : goto err;
12034 : : }
12035 : : /* Initialize quotas */
12036 [ # # # # : 0 : if (port_attr->nb_quotas || (host_priv && host_priv->quota_ctx.devx_obj)) {
# # ]
12037 : 0 : ret = mlx5_flow_quota_init(dev, port_attr->nb_quotas);
12038 [ # # ]: 0 : if (ret) {
12039 : 0 : rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12040 : : "Failed to initialize quota.");
12041 : 0 : goto err;
12042 : : }
12043 : : }
12044 : : /* Initialize meter library*/
12045 [ # # # # : 0 : if (port_attr->nb_meters || (host_priv && host_priv->hws_mpool))
# # ]
12046 [ # # ]: 0 : if (mlx5_flow_meter_init(dev, port_attr->nb_meters, 0, 0, nb_q_updated))
12047 : 0 : goto err;
12048 : : /* Add global actions. */
12049 [ # # ]: 0 : for (i = 0; i < MLX5_HW_ACTION_FLAG_MAX; i++) {
12050 : : uint32_t act_flags = 0;
12051 : 0 : uint32_t tag_flags = mlx5_hw_act_flag[i][0];
12052 : :
12053 : 0 : act_flags = mlx5_hw_act_flag[i][MLX5DR_TABLE_TYPE_NIC_RX] |
12054 : 0 : mlx5_hw_act_flag[i][MLX5DR_TABLE_TYPE_NIC_TX];
12055 [ # # ]: 0 : if (is_proxy) {
12056 : : /* Tag action is valid only in FDB_Rx domain. */
12057 [ # # ]: 0 : if (unified_fdb) {
12058 : 0 : act_flags |=
12059 : 0 : (mlx5_hw_act_flag[i][MLX5DR_TABLE_TYPE_FDB_RX] |
12060 : 0 : mlx5_hw_act_flag[i][MLX5DR_TABLE_TYPE_FDB_TX] |
12061 : 0 : mlx5_hw_act_flag[i][MLX5DR_TABLE_TYPE_FDB_UNIFIED]);
12062 [ # # ]: 0 : if (i == MLX5_HW_ACTION_FLAG_NONE_ROOT)
12063 : 0 : tag_flags |= mlx5_hw_act_flag[i][MLX5DR_TABLE_TYPE_FDB_RX];
12064 : : } else {
12065 : 0 : act_flags |= mlx5_hw_act_flag[i][MLX5DR_TABLE_TYPE_FDB];
12066 [ # # ]: 0 : if (i == MLX5_HW_ACTION_FLAG_NONE_ROOT)
12067 : 0 : tag_flags |= mlx5_hw_act_flag[i][MLX5DR_TABLE_TYPE_FDB];
12068 : : }
12069 : : }
12070 : 0 : priv->hw_drop[i] = mlx5dr_action_create_dest_drop(priv->dr_ctx, act_flags);
12071 [ # # ]: 0 : if (!priv->hw_drop[i])
12072 : 0 : goto err;
12073 : 0 : priv->hw_tag[i] = mlx5dr_action_create_tag
12074 : : (priv->dr_ctx, tag_flags);
12075 [ # # ]: 0 : if (!priv->hw_tag[i])
12076 : 0 : goto err;
12077 : : }
12078 [ # # # # ]: 0 : if (priv->sh->config.dv_esw_en && priv->sh->config.repr_matching) {
12079 : 0 : ret = flow_hw_setup_tx_repr_tagging(dev, error);
12080 [ # # ]: 0 : if (ret)
12081 : 0 : goto err;
12082 : : }
12083 : : /*
12084 : : * DEFAULT_MISS action have different behaviors in different domains.
12085 : : * In FDB, it will steering the packets to the E-switch manager.
12086 : : * In NIC Rx root, it will steering the packet to the kernel driver stack.
12087 : : * An action with all bits set in the flag can be created and the HWS
12088 : : * layer will translate it properly when being used in different rules.
12089 : : */
12090 : : action_flags = MLX5DR_ACTION_FLAG_ROOT_RX | MLX5DR_ACTION_FLAG_HWS_RX |
12091 : : MLX5DR_ACTION_FLAG_ROOT_TX | MLX5DR_ACTION_FLAG_HWS_TX;
12092 [ # # ]: 0 : if (is_proxy) {
12093 [ # # ]: 0 : if (unified_fdb)
12094 : : action_flags |=
12095 : : (MLX5DR_ACTION_FLAG_ROOT_FDB |
12096 : : MLX5DR_ACTION_FLAG_HWS_FDB_RX |
12097 : : MLX5DR_ACTION_FLAG_HWS_FDB_TX |
12098 : : MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED);
12099 : : else
12100 : : action_flags |=
12101 : : (MLX5DR_ACTION_FLAG_ROOT_FDB |
12102 : : MLX5DR_ACTION_FLAG_HWS_FDB);
12103 : : }
12104 : 0 : priv->hw_def_miss = mlx5dr_action_create_default_miss(priv->dr_ctx, action_flags);
12105 [ # # ]: 0 : if (!priv->hw_def_miss)
12106 : 0 : goto err;
12107 [ # # ]: 0 : if (is_proxy) {
12108 : 0 : ret = flow_hw_create_vport_actions(priv);
12109 [ # # ]: 0 : if (ret) {
12110 : 0 : rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12111 : : NULL, "Failed to create vport actions.");
12112 : 0 : goto err;
12113 : : }
12114 : 0 : ret = flow_hw_create_ctrl_tables(dev, error);
12115 [ # # ]: 0 : if (ret) {
12116 : 0 : rte_errno = -ret;
12117 : 0 : goto err;
12118 : : }
12119 : : }
12120 : : if (!priv->shared_host)
12121 : : flow_hw_create_send_to_kernel_actions(priv, is_proxy);
12122 [ # # # # : 0 : if (port_attr->nb_conn_tracks || (host_priv && host_priv->hws_ctpool)) {
# # ]
12123 [ # # ]: 0 : if (mlx5_flow_ct_init(dev, port_attr->nb_conn_tracks, nb_q_updated))
12124 : 0 : goto err;
12125 : : }
12126 [ # # # # : 0 : if (port_attr->nb_counters || (host_priv && host_priv->hws_cpool)) {
# # ]
12127 [ # # ]: 0 : struct mlx5_hws_cnt_pool *hws_cpool = host_priv ? host_priv->hws_cpool : NULL;
12128 : :
12129 : 0 : ret = mlx5_hws_cnt_pool_create(dev, port_attr->nb_counters,
12130 : : nb_queue, hws_cpool, error);
12131 [ # # ]: 0 : if (ret)
12132 : 0 : goto err;
12133 : : }
12134 [ # # ]: 0 : if (port_attr->nb_aging_objects) {
12135 [ # # ]: 0 : if (port_attr->nb_counters == 0) {
12136 : : /*
12137 : : * Aging management uses counter. Number counters
12138 : : * requesting should take into account a counter for
12139 : : * each flow rules containing AGE without counter.
12140 : : */
12141 : 0 : DRV_LOG(ERR, "Port %u AGE objects are requested (%u) "
12142 : : "without counters requesting.",
12143 : : dev->data->port_id,
12144 : : port_attr->nb_aging_objects);
12145 : 0 : rte_errno = EINVAL;
12146 : 0 : goto err;
12147 : : }
12148 [ # # ]: 0 : if (port_attr->flags & RTE_FLOW_PORT_FLAG_SHARE_INDIRECT) {
12149 : 0 : DRV_LOG(ERR, "Aging is not supported "
12150 : : "in cross vHCA sharing mode");
12151 : : ret = -ENOTSUP;
12152 : 0 : goto err;
12153 : : }
12154 : 0 : strict_queue = !!(port_attr->flags & RTE_FLOW_PORT_FLAG_STRICT_QUEUE);
12155 : 0 : ret = mlx5_hws_age_pool_init(dev, port_attr->nb_aging_objects,
12156 : : nb_queue, strict_queue);
12157 [ # # ]: 0 : if (ret < 0)
12158 : 0 : goto err;
12159 : : }
12160 : 0 : ret = flow_hw_create_vlan(dev);
12161 [ # # ]: 0 : if (ret) {
12162 : 0 : rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12163 : : NULL, "Failed to VLAN actions.");
12164 : 0 : goto err;
12165 : : }
12166 [ # # ]: 0 : if (flow_hw_should_create_nat64_actions(priv)) {
12167 [ # # ]: 0 : if (flow_hw_create_nat64_actions(priv, error))
12168 : 0 : goto err;
12169 : : } else {
12170 : 0 : DRV_LOG(WARNING, "Cannot create NAT64 action on port %u, "
12171 : : "please check the FW version. NAT64 will not be supported.",
12172 : : dev->data->port_id);
12173 : : }
12174 : : if (_queue_attr)
12175 : 0 : mlx5_free(_queue_attr);
12176 [ # # ]: 0 : if (port_attr->flags & RTE_FLOW_PORT_FLAG_STRICT_QUEUE)
12177 : 0 : priv->hws_strict_queue = 1;
12178 : 0 : dev->flow_fp_ops = &mlx5_flow_hw_fp_ops;
12179 : 0 : return 0;
12180 : 0 : err:
12181 : 0 : __flow_hw_resource_release(dev, true);
12182 [ # # ]: 0 : if (_queue_attr)
12183 : 0 : mlx5_free(_queue_attr);
12184 : : /* Do not overwrite the internal errno information. */
12185 [ # # # # ]: 0 : if (ret && error->type != RTE_FLOW_ERROR_TYPE_NONE)
12186 : : return ret;
12187 : 0 : return rte_flow_error_set(error, rte_errno,
12188 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12189 : : "fail to configure port");
12190 : : }
12191 : :
12192 : : /**
12193 : : * Configure port HWS resources.
12194 : : *
12195 : : * @param[in] dev
12196 : : * Pointer to the rte_eth_dev structure.
12197 : : * @param[in] port_attr
12198 : : * Port configuration attributes.
12199 : : * @param[in] nb_queue
12200 : : * Number of queue.
12201 : : * @param[in] queue_attr
12202 : : * Array that holds attributes for each flow queue.
12203 : : * @param[out] error
12204 : : * Pointer to error structure.
12205 : : *
12206 : : * @return
12207 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
12208 : : */
12209 : : static int
12210 : 0 : flow_hw_configure(struct rte_eth_dev *dev,
12211 : : const struct rte_flow_port_attr *port_attr,
12212 : : uint16_t nb_queue,
12213 : : const struct rte_flow_queue_attr *queue_attr[],
12214 : : struct rte_flow_error *error)
12215 : : {
12216 : 0 : struct rte_flow_error shadow_error = {0, };
12217 : :
12218 [ # # ]: 0 : if (!error)
12219 : : error = &shadow_error;
12220 : 0 : return __flow_hw_configure(dev, port_attr, nb_queue, queue_attr, false, error);
12221 : : }
12222 : :
12223 : : /**
12224 : : * Release HWS resources.
12225 : : *
12226 : : * @param[in] dev
12227 : : * Pointer to the rte_eth_dev structure.
12228 : : */
12229 : : void
12230 : 0 : flow_hw_resource_release(struct rte_eth_dev *dev)
12231 : : {
12232 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12233 : :
12234 [ # # ]: 0 : if (!priv->dr_ctx)
12235 : : return;
12236 : 0 : __flow_hw_resource_release(dev, false);
12237 : : }
12238 : :
12239 : : /* Sets vport tag and mask, for given port, used in HWS rules. */
12240 : : void
12241 : 0 : flow_hw_set_port_info(struct rte_eth_dev *dev)
12242 : : {
12243 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12244 : 0 : uint16_t port_id = dev->data->port_id;
12245 : : struct flow_hw_port_info *info;
12246 : :
12247 : : MLX5_ASSERT(port_id < RTE_MAX_ETHPORTS);
12248 : 0 : info = &mlx5_flow_hw_port_infos[port_id];
12249 : 0 : info->regc_mask = priv->vport_meta_mask;
12250 [ # # ]: 0 : info->regc_value = priv->vport_meta_tag;
12251 [ # # ]: 0 : info->is_wire = mlx5_is_port_on_mpesw_device(priv) ? priv->mpesw_uplink : priv->master;
12252 : 0 : }
12253 : :
12254 : : /* Clears vport tag and mask used for HWS rules. */
12255 : : void
12256 : 0 : flow_hw_clear_port_info(struct rte_eth_dev *dev)
12257 : : {
12258 : 0 : uint16_t port_id = dev->data->port_id;
12259 : : struct flow_hw_port_info *info;
12260 : :
12261 : : MLX5_ASSERT(port_id < RTE_MAX_ETHPORTS);
12262 : 0 : info = &mlx5_flow_hw_port_infos[port_id];
12263 : 0 : info->regc_mask = 0;
12264 : 0 : info->regc_value = 0;
12265 : 0 : info->is_wire = 0;
12266 : 0 : }
12267 : :
12268 : : static int
12269 : 0 : flow_hw_conntrack_destroy(struct rte_eth_dev *dev,
12270 : : uint32_t idx,
12271 : : struct rte_flow_error *error)
12272 : : {
12273 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12274 : 0 : struct mlx5_aso_ct_pool *pool = priv->hws_ctpool;
12275 : : struct mlx5_aso_ct_action *ct;
12276 : :
12277 [ # # ]: 0 : if (priv->shared_host)
12278 : 0 : return rte_flow_error_set(error, ENOTSUP,
12279 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12280 : : NULL,
12281 : : "CT destruction is not allowed to guest port");
12282 : 0 : ct = mlx5_ipool_get(pool->cts, idx);
12283 [ # # ]: 0 : if (!ct) {
12284 : 0 : return rte_flow_error_set(error, EINVAL,
12285 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12286 : : NULL,
12287 : : "Invalid CT destruction index");
12288 : : }
12289 : 0 : rte_atomic_store_explicit(&ct->state, ASO_CONNTRACK_FREE,
12290 : : rte_memory_order_relaxed);
12291 : 0 : mlx5_ipool_free(pool->cts, idx);
12292 : 0 : return 0;
12293 : : }
12294 : :
12295 : : static int
12296 : 0 : flow_hw_conntrack_query(struct rte_eth_dev *dev, uint32_t queue, uint32_t idx,
12297 : : struct rte_flow_action_conntrack *profile,
12298 : : void *user_data, bool push,
12299 : : struct rte_flow_error *error)
12300 : : {
12301 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12302 : 0 : struct mlx5_aso_ct_pool *pool = priv->hws_ctpool;
12303 : : struct mlx5_aso_ct_action *ct;
12304 : :
12305 [ # # ]: 0 : if (priv->shared_host)
12306 : 0 : return rte_flow_error_set(error, ENOTSUP,
12307 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12308 : : NULL,
12309 : : "CT query is not allowed to guest port");
12310 : 0 : ct = mlx5_ipool_get(pool->cts, idx);
12311 [ # # ]: 0 : if (!ct) {
12312 : 0 : return rte_flow_error_set(error, EINVAL,
12313 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12314 : : NULL,
12315 : : "Invalid CT query index");
12316 : : }
12317 : 0 : profile->peer_port = ct->peer;
12318 : 0 : profile->is_original_dir = ct->is_original;
12319 [ # # ]: 0 : if (mlx5_aso_ct_query_by_wqe(priv->sh, queue, ct, profile, user_data, push))
12320 : 0 : return rte_flow_error_set(error, EIO,
12321 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12322 : : NULL,
12323 : : "Failed to query CT context");
12324 : : return 0;
12325 : : }
12326 : :
12327 : :
12328 : : static int
12329 : 0 : flow_hw_conntrack_update(struct rte_eth_dev *dev, uint32_t queue,
12330 : : const struct rte_flow_modify_conntrack *action_conf,
12331 : : uint32_t idx, void *user_data, bool push,
12332 : : struct rte_flow_error *error)
12333 : : {
12334 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12335 : 0 : struct mlx5_aso_ct_pool *pool = priv->hws_ctpool;
12336 : : struct mlx5_aso_ct_action *ct;
12337 : : const struct rte_flow_action_conntrack *new_prf;
12338 : : int ret = 0;
12339 : :
12340 [ # # ]: 0 : if (priv->shared_host)
12341 : 0 : return rte_flow_error_set(error, ENOTSUP,
12342 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12343 : : NULL,
12344 : : "CT update is not allowed to guest port");
12345 : 0 : ct = mlx5_ipool_get(pool->cts, idx);
12346 [ # # ]: 0 : if (!ct) {
12347 : 0 : return rte_flow_error_set(error, EINVAL,
12348 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12349 : : NULL,
12350 : : "Invalid CT update index");
12351 : : }
12352 : 0 : new_prf = &action_conf->new_ct;
12353 [ # # ]: 0 : if (action_conf->direction)
12354 : 0 : ct->is_original = !!new_prf->is_original_dir;
12355 [ # # ]: 0 : if (action_conf->state) {
12356 : : /* Only validate the profile when it needs to be updated. */
12357 : 0 : ret = mlx5_validate_action_ct(dev, new_prf, error);
12358 [ # # ]: 0 : if (ret)
12359 : : return ret;
12360 : 0 : ret = mlx5_aso_ct_update_by_wqe(priv->sh, queue, ct, new_prf,
12361 : : user_data, push);
12362 [ # # ]: 0 : if (ret)
12363 : 0 : return rte_flow_error_set(error, EIO,
12364 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12365 : : NULL,
12366 : : "Failed to send CT context update WQE");
12367 [ # # ]: 0 : if (queue != MLX5_HW_INV_QUEUE)
12368 : : return 0;
12369 : : /* Block until ready or a failure in synchronous mode. */
12370 : 0 : ret = mlx5_aso_ct_available(priv->sh, queue, ct);
12371 [ # # ]: 0 : if (ret)
12372 : 0 : rte_flow_error_set(error, rte_errno,
12373 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12374 : : NULL,
12375 : : "Timeout to get the CT update");
12376 : : }
12377 : : return ret;
12378 : : }
12379 : :
12380 : : static struct rte_flow_action_handle *
12381 : 0 : flow_hw_conntrack_create(struct rte_eth_dev *dev, uint32_t queue,
12382 : : const struct rte_flow_action_conntrack *pro,
12383 : : void *user_data, bool push,
12384 : : struct rte_flow_error *error)
12385 : : {
12386 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12387 : 0 : struct mlx5_aso_ct_pool *pool = priv->hws_ctpool;
12388 : : struct mlx5_aso_ct_action *ct;
12389 : 0 : uint32_t ct_idx = 0;
12390 : : int ret;
12391 : : bool async = !!(queue != MLX5_HW_INV_QUEUE);
12392 : :
12393 [ # # ]: 0 : if (priv->shared_host) {
12394 : 0 : rte_flow_error_set(error, ENOTSUP,
12395 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12396 : : NULL,
12397 : : "CT create is not allowed to guest port");
12398 : 0 : return NULL;
12399 : : }
12400 [ # # ]: 0 : if (!pool) {
12401 : 0 : rte_flow_error_set(error, EINVAL,
12402 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12403 : : "CT is not enabled");
12404 : 0 : return 0;
12405 : : }
12406 : 0 : ct = mlx5_ipool_zmalloc(pool->cts, &ct_idx);
12407 [ # # ]: 0 : if (!ct) {
12408 : 0 : rte_flow_error_set(error, rte_errno,
12409 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12410 : : "Failed to allocate CT object");
12411 : 0 : return 0;
12412 : : }
12413 : 0 : ct->offset = ct_idx - 1;
12414 : 0 : ct->is_original = !!pro->is_original_dir;
12415 : 0 : ct->peer = pro->peer_port;
12416 : 0 : ct->pool = pool;
12417 [ # # ]: 0 : if (mlx5_aso_ct_update_by_wqe(priv->sh, queue, ct, pro, user_data, push)) {
12418 : 0 : mlx5_ipool_free(pool->cts, ct_idx);
12419 : 0 : rte_flow_error_set(error, EBUSY,
12420 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12421 : : "Failed to update CT");
12422 : 0 : return 0;
12423 : : }
12424 [ # # ]: 0 : if (!async) {
12425 : 0 : ret = mlx5_aso_ct_available(priv->sh, queue, ct);
12426 [ # # ]: 0 : if (ret) {
12427 : 0 : mlx5_ipool_free(pool->cts, ct_idx);
12428 : 0 : rte_flow_error_set(error, rte_errno,
12429 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12430 : : NULL,
12431 : : "Timeout to get the CT update");
12432 : 0 : return 0;
12433 : : }
12434 : : }
12435 : 0 : return MLX5_INDIRECT_ACT_HWS_CT_GEN_IDX(ct_idx);
12436 : : }
12437 : :
12438 : : /**
12439 : : * Validate shared action.
12440 : : *
12441 : : * @param[in] dev
12442 : : * Pointer to the rte_eth_dev structure.
12443 : : * @param[in] queue
12444 : : * Which queue to be used.
12445 : : * @param[in] attr
12446 : : * Operation attribute.
12447 : : * @param[in] conf
12448 : : * Indirect action configuration.
12449 : : * @param[in] action
12450 : : * rte_flow action detail.
12451 : : * @param[in] user_data
12452 : : * Pointer to the user_data.
12453 : : * @param[out] error
12454 : : * Pointer to error structure.
12455 : : *
12456 : : * @return
12457 : : * 0 on success, otherwise negative errno value.
12458 : : */
12459 : : static int
12460 : 0 : flow_hw_action_handle_validate(struct rte_eth_dev *dev, uint32_t queue,
12461 : : const struct rte_flow_op_attr *attr,
12462 : : const struct rte_flow_indir_action_conf *conf,
12463 : : const struct rte_flow_action *action,
12464 : : void *user_data,
12465 : : struct rte_flow_error *error)
12466 : : {
12467 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12468 : :
12469 : : RTE_SET_USED(attr);
12470 : : RTE_SET_USED(queue);
12471 : : RTE_SET_USED(user_data);
12472 [ # # # # : 0 : switch (action->type) {
# # # ]
12473 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
12474 [ # # ]: 0 : if (!priv->hws_age_req) {
12475 [ # # ]: 0 : if (flow_hw_allocate_actions(dev, MLX5_FLOW_ACTION_AGE,
12476 : : error))
12477 : 0 : return rte_flow_error_set
12478 : : (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
12479 : : NULL, "aging pool not initialized");
12480 : : }
12481 : : break;
12482 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
12483 [ # # ]: 0 : if (!priv->hws_cpool) {
12484 [ # # ]: 0 : if (flow_hw_allocate_actions(dev, MLX5_FLOW_ACTION_COUNT,
12485 : : error))
12486 : 0 : return rte_flow_error_set
12487 : : (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
12488 : : NULL, "counters pool not initialized");
12489 : : }
12490 : : break;
12491 : 0 : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
12492 [ # # ]: 0 : if (priv->hws_ctpool == NULL) {
12493 [ # # ]: 0 : if (flow_hw_allocate_actions(dev, MLX5_FLOW_ACTION_CT,
12494 : : error))
12495 : 0 : return rte_flow_error_set
12496 : : (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
12497 : : NULL, "CT pool not initialized");
12498 : : }
12499 : 0 : return mlx5_validate_action_ct(dev, action->conf, error);
12500 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
12501 : 0 : return flow_hw_validate_action_meter_mark(dev, action, true, error);
12502 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
12503 : 0 : return flow_dv_action_validate(dev, conf, action, error);
12504 : : case RTE_FLOW_ACTION_TYPE_QUOTA:
12505 : : return 0;
12506 : 0 : default:
12507 : 0 : return rte_flow_error_set(error, ENOTSUP,
12508 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12509 : : "action type not supported");
12510 : : }
12511 : : return 0;
12512 : : }
12513 : :
12514 : : static __rte_always_inline bool
12515 : : flow_hw_action_push(const struct rte_flow_op_attr *attr)
12516 : : {
12517 [ # # # # : 0 : return attr ? !attr->postpone : true;
# # # # #
# # # #
# ]
12518 : : }
12519 : :
12520 : : static __rte_always_inline struct mlx5_hw_q_job *
12521 : : flow_hw_action_job_init(struct mlx5_priv *priv, uint32_t queue,
12522 : : const struct rte_flow_action_handle *handle,
12523 : : void *user_data, void *query_data,
12524 : : enum mlx5_hw_job_type type,
12525 : : enum mlx5_hw_indirect_type indirect_type,
12526 : : struct rte_flow_error *error)
12527 : : {
12528 : : struct mlx5_hw_q_job *job;
12529 : :
12530 [ # # # # : 0 : if (queue == MLX5_HW_INV_QUEUE)
# # # # #
# # # #
# ]
12531 [ # # # # : 0 : queue = CTRL_QUEUE_ID(priv);
# # # # #
# # # ]
12532 : : job = flow_hw_job_get(priv, queue);
12533 [ # # # # : 0 : if (!job) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # ]
12534 : 0 : rte_flow_error_set(error, ENOMEM,
12535 : : RTE_FLOW_ERROR_TYPE_ACTION_NUM, NULL,
12536 : : "Action destroy failed due to queue full.");
12537 : 0 : return NULL;
12538 : : }
12539 : 0 : job->type = type;
12540 : 0 : job->action = handle;
12541 : 0 : job->user_data = user_data;
12542 : 0 : job->query.user = query_data;
12543 [ # # # # : 0 : job->indirect_type = indirect_type;
# # # # #
# # # ]
12544 : 0 : return job;
12545 : : }
12546 : :
12547 : : struct mlx5_hw_q_job *
12548 [ # # ]: 0 : mlx5_flow_action_job_init(struct mlx5_priv *priv, uint32_t queue,
12549 : : const struct rte_flow_action_handle *handle,
12550 : : void *user_data, void *query_data,
12551 : : enum mlx5_hw_job_type type,
12552 : : struct rte_flow_error *error)
12553 : : {
12554 : 0 : return flow_hw_action_job_init(priv, queue, handle, user_data, query_data,
12555 : : type, MLX5_HW_INDIRECT_TYPE_LEGACY, error);
12556 : : }
12557 : :
12558 : : static __rte_always_inline void
12559 : : flow_hw_action_finalize(struct rte_eth_dev *dev, uint32_t queue,
12560 : : struct mlx5_hw_q_job *job,
12561 : : bool push, bool aso, bool status)
12562 : : {
12563 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12564 : :
12565 [ # # ]: 0 : if (queue == MLX5_HW_INV_QUEUE)
12566 : 0 : queue = CTRL_QUEUE_ID(priv);
12567 [ # # # # : 0 : if (likely(status)) {
# # # # #
# # # ]
12568 : : /* 1. add new job to a queue */
12569 [ # # # # : 0 : if (!aso)
# # # # #
# ]
12570 [ # # # # : 0 : rte_ring_enqueue(push ?
# # # # #
# # # #
# ]
12571 : 0 : priv->hw_q[queue].indir_cq :
12572 : 0 : priv->hw_q[queue].indir_iq,
12573 : : job);
12574 : : /* 2. send pending jobs */
12575 [ # # # # : 0 : if (push)
# # # # #
# # # #
# ]
12576 : 0 : __flow_hw_push_action(dev, queue);
12577 : : } else {
12578 : : flow_hw_job_put(priv, job, queue);
12579 : : }
12580 : : }
12581 : :
12582 : : /**
12583 : : * Create shared action.
12584 : : *
12585 : : * @param[in] dev
12586 : : * Pointer to the rte_eth_dev structure.
12587 : : * @param[in] queue
12588 : : * Which queue to be used.
12589 : : * @param[in] attr
12590 : : * Operation attribute.
12591 : : * @param[in] conf
12592 : : * Indirect action configuration.
12593 : : * @param[in] action
12594 : : * rte_flow action detail.
12595 : : * @param[in] user_data
12596 : : * Pointer to the user_data.
12597 : : * @param[out] error
12598 : : * Pointer to error structure.
12599 : : *
12600 : : * @return
12601 : : * Action handle on success, NULL otherwise and rte_errno is set.
12602 : : */
12603 : : static struct rte_flow_action_handle *
12604 : 0 : flow_hw_action_handle_create(struct rte_eth_dev *dev, uint32_t queue,
12605 : : const struct rte_flow_op_attr *attr,
12606 : : const struct rte_flow_indir_action_conf *conf,
12607 : : const struct rte_flow_action *action,
12608 : : void *user_data,
12609 : : struct rte_flow_error *error)
12610 : : {
12611 : : struct rte_flow_action_handle *handle = NULL;
12612 : : struct mlx5_hw_q_job *job = NULL;
12613 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
12614 : : const struct rte_flow_action_age *age;
12615 : : struct mlx5_aso_mtr *aso_mtr;
12616 : : cnt_id_t cnt_id;
12617 : : uint32_t age_idx;
12618 : : bool push = flow_hw_action_push(attr);
12619 : : bool aso = false;
12620 : 0 : bool force_job = action->type == RTE_FLOW_ACTION_TYPE_METER_MARK;
12621 : :
12622 [ # # ]: 0 : if (!mlx5_hw_ctx_validate(dev, error))
12623 : : return NULL;
12624 [ # # ]: 0 : if (attr || force_job) {
12625 : : job = flow_hw_action_job_init(priv, queue, NULL, user_data,
12626 : : NULL, MLX5_HW_Q_JOB_TYPE_CREATE,
12627 : : MLX5_HW_INDIRECT_TYPE_LEGACY, error);
12628 : : if (!job)
12629 : 0 : return NULL;
12630 : : }
12631 [ # # # # : 0 : switch (action->type) {
# # # ]
12632 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
12633 [ # # ]: 0 : if (priv->hws_strict_queue) {
12634 : 0 : struct mlx5_age_info *info = GET_PORT_AGE_INFO(priv);
12635 : :
12636 [ # # ]: 0 : if (queue >= info->hw_q_age->nb_rings) {
12637 : 0 : rte_flow_error_set(error, EINVAL,
12638 : : RTE_FLOW_ERROR_TYPE_ACTION,
12639 : : NULL,
12640 : : "Invalid queue ID for indirect AGE.");
12641 : 0 : rte_errno = EINVAL;
12642 : 0 : return NULL;
12643 : : }
12644 : : }
12645 : 0 : age = action->conf;
12646 : 0 : age_idx = mlx5_hws_age_action_create(priv, queue, true, age,
12647 : : 0, error);
12648 [ # # ]: 0 : if (age_idx == 0) {
12649 : 0 : rte_flow_error_set(error, ENODEV,
12650 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12651 : : "AGE are not configured!");
12652 : : } else {
12653 : 0 : age_idx = (MLX5_INDIRECT_ACTION_TYPE_AGE <<
12654 : : MLX5_INDIRECT_ACTION_TYPE_OFFSET) | age_idx;
12655 : 0 : handle =
12656 : 0 : (struct rte_flow_action_handle *)(uintptr_t)age_idx;
12657 : : }
12658 : : break;
12659 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
12660 [ # # ]: 0 : if (mlx5_hws_cnt_shared_get(priv->hws_cpool, &cnt_id, 0))
12661 : 0 : rte_flow_error_set(error, ENODEV,
12662 : : RTE_FLOW_ERROR_TYPE_ACTION,
12663 : : NULL,
12664 : : "counter are not configured!");
12665 : : else
12666 : 0 : handle = (struct rte_flow_action_handle *)
12667 : 0 : (uintptr_t)cnt_id;
12668 : : break;
12669 : 0 : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
12670 : : aso = true;
12671 : 0 : handle = flow_hw_conntrack_create(dev, queue, action->conf, job,
12672 : : push, error);
12673 : 0 : break;
12674 [ # # ]: 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
12675 : : aso = true;
12676 : : aso_mtr = flow_hw_meter_mark_alloc(dev, queue, action, job, push, error);
12677 : : if (!aso_mtr)
12678 : : break;
12679 : 0 : handle = (void *)(uintptr_t)job->action;
12680 : 0 : break;
12681 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
12682 : 0 : handle = flow_dv_action_create(dev, conf, action, error);
12683 : 0 : break;
12684 : 0 : case RTE_FLOW_ACTION_TYPE_QUOTA:
12685 : : aso = true;
12686 : 0 : handle = mlx5_quota_alloc(dev, queue, action->conf,
12687 : : job, push, error);
12688 : 0 : break;
12689 : 0 : default:
12690 : 0 : rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
12691 : : NULL, "action type not supported");
12692 : 0 : break;
12693 : : }
12694 [ # # ]: 0 : if (job && !force_job) {
12695 : 0 : job->action = handle;
12696 [ # # ]: 0 : flow_hw_action_finalize(dev, queue, job, push, aso,
12697 : : handle != NULL);
12698 : : }
12699 : : return handle;
12700 : : }
12701 : :
12702 : : static int
12703 : 0 : mlx5_flow_update_meter_mark(struct rte_eth_dev *dev, uint32_t queue,
12704 : : const struct rte_flow_update_meter_mark *upd_meter_mark,
12705 : : uint32_t idx, bool push,
12706 : : struct mlx5_hw_q_job *job, struct rte_flow_error *error)
12707 : : {
12708 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12709 : 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
12710 : : const struct rte_flow_action_meter_mark *meter_mark = &upd_meter_mark->meter_mark;
12711 : 0 : struct mlx5_aso_mtr *aso_mtr = mlx5_ipool_get(pool->idx_pool, idx);
12712 : : struct mlx5_flow_meter_info *fm;
12713 : :
12714 [ # # ]: 0 : if (!aso_mtr)
12715 : 0 : return rte_flow_error_set(error, EINVAL,
12716 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12717 : : NULL, "Invalid meter_mark update index");
12718 : : fm = &aso_mtr->fm;
12719 [ # # ]: 0 : if (upd_meter_mark->profile_valid)
12720 : 0 : fm->profile = (struct mlx5_flow_meter_profile *)
12721 : 0 : (meter_mark->profile);
12722 [ # # ]: 0 : if (upd_meter_mark->color_mode_valid)
12723 : 0 : fm->color_aware = meter_mark->color_mode;
12724 [ # # ]: 0 : if (upd_meter_mark->state_valid)
12725 : 0 : fm->is_enable = meter_mark->state;
12726 [ # # ]: 0 : aso_mtr->state = (queue == MLX5_HW_INV_QUEUE) ?
12727 : : ASO_METER_WAIT : ASO_METER_WAIT_ASYNC;
12728 : : /* Update ASO flow meter by wqe. */
12729 [ # # ]: 0 : if (mlx5_aso_meter_update_by_wqe(priv, queue,
12730 : : aso_mtr, &priv->mtr_bulk, job, push))
12731 : 0 : return rte_flow_error_set(error, EINVAL,
12732 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12733 : : NULL, "Unable to update ASO meter WQE");
12734 : : /* Wait for ASO object completion. */
12735 [ # # # # ]: 0 : if (queue == MLX5_HW_INV_QUEUE &&
12736 : 0 : mlx5_aso_mtr_wait(priv, aso_mtr, true))
12737 : 0 : return rte_flow_error_set(error, EINVAL,
12738 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12739 : : NULL, "Unable to wait for ASO meter CQE");
12740 : : return 0;
12741 : : }
12742 : :
12743 : : /**
12744 : : * Update shared action.
12745 : : *
12746 : : * @param[in] dev
12747 : : * Pointer to the rte_eth_dev structure.
12748 : : * @param[in] queue
12749 : : * Which queue to be used.
12750 : : * @param[in] attr
12751 : : * Operation attribute.
12752 : : * @param[in] handle
12753 : : * Action handle to be updated.
12754 : : * @param[in] update
12755 : : * Update value.
12756 : : * @param[in] user_data
12757 : : * Pointer to the user_data.
12758 : : * @param[out] error
12759 : : * Pointer to error structure.
12760 : : *
12761 : : * @return
12762 : : * 0 on success, negative value otherwise and rte_errno is set.
12763 : : */
12764 : : static int
12765 : 0 : flow_hw_action_handle_update(struct rte_eth_dev *dev, uint32_t queue,
12766 : : const struct rte_flow_op_attr *attr,
12767 : : struct rte_flow_action_handle *handle,
12768 : : const void *update,
12769 : : void *user_data,
12770 : : struct rte_flow_error *error)
12771 : : {
12772 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12773 : : const struct rte_flow_modify_conntrack *ct_conf =
12774 : : (const struct rte_flow_modify_conntrack *)update;
12775 : : struct mlx5_hw_q_job *job = NULL;
12776 : 0 : uint32_t act_idx = (uint32_t)(uintptr_t)handle;
12777 : 0 : uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
12778 [ # # ]: 0 : uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
12779 : : int ret = 0;
12780 : : bool push = flow_hw_action_push(attr);
12781 : : bool aso = false;
12782 : 0 : bool force_job = type == MLX5_INDIRECT_ACTION_TYPE_METER_MARK;
12783 : :
12784 [ # # ]: 0 : if (attr || force_job) {
12785 : : job = flow_hw_action_job_init(priv, queue, handle, user_data,
12786 : : NULL, MLX5_HW_Q_JOB_TYPE_UPDATE,
12787 : : MLX5_HW_INDIRECT_TYPE_LEGACY, error);
12788 : : if (!job)
12789 : 0 : return -rte_errno;
12790 : : }
12791 [ # # # # : 0 : switch (type) {
# # ]
12792 : 0 : case MLX5_INDIRECT_ACTION_TYPE_AGE:
12793 : 0 : ret = mlx5_hws_age_action_update(priv, idx, update, error);
12794 : 0 : break;
12795 : 0 : case MLX5_INDIRECT_ACTION_TYPE_CT:
12796 [ # # ]: 0 : if (ct_conf->state)
12797 : : aso = true;
12798 : 0 : ret = flow_hw_conntrack_update(dev, queue, update, idx,
12799 : : job, push, error);
12800 : 0 : break;
12801 : 0 : case MLX5_INDIRECT_ACTION_TYPE_METER_MARK:
12802 : : aso = true;
12803 : 0 : ret = mlx5_flow_update_meter_mark(dev, queue, update, idx, push,
12804 : : job, error);
12805 : 0 : break;
12806 : 0 : case MLX5_INDIRECT_ACTION_TYPE_RSS:
12807 : 0 : ret = flow_dv_action_update(dev, handle, update, error);
12808 : 0 : break;
12809 : 0 : case MLX5_INDIRECT_ACTION_TYPE_QUOTA:
12810 : : aso = true;
12811 : 0 : ret = mlx5_quota_query_update(dev, queue, handle, update, NULL,
12812 : : job, push, error);
12813 : 0 : break;
12814 : 0 : default:
12815 : : ret = -ENOTSUP;
12816 : 0 : rte_flow_error_set(error, ENOTSUP,
12817 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12818 : : "action type not supported");
12819 : 0 : break;
12820 : : }
12821 [ # # ]: 0 : if (job && !force_job)
12822 [ # # ]: 0 : flow_hw_action_finalize(dev, queue, job, push, aso, ret == 0);
12823 : : return ret;
12824 : : }
12825 : :
12826 : : /**
12827 : : * Destroy shared action.
12828 : : *
12829 : : * @param[in] dev
12830 : : * Pointer to the rte_eth_dev structure.
12831 : : * @param[in] queue
12832 : : * Which queue to be used.
12833 : : * @param[in] attr
12834 : : * Operation attribute.
12835 : : * @param[in] handle
12836 : : * Action handle to be destroyed.
12837 : : * @param[in] user_data
12838 : : * Pointer to the user_data.
12839 : : * @param[out] error
12840 : : * Pointer to error structure.
12841 : : *
12842 : : * @return
12843 : : * 0 on success, negative value otherwise and rte_errno is set.
12844 : : */
12845 : : static int
12846 : 0 : flow_hw_action_handle_destroy(struct rte_eth_dev *dev, uint32_t queue,
12847 : : const struct rte_flow_op_attr *attr,
12848 : : struct rte_flow_action_handle *handle,
12849 : : void *user_data,
12850 : : struct rte_flow_error *error)
12851 : : {
12852 : 0 : uint32_t act_idx = (uint32_t)(uintptr_t)handle;
12853 : 0 : uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
12854 : 0 : uint32_t age_idx = act_idx & MLX5_HWS_AGE_IDX_MASK;
12855 : : uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
12856 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12857 [ # # ]: 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
12858 : : struct mlx5_hw_q_job *job = NULL;
12859 : : struct mlx5_aso_mtr *aso_mtr;
12860 : : struct mlx5_flow_meter_info *fm;
12861 : : bool push = flow_hw_action_push(attr);
12862 : : bool aso = false;
12863 : : int ret = 0;
12864 : 0 : bool force_job = type == MLX5_INDIRECT_ACTION_TYPE_METER_MARK;
12865 : :
12866 [ # # ]: 0 : if (attr || force_job) {
12867 : : job = flow_hw_action_job_init(priv, queue, handle, user_data,
12868 : : NULL, MLX5_HW_Q_JOB_TYPE_DESTROY,
12869 : : MLX5_HW_INDIRECT_TYPE_LEGACY, error);
12870 : : if (!job)
12871 : 0 : return -rte_errno;
12872 : : }
12873 [ # # # # : 0 : switch (type) {
# # # ]
12874 : 0 : case MLX5_INDIRECT_ACTION_TYPE_AGE:
12875 : 0 : ret = mlx5_hws_age_action_destroy(priv, age_idx, error);
12876 : 0 : break;
12877 : 0 : case MLX5_INDIRECT_ACTION_TYPE_COUNT:
12878 [ # # ]: 0 : age_idx = mlx5_hws_cnt_age_get(priv->hws_cpool, act_idx);
12879 [ # # ]: 0 : if (age_idx != 0)
12880 : : /*
12881 : : * If this counter belongs to indirect AGE, here is the
12882 : : * time to update the AGE.
12883 : : */
12884 : : mlx5_hws_age_nb_cnt_decrease(priv, age_idx);
12885 [ # # ]: 0 : mlx5_hws_cnt_shared_put(priv->hws_cpool, &act_idx);
12886 : : break;
12887 : 0 : case MLX5_INDIRECT_ACTION_TYPE_CT:
12888 : 0 : ret = flow_hw_conntrack_destroy(dev, idx, error);
12889 : 0 : break;
12890 : 0 : case MLX5_INDIRECT_ACTION_TYPE_METER_MARK:
12891 : 0 : aso_mtr = mlx5_ipool_get(pool->idx_pool, idx);
12892 [ # # ]: 0 : if (!aso_mtr) {
12893 : : ret = -EINVAL;
12894 : 0 : rte_flow_error_set(error, EINVAL,
12895 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12896 : : NULL, "Invalid meter_mark destroy index");
12897 : 0 : break;
12898 : : }
12899 : : fm = &aso_mtr->fm;
12900 : 0 : fm->is_enable = 0;
12901 : : /* Update ASO flow meter by wqe. */
12902 [ # # ]: 0 : if (mlx5_aso_meter_update_by_wqe(priv, queue, aso_mtr,
12903 : : &priv->mtr_bulk, job, push)) {
12904 : : ret = -EINVAL;
12905 : 0 : rte_flow_error_set(error, EINVAL,
12906 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12907 : : NULL, "Unable to update ASO meter WQE");
12908 : 0 : break;
12909 : : }
12910 : : /* Wait for ASO object completion. */
12911 [ # # # # ]: 0 : if (queue == MLX5_HW_INV_QUEUE &&
12912 : 0 : mlx5_aso_mtr_wait(priv, aso_mtr, true)) {
12913 : : ret = -EINVAL;
12914 : 0 : rte_flow_error_set(error, EINVAL,
12915 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12916 : : NULL, "Unable to wait for ASO meter CQE");
12917 : 0 : break;
12918 : : }
12919 : : aso = true;
12920 : : break;
12921 : 0 : case MLX5_INDIRECT_ACTION_TYPE_RSS:
12922 : 0 : ret = flow_dv_action_destroy(dev, handle, error);
12923 : 0 : break;
12924 : : case MLX5_INDIRECT_ACTION_TYPE_QUOTA:
12925 : : break;
12926 : 0 : default:
12927 : : ret = -ENOTSUP;
12928 : 0 : rte_flow_error_set(error, ENOTSUP,
12929 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12930 : : "action type not supported");
12931 : 0 : break;
12932 : : }
12933 [ # # ]: 0 : if (job && !force_job)
12934 [ # # ]: 0 : flow_hw_action_finalize(dev, queue, job, push, aso, ret == 0);
12935 : : return ret;
12936 : : }
12937 : :
12938 : : static int
12939 : 0 : flow_hw_query_counter(const struct rte_eth_dev *dev, uint32_t counter,
12940 : : void *data, struct rte_flow_error *error)
12941 : : {
12942 : : struct mlx5_hws_cnt_pool *hpool;
12943 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
12944 : : struct mlx5_hws_cnt *cnt;
12945 : : struct rte_flow_query_count *qc = data;
12946 : : uint32_t iidx;
12947 : : uint64_t pkts, bytes;
12948 : :
12949 [ # # ]: 0 : if (!mlx5_hws_cnt_id_valid(counter))
12950 : 0 : return rte_flow_error_set(error, EINVAL,
12951 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12952 : : "counter are not available");
12953 [ # # ]: 0 : hpool = mlx5_hws_cnt_host_pool(priv->hws_cpool);
12954 : : iidx = mlx5_hws_cnt_iidx(hpool, counter);
12955 : 0 : cnt = &hpool->pool[iidx];
12956 : : __hws_cnt_query_raw(priv->hws_cpool, counter, &pkts, &bytes);
12957 : 0 : qc->hits_set = 1;
12958 : 0 : qc->bytes_set = 1;
12959 : 0 : qc->hits = pkts - cnt->reset.hits;
12960 : 0 : qc->bytes = bytes - cnt->reset.bytes;
12961 [ # # ]: 0 : if (qc->reset) {
12962 : 0 : cnt->reset.bytes = bytes;
12963 : 0 : cnt->reset.hits = pkts;
12964 : : }
12965 : : return 0;
12966 : : }
12967 : :
12968 : : /**
12969 : : * Query a flow rule AGE action for aging information.
12970 : : *
12971 : : * @param[in] dev
12972 : : * Pointer to Ethernet device.
12973 : : * @param[in] age_idx
12974 : : * Index of AGE action parameter.
12975 : : * @param[out] data
12976 : : * Data retrieved by the query.
12977 : : * @param[out] error
12978 : : * Perform verbose error reporting if not NULL.
12979 : : *
12980 : : * @return
12981 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
12982 : : */
12983 : : static int
12984 : 0 : flow_hw_query_age(const struct rte_eth_dev *dev, uint32_t age_idx, void *data,
12985 : : struct rte_flow_error *error)
12986 : : {
12987 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12988 : 0 : struct mlx5_age_info *age_info = GET_PORT_AGE_INFO(priv);
12989 : 0 : struct mlx5_indexed_pool *ipool = age_info->ages_ipool;
12990 : 0 : struct mlx5_hws_age_param *param = mlx5_ipool_get(ipool, age_idx);
12991 : : struct rte_flow_query_age *resp = data;
12992 : :
12993 [ # # # # ]: 0 : if (!param || !param->timeout)
12994 : 0 : return rte_flow_error_set(error, EINVAL,
12995 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12996 : : NULL, "age data not available");
12997 [ # # # ]: 0 : switch (rte_atomic_load_explicit(¶m->state, rte_memory_order_relaxed)) {
12998 : 0 : case HWS_AGE_AGED_OUT_REPORTED:
12999 : : case HWS_AGE_AGED_OUT_NOT_REPORTED:
13000 : 0 : resp->aged = 1;
13001 : 0 : break;
13002 : 0 : case HWS_AGE_CANDIDATE:
13003 : : case HWS_AGE_CANDIDATE_INSIDE_RING:
13004 : 0 : resp->aged = 0;
13005 : 0 : break;
13006 : : case HWS_AGE_FREE:
13007 : : /*
13008 : : * When state is FREE the flow itself should be invalid.
13009 : : * Fall-through.
13010 : : */
13011 : : default:
13012 : : MLX5_ASSERT(0);
13013 : : break;
13014 : : }
13015 : 0 : resp->sec_since_last_hit_valid = !resp->aged;
13016 [ # # ]: 0 : if (resp->sec_since_last_hit_valid)
13017 : 0 : resp->sec_since_last_hit = rte_atomic_load_explicit
13018 : : (¶m->sec_since_last_hit, rte_memory_order_relaxed);
13019 : : return 0;
13020 : : }
13021 : :
13022 : : static int
13023 : 0 : flow_hw_query(struct rte_eth_dev *dev, struct rte_flow *flow,
13024 : : const struct rte_flow_action *actions, void *data,
13025 : : struct rte_flow_error *error)
13026 : : {
13027 : : int ret = -EINVAL;
13028 : : struct rte_flow_hw *hw_flow = (struct rte_flow_hw *)flow;
13029 : : struct rte_flow_hw_aux *aux;
13030 : :
13031 [ # # ]: 0 : for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
13032 [ # # # # ]: 0 : switch (actions->type) {
13033 : : case RTE_FLOW_ACTION_TYPE_VOID:
13034 : : break;
13035 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
13036 [ # # ]: 0 : if (!(hw_flow->flags & MLX5_FLOW_HW_FLOW_FLAG_CNT_ID))
13037 : 0 : return rte_flow_error_set(error, EINVAL,
13038 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13039 : : "counter not defined in the rule");
13040 : 0 : ret = flow_hw_query_counter(dev, hw_flow->cnt_id, data,
13041 : : error);
13042 : 0 : break;
13043 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
13044 [ # # ]: 0 : if (!(hw_flow->flags & MLX5_FLOW_HW_FLOW_FLAG_AGE_IDX))
13045 : 0 : return rte_flow_error_set(error, EINVAL,
13046 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13047 : : "age data not available");
13048 : 0 : aux = mlx5_flow_hw_aux(dev->data->port_id, hw_flow);
13049 : 0 : ret = flow_hw_query_age(dev, mlx5_flow_hw_aux_get_age_idx(hw_flow, aux),
13050 : : data, error);
13051 : 0 : break;
13052 : 0 : default:
13053 : 0 : return rte_flow_error_set(error, ENOTSUP,
13054 : : RTE_FLOW_ERROR_TYPE_ACTION,
13055 : : actions,
13056 : : "action not supported");
13057 : : }
13058 : : }
13059 : : return ret;
13060 : : }
13061 : :
13062 : : /**
13063 : : * Validate indirect action.
13064 : : *
13065 : : * @param[in] dev
13066 : : * Pointer to the Ethernet device structure.
13067 : : * @param[in] conf
13068 : : * Shared action configuration.
13069 : : * @param[in] action
13070 : : * Action specification used to create indirect action.
13071 : : * @param[out] error
13072 : : * Perform verbose error reporting if not NULL. Initialized in case of
13073 : : * error only.
13074 : : *
13075 : : * @return
13076 : : * 0 on success, otherwise negative errno value.
13077 : : */
13078 : : static int
13079 : 0 : flow_hw_action_validate(struct rte_eth_dev *dev,
13080 : : const struct rte_flow_indir_action_conf *conf,
13081 : : const struct rte_flow_action *action,
13082 : : struct rte_flow_error *err)
13083 : : {
13084 : 0 : struct rte_flow_error shadow_error = {0, };
13085 : :
13086 [ # # ]: 0 : if (!err)
13087 : : err = &shadow_error;
13088 : 0 : return flow_hw_action_handle_validate(dev, MLX5_HW_INV_QUEUE, NULL,
13089 : : conf, action, NULL, err);
13090 : : }
13091 : :
13092 : : /**
13093 : : * Create indirect action.
13094 : : *
13095 : : * @param[in] dev
13096 : : * Pointer to the Ethernet device structure.
13097 : : * @param[in] conf
13098 : : * Shared action configuration.
13099 : : * @param[in] action
13100 : : * Action specification used to create indirect action.
13101 : : * @param[out] error
13102 : : * Perform verbose error reporting if not NULL. Initialized in case of
13103 : : * error only.
13104 : : *
13105 : : * @return
13106 : : * A valid shared action handle in case of success, NULL otherwise and
13107 : : * rte_errno is set.
13108 : : */
13109 : : static struct rte_flow_action_handle *
13110 : 0 : flow_hw_action_create(struct rte_eth_dev *dev,
13111 : : const struct rte_flow_indir_action_conf *conf,
13112 : : const struct rte_flow_action *action,
13113 : : struct rte_flow_error *err)
13114 : : {
13115 : 0 : return flow_hw_action_handle_create(dev, MLX5_HW_INV_QUEUE,
13116 : : NULL, conf, action, NULL, err);
13117 : : }
13118 : :
13119 : : /**
13120 : : * Destroy the indirect action.
13121 : : * Release action related resources on the NIC and the memory.
13122 : : * Lock free, (mutex should be acquired by caller).
13123 : : * Dispatcher for action type specific call.
13124 : : *
13125 : : * @param[in] dev
13126 : : * Pointer to the Ethernet device structure.
13127 : : * @param[in] handle
13128 : : * The indirect action object handle to be removed.
13129 : : * @param[out] error
13130 : : * Perform verbose error reporting if not NULL. Initialized in case of
13131 : : * error only.
13132 : : *
13133 : : * @return
13134 : : * 0 on success, otherwise negative errno value.
13135 : : */
13136 : : static int
13137 : 0 : flow_hw_action_destroy(struct rte_eth_dev *dev,
13138 : : struct rte_flow_action_handle *handle,
13139 : : struct rte_flow_error *error)
13140 : : {
13141 : 0 : return flow_hw_action_handle_destroy(dev, MLX5_HW_INV_QUEUE,
13142 : : NULL, handle, NULL, error);
13143 : : }
13144 : :
13145 : : /**
13146 : : * Updates in place shared action configuration.
13147 : : *
13148 : : * @param[in] dev
13149 : : * Pointer to the Ethernet device structure.
13150 : : * @param[in] handle
13151 : : * The indirect action object handle to be updated.
13152 : : * @param[in] update
13153 : : * Action specification used to modify the action pointed by *handle*.
13154 : : * *update* could be of same type with the action pointed by the *handle*
13155 : : * handle argument, or some other structures like a wrapper, depending on
13156 : : * the indirect action type.
13157 : : * @param[out] error
13158 : : * Perform verbose error reporting if not NULL. Initialized in case of
13159 : : * error only.
13160 : : *
13161 : : * @return
13162 : : * 0 on success, otherwise negative errno value.
13163 : : */
13164 : : static int
13165 : 0 : flow_hw_action_update(struct rte_eth_dev *dev,
13166 : : struct rte_flow_action_handle *handle,
13167 : : const void *update,
13168 : : struct rte_flow_error *err)
13169 : : {
13170 : 0 : return flow_hw_action_handle_update(dev, MLX5_HW_INV_QUEUE,
13171 : : NULL, handle, update, NULL, err);
13172 : : }
13173 : :
13174 : : static int
13175 : 0 : flow_hw_action_handle_query(struct rte_eth_dev *dev, uint32_t queue,
13176 : : const struct rte_flow_op_attr *attr,
13177 : : const struct rte_flow_action_handle *handle,
13178 : : void *data, void *user_data,
13179 : : struct rte_flow_error *error)
13180 : : {
13181 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13182 : : struct mlx5_hw_q_job *job = NULL;
13183 : 0 : uint32_t act_idx = (uint32_t)(uintptr_t)handle;
13184 : 0 : uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
13185 [ # # ]: 0 : uint32_t idx = MLX5_INDIRECT_ACTION_IDX_GET(handle);
13186 : : uint32_t age_idx = act_idx & MLX5_HWS_AGE_IDX_MASK;
13187 : : int ret;
13188 : : bool push = flow_hw_action_push(attr);
13189 : : bool aso = false;
13190 : :
13191 [ # # ]: 0 : if (attr) {
13192 : : job = flow_hw_action_job_init(priv, queue, handle, user_data,
13193 : : data, MLX5_HW_Q_JOB_TYPE_QUERY,
13194 : : MLX5_HW_INDIRECT_TYPE_LEGACY, error);
13195 : : if (!job)
13196 : 0 : return -rte_errno;
13197 : : }
13198 [ # # # # : 0 : switch (type) {
# ]
13199 : 0 : case MLX5_INDIRECT_ACTION_TYPE_AGE:
13200 : 0 : ret = flow_hw_query_age(dev, age_idx, data, error);
13201 : 0 : break;
13202 : 0 : case MLX5_INDIRECT_ACTION_TYPE_COUNT:
13203 : 0 : ret = flow_hw_query_counter(dev, act_idx, data, error);
13204 : 0 : break;
13205 : 0 : case MLX5_INDIRECT_ACTION_TYPE_CT:
13206 : : aso = true;
13207 [ # # ]: 0 : if (job)
13208 : 0 : job->query.user = data;
13209 : 0 : ret = flow_hw_conntrack_query(dev, queue, idx, data,
13210 : : job, push, error);
13211 : 0 : break;
13212 : 0 : case MLX5_INDIRECT_ACTION_TYPE_QUOTA:
13213 : : aso = true;
13214 : 0 : ret = mlx5_quota_query(dev, queue, handle, data,
13215 : : job, push, error);
13216 : 0 : break;
13217 : 0 : default:
13218 : : ret = -ENOTSUP;
13219 : 0 : rte_flow_error_set(error, ENOTSUP,
13220 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13221 : : "action type not supported");
13222 : 0 : break;
13223 : : }
13224 [ # # ]: 0 : if (job)
13225 [ # # ]: 0 : flow_hw_action_finalize(dev, queue, job, push, aso, ret == 0);
13226 : : return ret;
13227 : : }
13228 : :
13229 : : static int
13230 : 0 : flow_hw_async_action_handle_query_update
13231 : : (struct rte_eth_dev *dev, uint32_t queue,
13232 : : const struct rte_flow_op_attr *attr,
13233 : : struct rte_flow_action_handle *handle,
13234 : : const void *update, void *query,
13235 : : enum rte_flow_query_update_mode qu_mode,
13236 : : void *user_data, struct rte_flow_error *error)
13237 : : {
13238 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
13239 : : bool push = flow_hw_action_push(attr);
13240 : : bool aso = false;
13241 : : struct mlx5_hw_q_job *job = NULL;
13242 : : int ret = 0;
13243 : :
13244 [ # # ]: 0 : if (attr) {
13245 : : job = flow_hw_action_job_init(priv, queue, handle, user_data,
13246 : : query,
13247 : : MLX5_HW_Q_JOB_TYPE_UPDATE_QUERY,
13248 : : MLX5_HW_INDIRECT_TYPE_LEGACY, error);
13249 : : if (!job)
13250 : 0 : return -rte_errno;
13251 : : }
13252 [ # # ]: 0 : switch (MLX5_INDIRECT_ACTION_TYPE_GET(handle)) {
13253 : 0 : case MLX5_INDIRECT_ACTION_TYPE_QUOTA:
13254 [ # # ]: 0 : if (qu_mode != RTE_FLOW_QU_QUERY_FIRST) {
13255 : 0 : ret = rte_flow_error_set
13256 : : (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION_CONF,
13257 : : NULL, "quota action must query before update");
13258 : 0 : break;
13259 : : }
13260 : : aso = true;
13261 : 0 : ret = mlx5_quota_query_update(dev, queue, handle,
13262 : : update, query, job, push, error);
13263 : 0 : break;
13264 : 0 : default:
13265 : 0 : ret = rte_flow_error_set(error, ENOTSUP,
13266 : : RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, "update and query not supportred");
13267 : : }
13268 [ # # ]: 0 : if (job)
13269 [ # # ]: 0 : flow_hw_action_finalize(dev, queue, job, push, aso, ret == 0);
13270 : : return ret;
13271 : : }
13272 : :
13273 : : static int
13274 : 0 : flow_hw_action_query(struct rte_eth_dev *dev,
13275 : : const struct rte_flow_action_handle *handle, void *data,
13276 : : struct rte_flow_error *error)
13277 : : {
13278 : 0 : return flow_hw_action_handle_query(dev, MLX5_HW_INV_QUEUE, NULL,
13279 : : handle, data, NULL, error);
13280 : : }
13281 : :
13282 : : static int
13283 : 0 : flow_hw_action_query_update(struct rte_eth_dev *dev,
13284 : : struct rte_flow_action_handle *handle,
13285 : : const void *update, void *query,
13286 : : enum rte_flow_query_update_mode qu_mode,
13287 : : struct rte_flow_error *error)
13288 : : {
13289 : 0 : return flow_hw_async_action_handle_query_update(dev, MLX5_HW_INV_QUEUE,
13290 : : NULL, handle, update,
13291 : : query, qu_mode, NULL,
13292 : : error);
13293 : : }
13294 : :
13295 : : /**
13296 : : * Get aged-out flows of a given port on the given HWS flow queue.
13297 : : *
13298 : : * @param[in] dev
13299 : : * Pointer to the Ethernet device structure.
13300 : : * @param[in] queue_id
13301 : : * Flow queue to query. Ignored when RTE_FLOW_PORT_FLAG_STRICT_QUEUE not set.
13302 : : * @param[in, out] contexts
13303 : : * The address of an array of pointers to the aged-out flows contexts.
13304 : : * @param[in] nb_contexts
13305 : : * The length of context array pointers.
13306 : : * @param[out] error
13307 : : * Perform verbose error reporting if not NULL. Initialized in case of
13308 : : * error only.
13309 : : *
13310 : : * @return
13311 : : * if nb_contexts is 0, return the amount of all aged contexts.
13312 : : * if nb_contexts is not 0 , return the amount of aged flows reported
13313 : : * in the context array, otherwise negative errno value.
13314 : : */
13315 : : static int
13316 : 0 : flow_hw_get_q_aged_flows(struct rte_eth_dev *dev, uint32_t queue_id,
13317 : : void **contexts, uint32_t nb_contexts,
13318 : : struct rte_flow_error *error)
13319 : : {
13320 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13321 : 0 : struct mlx5_age_info *age_info = GET_PORT_AGE_INFO(priv);
13322 : : struct rte_ring *r;
13323 : : int nb_flows = 0;
13324 : :
13325 [ # # ]: 0 : if (nb_contexts && !contexts)
13326 : 0 : return rte_flow_error_set(error, EINVAL,
13327 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13328 : : NULL, "empty context");
13329 [ # # ]: 0 : if (!priv->hws_age_req)
13330 : 0 : return rte_flow_error_set(error, ENOENT,
13331 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13332 : : NULL, "No aging initialized");
13333 [ # # ]: 0 : if (priv->hws_strict_queue) {
13334 [ # # ]: 0 : if (queue_id >= age_info->hw_q_age->nb_rings)
13335 : 0 : return rte_flow_error_set(error, EINVAL,
13336 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13337 : : NULL, "invalid queue id");
13338 : 0 : r = age_info->hw_q_age->aged_lists[queue_id];
13339 : : } else {
13340 : 0 : r = age_info->hw_age.aged_list;
13341 : 0 : MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
13342 : : }
13343 [ # # ]: 0 : if (nb_contexts == 0)
13344 : 0 : return rte_ring_count(r);
13345 [ # # ]: 0 : while ((uint32_t)nb_flows < nb_contexts) {
13346 : : uint32_t age_idx;
13347 : :
13348 : : if (rte_ring_dequeue_elem(r, &age_idx, sizeof(uint32_t)) < 0)
13349 : : break;
13350 : : /* get the AGE context if the aged-out index is still valid. */
13351 : 0 : contexts[nb_flows] = mlx5_hws_age_context_get(priv, age_idx);
13352 [ # # ]: 0 : if (!contexts[nb_flows])
13353 : 0 : continue;
13354 : 0 : nb_flows++;
13355 : : }
13356 : : return nb_flows;
13357 : : }
13358 : :
13359 : : /**
13360 : : * Get aged-out flows.
13361 : : *
13362 : : * This function is relevant only if RTE_FLOW_PORT_FLAG_STRICT_QUEUE isn't set.
13363 : : *
13364 : : * @param[in] dev
13365 : : * Pointer to the Ethernet device structure.
13366 : : * @param[in] contexts
13367 : : * The address of an array of pointers to the aged-out flows contexts.
13368 : : * @param[in] nb_contexts
13369 : : * The length of context array pointers.
13370 : : * @param[out] error
13371 : : * Perform verbose error reporting if not NULL. Initialized in case of
13372 : : * error only.
13373 : : *
13374 : : * @return
13375 : : * how many contexts get in success, otherwise negative errno value.
13376 : : * if nb_contexts is 0, return the amount of all aged contexts.
13377 : : * if nb_contexts is not 0 , return the amount of aged flows reported
13378 : : * in the context array.
13379 : : */
13380 : : static int
13381 : 0 : flow_hw_get_aged_flows(struct rte_eth_dev *dev, void **contexts,
13382 : : uint32_t nb_contexts, struct rte_flow_error *error)
13383 : : {
13384 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13385 : :
13386 [ # # ]: 0 : if (priv->hws_strict_queue)
13387 : 0 : DRV_LOG(WARNING,
13388 : : "port %u get aged flows called in strict queue mode.",
13389 : : dev->data->port_id);
13390 : 0 : return flow_hw_get_q_aged_flows(dev, 0, contexts, nb_contexts, error);
13391 : : }
13392 : : /**
13393 : : * Initialization function for non template API which calls
13394 : : * flow_hw_configure with default values.
13395 : : * Configure non queues cause 1 queue is configured by default for inner usage.
13396 : : *
13397 : : * @param[in] dev
13398 : : * Pointer to the Ethernet device structure.
13399 : : * @param[out] error
13400 : : * Pointer to the error structure.
13401 : : *
13402 : : * @return
13403 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
13404 : : */
13405 : : int
13406 : 0 : flow_hw_init(struct rte_eth_dev *dev,
13407 : : struct rte_flow_error *error)
13408 : : {
13409 : 0 : const struct rte_flow_port_attr port_attr = {0};
13410 : 0 : const struct rte_flow_queue_attr queue_attr = {.size = MLX5_NT_DEFAULT_QUEUE_SIZE};
13411 : 0 : const struct rte_flow_queue_attr *attr_list = &queue_attr;
13412 : :
13413 : : /**
13414 : : * If user uses template and non template API:
13415 : : * User will call flow_hw_configure and non template
13416 : : * API will use the allocated actions.
13417 : : * Init function will not call flow_hw_configure.
13418 : : *
13419 : : * If user uses only non template API's:
13420 : : * Init function will call flow_hw_configure.
13421 : : * It will not allocate memory for actions.
13422 : : * When needed allocation, it will handle same as for SWS today,
13423 : : * meaning using bulk allocations and resize as needed.
13424 : : */
13425 : : /* Configure hws with default values. */
13426 : 0 : DRV_LOG(DEBUG, "Apply default configuration, zero number of queues, inner control queue size is %u",
13427 : : MLX5_NT_DEFAULT_QUEUE_SIZE);
13428 : 0 : return __flow_hw_configure(dev, &port_attr, 0, &attr_list, true, error);
13429 : : }
13430 : :
13431 : 0 : static int flow_hw_prepare(struct rte_eth_dev *dev,
13432 : : const struct rte_flow_action actions[] __rte_unused,
13433 : : enum mlx5_flow_type type,
13434 : : struct rte_flow_hw **flow,
13435 : : struct rte_flow_error *error)
13436 : : {
13437 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13438 : 0 : uint32_t idx = 0;
13439 : :
13440 : : /*
13441 : : * Notice pool idx size = (sizeof(struct rte_flow_hw)
13442 : : * + sizeof(struct rte_flow_nt2hws)) for HWS mode.
13443 : : */
13444 : 0 : *flow = mlx5_ipool_zmalloc(priv->flows[type], &idx);
13445 [ # # ]: 0 : if (!(*flow))
13446 : 0 : return rte_flow_error_set(error, ENOMEM,
13447 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13448 : : "cannot allocate flow memory");
13449 : : /* Allocating 2 structures in one pool slot, updating nt2hw pointer.*/
13450 : 0 : (*flow)->nt2hws = (struct rte_flow_nt2hws *)
13451 : 0 : ((uintptr_t)(*flow) + sizeof(struct rte_flow_hw));
13452 : 0 : (*flow)->idx = idx;
13453 : 0 : (*flow)->nt2hws->flow_aux = mlx5_malloc(MLX5_MEM_ZERO, sizeof(struct rte_flow_hw_aux),
13454 : 0 : RTE_CACHE_LINE_SIZE, rte_dev_numa_node(dev->device));
13455 [ # # ]: 0 : if (!(*flow)->nt2hws->flow_aux)
13456 : 0 : return rte_flow_error_set(error, ENOMEM,
13457 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13458 : : "cannot allocate flow aux memory");
13459 : : return 0;
13460 : : }
13461 : :
13462 : : static inline void
13463 : 0 : flow_hw_set_dv_fields(struct rte_flow_template_table_attr *table_attr, uint32_t fdb_unified_en,
13464 : : bool *root, uint8_t *ft_type, uint64_t *flags)
13465 : : {
13466 [ # # ]: 0 : if (table_attr->flow_attr.transfer)
13467 : 0 : *ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
13468 : : else
13469 : 0 : *ft_type = table_attr->flow_attr.egress ?
13470 : 0 : MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
13471 : : MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
13472 : 0 : uint32_t group = table_attr->flow_attr.group;
13473 : 0 : *root = group ? 0 : 1;
13474 : 0 : *flags = mlx5_hw_act_flag[!!group][get_mlx5dr_table_type(&table_attr->flow_attr,
13475 : : table_attr->specialize,
13476 : : fdb_unified_en)];
13477 : 0 : }
13478 : :
13479 : : static int
13480 : 0 : flow_hw_modify_hdr_resource_register
13481 : : (struct rte_eth_dev *dev,
13482 : : struct rte_flow_template_table *table,
13483 : : struct mlx5_hw_actions *hw_acts,
13484 : : struct rte_flow_hw *dev_flow,
13485 : : struct rte_flow_error *error)
13486 : : {
13487 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
13488 : : bool unified_fdb = is_unified_fdb(priv);
13489 : 0 : struct rte_flow_template_table_attr *table_attr = &table->cfg.attr;
13490 : 0 : struct mlx5_flow_dv_modify_hdr_resource *dv_resource_ptr = NULL;
13491 : : union {
13492 : : struct mlx5_flow_dv_modify_hdr_resource dv_resource;
13493 : : uint8_t data[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
13494 : : sizeof(struct mlx5_modification_cmd) * MLX5_MHDR_MAX_CMD];
13495 : : } dummy;
13496 : : int ret;
13497 : :
13498 [ # # ]: 0 : if (hw_acts->mhdr) {
13499 : 0 : dummy.dv_resource.actions_num = hw_acts->mhdr->mhdr_cmds_num;
13500 : 0 : memcpy(dummy.dv_resource.actions, hw_acts->mhdr->mhdr_cmds,
13501 : 0 : sizeof(struct mlx5_modification_cmd) * dummy.dv_resource.actions_num);
13502 : : } else {
13503 : : return 0;
13504 : : }
13505 : 0 : flow_hw_set_dv_fields(table_attr, unified_fdb,
13506 : : &dummy.dv_resource.root, &dummy.dv_resource.ft_type,
13507 : : &dummy.dv_resource.flags);
13508 : 0 : dummy.dv_resource.flags |= MLX5DR_ACTION_FLAG_SHARED;
13509 : 0 : ret = __flow_modify_hdr_resource_register(dev, &dummy.dv_resource,
13510 : : &dv_resource_ptr, error);
13511 [ # # ]: 0 : if (ret)
13512 : : return ret;
13513 : : MLX5_ASSERT(dv_resource_ptr);
13514 : 0 : dev_flow->nt2hws->modify_hdr = dv_resource_ptr;
13515 : : /* keep action for the rule construction. */
13516 : 0 : hw_acts->rule_acts[hw_acts->mhdr->pos].action = dv_resource_ptr->action;
13517 : : /* Bulk size is 1, so index is 1. */
13518 : 0 : dev_flow->res_idx = 1;
13519 : 0 : return 0;
13520 : : }
13521 : :
13522 : : static int
13523 : 0 : flow_hw_encap_decap_resource_register
13524 : : (struct rte_eth_dev *dev,
13525 : : struct rte_flow_template_table *table,
13526 : : struct mlx5_hw_actions *hw_acts,
13527 : : struct rte_flow_hw *dev_flow,
13528 : : struct rte_flow_error *error)
13529 : : {
13530 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
13531 : : bool unified_fdb = is_unified_fdb(priv);
13532 : 0 : struct rte_flow_template_table_attr *table_attr = &table->cfg.attr;
13533 : 0 : struct mlx5_flow_dv_encap_decap_resource *dv_resource_ptr = NULL;
13534 : : struct mlx5_flow_dv_encap_decap_resource dv_resource;
13535 : : struct mlx5_tbl_multi_pattern_ctx *mpctx = &table->mpctx;
13536 : : int ret;
13537 : : bool is_root;
13538 : : int ix;
13539 : :
13540 [ # # ]: 0 : if (hw_acts->encap_decap)
13541 : 0 : dv_resource.reformat_type = hw_acts->encap_decap->action_type;
13542 : : else
13543 : : return 0;
13544 : 0 : flow_hw_set_dv_fields(table_attr, unified_fdb, &is_root, &dv_resource.ft_type,
13545 : : &dv_resource.flags);
13546 [ # # ]: 0 : ix = mlx5_bwc_multi_pattern_reformat_to_index((enum mlx5dr_action_type)
13547 : : dv_resource.reformat_type);
13548 : : if (ix < 0)
13549 : 0 : return ix;
13550 [ # # ]: 0 : if (hw_acts->encap_decap->shared) {
13551 : 0 : dv_resource.size = hw_acts->encap_decap->data_size;
13552 : : MLX5_ASSERT(dv_resource.size <= MLX5_ENCAP_MAX_LEN);
13553 : 0 : memcpy(&dv_resource.buf, hw_acts->encap_decap->data, dv_resource.size);
13554 : 0 : dv_resource.flags |= MLX5DR_ACTION_FLAG_SHARED;
13555 : : } else {
13556 : 0 : typeof(mpctx->reformat[0]) *reformat = mpctx->reformat + ix;
13557 [ # # ]: 0 : if (!reformat->elements_num)
13558 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
13559 : : NULL, "No reformat action exist in the table.");
13560 : 0 : dv_resource.size = reformat->reformat_hdr->sz;
13561 : : MLX5_ASSERT(dv_resource.size <= MLX5_ENCAP_MAX_LEN);
13562 : 0 : memcpy(&dv_resource.buf, reformat->reformat_hdr->data, dv_resource.size);
13563 : : }
13564 : 0 : ret = __flow_encap_decap_resource_register(dev, &dv_resource, is_root,
13565 : : &dv_resource_ptr, error);
13566 [ # # ]: 0 : if (ret)
13567 : : return ret;
13568 : : MLX5_ASSERT(dv_resource_ptr);
13569 : 0 : dev_flow->nt2hws->rix_encap_decap = dv_resource_ptr->idx;
13570 : : /* keep action for the rule construction. */
13571 [ # # ]: 0 : if (hw_acts->encap_decap->shared)
13572 : 0 : hw_acts->rule_acts[hw_acts->encap_decap_pos].action = dv_resource_ptr->action;
13573 : : else
13574 : 0 : mpctx->segments[0].reformat_action[ix] = dv_resource_ptr->action;
13575 : : /* Bulk size is 1, so index is 1. */
13576 : 0 : dev_flow->res_idx = 1;
13577 : 0 : return 0;
13578 : : }
13579 : :
13580 : : static enum rte_flow_action_type
13581 : : flow_nta_get_indirect_action_type(const struct rte_flow_action *action)
13582 : : {
13583 [ # # ]: 0 : switch (MLX5_INDIRECT_ACTION_TYPE_GET(action->conf)) {
13584 : : case MLX5_INDIRECT_ACTION_TYPE_RSS:
13585 : : return RTE_FLOW_ACTION_TYPE_RSS;
13586 : : case MLX5_INDIRECT_ACTION_TYPE_AGE:
13587 : : return RTE_FLOW_ACTION_TYPE_AGE;
13588 : : case MLX5_INDIRECT_ACTION_TYPE_COUNT:
13589 : : return RTE_FLOW_ACTION_TYPE_COUNT;
13590 : : case MLX5_INDIRECT_ACTION_TYPE_CT:
13591 : : return RTE_FLOW_ACTION_TYPE_CONNTRACK;
13592 : : default:
13593 : : break;
13594 : : }
13595 : : return RTE_FLOW_ACTION_TYPE_END;
13596 : : }
13597 : :
13598 : : static void
13599 : : flow_nta_set_mh_mask_conf(const struct rte_flow_action_modify_field *action_conf,
13600 : : struct rte_flow_action_modify_field *mask_conf)
13601 : : {
13602 : : memset(mask_conf, 0xff, sizeof(*mask_conf));
13603 : 0 : mask_conf->operation = action_conf->operation;
13604 : 0 : mask_conf->dst.field = action_conf->dst.field;
13605 : 0 : mask_conf->src.field = action_conf->src.field;
13606 : : }
13607 : :
13608 : : union actions_conf {
13609 : : struct rte_flow_action_modify_field modify_field;
13610 : : struct rte_flow_action_raw_encap raw_encap;
13611 : : struct rte_flow_action_vxlan_encap vxlan_encap;
13612 : : struct rte_flow_action_nvgre_encap nvgre_encap;
13613 : : };
13614 : :
13615 : : static int
13616 : 0 : flow_nta_build_template_mask(const struct rte_flow_action actions[],
13617 : : struct rte_flow_action masks[MLX5_HW_MAX_ACTS],
13618 : : union actions_conf mask_conf[MLX5_HW_MAX_ACTS])
13619 : : {
13620 : : int i;
13621 : :
13622 [ # # # # ]: 0 : for (i = 0; i == 0 || actions[i - 1].type != RTE_FLOW_ACTION_TYPE_END; i++) {
13623 : 0 : const struct rte_flow_action *action = &actions[i];
13624 : 0 : struct rte_flow_action *mask = &masks[i];
13625 : 0 : union actions_conf *conf = &mask_conf[i];
13626 : :
13627 : 0 : mask->type = action->type;
13628 [ # # # # : 0 : switch (action->type) {
# # # ]
13629 : : case RTE_FLOW_ACTION_TYPE_INDIRECT:
13630 : 0 : mask->type = flow_nta_get_indirect_action_type(action);
13631 [ # # ]: 0 : if (!mask->type)
13632 : : return -EINVAL;
13633 : : break;
13634 : 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
13635 : 0 : flow_nta_set_mh_mask_conf(action->conf, (void *)conf);
13636 : 0 : mask->conf = conf;
13637 : 0 : break;
13638 : : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
13639 : : /* This mask will set this action as shared. */
13640 : : memset(conf, 0xff, sizeof(struct rte_flow_action_raw_encap));
13641 : 0 : mask->conf = conf;
13642 : 0 : break;
13643 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
13644 : : /* This mask will set this action as shared. */
13645 : 0 : conf->vxlan_encap.definition =
13646 : : ((const struct rte_flow_action_vxlan_encap *)
13647 : 0 : action->conf)->definition;
13648 : 0 : mask->conf = conf;
13649 : 0 : break;
13650 : 0 : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
13651 : : /* This mask will set this action as shared. */
13652 : 0 : conf->nvgre_encap.definition =
13653 : : ((const struct rte_flow_action_nvgre_encap *)
13654 : 0 : action->conf)->definition;
13655 : 0 : mask->conf = conf;
13656 : 0 : break;
13657 : : case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
13658 : : memset(conf, 0xff, sizeof(struct rte_flow_action_of_set_vlan_vid));
13659 : 0 : mask->conf = conf;
13660 : 0 : break;
13661 : : default:
13662 : : break;
13663 : : }
13664 : : }
13665 : : return 0;
13666 : : #undef NTA_CHECK_CONF_BUF_SIZE
13667 : : }
13668 : :
13669 : : static int
13670 : 0 : flow_hw_translate_flow_actions(struct rte_eth_dev *dev,
13671 : : const struct rte_flow_attr *attr,
13672 : : const struct rte_flow_action actions[],
13673 : : struct rte_flow_hw *flow,
13674 : : struct mlx5_flow_hw_action_params *ap,
13675 : : struct mlx5_hw_actions *hw_acts,
13676 : : uint64_t item_flags, uint64_t action_flags,
13677 : : bool external,
13678 : : struct rte_flow_error *error)
13679 : : {
13680 : : int ret = 0;
13681 : 0 : uint32_t src_group = 0;
13682 : : enum mlx5dr_table_type table_type;
13683 : : struct mlx5_flow_group grp;
13684 : : struct rte_flow_actions_template *at = NULL;
13685 : 0 : struct rte_flow_actions_template_attr template_attr = {
13686 : 0 : .egress = attr->egress,
13687 : 0 : .ingress = attr->ingress,
13688 : 0 : .transfer = attr->transfer,
13689 : : };
13690 : : struct rte_flow_action masks[MLX5_HW_MAX_ACTS];
13691 : : union actions_conf mask_conf[MLX5_HW_MAX_ACTS];
13692 : :
13693 : : RTE_SET_USED(action_flags);
13694 : : memset(masks, 0, sizeof(masks));
13695 : : memset(mask_conf, 0, sizeof(mask_conf));
13696 : : /* Only set the needed fields explicitly. */
13697 : 0 : struct mlx5_flow_workspace *wks = mlx5_flow_push_thread_workspace();
13698 : : struct rte_flow_template_table *table;
13699 : :
13700 : : /*
13701 : : * Notice All direct actions will be unmasked,
13702 : : * except for modify header and encap,
13703 : : * and therefore will be parsed as part of action construct.
13704 : : * Modify header is always shared in HWS,
13705 : : * encap is masked such that it will be treated as shared.
13706 : : * shared actions will be parsed as part of template translation
13707 : : * and not during action construct.
13708 : : */
13709 [ # # ]: 0 : if (!wks)
13710 : 0 : return rte_flow_error_set(error, ENOMEM,
13711 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13712 : : NULL,
13713 : : "failed to push flow workspace");
13714 : 0 : table = wks->table;
13715 : 0 : flow_nta_build_template_mask(actions, masks, mask_conf);
13716 : : /* The group in the attribute translation was done in advance. */
13717 : 0 : ret = __translate_group(dev, attr, external, attr->group, &src_group, error);
13718 [ # # ]: 0 : if (ret)
13719 : : return ret;
13720 [ # # ]: 0 : if (attr->transfer)
13721 : : table_type = MLX5DR_TABLE_TYPE_FDB;
13722 [ # # ]: 0 : else if (attr->egress)
13723 : : table_type = MLX5DR_TABLE_TYPE_NIC_TX;
13724 : : else
13725 : : table_type = MLX5DR_TABLE_TYPE_NIC_RX;
13726 : 0 : at = __flow_hw_actions_template_create(dev, &template_attr, actions, masks, true, error);
13727 [ # # ]: 0 : if (!at) {
13728 : 0 : ret = -rte_errno;
13729 : 0 : goto end;
13730 : : }
13731 : 0 : grp.group_id = src_group;
13732 : 0 : table->grp = &grp;
13733 : 0 : table->type = table_type;
13734 : 0 : table->cfg.external = external;
13735 : 0 : table->nb_action_templates = 1;
13736 : 0 : memcpy(&table->cfg.attr.flow_attr, attr, sizeof(*attr));
13737 : 0 : table->cfg.attr.flow_attr.group = src_group;
13738 : 0 : table->ats[0].action_template = at;
13739 : 0 : ret = __flow_hw_translate_actions_template(dev, &table->cfg, hw_acts, at,
13740 : : &table->mpctx, true, error);
13741 [ # # ]: 0 : if (ret)
13742 : 0 : goto end;
13743 : : /* handle bulk actions register. */
13744 : 0 : ret = flow_hw_encap_decap_resource_register(dev, table, hw_acts, flow, error);
13745 [ # # ]: 0 : if (ret)
13746 : 0 : goto end;
13747 : 0 : ret = flow_hw_modify_hdr_resource_register(dev, table, hw_acts, flow, error);
13748 [ # # ]: 0 : if (ret)
13749 : 0 : goto end;
13750 : 0 : table->ats[0].acts = *hw_acts;
13751 : 0 : ret = flow_hw_actions_construct(dev, flow, ap,
13752 : : &table->ats[0], item_flags, table,
13753 [ # # ]: 0 : actions, hw_acts->rule_acts, 0, error);
13754 [ # # ]: 0 : if (ret)
13755 : 0 : goto end;
13756 : 0 : goto end;
13757 : 0 : end:
13758 [ # # ]: 0 : if (ret)
13759 : : /* Make sure that there is no garbage in the actions. */
13760 : 0 : __flow_hw_action_template_destroy(dev, hw_acts);
13761 : : else
13762 : 0 : __flow_hw_act_data_flush(dev, hw_acts);
13763 [ # # ]: 0 : if (at)
13764 : 0 : mlx5_free(at);
13765 : 0 : mlx5_flow_pop_thread_workspace();
13766 : 0 : return ret;
13767 : : }
13768 : :
13769 : : static int
13770 : 0 : flow_hw_unregister_matcher(struct rte_eth_dev *dev,
13771 : : struct mlx5_flow_dv_matcher *matcher)
13772 : : {
13773 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13774 : 0 : struct mlx5_flow_group *group = matcher->group;
13775 : : int ret = 0;
13776 : :
13777 [ # # ]: 0 : if (group) {
13778 [ # # ]: 0 : if (matcher->matcher_object)
13779 : 0 : ret |= mlx5_list_unregister(group->matchers, &matcher->entry);
13780 : 0 : ret |= mlx5_hlist_unregister(priv->sh->groups, &group->entry);
13781 : : }
13782 : 0 : return ret;
13783 : : }
13784 : :
13785 : 0 : static int flow_hw_register_matcher(struct rte_eth_dev *dev,
13786 : : const struct rte_flow_attr *attr,
13787 : : const struct rte_flow_item items[],
13788 : : bool external,
13789 : : struct rte_flow_hw *flow,
13790 : : struct mlx5_flow_dv_matcher *matcher,
13791 : : struct rte_flow_error *error)
13792 : : {
13793 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13794 : 0 : struct rte_flow_error sub_error = {
13795 : : .type = RTE_FLOW_ERROR_TYPE_NONE,
13796 : : .cause = NULL,
13797 : : .message = NULL,
13798 : : };
13799 : 0 : struct rte_flow_attr flow_attr = *attr;
13800 : 0 : uint32_t specialize = 0; /* No unified FDB. */
13801 : 0 : struct mlx5_flow_cb_ctx ctx = {
13802 : : .dev = dev,
13803 : : .error = &sub_error,
13804 : : .data = &flow_attr,
13805 : : .data2 = &specialize,
13806 : : };
13807 : : void *items_ptr = &items;
13808 : 0 : struct mlx5_flow_cb_ctx matcher_ctx = {
13809 : : .error = &sub_error,
13810 : : .data = matcher,
13811 : : .data2 = items_ptr,
13812 : : };
13813 : : struct mlx5_list_entry *group_entry = NULL;
13814 : : struct mlx5_list_entry *matcher_entry = NULL;
13815 : : struct mlx5_flow_dv_matcher *resource;
13816 : : struct mlx5_list *matchers_list;
13817 : : struct mlx5_flow_group *flow_group;
13818 : : int ret;
13819 : :
13820 : :
13821 : 0 : matcher->crc = rte_raw_cksum((const void *)matcher->mask.buf,
13822 : : matcher->mask.size);
13823 : 0 : matcher->priority = attr->priority;
13824 : 0 : ret = __translate_group(dev, attr, external, attr->group, &flow_attr.group, error);
13825 [ # # ]: 0 : if (ret)
13826 : : return ret;
13827 : :
13828 : : /* Register the flow group. */
13829 : 0 : group_entry = mlx5_hlist_register(priv->sh->groups, flow_attr.group, &ctx);
13830 [ # # ]: 0 : if (!group_entry)
13831 : 0 : goto error;
13832 : : flow_group = container_of(group_entry, struct mlx5_flow_group, entry);
13833 : :
13834 : 0 : matchers_list = flow_group->matchers;
13835 : 0 : matcher->group = flow_group;
13836 : 0 : matcher_entry = mlx5_list_register(matchers_list, &matcher_ctx);
13837 [ # # ]: 0 : if (!matcher_entry)
13838 : 0 : goto error;
13839 : : resource = container_of(matcher_entry, typeof(*resource), entry);
13840 : 0 : flow->nt2hws->matcher = resource;
13841 : 0 : return 0;
13842 : :
13843 : 0 : error:
13844 [ # # ]: 0 : if (group_entry)
13845 : 0 : mlx5_hlist_unregister(priv->sh->groups, group_entry);
13846 [ # # ]: 0 : if (error) {
13847 [ # # ]: 0 : if (sub_error.type != RTE_FLOW_ERROR_TYPE_NONE)
13848 : : rte_memcpy(error, &sub_error, sizeof(sub_error));
13849 : : }
13850 : 0 : return rte_flow_error_set(error, rte_errno,
13851 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13852 : : NULL, "fail to register matcher");
13853 : : }
13854 : :
13855 : : static int
13856 : 0 : flow_hw_allocate_actions(struct rte_eth_dev *dev,
13857 : : uint64_t action_flags,
13858 : : struct rte_flow_error *error)
13859 : : {
13860 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13861 : : int ret;
13862 : : uint obj_num;
13863 : :
13864 : 0 : error->type = RTE_FLOW_ERROR_TYPE_NONE;
13865 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_AGE) {
13866 : : /* If no age objects were previously allocated. */
13867 [ # # ]: 0 : if (!priv->hws_age_req) {
13868 : : /* If no counters were previously allocated. */
13869 [ # # ]: 0 : if (!priv->hws_cpool) {
13870 : 0 : obj_num = MLX5_CNT_NT_MAX(priv);
13871 : 0 : ret = mlx5_hws_cnt_pool_create(dev, obj_num,
13872 : 0 : priv->nb_queue,
13873 : : NULL, error);
13874 [ # # ]: 0 : if (ret)
13875 : 0 : goto err;
13876 : : }
13877 : : /* Allocate same number of counters. */
13878 : 0 : ret = mlx5_hws_age_pool_init(dev, priv->hws_cpool->cfg.request_num,
13879 : 0 : priv->nb_queue, false);
13880 [ # # ]: 0 : if (ret)
13881 : 0 : goto err;
13882 : : }
13883 : : }
13884 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_COUNT) {
13885 : : /* If no counters were previously allocated. */
13886 [ # # ]: 0 : if (!priv->hws_cpool) {
13887 : 0 : obj_num = MLX5_CNT_NT_MAX(priv);
13888 : 0 : ret = mlx5_hws_cnt_pool_create(dev, obj_num,
13889 : 0 : priv->nb_queue, NULL,
13890 : : error);
13891 [ # # ]: 0 : if (ret)
13892 : 0 : goto err;
13893 : : }
13894 : : }
13895 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_CT) {
13896 : : /* If no CT were previously allocated. */
13897 [ # # ]: 0 : if (!priv->hws_ctpool) {
13898 : 0 : obj_num = MLX5_CT_NT_MAX(priv);
13899 : 0 : ret = mlx5_flow_ct_init(dev, obj_num, priv->nb_queue);
13900 [ # # ]: 0 : if (ret)
13901 : 0 : goto err;
13902 : : }
13903 : : }
13904 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_METER) {
13905 : : /* If no meters were previously allocated. */
13906 [ # # ]: 0 : if (!priv->hws_mpool) {
13907 : 0 : obj_num = MLX5_MTR_NT_MAX(priv);
13908 : 0 : ret = mlx5_flow_meter_init(dev, obj_num, 0, 0,
13909 : : priv->nb_queue);
13910 [ # # ]: 0 : if (ret)
13911 : 0 : goto err;
13912 : : }
13913 : : }
13914 : : return 0;
13915 : 0 : err:
13916 [ # # ]: 0 : if (ret && error->type != RTE_FLOW_ERROR_TYPE_NONE)
13917 : : return ret;
13918 : 0 : return rte_flow_error_set(error, ret,
13919 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13920 : : NULL, "fail to allocate actions");
13921 : : }
13922 : :
13923 : 0 : static int flow_hw_apply(const struct rte_flow_item items[],
13924 : : struct mlx5dr_rule_action rule_actions[],
13925 : : struct rte_flow_hw *flow,
13926 : : struct rte_flow_error *error)
13927 : : {
13928 : : struct mlx5dr_bwc_rule *rule = NULL;
13929 : :
13930 : 0 : rule = mlx5dr_bwc_rule_create((struct mlx5dr_bwc_matcher *)
13931 : 0 : flow->nt2hws->matcher->matcher_object,
13932 : : items, rule_actions);
13933 : 0 : flow->nt2hws->nt_rule = rule;
13934 [ # # ]: 0 : if (!rule) {
13935 : 0 : return rte_flow_error_set(error, EINVAL,
13936 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13937 : : NULL, "fail to create rte flow");
13938 : : }
13939 : : return 0;
13940 : : }
13941 : :
13942 : : #ifdef HAVE_MLX5_HWS_SUPPORT
13943 : : /**
13944 : : * Create a flow.
13945 : : *
13946 : : * @param[in] dev
13947 : : * Pointer to Ethernet device.
13948 : : * @param[in] type
13949 : : * Flow type.
13950 : : * @param[in] attr
13951 : : * Flow rule attributes.
13952 : : * @param[in] items
13953 : : * Pattern specification (list terminated by the END pattern item).
13954 : : * @param[in] actions
13955 : : * Associated actions (list terminated by the END action).
13956 : : * @param[in] external
13957 : : * This flow rule is created by request external to PMD.
13958 : : * @param[out] flow
13959 : : * Flow pointer
13960 : : * @param[out] error
13961 : : * Perform verbose error reporting if not NULL.
13962 : : *
13963 : : * @return
13964 : : * 0 on success, negative errno value otherwise and rte_errno set.
13965 : : */
13966 : : int
13967 : 0 : flow_hw_create_flow(struct rte_eth_dev *dev, enum mlx5_flow_type type,
13968 : : const struct rte_flow_attr *attr,
13969 : : const struct rte_flow_item items[],
13970 : : const struct rte_flow_action actions[],
13971 : : uint64_t item_flags, uint64_t action_flags, bool external,
13972 : : struct rte_flow_hw **flow, struct rte_flow_error *error)
13973 : : {
13974 : : int ret;
13975 : 0 : struct mlx5_hw_actions hw_act = { { NULL } };
13976 : : struct mlx5_flow_hw_action_params ap;
13977 : 0 : struct mlx5_flow_dv_matcher matcher = {
13978 : : .mask = {
13979 : : .size = sizeof(matcher.mask.buf),
13980 : : },
13981 : : };
13982 : : uint32_t tbl_type;
13983 : :
13984 : 0 : struct mlx5_flow_attr flow_attr = {
13985 : 0 : .port_id = dev->data->port_id,
13986 : 0 : .group = attr->group,
13987 : 0 : .priority = attr->priority,
13988 : : .rss_level = 0,
13989 : : .act_flags = action_flags,
13990 : : .tbl_type = 0,
13991 : : };
13992 : :
13993 [ # # ]: 0 : if (attr->transfer)
13994 : : tbl_type = MLX5DR_TABLE_TYPE_FDB;
13995 [ # # ]: 0 : else if (attr->egress)
13996 : : tbl_type = MLX5DR_TABLE_TYPE_NIC_TX;
13997 : : else
13998 : : tbl_type = MLX5DR_TABLE_TYPE_NIC_RX;
13999 : 0 : flow_attr.tbl_type = tbl_type;
14000 : :
14001 : : /* Allocate needed memory. */
14002 : 0 : ret = flow_hw_prepare(dev, actions, type, flow, error);
14003 [ # # ]: 0 : if (ret)
14004 : 0 : goto error;
14005 : :
14006 : : /* TODO TBD flow_hw_handle_tunnel_offload(). */
14007 : 0 : (*flow)->nt_rule = true;
14008 : 0 : (*flow)->nt2hws->matcher = &matcher;
14009 : 0 : ret = __flow_dv_translate_items_hws(items, &flow_attr, &matcher.mask.buf,
14010 : : MLX5_SET_MATCHER_HS_M, NULL,
14011 : : NULL, true, error);
14012 : :
14013 [ # # ]: 0 : if (ret)
14014 : 0 : goto error;
14015 : :
14016 [ # # # # ]: 0 : if (item_flags & MLX5_FLOW_LAYER_ECPRI && !mlx5_flex_parser_ecpri_exist(dev))
14017 [ # # ]: 0 : if (mlx5_flex_parser_ecpri_alloc(dev)) {
14018 : 0 : rte_flow_error_set(error, EIO,
14019 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14020 : : NULL,
14021 : : "failed to create Flex parser "
14022 : : "profile for ECPRI");
14023 : 0 : goto error;
14024 : : }
14025 : 0 : ret = flow_hw_register_matcher(dev, attr, items, external, *flow, &matcher, error);
14026 [ # # ]: 0 : if (ret) {
14027 [ # # ]: 0 : if (rte_errno == E2BIG)
14028 : 0 : rte_flow_error_set(error, E2BIG, RTE_FLOW_ERROR_TYPE_ITEM, NULL,
14029 : : "flow pattern is too big");
14030 : 0 : goto error;
14031 : : }
14032 : :
14033 : : /*
14034 : : * ASO allocation – iterating on actions list to allocate missing resources.
14035 : : * In the future when validate function in hws will be added,
14036 : : * The output actions bit mask instead of
14037 : : * looping on the actions array twice.
14038 : : */
14039 : 0 : ret = flow_hw_allocate_actions(dev, action_flags, error);
14040 [ # # ]: 0 : if (ret)
14041 : 0 : goto error;
14042 : :
14043 : : /* Note: the actions should be saved in the sub-flow rule itself for reference. */
14044 : 0 : ret = flow_hw_translate_flow_actions(dev, attr, actions, *flow, &ap, &hw_act,
14045 : : item_flags, action_flags, external, error);
14046 [ # # ]: 0 : if (ret)
14047 : 0 : goto error;
14048 : :
14049 : : /*
14050 : : * If the flow is external (from application) OR device is started,
14051 : : * OR mreg discover, then apply immediately.
14052 : : */
14053 [ # # # # ]: 0 : if (external || dev->data->dev_started ||
14054 [ # # ]: 0 : (attr->group == MLX5_FLOW_MREG_CP_TABLE_GROUP &&
14055 [ # # ]: 0 : attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR)) {
14056 : 0 : ret = flow_hw_apply(items, hw_act.rule_acts, *flow, error);
14057 [ # # ]: 0 : if (ret)
14058 : 0 : goto error;
14059 : : }
14060 : : ret = 0;
14061 : 0 : error:
14062 : : /*
14063 : : * Release memory allocated.
14064 : : * Cannot use __flow_hw_actions_release(dev, &hw_act);
14065 : : * since it destroys the actions as well.
14066 : : */
14067 [ # # ]: 0 : if (hw_act.encap_decap)
14068 : 0 : mlx5_free(hw_act.encap_decap);
14069 [ # # ]: 0 : if (hw_act.push_remove)
14070 : 0 : mlx5_free(hw_act.push_remove);
14071 [ # # ]: 0 : if (hw_act.mhdr)
14072 : 0 : mlx5_free(hw_act.mhdr);
14073 [ # # ]: 0 : if (ret) {
14074 : : /* release after actual error */
14075 [ # # # # ]: 0 : if ((*flow)->nt2hws && (*flow)->nt2hws->matcher)
14076 : 0 : flow_hw_unregister_matcher(dev, (*flow)->nt2hws->matcher);
14077 : : }
14078 : 0 : return ret;
14079 : : }
14080 : : #endif
14081 : :
14082 : : void
14083 : 0 : flow_hw_destroy(struct rte_eth_dev *dev, struct rte_flow_hw *flow)
14084 : : {
14085 : : int ret;
14086 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14087 : :
14088 [ # # # # ]: 0 : if (!flow || !flow->nt2hws)
14089 : : return;
14090 : :
14091 [ # # ]: 0 : if (flow->nt2hws->nt_rule) {
14092 : 0 : ret = mlx5dr_bwc_rule_destroy(flow->nt2hws->nt_rule);
14093 [ # # ]: 0 : if (ret)
14094 : 0 : DRV_LOG(ERR, "bwc rule destroy failed");
14095 : : }
14096 [ # # ]: 0 : flow->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_DESTROY;
14097 : : /* Notice this function does not handle shared/static actions. */
14098 : : hw_cmpl_flow_update_or_destroy(dev, flow, 0, NULL);
14099 : :
14100 : : /**
14101 : : * TODO: TBD - Release tunnel related memory allocations(mlx5_flow_tunnel_free)
14102 : : * – needed only if supporting tunnel offloads, notice update RX queue flags in SWS.
14103 : : */
14104 : :
14105 : : /**
14106 : : * Notice matcher destroy will take place when matcher's list is destroyed
14107 : : * , same as for DV.
14108 : : */
14109 [ # # ]: 0 : if (flow->nt2hws->flow_aux)
14110 : 0 : mlx5_free(flow->nt2hws->flow_aux);
14111 : :
14112 [ # # ]: 0 : if (flow->nt2hws->rix_encap_decap)
14113 : 0 : flow_encap_decap_resource_release(dev, flow->nt2hws->rix_encap_decap);
14114 [ # # ]: 0 : if (flow->nt2hws->modify_hdr) {
14115 : : MLX5_ASSERT(flow->nt2hws->modify_hdr->action);
14116 : 0 : mlx5_hlist_unregister(priv->sh->modify_cmds,
14117 : : &flow->nt2hws->modify_hdr->entry);
14118 : : }
14119 [ # # ]: 0 : if (flow->nt2hws->matcher)
14120 : 0 : flow_hw_unregister_matcher(dev, flow->nt2hws->matcher);
14121 : : }
14122 : :
14123 : : #ifdef HAVE_MLX5_HWS_SUPPORT
14124 : : /**
14125 : : * Destroy a flow.
14126 : : *
14127 : : * @param[in] dev
14128 : : * Pointer to Ethernet device.
14129 : : * @param[in] type
14130 : : * Flow type.
14131 : : * @param[in] flow_addr
14132 : : * Address of flow to destroy.
14133 : : */
14134 : : void
14135 : 0 : flow_hw_list_destroy(struct rte_eth_dev *dev, enum mlx5_flow_type type,
14136 : : uintptr_t flow_addr)
14137 : : {
14138 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14139 : 0 : struct rte_flow_hw *flow = (struct rte_flow_hw *)flow_addr;
14140 : : struct mlx5_nta_rss_flow_head head = { .slh_first = flow };
14141 : :
14142 [ # # # # : 0 : if (!flow || !flow->nt2hws || flow->nt2hws->chaned_flow)
# # ]
14143 : : return;
14144 : 0 : mlx5_flow_nta_del_copy_action(dev, flow->nt2hws->rix_mreg_copy);
14145 [ # # ]: 0 : while (!SLIST_EMPTY(&head)) {
14146 : : flow = SLIST_FIRST(&head);
14147 : 0 : SLIST_REMOVE_HEAD(&head, nt2hws->next);
14148 : 0 : flow_hw_destroy(dev, flow);
14149 : : /* Release flow memory by idx */
14150 : 0 : mlx5_ipool_free(priv->flows[type], flow->idx);
14151 : : }
14152 : : }
14153 : : #endif
14154 : :
14155 : : /**
14156 : : * Create a flow.
14157 : : *
14158 : : * @param[in] dev
14159 : : * Pointer to Ethernet device.
14160 : : * @param[in] type
14161 : : * Flow type.
14162 : : * @param[in] attr
14163 : : * Flow rule attributes.
14164 : : * @param[in] items
14165 : : * Pattern specification (list terminated by the END pattern item).
14166 : : * @param[in] actions
14167 : : * Associated actions (list terminated by the END action).
14168 : : * @param[in] external
14169 : : * This flow rule is created by request external to PMD.
14170 : : * @param[out] error
14171 : : * Perform verbose error reporting if not NULL.
14172 : : *
14173 : : * @return
14174 : : * A flow addr on success, 0 otherwise and rte_errno is set.
14175 : : */
14176 : 0 : static uintptr_t flow_hw_list_create(struct rte_eth_dev *dev,
14177 : : enum mlx5_flow_type type,
14178 : : const struct rte_flow_attr *attr,
14179 : : const struct rte_flow_item items[],
14180 : : const struct rte_flow_action actions[],
14181 : : bool external,
14182 : : struct rte_flow_error *error)
14183 : : {
14184 : : int ret;
14185 : : int split;
14186 : : int encap_idx;
14187 : 0 : uint32_t cpy_idx = 0;
14188 : 0 : int actions_n = 0;
14189 : 0 : struct rte_flow_hw *flow = NULL;
14190 : 0 : struct rte_flow_hw *prfx_flow = NULL;
14191 : 0 : const struct rte_flow_action *qrss = NULL;
14192 : 0 : const struct rte_flow_action *mark = NULL;
14193 : 0 : uint64_t item_flags = 0;
14194 : 0 : uint64_t action_flags = flow_hw_action_flags_get(actions, &qrss, &mark,
14195 : : &encap_idx, &actions_n, error);
14196 : 0 : struct mlx5_flow_hw_split_resource resource = {
14197 : : .suffix = {
14198 : : .attr = attr,
14199 : : .items = items,
14200 : : .actions = actions,
14201 : : },
14202 : : };
14203 : 0 : struct rte_flow_error shadow_error = {0, };
14204 : 0 : const struct rte_flow_pattern_template_attr pattern_template_attr = {
14205 : : .relaxed_matching = 0,
14206 : 0 : .ingress = attr->ingress,
14207 : 0 : .egress = attr->egress,
14208 : 0 : .transfer = attr->transfer,
14209 : : };
14210 : :
14211 : : /* Validate application items only */
14212 : 0 : ret = __flow_hw_pattern_validate(dev, &pattern_template_attr, items,
14213 : : &item_flags, true, error);
14214 [ # # ]: 0 : if (ret < 0)
14215 : : return 0;
14216 : :
14217 : : RTE_SET_USED(encap_idx);
14218 [ # # ]: 0 : if (!error)
14219 : : error = &shadow_error;
14220 : 0 : split = mlx5_flow_nta_split_metadata(dev, attr, actions, qrss, action_flags,
14221 : : actions_n, external, &resource, error);
14222 [ # # ]: 0 : if (split < 0)
14223 : 0 : return split;
14224 : :
14225 : : /* Update the metadata copy table - MLX5_FLOW_MREG_CP_TABLE_GROUP */
14226 [ # # # # : 0 : if (((attr->ingress && attr->group != MLX5_FLOW_MREG_CP_TABLE_GROUP) ||
# # ]
14227 [ # # ]: 0 : attr->transfer) && external) {
14228 : 0 : ret = mlx5_flow_nta_update_copy_table(dev, &cpy_idx, mark,
14229 : : action_flags, error);
14230 [ # # ]: 0 : if (ret)
14231 : 0 : goto free;
14232 : : }
14233 : :
14234 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_RSS) {
14235 : : const struct rte_flow_action_rss
14236 : 0 : *rss_conf = flow_nta_locate_rss(dev, actions, error);
14237 : 0 : flow = flow_nta_handle_rss(dev, attr, items, actions, rss_conf,
14238 : : item_flags, action_flags, external,
14239 : : type, error);
14240 [ # # ]: 0 : if (flow) {
14241 : 0 : flow->nt2hws->rix_mreg_copy = cpy_idx;
14242 : 0 : cpy_idx = 0;
14243 [ # # ]: 0 : if (!split)
14244 : 0 : return (uintptr_t)flow;
14245 : 0 : goto prefix_flow;
14246 : : }
14247 : 0 : goto free;
14248 : : }
14249 : : /* Create single flow. */
14250 : 0 : ret = flow_hw_create_flow(dev, type, resource.suffix.attr, resource.suffix.items,
14251 : : resource.suffix.actions, item_flags, action_flags,
14252 : : external, &flow, error);
14253 [ # # ]: 0 : if (ret)
14254 : 0 : goto free;
14255 [ # # ]: 0 : if (flow) {
14256 : 0 : flow->nt2hws->rix_mreg_copy = cpy_idx;
14257 : 0 : cpy_idx = 0;
14258 [ # # ]: 0 : if (!split)
14259 : 0 : return (uintptr_t)flow;
14260 : : /* Fall Through to prefix flow creation. */
14261 : : }
14262 : 0 : prefix_flow:
14263 : 0 : ret = flow_hw_create_flow(dev, type, attr, items, resource.prefix.actions,
14264 : : item_flags, action_flags, external, &prfx_flow, error);
14265 [ # # ]: 0 : if (ret)
14266 : 0 : goto free;
14267 [ # # ]: 0 : if (prfx_flow) {
14268 : 0 : prfx_flow->nt2hws->rix_mreg_copy = flow->nt2hws->rix_mreg_copy;
14269 : 0 : flow->nt2hws->chaned_flow = 1;
14270 : 0 : SLIST_INSERT_AFTER(prfx_flow, flow, nt2hws->next);
14271 : 0 : mlx5_flow_nta_split_resource_free(dev, &resource);
14272 : 0 : return (uintptr_t)prfx_flow;
14273 : : }
14274 : 0 : free:
14275 [ # # ]: 0 : if (prfx_flow)
14276 : 0 : flow_hw_list_destroy(dev, type, (uintptr_t)prfx_flow);
14277 [ # # ]: 0 : if (flow)
14278 : 0 : flow_hw_list_destroy(dev, type, (uintptr_t)flow);
14279 [ # # ]: 0 : if (cpy_idx)
14280 : 0 : mlx5_flow_nta_del_copy_action(dev, cpy_idx);
14281 [ # # ]: 0 : if (split > 0)
14282 : 0 : mlx5_flow_nta_split_resource_free(dev, &resource);
14283 : : return 0;
14284 : : }
14285 : :
14286 : : static void
14287 : 0 : mlx5_mirror_destroy_clone(struct rte_eth_dev *dev,
14288 : : struct mlx5_mirror_clone *clone)
14289 : : {
14290 [ # # # ]: 0 : switch (clone->type) {
14291 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
14292 : : case RTE_FLOW_ACTION_TYPE_QUEUE:
14293 : 0 : mlx5_hrxq_release(dev,
14294 : 0 : ((struct mlx5_hrxq *)(clone->action_ctx))->idx);
14295 : 0 : break;
14296 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP:
14297 : 0 : flow_hw_jump_release(dev, clone->action_ctx);
14298 : : break;
14299 : : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
14300 : : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
14301 : : case RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:
14302 : : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
14303 : : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
14304 : : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
14305 : : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
14306 : : default:
14307 : : break;
14308 : : }
14309 : 0 : }
14310 : :
14311 : : void
14312 [ # # ]: 0 : mlx5_hw_mirror_destroy(struct rte_eth_dev *dev, struct mlx5_mirror *mirror)
14313 : : {
14314 : : uint32_t i;
14315 : :
14316 : : mlx5_indirect_list_remove_entry(&mirror->indirect);
14317 [ # # ]: 0 : for (i = 0; i < mirror->clones_num; i++)
14318 : 0 : mlx5_mirror_destroy_clone(dev, &mirror->clone[i]);
14319 [ # # ]: 0 : if (mirror->mirror_action)
14320 : 0 : mlx5dr_action_destroy(mirror->mirror_action);
14321 : 0 : mlx5_free(mirror);
14322 : 0 : }
14323 : :
14324 : : static __rte_always_inline bool
14325 : : mlx5_mirror_terminal_action(const struct rte_flow_action *action)
14326 : : {
14327 : 0 : switch (action->type) {
14328 : : case RTE_FLOW_ACTION_TYPE_JUMP:
14329 : : case RTE_FLOW_ACTION_TYPE_RSS:
14330 : : case RTE_FLOW_ACTION_TYPE_QUEUE:
14331 : : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
14332 : : case RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:
14333 : : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
14334 : : case RTE_FLOW_ACTION_TYPE_DROP:
14335 : : return true;
14336 : : default:
14337 : : break;
14338 : : }
14339 : : return false;
14340 : : }
14341 : :
14342 : : static bool
14343 : 0 : mlx5_mirror_validate_sample_action(struct rte_eth_dev *dev,
14344 : : const struct rte_flow_attr *flow_attr,
14345 : : const struct rte_flow_action *action)
14346 : : {
14347 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14348 : : const struct rte_flow_action_ethdev *port = NULL;
14349 [ # # # # ]: 0 : bool is_proxy = MLX5_HW_PORT_IS_PROXY(priv);
14350 : :
14351 [ # # ]: 0 : if (!action)
14352 : : return false;
14353 [ # # # # : 0 : switch (action->type) {
# ]
14354 : 0 : case RTE_FLOW_ACTION_TYPE_QUEUE:
14355 : : case RTE_FLOW_ACTION_TYPE_RSS:
14356 [ # # ]: 0 : if (flow_attr->transfer)
14357 : : return false;
14358 : : break;
14359 : 0 : case RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:
14360 [ # # # # ]: 0 : if (!is_proxy || !flow_attr->transfer)
14361 : : return false;
14362 : 0 : port = action->conf;
14363 [ # # # # ]: 0 : if (!port || port->port_id != MLX5_REPRESENTED_PORT_ESW_MGR)
14364 : : return false;
14365 : : break;
14366 : 0 : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
14367 : : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
14368 : : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
14369 : : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
14370 : : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
14371 [ # # # # ]: 0 : if (!is_proxy || !flow_attr->transfer)
14372 : : return false;
14373 [ # # ]: 0 : if (action[0].type == RTE_FLOW_ACTION_TYPE_RAW_DECAP &&
14374 [ # # ]: 0 : action[1].type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP)
14375 : : return false;
14376 : : break;
14377 : : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
14378 : : case RTE_FLOW_ACTION_TYPE_JUMP:
14379 : : case RTE_FLOW_ACTION_TYPE_DROP:
14380 : : break;
14381 : : default:
14382 : : return false;
14383 : : }
14384 : 0 : return true;
14385 : : }
14386 : :
14387 : : /**
14388 : : * Valid mirror actions list includes one or two SAMPLE actions
14389 : : * followed by JUMP.
14390 : : *
14391 : : * @return
14392 : : * Number of mirrors *action* list was valid.
14393 : : * -EINVAL otherwise.
14394 : : */
14395 : : static int
14396 : 0 : mlx5_hw_mirror_actions_list_validate(struct rte_eth_dev *dev,
14397 : : const struct rte_flow_attr *flow_attr,
14398 : : const struct rte_flow_action *actions)
14399 : : {
14400 [ # # ]: 0 : if (actions[0].type == RTE_FLOW_ACTION_TYPE_SAMPLE) {
14401 : : int i = 1;
14402 : : bool valid;
14403 : 0 : const struct rte_flow_action_sample *sample = actions[0].conf;
14404 : 0 : valid = mlx5_mirror_validate_sample_action(dev, flow_attr,
14405 : 0 : sample->actions);
14406 [ # # ]: 0 : if (!valid)
14407 : : return -EINVAL;
14408 [ # # ]: 0 : if (actions[1].type == RTE_FLOW_ACTION_TYPE_SAMPLE) {
14409 : : i = 2;
14410 : 0 : sample = actions[1].conf;
14411 : 0 : valid = mlx5_mirror_validate_sample_action(dev, flow_attr,
14412 : 0 : sample->actions);
14413 [ # # ]: 0 : if (!valid)
14414 : : return -EINVAL;
14415 : : }
14416 [ # # ]: 0 : return mlx5_mirror_terminal_action(actions + i) ? i + 1 : -EINVAL;
14417 : : }
14418 : : return -EINVAL;
14419 : : }
14420 : :
14421 : : static int
14422 : 0 : mirror_format_tir(struct rte_eth_dev *dev,
14423 : : struct mlx5_mirror_clone *clone,
14424 : : const struct mlx5_flow_template_table_cfg *table_cfg,
14425 : : const struct rte_flow_action *action,
14426 : : struct mlx5dr_action_dest_attr *dest_attr,
14427 : : struct rte_flow_error *error)
14428 : : {
14429 : : uint32_t hws_flags;
14430 : : enum mlx5dr_table_type table_type;
14431 : : struct mlx5_hrxq *tir_ctx;
14432 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14433 : : bool unified_fdb = is_unified_fdb(priv);
14434 : :
14435 : 0 : table_type = get_mlx5dr_table_type(&table_cfg->attr.flow_attr, table_cfg->attr.specialize,
14436 : : unified_fdb);
14437 : 0 : hws_flags = mlx5_hw_act_flag[MLX5_HW_ACTION_FLAG_NONE_ROOT][table_type];
14438 : 0 : tir_ctx = flow_hw_tir_action_register(dev, hws_flags, action);
14439 [ # # ]: 0 : if (!tir_ctx)
14440 : 0 : return rte_flow_error_set(error, EINVAL,
14441 : : RTE_FLOW_ERROR_TYPE_ACTION,
14442 : : action, "failed to create QUEUE action for mirror clone");
14443 : 0 : dest_attr->dest = tir_ctx->action;
14444 : 0 : clone->action_ctx = tir_ctx;
14445 : 0 : return 0;
14446 : : }
14447 : :
14448 : : static int
14449 : 0 : mirror_format_jump(struct rte_eth_dev *dev,
14450 : : struct mlx5_mirror_clone *clone,
14451 : : const struct mlx5_flow_template_table_cfg *table_cfg,
14452 : : const struct rte_flow_action *action,
14453 : : struct mlx5dr_action_dest_attr *dest_attr,
14454 : : struct rte_flow_error *error)
14455 : : {
14456 : 0 : const struct rte_flow_action_jump *jump_conf = action->conf;
14457 : 0 : struct mlx5_hw_jump_action *jump = flow_hw_jump_action_register
14458 : : (dev, table_cfg,
14459 : 0 : jump_conf->group, error);
14460 : :
14461 [ # # ]: 0 : if (!jump)
14462 : 0 : return rte_flow_error_set(error, EINVAL,
14463 : : RTE_FLOW_ERROR_TYPE_ACTION,
14464 : : action, "failed to create JUMP action for mirror clone");
14465 : 0 : dest_attr->dest = jump->hws_action;
14466 : 0 : clone->action_ctx = jump;
14467 : 0 : return 0;
14468 : : }
14469 : :
14470 : : static int
14471 : : mirror_format_port(struct rte_eth_dev *dev,
14472 : : const struct rte_flow_action *action,
14473 : : struct mlx5dr_action_dest_attr *dest_attr,
14474 : : struct rte_flow_error __rte_unused *error)
14475 : : {
14476 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14477 : 0 : const struct rte_flow_action_ethdev *port_action = action->conf;
14478 : :
14479 : 0 : dest_attr->dest = priv->hw_vport[port_action->port_id];
14480 : : return 0;
14481 : : }
14482 : :
14483 : : static int
14484 : 0 : hw_mirror_clone_reformat(const struct rte_flow_action *actions,
14485 : : struct mlx5dr_action_dest_attr *dest_attr,
14486 : : enum mlx5dr_action_type *action_type,
14487 : : uint8_t *reformat_buf, bool decap)
14488 : : {
14489 : : int ret;
14490 : : const struct rte_flow_item *encap_item = NULL;
14491 : : const struct rte_flow_action_raw_encap *encap_conf = NULL;
14492 : : typeof(dest_attr->reformat) *reformat = &dest_attr->reformat;
14493 : :
14494 [ # # # # ]: 0 : switch (actions[0].type) {
14495 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
14496 : 0 : encap_conf = actions[0].conf;
14497 : 0 : break;
14498 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
14499 : 0 : encap_item = MLX5_CONST_ENCAP_ITEM(rte_flow_action_vxlan_encap,
14500 : : actions);
14501 : 0 : break;
14502 : 0 : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
14503 : 0 : encap_item = MLX5_CONST_ENCAP_ITEM(rte_flow_action_nvgre_encap,
14504 : : actions);
14505 : 0 : break;
14506 : : default:
14507 : : return -EINVAL;
14508 : : }
14509 : 0 : *action_type = decap ?
14510 [ # # ]: 0 : MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3 :
14511 : : MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;
14512 [ # # ]: 0 : if (encap_item) {
14513 : 0 : ret = flow_dv_convert_encap_data(encap_item, reformat_buf,
14514 : : &reformat->reformat_data_sz, NULL);
14515 [ # # ]: 0 : if (ret)
14516 : : return -EINVAL;
14517 : 0 : reformat->reformat_data = reformat_buf;
14518 : : } else {
14519 : 0 : reformat->reformat_data = (void *)(uintptr_t)encap_conf->data;
14520 : 0 : reformat->reformat_data_sz = encap_conf->size;
14521 : : }
14522 : : return 0;
14523 : : }
14524 : :
14525 : : static int
14526 : 0 : hw_mirror_format_clone(struct rte_eth_dev *dev,
14527 : : struct mlx5_mirror_clone *clone,
14528 : : const struct mlx5_flow_template_table_cfg *table_cfg,
14529 : : const struct rte_flow_action *actions,
14530 : : struct mlx5dr_action_dest_attr *dest_attr,
14531 : : uint8_t *reformat_buf, struct rte_flow_error *error)
14532 : : {
14533 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14534 : : int ret;
14535 : : uint32_t i;
14536 : : bool decap_seen = false;
14537 : :
14538 [ # # ]: 0 : for (i = 0; actions[i].type != RTE_FLOW_ACTION_TYPE_END; i++) {
14539 : 0 : dest_attr->action_type[i] = mlx5_hw_dr_action_types[actions[i].type];
14540 [ # # # # : 0 : switch (actions[i].type) {
# # # # ]
14541 : 0 : case RTE_FLOW_ACTION_TYPE_QUEUE:
14542 : : case RTE_FLOW_ACTION_TYPE_RSS:
14543 : 0 : ret = mirror_format_tir(dev, clone, table_cfg,
14544 : : &actions[i], dest_attr, error);
14545 [ # # ]: 0 : if (ret)
14546 : 0 : return ret;
14547 : : break;
14548 : 0 : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
14549 : : ret = mirror_format_port(dev, &actions[i],
14550 : : dest_attr, error);
14551 : : if (ret)
14552 : : return ret;
14553 : : break;
14554 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP:
14555 : 0 : ret = mirror_format_jump(dev, clone, table_cfg,
14556 : : &actions[i], dest_attr, error);
14557 [ # # ]: 0 : if (ret)
14558 : 0 : return ret;
14559 : : break;
14560 : 0 : case RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:
14561 : 0 : dest_attr->dest = priv->hw_def_miss;
14562 : 0 : break;
14563 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
14564 : : decap_seen = true;
14565 : 0 : break;
14566 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
14567 : : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
14568 : : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
14569 : 0 : ret = hw_mirror_clone_reformat(&actions[i], dest_attr,
14570 : : &dest_attr->action_type[i],
14571 : : reformat_buf, decap_seen);
14572 [ # # ]: 0 : if (ret < 0)
14573 : 0 : return rte_flow_error_set(error, EINVAL,
14574 : : RTE_FLOW_ERROR_TYPE_ACTION,
14575 : : &actions[i],
14576 : : "failed to create reformat action");
14577 : : break;
14578 : : case RTE_FLOW_ACTION_TYPE_DROP:
14579 : : break;
14580 : 0 : default:
14581 : 0 : return rte_flow_error_set(error, EINVAL,
14582 : : RTE_FLOW_ERROR_TYPE_ACTION,
14583 : : &actions[i], "unsupported sample action");
14584 : : }
14585 : 0 : clone->type = actions->type;
14586 : : }
14587 : 0 : dest_attr->action_type[i] = MLX5DR_ACTION_TYP_LAST;
14588 : 0 : return 0;
14589 : : }
14590 : :
14591 : : static struct rte_flow_action_list_handle *
14592 : 0 : mlx5_hw_mirror_handle_create(struct rte_eth_dev *dev,
14593 : : const struct mlx5_flow_template_table_cfg *table_cfg,
14594 : : const struct rte_flow_action *actions,
14595 : : struct rte_flow_error *error)
14596 : : {
14597 : : uint32_t hws_flags;
14598 : : int ret = 0, i, clones_num;
14599 : : struct mlx5_mirror *mirror;
14600 : : enum mlx5dr_table_type table_type;
14601 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
14602 : : bool unified_fdb = is_unified_fdb(priv);
14603 [ # # ]: 0 : const struct rte_flow_attr *flow_attr = &table_cfg->attr.flow_attr;
14604 : : uint8_t reformat_buf[MLX5_MIRROR_MAX_CLONES_NUM][MLX5_ENCAP_MAX_LEN];
14605 : : struct mlx5dr_action_dest_attr mirror_attr[MLX5_MIRROR_MAX_CLONES_NUM + 1];
14606 : : enum mlx5dr_action_type array_action_types[MLX5_MIRROR_MAX_CLONES_NUM + 1]
14607 : : [MLX5_MIRROR_MAX_SAMPLE_ACTIONS_LEN + 1];
14608 : :
14609 : : memset(mirror_attr, 0, sizeof(mirror_attr));
14610 : : memset(array_action_types, 0, sizeof(array_action_types));
14611 : 0 : table_type = get_mlx5dr_table_type(flow_attr, table_cfg->attr.specialize, unified_fdb);
14612 : 0 : hws_flags = mlx5_hw_act_flag[MLX5_HW_ACTION_FLAG_NONE_ROOT][table_type];
14613 : 0 : clones_num = mlx5_hw_mirror_actions_list_validate(dev, flow_attr,
14614 : : actions);
14615 [ # # ]: 0 : if (clones_num < 0) {
14616 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14617 : : actions, "Invalid mirror list format");
14618 : 0 : return NULL;
14619 : : }
14620 : 0 : mirror = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mirror),
14621 : : 0, SOCKET_ID_ANY);
14622 [ # # ]: 0 : if (!mirror) {
14623 : 0 : rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_ACTION,
14624 : : actions, "Failed to allocate mirror context");
14625 : 0 : return NULL;
14626 : : }
14627 : :
14628 : 0 : mirror->indirect.type = MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR;
14629 : 0 : mirror->clones_num = clones_num;
14630 [ # # ]: 0 : for (i = 0; i < clones_num; i++) {
14631 : : const struct rte_flow_action *clone_actions;
14632 : :
14633 : 0 : mirror_attr[i].action_type = array_action_types[i];
14634 [ # # ]: 0 : if (actions[i].type == RTE_FLOW_ACTION_TYPE_SAMPLE) {
14635 : 0 : const struct rte_flow_action_sample *sample = actions[i].conf;
14636 : :
14637 : 0 : clone_actions = sample->actions;
14638 : : } else {
14639 : : clone_actions = &actions[i];
14640 : : }
14641 : 0 : ret = hw_mirror_format_clone(dev, &mirror->clone[i], table_cfg,
14642 : : clone_actions, &mirror_attr[i],
14643 : 0 : reformat_buf[i], error);
14644 : :
14645 [ # # ]: 0 : if (ret)
14646 : 0 : goto error;
14647 : : }
14648 : 0 : hws_flags |= MLX5DR_ACTION_FLAG_SHARED;
14649 : 0 : mirror->mirror_action = mlx5dr_action_create_dest_array(priv->dr_ctx,
14650 : : clones_num,
14651 : : mirror_attr,
14652 : : hws_flags);
14653 [ # # ]: 0 : if (!mirror->mirror_action) {
14654 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14655 : : actions, "Failed to create HWS mirror action");
14656 : 0 : goto error;
14657 : : }
14658 : :
14659 [ # # ]: 0 : mlx5_indirect_list_add_entry(&priv->indirect_list_head, &mirror->indirect);
14660 : 0 : return (struct rte_flow_action_list_handle *)mirror;
14661 : :
14662 : 0 : error:
14663 : 0 : mlx5_hw_mirror_destroy(dev, mirror);
14664 : 0 : return NULL;
14665 : : }
14666 : :
14667 : : void
14668 : 0 : mlx5_destroy_legacy_indirect(__rte_unused struct rte_eth_dev *dev,
14669 : : struct mlx5_indirect_list *ptr)
14670 : : {
14671 : : struct mlx5_indlst_legacy *obj = (typeof(obj))ptr;
14672 : :
14673 : : switch (obj->legacy_type) {
14674 : : case RTE_FLOW_ACTION_TYPE_METER_MARK:
14675 : : break; /* ASO meters were released in mlx5_flow_meter_flush() */
14676 : : default:
14677 : : break;
14678 : : }
14679 : 0 : mlx5_free(obj);
14680 : 0 : }
14681 : :
14682 : : static struct rte_flow_action_list_handle *
14683 : 0 : mlx5_create_legacy_indlst(struct rte_eth_dev *dev, uint32_t queue,
14684 : : const struct rte_flow_op_attr *attr,
14685 : : const struct rte_flow_indir_action_conf *conf,
14686 : : const struct rte_flow_action *actions,
14687 : : void *user_data, struct rte_flow_error *error)
14688 : : {
14689 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14690 : 0 : struct mlx5_indlst_legacy *indlst_obj = mlx5_malloc(MLX5_MEM_ZERO,
14691 : : sizeof(*indlst_obj),
14692 : : 0, SOCKET_ID_ANY);
14693 : :
14694 [ # # ]: 0 : if (!indlst_obj)
14695 : : return NULL;
14696 : 0 : indlst_obj->handle = flow_hw_action_handle_create(dev, queue, attr, conf,
14697 : : actions, user_data,
14698 : : error);
14699 [ # # ]: 0 : if (!indlst_obj->handle) {
14700 : 0 : mlx5_free(indlst_obj);
14701 : 0 : return NULL;
14702 : : }
14703 : 0 : indlst_obj->legacy_type = actions[0].type;
14704 : 0 : indlst_obj->indirect.type = MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY;
14705 [ # # ]: 0 : mlx5_indirect_list_add_entry(&priv->indirect_list_head, &indlst_obj->indirect);
14706 : 0 : return (struct rte_flow_action_list_handle *)indlst_obj;
14707 : : }
14708 : :
14709 : : static __rte_always_inline enum mlx5_indirect_list_type
14710 : : flow_hw_inlist_type_get(const struct rte_flow_action *actions)
14711 : : {
14712 [ # # # # ]: 0 : switch (actions[0].type) {
14713 : : case RTE_FLOW_ACTION_TYPE_SAMPLE:
14714 : : return MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR;
14715 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
14716 : 0 : return actions[1].type == RTE_FLOW_ACTION_TYPE_END ?
14717 : 0 : MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY :
14718 : : MLX5_INDIRECT_ACTION_LIST_TYPE_ERR;
14719 : : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
14720 : : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
14721 : : return MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT;
14722 : : default:
14723 : : break;
14724 : : }
14725 : : return MLX5_INDIRECT_ACTION_LIST_TYPE_ERR;
14726 : : }
14727 : :
14728 : : static struct rte_flow_action_list_handle*
14729 : 0 : mlx5_hw_decap_encap_handle_create(struct rte_eth_dev *dev,
14730 : : const struct mlx5_flow_template_table_cfg *table_cfg,
14731 : : const struct rte_flow_action *actions,
14732 : : struct rte_flow_error *error)
14733 : : {
14734 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14735 : : const struct rte_flow_attr *flow_attr = &table_cfg->attr.flow_attr;
14736 : : const struct rte_flow_action *encap = NULL;
14737 : : const struct rte_flow_action *decap = NULL;
14738 : 0 : struct rte_flow_indir_action_conf indirect_conf = {
14739 : 0 : .ingress = flow_attr->ingress,
14740 : 0 : .egress = flow_attr->egress,
14741 : 0 : .transfer = flow_attr->transfer,
14742 : : };
14743 : : struct mlx5_hw_encap_decap_action *handle;
14744 : : uint64_t action_flags = 0;
14745 : :
14746 : : /*
14747 : : * Allow
14748 : : * 1. raw_decap / raw_encap / end
14749 : : * 2. raw_encap / end
14750 : : * 3. raw_decap / end
14751 : : */
14752 [ # # ]: 0 : while (actions->type != RTE_FLOW_ACTION_TYPE_END) {
14753 [ # # ]: 0 : if (actions->type == RTE_FLOW_ACTION_TYPE_RAW_DECAP) {
14754 [ # # ]: 0 : if (action_flags) {
14755 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14756 : : actions, "Invalid indirect action list sequence");
14757 : 0 : return NULL;
14758 : : }
14759 : : action_flags |= MLX5_FLOW_ACTION_DECAP;
14760 : : decap = actions;
14761 [ # # ]: 0 : } else if (actions->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
14762 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_ENCAP) {
14763 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14764 : : actions, "Invalid indirect action list sequence");
14765 : 0 : return NULL;
14766 : : }
14767 : 0 : action_flags |= MLX5_FLOW_ACTION_ENCAP;
14768 : : encap = actions;
14769 : : } else {
14770 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14771 : : actions, "Invalid indirect action type in list");
14772 : 0 : return NULL;
14773 : : }
14774 : 0 : actions++;
14775 : : }
14776 [ # # ]: 0 : if (!decap && !encap) {
14777 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14778 : : actions, "Invalid indirect action combinations");
14779 : 0 : return NULL;
14780 : : }
14781 : 0 : handle = mlx5_reformat_action_create(dev, &indirect_conf, encap, decap, error);
14782 [ # # ]: 0 : if (!handle) {
14783 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14784 : : actions, "Failed to create HWS decap_encap action");
14785 : 0 : return NULL;
14786 : : }
14787 : 0 : handle->indirect.type = MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT;
14788 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->indirect_list_head, &handle->indirect, entry);
14789 : 0 : return (struct rte_flow_action_list_handle *)handle;
14790 : : }
14791 : :
14792 : : static struct rte_flow_action_list_handle *
14793 [ # # ]: 0 : flow_hw_async_action_list_handle_create(struct rte_eth_dev *dev, uint32_t queue,
14794 : : const struct rte_flow_op_attr *attr,
14795 : : const struct rte_flow_indir_action_conf *conf,
14796 : : const struct rte_flow_action *actions,
14797 : : void *user_data,
14798 : : struct rte_flow_error *error)
14799 : : {
14800 : : struct mlx5_hw_q_job *job = NULL;
14801 : : bool push = flow_hw_action_push(attr);
14802 : : enum mlx5_indirect_list_type list_type;
14803 : : struct rte_flow_action_list_handle *handle;
14804 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14805 : 0 : const struct mlx5_flow_template_table_cfg table_cfg = {
14806 : : .external = true,
14807 : : .attr = {
14808 : : .flow_attr = {
14809 : 0 : .ingress = conf->ingress,
14810 : 0 : .egress = conf->egress,
14811 : 0 : .transfer = conf->transfer
14812 : : }
14813 : : }
14814 : : };
14815 : :
14816 [ # # ]: 0 : if (!mlx5_hw_ctx_validate(dev, error))
14817 : : return NULL;
14818 [ # # ]: 0 : if (!actions) {
14819 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14820 : : NULL, "No action list");
14821 : 0 : return NULL;
14822 : : }
14823 : : list_type = flow_hw_inlist_type_get(actions);
14824 [ # # ]: 0 : if (list_type == MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY) {
14825 : : /*
14826 : : * Legacy indirect actions already have
14827 : : * async resources management. No need to do it twice.
14828 : : */
14829 : 0 : handle = mlx5_create_legacy_indlst(dev, queue, attr, conf,
14830 : : actions, user_data, error);
14831 : 0 : goto end;
14832 : : }
14833 [ # # ]: 0 : if (attr) {
14834 : : job = flow_hw_action_job_init(priv, queue, NULL, user_data,
14835 : : NULL, MLX5_HW_Q_JOB_TYPE_CREATE,
14836 : : MLX5_HW_INDIRECT_TYPE_LIST, error);
14837 : : if (!job)
14838 : 0 : return NULL;
14839 : : }
14840 [ # # # ]: 0 : switch (list_type) {
14841 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR:
14842 : 0 : handle = mlx5_hw_mirror_handle_create(dev, &table_cfg,
14843 : : actions, error);
14844 : 0 : break;
14845 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT:
14846 : 0 : handle = mlx5_hw_decap_encap_handle_create(dev, &table_cfg,
14847 : : actions, error);
14848 : 0 : break;
14849 : 0 : default:
14850 : : handle = NULL;
14851 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14852 : : actions, "Invalid list");
14853 : : }
14854 [ # # ]: 0 : if (job) {
14855 : 0 : job->action = handle;
14856 [ # # ]: 0 : flow_hw_action_finalize(dev, queue, job, push, false,
14857 : : handle != NULL);
14858 : : }
14859 : 0 : end:
14860 : : return handle;
14861 : : }
14862 : :
14863 : : static struct rte_flow_action_list_handle *
14864 : 0 : flow_hw_action_list_handle_create(struct rte_eth_dev *dev,
14865 : : const struct rte_flow_indir_action_conf *conf,
14866 : : const struct rte_flow_action *actions,
14867 : : struct rte_flow_error *error)
14868 : : {
14869 : 0 : return flow_hw_async_action_list_handle_create(dev, MLX5_HW_INV_QUEUE,
14870 : : NULL, conf, actions,
14871 : : NULL, error);
14872 : : }
14873 : :
14874 : : static int
14875 [ # # ]: 0 : flow_hw_async_action_list_handle_destroy
14876 : : (struct rte_eth_dev *dev, uint32_t queue,
14877 : : const struct rte_flow_op_attr *attr,
14878 : : struct rte_flow_action_list_handle *handle,
14879 : : void *user_data, struct rte_flow_error *error)
14880 : : {
14881 : : int ret = 0;
14882 : : struct mlx5_hw_q_job *job = NULL;
14883 : : bool push = flow_hw_action_push(attr);
14884 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
14885 : : enum mlx5_indirect_list_type type =
14886 : : mlx5_get_indirect_list_type((void *)handle);
14887 : :
14888 [ # # ]: 0 : if (type == MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY) {
14889 : : struct mlx5_indlst_legacy *legacy = (typeof(legacy))handle;
14890 : :
14891 : 0 : ret = flow_hw_action_handle_destroy(dev, queue, attr,
14892 : : legacy->handle,
14893 : : user_data, error);
14894 : : mlx5_indirect_list_remove_entry(&legacy->indirect);
14895 : 0 : goto end;
14896 : : }
14897 [ # # ]: 0 : if (attr) {
14898 : : job = flow_hw_action_job_init(priv, queue, NULL, user_data,
14899 : : NULL, MLX5_HW_Q_JOB_TYPE_DESTROY,
14900 : : MLX5_HW_INDIRECT_TYPE_LIST, error);
14901 : : if (!job)
14902 : 0 : return rte_errno;
14903 : : }
14904 [ # # # ]: 0 : switch (type) {
14905 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR:
14906 : 0 : mlx5_hw_mirror_destroy(dev, (struct mlx5_mirror *)handle);
14907 : 0 : break;
14908 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT:
14909 [ # # ]: 0 : LIST_REMOVE(&((struct mlx5_hw_encap_decap_action *)handle)->indirect,
14910 : : entry);
14911 : 0 : mlx5_reformat_action_destroy(dev, handle, error);
14912 : 0 : break;
14913 : 0 : default:
14914 : 0 : ret = rte_flow_error_set(error, EINVAL,
14915 : : RTE_FLOW_ERROR_TYPE_ACTION,
14916 : : NULL, "Invalid indirect list handle");
14917 : : }
14918 [ # # ]: 0 : if (job) {
14919 : : flow_hw_action_finalize(dev, queue, job, push, false, true);
14920 : : }
14921 : 0 : end:
14922 : : return ret;
14923 : : }
14924 : :
14925 : : static int
14926 : 0 : flow_hw_action_list_handle_destroy(struct rte_eth_dev *dev,
14927 : : struct rte_flow_action_list_handle *handle,
14928 : : struct rte_flow_error *error)
14929 : : {
14930 : 0 : return flow_hw_async_action_list_handle_destroy(dev, MLX5_HW_INV_QUEUE,
14931 : : NULL, handle, NULL,
14932 : : error);
14933 : : }
14934 : :
14935 : : static int
14936 [ # # ]: 0 : flow_hw_async_action_list_handle_query_update
14937 : : (struct rte_eth_dev *dev, uint32_t queue_id,
14938 : : const struct rte_flow_op_attr *attr,
14939 : : const struct rte_flow_action_list_handle *handle,
14940 : : const void **update, void **query,
14941 : : enum rte_flow_query_update_mode mode,
14942 : : void *user_data, struct rte_flow_error *error)
14943 : : {
14944 : : enum mlx5_indirect_list_type type =
14945 : : mlx5_get_indirect_list_type((const void *)handle);
14946 : :
14947 [ # # ]: 0 : if (type == MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY) {
14948 : : struct mlx5_indlst_legacy *legacy = (void *)(uintptr_t)handle;
14949 : :
14950 [ # # ]: 0 : if (update && query)
14951 : 0 : return flow_hw_async_action_handle_query_update
14952 : : (dev, queue_id, attr, legacy->handle,
14953 : : update, query, mode, user_data, error);
14954 [ # # # # ]: 0 : else if (update && update[0])
14955 : 0 : return flow_hw_action_handle_update(dev, queue_id, attr,
14956 : : legacy->handle, update[0],
14957 : : user_data, error);
14958 [ # # # # ]: 0 : else if (query && query[0])
14959 : 0 : return flow_hw_action_handle_query(dev, queue_id, attr,
14960 : 0 : legacy->handle, query[0],
14961 : : user_data, error);
14962 : : else
14963 : 0 : return rte_flow_error_set(error, EINVAL,
14964 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14965 : : NULL, "invalid legacy handle query_update parameters");
14966 : : }
14967 : : return -ENOTSUP;
14968 : : }
14969 : :
14970 : : static int
14971 : 0 : flow_hw_action_list_handle_query_update(struct rte_eth_dev *dev,
14972 : : const struct rte_flow_action_list_handle *handle,
14973 : : const void **update, void **query,
14974 : : enum rte_flow_query_update_mode mode,
14975 : : struct rte_flow_error *error)
14976 : : {
14977 : 0 : return flow_hw_async_action_list_handle_query_update
14978 : : (dev, MLX5_HW_INV_QUEUE, NULL, handle,
14979 : : update, query, mode, NULL, error);
14980 : : }
14981 : :
14982 : : static int
14983 : 0 : flow_hw_calc_table_hash(struct rte_eth_dev *dev,
14984 : : const struct rte_flow_template_table *table,
14985 : : const struct rte_flow_item pattern[],
14986 : : uint8_t pattern_template_index,
14987 : : uint32_t *hash, struct rte_flow_error *error)
14988 : : {
14989 : : const struct rte_flow_item *items;
14990 : : struct mlx5_flow_hw_pattern_params pp;
14991 : : int res;
14992 : :
14993 : 0 : items = flow_hw_get_rule_items(dev, table, pattern,
14994 : : pattern_template_index,
14995 : : &pp);
14996 : 0 : res = mlx5dr_rule_hash_calculate(mlx5_table_matcher(table), items,
14997 : : pattern_template_index,
14998 : : MLX5DR_RULE_HASH_CALC_MODE_RAW,
14999 : : hash);
15000 [ # # ]: 0 : if (res)
15001 : 0 : return rte_flow_error_set(error, res,
15002 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15003 : : NULL,
15004 : : "hash could not be calculated");
15005 : : return 0;
15006 : : }
15007 : :
15008 : : static int
15009 : 0 : flow_hw_calc_encap_hash(struct rte_eth_dev *dev,
15010 : : const struct rte_flow_item pattern[],
15011 : : enum rte_flow_encap_hash_field dest_field,
15012 : : uint8_t *hash,
15013 : : struct rte_flow_error *error)
15014 : : {
15015 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
15016 : : struct mlx5dr_crc_encap_entropy_hash_fields data;
15017 : 0 : enum mlx5dr_crc_encap_entropy_hash_size res_size =
15018 : : dest_field == RTE_FLOW_ENCAP_HASH_FIELD_SRC_PORT ?
15019 : 0 : MLX5DR_CRC_ENCAP_ENTROPY_HASH_SIZE_16 :
15020 : : MLX5DR_CRC_ENCAP_ENTROPY_HASH_SIZE_8;
15021 : : int res;
15022 : :
15023 : : memset(&data, 0, sizeof(struct mlx5dr_crc_encap_entropy_hash_fields));
15024 : :
15025 [ # # ]: 0 : for (; pattern->type != RTE_FLOW_ITEM_TYPE_END; pattern++) {
15026 [ # # # # : 0 : switch (pattern->type) {
# # # # ]
15027 : 0 : case RTE_FLOW_ITEM_TYPE_IPV4:
15028 : 0 : data.dst.ipv4_addr =
15029 : 0 : ((const struct rte_flow_item_ipv4 *)(pattern->spec))->hdr.dst_addr;
15030 : 0 : data.src.ipv4_addr =
15031 : 0 : ((const struct rte_flow_item_ipv4 *)(pattern->spec))->hdr.src_addr;
15032 : 0 : break;
15033 : 0 : case RTE_FLOW_ITEM_TYPE_IPV6:
15034 : : memcpy(data.dst.ipv6_addr,
15035 : 0 : &((const struct rte_flow_item_ipv6 *)(pattern->spec))->hdr.dst_addr,
15036 : : sizeof(data.dst.ipv6_addr));
15037 : : memcpy(data.src.ipv6_addr,
15038 : : &((const struct rte_flow_item_ipv6 *)(pattern->spec))->hdr.src_addr,
15039 : : sizeof(data.src.ipv6_addr));
15040 : : break;
15041 : 0 : case RTE_FLOW_ITEM_TYPE_UDP:
15042 : 0 : data.next_protocol = IPPROTO_UDP;
15043 : 0 : data.dst_port =
15044 : 0 : ((const struct rte_flow_item_udp *)(pattern->spec))->hdr.dst_port;
15045 : 0 : data.src_port =
15046 : 0 : ((const struct rte_flow_item_udp *)(pattern->spec))->hdr.src_port;
15047 : 0 : break;
15048 : 0 : case RTE_FLOW_ITEM_TYPE_TCP:
15049 : 0 : data.next_protocol = IPPROTO_TCP;
15050 : 0 : data.dst_port =
15051 : 0 : ((const struct rte_flow_item_tcp *)(pattern->spec))->hdr.dst_port;
15052 : 0 : data.src_port =
15053 : 0 : ((const struct rte_flow_item_tcp *)(pattern->spec))->hdr.src_port;
15054 : 0 : break;
15055 : 0 : case RTE_FLOW_ITEM_TYPE_ICMP:
15056 : 0 : data.next_protocol = IPPROTO_ICMP;
15057 : 0 : break;
15058 : 0 : case RTE_FLOW_ITEM_TYPE_ICMP6:
15059 : 0 : data.next_protocol = IPPROTO_ICMPV6;
15060 : 0 : break;
15061 : 0 : case RTE_FLOW_ITEM_TYPE_GRE:
15062 : 0 : data.next_protocol = IPPROTO_GRE;
15063 : 0 : break;
15064 : : default:
15065 : : break;
15066 : : }
15067 : : }
15068 : 0 : res = mlx5dr_crc_encap_entropy_hash_calc(priv->dr_ctx, &data, hash, res_size);
15069 [ # # ]: 0 : if (res)
15070 : 0 : return rte_flow_error_set(error, res,
15071 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15072 : : NULL, "error while calculating encap hash");
15073 : : return 0;
15074 : : }
15075 : :
15076 : : static int
15077 : 0 : flow_hw_table_resize_multi_pattern_actions(struct rte_eth_dev *dev,
15078 : : struct rte_flow_template_table *table,
15079 : : uint32_t nb_flows,
15080 : : struct rte_flow_error *error)
15081 : : {
15082 : 0 : struct mlx5_multi_pattern_segment *segment = table->mpctx.segments;
15083 : : uint32_t bulk_size;
15084 : : int i, ret;
15085 : :
15086 : : /**
15087 : : * Segment always allocates Modify Header Argument Objects number in
15088 : : * powers of 2.
15089 : : * On resize, PMD adds minimal required argument objects number.
15090 : : * For example, if table size was 10, it allocated 16 argument objects.
15091 : : * Resize to 15 will not add new objects.
15092 : : */
15093 : 0 : for (i = 1;
15094 [ # # # # ]: 0 : i < MLX5_MAX_TABLE_RESIZE_NUM && segment->capacity;
15095 : 0 : i++, segment++) {
15096 : : /* keep the devtools/checkpatches.sh happy */
15097 : : }
15098 [ # # ]: 0 : if (i == MLX5_MAX_TABLE_RESIZE_NUM)
15099 : 0 : return rte_flow_error_set(error, EINVAL,
15100 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15101 : : table, "too many resizes");
15102 [ # # ]: 0 : if (segment->head_index - 1 >= nb_flows)
15103 : : return 0;
15104 [ # # ]: 0 : bulk_size = rte_align32pow2(nb_flows - segment->head_index + 1);
15105 : 0 : ret = mlx5_tbl_multi_pattern_process(dev, table, segment,
15106 : : rte_log2_u32(bulk_size),
15107 : : error);
15108 [ # # ]: 0 : if (ret)
15109 : 0 : return rte_flow_error_set(error, EINVAL,
15110 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15111 : : table, "too many resizes");
15112 : : return i;
15113 : : }
15114 : :
15115 : : static int
15116 : 0 : flow_hw_table_resize(struct rte_eth_dev *dev,
15117 : : struct rte_flow_template_table *table,
15118 : : uint32_t nb_flows,
15119 : : struct rte_flow_error *error)
15120 : : {
15121 : : struct mlx5dr_action_template *at[MLX5_HW_TBL_MAX_ACTION_TEMPLATE];
15122 : : struct mlx5dr_match_template *mt[MLX5_HW_TBL_MAX_ITEM_TEMPLATE];
15123 : 0 : struct mlx5dr_matcher_attr matcher_attr = table->matcher_attr;
15124 : 0 : struct mlx5dr_action_jump_to_matcher_attr jump_attr = {
15125 : : .type = MLX5DR_ACTION_JUMP_TO_MATCHER_BY_INDEX,
15126 : : .matcher = NULL,
15127 : : };
15128 : : struct mlx5_multi_pattern_segment *segment = NULL;
15129 : : struct mlx5dr_matcher *matcher = NULL;
15130 : : struct mlx5dr_action *jump = NULL;
15131 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
15132 : 0 : uint32_t i, selector = table->matcher_selector;
15133 : 0 : uint32_t other_selector = (selector + 1) & 1;
15134 : : int ret;
15135 : :
15136 [ # # ]: 0 : if (!rte_flow_template_table_resizable(dev->data->port_id, &table->cfg.attr))
15137 : 0 : return rte_flow_error_set(error, EINVAL,
15138 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15139 : : table, "no resizable attribute");
15140 [ # # ]: 0 : if (table->matcher_info[other_selector].matcher)
15141 : 0 : return rte_flow_error_set(error, EINVAL,
15142 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15143 : : table, "last table resize was not completed");
15144 [ # # ]: 0 : if (nb_flows <= table->cfg.attr.nb_flows)
15145 : 0 : return rte_flow_error_set(error, EINVAL,
15146 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15147 : : table, "shrinking table is not supported");
15148 : 0 : ret = mlx5_ipool_resize(table->flow, nb_flows, error);
15149 [ # # ]: 0 : if (ret)
15150 : : return ret;
15151 : : /*
15152 : : * A resizable matcher doesn't support rule update. In this case, the ipool
15153 : : * for the resource is not created and there is no need to resize it.
15154 : : */
15155 : : MLX5_ASSERT(!table->resource);
15156 [ # # ]: 0 : if (mlx5_is_multi_pattern_active(&table->mpctx)) {
15157 : 0 : ret = flow_hw_table_resize_multi_pattern_actions(dev, table, nb_flows, error);
15158 [ # # ]: 0 : if (ret < 0)
15159 : : return ret;
15160 [ # # ]: 0 : if (ret > 0)
15161 : 0 : segment = table->mpctx.segments + ret;
15162 : : }
15163 [ # # ]: 0 : for (i = 0; i < table->nb_item_templates; i++)
15164 : 0 : mt[i] = table->its[i]->mt;
15165 [ # # ]: 0 : for (i = 0; i < table->nb_action_templates; i++)
15166 : 0 : at[i] = table->ats[i].action_template->tmpl;
15167 : : nb_flows = rte_align32pow2(nb_flows);
15168 : 0 : matcher_attr.rule.num_log = rte_log2_u32(nb_flows);
15169 : 0 : matcher = mlx5dr_matcher_create(table->grp->tbl, mt,
15170 : : table->nb_item_templates, at,
15171 : : table->nb_action_templates,
15172 : : &matcher_attr);
15173 [ # # ]: 0 : if (!matcher) {
15174 : 0 : ret = rte_flow_error_set(error, rte_errno,
15175 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15176 : : table, "failed to create new matcher");
15177 : 0 : goto error;
15178 : : }
15179 [ # # ]: 0 : if (matcher_attr.isolated) {
15180 : 0 : jump_attr.matcher = matcher;
15181 : 0 : jump = mlx5dr_action_create_jump_to_matcher(priv->dr_ctx, &jump_attr,
15182 : 0 : mlx5_hw_act_flag[!!table->cfg.attr.flow_attr.group][table->type]);
15183 [ # # ]: 0 : if (!jump) {
15184 : 0 : ret = rte_flow_error_set(error, rte_errno,
15185 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15186 : : table, "failed to create jump to matcher action");
15187 : 0 : goto error;
15188 : : }
15189 : : }
15190 : 0 : rte_rwlock_write_lock(&table->matcher_replace_rwlk);
15191 : 0 : ret = mlx5dr_matcher_resize_set_target
15192 : : (table->matcher_info[selector].matcher, matcher);
15193 [ # # ]: 0 : if (ret) {
15194 : : rte_rwlock_write_unlock(&table->matcher_replace_rwlk);
15195 : 0 : ret = rte_flow_error_set(error, rte_errno,
15196 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15197 : : table, "failed to initiate matcher swap");
15198 : 0 : goto error;
15199 : : }
15200 : 0 : table->cfg.attr.nb_flows = nb_flows;
15201 : 0 : table->matcher_info[other_selector].matcher = matcher;
15202 : 0 : table->matcher_info[other_selector].jump = jump;
15203 : 0 : table->matcher_selector = other_selector;
15204 : 0 : rte_atomic_store_explicit(&table->matcher_info[other_selector].refcnt,
15205 : : 0, rte_memory_order_relaxed);
15206 : : rte_rwlock_write_unlock(&table->matcher_replace_rwlk);
15207 : 0 : return 0;
15208 : 0 : error:
15209 [ # # ]: 0 : if (segment)
15210 : 0 : mlx5_destroy_multi_pattern_segment(segment);
15211 [ # # ]: 0 : if (jump)
15212 : 0 : mlx5dr_action_destroy(jump);
15213 [ # # ]: 0 : if (matcher) {
15214 : 0 : ret = mlx5dr_matcher_destroy(matcher);
15215 : 0 : return rte_flow_error_set(error, rte_errno,
15216 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15217 : : table, "failed to destroy new matcher");
15218 : : }
15219 : : return ret;
15220 : : }
15221 : :
15222 : : static int
15223 : 0 : flow_hw_table_resize_complete(__rte_unused struct rte_eth_dev *dev,
15224 : : struct rte_flow_template_table *table,
15225 : : struct rte_flow_error *error)
15226 : : {
15227 : : int ret;
15228 : 0 : uint32_t selector = table->matcher_selector;
15229 : 0 : uint32_t other_selector = (selector + 1) & 1;
15230 : : struct mlx5_matcher_info *matcher_info = &table->matcher_info[other_selector];
15231 : : uint32_t matcher_refcnt;
15232 : :
15233 [ # # ]: 0 : if (!rte_flow_template_table_resizable(dev->data->port_id, &table->cfg.attr))
15234 : 0 : return rte_flow_error_set(error, EINVAL,
15235 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15236 : : table, "no resizable attribute");
15237 : 0 : matcher_refcnt = rte_atomic_load_explicit(&matcher_info->refcnt,
15238 : : rte_memory_order_relaxed);
15239 [ # # # # ]: 0 : if (!matcher_info->matcher || matcher_refcnt)
15240 : 0 : return rte_flow_error_set(error, EBUSY,
15241 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15242 : : table, "cannot complete table resize");
15243 [ # # ]: 0 : if (matcher_info->jump)
15244 : 0 : mlx5dr_action_destroy(matcher_info->jump);
15245 : 0 : ret = mlx5dr_matcher_destroy(matcher_info->matcher);
15246 [ # # ]: 0 : if (ret)
15247 : 0 : return rte_flow_error_set(error, rte_errno,
15248 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15249 : : table, "failed to destroy retired matcher");
15250 : 0 : matcher_info->matcher = NULL;
15251 : 0 : return 0;
15252 : : }
15253 : :
15254 : : static int
15255 : 0 : flow_hw_update_resized(struct rte_eth_dev *dev, uint32_t queue,
15256 : : const struct rte_flow_op_attr *attr,
15257 : : struct rte_flow *flow, void *user_data,
15258 : : struct rte_flow_error *error)
15259 : : {
15260 : : int ret;
15261 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
15262 : : struct rte_flow_hw *hw_flow = (struct rte_flow_hw *)flow;
15263 : 0 : struct rte_flow_template_table *table = hw_flow->table;
15264 : 0 : struct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(dev->data->port_id, hw_flow);
15265 : 0 : uint32_t table_selector = table->matcher_selector;
15266 : 0 : uint32_t rule_selector = aux->matcher_selector;
15267 : : uint32_t other_selector;
15268 : : struct mlx5dr_matcher *other_matcher;
15269 : 0 : struct mlx5dr_rule_attr rule_attr = {
15270 : : .queue_id = queue,
15271 : 0 : .burst = attr->postpone,
15272 : : };
15273 : :
15274 : : MLX5_ASSERT(hw_flow->flags & MLX5_FLOW_HW_FLOW_FLAG_MATCHER_SELECTOR);
15275 : : /**
15276 : : * mlx5dr_matcher_resize_rule_move() accepts original table matcher -
15277 : : * the one that was used BEFORE table resize.
15278 : : * Since the function is called AFTER table resize,
15279 : : * `table->matcher_selector` always points to the new matcher and
15280 : : * `aux->matcher_selector` points to a matcher used to create the flow.
15281 : : */
15282 : : other_selector = rule_selector == table_selector ?
15283 [ # # ]: 0 : (rule_selector + 1) & 1 : rule_selector;
15284 : 0 : other_matcher = table->matcher_info[other_selector].matcher;
15285 [ # # ]: 0 : if (!other_matcher)
15286 : 0 : return rte_flow_error_set(error, EINVAL,
15287 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
15288 : : "no active table resize");
15289 : 0 : hw_flow->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_MOVE;
15290 : 0 : hw_flow->user_data = user_data;
15291 : 0 : rule_attr.user_data = hw_flow;
15292 [ # # ]: 0 : if (rule_selector == table_selector) {
15293 : 0 : struct rte_ring *ring = !attr->postpone ?
15294 [ # # ]: 0 : priv->hw_q[queue].flow_transfer_completed :
15295 : 0 : priv->hw_q[queue].flow_transfer_pending;
15296 : 0 : rte_ring_enqueue(ring, hw_flow);
15297 : : flow_hw_q_inc_flow_ops(priv, queue);
15298 : 0 : return 0;
15299 : : }
15300 : 0 : ret = mlx5dr_matcher_resize_rule_move(other_matcher,
15301 : 0 : (struct mlx5dr_rule *)hw_flow->rule,
15302 : : &rule_attr);
15303 [ # # ]: 0 : if (ret) {
15304 : 0 : return rte_flow_error_set(error, rte_errno,
15305 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
15306 : : "flow transfer failed");
15307 : : }
15308 : : flow_hw_q_inc_flow_ops(priv, queue);
15309 : 0 : return 0;
15310 : : }
15311 : :
15312 : : /**
15313 : : * Internal validation function. For validating both actions and items.
15314 : : *
15315 : : * @param[in] dev
15316 : : * Pointer to the rte_eth_dev structure.
15317 : : * @param[in] attr
15318 : : * Pointer to the flow attributes.
15319 : : * @param[in] items
15320 : : * Pointer to the list of items.
15321 : : * @param[in] actions
15322 : : * Pointer to the list of actions.
15323 : : * @param[in] external
15324 : : * This flow rule is created by request external to PMD.
15325 : : * @param[in] hairpin
15326 : : * Number of hairpin TX actions, 0 means classic flow.
15327 : : * @param[out] error
15328 : : * Pointer to the error structure.
15329 : : *
15330 : : * @return
15331 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
15332 : : */
15333 : : static int
15334 : 0 : flow_hw_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
15335 : : const struct rte_flow_item items[],
15336 : : const struct rte_flow_action actions[] __rte_unused,
15337 : : bool external, int hairpin __rte_unused,
15338 : : struct rte_flow_error *error)
15339 : : {
15340 : 0 : const struct rte_flow_pattern_template_attr pattern_template_attr = {
15341 : : .relaxed_matching = 0,
15342 : 0 : .ingress = attr->ingress,
15343 : 0 : .egress = attr->egress,
15344 : 0 : .transfer = attr->transfer,
15345 : : };
15346 : 0 : uint64_t item_flags = 0;
15347 : : int ret = 0;
15348 : :
15349 [ # # ]: 0 : if (external) {
15350 : : /* Validate application items only */
15351 : 0 : ret = __flow_hw_pattern_validate(dev, &pattern_template_attr, items,
15352 : : &item_flags, true, error);
15353 [ # # ]: 0 : if (ret < 0)
15354 : 0 : return -rte_errno;
15355 : : }
15356 : : return 0;
15357 : : }
15358 : :
15359 : : const struct mlx5_flow_driver_ops mlx5_flow_hw_drv_ops = {
15360 : : .list_create = flow_hw_list_create,
15361 : : .list_destroy = flow_hw_list_destroy,
15362 : : .validate = flow_hw_validate,
15363 : : .info_get = flow_hw_info_get,
15364 : : .configure = flow_hw_configure,
15365 : : .pattern_validate = flow_hw_pattern_validate,
15366 : : .pattern_template_create = flow_hw_pattern_template_create,
15367 : : .pattern_template_destroy = flow_hw_pattern_template_destroy,
15368 : : .actions_validate = flow_hw_actions_validate,
15369 : : .actions_template_create = flow_hw_actions_template_create,
15370 : : .actions_template_destroy = flow_hw_actions_template_destroy,
15371 : : .template_table_create = flow_hw_template_table_create,
15372 : : .template_table_destroy = flow_hw_table_destroy,
15373 : : .table_resize = flow_hw_table_resize,
15374 : : .group_set_miss_actions = flow_hw_group_set_miss_actions,
15375 : : .async_flow_create = flow_hw_async_flow_create,
15376 : : .async_flow_create_by_index = flow_hw_async_flow_create_by_index,
15377 : : .async_flow_update = flow_hw_async_flow_update,
15378 : : .async_flow_destroy = flow_hw_async_flow_destroy,
15379 : : .flow_update_resized = flow_hw_update_resized,
15380 : : .table_resize_complete = flow_hw_table_resize_complete,
15381 : : .pull = flow_hw_pull,
15382 : : .push = flow_hw_push,
15383 : : .async_action_create = flow_hw_action_handle_create,
15384 : : .async_action_destroy = flow_hw_action_handle_destroy,
15385 : : .async_action_update = flow_hw_action_handle_update,
15386 : : .async_action_query_update = flow_hw_async_action_handle_query_update,
15387 : : .async_action_query = flow_hw_action_handle_query,
15388 : : .action_validate = flow_hw_action_validate,
15389 : : .action_create = flow_hw_action_create,
15390 : : .action_destroy = flow_hw_action_destroy,
15391 : : .action_update = flow_hw_action_update,
15392 : : .action_query = flow_hw_action_query,
15393 : : .action_query_update = flow_hw_action_query_update,
15394 : : .action_list_handle_create = flow_hw_action_list_handle_create,
15395 : : .action_list_handle_destroy = flow_hw_action_list_handle_destroy,
15396 : : .action_list_handle_query_update =
15397 : : flow_hw_action_list_handle_query_update,
15398 : : .async_action_list_handle_create =
15399 : : flow_hw_async_action_list_handle_create,
15400 : : .async_action_list_handle_destroy =
15401 : : flow_hw_async_action_list_handle_destroy,
15402 : : .async_action_list_handle_query_update =
15403 : : flow_hw_async_action_list_handle_query_update,
15404 : : .query = flow_hw_query,
15405 : : .get_aged_flows = flow_hw_get_aged_flows,
15406 : : .get_q_aged_flows = flow_hw_get_q_aged_flows,
15407 : : .item_create = flow_dv_item_create,
15408 : : .item_release = flow_dv_item_release,
15409 : : .flow_calc_table_hash = flow_hw_calc_table_hash,
15410 : : .flow_calc_encap_hash = flow_hw_calc_encap_hash,
15411 : : };
15412 : :
15413 : : /**
15414 : : * Creates a control flow using flow template API on @p proxy_dev device,
15415 : : * on behalf of @p owner_dev device.
15416 : : *
15417 : : * This function uses locks internally to synchronize access to the
15418 : : * flow queue.
15419 : : *
15420 : : * Created flow is stored in private list associated with @p proxy_dev device.
15421 : : *
15422 : : * @param owner_dev
15423 : : * Pointer to Ethernet device on behalf of which flow is created.
15424 : : * @param proxy_dev
15425 : : * Pointer to Ethernet device on which flow is created.
15426 : : * @param table
15427 : : * Pointer to flow table.
15428 : : * @param items
15429 : : * Pointer to flow rule items.
15430 : : * @param item_template_idx
15431 : : * Index of an item template associated with @p table.
15432 : : * @param actions
15433 : : * Pointer to flow rule actions.
15434 : : * @param action_template_idx
15435 : : * Index of an action template associated with @p table.
15436 : : * @param info
15437 : : * Additional info about control flow rule.
15438 : : * @param external
15439 : : * External ctrl flow.
15440 : : *
15441 : : * @return
15442 : : * 0 on success, negative errno value otherwise and rte_errno set.
15443 : : */
15444 : : static __rte_unused int
15445 : 0 : flow_hw_create_ctrl_flow(struct rte_eth_dev *owner_dev,
15446 : : struct rte_eth_dev *proxy_dev,
15447 : : struct rte_flow_template_table *table,
15448 : : struct rte_flow_item items[],
15449 : : uint8_t item_template_idx,
15450 : : struct rte_flow_action actions[],
15451 : : uint8_t action_template_idx,
15452 : : struct mlx5_ctrl_flow_info *info,
15453 : : bool external)
15454 : : {
15455 : 0 : struct mlx5_priv *priv = proxy_dev->data->dev_private;
15456 : 0 : uint32_t queue = CTRL_QUEUE_ID(priv);
15457 : 0 : struct rte_flow_op_attr op_attr = {
15458 : : .postpone = 0,
15459 : : };
15460 : : struct rte_flow *flow = NULL;
15461 : : struct mlx5_ctrl_flow_entry *entry = NULL;
15462 : : int ret;
15463 : :
15464 : 0 : rte_spinlock_lock(&priv->hw_ctrl_lock);
15465 : 0 : entry = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_SYS, sizeof(*entry),
15466 : : 0, SOCKET_ID_ANY);
15467 [ # # ]: 0 : if (!entry) {
15468 : 0 : DRV_LOG(ERR, "port %u not enough memory to create control flows",
15469 : : proxy_dev->data->port_id);
15470 : 0 : rte_errno = ENOMEM;
15471 : : ret = -rte_errno;
15472 : 0 : goto error;
15473 : : }
15474 : 0 : flow = flow_hw_async_flow_create(proxy_dev, queue, &op_attr, table,
15475 : : items, item_template_idx,
15476 : : actions, action_template_idx,
15477 : : NULL, NULL);
15478 [ # # ]: 0 : if (!flow) {
15479 : 0 : DRV_LOG(ERR, "port %u failed to enqueue create control"
15480 : : " flow operation", proxy_dev->data->port_id);
15481 : 0 : ret = -rte_errno;
15482 : 0 : goto error;
15483 : : }
15484 : 0 : ret = __flow_hw_pull_comp(proxy_dev, queue, NULL);
15485 [ # # ]: 0 : if (ret) {
15486 : 0 : DRV_LOG(ERR, "port %u failed to insert control flow",
15487 : : proxy_dev->data->port_id);
15488 : 0 : rte_errno = EINVAL;
15489 : : ret = -rte_errno;
15490 : 0 : goto error;
15491 : : }
15492 : 0 : entry->owner_dev = owner_dev;
15493 : 0 : entry->flow = flow;
15494 [ # # ]: 0 : if (info)
15495 : 0 : entry->info = *info;
15496 : : else
15497 : 0 : entry->info.type = MLX5_CTRL_FLOW_TYPE_GENERAL;
15498 [ # # ]: 0 : if (external)
15499 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->hw_ext_ctrl_flows, entry, next);
15500 : : else
15501 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->hw_ctrl_flows, entry, next);
15502 : : rte_spinlock_unlock(&priv->hw_ctrl_lock);
15503 : 0 : return 0;
15504 : 0 : error:
15505 [ # # ]: 0 : if (entry)
15506 : 0 : mlx5_free(entry);
15507 : : rte_spinlock_unlock(&priv->hw_ctrl_lock);
15508 : 0 : return ret;
15509 : : }
15510 : :
15511 : : /**
15512 : : * Destroys a control flow @p flow using flow template API on @p dev device.
15513 : : *
15514 : : * This function uses locks internally to synchronize access to the
15515 : : * flow queue.
15516 : : *
15517 : : * If the @p flow is stored on any private list/pool, then caller must free up
15518 : : * the relevant resources.
15519 : : *
15520 : : * @param dev
15521 : : * Pointer to Ethernet device.
15522 : : * @param flow
15523 : : * Pointer to flow rule.
15524 : : *
15525 : : * @return
15526 : : * 0 on success, non-zero value otherwise.
15527 : : */
15528 : : static int
15529 : 0 : flow_hw_destroy_ctrl_flow(struct rte_eth_dev *dev, struct rte_flow *flow)
15530 : : {
15531 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
15532 : 0 : uint32_t queue = CTRL_QUEUE_ID(priv);
15533 : 0 : struct rte_flow_op_attr op_attr = {
15534 : : .postpone = 0,
15535 : : };
15536 : : int ret;
15537 : :
15538 : 0 : rte_spinlock_lock(&priv->hw_ctrl_lock);
15539 : 0 : ret = flow_hw_async_flow_destroy(dev, queue, &op_attr, flow, NULL, NULL);
15540 [ # # ]: 0 : if (ret) {
15541 : 0 : DRV_LOG(ERR, "port %u failed to enqueue destroy control"
15542 : : " flow operation", dev->data->port_id);
15543 : 0 : goto exit;
15544 : : }
15545 : 0 : ret = __flow_hw_pull_comp(dev, queue, NULL);
15546 [ # # ]: 0 : if (ret) {
15547 : 0 : DRV_LOG(ERR, "port %u failed to destroy control flow",
15548 : : dev->data->port_id);
15549 : 0 : rte_errno = EINVAL;
15550 : : ret = -rte_errno;
15551 : 0 : goto exit;
15552 : : }
15553 : 0 : exit:
15554 : : rte_spinlock_unlock(&priv->hw_ctrl_lock);
15555 : 0 : return ret;
15556 : : }
15557 : :
15558 : : /**
15559 : : * Destroys control flows created on behalf of @p owner device on @p dev device.
15560 : : *
15561 : : * @param dev
15562 : : * Pointer to Ethernet device on which control flows were created.
15563 : : * @param owner
15564 : : * Pointer to Ethernet device owning control flows.
15565 : : *
15566 : : * @return
15567 : : * 0 on success, otherwise negative error code is returned and
15568 : : * rte_errno is set.
15569 : : */
15570 : : static int
15571 : 0 : flow_hw_flush_ctrl_flows_owned_by(struct rte_eth_dev *dev, struct rte_eth_dev *owner)
15572 : : {
15573 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
15574 : : struct mlx5_ctrl_flow_entry *cf;
15575 : : struct mlx5_ctrl_flow_entry *cf_next;
15576 : : int ret;
15577 : :
15578 : 0 : cf = LIST_FIRST(&priv->hw_ctrl_flows);
15579 [ # # ]: 0 : while (cf != NULL) {
15580 : 0 : cf_next = LIST_NEXT(cf, next);
15581 [ # # ]: 0 : if (cf->owner_dev == owner) {
15582 : 0 : ret = flow_hw_destroy_ctrl_flow(dev, cf->flow);
15583 [ # # ]: 0 : if (ret) {
15584 : 0 : rte_errno = ret;
15585 : 0 : return -ret;
15586 : : }
15587 [ # # ]: 0 : LIST_REMOVE(cf, next);
15588 : 0 : mlx5_free(cf);
15589 : : }
15590 : : cf = cf_next;
15591 : : }
15592 : : return 0;
15593 : : }
15594 : :
15595 : : /**
15596 : : * Destroys control flows created for @p owner_dev device.
15597 : : *
15598 : : * @param owner_dev
15599 : : * Pointer to Ethernet device owning control flows.
15600 : : *
15601 : : * @return
15602 : : * 0 on success, otherwise negative error code is returned and
15603 : : * rte_errno is set.
15604 : : */
15605 : : int
15606 : 0 : mlx5_flow_hw_flush_ctrl_flows(struct rte_eth_dev *owner_dev)
15607 : : {
15608 : 0 : struct mlx5_priv *owner_priv = owner_dev->data->dev_private;
15609 : : struct rte_eth_dev *proxy_dev;
15610 : 0 : uint16_t owner_port_id = owner_dev->data->port_id;
15611 : 0 : uint16_t proxy_port_id = owner_dev->data->port_id;
15612 : : int ret;
15613 : :
15614 : : /* Flush all flows created by this port for itself. */
15615 : 0 : ret = flow_hw_flush_ctrl_flows_owned_by(owner_dev, owner_dev);
15616 [ # # ]: 0 : if (ret)
15617 : : return ret;
15618 : : /* Flush all flows created for this port on proxy port. */
15619 [ # # ]: 0 : if (owner_priv->sh->config.dv_esw_en) {
15620 : 0 : ret = rte_flow_pick_transfer_proxy(owner_port_id, &proxy_port_id, NULL);
15621 [ # # ]: 0 : if (ret == -ENODEV) {
15622 : 0 : DRV_LOG(DEBUG, "Unable to find transfer proxy port for port %u. It was "
15623 : : "probably closed. Control flows were cleared.",
15624 : : owner_port_id);
15625 : 0 : rte_errno = 0;
15626 : 0 : return 0;
15627 [ # # ]: 0 : } else if (ret) {
15628 : 0 : DRV_LOG(ERR, "Unable to find proxy port for port %u (ret = %d)",
15629 : : owner_port_id, ret);
15630 : 0 : return ret;
15631 : : }
15632 : 0 : proxy_dev = &rte_eth_devices[proxy_port_id];
15633 : : } else {
15634 : : proxy_dev = owner_dev;
15635 : : }
15636 : 0 : return flow_hw_flush_ctrl_flows_owned_by(proxy_dev, owner_dev);
15637 : : }
15638 : :
15639 : : /**
15640 : : * Destroys all control flows created on @p dev device.
15641 : : *
15642 : : * @param owner_dev
15643 : : * Pointer to Ethernet device.
15644 : : *
15645 : : * @return
15646 : : * 0 on success, otherwise negative error code is returned and
15647 : : * rte_errno is set.
15648 : : */
15649 : : static int
15650 : 0 : flow_hw_flush_all_ctrl_flows(struct rte_eth_dev *dev)
15651 : : {
15652 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
15653 : : struct mlx5_ctrl_flow_entry *cf;
15654 : : struct mlx5_ctrl_flow_entry *cf_next;
15655 : : int ret;
15656 : :
15657 : 0 : cf = LIST_FIRST(&priv->hw_ctrl_flows);
15658 [ # # ]: 0 : while (cf != NULL) {
15659 : 0 : cf_next = LIST_NEXT(cf, next);
15660 : 0 : ret = flow_hw_destroy_ctrl_flow(dev, cf->flow);
15661 [ # # ]: 0 : if (ret) {
15662 : 0 : rte_errno = ret;
15663 : 0 : return -ret;
15664 : : }
15665 [ # # ]: 0 : LIST_REMOVE(cf, next);
15666 : 0 : mlx5_free(cf);
15667 : : cf = cf_next;
15668 : : }
15669 : 0 : cf = LIST_FIRST(&priv->hw_ext_ctrl_flows);
15670 [ # # ]: 0 : while (cf != NULL) {
15671 : 0 : cf_next = LIST_NEXT(cf, next);
15672 : 0 : ret = flow_hw_destroy_ctrl_flow(dev, cf->flow);
15673 [ # # ]: 0 : if (ret) {
15674 : 0 : rte_errno = ret;
15675 : 0 : return -ret;
15676 : : }
15677 [ # # ]: 0 : LIST_REMOVE(cf, next);
15678 : 0 : mlx5_free(cf);
15679 : : cf = cf_next;
15680 : : }
15681 : : return 0;
15682 : : }
15683 : :
15684 : : int
15685 : 0 : mlx5_flow_hw_esw_create_sq_miss_flow(struct rte_eth_dev *dev, uint32_t sqn, bool external)
15686 : : {
15687 : 0 : uint16_t port_id = dev->data->port_id;
15688 : 0 : struct rte_flow_item_ethdev esw_mgr_spec = {
15689 : : .port_id = MLX5_REPRESENTED_PORT_ESW_MGR,
15690 : : };
15691 : 0 : struct rte_flow_item_ethdev esw_mgr_mask = {
15692 : : .port_id = MLX5_REPRESENTED_PORT_ESW_MGR,
15693 : : };
15694 : 0 : struct rte_flow_item_tag reg_c0_spec = {
15695 : : .index = (uint8_t)REG_C_0,
15696 : : .data = flow_hw_esw_mgr_regc_marker(dev),
15697 : : };
15698 : 0 : struct rte_flow_item_tag reg_c0_mask = {
15699 : : .index = 0xff,
15700 : : .data = flow_hw_esw_mgr_regc_marker_mask(dev),
15701 : : };
15702 : 0 : struct mlx5_rte_flow_item_sq sq_spec = {
15703 : : .queue = sqn,
15704 : : };
15705 : 0 : struct rte_flow_action_ethdev port = {
15706 : : .port_id = port_id,
15707 : : };
15708 : 0 : struct rte_flow_item items[3] = { { 0 } };
15709 : 0 : struct rte_flow_action actions[3] = { { 0 } };
15710 : 0 : struct mlx5_ctrl_flow_info flow_info = {
15711 : : .type = MLX5_CTRL_FLOW_TYPE_SQ_MISS_ROOT,
15712 : : .esw_mgr_sq = sqn,
15713 : : };
15714 : : struct rte_eth_dev *proxy_dev;
15715 : : struct mlx5_priv *proxy_priv;
15716 : 0 : uint16_t proxy_port_id = dev->data->port_id;
15717 : : int ret;
15718 : :
15719 : 0 : ret = rte_flow_pick_transfer_proxy(port_id, &proxy_port_id, NULL);
15720 [ # # ]: 0 : if (ret) {
15721 : 0 : DRV_LOG(ERR, "Unable to pick transfer proxy port for port %u. Transfer proxy "
15722 : : "port must be present to create default SQ miss flows.",
15723 : : port_id);
15724 : 0 : return ret;
15725 : : }
15726 : 0 : proxy_dev = &rte_eth_devices[proxy_port_id];
15727 : 0 : proxy_priv = proxy_dev->data->dev_private;
15728 [ # # ]: 0 : if (!proxy_priv->dr_ctx) {
15729 : 0 : DRV_LOG(DEBUG, "Transfer proxy port (port %u) of port %u must be configured "
15730 : : "for HWS to create default SQ miss flows. Default flows will "
15731 : : "not be created.",
15732 : : proxy_port_id, port_id);
15733 : 0 : return 0;
15734 : : }
15735 [ # # ]: 0 : if (!proxy_priv->hw_ctrl_fdb ||
15736 [ # # ]: 0 : !proxy_priv->hw_ctrl_fdb->hw_esw_sq_miss_root_tbl ||
15737 [ # # ]: 0 : !proxy_priv->hw_ctrl_fdb->hw_esw_sq_miss_tbl) {
15738 : 0 : DRV_LOG(ERR, "Transfer proxy port (port %u) of port %u was configured, but "
15739 : : "default flow tables were not created.",
15740 : : proxy_port_id, port_id);
15741 : 0 : rte_errno = ENOMEM;
15742 : 0 : return -rte_errno;
15743 : : }
15744 : : /*
15745 : : * Create a root SQ miss flow rule - match E-Switch Manager and SQ,
15746 : : * and jump to group 1.
15747 : : */
15748 : 0 : items[0] = (struct rte_flow_item){
15749 : : .type = RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT,
15750 : : .spec = &esw_mgr_spec,
15751 : : .mask = &esw_mgr_mask,
15752 : : };
15753 : 0 : items[1] = (struct rte_flow_item){
15754 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_SQ,
15755 : : .spec = &sq_spec,
15756 : : };
15757 : 0 : items[2] = (struct rte_flow_item){
15758 : : .type = RTE_FLOW_ITEM_TYPE_END,
15759 : : };
15760 : 0 : actions[0] = (struct rte_flow_action){
15761 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
15762 : : };
15763 : 0 : actions[1] = (struct rte_flow_action){
15764 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
15765 : : };
15766 : 0 : actions[2] = (struct rte_flow_action) {
15767 : : .type = RTE_FLOW_ACTION_TYPE_END,
15768 : : };
15769 : 0 : ret = flow_hw_create_ctrl_flow(dev, proxy_dev,
15770 : : proxy_priv->hw_ctrl_fdb->hw_esw_sq_miss_root_tbl,
15771 : : items, 0, actions, 0, &flow_info, external);
15772 [ # # ]: 0 : if (ret) {
15773 : 0 : DRV_LOG(ERR, "Port %u failed to create root SQ miss flow rule for SQ %u, ret %d",
15774 : : port_id, sqn, ret);
15775 : 0 : return ret;
15776 : : }
15777 : : /*
15778 : : * Create a non-root SQ miss flow rule - match REG_C_0 marker and SQ,
15779 : : * and forward to port.
15780 : : */
15781 : 0 : items[0] = (struct rte_flow_item){
15782 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_TAG,
15783 : : .spec = ®_c0_spec,
15784 : : .mask = ®_c0_mask,
15785 : : };
15786 : 0 : items[1] = (struct rte_flow_item){
15787 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_SQ,
15788 : : .spec = &sq_spec,
15789 : : };
15790 : 0 : items[2] = (struct rte_flow_item){
15791 : : .type = RTE_FLOW_ITEM_TYPE_END,
15792 : : };
15793 : 0 : actions[0] = (struct rte_flow_action){
15794 : : .type = RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT,
15795 : : .conf = &port,
15796 : : };
15797 : 0 : actions[1] = (struct rte_flow_action){
15798 : : .type = RTE_FLOW_ACTION_TYPE_END,
15799 : : };
15800 : 0 : flow_info.type = MLX5_CTRL_FLOW_TYPE_SQ_MISS;
15801 : 0 : ret = flow_hw_create_ctrl_flow(dev, proxy_dev,
15802 : 0 : proxy_priv->hw_ctrl_fdb->hw_esw_sq_miss_tbl,
15803 : : items, 0, actions, 0, &flow_info, external);
15804 [ # # ]: 0 : if (ret) {
15805 : 0 : DRV_LOG(ERR, "Port %u failed to create HWS SQ miss flow rule for SQ %u, ret %d",
15806 : : port_id, sqn, ret);
15807 : 0 : return ret;
15808 : : }
15809 : : return 0;
15810 : : }
15811 : :
15812 : : static bool
15813 : : flow_hw_is_matching_sq_miss_flow(struct mlx5_ctrl_flow_entry *cf,
15814 : : struct rte_eth_dev *dev,
15815 : : uint32_t sqn)
15816 : : {
15817 : 0 : if (cf->owner_dev != dev)
15818 : : return false;
15819 [ # # # # ]: 0 : if (cf->info.type == MLX5_CTRL_FLOW_TYPE_SQ_MISS_ROOT && cf->info.esw_mgr_sq == sqn)
15820 : : return true;
15821 [ # # # # ]: 0 : if (cf->info.type == MLX5_CTRL_FLOW_TYPE_SQ_MISS && cf->info.esw_mgr_sq == sqn)
15822 : : return true;
15823 : : return false;
15824 : : }
15825 : :
15826 : : int
15827 : 0 : mlx5_flow_hw_esw_destroy_sq_miss_flow(struct rte_eth_dev *dev, uint32_t sqn)
15828 : : {
15829 : 0 : uint16_t port_id = dev->data->port_id;
15830 : 0 : uint16_t proxy_port_id = dev->data->port_id;
15831 : : struct rte_eth_dev *proxy_dev;
15832 : : struct mlx5_priv *proxy_priv;
15833 : : struct mlx5_ctrl_flow_entry *cf;
15834 : : struct mlx5_ctrl_flow_entry *cf_next;
15835 : : int ret;
15836 : :
15837 : 0 : ret = rte_flow_pick_transfer_proxy(port_id, &proxy_port_id, NULL);
15838 [ # # ]: 0 : if (ret) {
15839 : 0 : DRV_LOG(ERR, "Unable to pick transfer proxy port for port %u. Transfer proxy "
15840 : : "port must be present for default SQ miss flow rules to exist.",
15841 : : port_id);
15842 : 0 : return ret;
15843 : : }
15844 : 0 : proxy_dev = &rte_eth_devices[proxy_port_id];
15845 : 0 : proxy_priv = proxy_dev->data->dev_private;
15846 : : /* FDB default flow rules must be enabled. */
15847 : : MLX5_ASSERT(proxy_priv->sh->config.fdb_def_rule);
15848 [ # # ]: 0 : if (!proxy_priv->dr_ctx)
15849 : : return 0;
15850 [ # # ]: 0 : if (!proxy_priv->hw_ctrl_fdb ||
15851 [ # # ]: 0 : !proxy_priv->hw_ctrl_fdb->hw_esw_sq_miss_root_tbl ||
15852 [ # # ]: 0 : !proxy_priv->hw_ctrl_fdb->hw_esw_sq_miss_tbl)
15853 : : return 0;
15854 : 0 : cf = LIST_FIRST(&proxy_priv->hw_ctrl_flows);
15855 [ # # ]: 0 : while (cf != NULL) {
15856 [ # # ]: 0 : cf_next = LIST_NEXT(cf, next);
15857 : : if (flow_hw_is_matching_sq_miss_flow(cf, dev, sqn)) {
15858 : 0 : claim_zero(flow_hw_destroy_ctrl_flow(proxy_dev, cf->flow));
15859 [ # # ]: 0 : LIST_REMOVE(cf, next);
15860 : 0 : mlx5_free(cf);
15861 : : }
15862 : : cf = cf_next;
15863 : : }
15864 : : return 0;
15865 : : }
15866 : :
15867 : : int
15868 : 0 : mlx5_flow_hw_esw_create_default_jump_flow(struct rte_eth_dev *dev)
15869 : : {
15870 : 0 : uint16_t port_id = dev->data->port_id;
15871 : 0 : struct rte_flow_item_ethdev port_spec = {
15872 : : .port_id = port_id,
15873 : : };
15874 : 0 : struct rte_flow_item items[] = {
15875 : : {
15876 : : .type = RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT,
15877 : : .spec = &port_spec,
15878 : : },
15879 : : {
15880 : : .type = RTE_FLOW_ITEM_TYPE_END,
15881 : : },
15882 : : };
15883 : 0 : struct rte_flow_action_jump jump = {
15884 : : .group = 1,
15885 : : };
15886 : 0 : struct rte_flow_action actions[] = {
15887 : : {
15888 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
15889 : : .conf = &jump,
15890 : : },
15891 : : {
15892 : : .type = RTE_FLOW_ACTION_TYPE_END,
15893 : : }
15894 : : };
15895 : 0 : struct mlx5_ctrl_flow_info flow_info = {
15896 : : .type = MLX5_CTRL_FLOW_TYPE_DEFAULT_JUMP,
15897 : : };
15898 : : struct rte_eth_dev *proxy_dev;
15899 : : struct mlx5_priv *proxy_priv;
15900 : 0 : uint16_t proxy_port_id = dev->data->port_id;
15901 : : int ret;
15902 : :
15903 : 0 : ret = rte_flow_pick_transfer_proxy(port_id, &proxy_port_id, NULL);
15904 [ # # ]: 0 : if (ret) {
15905 : 0 : DRV_LOG(ERR, "Unable to pick transfer proxy port for port %u. Transfer proxy "
15906 : : "port must be present to create default FDB jump rule.",
15907 : : port_id);
15908 : 0 : return ret;
15909 : : }
15910 : 0 : proxy_dev = &rte_eth_devices[proxy_port_id];
15911 : 0 : proxy_priv = proxy_dev->data->dev_private;
15912 : : /* FDB default flow rules must be enabled. */
15913 : : MLX5_ASSERT(proxy_priv->sh->config.fdb_def_rule);
15914 [ # # ]: 0 : if (!proxy_priv->dr_ctx) {
15915 : 0 : DRV_LOG(DEBUG, "Transfer proxy port (port %u) of port %u must be configured "
15916 : : "for HWS to create default FDB jump rule. Default rule will "
15917 : : "not be created.",
15918 : : proxy_port_id, port_id);
15919 : 0 : return 0;
15920 : : }
15921 [ # # # # ]: 0 : if (!proxy_priv->hw_ctrl_fdb || !proxy_priv->hw_ctrl_fdb->hw_esw_zero_tbl) {
15922 : 0 : DRV_LOG(ERR, "Transfer proxy port (port %u) of port %u was configured, but "
15923 : : "default flow tables were not created.",
15924 : : proxy_port_id, port_id);
15925 : 0 : rte_errno = EINVAL;
15926 : 0 : return -rte_errno;
15927 : : }
15928 : 0 : return flow_hw_create_ctrl_flow(dev, proxy_dev,
15929 : : proxy_priv->hw_ctrl_fdb->hw_esw_zero_tbl,
15930 : : items, 0, actions, 0, &flow_info, false);
15931 : : }
15932 : :
15933 : : int
15934 : 0 : mlx5_flow_hw_create_tx_default_mreg_copy_flow(struct rte_eth_dev *dev)
15935 : : {
15936 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
15937 : 0 : struct rte_flow_item_eth promisc = {
15938 : : .hdr.dst_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
15939 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
15940 : : .hdr.ether_type = 0,
15941 : : };
15942 : 0 : struct rte_flow_item eth_all[] = {
15943 : : [0] = {
15944 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
15945 : : .spec = &promisc,
15946 : : .mask = &promisc,
15947 : : },
15948 : : [1] = {
15949 : : .type = RTE_FLOW_ITEM_TYPE_END,
15950 : : },
15951 : : };
15952 : 0 : struct rte_flow_action_modify_field mreg_action = {
15953 : : .operation = RTE_FLOW_MODIFY_SET,
15954 : : .dst = {
15955 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
15956 : : .tag_index = REG_C_1,
15957 : : },
15958 : : .src = {
15959 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
15960 : : .tag_index = REG_A,
15961 : : },
15962 : : .width = 32,
15963 : : };
15964 : 0 : struct rte_flow_action copy_reg_action[] = {
15965 : : [0] = {
15966 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
15967 : : .conf = &mreg_action,
15968 : : },
15969 : : [1] = {
15970 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
15971 : : },
15972 : : [2] = {
15973 : : .type = RTE_FLOW_ACTION_TYPE_END,
15974 : : },
15975 : : };
15976 : 0 : struct mlx5_ctrl_flow_info flow_info = {
15977 : : .type = MLX5_CTRL_FLOW_TYPE_TX_META_COPY,
15978 : : };
15979 : :
15980 : : MLX5_ASSERT(priv->master);
15981 [ # # ]: 0 : if (!priv->dr_ctx ||
15982 [ # # ]: 0 : !priv->hw_ctrl_fdb ||
15983 [ # # ]: 0 : !priv->hw_ctrl_fdb->hw_tx_meta_cpy_tbl)
15984 : : return 0;
15985 : 0 : return flow_hw_create_ctrl_flow(dev, dev,
15986 : : priv->hw_ctrl_fdb->hw_tx_meta_cpy_tbl,
15987 : : eth_all, 0, copy_reg_action, 0, &flow_info, false);
15988 : : }
15989 : :
15990 : : int
15991 : 0 : mlx5_flow_hw_tx_repr_matching_flow(struct rte_eth_dev *dev, uint32_t sqn, bool external)
15992 : : {
15993 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
15994 : 0 : struct mlx5_rte_flow_item_sq sq_spec = {
15995 : : .queue = sqn,
15996 : : };
15997 : 0 : struct rte_flow_item items[] = {
15998 : : {
15999 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_SQ,
16000 : : .spec = &sq_spec,
16001 : : },
16002 : : {
16003 : : .type = RTE_FLOW_ITEM_TYPE_END,
16004 : : },
16005 : : };
16006 : : /*
16007 : : * Allocate actions array suitable for all cases - extended metadata enabled or not.
16008 : : * With extended metadata there will be an additional MODIFY_FIELD action before JUMP.
16009 : : */
16010 : 0 : struct rte_flow_action actions[] = {
16011 : : { .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD },
16012 : : { .type = RTE_FLOW_ACTION_TYPE_JUMP },
16013 : : { .type = RTE_FLOW_ACTION_TYPE_END },
16014 : : { .type = RTE_FLOW_ACTION_TYPE_END },
16015 : : };
16016 : 0 : struct mlx5_ctrl_flow_info flow_info = {
16017 : : .type = MLX5_CTRL_FLOW_TYPE_TX_REPR_MATCH,
16018 : : .tx_repr_sq = sqn,
16019 : : };
16020 : :
16021 : : /* It is assumed that caller checked for representor matching. */
16022 : : MLX5_ASSERT(priv->sh->config.repr_matching);
16023 [ # # ]: 0 : if (!priv->dr_ctx) {
16024 : 0 : DRV_LOG(DEBUG, "Port %u must be configured for HWS, before creating "
16025 : : "default egress flow rules. Omitting creation.",
16026 : : dev->data->port_id);
16027 : 0 : return 0;
16028 : : }
16029 [ # # ]: 0 : if (!priv->hw_tx_repr_tagging_tbl) {
16030 : 0 : DRV_LOG(ERR, "Port %u is configured for HWS, but table for default "
16031 : : "egress flow rules does not exist.",
16032 : : dev->data->port_id);
16033 : 0 : rte_errno = EINVAL;
16034 : 0 : return -rte_errno;
16035 : : }
16036 : : /*
16037 : : * If extended metadata mode is enabled, then an additional MODIFY_FIELD action must be
16038 : : * placed before terminating JUMP action.
16039 : : */
16040 [ # # ]: 0 : if (priv->sh->config.dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS) {
16041 : 0 : actions[1].type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD;
16042 : 0 : actions[2].type = RTE_FLOW_ACTION_TYPE_JUMP;
16043 : : }
16044 : 0 : return flow_hw_create_ctrl_flow(dev, dev, priv->hw_tx_repr_tagging_tbl,
16045 : : items, 0, actions, 0, &flow_info, external);
16046 : : }
16047 : :
16048 : : int
16049 : 0 : mlx5_flow_hw_lacp_rx_flow(struct rte_eth_dev *dev)
16050 : : {
16051 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16052 : 0 : struct rte_flow_item_eth lacp_item = {
16053 : : .type = RTE_BE16(RTE_ETHER_TYPE_SLOW),
16054 : : };
16055 : 0 : struct rte_flow_item eth_lacp[] = {
16056 : : [0] = {
16057 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
16058 : : .spec = &lacp_item,
16059 : : .mask = &lacp_item,
16060 : : },
16061 : : [1] = {
16062 : : .type = RTE_FLOW_ITEM_TYPE_END,
16063 : : },
16064 : : };
16065 : 0 : struct rte_flow_action miss_action[] = {
16066 : : [0] = {
16067 : : .type = (enum rte_flow_action_type)
16068 : : MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS,
16069 : : },
16070 : : [1] = {
16071 : : .type = RTE_FLOW_ACTION_TYPE_END,
16072 : : },
16073 : : };
16074 : 0 : struct mlx5_ctrl_flow_info flow_info = {
16075 : : .type = MLX5_CTRL_FLOW_TYPE_LACP_RX,
16076 : : };
16077 : :
16078 [ # # # # : 0 : if (!priv->dr_ctx || !priv->hw_ctrl_fdb || !priv->hw_ctrl_fdb->hw_lacp_rx_tbl)
# # ]
16079 : : return 0;
16080 : 0 : return flow_hw_create_ctrl_flow(dev, dev,
16081 : : priv->hw_ctrl_fdb->hw_lacp_rx_tbl,
16082 : : eth_lacp, 0, miss_action, 0, &flow_info, false);
16083 : : }
16084 : :
16085 : : static uint32_t
16086 : : __calc_pattern_flags(const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type)
16087 : : {
16088 : : switch (eth_pattern_type) {
16089 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL:
16090 : : return MLX5_CTRL_PROMISCUOUS;
16091 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL_MCAST:
16092 : : return MLX5_CTRL_ALL_MULTICAST;
16093 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST:
16094 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST_VLAN:
16095 : : return MLX5_CTRL_BROADCAST;
16096 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST:
16097 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST_VLAN:
16098 : : return MLX5_CTRL_IPV4_MULTICAST;
16099 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST:
16100 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST_VLAN:
16101 : : return MLX5_CTRL_IPV6_MULTICAST;
16102 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC:
16103 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN:
16104 : : return MLX5_CTRL_DMAC;
16105 : : default:
16106 : : /* Should not reach here. */
16107 : : MLX5_ASSERT(false);
16108 : : return 0;
16109 : : }
16110 : : }
16111 : :
16112 : : static uint32_t
16113 : : __calc_vlan_flags(const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type)
16114 : : {
16115 [ # # ]: 0 : switch (eth_pattern_type) {
16116 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST_VLAN:
16117 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST_VLAN:
16118 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST_VLAN:
16119 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN:
16120 : : return MLX5_CTRL_VLAN_FILTER;
16121 : 0 : default:
16122 : 0 : return 0;
16123 : : }
16124 : : }
16125 : :
16126 : : static bool
16127 [ # # ]: 0 : eth_pattern_type_is_requested(const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type,
16128 : : uint32_t flags)
16129 : : {
16130 : : uint32_t pattern_flags = __calc_pattern_flags(eth_pattern_type);
16131 : : uint32_t vlan_flags = __calc_vlan_flags(eth_pattern_type);
16132 : 0 : bool pattern_requested = !!(pattern_flags & flags);
16133 [ # # # # ]: 0 : bool consider_vlan = vlan_flags || (MLX5_CTRL_VLAN_FILTER & flags);
16134 : 0 : bool vlan_requested = !!(vlan_flags & flags);
16135 : :
16136 [ # # ]: 0 : if (consider_vlan)
16137 : 0 : return pattern_requested && vlan_requested;
16138 : : else
16139 : : return pattern_requested;
16140 : : }
16141 : :
16142 : : static bool
16143 : : rss_type_is_requested(struct mlx5_priv *priv,
16144 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
16145 : : {
16146 : 0 : struct rte_flow_actions_template *at = priv->hw_ctrl_rx->rss[rss_type];
16147 : : unsigned int i;
16148 : :
16149 [ # # # # ]: 0 : for (i = 0; at->actions[i].type != RTE_FLOW_ACTION_TYPE_END; ++i) {
16150 [ # # # # ]: 0 : if (at->actions[i].type == RTE_FLOW_ACTION_TYPE_RSS) {
16151 : 0 : const struct rte_flow_action_rss *rss = at->actions[i].conf;
16152 : 0 : uint64_t rss_types = rss->types;
16153 : :
16154 [ # # # # ]: 0 : if ((rss_types & priv->rss_conf.rss_hf) != rss_types)
16155 : : return false;
16156 : : }
16157 : : }
16158 : : return true;
16159 : : }
16160 : :
16161 : : static const struct rte_flow_item_eth *
16162 : : __get_eth_spec(const enum mlx5_flow_ctrl_rx_eth_pattern_type pattern)
16163 : : {
16164 : 0 : switch (pattern) {
16165 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL:
16166 : : return &ctrl_rx_eth_promisc_spec;
16167 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL_MCAST:
16168 : 0 : return &ctrl_rx_eth_mcast_spec;
16169 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST:
16170 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST_VLAN:
16171 : 0 : return &ctrl_rx_eth_bcast_spec;
16172 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST:
16173 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST_VLAN:
16174 : 0 : return &ctrl_rx_eth_ipv4_mcast_spec;
16175 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST:
16176 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST_VLAN:
16177 : 0 : return &ctrl_rx_eth_ipv6_mcast_spec;
16178 : 0 : default:
16179 : : /* This case should not be reached. */
16180 : : MLX5_ASSERT(false);
16181 : 0 : return NULL;
16182 : : }
16183 : : }
16184 : :
16185 : : static int
16186 [ # # # # : 0 : __flow_hw_ctrl_flows_single(struct rte_eth_dev *dev,
# # ]
16187 : : struct rte_flow_template_table *tbl,
16188 : : const enum mlx5_flow_ctrl_rx_eth_pattern_type pattern_type,
16189 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
16190 : : {
16191 : : const struct rte_flow_item_eth *eth_spec = __get_eth_spec(pattern_type);
16192 : : struct rte_flow_item items[5];
16193 : 0 : struct rte_flow_action actions[] = {
16194 : : { .type = RTE_FLOW_ACTION_TYPE_RSS },
16195 : : { .type = RTE_FLOW_ACTION_TYPE_END },
16196 : : };
16197 : 0 : struct mlx5_ctrl_flow_info flow_info = {
16198 : : .type = MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS,
16199 : : };
16200 : :
16201 [ # # ]: 0 : if (!eth_spec)
16202 : : return -EINVAL;
16203 : : memset(items, 0, sizeof(items));
16204 : 0 : items[0] = (struct rte_flow_item){
16205 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
16206 : : .spec = eth_spec,
16207 : : };
16208 [ # # # ]: 0 : items[1] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_VOID };
16209 [ # # # ]: 0 : items[2] = flow_hw_get_ctrl_rx_l3_item(rss_type);
16210 : 0 : items[3] = flow_hw_get_ctrl_rx_l4_item(rss_type);
16211 : 0 : items[4] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_END };
16212 : : /* Without VLAN filtering, only a single flow rule must be created. */
16213 : 0 : return flow_hw_create_ctrl_flow(dev, dev, tbl, items, 0, actions, 0, &flow_info, false);
16214 : : }
16215 : :
16216 : : static int
16217 : 0 : __flow_hw_ctrl_flows_single_vlan(struct rte_eth_dev *dev,
16218 : : struct rte_flow_template_table *tbl,
16219 : : const enum mlx5_flow_ctrl_rx_eth_pattern_type pattern_type,
16220 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
16221 : : {
16222 [ # # # # : 0 : struct mlx5_priv *priv = dev->data->dev_private;
# # ]
16223 : : const struct rte_flow_item_eth *eth_spec = __get_eth_spec(pattern_type);
16224 : : struct rte_flow_item items[5];
16225 : 0 : struct rte_flow_action actions[] = {
16226 : : { .type = RTE_FLOW_ACTION_TYPE_RSS },
16227 : : { .type = RTE_FLOW_ACTION_TYPE_END },
16228 : : };
16229 : 0 : struct mlx5_ctrl_flow_info flow_info = {
16230 : : .type = MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS,
16231 : : };
16232 : : unsigned int i;
16233 : :
16234 [ # # ]: 0 : if (!eth_spec)
16235 : : return -EINVAL;
16236 : : memset(items, 0, sizeof(items));
16237 : 0 : items[0] = (struct rte_flow_item){
16238 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
16239 : : .spec = eth_spec,
16240 : : };
16241 : : /* Optional VLAN for now will be VOID - will be filled later. */
16242 [ # # # ]: 0 : items[1] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_VLAN };
16243 [ # # # ]: 0 : items[2] = flow_hw_get_ctrl_rx_l3_item(rss_type);
16244 : 0 : items[3] = flow_hw_get_ctrl_rx_l4_item(rss_type);
16245 : 0 : items[4] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_END };
16246 : : /* Since VLAN filtering is done, create a single flow rule for each registered vid. */
16247 [ # # ]: 0 : for (i = 0; i < priv->vlan_filter_n; ++i) {
16248 : 0 : uint16_t vlan = priv->vlan_filter[i];
16249 : 0 : struct rte_flow_item_vlan vlan_spec = {
16250 [ # # ]: 0 : .hdr.vlan_tci = rte_cpu_to_be_16(vlan),
16251 : : };
16252 : :
16253 : 0 : items[1].spec = &vlan_spec;
16254 [ # # ]: 0 : if (flow_hw_create_ctrl_flow(dev, dev,
16255 : : tbl, items, 0, actions, 0, &flow_info, false))
16256 : 0 : return -rte_errno;
16257 : : }
16258 : : return 0;
16259 : : }
16260 : :
16261 : : static int
16262 : 0 : __flow_hw_ctrl_flows_unicast_create(struct rte_eth_dev *dev,
16263 : : struct rte_flow_template_table *tbl,
16264 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type,
16265 : : const struct rte_ether_addr *addr)
16266 : : {
16267 : 0 : struct rte_flow_item_eth eth_spec = {
16268 : : .hdr.dst_addr = *addr,
16269 : : };
16270 : : struct rte_flow_item items[5];
16271 : 0 : struct rte_flow_action actions[] = {
16272 : : { .type = RTE_FLOW_ACTION_TYPE_RSS },
16273 : : { .type = RTE_FLOW_ACTION_TYPE_END },
16274 : : };
16275 [ # # # ]: 0 : struct mlx5_ctrl_flow_info flow_info = {
16276 : : .type = MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC,
16277 : : .uc = {
16278 : : .dmac = *addr,
16279 : : },
16280 : : };
16281 : :
16282 : : memset(items, 0, sizeof(items));
16283 : 0 : items[0] = (struct rte_flow_item){
16284 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
16285 : : .spec = ð_spec,
16286 : : };
16287 [ # # # ]: 0 : items[1] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_VOID };
16288 [ # # # ]: 0 : items[2] = flow_hw_get_ctrl_rx_l3_item(rss_type);
16289 : 0 : items[3] = flow_hw_get_ctrl_rx_l4_item(rss_type);
16290 : 0 : items[4] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_END };
16291 : :
16292 [ # # ]: 0 : if (flow_hw_create_ctrl_flow(dev, dev, tbl, items, 0, actions, 0, &flow_info, false))
16293 : 0 : return -rte_errno;
16294 : :
16295 : : return 0;
16296 : : }
16297 : :
16298 : : static int
16299 : 0 : __flow_hw_ctrl_flows_unicast(struct rte_eth_dev *dev,
16300 : : struct rte_flow_template_table *tbl,
16301 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
16302 : : {
16303 : : unsigned int i;
16304 : : int ret;
16305 : :
16306 [ # # ]: 0 : for (i = 0; i < MLX5_MAX_MAC_ADDRESSES; ++i) {
16307 [ # # ]: 0 : struct rte_ether_addr *mac = &dev->data->mac_addrs[i];
16308 : :
16309 [ # # ]: 0 : if (rte_is_zero_ether_addr(mac))
16310 : 0 : continue;
16311 : :
16312 : 0 : ret = __flow_hw_ctrl_flows_unicast_create(dev, tbl, rss_type, mac);
16313 [ # # ]: 0 : if (ret < 0)
16314 : 0 : return ret;
16315 : : }
16316 : : return 0;
16317 : : }
16318 : :
16319 : : static int
16320 : 0 : __flow_hw_ctrl_flows_unicast_vlan_create(struct rte_eth_dev *dev,
16321 : : struct rte_flow_template_table *tbl,
16322 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type,
16323 : : const struct rte_ether_addr *addr,
16324 : : const uint16_t vid)
16325 : : {
16326 : 0 : struct rte_flow_item_eth eth_spec = {
16327 : : .hdr.dst_addr = *addr,
16328 : : };
16329 : 0 : struct rte_flow_item_vlan vlan_spec = {
16330 [ # # ]: 0 : .tci = rte_cpu_to_be_16(vid),
16331 : : };
16332 : : struct rte_flow_item items[5];
16333 : 0 : struct rte_flow_action actions[] = {
16334 : : { .type = RTE_FLOW_ACTION_TYPE_RSS },
16335 : : { .type = RTE_FLOW_ACTION_TYPE_END },
16336 : : };
16337 [ # # # ]: 0 : struct mlx5_ctrl_flow_info flow_info = {
16338 : : .type = MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC_VLAN,
16339 : : .uc = {
16340 : : .dmac = *addr,
16341 : : .vlan = vid,
16342 : : },
16343 : : };
16344 : :
16345 : : memset(items, 0, sizeof(items));
16346 : 0 : items[0] = (struct rte_flow_item){
16347 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
16348 : : .spec = ð_spec,
16349 : : };
16350 [ # # # ]: 0 : items[1] = (struct rte_flow_item){
16351 : : .type = RTE_FLOW_ITEM_TYPE_VLAN,
16352 : : .spec = &vlan_spec,
16353 : : };
16354 [ # # # ]: 0 : items[2] = flow_hw_get_ctrl_rx_l3_item(rss_type);
16355 : 0 : items[3] = flow_hw_get_ctrl_rx_l4_item(rss_type);
16356 : 0 : items[4] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_END };
16357 : :
16358 [ # # ]: 0 : if (flow_hw_create_ctrl_flow(dev, dev, tbl, items, 0, actions, 0, &flow_info, false))
16359 : 0 : return -rte_errno;
16360 : :
16361 : : return 0;
16362 : : }
16363 : :
16364 : : static int
16365 : 0 : __flow_hw_ctrl_flows_unicast_vlan(struct rte_eth_dev *dev,
16366 : : struct rte_flow_template_table *tbl,
16367 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
16368 : : {
16369 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16370 : : unsigned int i;
16371 : : unsigned int j;
16372 : :
16373 [ # # ]: 0 : for (i = 0; i < MLX5_MAX_MAC_ADDRESSES; ++i) {
16374 [ # # ]: 0 : struct rte_ether_addr *mac = &dev->data->mac_addrs[i];
16375 : :
16376 [ # # ]: 0 : if (rte_is_zero_ether_addr(mac))
16377 : 0 : continue;
16378 : :
16379 [ # # ]: 0 : for (j = 0; j < priv->vlan_filter_n; ++j) {
16380 : 0 : uint16_t vlan = priv->vlan_filter[j];
16381 : : int ret;
16382 : :
16383 : 0 : ret = __flow_hw_ctrl_flows_unicast_vlan_create(dev, tbl, rss_type,
16384 : : mac, vlan);
16385 [ # # ]: 0 : if (ret < 0)
16386 : 0 : return ret;
16387 : : }
16388 : : }
16389 : : return 0;
16390 : : }
16391 : :
16392 : : static int
16393 : 0 : __flow_hw_ctrl_flows(struct rte_eth_dev *dev,
16394 : : struct rte_flow_template_table *tbl,
16395 : : const enum mlx5_flow_ctrl_rx_eth_pattern_type pattern_type,
16396 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
16397 : : {
16398 [ # # # # : 0 : switch (pattern_type) {
# ]
16399 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL:
16400 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL_MCAST:
16401 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST:
16402 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST:
16403 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST:
16404 : 0 : return __flow_hw_ctrl_flows_single(dev, tbl, pattern_type, rss_type);
16405 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST_VLAN:
16406 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST_VLAN:
16407 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST_VLAN:
16408 : 0 : return __flow_hw_ctrl_flows_single_vlan(dev, tbl, pattern_type, rss_type);
16409 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC:
16410 : 0 : return __flow_hw_ctrl_flows_unicast(dev, tbl, rss_type);
16411 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN:
16412 : 0 : return __flow_hw_ctrl_flows_unicast_vlan(dev, tbl, rss_type);
16413 : 0 : default:
16414 : : /* Should not reach here. */
16415 : : MLX5_ASSERT(false);
16416 : 0 : rte_errno = EINVAL;
16417 : 0 : return -EINVAL;
16418 : : }
16419 : : }
16420 : :
16421 : :
16422 : : int
16423 : 0 : mlx5_flow_hw_ctrl_flows(struct rte_eth_dev *dev, uint32_t flags)
16424 : : {
16425 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16426 : : struct mlx5_flow_hw_ctrl_rx *hw_ctrl_rx;
16427 : : unsigned int i;
16428 : : int j;
16429 : : int ret = 0;
16430 : :
16431 : : RTE_SET_USED(priv);
16432 : : RTE_SET_USED(flags);
16433 [ # # ]: 0 : if (!priv->dr_ctx) {
16434 : 0 : DRV_LOG(DEBUG, "port %u Control flow rules will not be created. "
16435 : : "HWS needs to be configured beforehand.",
16436 : : dev->data->port_id);
16437 : 0 : return 0;
16438 : : }
16439 [ # # ]: 0 : if (!priv->hw_ctrl_rx) {
16440 : 0 : DRV_LOG(ERR, "port %u Control flow rules templates were not created.",
16441 : : dev->data->port_id);
16442 : 0 : rte_errno = EINVAL;
16443 : 0 : return -rte_errno;
16444 : : }
16445 : : hw_ctrl_rx = priv->hw_ctrl_rx;
16446 [ # # ]: 0 : for (i = 0; i < MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_MAX; ++i) {
16447 : : const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type = i;
16448 : :
16449 [ # # ]: 0 : if (!eth_pattern_type_is_requested(eth_pattern_type, flags))
16450 : 0 : continue;
16451 [ # # ]: 0 : for (j = 0; j < MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX; ++j) {
16452 : 0 : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type = j;
16453 : : struct rte_flow_actions_template *at;
16454 : : struct mlx5_flow_hw_ctrl_rx_table *tmpls = &hw_ctrl_rx->tables[i][j];
16455 : 0 : const struct mlx5_flow_template_table_cfg cfg = {
16456 : : .attr = tmpls->attr,
16457 : : .external = 0,
16458 : : };
16459 : :
16460 [ # # ]: 0 : if (!hw_ctrl_rx->rss[rss_type]) {
16461 : 0 : at = flow_hw_create_ctrl_rx_rss_template(dev, rss_type);
16462 [ # # ]: 0 : if (!at)
16463 : 0 : return -rte_errno;
16464 : 0 : hw_ctrl_rx->rss[rss_type] = at;
16465 : : } else {
16466 : 0 : at = hw_ctrl_rx->rss[rss_type];
16467 : : }
16468 [ # # ]: 0 : if (!rss_type_is_requested(priv, rss_type))
16469 : 0 : continue;
16470 [ # # ]: 0 : if (!tmpls->tbl) {
16471 : 0 : tmpls->tbl = flow_hw_table_create(dev, &cfg,
16472 : : &tmpls->pt, 1, &at, 1, NULL);
16473 [ # # ]: 0 : if (!tmpls->tbl) {
16474 : 0 : DRV_LOG(ERR, "port %u Failed to create template table "
16475 : : "for control flow rules. Unable to create "
16476 : : "control flow rules.",
16477 : : dev->data->port_id);
16478 : 0 : return -rte_errno;
16479 : : }
16480 : : }
16481 : :
16482 : 0 : ret = __flow_hw_ctrl_flows(dev, tmpls->tbl, eth_pattern_type, rss_type);
16483 [ # # ]: 0 : if (ret) {
16484 : 0 : DRV_LOG(ERR, "port %u Failed to create control flow rule.",
16485 : : dev->data->port_id);
16486 : 0 : return ret;
16487 : : }
16488 : : }
16489 : : }
16490 : : return 0;
16491 : : }
16492 : :
16493 : : static int
16494 : 0 : mlx5_flow_hw_ctrl_flow_single(struct rte_eth_dev *dev,
16495 : : const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type,
16496 : : const struct rte_ether_addr *addr,
16497 : : const uint16_t vlan)
16498 : : {
16499 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16500 : : struct mlx5_flow_hw_ctrl_rx *hw_ctrl_rx;
16501 : : unsigned int j;
16502 : : int ret = 0;
16503 : :
16504 [ # # ]: 0 : if (!priv->dr_ctx) {
16505 : 0 : DRV_LOG(DEBUG, "port %u Control flow rules will not be created. "
16506 : : "HWS needs to be configured beforehand.",
16507 : : dev->data->port_id);
16508 : 0 : return 0;
16509 : : }
16510 [ # # ]: 0 : if (!priv->hw_ctrl_rx) {
16511 : 0 : DRV_LOG(ERR, "port %u Control flow rules templates were not created.",
16512 : : dev->data->port_id);
16513 : 0 : rte_errno = EINVAL;
16514 : 0 : return -rte_errno;
16515 : : }
16516 : : hw_ctrl_rx = priv->hw_ctrl_rx;
16517 : :
16518 : : /* TODO: this part should be somehow refactored. It's common with common flow creation. */
16519 [ # # ]: 0 : for (j = 0; j < MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX; ++j) {
16520 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type = j;
16521 : : const unsigned int pti = eth_pattern_type;
16522 : : struct rte_flow_actions_template *at;
16523 : : struct mlx5_flow_hw_ctrl_rx_table *tmpls = &hw_ctrl_rx->tables[pti][j];
16524 : 0 : const struct mlx5_flow_template_table_cfg cfg = {
16525 : : .attr = tmpls->attr,
16526 : : .external = 0,
16527 : : };
16528 : :
16529 [ # # ]: 0 : if (!hw_ctrl_rx->rss[rss_type]) {
16530 : 0 : at = flow_hw_create_ctrl_rx_rss_template(dev, rss_type);
16531 [ # # ]: 0 : if (!at)
16532 : 0 : return -rte_errno;
16533 : 0 : hw_ctrl_rx->rss[rss_type] = at;
16534 : : } else {
16535 : 0 : at = hw_ctrl_rx->rss[rss_type];
16536 : : }
16537 [ # # ]: 0 : if (!rss_type_is_requested(priv, rss_type))
16538 : 0 : continue;
16539 [ # # ]: 0 : if (!tmpls->tbl) {
16540 : 0 : tmpls->tbl = flow_hw_table_create(dev, &cfg,
16541 : : &tmpls->pt, 1, &at, 1, NULL);
16542 [ # # ]: 0 : if (!tmpls->tbl) {
16543 : 0 : DRV_LOG(ERR, "port %u Failed to create template table "
16544 : : "for control flow rules. Unable to create "
16545 : : "control flow rules.",
16546 : : dev->data->port_id);
16547 : 0 : return -rte_errno;
16548 : : }
16549 : : }
16550 : :
16551 : : MLX5_ASSERT(eth_pattern_type == MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC ||
16552 : : eth_pattern_type == MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN);
16553 : :
16554 [ # # ]: 0 : if (eth_pattern_type == MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC)
16555 : 0 : ret = __flow_hw_ctrl_flows_unicast_create(dev, tmpls->tbl, rss_type, addr);
16556 : : else
16557 : 0 : ret = __flow_hw_ctrl_flows_unicast_vlan_create(dev, tmpls->tbl, rss_type,
16558 : : addr, vlan);
16559 [ # # ]: 0 : if (ret) {
16560 : 0 : DRV_LOG(ERR, "port %u Failed to create unicast control flow rule.",
16561 : : dev->data->port_id);
16562 : 0 : return ret;
16563 : : }
16564 : : }
16565 : :
16566 : : return 0;
16567 : : }
16568 : :
16569 : : int
16570 : 0 : mlx5_flow_hw_ctrl_flow_dmac(struct rte_eth_dev *dev,
16571 : : const struct rte_ether_addr *addr)
16572 : : {
16573 : 0 : return mlx5_flow_hw_ctrl_flow_single(dev, MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC,
16574 : : addr, 0);
16575 : : }
16576 : :
16577 : :
16578 : : int
16579 : 0 : mlx5_flow_hw_ctrl_flow_dmac_destroy(struct rte_eth_dev *dev,
16580 : : const struct rte_ether_addr *addr)
16581 : : {
16582 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16583 : : struct mlx5_ctrl_flow_entry *entry;
16584 : : struct mlx5_ctrl_flow_entry *tmp;
16585 : : int ret;
16586 : :
16587 : : /*
16588 : : * HWS does not have automatic RSS flow expansion,
16589 : : * so each variant of the control flow rule is a separate entry in the list.
16590 : : * In that case, the whole list must be traversed.
16591 : : */
16592 : 0 : entry = LIST_FIRST(&priv->hw_ctrl_flows);
16593 [ # # ]: 0 : while (entry != NULL) {
16594 : 0 : tmp = LIST_NEXT(entry, next);
16595 : :
16596 [ # # # # ]: 0 : if (entry->info.type != MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC ||
16597 : : !rte_is_same_ether_addr(addr, &entry->info.uc.dmac)) {
16598 : : entry = tmp;
16599 : 0 : continue;
16600 : : }
16601 : :
16602 : 0 : ret = flow_hw_destroy_ctrl_flow(dev, entry->flow);
16603 [ # # ]: 0 : LIST_REMOVE(entry, next);
16604 : 0 : mlx5_free(entry);
16605 [ # # ]: 0 : if (ret)
16606 : 0 : return ret;
16607 : :
16608 : : entry = tmp;
16609 : : }
16610 : : return 0;
16611 : : }
16612 : :
16613 : : int
16614 : 0 : mlx5_flow_hw_ctrl_flow_dmac_vlan(struct rte_eth_dev *dev,
16615 : : const struct rte_ether_addr *addr,
16616 : : const uint16_t vlan)
16617 : : {
16618 : 0 : return mlx5_flow_hw_ctrl_flow_single(dev, MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN,
16619 : : addr, vlan);
16620 : : }
16621 : :
16622 : : int
16623 : 0 : mlx5_flow_hw_ctrl_flow_dmac_vlan_destroy(struct rte_eth_dev *dev,
16624 : : const struct rte_ether_addr *addr,
16625 : : const uint16_t vlan)
16626 : : {
16627 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16628 : : struct mlx5_ctrl_flow_entry *entry;
16629 : : struct mlx5_ctrl_flow_entry *tmp;
16630 : : int ret;
16631 : :
16632 : : /*
16633 : : * HWS does not have automatic RSS flow expansion,
16634 : : * so each variant of the control flow rule is a separate entry in the list.
16635 : : * In that case, the whole list must be traversed.
16636 : : */
16637 : 0 : entry = LIST_FIRST(&priv->hw_ctrl_flows);
16638 [ # # ]: 0 : while (entry != NULL) {
16639 : 0 : tmp = LIST_NEXT(entry, next);
16640 : :
16641 [ # # # # ]: 0 : if (entry->info.type != MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC_VLAN ||
16642 : 0 : !rte_is_same_ether_addr(addr, &entry->info.uc.dmac) ||
16643 [ # # ]: 0 : vlan != entry->info.uc.vlan) {
16644 : : entry = tmp;
16645 : 0 : continue;
16646 : : }
16647 : :
16648 : 0 : ret = flow_hw_destroy_ctrl_flow(dev, entry->flow);
16649 [ # # ]: 0 : LIST_REMOVE(entry, next);
16650 : 0 : mlx5_free(entry);
16651 [ # # ]: 0 : if (ret)
16652 : 0 : return ret;
16653 : :
16654 : : entry = tmp;
16655 : : }
16656 : : return 0;
16657 : : }
16658 : :
16659 : : struct mlx5_ecpri_parser_profile *
16660 : 0 : flow_hw_get_ecpri_parser_profile(void *dr_ctx)
16661 : : {
16662 : : uint16_t port_id;
16663 : : bool found = false;
16664 : : struct mlx5_priv *priv;
16665 : :
16666 [ # # ]: 0 : MLX5_ETH_FOREACH_DEV(port_id, NULL) {
16667 : 0 : priv = rte_eth_devices[port_id].data->dev_private;
16668 [ # # ]: 0 : if (priv->dr_ctx == dr_ctx) {
16669 : : found = true;
16670 : : break;
16671 : : }
16672 : : }
16673 [ # # ]: 0 : if (found)
16674 : 0 : return &priv->sh->ecpri_parser;
16675 : 0 : rte_errno = ENODEV;
16676 : 0 : return NULL;
16677 : : }
16678 : :
16679 : :
16680 : : static __rte_always_inline uint32_t
16681 : : mlx5_reformat_domain_to_tbl_type(const struct rte_flow_indir_action_conf *domain,
16682 : : bool fdb_unified_en)
16683 : : {
16684 : : uint32_t tbl_type;
16685 : :
16686 [ # # ]: 0 : if (domain->transfer)
16687 : : tbl_type = (fdb_unified_en ?
16688 : : (MLX5DR_ACTION_FLAG_HWS_FDB_RX |
16689 : : MLX5DR_ACTION_FLAG_HWS_FDB_TX |
16690 [ # # ]: 0 : MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED) :
16691 : : MLX5DR_ACTION_FLAG_HWS_FDB);
16692 [ # # ]: 0 : else if (domain->egress)
16693 : : tbl_type = MLX5DR_ACTION_FLAG_HWS_TX;
16694 [ # # ]: 0 : else if (domain->ingress)
16695 : : tbl_type = MLX5DR_ACTION_FLAG_HWS_RX;
16696 : : else
16697 : : tbl_type = UINT32_MAX;
16698 : : return tbl_type;
16699 : : }
16700 : :
16701 : : static struct mlx5_hw_encap_decap_action *
16702 : 0 : __mlx5_reformat_create(struct rte_eth_dev *dev,
16703 : : const struct rte_flow_action_raw_encap *encap_conf,
16704 : : const struct rte_flow_indir_action_conf *domain,
16705 : : enum mlx5dr_action_type type)
16706 : : {
16707 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
16708 : : struct mlx5_hw_encap_decap_action *handle;
16709 : : struct mlx5dr_action_reformat_header hdr;
16710 : : uint32_t flags;
16711 : : bool unified_fdb = is_unified_fdb(priv);
16712 : :
16713 : : flags = mlx5_reformat_domain_to_tbl_type(domain, unified_fdb);
16714 : 0 : flags |= (uint32_t)MLX5DR_ACTION_FLAG_SHARED;
16715 [ # # ]: 0 : if (flags == UINT32_MAX) {
16716 : 0 : DRV_LOG(ERR, "Reformat: invalid indirect action configuration");
16717 : 0 : return NULL;
16718 : : }
16719 : : /* Allocate new list entry. */
16720 : 0 : handle = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*handle), 0, SOCKET_ID_ANY);
16721 [ # # ]: 0 : if (!handle) {
16722 : 0 : DRV_LOG(ERR, "Reformat: failed to allocate reformat entry");
16723 : 0 : return NULL;
16724 : : }
16725 : 0 : handle->action_type = type;
16726 [ # # ]: 0 : hdr.sz = encap_conf ? encap_conf->size : 0;
16727 [ # # ]: 0 : hdr.data = encap_conf ? encap_conf->data : NULL;
16728 : 0 : handle->action = mlx5dr_action_create_reformat(priv->dr_ctx,
16729 : : type, 1, &hdr, 0, flags);
16730 [ # # ]: 0 : if (!handle->action) {
16731 : 0 : DRV_LOG(ERR, "Reformat: failed to create reformat action");
16732 : 0 : mlx5_free(handle);
16733 : 0 : return NULL;
16734 : : }
16735 : : return handle;
16736 : : }
16737 : :
16738 : : /**
16739 : : * Create mlx5 reformat action.
16740 : : *
16741 : : * @param[in] dev
16742 : : * Pointer to rte_eth_dev structure.
16743 : : * @param[in] conf
16744 : : * Pointer to the indirect action parameters.
16745 : : * @param[in] encap_action
16746 : : * Pointer to the raw_encap action configuration.
16747 : : * @param[in] decap_action
16748 : : * Pointer to the raw_decap action configuration.
16749 : : * @param[out] error
16750 : : * Pointer to error structure.
16751 : : *
16752 : : * @return
16753 : : * A valid shared action handle in case of success, NULL otherwise and
16754 : : * rte_errno is set.
16755 : : */
16756 : : struct mlx5_hw_encap_decap_action*
16757 : 0 : mlx5_reformat_action_create(struct rte_eth_dev *dev,
16758 : : const struct rte_flow_indir_action_conf *conf,
16759 : : const struct rte_flow_action *encap_action,
16760 : : const struct rte_flow_action *decap_action,
16761 : : struct rte_flow_error *error)
16762 : : {
16763 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16764 : : struct mlx5_hw_encap_decap_action *handle;
16765 : : const struct rte_flow_action_raw_encap *encap = NULL;
16766 : : const struct rte_flow_action_raw_decap *decap = NULL;
16767 : : enum mlx5dr_action_type type = MLX5DR_ACTION_TYP_LAST;
16768 : :
16769 : : MLX5_ASSERT(!encap_action || encap_action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP);
16770 : : MLX5_ASSERT(!decap_action || decap_action->type == RTE_FLOW_ACTION_TYPE_RAW_DECAP);
16771 [ # # ]: 0 : if (priv->sh->config.dv_flow_en != 2) {
16772 : 0 : rte_flow_error_set(error, ENOTSUP,
16773 : : RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
16774 : : "Reformat: hardware does not support");
16775 : 0 : return NULL;
16776 : : }
16777 [ # # # # ]: 0 : if (!conf || (conf->transfer + conf->egress + conf->ingress != 1)) {
16778 : 0 : rte_flow_error_set(error, EINVAL,
16779 : : RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
16780 : : "Reformat: domain should be specified");
16781 : 0 : return NULL;
16782 : : }
16783 [ # # # # : 0 : if ((encap_action && !encap_action->conf) || (decap_action && !decap_action->conf)) {
# # # # ]
16784 : 0 : rte_flow_error_set(error, EINVAL,
16785 : : RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
16786 : : "Reformat: missed action configuration");
16787 : 0 : return NULL;
16788 : : }
16789 [ # # ]: 0 : if (encap_action && !decap_action) {
16790 : 0 : encap = (const struct rte_flow_action_raw_encap *)encap_action->conf;
16791 [ # # ]: 0 : if (!encap->size || encap->size > MLX5_ENCAP_MAX_LEN ||
16792 : : encap->size < MLX5_ENCAPSULATION_DECISION_SIZE) {
16793 : 0 : rte_flow_error_set(error, EINVAL,
16794 : : RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
16795 : : "Reformat: Invalid encap length");
16796 : 0 : return NULL;
16797 : : }
16798 : : type = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;
16799 [ # # ]: 0 : } else if (decap_action && !encap_action) {
16800 : 0 : decap = (const struct rte_flow_action_raw_decap *)decap_action->conf;
16801 [ # # ]: 0 : if (!decap->size || decap->size < MLX5_ENCAPSULATION_DECISION_SIZE) {
16802 : 0 : rte_flow_error_set(error, EINVAL,
16803 : : RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
16804 : : "Reformat: Invalid decap length");
16805 : 0 : return NULL;
16806 : : }
16807 : : type = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2;
16808 [ # # ]: 0 : } else if (encap_action && decap_action) {
16809 : 0 : decap = (const struct rte_flow_action_raw_decap *)decap_action->conf;
16810 : 0 : encap = (const struct rte_flow_action_raw_encap *)encap_action->conf;
16811 [ # # ]: 0 : if (decap->size < MLX5_ENCAPSULATION_DECISION_SIZE &&
16812 [ # # # # ]: 0 : encap->size >= MLX5_ENCAPSULATION_DECISION_SIZE &&
16813 : : encap->size <= MLX5_ENCAP_MAX_LEN) {
16814 : : type = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3;
16815 [ # # ]: 0 : } else if (decap->size >= MLX5_ENCAPSULATION_DECISION_SIZE &&
16816 [ # # ]: 0 : encap->size < MLX5_ENCAPSULATION_DECISION_SIZE) {
16817 : : type = MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2;
16818 : : } else {
16819 : 0 : rte_flow_error_set(error, EINVAL,
16820 : : RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
16821 : : "Reformat: Invalid decap & encap length");
16822 : 0 : return NULL;
16823 : : }
16824 [ # # ]: 0 : } else if (!encap_action && !decap_action) {
16825 : 0 : rte_flow_error_set(error, EINVAL,
16826 : : RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
16827 : : "Reformat: Invalid decap & encap configurations");
16828 : 0 : return NULL;
16829 : : }
16830 [ # # ]: 0 : if (!priv->dr_ctx) {
16831 : 0 : rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
16832 : : encap_action, "Reformat: HWS not supported");
16833 : 0 : return NULL;
16834 : : }
16835 : 0 : handle = __mlx5_reformat_create(dev, encap, conf, type);
16836 [ # # ]: 0 : if (!handle) {
16837 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
16838 : : "Reformat: failed to create indirect action");
16839 : 0 : return NULL;
16840 : : }
16841 : : return handle;
16842 : : }
16843 : :
16844 : : /**
16845 : : * Destroy the indirect reformat action.
16846 : : * Release action related resources on the NIC and the memory.
16847 : : * Lock free, (mutex should be acquired by caller).
16848 : : *
16849 : : * @param[in] dev
16850 : : * Pointer to the Ethernet device structure.
16851 : : * @param[in] handle
16852 : : * The indirect action list handle to be removed.
16853 : : * @param[out] error
16854 : : * Perform verbose error reporting if not NULL. Initialized in case of
16855 : : * error only.
16856 : : *
16857 : : * @return
16858 : : * 0 on success, otherwise negative errno value.
16859 : : */
16860 : : int
16861 : 0 : mlx5_reformat_action_destroy(struct rte_eth_dev *dev,
16862 : : struct rte_flow_action_list_handle *handle,
16863 : : struct rte_flow_error *error)
16864 : : {
16865 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16866 : : struct mlx5_hw_encap_decap_action *action;
16867 : :
16868 : : action = (struct mlx5_hw_encap_decap_action *)handle;
16869 [ # # # # ]: 0 : if (!priv->dr_ctx || !action)
16870 : 0 : return rte_flow_error_set(error, ENOTSUP,
16871 : : RTE_FLOW_ERROR_TYPE_ACTION, handle,
16872 : : "Reformat: invalid action handle");
16873 : 0 : mlx5dr_action_destroy(action->action);
16874 : 0 : mlx5_free(handle);
16875 : 0 : return 0;
16876 : : }
16877 : :
16878 : : static bool
16879 : 0 : flow_hw_is_item_masked(const struct rte_flow_item *item)
16880 : : {
16881 : : const uint8_t *byte;
16882 : : int size;
16883 : : int i;
16884 : :
16885 [ # # ]: 0 : if (item->mask == NULL)
16886 : : return false;
16887 : :
16888 [ # # ]: 0 : switch ((int)item->type) {
16889 : : case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
16890 : : size = sizeof(struct rte_flow_item_tag);
16891 : : break;
16892 : : case MLX5_RTE_FLOW_ITEM_TYPE_SQ:
16893 : : size = sizeof(struct mlx5_rte_flow_item_sq);
16894 : : break;
16895 : 0 : default:
16896 : 0 : size = rte_flow_conv(RTE_FLOW_CONV_OP_ITEM_MASK, NULL, 0, item, NULL);
16897 : : /*
16898 : : * Pattern template items are passed to this function.
16899 : : * These items were already validated, so error is not expected.
16900 : : * Also, if mask is NULL, then spec size is bigger than 0 always.
16901 : : */
16902 : : MLX5_ASSERT(size > 0);
16903 : : }
16904 : :
16905 : 0 : byte = (const uint8_t *)item->mask;
16906 [ # # ]: 0 : for (i = 0; i < size; ++i)
16907 [ # # ]: 0 : if (byte[i])
16908 : : return true;
16909 : :
16910 : : return false;
16911 : : }
16912 : :
16913 : : static int
16914 : 0 : flow_hw_validate_rule_pattern(struct rte_eth_dev *dev,
16915 : : const struct rte_flow_template_table *table,
16916 : : const uint8_t pattern_template_idx,
16917 : : const struct rte_flow_item items[],
16918 : : struct rte_flow_error *error)
16919 : : {
16920 : : const struct rte_flow_pattern_template *pt;
16921 : : const struct rte_flow_item *pt_item;
16922 : :
16923 [ # # ]: 0 : if (pattern_template_idx >= table->nb_item_templates)
16924 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
16925 : : "Pattern template index out of range");
16926 : :
16927 : 0 : pt = table->its[pattern_template_idx];
16928 : 0 : pt_item = pt->items;
16929 : :
16930 : : /* If any item was prepended, skip it. */
16931 [ # # ]: 0 : if (pt->implicit_port || pt->implicit_tag)
16932 : 0 : pt_item++;
16933 : :
16934 [ # # ]: 0 : for (; pt_item->type != RTE_FLOW_ITEM_TYPE_END; pt_item++, items++) {
16935 [ # # ]: 0 : if (pt_item->type != items->type)
16936 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM,
16937 : : items, "Item type does not match the template");
16938 : :
16939 : : /*
16940 : : * Assumptions:
16941 : : * - Currently mlx5dr layer contains info on which fields in masks are supported.
16942 : : * - This info is not exposed to PMD directly.
16943 : : * - Because of that, it is assumed that since pattern template is correct,
16944 : : * then, items' masks in pattern template have nonzero values only in
16945 : : * supported fields.
16946 : : * This is known, because a temporary mlx5dr matcher is created during pattern
16947 : : * template creation to validate the template.
16948 : : * - As a result, it is safe to look for nonzero bytes in mask to determine if
16949 : : * item spec is needed in a flow rule.
16950 : : */
16951 [ # # ]: 0 : if (!flow_hw_is_item_masked(pt_item))
16952 : 0 : continue;
16953 : :
16954 [ # # ]: 0 : if (items->spec == NULL)
16955 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
16956 : : items, "Item spec is required");
16957 : :
16958 [ # # # ]: 0 : switch (items->type) {
16959 : : const struct rte_flow_item_ethdev *ethdev;
16960 : : const struct rte_flow_item_tx_queue *tx_queue;
16961 : : struct mlx5_txq_ctrl *txq;
16962 : :
16963 : 0 : case RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT:
16964 : : ethdev = items->spec;
16965 [ # # ]: 0 : if (flow_hw_validate_target_port_id(dev, ethdev->port_id)) {
16966 : 0 : return rte_flow_error_set(error, EINVAL,
16967 : : RTE_FLOW_ERROR_TYPE_ITEM_SPEC, items,
16968 : : "Invalid port");
16969 : : }
16970 : : break;
16971 : 0 : case RTE_FLOW_ITEM_TYPE_TX_QUEUE:
16972 : : tx_queue = items->spec;
16973 [ # # # # ]: 0 : if (mlx5_is_external_txq(dev, tx_queue->tx_queue))
16974 : 0 : continue;
16975 : 0 : txq = mlx5_txq_get(dev, tx_queue->tx_queue);
16976 [ # # ]: 0 : if (!txq)
16977 : 0 : return rte_flow_error_set(error, EINVAL,
16978 : : RTE_FLOW_ERROR_TYPE_ITEM_SPEC, items,
16979 : : "Invalid Tx queue");
16980 : 0 : mlx5_txq_release(dev, tx_queue->tx_queue);
16981 : : default:
16982 : : break;
16983 : : }
16984 : : }
16985 : :
16986 : : return 0;
16987 : : }
16988 : :
16989 : : static bool
16990 : 0 : flow_hw_valid_indirect_action_type(const struct rte_flow_action *user_action,
16991 : : const enum rte_flow_action_type expected_type)
16992 : : {
16993 : 0 : uint32_t user_indirect_type = MLX5_INDIRECT_ACTION_TYPE_GET(user_action->conf);
16994 : : uint32_t expected_indirect_type;
16995 : :
16996 [ # # # # : 0 : switch ((int)expected_type) {
# # # ]
16997 : : case RTE_FLOW_ACTION_TYPE_RSS:
16998 : : case MLX5_RTE_FLOW_ACTION_TYPE_RSS:
16999 : : expected_indirect_type = MLX5_INDIRECT_ACTION_TYPE_RSS;
17000 : : break;
17001 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
17002 : : case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
17003 : : expected_indirect_type = MLX5_INDIRECT_ACTION_TYPE_COUNT;
17004 : 0 : break;
17005 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
17006 : : expected_indirect_type = MLX5_INDIRECT_ACTION_TYPE_AGE;
17007 : 0 : break;
17008 : 0 : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
17009 : : expected_indirect_type = MLX5_INDIRECT_ACTION_TYPE_CT;
17010 : 0 : break;
17011 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
17012 : : case MLX5_RTE_FLOW_ACTION_TYPE_METER_MARK:
17013 : : expected_indirect_type = MLX5_INDIRECT_ACTION_TYPE_METER_MARK;
17014 : 0 : break;
17015 : 0 : case RTE_FLOW_ACTION_TYPE_QUOTA:
17016 : : expected_indirect_type = MLX5_INDIRECT_ACTION_TYPE_QUOTA;
17017 : 0 : break;
17018 : : default:
17019 : : return false;
17020 : : }
17021 : :
17022 : 0 : return user_indirect_type == expected_indirect_type;
17023 : : }
17024 : :
17025 : : static int
17026 : 0 : flow_hw_validate_rule_actions(struct rte_eth_dev *dev,
17027 : : const struct rte_flow_template_table *table,
17028 : : const uint8_t actions_template_idx,
17029 : : const struct rte_flow_action actions[],
17030 : : struct rte_flow_error *error)
17031 : : {
17032 : : const struct rte_flow_actions_template *at;
17033 : : const struct mlx5_hw_actions *hw_acts;
17034 : : const struct mlx5_action_construct_data *act_data;
17035 : : unsigned int idx;
17036 : :
17037 [ # # ]: 0 : if (actions_template_idx >= table->nb_action_templates)
17038 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17039 : : "Actions template index out of range");
17040 : :
17041 : 0 : at = table->ats[actions_template_idx].action_template;
17042 : : hw_acts = &table->ats[actions_template_idx].acts;
17043 : :
17044 [ # # ]: 0 : for (idx = 0; actions[idx].type != RTE_FLOW_ACTION_TYPE_END; ++idx) {
17045 : : const struct rte_flow_action *user_action = &actions[idx];
17046 : 0 : const struct rte_flow_action *tmpl_action = &at->orig_actions[idx];
17047 : :
17048 [ # # ]: 0 : if (user_action->type != tmpl_action->type)
17049 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
17050 : : user_action,
17051 : : "Action type does not match type specified in "
17052 : : "actions template");
17053 : : }
17054 : :
17055 : : /*
17056 : : * Only go through unmasked actions and check if configuration is provided.
17057 : : * Configuration of masked actions is ignored.
17058 : : */
17059 [ # # ]: 0 : LIST_FOREACH(act_data, &hw_acts->act_list, next) {
17060 : : const struct rte_flow_action *user_action;
17061 : :
17062 : 0 : user_action = &actions[act_data->action_src];
17063 : :
17064 : : /* Skip actions which do not require conf. */
17065 [ # # ]: 0 : switch ((int)act_data->type) {
17066 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
17067 : : case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
17068 : : case MLX5_RTE_FLOW_ACTION_TYPE_METER_MARK:
17069 : : case MLX5_RTE_FLOW_ACTION_TYPE_RSS:
17070 : 0 : continue;
17071 : : default:
17072 : : break;
17073 : : }
17074 : :
17075 [ # # ]: 0 : if (user_action->conf == NULL)
17076 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
17077 : : user_action,
17078 : : "Action requires configuration");
17079 : :
17080 [ # # # # : 0 : switch ((int)user_action->type) {
# # ]
17081 : : enum rte_flow_action_type expected_type;
17082 : : const struct rte_flow_action_ethdev *ethdev;
17083 : : const struct rte_flow_action_modify_field *mf;
17084 : :
17085 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT:
17086 : 0 : expected_type = act_data->indirect.expected_type;
17087 [ # # ]: 0 : if (!flow_hw_valid_indirect_action_type(user_action, expected_type))
17088 : 0 : return rte_flow_error_set(error, EINVAL,
17089 : : RTE_FLOW_ERROR_TYPE_ACTION_CONF,
17090 : : user_action,
17091 : : "Indirect action type does not match "
17092 : : "the type specified in the mask");
17093 : : break;
17094 : 0 : case RTE_FLOW_ACTION_TYPE_QUEUE:
17095 [ # # ]: 0 : if (mlx5_flow_validate_target_queue(dev, user_action, error))
17096 : 0 : return -rte_errno;
17097 : : break;
17098 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
17099 [ # # ]: 0 : if (mlx5_validate_action_rss(dev, user_action, error))
17100 : 0 : return -rte_errno;
17101 : : break;
17102 : 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
17103 : : /* TODO: Compare other fields if needed. */
17104 : : mf = user_action->conf;
17105 [ # # ]: 0 : if (mf->operation != act_data->modify_header.action.operation ||
17106 [ # # ]: 0 : mf->src.field != act_data->modify_header.action.src.field ||
17107 [ # # ]: 0 : mf->dst.field != act_data->modify_header.action.dst.field ||
17108 [ # # ]: 0 : mf->width != act_data->modify_header.action.width)
17109 : 0 : return rte_flow_error_set(error, EINVAL,
17110 : : RTE_FLOW_ERROR_TYPE_ACTION_CONF,
17111 : : user_action,
17112 : : "Modify field configuration does not "
17113 : : "match configuration from actions "
17114 : : "template");
17115 : : break;
17116 : 0 : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
17117 : : ethdev = user_action->conf;
17118 [ # # ]: 0 : if (flow_hw_validate_target_port_id(dev, ethdev->port_id)) {
17119 : 0 : return rte_flow_error_set(error, EINVAL,
17120 : : RTE_FLOW_ERROR_TYPE_ACTION_CONF,
17121 : : user_action, "Invalid port");
17122 : : }
17123 : : break;
17124 : : default:
17125 : : break;
17126 : : }
17127 : : }
17128 : :
17129 : : return 0;
17130 : : }
17131 : :
17132 : : static int
17133 : 0 : flow_hw_async_op_validate(struct rte_eth_dev *dev,
17134 : : const uint32_t queue,
17135 : : const struct rte_flow_template_table *table,
17136 : : struct rte_flow_error *error)
17137 : : {
17138 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
17139 : :
17140 : : MLX5_ASSERT(table != NULL);
17141 : :
17142 [ # # # # ]: 0 : if (table->cfg.external && queue >= priv->hw_attr->nb_queue)
17143 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17144 : : "Incorrect queue");
17145 : :
17146 : : return 0;
17147 : : }
17148 : :
17149 : : /**
17150 : : * Validate user input for rte_flow_async_create() implementation.
17151 : : *
17152 : : * If RTE_LIBRTE_MLX5_DEBUG macro is not defined, this function is a no-op.
17153 : : *
17154 : : * @param[in] dev
17155 : : * Pointer to the rte_eth_dev structure.
17156 : : * @param[in] queue
17157 : : * The queue to create the flow.
17158 : : * @param[in] table
17159 : : * Pointer to template table.
17160 : : * @param[in] rule_index
17161 : : * The item pattern flow follows from the table.
17162 : : * @param[in] items
17163 : : * Items with flow spec value.
17164 : : * @param[in] pattern_template_index
17165 : : * The item pattern flow follows from the table.
17166 : : * @param[in] actions
17167 : : * Action with flow spec value.
17168 : : * @param[in] action_template_index
17169 : : * The action pattern flow follows from the table.
17170 : : * @param[out] error
17171 : : * Pointer to error structure.
17172 : : *
17173 : : * @return
17174 : : * 0 if user input is valid.
17175 : : * Negative errno otherwise, rte_errno and error struct is populated.
17176 : : */
17177 : : static int
17178 : 0 : flow_hw_async_create_validate(struct rte_eth_dev *dev,
17179 : : const uint32_t queue,
17180 : : const struct rte_flow_template_table *table,
17181 : : enum rte_flow_table_insertion_type insertion_type,
17182 : : uint32_t rule_index,
17183 : : const struct rte_flow_item items[],
17184 : : const uint8_t pattern_template_index,
17185 : : const struct rte_flow_action actions[],
17186 : : const uint8_t action_template_index,
17187 : : struct rte_flow_error *error)
17188 : : {
17189 [ # # ]: 0 : if (flow_hw_async_op_validate(dev, queue, table, error))
17190 : 0 : return -rte_errno;
17191 : :
17192 [ # # ]: 0 : if (insertion_type != table->cfg.attr.insertion_type)
17193 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
17194 : : NULL, "Flow rule insertion type mismatch with table configuration");
17195 : :
17196 [ # # ]: 0 : if (table->cfg.attr.insertion_type != RTE_FLOW_TABLE_INSERTION_TYPE_PATTERN)
17197 [ # # ]: 0 : if (rule_index >= table->cfg.attr.nb_flows)
17198 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
17199 : : NULL, "Flow rule index exceeds table size");
17200 : :
17201 [ # # ]: 0 : if (table->cfg.attr.insertion_type != RTE_FLOW_TABLE_INSERTION_TYPE_INDEX)
17202 [ # # ]: 0 : if (flow_hw_validate_rule_pattern(dev, table, pattern_template_index, items, error))
17203 : 0 : return -rte_errno;
17204 : :
17205 [ # # ]: 0 : if (flow_hw_validate_rule_actions(dev, table, action_template_index, actions, error))
17206 : 0 : return -rte_errno;
17207 : :
17208 : : return 0;
17209 : : }
17210 : :
17211 : : /**
17212 : : * Validate user input for rte_flow_async_update() implementation.
17213 : : *
17214 : : * If RTE_LIBRTE_MLX5_DEBUG macro is not defined, this function is a no-op.
17215 : : *
17216 : : * @param[in] dev
17217 : : * Pointer to the rte_eth_dev structure.
17218 : : * @param[in] queue
17219 : : * The queue to create the flow.
17220 : : * @param[in] flow
17221 : : * Flow rule to be updated.
17222 : : * @param[in] actions
17223 : : * Action with flow spec value.
17224 : : * @param[in] action_template_index
17225 : : * The action pattern flow follows from the table.
17226 : : * @param[out] error
17227 : : * Pointer to error structure.
17228 : : *
17229 : : * @return
17230 : : * 0 if user input is valid.
17231 : : * Negative errno otherwise, rte_errno and error struct is set.
17232 : : */
17233 : : static int
17234 : 0 : flow_hw_async_update_validate(struct rte_eth_dev *dev,
17235 : : const uint32_t queue,
17236 : : const struct rte_flow_hw *flow,
17237 : : const struct rte_flow_action actions[],
17238 : : const uint8_t action_template_index,
17239 : : struct rte_flow_error *error)
17240 : : {
17241 [ # # ]: 0 : if (flow_hw_async_op_validate(dev, queue, flow->table, error))
17242 : 0 : return -rte_errno;
17243 : :
17244 [ # # ]: 0 : if (flow_hw_validate_rule_actions(dev, flow->table, action_template_index, actions, error))
17245 : 0 : return -rte_errno;
17246 : :
17247 : : return 0;
17248 : : }
17249 : :
17250 : : /**
17251 : : * Validate user input for rte_flow_async_destroy() implementation.
17252 : : *
17253 : : * If RTE_LIBRTE_MLX5_DEBUG macro is not defined, this function is a no-op.
17254 : : *
17255 : : * @param[in] dev
17256 : : * Pointer to the rte_eth_dev structure.
17257 : : * @param[in] queue
17258 : : * The queue to create the flow.
17259 : : * @param[in] flow
17260 : : * Flow rule to be destroyed.
17261 : : * @param[out] error
17262 : : * Pointer to error structure.
17263 : : *
17264 : : * @return
17265 : : * 0 if user input is valid.
17266 : : * Negative errno otherwise, rte_errno and error struct is set.
17267 : : */
17268 : : static int
17269 : : flow_hw_async_destroy_validate(struct rte_eth_dev *dev,
17270 : : const uint32_t queue,
17271 : : const struct rte_flow_hw *flow,
17272 : : struct rte_flow_error *error)
17273 : : {
17274 : : if (flow_hw_async_op_validate(dev, queue, flow->table, error))
17275 : : return -rte_errno;
17276 : :
17277 : : return 0;
17278 : : }
17279 : :
17280 : : static struct rte_flow_fp_ops mlx5_flow_hw_fp_ops = {
17281 : : .async_create = flow_hw_async_flow_create,
17282 : : .async_create_by_index = flow_hw_async_flow_create_by_index,
17283 : : .async_create_by_index_with_pattern = flow_hw_async_flow_create_by_index_with_pattern,
17284 : : .async_actions_update = flow_hw_async_flow_update,
17285 : : .async_destroy = flow_hw_async_flow_destroy,
17286 : : .push = flow_hw_push,
17287 : : .pull = flow_hw_pull,
17288 : : .async_action_handle_create = flow_hw_action_handle_create,
17289 : : .async_action_handle_destroy = flow_hw_action_handle_destroy,
17290 : : .async_action_handle_update = flow_hw_action_handle_update,
17291 : : .async_action_handle_query = flow_hw_action_handle_query,
17292 : : .async_action_handle_query_update = flow_hw_async_action_handle_query_update,
17293 : : .async_action_list_handle_create = flow_hw_async_action_list_handle_create,
17294 : : .async_action_list_handle_destroy = flow_hw_async_action_list_handle_destroy,
17295 : : .async_action_list_handle_query_update =
17296 : : flow_hw_async_action_list_handle_query_update,
17297 : : };
17298 : :
17299 : : #endif
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