Branch data Line data Source code
1 : : /* SPDX-License-Identifier: BSD-3-Clause
2 : : * Copyright (c) 2022 NVIDIA Corporation & Affiliates
3 : : */
4 : :
5 : : #include <rte_flow.h>
6 : : #include <rte_flow_driver.h>
7 : : #include <rte_stdatomic.h>
8 : :
9 : : #include <mlx5_malloc.h>
10 : :
11 : : #include "mlx5.h"
12 : : #include "mlx5_common.h"
13 : : #include "mlx5_defs.h"
14 : : #include "mlx5_flow.h"
15 : : #include "mlx5_flow_os.h"
16 : : #include "mlx5_rx.h"
17 : :
18 : : #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
19 : : #include "mlx5_hws_cnt.h"
20 : :
21 : : /** Fast path async flow API functions. */
22 : : static struct rte_flow_fp_ops mlx5_flow_hw_fp_ops;
23 : :
24 : : /*
25 : : * The default ipool threshold value indicates which per_core_cache
26 : : * value to set.
27 : : */
28 : : #define MLX5_HW_IPOOL_SIZE_THRESHOLD (1 << 19)
29 : : /* The default min local cache size. */
30 : : #define MLX5_HW_IPOOL_CACHE_MIN (1 << 9)
31 : :
32 : : /* Default push burst threshold. */
33 : : #define BURST_THR 32u
34 : :
35 : : /* Default queue to flush the flows. */
36 : : #define MLX5_DEFAULT_FLUSH_QUEUE 0
37 : :
38 : : /* Maximum number of rules in control flow tables. */
39 : : #define MLX5_HW_CTRL_FLOW_NB_RULES (4096)
40 : :
41 : : /* Lowest flow group usable by an application if group translation is done. */
42 : : #define MLX5_HW_LOWEST_USABLE_GROUP (1)
43 : :
44 : : /* Maximum group index usable by user applications for transfer flows. */
45 : : #define MLX5_HW_MAX_TRANSFER_GROUP (UINT32_MAX - 1)
46 : :
47 : : /* Maximum group index usable by user applications for egress flows. */
48 : : #define MLX5_HW_MAX_EGRESS_GROUP (UINT32_MAX - 1)
49 : :
50 : : /* Lowest priority for HW root table. */
51 : : #define MLX5_HW_LOWEST_PRIO_ROOT 15
52 : :
53 : : /* Lowest priority for HW non-root table. */
54 : : #define MLX5_HW_LOWEST_PRIO_NON_ROOT (UINT32_MAX)
55 : :
56 : : /* Priorities for Rx control flow rules. */
57 : : #define MLX5_HW_CTRL_RX_PRIO_L2 (MLX5_HW_LOWEST_PRIO_ROOT)
58 : : #define MLX5_HW_CTRL_RX_PRIO_L3 (MLX5_HW_LOWEST_PRIO_ROOT - 1)
59 : : #define MLX5_HW_CTRL_RX_PRIO_L4 (MLX5_HW_LOWEST_PRIO_ROOT - 2)
60 : :
61 : : #define MLX5_HW_VLAN_PUSH_TYPE_IDX 0
62 : : #define MLX5_HW_VLAN_PUSH_VID_IDX 1
63 : : #define MLX5_HW_VLAN_PUSH_PCP_IDX 2
64 : :
65 : : #define MLX5_MIRROR_MAX_CLONES_NUM 3
66 : : #define MLX5_MIRROR_MAX_SAMPLE_ACTIONS_LEN 4
67 : :
68 : : #define MLX5_HW_PORT_IS_PROXY(priv) \
69 : : (!!((priv)->sh->esw_mode && (priv)->master))
70 : :
71 : :
72 : : struct mlx5_indlst_legacy {
73 : : struct mlx5_indirect_list indirect;
74 : : struct rte_flow_action_handle *handle;
75 : : enum rte_flow_action_type legacy_type;
76 : : };
77 : :
78 : : #define MLX5_CONST_ENCAP_ITEM(encap_type, ptr) \
79 : : (((const struct encap_type *)(ptr))->definition)
80 : :
81 : : /**
82 : : * Returns the size of a struct with a following layout:
83 : : *
84 : : * @code{.c}
85 : : * struct rte_flow_hw {
86 : : * // rte_flow_hw fields
87 : : * uint8_t rule[mlx5dr_rule_get_handle_size()];
88 : : * };
89 : : * @endcode
90 : : *
91 : : * Such struct is used as a basic container for HW Steering flow rule.
92 : : */
93 : : static size_t
94 : : mlx5_flow_hw_entry_size(void)
95 : : {
96 : 0 : return sizeof(struct rte_flow_hw) + mlx5dr_rule_get_handle_size();
97 : : }
98 : :
99 : : /**
100 : : * Returns the size of "auxed" rte_flow_hw structure which is assumed to be laid out as follows:
101 : : *
102 : : * @code{.c}
103 : : * struct {
104 : : * struct rte_flow_hw {
105 : : * // rte_flow_hw fields
106 : : * uint8_t rule[mlx5dr_rule_get_handle_size()];
107 : : * } flow;
108 : : * struct rte_flow_hw_aux aux;
109 : : * };
110 : : * @endcode
111 : : *
112 : : * Such struct is used whenever rte_flow_hw_aux cannot be allocated separately from the rte_flow_hw
113 : : * e.g., when table is resizable.
114 : : */
115 : : static size_t
116 : : mlx5_flow_hw_auxed_entry_size(void)
117 : : {
118 : 0 : size_t rule_size = mlx5dr_rule_get_handle_size();
119 : :
120 : 0 : return sizeof(struct rte_flow_hw) + rule_size + sizeof(struct rte_flow_hw_aux);
121 : : }
122 : :
123 : : /**
124 : : * Returns a valid pointer to rte_flow_hw_aux associated with given rte_flow_hw
125 : : * depending on template table configuration.
126 : : */
127 : : static __rte_always_inline struct rte_flow_hw_aux *
128 : : mlx5_flow_hw_aux(uint16_t port_id, struct rte_flow_hw *flow)
129 : : {
130 : 0 : struct rte_flow_template_table *table = flow->table;
131 : :
132 [ # # # # : 0 : if (rte_flow_template_table_resizable(port_id, &table->cfg.attr)) {
# # # # #
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# ]
133 : 0 : size_t offset = sizeof(struct rte_flow_hw) + mlx5dr_rule_get_handle_size();
134 : :
135 : 0 : return RTE_PTR_ADD(flow, offset);
136 : : } else {
137 [ # # # # : 0 : return ((flow->nt_rule) ? flow->nt2hws->flow_aux : &table->flow_aux[flow->idx - 1]);
# # # # #
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# ]
138 : : }
139 : : }
140 : :
141 : : static __rte_always_inline void
142 : : mlx5_flow_hw_aux_set_age_idx(struct rte_flow_hw *flow,
143 : : struct rte_flow_hw_aux *aux,
144 : : uint32_t age_idx)
145 : : {
146 : : /*
147 : : * Only when creating a flow rule, the type will be set explicitly.
148 : : * Or else, it should be none in the rule update case.
149 : : */
150 [ # # # # : 0 : if (unlikely(flow->operation_type == MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE))
# # # # #
# # # # #
# # # # #
# ]
151 : 0 : aux->upd.age_idx = age_idx;
152 : : else
153 : 0 : aux->orig.age_idx = age_idx;
154 : : }
155 : :
156 : : static __rte_always_inline uint32_t
157 : : mlx5_flow_hw_aux_get_age_idx(struct rte_flow_hw *flow, struct rte_flow_hw_aux *aux)
158 : : {
159 [ # # # # : 0 : if (unlikely(flow->operation_type == MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE))
# # # # #
# # # ]
160 : 0 : return aux->upd.age_idx;
161 : : else
162 : 0 : return aux->orig.age_idx;
163 : : }
164 : :
165 : : static __rte_always_inline void
166 : : mlx5_flow_hw_aux_set_mtr_id(struct rte_flow_hw *flow,
167 : : struct rte_flow_hw_aux *aux,
168 : : uint32_t mtr_id)
169 : : {
170 [ # # # # : 0 : if (unlikely(flow->operation_type == MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE))
# # # # #
# ]
171 : 0 : aux->upd.mtr_id = mtr_id;
172 : : else
173 : 0 : aux->orig.mtr_id = mtr_id;
174 : : }
175 : :
176 : : static __rte_always_inline uint32_t
177 : : mlx5_flow_hw_aux_get_mtr_id(struct rte_flow_hw *flow, struct rte_flow_hw_aux *aux)
178 : : {
179 [ # # ]: 0 : if (unlikely(flow->operation_type == MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE))
180 : 0 : return aux->upd.mtr_id;
181 : : else
182 : 0 : return aux->orig.mtr_id;
183 : : }
184 : :
185 : : static __rte_always_inline struct mlx5_hw_q_job *
186 : : flow_hw_action_job_init(struct mlx5_priv *priv, uint32_t queue,
187 : : const struct rte_flow_action_handle *handle,
188 : : void *user_data, void *query_data,
189 : : enum mlx5_hw_job_type type,
190 : : enum mlx5_hw_indirect_type indirect_type,
191 : : struct rte_flow_error *error);
192 : : static void
193 : : flow_hw_age_count_release(struct mlx5_priv *priv, uint32_t queue, struct rte_flow_hw *flow,
194 : : struct rte_flow_error *error);
195 : :
196 : : static int
197 : : mlx5_tbl_multi_pattern_process(struct rte_eth_dev *dev,
198 : : struct rte_flow_template_table *tbl,
199 : : struct mlx5_multi_pattern_segment *segment,
200 : : uint32_t bulk_size,
201 : : struct rte_flow_error *error);
202 : : static void
203 : : mlx5_destroy_multi_pattern_segment(struct mlx5_multi_pattern_segment *segment);
204 : :
205 : : static __rte_always_inline enum mlx5_indirect_list_type
206 : : flow_hw_inlist_type_get(const struct rte_flow_action *actions);
207 : :
208 : : static int
209 : : flow_hw_allocate_actions(struct rte_eth_dev *dev,
210 : : uint64_t action_flags,
211 : : struct rte_flow_error *error);
212 : :
213 : : static int
214 : : flow_hw_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
215 : : const struct rte_flow_item items[],
216 : : const struct rte_flow_action actions[],
217 : : bool external __rte_unused, int hairpin __rte_unused,
218 : : struct rte_flow_error *error);
219 : :
220 : : bool
221 : 0 : mlx5_hw_ctx_validate(const struct rte_eth_dev *dev, struct rte_flow_error *error)
222 : : {
223 : 0 : const struct mlx5_priv *priv = dev->data->dev_private;
224 : :
225 [ # # ]: 0 : if (!priv->dr_ctx) {
226 : 0 : rte_flow_error_set(error, EINVAL,
227 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
228 : : "non-template flow engine was not configured");
229 : 0 : return false;
230 : : }
231 : : return true;
232 : : }
233 : :
234 : : static int
235 : : flow_hw_allocate_actions(struct rte_eth_dev *dev,
236 : : uint64_t action_flags,
237 : : struct rte_flow_error *error);
238 : :
239 : : static __rte_always_inline int
240 : : mlx5_multi_pattern_reformat_to_index(enum mlx5dr_action_type type)
241 : : {
242 : : switch (type) {
243 : : case MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2:
244 : : return 0;
245 : : case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2:
246 : : return 1;
247 : : case MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2:
248 : : return 2;
249 : : case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3:
250 : : return 3;
251 : : default:
252 : : break;
253 : : }
254 : : return -1;
255 : : }
256 : :
257 : : /* Include only supported reformat actions for BWC non template API. */
258 : : static __rte_always_inline int
259 : : mlx5_bwc_multi_pattern_reformat_to_index(enum mlx5dr_action_type type)
260 : : {
261 : 0 : switch (type) {
262 : : case MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2:
263 : : case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2:
264 : : case MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2:
265 : : case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3:
266 : : return mlx5_multi_pattern_reformat_to_index(type);
267 : : default:
268 : : break;
269 : : }
270 : : return -1;
271 : : }
272 : :
273 : : static __rte_always_inline enum mlx5dr_action_type
274 : : mlx5_multi_pattern_reformat_index_to_type(uint32_t ix)
275 : : {
276 : : switch (ix) {
277 : : case 0:
278 : : return MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2;
279 : : case 1:
280 : : return MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;
281 : : case 2:
282 : : return MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2;
283 : : case 3:
284 : : return MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3;
285 : : default:
286 : : break;
287 : : }
288 : : return MLX5DR_ACTION_TYP_MAX;
289 : : }
290 : :
291 : : static inline enum mlx5dr_table_type
292 : : get_mlx5dr_fdb_table_type(const struct rte_flow_attr *attr,
293 : : uint32_t specialize, bool fdb_unified_en)
294 : : {
295 [ # # # # ]: 0 : if (fdb_unified_en && !!attr->group) {
296 [ # # ]: 0 : if ((specialize & (RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_WIRE_ORIG |
297 : : RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_VPORT_ORIG)) == 0)
298 : : return MLX5DR_TABLE_TYPE_FDB_UNIFIED;
299 : : MLX5_ASSERT((specialize & (RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_WIRE_ORIG |
300 : : RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_VPORT_ORIG)) !=
301 : : (RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_WIRE_ORIG |
302 : : RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_VPORT_ORIG));
303 [ # # ]: 0 : if (specialize & RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_WIRE_ORIG)
304 : : return MLX5DR_TABLE_TYPE_FDB_RX;
305 [ # # ]: 0 : if (specialize & RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_VPORT_ORIG)
306 : 0 : return MLX5DR_TABLE_TYPE_FDB_TX;
307 : : }
308 : :
309 : : return MLX5DR_TABLE_TYPE_FDB;
310 : : }
311 : :
312 : : static inline enum mlx5dr_table_type
313 : 0 : get_mlx5dr_table_type(const struct rte_flow_attr *attr, uint32_t specialize,
314 : : bool fdb_unified_en)
315 : : {
316 : : enum mlx5dr_table_type type;
317 : :
318 [ # # ]: 0 : if (attr->transfer)
319 : : type = get_mlx5dr_fdb_table_type(attr, specialize, fdb_unified_en);
320 [ # # ]: 0 : else if (attr->egress)
321 : : type = MLX5DR_TABLE_TYPE_NIC_TX;
322 : : else
323 : : type = MLX5DR_TABLE_TYPE_NIC_RX;
324 : 0 : return type;
325 : : }
326 : :
327 : : /* Non template default queue size used for inner ctrl queue. */
328 : : #define MLX5_NT_DEFAULT_QUEUE_SIZE 32
329 : :
330 : : struct mlx5_mirror_clone {
331 : : enum rte_flow_action_type type;
332 : : void *action_ctx;
333 : : };
334 : :
335 : : struct mlx5_mirror {
336 : : struct mlx5_indirect_list indirect;
337 : : uint32_t clones_num;
338 : : struct mlx5dr_action *mirror_action;
339 : : struct mlx5_mirror_clone clone[MLX5_MIRROR_MAX_CLONES_NUM];
340 : : };
341 : :
342 : : static int flow_hw_flush_all_ctrl_flows(struct rte_eth_dev *dev);
343 : : static int flow_hw_translate_group(struct rte_eth_dev *dev,
344 : : const struct mlx5_flow_template_table_cfg *cfg,
345 : : uint32_t group,
346 : : uint32_t *table_group,
347 : : struct rte_flow_error *error);
348 : : static __rte_always_inline int
349 : : flow_hw_set_vlan_vid_construct(struct rte_eth_dev *dev,
350 : : struct mlx5_modification_cmd *mhdr_cmd,
351 : : struct mlx5_action_construct_data *act_data,
352 : : const struct mlx5_hw_actions *hw_acts,
353 : : const struct rte_flow_action *action);
354 : : static void
355 : : flow_hw_construct_quota(struct mlx5_priv *priv,
356 : : struct mlx5dr_rule_action *rule_act, uint32_t qid);
357 : :
358 : : static int
359 : : mlx5_flow_ct_init(struct rte_eth_dev *dev,
360 : : uint32_t nb_conn_tracks,
361 : : uint16_t nb_queue);
362 : :
363 : : static __rte_always_inline uint32_t flow_hw_tx_tag_regc_mask(struct rte_eth_dev *dev);
364 : : static __rte_always_inline uint32_t flow_hw_tx_tag_regc_value(struct rte_eth_dev *dev);
365 : :
366 : : static int flow_hw_async_create_validate(struct rte_eth_dev *dev,
367 : : const uint32_t queue,
368 : : const struct rte_flow_template_table *table,
369 : : enum rte_flow_table_insertion_type insertion_type,
370 : : const uint32_t rule_index,
371 : : const struct rte_flow_item items[],
372 : : const uint8_t pattern_template_index,
373 : : const struct rte_flow_action actions[],
374 : : const uint8_t action_template_index,
375 : : struct rte_flow_error *error);
376 : : static int flow_hw_async_update_validate(struct rte_eth_dev *dev,
377 : : const uint32_t queue,
378 : : const struct rte_flow_hw *flow,
379 : : const struct rte_flow_action actions[],
380 : : const uint8_t action_template_index,
381 : : struct rte_flow_error *error);
382 : : static int flow_hw_async_destroy_validate(struct rte_eth_dev *dev,
383 : : const uint32_t queue,
384 : : const struct rte_flow_hw *flow,
385 : : struct rte_flow_error *error);
386 : :
387 : : const struct mlx5_flow_driver_ops mlx5_flow_hw_drv_ops;
388 : :
389 : : /* DR action flags with different table. */
390 : : static uint32_t mlx5_hw_act_flag[MLX5_HW_ACTION_FLAG_MAX]
391 : : [MLX5DR_TABLE_TYPE_MAX] = {
392 : : {
393 : : MLX5DR_ACTION_FLAG_ROOT_RX,
394 : : MLX5DR_ACTION_FLAG_ROOT_TX,
395 : : MLX5DR_ACTION_FLAG_ROOT_FDB,
396 : : MLX5DR_ACTION_FLAG_ROOT_FDB,
397 : : MLX5DR_ACTION_FLAG_ROOT_FDB,
398 : : MLX5DR_ACTION_FLAG_ROOT_FDB,
399 : : },
400 : : {
401 : : MLX5DR_ACTION_FLAG_HWS_RX,
402 : : MLX5DR_ACTION_FLAG_HWS_TX,
403 : : MLX5DR_ACTION_FLAG_HWS_FDB,
404 : : MLX5DR_ACTION_FLAG_HWS_FDB_RX,
405 : : MLX5DR_ACTION_FLAG_HWS_FDB_TX,
406 : : MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED,
407 : : },
408 : : };
409 : :
410 : : /**
411 : : * Jump table flags.
412 : : * Can jump to FDB_RX table from FDB_RX or UNIFIED tables.
413 : : * Can jump to FDB_TX table from FDB_TX or UNIFIED tables.
414 : : * Can jump to UNIFIED table from all tables.
415 : : */
416 : : static uint32_t mlx5_hw_act_dest_table_flag[MLX5DR_TABLE_TYPE_MAX] = {
417 : : MLX5DR_ACTION_FLAG_HWS_RX,
418 : : MLX5DR_ACTION_FLAG_HWS_TX,
419 : : MLX5DR_ACTION_FLAG_HWS_FDB,
420 : : (MLX5DR_ACTION_FLAG_HWS_FDB_RX | MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED),
421 : : (MLX5DR_ACTION_FLAG_HWS_FDB_TX | MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED),
422 : : (MLX5DR_ACTION_FLAG_HWS_FDB_RX | MLX5DR_ACTION_FLAG_HWS_FDB_TX |
423 : : MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED),
424 : : };
425 : :
426 : : /* Ethernet item spec for promiscuous mode. */
427 : : static const struct rte_flow_item_eth ctrl_rx_eth_promisc_spec = {
428 : : .hdr.dst_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
429 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
430 : : .hdr.ether_type = 0,
431 : : };
432 : : /* Ethernet item mask for promiscuous mode. */
433 : : static const struct rte_flow_item_eth ctrl_rx_eth_promisc_mask = {
434 : : .hdr.dst_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
435 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
436 : : .hdr.ether_type = 0,
437 : : };
438 : :
439 : : /* Ethernet item spec for all multicast mode. */
440 : : static const struct rte_flow_item_eth ctrl_rx_eth_mcast_spec = {
441 : : .hdr.dst_addr.addr_bytes = { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 },
442 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
443 : : .hdr.ether_type = 0,
444 : : };
445 : : /* Ethernet item mask for all multicast mode. */
446 : : static const struct rte_flow_item_eth ctrl_rx_eth_mcast_mask = {
447 : : .hdr.dst_addr.addr_bytes = { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 },
448 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
449 : : .hdr.ether_type = 0,
450 : : };
451 : :
452 : : /* Ethernet item spec for IPv4 multicast traffic. */
453 : : static const struct rte_flow_item_eth ctrl_rx_eth_ipv4_mcast_spec = {
454 : : .hdr.dst_addr.addr_bytes = { 0x01, 0x00, 0x5e, 0x00, 0x00, 0x00 },
455 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
456 : : .hdr.ether_type = 0,
457 : : };
458 : : /* Ethernet item mask for IPv4 multicast traffic. */
459 : : static const struct rte_flow_item_eth ctrl_rx_eth_ipv4_mcast_mask = {
460 : : .hdr.dst_addr.addr_bytes = { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 },
461 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
462 : : .hdr.ether_type = 0,
463 : : };
464 : :
465 : : /* Ethernet item spec for IPv6 multicast traffic. */
466 : : static const struct rte_flow_item_eth ctrl_rx_eth_ipv6_mcast_spec = {
467 : : .hdr.dst_addr.addr_bytes = { 0x33, 0x33, 0x00, 0x00, 0x00, 0x00 },
468 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
469 : : .hdr.ether_type = 0,
470 : : };
471 : : /* Ethernet item mask for IPv6 multicast traffic. */
472 : : static const struct rte_flow_item_eth ctrl_rx_eth_ipv6_mcast_mask = {
473 : : .hdr.dst_addr.addr_bytes = { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 },
474 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
475 : : .hdr.ether_type = 0,
476 : : };
477 : :
478 : : /* Ethernet item mask for unicast traffic. */
479 : : static const struct rte_flow_item_eth ctrl_rx_eth_dmac_mask = {
480 : : .hdr.dst_addr.addr_bytes = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
481 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
482 : : .hdr.ether_type = 0,
483 : : };
484 : :
485 : : /* Ethernet item spec for broadcast. */
486 : : static const struct rte_flow_item_eth ctrl_rx_eth_bcast_spec = {
487 : : .hdr.dst_addr.addr_bytes = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
488 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
489 : : .hdr.ether_type = 0,
490 : : };
491 : :
492 : : static inline uint32_t
493 : : flow_hw_q_pending(struct mlx5_priv *priv, uint32_t queue)
494 : : {
495 : 0 : struct mlx5_hw_q *q = &priv->hw_q[queue];
496 : :
497 : : MLX5_ASSERT(q->size >= q->job_idx);
498 : 0 : return (q->size - q->job_idx) + q->ongoing_flow_ops;
499 : : }
500 : :
501 : : static inline void
502 : 0 : flow_hw_q_inc_flow_ops(struct mlx5_priv *priv, uint32_t queue)
503 : : {
504 : 0 : struct mlx5_hw_q *q = &priv->hw_q[queue];
505 : :
506 : 0 : q->ongoing_flow_ops++;
507 : 0 : }
508 : :
509 : : static inline void
510 : : flow_hw_q_dec_flow_ops(struct mlx5_priv *priv, uint32_t queue)
511 : : {
512 : 0 : struct mlx5_hw_q *q = &priv->hw_q[queue];
513 : :
514 : 0 : q->ongoing_flow_ops--;
515 : : }
516 : :
517 : : static inline enum mlx5dr_matcher_insert_mode
518 : : flow_hw_matcher_insert_mode_get(enum rte_flow_table_insertion_type insert_type)
519 : : {
520 : 0 : if (insert_type == RTE_FLOW_TABLE_INSERTION_TYPE_PATTERN)
521 : : return MLX5DR_MATCHER_INSERT_BY_HASH;
522 : : else
523 : 0 : return MLX5DR_MATCHER_INSERT_BY_INDEX;
524 : : }
525 : :
526 : : static inline enum mlx5dr_matcher_distribute_mode
527 : : flow_hw_matcher_distribute_mode_get(enum rte_flow_table_hash_func hash_func)
528 : : {
529 [ # # ]: 0 : if (hash_func == RTE_FLOW_TABLE_HASH_FUNC_LINEAR)
530 : : return MLX5DR_MATCHER_DISTRIBUTE_BY_LINEAR;
531 : : else
532 : 0 : return MLX5DR_MATCHER_DISTRIBUTE_BY_HASH;
533 : : }
534 : :
535 : : /**
536 : : * Set the hash fields according to the @p rss_desc information.
537 : : *
538 : : * @param[in] rss_desc
539 : : * Pointer to the mlx5_flow_rss_desc.
540 : : * @param[out] hash_fields
541 : : * Pointer to the RSS hash fields.
542 : : */
543 : : static void
544 : 0 : flow_hw_hashfields_set(struct mlx5_flow_rss_desc *rss_desc,
545 : : uint64_t *hash_fields)
546 : : {
547 : : uint64_t fields = 0;
548 : : int rss_inner = 0;
549 [ # # ]: 0 : uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
550 : :
551 : : #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
552 [ # # ]: 0 : if (rss_desc->level >= 2)
553 : : rss_inner = 1;
554 : : #endif
555 [ # # ]: 0 : if (rss_types & MLX5_IPV4_LAYER_TYPES) {
556 [ # # ]: 0 : if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
557 : : fields |= IBV_RX_HASH_SRC_IPV4;
558 [ # # ]: 0 : else if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
559 : : fields |= IBV_RX_HASH_DST_IPV4;
560 : : else
561 : : fields |= MLX5_IPV4_IBV_RX_HASH;
562 [ # # ]: 0 : } else if (rss_types & MLX5_IPV6_LAYER_TYPES) {
563 [ # # ]: 0 : if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
564 : : fields |= IBV_RX_HASH_SRC_IPV6;
565 [ # # ]: 0 : else if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
566 : : fields |= IBV_RX_HASH_DST_IPV6;
567 : : else
568 : : fields |= MLX5_IPV6_IBV_RX_HASH;
569 : : }
570 [ # # ]: 0 : if (rss_types & RTE_ETH_RSS_UDP) {
571 [ # # ]: 0 : if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
572 : 0 : fields |= IBV_RX_HASH_SRC_PORT_UDP;
573 [ # # ]: 0 : else if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
574 : 0 : fields |= IBV_RX_HASH_DST_PORT_UDP;
575 : : else
576 : 0 : fields |= MLX5_UDP_IBV_RX_HASH;
577 [ # # ]: 0 : } else if (rss_types & RTE_ETH_RSS_TCP) {
578 [ # # ]: 0 : if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
579 : 0 : fields |= IBV_RX_HASH_SRC_PORT_TCP;
580 [ # # ]: 0 : else if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
581 : 0 : fields |= IBV_RX_HASH_DST_PORT_TCP;
582 : : else
583 : 0 : fields |= MLX5_TCP_IBV_RX_HASH;
584 : : }
585 [ # # ]: 0 : if (rss_types & RTE_ETH_RSS_ESP)
586 : 0 : fields |= IBV_RX_HASH_IPSEC_SPI;
587 [ # # ]: 0 : if (rss_inner)
588 : 0 : fields |= IBV_RX_HASH_INNER;
589 : 0 : *hash_fields |= fields;
590 : 0 : }
591 : :
592 : : static uint64_t
593 : 0 : flow_hw_action_flags_get(const struct rte_flow_action actions[],
594 : : const struct rte_flow_action **qrss,
595 : : const struct rte_flow_action **mark,
596 : : int *encap_idx,
597 : : int *act_cnt,
598 : : struct rte_flow_error *error)
599 : : {
600 : : uint64_t action_flags = 0;
601 : : const struct rte_flow_action *action;
602 : : const struct rte_flow_action_raw_encap *raw_encap;
603 : : int raw_decap_idx = -1;
604 : : int action_idx;
605 : :
606 : 0 : *encap_idx = -1;
607 : : action_idx = 0;
608 [ # # ]: 0 : for (action = actions; action->type != RTE_FLOW_ACTION_TYPE_END; action++) {
609 : 0 : int type = (int)action->type;
610 [ # # # # : 0 : switch (type) {
# # # # #
# # # # #
# # # # #
# # # # #
# ]
611 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT:
612 [ # # # # : 0 : switch (MLX5_INDIRECT_ACTION_TYPE_GET(action->conf)) {
# # ]
613 : 0 : case MLX5_INDIRECT_ACTION_TYPE_RSS:
614 : 0 : goto rss;
615 : 0 : case MLX5_INDIRECT_ACTION_TYPE_AGE:
616 : 0 : goto age;
617 : 0 : case MLX5_INDIRECT_ACTION_TYPE_COUNT:
618 : 0 : goto count;
619 : 0 : case MLX5_INDIRECT_ACTION_TYPE_CT:
620 : 0 : goto ct;
621 : 0 : case MLX5_INDIRECT_ACTION_TYPE_METER_MARK:
622 : 0 : goto meter;
623 : 0 : default:
624 : 0 : goto error;
625 : : }
626 : : break;
627 : 0 : case RTE_FLOW_ACTION_TYPE_DROP:
628 : 0 : action_flags |= MLX5_FLOW_ACTION_DROP;
629 : 0 : break;
630 : 0 : case RTE_FLOW_ACTION_TYPE_FLAG:
631 : 0 : action_flags |= MLX5_FLOW_ACTION_FLAG;
632 : 0 : break;
633 : 0 : case RTE_FLOW_ACTION_TYPE_MARK:
634 : 0 : action_flags |= MLX5_FLOW_ACTION_MARK;
635 : 0 : *mark = action;
636 : 0 : break;
637 : 0 : case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
638 : 0 : action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
639 : 0 : break;
640 : 0 : case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
641 : 0 : action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
642 : 0 : break;
643 : 0 : case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
644 : 0 : action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
645 : 0 : break;
646 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP:
647 : 0 : action_flags |= MLX5_FLOW_ACTION_JUMP;
648 : 0 : break;
649 : 0 : case RTE_FLOW_ACTION_TYPE_QUEUE:
650 : 0 : action_flags |= MLX5_FLOW_ACTION_QUEUE;
651 : 0 : *qrss = action;
652 : 0 : break;
653 : : case RTE_FLOW_ACTION_TYPE_RSS:
654 : 0 : rss:
655 : 0 : action_flags |= MLX5_FLOW_ACTION_RSS;
656 : 0 : *qrss = action;
657 : 0 : break;
658 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
659 : : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
660 : 0 : action_flags |= MLX5_FLOW_ACTION_ENCAP;
661 : 0 : *encap_idx = action_idx;
662 : 0 : break;
663 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
664 : 0 : action_flags |= MLX5_FLOW_ACTION_ENCAP;
665 : 0 : raw_encap = action->conf;
666 [ # # ]: 0 : if (raw_encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
667 : 0 : *encap_idx = raw_decap_idx != -1 ?
668 [ # # ]: 0 : raw_decap_idx : action_idx;
669 : : break;
670 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
671 : : case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
672 : 0 : action_flags |= MLX5_FLOW_ACTION_DECAP;
673 : 0 : break;
674 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
675 : 0 : action_flags |= MLX5_FLOW_ACTION_DECAP;
676 : : raw_decap_idx = action_idx;
677 : 0 : break;
678 : 0 : case RTE_FLOW_ACTION_TYPE_SEND_TO_KERNEL:
679 : 0 : action_flags |= MLX5_FLOW_ACTION_SEND_TO_KERNEL;
680 : 0 : break;
681 : 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
682 : 0 : action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
683 : 0 : break;
684 : 0 : case RTE_FLOW_ACTION_TYPE_PORT_ID:
685 : : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
686 : 0 : action_flags |= MLX5_FLOW_ACTION_PORT_ID;
687 : 0 : break;
688 : : case RTE_FLOW_ACTION_TYPE_AGE:
689 : 0 : age:
690 : 0 : action_flags |= MLX5_FLOW_ACTION_AGE;
691 : 0 : break;
692 : : case RTE_FLOW_ACTION_TYPE_COUNT:
693 : 0 : count:
694 : 0 : action_flags |= MLX5_FLOW_ACTION_COUNT;
695 : 0 : break;
696 : : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
697 : 0 : ct:
698 : 0 : action_flags |= MLX5_FLOW_ACTION_CT;
699 : 0 : break;
700 : : case RTE_FLOW_ACTION_TYPE_METER_MARK:
701 : 0 : meter:
702 : 0 : action_flags |= MLX5_FLOW_ACTION_METER;
703 : 0 : break;
704 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
705 : 0 : action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
706 : 0 : break;
707 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
708 : 0 : action_flags |= MLX5_FLOW_ACTION_JUMP_TO_TABLE_INDEX;
709 : 0 : break;
710 : : case RTE_FLOW_ACTION_TYPE_VOID:
711 : : case RTE_FLOW_ACTION_TYPE_END:
712 : : break;
713 : 0 : default:
714 : 0 : goto error;
715 : : }
716 : 0 : action_idx++;
717 : : }
718 [ # # ]: 0 : if (*encap_idx == -1)
719 : 0 : *encap_idx = action_idx;
720 : 0 : action_idx++; /* The END action. */
721 : 0 : *act_cnt = action_idx;
722 : 0 : return action_flags;
723 : 0 : error:
724 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
725 : : action, "invalid flow action");
726 : 0 : return 0;
727 : : }
728 : :
729 : : /**
730 : : * Register destination table DR jump action.
731 : : *
732 : : * @param[in] dev
733 : : * Pointer to the rte_eth_dev structure.
734 : : * @param[in] table_attr
735 : : * Pointer to the flow attributes.
736 : : * @param[in] dest_group
737 : : * The destination group ID.
738 : : * @param[out] error
739 : : * Pointer to error structure.
740 : : *
741 : : * @return
742 : : * Table on success, NULL otherwise and rte_errno is set.
743 : : */
744 : : static struct mlx5_hw_jump_action *
745 : 0 : flow_hw_jump_action_register(struct rte_eth_dev *dev,
746 : : const struct mlx5_flow_template_table_cfg *cfg,
747 : : uint32_t dest_group,
748 : : struct rte_flow_error *error)
749 : : {
750 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
751 : 0 : struct rte_flow_attr jattr = cfg->attr.flow_attr;
752 : 0 : uint32_t specialize = cfg->attr.specialize;
753 : : struct mlx5_flow_group *grp;
754 : 0 : struct mlx5_flow_cb_ctx ctx = {
755 : : .dev = dev,
756 : : .error = error,
757 : : .data = &jattr,
758 : : .data2 = &specialize,
759 : : };
760 : : struct mlx5_list_entry *ge;
761 : : uint32_t target_group;
762 : :
763 : 0 : target_group = dest_group;
764 [ # # ]: 0 : if (flow_hw_translate_group(dev, cfg, dest_group, &target_group, error))
765 : : return NULL;
766 : 0 : jattr.group = target_group;
767 : 0 : ge = mlx5_hlist_register(priv->sh->flow_tbls, target_group, &ctx);
768 [ # # ]: 0 : if (!ge)
769 : : return NULL;
770 : : grp = container_of(ge, struct mlx5_flow_group, entry);
771 : 0 : return &grp->jump;
772 : : }
773 : :
774 : : /**
775 : : * Release jump action.
776 : : *
777 : : * @param[in] dev
778 : : * Pointer to the rte_eth_dev structure.
779 : : * @param[in] jump
780 : : * Pointer to the jump action.
781 : : */
782 : :
783 : : static void
784 : : flow_hw_jump_release(struct rte_eth_dev *dev, struct mlx5_hw_jump_action *jump)
785 : : {
786 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
787 : : struct mlx5_flow_group *grp;
788 : :
789 : 0 : grp = container_of(jump, struct mlx5_flow_group, jump);
790 : 0 : mlx5_hlist_unregister(priv->sh->flow_tbls, &grp->entry);
791 : 0 : }
792 : :
793 : : /**
794 : : * Register queue/RSS action.
795 : : *
796 : : * @param[in] dev
797 : : * Pointer to the rte_eth_dev structure.
798 : : * @param[in] hws_flags
799 : : * DR action flags.
800 : : * @param[in] action
801 : : * rte flow action.
802 : : * @param[in] item_flags
803 : : * Item flags for non template rule.
804 : : * @param[in] is_template
805 : : * True if it is a template rule.
806 : : *
807 : : * @return
808 : : * Table on success, NULL otherwise and rte_errno is set.
809 : : */
810 : : static inline struct mlx5_hrxq*
811 : 0 : flow_hw_tir_action_register(struct rte_eth_dev *dev,
812 : : uint32_t hws_flags,
813 : : const struct rte_flow_action *action)
814 : : {
815 : 0 : struct mlx5_flow_rss_desc rss_desc = {
816 : : .hws_flags = hws_flags,
817 : : };
818 : : struct mlx5_hrxq *hrxq;
819 : :
820 [ # # ]: 0 : if (action->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
821 : 0 : const struct rte_flow_action_queue *queue = action->conf;
822 : :
823 : 0 : rss_desc.const_q = &queue->index;
824 : 0 : rss_desc.queue_num = 1;
825 : : } else {
826 : 0 : const struct rte_flow_action_rss *rss = action->conf;
827 : :
828 : 0 : rss_desc.queue_num = rss->queue_num;
829 : 0 : rss_desc.const_q = rss->queue;
830 : 0 : memcpy(rss_desc.key,
831 [ # # ]: 0 : !rss->key ? rss_hash_default_key : rss->key,
832 : : MLX5_RSS_HASH_KEY_LEN);
833 : 0 : rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
834 [ # # ]: 0 : rss_desc.types = !rss->types ? RTE_ETH_RSS_IP : rss->types;
835 : 0 : rss_desc.symmetric_hash_function = MLX5_RSS_IS_SYMM(rss->func);
836 : 0 : flow_hw_hashfields_set(&rss_desc, &rss_desc.hash_fields);
837 : 0 : flow_dv_action_rss_l34_hash_adjust(rss->types,
838 : : &rss_desc.hash_fields);
839 [ # # ]: 0 : if (rss->level > 1) {
840 : 0 : rss_desc.hash_fields |= IBV_RX_HASH_INNER;
841 : 0 : rss_desc.tunnel = 1;
842 : : }
843 : : }
844 : 0 : hrxq = mlx5_hrxq_get(dev, &rss_desc);
845 : 0 : return hrxq;
846 : : }
847 : :
848 : : static __rte_always_inline int
849 : : flow_hw_ct_compile(struct rte_eth_dev *dev,
850 : : uint32_t queue, uint32_t idx,
851 : : struct mlx5dr_rule_action *rule_act)
852 : : {
853 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
854 : : struct mlx5_aso_ct_action *ct;
855 : :
856 : 0 : ct = mlx5_ipool_get(priv->hws_ctpool->cts, idx);
857 [ # # # # : 0 : if (!ct || (!priv->shared_host && mlx5_aso_ct_available(priv->sh, queue, ct)))
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # ]
858 : : return -1;
859 : 0 : rule_act->action = priv->hws_ctpool->dr_action;
860 : 0 : rule_act->aso_ct.offset = ct->offset;
861 : 0 : rule_act->aso_ct.direction = ct->is_original ?
862 : 0 : MLX5DR_ACTION_ASO_CT_DIRECTION_INITIATOR :
863 : : MLX5DR_ACTION_ASO_CT_DIRECTION_RESPONDER;
864 : : return 0;
865 : : }
866 : :
867 : : static void
868 : : flow_hw_template_destroy_reformat_action(struct mlx5_hw_encap_decap_action *encap_decap)
869 : : {
870 [ # # # # ]: 0 : if (encap_decap->action && !encap_decap->multi_pattern)
871 : 0 : mlx5dr_action_destroy(encap_decap->action);
872 : : }
873 : :
874 : : static void
875 : : flow_hw_template_destroy_mhdr_action(struct mlx5_hw_modify_header_action *mhdr)
876 : : {
877 [ # # # # ]: 0 : if (mhdr->action && !mhdr->multi_pattern)
878 : 0 : mlx5dr_action_destroy(mhdr->action);
879 : : }
880 : :
881 : : /**
882 : : * Destroy DR actions created by action template.
883 : : *
884 : : * For DR actions created during table creation's action translate.
885 : : * Need to destroy the DR action when destroying the table.
886 : : *
887 : : * @param[in] dev
888 : : * Pointer to the rte_eth_dev structure.
889 : : * @param[in] acts
890 : : * Pointer to the template HW steering DR actions.
891 : : */
892 : : static void
893 : 0 : __flow_hw_actions_release(struct rte_eth_dev *dev, struct mlx5_hw_actions *acts)
894 : : {
895 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
896 : :
897 [ # # ]: 0 : if (acts->mark)
898 [ # # ]: 0 : if (!(rte_atomic_fetch_sub_explicit(&priv->hws_mark_refcnt, 1,
899 : : rte_memory_order_relaxed) - 1))
900 : 0 : flow_hw_rxq_flag_set(dev, false);
901 : :
902 [ # # ]: 0 : if (acts->jump) {
903 : : struct mlx5_flow_group *grp;
904 : :
905 : 0 : grp = container_of
906 : : (acts->jump, struct mlx5_flow_group, jump);
907 : 0 : mlx5_hlist_unregister(priv->sh->flow_tbls, &grp->entry);
908 : 0 : acts->jump = NULL;
909 : : }
910 [ # # ]: 0 : if (acts->tir) {
911 : 0 : mlx5_hrxq_release(dev, acts->tir->idx);
912 : 0 : acts->tir = NULL;
913 : : }
914 [ # # ]: 0 : if (acts->encap_decap) {
915 : : flow_hw_template_destroy_reformat_action(acts->encap_decap);
916 : 0 : mlx5_free(acts->encap_decap);
917 : 0 : acts->encap_decap = NULL;
918 : : }
919 [ # # ]: 0 : if (acts->push_remove) {
920 [ # # ]: 0 : if (acts->push_remove->action)
921 : 0 : mlx5dr_action_destroy(acts->push_remove->action);
922 : 0 : mlx5_free(acts->push_remove);
923 : 0 : acts->push_remove = NULL;
924 : : }
925 [ # # ]: 0 : if (acts->mhdr) {
926 : : flow_hw_template_destroy_mhdr_action(acts->mhdr);
927 : 0 : mlx5_free(acts->mhdr);
928 : 0 : acts->mhdr = NULL;
929 : : }
930 [ # # ]: 0 : if (mlx5_hws_cnt_id_valid(acts->cnt_id)) {
931 [ # # ]: 0 : mlx5_hws_cnt_shared_put(priv->hws_cpool, &acts->cnt_id);
932 : 0 : acts->cnt_id = 0;
933 : : }
934 [ # # ]: 0 : if (acts->mtr_id) {
935 : 0 : mlx5_ipool_free(priv->hws_mpool->idx_pool, acts->mtr_id);
936 : 0 : acts->mtr_id = 0;
937 : : }
938 : 0 : }
939 : :
940 : : /**
941 : : * Release the action data back into the pool without destroy any action.
942 : : *
943 : : * @param[in] dev
944 : : * Pointer to the rte_eth_dev structure.
945 : : * @param[in] acts
946 : : * Pointer to the template HW steering DR actions.
947 : : */
948 : : static inline void
949 : 0 : __flow_hw_act_data_flush(struct rte_eth_dev *dev, struct mlx5_hw_actions *acts)
950 : : {
951 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
952 : : struct mlx5_action_construct_data *data;
953 : :
954 [ # # ]: 0 : while (!LIST_EMPTY(&acts->act_list)) {
955 : : data = LIST_FIRST(&acts->act_list);
956 [ # # ]: 0 : LIST_REMOVE(data, next);
957 : 0 : mlx5_ipool_free(priv->acts_ipool, data->idx);
958 : : }
959 : 0 : }
960 : :
961 : : /*
962 : : * Destroy DR actions created by action template.
963 : : *
964 : : * For DR actions created during table creation's action translate.
965 : : * Need to destroy the DR action when destroying the table.
966 : : *
967 : : * @param[in] dev
968 : : * Pointer to the rte_eth_dev structure.
969 : : * @param[in] acts
970 : : * Pointer to the template HW steering DR actions.
971 : : */
972 : : static void
973 : 0 : __flow_hw_action_template_destroy(struct rte_eth_dev *dev, struct mlx5_hw_actions *acts)
974 : : {
975 : 0 : __flow_hw_act_data_flush(dev, acts);
976 : 0 : __flow_hw_actions_release(dev, acts);
977 : 0 : }
978 : :
979 : : /**
980 : : * Append dynamic action to the dynamic action list.
981 : : *
982 : : * @param[in] priv
983 : : * Pointer to the port private data structure.
984 : : * @param[in] acts
985 : : * Pointer to the template HW steering DR actions.
986 : : * @param[in] type
987 : : * Action type.
988 : : * @param[in] action_src
989 : : * Offset of source rte flow action.
990 : : * @param[in] action_dst
991 : : * Offset of destination DR action.
992 : : *
993 : : * @return
994 : : * 0 on success, negative value otherwise and rte_errno is set.
995 : : */
996 : : static __rte_always_inline struct mlx5_action_construct_data *
997 : : __flow_hw_act_data_alloc(struct mlx5_priv *priv,
998 : : enum rte_flow_action_type type,
999 : : uint16_t action_src,
1000 : : uint16_t action_dst)
1001 : : {
1002 : : struct mlx5_action_construct_data *act_data;
1003 : 0 : uint32_t idx = 0;
1004 : :
1005 : 0 : act_data = mlx5_ipool_zmalloc(priv->acts_ipool, &idx);
1006 [ # # # # : 0 : if (!act_data)
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
1007 : : return NULL;
1008 : 0 : act_data->idx = idx;
1009 : 0 : act_data->type = type;
1010 : 0 : act_data->action_src = action_src;
1011 : 0 : act_data->action_dst = action_dst;
1012 : : return act_data;
1013 : : }
1014 : :
1015 : : /**
1016 : : * Append dynamic action to the dynamic action list.
1017 : : *
1018 : : * @param[in] priv
1019 : : * Pointer to the port private data structure.
1020 : : * @param[in] acts
1021 : : * Pointer to the template HW steering DR actions.
1022 : : * @param[in] type
1023 : : * Action type.
1024 : : * @param[in] action_src
1025 : : * Offset of source rte flow action.
1026 : : * @param[in] action_dst
1027 : : * Offset of destination DR action.
1028 : : *
1029 : : * @return
1030 : : * 0 on success, negative value otherwise and rte_errno is set.
1031 : : */
1032 : : static __rte_always_inline int
1033 : : __flow_hw_act_data_general_append(struct mlx5_priv *priv,
1034 : : struct mlx5_hw_actions *acts,
1035 : : enum rte_flow_action_type type,
1036 : : uint16_t action_src,
1037 : : uint16_t action_dst)
1038 : : {
1039 : : struct mlx5_action_construct_data *act_data;
1040 : :
1041 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1042 : : if (!act_data)
1043 : : return -1;
1044 [ # # # # : 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
1045 : : return 0;
1046 : : }
1047 : :
1048 : : static __rte_always_inline int
1049 : : __flow_hw_act_data_indirect_append(struct mlx5_priv *priv,
1050 : : struct mlx5_hw_actions *acts,
1051 : : enum rte_flow_action_type type,
1052 : : enum rte_flow_action_type mask_type,
1053 : : uint16_t action_src,
1054 : : uint16_t action_dst)
1055 : : {
1056 : : struct mlx5_action_construct_data *act_data;
1057 : :
1058 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1059 : : if (!act_data)
1060 : : return -1;
1061 : 0 : act_data->indirect.expected_type = mask_type;
1062 [ # # ]: 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
1063 : : return 0;
1064 : : }
1065 : :
1066 : : static __rte_always_inline int
1067 : : flow_hw_act_data_indirect_list_append(struct mlx5_priv *priv,
1068 : : struct mlx5_hw_actions *acts,
1069 : : enum rte_flow_action_type type,
1070 : : uint16_t action_src, uint16_t action_dst,
1071 : : indirect_list_callback_t cb)
1072 : : {
1073 : : struct mlx5_action_construct_data *act_data;
1074 : :
1075 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1076 : : if (!act_data)
1077 : 0 : return -1;
1078 : 0 : act_data->indirect_list_cb = cb;
1079 [ # # # # : 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
# # ]
1080 : 0 : return 0;
1081 : : }
1082 : : /**
1083 : : * Append dynamic encap action to the dynamic action list.
1084 : : *
1085 : : * @param[in] priv
1086 : : * Pointer to the port private data structure.
1087 : : * @param[in] acts
1088 : : * Pointer to the template HW steering DR actions.
1089 : : * @param[in] type
1090 : : * Action type.
1091 : : * @param[in] action_src
1092 : : * Offset of source rte flow action.
1093 : : * @param[in] action_dst
1094 : : * Offset of destination DR action.
1095 : : * @param[in] len
1096 : : * Length of the data to be updated.
1097 : : *
1098 : : * @return
1099 : : * 0 on success, negative value otherwise and rte_errno is set.
1100 : : */
1101 : : static __rte_always_inline int
1102 : : __flow_hw_act_data_encap_append(struct mlx5_priv *priv,
1103 : : struct mlx5_hw_actions *acts,
1104 : : enum rte_flow_action_type type,
1105 : : uint16_t action_src,
1106 : : uint16_t action_dst,
1107 : : uint16_t len)
1108 : : {
1109 : : struct mlx5_action_construct_data *act_data;
1110 : :
1111 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1112 : : if (!act_data)
1113 : : return -1;
1114 : 0 : act_data->encap.len = len;
1115 [ # # ]: 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
1116 : : return 0;
1117 : : }
1118 : :
1119 : : /**
1120 : : * Append dynamic push action to the dynamic action list.
1121 : : *
1122 : : * @param[in] dev
1123 : : * Pointer to the port.
1124 : : * @param[in] acts
1125 : : * Pointer to the template HW steering DR actions.
1126 : : * @param[in] type
1127 : : * Action type.
1128 : : * @param[in] action_src
1129 : : * Offset of source rte flow action.
1130 : : * @param[in] action_dst
1131 : : * Offset of destination DR action.
1132 : : * @param[in] len
1133 : : * Length of the data to be updated.
1134 : : *
1135 : : * @return
1136 : : * Data pointer on success, NULL otherwise and rte_errno is set.
1137 : : */
1138 : : static __rte_always_inline void *
1139 : : __flow_hw_act_data_push_append(struct rte_eth_dev *dev,
1140 : : struct mlx5_hw_actions *acts,
1141 : : enum rte_flow_action_type type,
1142 : : uint16_t action_src,
1143 : : uint16_t action_dst,
1144 : : uint16_t len)
1145 : : {
1146 : : struct mlx5_action_construct_data *act_data;
1147 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1148 : :
1149 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1150 : : if (!act_data)
1151 : : return NULL;
1152 : 0 : act_data->ipv6_ext.len = len;
1153 [ # # ]: 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
1154 : : return act_data;
1155 : : }
1156 : :
1157 : : static __rte_always_inline int
1158 : : __flow_hw_act_data_hdr_modify_append(struct mlx5_priv *priv,
1159 : : struct mlx5_hw_actions *acts,
1160 : : enum rte_flow_action_type type,
1161 : : uint16_t action_src,
1162 : : uint16_t action_dst,
1163 : : const struct rte_flow_action_modify_field *mf,
1164 : : uint16_t mhdr_cmds_off,
1165 : : uint16_t mhdr_cmds_end,
1166 : : bool shared,
1167 : : struct field_modify_info *field,
1168 : : struct field_modify_info *dcopy,
1169 : : uint32_t *mask)
1170 : : {
1171 : : struct mlx5_action_construct_data *act_data;
1172 : :
1173 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1174 : : if (!act_data)
1175 : : return -1;
1176 : 0 : act_data->modify_header.action = *mf;
1177 : 0 : act_data->modify_header.mhdr_cmds_off = mhdr_cmds_off;
1178 : 0 : act_data->modify_header.mhdr_cmds_end = mhdr_cmds_end;
1179 : 0 : act_data->modify_header.shared = shared;
1180 [ # # ]: 0 : rte_memcpy(act_data->modify_header.field, field,
1181 : : sizeof(*field) * MLX5_ACT_MAX_MOD_FIELDS);
1182 [ # # ]: 0 : rte_memcpy(act_data->modify_header.dcopy, dcopy,
1183 : : sizeof(*dcopy) * MLX5_ACT_MAX_MOD_FIELDS);
1184 [ # # ]: 0 : rte_memcpy(act_data->modify_header.mask, mask,
1185 : : sizeof(*mask) * MLX5_ACT_MAX_MOD_FIELDS);
1186 [ # # ]: 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
1187 : : return 0;
1188 : : }
1189 : :
1190 : : /**
1191 : : * Append shared RSS action to the dynamic action list.
1192 : : *
1193 : : * @param[in] priv
1194 : : * Pointer to the port private data structure.
1195 : : * @param[in] acts
1196 : : * Pointer to the template HW steering DR actions.
1197 : : * @param[in] type
1198 : : * Action type.
1199 : : * @param[in] action_src
1200 : : * Offset of source rte flow action.
1201 : : * @param[in] action_dst
1202 : : * Offset of destination DR action.
1203 : : * @param[in] idx
1204 : : * Shared RSS index.
1205 : : * @param[in] rss
1206 : : * Pointer to the shared RSS info.
1207 : : *
1208 : : * @return
1209 : : * 0 on success, negative value otherwise and rte_errno is set.
1210 : : */
1211 : : static __rte_always_inline int
1212 : : __flow_hw_act_data_shared_rss_append(struct mlx5_priv *priv,
1213 : : struct mlx5_hw_actions *acts,
1214 : : enum rte_flow_action_type type,
1215 : : uint16_t action_src,
1216 : : uint16_t action_dst,
1217 : : uint32_t idx,
1218 : : struct mlx5_shared_action_rss *rss)
1219 : : {
1220 : : struct mlx5_action_construct_data *act_data;
1221 : :
1222 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1223 : : if (!act_data)
1224 : : return -1;
1225 : 0 : act_data->shared_rss.level = rss->origin.level;
1226 [ # # ]: 0 : act_data->shared_rss.types = !rss->origin.types ? RTE_ETH_RSS_IP :
1227 : : rss->origin.types;
1228 : 0 : act_data->shared_rss.idx = idx;
1229 : 0 : act_data->shared_rss.symmetric_hash_function =
1230 : 0 : MLX5_RSS_IS_SYMM(rss->origin.func);
1231 [ # # ]: 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
1232 : : return 0;
1233 : : }
1234 : :
1235 : : /**
1236 : : * Append shared counter action to the dynamic action list.
1237 : : *
1238 : : * @param[in] priv
1239 : : * Pointer to the port private data structure.
1240 : : * @param[in] acts
1241 : : * Pointer to the template HW steering DR actions.
1242 : : * @param[in] type
1243 : : * Action type.
1244 : : * @param[in] action_src
1245 : : * Offset of source rte flow action.
1246 : : * @param[in] action_dst
1247 : : * Offset of destination DR action.
1248 : : * @param[in] cnt_id
1249 : : * Shared counter id.
1250 : : *
1251 : : * @return
1252 : : * 0 on success, negative value otherwise and rte_errno is set.
1253 : : */
1254 : : static __rte_always_inline int
1255 : : __flow_hw_act_data_shared_cnt_append(struct mlx5_priv *priv,
1256 : : struct mlx5_hw_actions *acts,
1257 : : enum rte_flow_action_type type,
1258 : : uint16_t action_src,
1259 : : uint16_t action_dst,
1260 : : cnt_id_t cnt_id)
1261 : : {
1262 : : struct mlx5_action_construct_data *act_data;
1263 : :
1264 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1265 : : if (!act_data)
1266 : : return -1;
1267 : : act_data->type = type;
1268 : 0 : act_data->shared_counter.id = cnt_id;
1269 [ # # ]: 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
1270 : : return 0;
1271 : : }
1272 : :
1273 : : /**
1274 : : * Append shared meter_mark action to the dynamic action list.
1275 : : *
1276 : : * @param[in] priv
1277 : : * Pointer to the port private data structure.
1278 : : * @param[in] acts
1279 : : * Pointer to the template HW steering DR actions.
1280 : : * @param[in] type
1281 : : * Action type.
1282 : : * @param[in] action_src
1283 : : * Offset of source rte flow action.
1284 : : * @param[in] action_dst
1285 : : * Offset of destination DR action.
1286 : : * @param[in] mtr_id
1287 : : * Shared meter id.
1288 : : *
1289 : : * @return
1290 : : * 0 on success, negative value otherwise and rte_errno is set.
1291 : : */
1292 : : static __rte_always_inline int
1293 : : __flow_hw_act_data_shared_mtr_append(struct mlx5_priv *priv,
1294 : : struct mlx5_hw_actions *acts,
1295 : : enum rte_flow_action_type type,
1296 : : uint16_t action_src,
1297 : : uint16_t action_dst,
1298 : : cnt_id_t mtr_id)
1299 : : { struct mlx5_action_construct_data *act_data;
1300 : :
1301 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1302 : : if (!act_data)
1303 : : return -1;
1304 : : act_data->type = type;
1305 : 0 : act_data->shared_meter.id = mtr_id;
1306 [ # # ]: 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
1307 : : return 0;
1308 : : }
1309 : :
1310 : : /**
1311 : : * Translate shared indirect action.
1312 : : *
1313 : : * @param[in] dev
1314 : : * Pointer to the rte_eth_dev data structure.
1315 : : * @param[in] action
1316 : : * Pointer to the shared indirect rte_flow action.
1317 : : * @param[in] acts
1318 : : * Pointer to the template HW steering DR actions.
1319 : : * @param[in] action_src
1320 : : * Offset of source rte flow action.
1321 : : * @param[in] action_dst
1322 : : * Offset of destination DR action.
1323 : : *
1324 : : * @return
1325 : : * 0 on success, negative value otherwise and rte_errno is set.
1326 : : */
1327 : : static __rte_always_inline int
1328 : : flow_hw_shared_action_translate(struct rte_eth_dev *dev,
1329 : : const struct rte_flow_action *action,
1330 : : struct mlx5_hw_actions *acts,
1331 : : uint16_t action_src,
1332 : : uint16_t action_dst)
1333 : : {
1334 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1335 : : struct mlx5_shared_action_rss *shared_rss;
1336 : 0 : uint32_t act_idx = (uint32_t)(uintptr_t)action->conf;
1337 : 0 : uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
1338 : 0 : uint32_t idx = act_idx &
1339 : : ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
1340 : :
1341 : 0 : switch (type) {
1342 : 0 : case MLX5_INDIRECT_ACTION_TYPE_RSS:
1343 : 0 : shared_rss = mlx5_ipool_get
1344 : 0 : (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
1345 [ # # ]: 0 : if (!shared_rss || __flow_hw_act_data_shared_rss_append
1346 : : (priv, acts,
1347 : : (enum rte_flow_action_type)MLX5_RTE_FLOW_ACTION_TYPE_RSS,
1348 : : action_src, action_dst, idx, shared_rss)) {
1349 : 0 : DRV_LOG(WARNING, "Indirect RSS action index %d translate failed", act_idx);
1350 : : return -1;
1351 : : }
1352 : : break;
1353 : 0 : case MLX5_INDIRECT_ACTION_TYPE_COUNT:
1354 : : if (__flow_hw_act_data_shared_cnt_append(priv, acts,
1355 : : (enum rte_flow_action_type)
1356 : : MLX5_RTE_FLOW_ACTION_TYPE_COUNT,
1357 : : action_src, action_dst, act_idx)) {
1358 : 0 : DRV_LOG(WARNING, "Indirect count action translate failed");
1359 : : return -1;
1360 : : }
1361 : : break;
1362 : : case MLX5_INDIRECT_ACTION_TYPE_AGE:
1363 : : /* Not supported, prevent by validate function. */
1364 : : MLX5_ASSERT(0);
1365 : : break;
1366 : 0 : case MLX5_INDIRECT_ACTION_TYPE_CT:
1367 : : if (flow_hw_ct_compile(dev, MLX5_HW_INV_QUEUE,
1368 : : idx, &acts->rule_acts[action_dst])) {
1369 : 0 : DRV_LOG(WARNING, "Indirect CT action translate failed");
1370 : : return -1;
1371 : : }
1372 : : break;
1373 : 0 : case MLX5_INDIRECT_ACTION_TYPE_METER_MARK:
1374 : : if (__flow_hw_act_data_shared_mtr_append(priv, acts,
1375 : : (enum rte_flow_action_type)
1376 : : MLX5_RTE_FLOW_ACTION_TYPE_METER_MARK,
1377 : : action_src, action_dst, idx)) {
1378 : 0 : DRV_LOG(WARNING, "Indirect meter mark action translate failed");
1379 : : return -1;
1380 : : }
1381 : : break;
1382 : 0 : case MLX5_INDIRECT_ACTION_TYPE_QUOTA:
1383 : : flow_hw_construct_quota(priv, &acts->rule_acts[action_dst], idx);
1384 : : break;
1385 : 0 : default:
1386 : 0 : DRV_LOG(WARNING, "Unsupported shared action type:%d", type);
1387 : : break;
1388 : : }
1389 : : return 0;
1390 : : }
1391 : :
1392 : : static __rte_always_inline bool
1393 : : flow_hw_action_modify_field_is_shared(const struct rte_flow_action *action,
1394 : : const struct rte_flow_action *mask)
1395 : : {
1396 : : const struct rte_flow_action_modify_field *v = action->conf;
1397 : 0 : const struct rte_flow_action_modify_field *m = mask->conf;
1398 : :
1399 : 0 : if (v->src.field == RTE_FLOW_FIELD_VALUE) {
1400 : : uint32_t j;
1401 : :
1402 [ # # ]: 0 : for (j = 0; j < RTE_DIM(m->src.value); ++j) {
1403 : : /*
1404 : : * Immediate value is considered to be masked
1405 : : * (and thus shared by all flow rules), if mask
1406 : : * is non-zero. Partial mask over immediate value
1407 : : * is not allowed.
1408 : : */
1409 [ # # ]: 0 : if (m->src.value[j])
1410 : : return true;
1411 : : }
1412 : : return false;
1413 : : }
1414 [ # # ]: 0 : if (v->src.field == RTE_FLOW_FIELD_POINTER)
1415 : 0 : return m->src.pvalue != NULL;
1416 : : /*
1417 : : * Source field types other than VALUE and
1418 : : * POINTER are always shared.
1419 : : */
1420 : : return true;
1421 : : }
1422 : :
1423 : : static __rte_always_inline bool
1424 : : flow_hw_should_insert_nop(const struct mlx5_hw_modify_header_action *mhdr,
1425 : : const struct mlx5_modification_cmd *cmd)
1426 : : {
1427 : : struct mlx5_modification_cmd last_cmd = { { 0 } };
1428 : : struct mlx5_modification_cmd new_cmd = { { 0 } };
1429 : 0 : const uint32_t cmds_num = mhdr->mhdr_cmds_num;
1430 : : unsigned int last_type;
1431 : : bool should_insert = false;
1432 : :
1433 [ # # # # ]: 0 : if (cmds_num == 0)
1434 : : return false;
1435 : 0 : last_cmd = *(&mhdr->mhdr_cmds[cmds_num - 1]);
1436 [ # # # # ]: 0 : last_cmd.data0 = rte_be_to_cpu_32(last_cmd.data0);
1437 [ # # # # ]: 0 : last_cmd.data1 = rte_be_to_cpu_32(last_cmd.data1);
1438 : 0 : last_type = last_cmd.action_type;
1439 : 0 : new_cmd = *cmd;
1440 [ # # # # ]: 0 : new_cmd.data0 = rte_be_to_cpu_32(new_cmd.data0);
1441 [ # # # # ]: 0 : new_cmd.data1 = rte_be_to_cpu_32(new_cmd.data1);
1442 [ # # # # : 0 : switch (new_cmd.action_type) {
# # ]
1443 : 0 : case MLX5_MODIFICATION_TYPE_SET:
1444 : : case MLX5_MODIFICATION_TYPE_ADD:
1445 [ # # # # ]: 0 : if (last_type == MLX5_MODIFICATION_TYPE_SET ||
1446 : : last_type == MLX5_MODIFICATION_TYPE_ADD)
1447 : 0 : should_insert = new_cmd.field == last_cmd.field;
1448 : 0 : else if (last_type == MLX5_MODIFICATION_TYPE_COPY ||
1449 [ # # # # ]: 0 : last_type == MLX5_MODIFICATION_TYPE_ADD_FIELD)
1450 : 0 : should_insert = new_cmd.field == last_cmd.dst_field;
1451 : : else if (last_type == MLX5_MODIFICATION_TYPE_NOP)
1452 : : should_insert = false;
1453 : : else
1454 : : MLX5_ASSERT(false); /* Other types are not supported. */
1455 : : break;
1456 : 0 : case MLX5_MODIFICATION_TYPE_COPY:
1457 : : case MLX5_MODIFICATION_TYPE_ADD_FIELD:
1458 [ # # # # ]: 0 : if (last_type == MLX5_MODIFICATION_TYPE_SET ||
1459 : : last_type == MLX5_MODIFICATION_TYPE_ADD)
1460 [ # # # # ]: 0 : should_insert = (new_cmd.field == last_cmd.field ||
1461 [ # # # # ]: 0 : new_cmd.dst_field == last_cmd.field);
1462 : 0 : else if (last_type == MLX5_MODIFICATION_TYPE_COPY ||
1463 [ # # # # ]: 0 : last_type == MLX5_MODIFICATION_TYPE_ADD_FIELD)
1464 [ # # # # ]: 0 : should_insert = (new_cmd.field == last_cmd.dst_field ||
1465 [ # # # # ]: 0 : new_cmd.dst_field == last_cmd.dst_field);
1466 : : else if (last_type == MLX5_MODIFICATION_TYPE_NOP)
1467 : : should_insert = false;
1468 : : else
1469 : : MLX5_ASSERT(false); /* Other types are not supported. */
1470 : : break;
1471 : : default:
1472 : : /* Other action types should be rejected on AT validation. */
1473 : : MLX5_ASSERT(false);
1474 : : break;
1475 : : }
1476 : : return should_insert;
1477 : : }
1478 : :
1479 : : static __rte_always_inline int
1480 : : flow_hw_mhdr_cmd_nop_append(struct mlx5_hw_modify_header_action *mhdr)
1481 : : {
1482 : : struct mlx5_modification_cmd *nop;
1483 : : uint32_t num = mhdr->mhdr_cmds_num;
1484 : :
1485 [ # # # # ]: 0 : if (num + 1 >= MLX5_MHDR_MAX_CMD)
1486 : : return -ENOMEM;
1487 : 0 : nop = mhdr->mhdr_cmds + num;
1488 : : nop->data0 = 0;
1489 : : nop->action_type = MLX5_MODIFICATION_TYPE_NOP;
1490 : 0 : nop->data0 = rte_cpu_to_be_32(nop->data0);
1491 : 0 : nop->data1 = 0;
1492 : 0 : mhdr->mhdr_cmds_num = num + 1;
1493 : : return 0;
1494 : : }
1495 : :
1496 : : static __rte_always_inline int
1497 : : flow_hw_mhdr_cmd_append(struct mlx5_hw_modify_header_action *mhdr,
1498 : : struct mlx5_modification_cmd *cmd)
1499 : : {
1500 : 0 : uint32_t num = mhdr->mhdr_cmds_num;
1501 : :
1502 [ # # ]: 0 : if (num + 1 >= MLX5_MHDR_MAX_CMD)
1503 : : return -ENOMEM;
1504 : 0 : mhdr->mhdr_cmds[num] = *cmd;
1505 : 0 : mhdr->mhdr_cmds_num = num + 1;
1506 : : return 0;
1507 : : }
1508 : :
1509 : : static __rte_always_inline int
1510 : : flow_hw_converted_mhdr_cmds_append(struct mlx5_hw_modify_header_action *mhdr,
1511 : : struct mlx5_flow_dv_modify_hdr_resource *resource)
1512 : : {
1513 : : uint32_t idx;
1514 : : int ret;
1515 : :
1516 [ # # ]: 0 : for (idx = 0; idx < resource->actions_num; ++idx) {
1517 : : struct mlx5_modification_cmd *src = &resource->actions[idx];
1518 : :
1519 [ # # ]: 0 : if (flow_hw_should_insert_nop(mhdr, src)) {
1520 : : ret = flow_hw_mhdr_cmd_nop_append(mhdr);
1521 : : if (ret)
1522 : : return ret;
1523 : : }
1524 : : ret = flow_hw_mhdr_cmd_append(mhdr, src);
1525 : : if (ret)
1526 : : return ret;
1527 : : }
1528 : : return 0;
1529 : : }
1530 : :
1531 : : static __rte_always_inline void
1532 : : flow_hw_modify_field_init(struct mlx5_hw_modify_header_action *mhdr,
1533 : : struct rte_flow_actions_template *at)
1534 : : {
1535 : : memset(mhdr, 0, sizeof(*mhdr));
1536 : : /* Modify header action without any commands is shared by default. */
1537 : 0 : mhdr->shared = true;
1538 : 0 : mhdr->pos = at->mhdr_off;
1539 : : }
1540 : :
1541 : : static __rte_always_inline int
1542 : : flow_hw_modify_field_compile(struct rte_eth_dev *dev,
1543 : : const struct rte_flow_attr *attr,
1544 : : const struct rte_flow_action *action, /* Current action from AT. */
1545 : : const struct rte_flow_action *action_mask, /* Current mask from AT. */
1546 : : struct mlx5_hw_actions *acts,
1547 : : struct mlx5_hw_modify_header_action *mhdr,
1548 : : uint16_t src_pos,
1549 : : struct rte_flow_error *error)
1550 : : {
1551 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1552 : 0 : const struct rte_flow_action_modify_field *conf = action->conf;
1553 : : union {
1554 : : struct mlx5_flow_dv_modify_hdr_resource resource;
1555 : : uint8_t data[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
1556 : : sizeof(struct mlx5_modification_cmd) * MLX5_MHDR_MAX_CMD];
1557 : : } dummy;
1558 : : struct mlx5_flow_dv_modify_hdr_resource *resource;
1559 : 0 : struct rte_flow_item item = {
1560 : : .spec = NULL,
1561 : : .mask = NULL
1562 : : };
1563 : 0 : struct field_modify_info field[MLX5_ACT_MAX_MOD_FIELDS] = {
1564 : : {0, 0, MLX5_MODI_OUT_NONE} };
1565 : 0 : struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {
1566 : : {0, 0, MLX5_MODI_OUT_NONE} };
1567 : 0 : uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = { 0 };
1568 : 0 : uint32_t type, value = 0;
1569 : : uint16_t cmds_start, cmds_end;
1570 : : bool shared;
1571 : : int ret;
1572 : :
1573 : : /*
1574 : : * Modify header action is shared if previous modify_field actions
1575 : : * are shared and currently compiled action is shared.
1576 : : */
1577 : : shared = flow_hw_action_modify_field_is_shared(action, action_mask);
1578 : 0 : mhdr->shared &= shared;
1579 [ # # ]: 0 : if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
1580 : : conf->src.field == RTE_FLOW_FIELD_VALUE) {
1581 [ # # ]: 0 : type = conf->operation == RTE_FLOW_MODIFY_SET ? MLX5_MODIFICATION_TYPE_SET :
1582 : : MLX5_MODIFICATION_TYPE_ADD;
1583 : : /* For SET/ADD fill the destination field (field) first. */
1584 : 0 : mlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,
1585 : 0 : conf->width, dev,
1586 : : attr, error);
1587 : 0 : item.spec = conf->src.field == RTE_FLOW_FIELD_POINTER ?
1588 [ # # ]: 0 : (void *)(uintptr_t)conf->src.pvalue :
1589 : : (void *)(uintptr_t)&conf->src.value;
1590 [ # # ]: 0 : if (conf->dst.field == RTE_FLOW_FIELD_META ||
1591 [ # # ]: 0 : conf->dst.field == RTE_FLOW_FIELD_TAG ||
1592 [ # # ]: 0 : conf->dst.field == RTE_FLOW_FIELD_METER_COLOR ||
1593 : 0 : conf->dst.field == (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG) {
1594 : : uint8_t tag_index = flow_tag_index_get(&conf->dst);
1595 : :
1596 : 0 : value = *(const unaligned_uint32_t *)item.spec;
1597 [ # # # # ]: 0 : if (conf->dst.field == RTE_FLOW_FIELD_TAG &&
1598 : : tag_index == RTE_PMD_MLX5_LINEAR_HASH_TAG_INDEX)
1599 [ # # ]: 0 : value = rte_cpu_to_be_32(value << 16);
1600 : : else
1601 [ # # ]: 0 : value = rte_cpu_to_be_32(value);
1602 : 0 : item.spec = &value;
1603 [ # # ]: 0 : } else if (conf->dst.field == RTE_FLOW_FIELD_GTP_PSC_QFI ||
1604 : : conf->dst.field == RTE_FLOW_FIELD_GENEVE_OPT_TYPE) {
1605 : : /*
1606 : : * Both QFI and Geneve option type are passed as an uint8_t integer,
1607 : : * but it is accessed through a 2nd least significant byte of a 32-bit
1608 : : * field in modify header command.
1609 : : */
1610 : 0 : value = *(const uint8_t *)item.spec;
1611 [ # # ]: 0 : value = rte_cpu_to_be_32(value << 8);
1612 : 0 : item.spec = &value;
1613 [ # # ]: 0 : } else if (conf->dst.field == RTE_FLOW_FIELD_VXLAN_LAST_RSVD) {
1614 : 0 : value = *(const uint8_t *)item.spec << 24;
1615 [ # # ]: 0 : value = rte_cpu_to_be_32(value);
1616 : 0 : item.spec = &value;
1617 : : }
1618 : : } else {
1619 : 0 : type = conf->operation == RTE_FLOW_MODIFY_SET ?
1620 [ # # ]: 0 : MLX5_MODIFICATION_TYPE_COPY : MLX5_MODIFICATION_TYPE_ADD_FIELD;
1621 : : /* For COPY fill the destination field (dcopy) without mask. */
1622 : 0 : mlx5_flow_field_id_to_modify_info(&conf->dst, dcopy, NULL,
1623 : 0 : conf->width, dev,
1624 : : attr, error);
1625 : : /* Then construct the source field (field) with mask. */
1626 : 0 : mlx5_flow_field_id_to_modify_info(&conf->src, field, mask,
1627 : 0 : conf->width, dev,
1628 : : attr, error);
1629 : : }
1630 : 0 : item.mask = &mask;
1631 : : memset(&dummy, 0, sizeof(dummy));
1632 : : resource = &dummy.resource;
1633 : 0 : ret = flow_dv_convert_modify_action(&item, field, dcopy, resource, type, error);
1634 [ # # ]: 0 : if (ret)
1635 : : return ret;
1636 : : MLX5_ASSERT(resource->actions_num > 0);
1637 : : /*
1638 : : * If previous modify field action collide with this one, then insert NOP command.
1639 : : * This NOP command will not be a part of action's command range used to update commands
1640 : : * on rule creation.
1641 : : */
1642 [ # # ]: 0 : if (flow_hw_should_insert_nop(mhdr, &resource->actions[0])) {
1643 : : ret = flow_hw_mhdr_cmd_nop_append(mhdr);
1644 : : if (ret)
1645 : 0 : return rte_flow_error_set(error, ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1646 : : NULL, "too many modify field operations specified");
1647 : : }
1648 : 0 : cmds_start = mhdr->mhdr_cmds_num;
1649 : : ret = flow_hw_converted_mhdr_cmds_append(mhdr, resource);
1650 [ # # ]: 0 : if (ret)
1651 : 0 : return rte_flow_error_set(error, ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1652 : : NULL, "too many modify field operations specified");
1653 : :
1654 : 0 : cmds_end = mhdr->mhdr_cmds_num;
1655 [ # # ]: 0 : if (shared)
1656 : : return 0;
1657 : : ret = __flow_hw_act_data_hdr_modify_append(priv, acts, RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
1658 : 0 : src_pos, mhdr->pos, conf,
1659 : : cmds_start, cmds_end, shared,
1660 : : field, dcopy, mask);
1661 : : if (ret)
1662 : 0 : return rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1663 : : NULL, "not enough memory to store modify field metadata");
1664 : : return 0;
1665 : : }
1666 : :
1667 : : static uint32_t
1668 : 0 : flow_hw_count_nop_modify_field(struct mlx5_hw_modify_header_action *mhdr)
1669 : : {
1670 : : uint32_t i;
1671 : : uint32_t nops = 0;
1672 : :
1673 [ # # ]: 0 : for (i = 0; i < mhdr->mhdr_cmds_num; ++i) {
1674 : 0 : struct mlx5_modification_cmd cmd = mhdr->mhdr_cmds[i];
1675 : :
1676 [ # # ]: 0 : cmd.data0 = rte_be_to_cpu_32(cmd.data0);
1677 [ # # ]: 0 : if (cmd.action_type == MLX5_MODIFICATION_TYPE_NOP)
1678 : 0 : ++nops;
1679 : : }
1680 : 0 : return nops;
1681 : : }
1682 : :
1683 : : static int
1684 : 0 : flow_hw_validate_compiled_modify_field(struct rte_eth_dev *dev,
1685 : : const struct mlx5_flow_template_table_cfg *cfg,
1686 : : struct mlx5_hw_modify_header_action *mhdr,
1687 : : struct rte_flow_error *error)
1688 : : {
1689 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1690 : 0 : struct mlx5_hca_attr *hca_attr = &priv->sh->cdev->config.hca_attr;
1691 : :
1692 : : /*
1693 : : * Header modify pattern length limitation is only valid for HWS groups, i.e. groups > 0.
1694 : : * In group 0, MODIFY_FIELD actions are handled with header modify actions
1695 : : * managed by rdma-core.
1696 : : */
1697 [ # # ]: 0 : if (cfg->attr.flow_attr.group != 0 &&
1698 [ # # ]: 0 : mhdr->mhdr_cmds_num > hca_attr->max_header_modify_pattern_length) {
1699 : 0 : uint32_t nops = flow_hw_count_nop_modify_field(mhdr);
1700 : :
1701 : 0 : DRV_LOG(ERR, "Too many modify header commands generated from "
1702 : : "MODIFY_FIELD actions. "
1703 : : "Generated HW commands = %u (amount of NOP commands = %u). "
1704 : : "Maximum supported = %u.",
1705 : : mhdr->mhdr_cmds_num, nops,
1706 : : hca_attr->max_header_modify_pattern_length);
1707 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1708 : : "Number of MODIFY_FIELD actions exceeds maximum "
1709 : : "supported limit of actions");
1710 : : }
1711 : : return 0;
1712 : : }
1713 : :
1714 : : static int
1715 : 0 : flow_hw_represented_port_compile(struct rte_eth_dev *dev,
1716 : : const struct rte_flow_attr *attr,
1717 : : const struct rte_flow_action *action,
1718 : : const struct rte_flow_action *action_mask,
1719 : : struct mlx5_hw_actions *acts,
1720 : : uint16_t action_src, uint16_t action_dst,
1721 : : struct rte_flow_error *error)
1722 : : {
1723 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1724 : 0 : const struct rte_flow_action_ethdev *v = action->conf;
1725 : 0 : const struct rte_flow_action_ethdev *m = action_mask->conf;
1726 : : int ret;
1727 : :
1728 [ # # ]: 0 : if (!attr->group)
1729 : 0 : return rte_flow_error_set(error, EINVAL,
1730 : : RTE_FLOW_ERROR_TYPE_ATTR, NULL,
1731 : : "represented_port action cannot"
1732 : : " be used on group 0");
1733 [ # # ]: 0 : if (!attr->transfer)
1734 : 0 : return rte_flow_error_set(error, EINVAL,
1735 : : RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER,
1736 : : NULL,
1737 : : "represented_port action requires"
1738 : : " transfer attribute");
1739 [ # # ]: 0 : if (attr->ingress || attr->egress)
1740 : 0 : return rte_flow_error_set(error, EINVAL,
1741 : : RTE_FLOW_ERROR_TYPE_ATTR, NULL,
1742 : : "represented_port action cannot"
1743 : : " be used with direction attributes");
1744 [ # # ]: 0 : if (!priv->master)
1745 : 0 : return rte_flow_error_set(error, EINVAL,
1746 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1747 : : "represented_port action must"
1748 : : " be used on proxy port");
1749 [ # # # # ]: 0 : if (m && !!m->port_id) {
1750 : : struct mlx5_priv *port_priv;
1751 : :
1752 [ # # ]: 0 : if (!v)
1753 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
1754 : : action, "port index was not provided");
1755 : 0 : port_priv = mlx5_port_to_eswitch_info(v->port_id, false);
1756 [ # # ]: 0 : if (port_priv == NULL)
1757 : 0 : return rte_flow_error_set
1758 : : (error, EINVAL,
1759 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1760 : : "port does not exist or unable to"
1761 : : " obtain E-Switch info for port");
1762 : : MLX5_ASSERT(priv->hw_vport != NULL);
1763 [ # # ]: 0 : if (priv->hw_vport[v->port_id]) {
1764 : 0 : acts->rule_acts[action_dst].action =
1765 : : priv->hw_vport[v->port_id];
1766 : : } else {
1767 : 0 : return rte_flow_error_set
1768 : : (error, EINVAL,
1769 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1770 : : "cannot use represented_port action"
1771 : : " with this port");
1772 : : }
1773 : : } else {
1774 : : ret = __flow_hw_act_data_general_append
1775 : 0 : (priv, acts, action->type,
1776 : : action_src, action_dst);
1777 : : if (ret)
1778 : 0 : return rte_flow_error_set
1779 : : (error, ENOMEM,
1780 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1781 : : "not enough memory to store"
1782 : : " vport action");
1783 : : }
1784 : : return 0;
1785 : : }
1786 : :
1787 : : static __rte_always_inline int
1788 : : flow_hw_meter_compile(struct rte_eth_dev *dev,
1789 : : const struct mlx5_flow_template_table_cfg *cfg,
1790 : : uint16_t aso_mtr_pos,
1791 : : uint16_t jump_pos,
1792 : : const struct rte_flow_action *action,
1793 : : struct mlx5_hw_actions *acts,
1794 : : struct rte_flow_error *error)
1795 : : {
1796 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1797 : : struct mlx5_aso_mtr *aso_mtr;
1798 : : const struct rte_flow_action_meter *meter = action->conf;
1799 : 0 : uint32_t group = cfg->attr.flow_attr.group;
1800 : :
1801 : 0 : aso_mtr = mlx5_aso_meter_by_idx(priv, meter->mtr_id);
1802 : 0 : acts->rule_acts[aso_mtr_pos].action = priv->mtr_bulk.action;
1803 : 0 : acts->rule_acts[aso_mtr_pos].aso_meter.offset = aso_mtr->offset;
1804 : 0 : acts->jump = flow_hw_jump_action_register
1805 : 0 : (dev, cfg, aso_mtr->fm.group, error);
1806 [ # # ]: 0 : if (!acts->jump)
1807 : : return -ENOMEM;
1808 : 0 : acts->rule_acts[jump_pos].action = (!!group) ?
1809 [ # # ]: 0 : acts->jump->hws_action :
1810 : : acts->jump->root_action;
1811 [ # # ]: 0 : if (mlx5_aso_mtr_wait(priv, aso_mtr, true))
1812 : : return -ENOMEM;
1813 : : return 0;
1814 : : }
1815 : :
1816 : : static __rte_always_inline int
1817 : : flow_hw_cnt_compile(struct rte_eth_dev *dev, uint32_t start_pos,
1818 : : struct mlx5_hw_actions *acts)
1819 : : {
1820 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1821 : : uint32_t pos = start_pos;
1822 : : cnt_id_t cnt_id;
1823 : : int ret;
1824 : :
1825 : 0 : ret = mlx5_hws_cnt_shared_get(priv->hws_cpool, &cnt_id, 0);
1826 : : if (ret != 0)
1827 : : return ret;
1828 : 0 : ret = mlx5_hws_cnt_pool_get_action_offset
1829 : : (priv->hws_cpool,
1830 : : cnt_id,
1831 : : &acts->rule_acts[pos].action,
1832 : : &acts->rule_acts[pos].counter.offset);
1833 : : if (ret != 0)
1834 : : return ret;
1835 : 0 : acts->cnt_id = cnt_id;
1836 : : return 0;
1837 : : }
1838 : :
1839 : : static __rte_always_inline bool
1840 : : is_of_vlan_pcp_present(const struct rte_flow_action *actions)
1841 : : {
1842 : : /*
1843 : : * Order of RTE VLAN push actions is
1844 : : * OF_PUSH_VLAN / OF_SET_VLAN_VID [ / OF_SET_VLAN_PCP ]
1845 : : */
1846 : 0 : return actions[MLX5_HW_VLAN_PUSH_PCP_IDX].type ==
1847 : : RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP;
1848 : : }
1849 : :
1850 : : static __rte_always_inline bool
1851 : : is_template_masked_push_vlan(const struct rte_flow_action_of_push_vlan *mask)
1852 : : {
1853 : : /*
1854 : : * In masked push VLAN template all RTE push actions are masked.
1855 : : */
1856 [ # # ]: 0 : return mask && mask->ethertype != 0;
1857 : : }
1858 : :
1859 : 0 : static rte_be32_t vlan_hdr_to_be32(const struct rte_flow_action *actions)
1860 : : {
1861 : : /*
1862 : : * OpenFlow Switch Specification defines 801.1q VID as 12+1 bits.
1863 : : */
1864 : : rte_be32_t type, vid, pcp;
1865 : : #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
1866 : : rte_be32_t vid_lo, vid_hi;
1867 : : #endif
1868 : :
1869 : 0 : type = ((const struct rte_flow_action_of_push_vlan *)
1870 : 0 : actions[MLX5_HW_VLAN_PUSH_TYPE_IDX].conf)->ethertype;
1871 : 0 : vid = ((const struct rte_flow_action_of_set_vlan_vid *)
1872 : 0 : actions[MLX5_HW_VLAN_PUSH_VID_IDX].conf)->vlan_vid;
1873 : : pcp = is_of_vlan_pcp_present(actions) ?
1874 : : ((const struct rte_flow_action_of_set_vlan_pcp *)
1875 [ # # # # ]: 0 : actions[MLX5_HW_VLAN_PUSH_PCP_IDX].conf)->vlan_pcp : 0;
1876 : : #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
1877 : 0 : vid_hi = vid & 0xff;
1878 : : vid_lo = vid >> 8;
1879 : 0 : return (((vid_lo << 8) | (pcp << 5) | vid_hi) << 16) | type;
1880 : : #else
1881 : : return (type << 16) | (pcp << 13) | vid;
1882 : : #endif
1883 : : }
1884 : :
1885 : : static __rte_always_inline struct mlx5_aso_mtr *
1886 : : flow_hw_meter_mark_alloc(struct rte_eth_dev *dev, uint32_t queue,
1887 : : const struct rte_flow_action *action,
1888 : : struct mlx5_hw_q_job *job, bool push,
1889 : : struct rte_flow_error *error)
1890 : : {
1891 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1892 : 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
1893 : 0 : const struct rte_flow_action_meter_mark *meter_mark = action->conf;
1894 : : struct mlx5_aso_mtr *aso_mtr;
1895 : : struct mlx5_flow_meter_info *fm;
1896 : 0 : uint32_t mtr_id = 0;
1897 : : uintptr_t handle = (uintptr_t)MLX5_INDIRECT_ACTION_TYPE_METER_MARK <<
1898 : : MLX5_INDIRECT_ACTION_TYPE_OFFSET;
1899 : :
1900 : 0 : if (priv->shared_host) {
1901 : 0 : rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1902 : : "Meter mark actions can only be created on the host port");
1903 : : return NULL;
1904 : : }
1905 [ # # # # : 0 : if (meter_mark->profile == NULL)
# # # # #
# # # #
# ]
1906 : : return NULL;
1907 : 0 : aso_mtr = mlx5_ipool_malloc(pool->idx_pool, &mtr_id);
1908 [ # # # # : 0 : if (!aso_mtr) {
# # # # #
# # # #
# ]
1909 : 0 : rte_flow_error_set(error, ENOMEM,
1910 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1911 : : NULL,
1912 : : "failed to allocate aso meter entry");
1913 [ # # # # : 0 : if (mtr_id)
# # # # #
# # # #
# ]
1914 : 0 : mlx5_ipool_free(pool->idx_pool, mtr_id);
1915 : : return NULL;
1916 : : }
1917 : : /* Fill the flow meter parameters. */
1918 : 0 : aso_mtr->type = ASO_METER_INDIRECT;
1919 : : fm = &aso_mtr->fm;
1920 : 0 : fm->meter_id = mtr_id;
1921 : 0 : fm->profile = (struct mlx5_flow_meter_profile *)(meter_mark->profile);
1922 : 0 : fm->is_enable = meter_mark->state;
1923 : 0 : fm->color_aware = meter_mark->color_mode;
1924 : 0 : aso_mtr->pool = pool;
1925 [ # # ]: 0 : aso_mtr->state = (queue == MLX5_HW_INV_QUEUE) ?
1926 : : ASO_METER_WAIT : ASO_METER_WAIT_ASYNC;
1927 : 0 : aso_mtr->offset = mtr_id - 1;
1928 [ # # # # : 0 : aso_mtr->init_color = fm->color_aware ? RTE_COLORS : RTE_COLOR_GREEN;
# # # # #
# # # #
# ]
1929 : 0 : job->action = (void *)(handle | mtr_id);
1930 : : /* Update ASO flow meter by wqe. */
1931 [ # # # # : 0 : if (mlx5_aso_meter_update_by_wqe(priv, queue, aso_mtr,
# # # # #
# # # #
# ]
1932 : : &priv->mtr_bulk, job, push)) {
1933 : 0 : mlx5_ipool_free(pool->idx_pool, mtr_id);
1934 : : return NULL;
1935 : : }
1936 : : /* Wait for ASO object completion. */
1937 [ # # # # : 0 : if (queue == MLX5_HW_INV_QUEUE &&
# # # # #
# # # # #
# # ]
1938 : 0 : mlx5_aso_mtr_wait(priv, aso_mtr, true)) {
1939 : 0 : mlx5_ipool_free(pool->idx_pool, mtr_id);
1940 : : return NULL;
1941 : : }
1942 : : return aso_mtr;
1943 : : }
1944 : :
1945 : : static __rte_always_inline int
1946 : : flow_hw_meter_mark_compile(struct rte_eth_dev *dev,
1947 : : uint16_t aso_mtr_pos,
1948 : : const struct rte_flow_action *action,
1949 : : struct mlx5dr_rule_action *acts,
1950 : : uint32_t *index,
1951 : : uint32_t queue,
1952 : : struct rte_flow_error *error)
1953 : : {
1954 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1955 : 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
1956 : : struct mlx5_aso_mtr *aso_mtr;
1957 : : struct mlx5_hw_q_job *job =
1958 : : flow_hw_action_job_init(priv, queue, NULL, NULL, NULL,
1959 : : MLX5_HW_Q_JOB_TYPE_CREATE,
1960 : : MLX5_HW_INDIRECT_TYPE_LEGACY, NULL);
1961 : :
1962 : : if (!job)
1963 : : return -1;
1964 : : aso_mtr = flow_hw_meter_mark_alloc(dev, queue, action, job,
1965 : : true, error);
1966 : : if (!aso_mtr) {
1967 : : flow_hw_job_put(priv, job, queue);
1968 : : return -1;
1969 : : }
1970 : :
1971 : : /* Compile METER_MARK action */
1972 : 0 : acts[aso_mtr_pos].action = pool->action;
1973 : 0 : acts[aso_mtr_pos].aso_meter.offset = aso_mtr->offset;
1974 : 0 : *index = aso_mtr->fm.meter_id;
1975 : : return 0;
1976 : : }
1977 : :
1978 : : static int
1979 : 0 : flow_hw_translate_indirect_mirror(__rte_unused struct rte_eth_dev *dev,
1980 : : __rte_unused const struct mlx5_action_construct_data *act_data,
1981 : : const struct rte_flow_action *action,
1982 : : struct mlx5dr_rule_action *dr_rule)
1983 : : {
1984 : 0 : const struct rte_flow_action_indirect_list *list_conf = action->conf;
1985 : 0 : const struct mlx5_mirror *mirror = (typeof(mirror))list_conf->handle;
1986 : :
1987 : 0 : dr_rule->action = mirror->mirror_action;
1988 : 0 : return 0;
1989 : : }
1990 : :
1991 : : /**
1992 : : * HWS mirror implemented as FW island.
1993 : : * The action does not support indirect list flow configuration.
1994 : : * If template handle was masked, use handle mirror action in flow rules.
1995 : : * Otherwise let flow rule specify mirror handle.
1996 : : */
1997 : : static int
1998 : 0 : hws_table_tmpl_translate_indirect_mirror(struct rte_eth_dev *dev,
1999 : : const struct rte_flow_action *action,
2000 : : const struct rte_flow_action *mask,
2001 : : struct mlx5_hw_actions *acts,
2002 : : uint16_t action_src, uint16_t action_dst)
2003 : : {
2004 : : int ret = 0;
2005 : 0 : const struct rte_flow_action_indirect_list *mask_conf = mask->conf;
2006 : :
2007 [ # # # # ]: 0 : if (mask_conf && mask_conf->handle) {
2008 : : /**
2009 : : * If mirror handle was masked, assign fixed DR5 mirror action.
2010 : : */
2011 : : flow_hw_translate_indirect_mirror(dev, NULL, action,
2012 : 0 : &acts->rule_acts[action_dst]);
2013 : : } else {
2014 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
2015 : : ret = flow_hw_act_data_indirect_list_append
2016 : : (priv, acts, RTE_FLOW_ACTION_TYPE_INDIRECT_LIST,
2017 : : action_src, action_dst,
2018 : : flow_hw_translate_indirect_mirror);
2019 : : }
2020 : 0 : return ret;
2021 : : }
2022 : :
2023 : : static int
2024 : 0 : flow_hw_reformat_action(__rte_unused struct rte_eth_dev *dev,
2025 : : __rte_unused const struct mlx5_action_construct_data *data,
2026 : : const struct rte_flow_action *action,
2027 : : struct mlx5dr_rule_action *dr_rule)
2028 : : {
2029 : 0 : const struct rte_flow_action_indirect_list *indlst_conf = action->conf;
2030 : :
2031 : 0 : dr_rule->action = ((struct mlx5_hw_encap_decap_action *)
2032 : 0 : (indlst_conf->handle))->action;
2033 [ # # ]: 0 : if (!dr_rule->action)
2034 : 0 : return -EINVAL;
2035 : : return 0;
2036 : : }
2037 : :
2038 : : /**
2039 : : * Template conf must not be masked. If handle is masked, use the one in template,
2040 : : * otherwise update per flow rule.
2041 : : */
2042 : : static int
2043 : 0 : hws_table_tmpl_translate_indirect_reformat(struct rte_eth_dev *dev,
2044 : : const struct rte_flow_action *action,
2045 : : const struct rte_flow_action *mask,
2046 : : struct mlx5_hw_actions *acts,
2047 : : uint16_t action_src, uint16_t action_dst)
2048 : : {
2049 : : int ret = -1;
2050 : 0 : const struct rte_flow_action_indirect_list *mask_conf = mask->conf;
2051 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
2052 : :
2053 [ # # # # : 0 : if (mask_conf && mask_conf->handle && !mask_conf->conf)
# # ]
2054 : : /**
2055 : : * If handle was masked, assign fixed DR action.
2056 : : */
2057 : : ret = flow_hw_reformat_action(dev, NULL, action,
2058 [ # # ]: 0 : &acts->rule_acts[action_dst]);
2059 [ # # # # : 0 : else if (mask_conf && !mask_conf->handle && !mask_conf->conf)
# # ]
2060 : : ret = flow_hw_act_data_indirect_list_append
2061 : : (priv, acts, RTE_FLOW_ACTION_TYPE_INDIRECT_LIST,
2062 : : action_src, action_dst, flow_hw_reformat_action);
2063 : 0 : return ret;
2064 : : }
2065 : :
2066 : : static int
2067 : 0 : flow_dr_set_meter(struct mlx5_priv *priv,
2068 : : struct mlx5dr_rule_action *dr_rule,
2069 : : const struct rte_flow_action_indirect_list *action_conf)
2070 : : {
2071 : 0 : const struct mlx5_indlst_legacy *legacy_obj =
2072 : : (typeof(legacy_obj))action_conf->handle;
2073 : 0 : struct mlx5_aso_mtr_pool *mtr_pool = priv->hws_mpool;
2074 : 0 : uint32_t act_idx = (uint32_t)(uintptr_t)legacy_obj->handle;
2075 : 0 : uint32_t mtr_id = act_idx & (RTE_BIT32(MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
2076 : 0 : struct mlx5_aso_mtr *aso_mtr = mlx5_ipool_get(mtr_pool->idx_pool, mtr_id);
2077 : :
2078 [ # # ]: 0 : if (!aso_mtr)
2079 : : return -EINVAL;
2080 : 0 : dr_rule->action = mtr_pool->action;
2081 : 0 : dr_rule->aso_meter.offset = aso_mtr->offset;
2082 : 0 : return 0;
2083 : : }
2084 : :
2085 : : __rte_always_inline static void
2086 : : flow_dr_mtr_flow_color(struct mlx5dr_rule_action *dr_rule, enum rte_color init_color)
2087 : : {
2088 : 0 : dr_rule->aso_meter.init_color =
2089 : 0 : (enum mlx5dr_action_aso_meter_color)rte_col_2_mlx5_col(init_color);
2090 : 0 : }
2091 : :
2092 : : static int
2093 : 0 : flow_hw_translate_indirect_meter(struct rte_eth_dev *dev,
2094 : : const struct mlx5_action_construct_data *act_data,
2095 : : const struct rte_flow_action *action,
2096 : : struct mlx5dr_rule_action *dr_rule)
2097 : : {
2098 : : int ret;
2099 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
2100 : 0 : const struct rte_flow_action_indirect_list *action_conf = action->conf;
2101 : 0 : const struct rte_flow_indirect_update_flow_meter_mark **flow_conf =
2102 : : (typeof(flow_conf))action_conf->conf;
2103 : :
2104 : 0 : ret = flow_dr_set_meter(priv, dr_rule, action_conf);
2105 [ # # ]: 0 : if (ret)
2106 : : return ret;
2107 [ # # ]: 0 : if (!act_data->shared_meter.conf_masked) {
2108 [ # # # # : 0 : if (flow_conf && flow_conf[0] && flow_conf[0]->init_color < RTE_COLORS)
# # ]
2109 : : flow_dr_mtr_flow_color(dr_rule, flow_conf[0]->init_color);
2110 : : }
2111 : : return 0;
2112 : : }
2113 : :
2114 : : static int
2115 : 0 : hws_table_tmpl_translate_indirect_meter(struct rte_eth_dev *dev,
2116 : : const struct rte_flow_action *action,
2117 : : const struct rte_flow_action *mask,
2118 : : struct mlx5_hw_actions *acts,
2119 : : uint16_t action_src, uint16_t action_dst)
2120 : : {
2121 : : int ret;
2122 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
2123 : 0 : const struct rte_flow_action_indirect_list *action_conf = action->conf;
2124 : 0 : const struct rte_flow_action_indirect_list *mask_conf = mask->conf;
2125 [ # # # # ]: 0 : bool is_handle_masked = mask_conf && mask_conf->handle;
2126 [ # # # # : 0 : bool is_conf_masked = mask_conf && mask_conf->conf && mask_conf->conf[0];
# # ]
2127 : 0 : struct mlx5dr_rule_action *dr_rule = &acts->rule_acts[action_dst];
2128 : :
2129 [ # # ]: 0 : if (is_handle_masked) {
2130 : 0 : ret = flow_dr_set_meter(priv, dr_rule, action->conf);
2131 [ # # ]: 0 : if (ret)
2132 : : return ret;
2133 : : }
2134 [ # # ]: 0 : if (is_conf_masked) {
2135 : : const struct
2136 : 0 : rte_flow_indirect_update_flow_meter_mark **flow_conf =
2137 : : (typeof(flow_conf))action_conf->conf;
2138 : : flow_dr_mtr_flow_color(dr_rule,
2139 [ # # ]: 0 : flow_conf[0]->init_color);
2140 : : }
2141 [ # # ]: 0 : if (!is_handle_masked || !is_conf_masked) {
2142 : : struct mlx5_action_construct_data *act_data;
2143 : :
2144 : : ret = flow_hw_act_data_indirect_list_append
2145 : : (priv, acts, RTE_FLOW_ACTION_TYPE_INDIRECT_LIST,
2146 : : action_src, action_dst, flow_hw_translate_indirect_meter);
2147 : : if (ret)
2148 : 0 : return ret;
2149 : : act_data = LIST_FIRST(&acts->act_list);
2150 : 0 : act_data->shared_meter.conf_masked = is_conf_masked;
2151 : : }
2152 : : return 0;
2153 : : }
2154 : :
2155 : : static int
2156 : : hws_table_tmpl_translate_indirect_legacy(struct rte_eth_dev *dev,
2157 : : const struct rte_flow_action *action,
2158 : : const struct rte_flow_action *mask,
2159 : : struct mlx5_hw_actions *acts,
2160 : : uint16_t action_src, uint16_t action_dst)
2161 : : {
2162 : : int ret;
2163 : : const struct rte_flow_action_indirect_list *indlst_conf = action->conf;
2164 : : struct mlx5_indlst_legacy *indlst_obj = (typeof(indlst_obj))indlst_conf->handle;
2165 : 0 : uint32_t act_idx = (uint32_t)(uintptr_t)indlst_obj->handle;
2166 : 0 : uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
2167 : :
2168 : 0 : switch (type) {
2169 : 0 : case MLX5_INDIRECT_ACTION_TYPE_METER_MARK:
2170 : 0 : ret = hws_table_tmpl_translate_indirect_meter(dev, action, mask,
2171 : : acts, action_src,
2172 : : action_dst);
2173 : 0 : break;
2174 : : default:
2175 : : ret = -EINVAL;
2176 : : break;
2177 : : }
2178 : : return ret;
2179 : : }
2180 : :
2181 : : /*
2182 : : * template .. indirect_list handle Ht conf Ct ..
2183 : : * mask .. indirect_list handle Hm conf Cm ..
2184 : : *
2185 : : * PMD requires Ht != 0 to resolve handle type.
2186 : : * If Ht was masked (Hm != 0) DR5 action will be set according to Ht and will
2187 : : * not change. Otherwise, DR5 action will be resolved during flow rule build.
2188 : : * If Ct was masked (Cm != 0), table template processing updates base
2189 : : * indirect action configuration with Ct parameters.
2190 : : */
2191 : : static int
2192 : 0 : table_template_translate_indirect_list(struct rte_eth_dev *dev,
2193 : : const struct rte_flow_action *action,
2194 : : const struct rte_flow_action *mask,
2195 : : struct mlx5_hw_actions *acts,
2196 : : uint16_t action_src, uint16_t action_dst)
2197 : : {
2198 : : int ret = 0;
2199 : : enum mlx5_indirect_list_type type;
2200 : 0 : const struct rte_flow_action_indirect_list *list_conf = action->conf;
2201 : :
2202 [ # # # # ]: 0 : if (!list_conf || !list_conf->handle)
2203 : : return -EINVAL;
2204 : : type = mlx5_get_indirect_list_type(list_conf->handle);
2205 [ # # # # ]: 0 : switch (type) {
2206 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY:
2207 [ # # ]: 0 : ret = hws_table_tmpl_translate_indirect_legacy(dev, action, mask,
2208 : : acts, action_src,
2209 : : action_dst);
2210 : : break;
2211 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR:
2212 : 0 : ret = hws_table_tmpl_translate_indirect_mirror(dev, action, mask,
2213 : : acts, action_src,
2214 : : action_dst);
2215 : 0 : break;
2216 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT:
2217 [ # # ]: 0 : if (list_conf->conf)
2218 : : return -EINVAL;
2219 : 0 : ret = hws_table_tmpl_translate_indirect_reformat(dev, action, mask,
2220 : : acts, action_src,
2221 : : action_dst);
2222 : 0 : break;
2223 : : default:
2224 : : return -EINVAL;
2225 : : }
2226 : : return ret;
2227 : : }
2228 : :
2229 : : static void
2230 : : mlx5_set_reformat_header(struct mlx5dr_action_reformat_header *hdr,
2231 : : uint8_t *encap_data,
2232 : : size_t data_size)
2233 : : {
2234 : 0 : hdr->sz = data_size;
2235 : 0 : hdr->data = encap_data;
2236 : : }
2237 : :
2238 : : static int
2239 [ # # ]: 0 : mlx5_tbl_translate_reformat(struct mlx5_priv *priv,
2240 : : struct mlx5_hw_actions *acts,
2241 : : struct rte_flow_actions_template *at,
2242 : : const struct rte_flow_item *enc_item,
2243 : : const struct rte_flow_item *enc_item_m,
2244 : : uint8_t *encap_data, uint8_t *encap_data_m,
2245 : : struct mlx5_tbl_multi_pattern_ctx *mp_ctx,
2246 : : size_t data_size, uint16_t reformat_src,
2247 : : enum mlx5dr_action_type refmt_type,
2248 : : struct rte_flow_error *error)
2249 : : {
2250 : : int mp_reformat_ix = mlx5_multi_pattern_reformat_to_index(refmt_type);
2251 : : struct mlx5dr_action_reformat_header hdr;
2252 : : uint8_t buf[MLX5_ENCAP_MAX_LEN];
2253 : : bool shared_rfmt = false;
2254 : : int ret;
2255 : :
2256 : : MLX5_ASSERT(at->reformat_off != UINT16_MAX);
2257 [ # # ]: 0 : if (enc_item) {
2258 : : MLX5_ASSERT(!encap_data);
2259 : 0 : ret = flow_dv_convert_encap_data(enc_item, buf, &data_size, error);
2260 [ # # ]: 0 : if (ret)
2261 : : return ret;
2262 : : encap_data = buf;
2263 [ # # ]: 0 : if (enc_item_m)
2264 : : shared_rfmt = true;
2265 [ # # ]: 0 : } else if (encap_data && encap_data_m) {
2266 : : shared_rfmt = true;
2267 : : }
2268 : 0 : acts->encap_decap = mlx5_malloc(MLX5_MEM_ZERO,
2269 : : sizeof(*acts->encap_decap) + data_size,
2270 : : 0, SOCKET_ID_ANY);
2271 [ # # ]: 0 : if (!acts->encap_decap)
2272 : 0 : return rte_flow_error_set(error, ENOMEM,
2273 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2274 : : NULL, "no memory for reformat context");
2275 : 0 : acts->encap_decap_pos = at->reformat_off;
2276 : 0 : acts->encap_decap->data_size = data_size;
2277 : 0 : acts->encap_decap->action_type = refmt_type;
2278 [ # # ]: 0 : if (shared_rfmt || mp_reformat_ix < 0) {
2279 : : uint16_t reformat_ix = at->reformat_off;
2280 : : /*
2281 : : * This copy is only needed in non template mode.
2282 : : * In order to create the action later.
2283 : : */
2284 : 0 : memcpy(acts->encap_decap->data, encap_data, data_size);
2285 : 0 : acts->rule_acts[reformat_ix].reformat.data = acts->encap_decap->data;
2286 : 0 : acts->rule_acts[reformat_ix].reformat.offset = 0;
2287 : 0 : acts->encap_decap->shared = true;
2288 : : } else {
2289 : : uint32_t ix;
2290 : 0 : typeof(mp_ctx->reformat[0]) *reformat = mp_ctx->reformat +
2291 : : mp_reformat_ix;
2292 : : mlx5_set_reformat_header(&hdr, encap_data, data_size);
2293 : 0 : ix = reformat->elements_num++;
2294 : 0 : reformat->reformat_hdr[ix] = hdr;
2295 : 0 : acts->rule_acts[at->reformat_off].reformat.hdr_idx = ix;
2296 : 0 : acts->encap_decap->multi_pattern = 1;
2297 : 0 : ret = __flow_hw_act_data_encap_append
2298 : 0 : (priv, acts, (at->actions + reformat_src)->type,
2299 : : reformat_src, at->reformat_off, data_size);
2300 : : if (ret)
2301 : 0 : return -rte_errno;
2302 : : mlx5_multi_pattern_activate(mp_ctx);
2303 : : }
2304 : : return 0;
2305 : : }
2306 : :
2307 : : static int
2308 : 0 : mlx5_tbl_create_reformat_action(struct mlx5_priv *priv,
2309 : : const struct rte_flow_template_table_attr *table_attr,
2310 : : struct mlx5_hw_actions *acts,
2311 : : struct rte_flow_actions_template *at,
2312 : : uint8_t *encap_data,
2313 : : size_t data_size,
2314 : : enum mlx5dr_action_type refmt_type)
2315 : : {
2316 : 0 : const struct rte_flow_attr *attr = &table_attr->flow_attr;
2317 : : bool unified_fdb = is_unified_fdb(priv);
2318 : 0 : enum mlx5dr_table_type tbl_type = get_mlx5dr_table_type(attr, table_attr->specialize,
2319 : : unified_fdb);
2320 : : struct mlx5dr_action_reformat_header hdr;
2321 : :
2322 : : mlx5_set_reformat_header(&hdr, encap_data, data_size);
2323 : 0 : uint16_t reformat_ix = at->reformat_off;
2324 : 0 : uint32_t flags = mlx5_hw_act_flag[!!attr->group][tbl_type] |
2325 : : MLX5DR_ACTION_FLAG_SHARED;
2326 : :
2327 : 0 : acts->encap_decap->action = mlx5dr_action_create_reformat(priv->dr_ctx, refmt_type,
2328 : : 1, &hdr, 0, flags);
2329 [ # # ]: 0 : if (!acts->encap_decap->action)
2330 : 0 : return -rte_errno;
2331 : 0 : acts->rule_acts[reformat_ix].action = acts->encap_decap->action;
2332 : 0 : return 0;
2333 : : }
2334 : :
2335 : : static int
2336 : 0 : mlx5_tbl_translate_modify_header(struct rte_eth_dev *dev,
2337 : : const struct mlx5_flow_template_table_cfg *cfg,
2338 : : struct mlx5_hw_actions *acts,
2339 : : struct mlx5_tbl_multi_pattern_ctx *mp_ctx,
2340 : : struct mlx5_hw_modify_header_action *mhdr,
2341 : : struct rte_flow_error *error)
2342 : : {
2343 : 0 : uint16_t mhdr_ix = mhdr->pos;
2344 : : struct mlx5dr_action_mh_pattern pattern = {
2345 : 0 : .sz = sizeof(struct mlx5_modification_cmd) * mhdr->mhdr_cmds_num
2346 : : };
2347 : :
2348 [ # # ]: 0 : if (flow_hw_validate_compiled_modify_field(dev, cfg, mhdr, error)) {
2349 : : __flow_hw_action_template_destroy(dev, acts);
2350 : 0 : return -rte_errno;
2351 : : }
2352 : 0 : acts->mhdr = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*acts->mhdr),
2353 : : 0, SOCKET_ID_ANY);
2354 [ # # ]: 0 : if (!acts->mhdr)
2355 : 0 : return rte_flow_error_set(error, ENOMEM,
2356 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2357 : : NULL, "translate modify_header: no memory for modify header context");
2358 : : rte_memcpy(acts->mhdr, mhdr, sizeof(*mhdr));
2359 [ # # ]: 0 : if (!mhdr->shared) {
2360 : 0 : pattern.data = (__be64 *)acts->mhdr->mhdr_cmds;
2361 : : typeof(mp_ctx->mh) *mh = &mp_ctx->mh;
2362 : 0 : uint32_t idx = mh->elements_num;
2363 : 0 : mh->pattern[mh->elements_num++] = pattern;
2364 : 0 : acts->mhdr->multi_pattern = 1;
2365 : 0 : acts->rule_acts[mhdr_ix].modify_header.pattern_idx = idx;
2366 : : mlx5_multi_pattern_activate(mp_ctx);
2367 : : }
2368 : : return 0;
2369 : : }
2370 : :
2371 : : static int
2372 : 0 : mlx5_tbl_ensure_shared_modify_header(struct rte_eth_dev *dev,
2373 : : const struct mlx5_flow_template_table_cfg *cfg,
2374 : : struct mlx5_hw_actions *acts,
2375 : : struct rte_flow_error *error)
2376 : : {
2377 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
2378 : : bool unified_fdb = is_unified_fdb(priv);
2379 : : const struct rte_flow_template_table_attr *table_attr = &cfg->attr;
2380 : 0 : const struct rte_flow_attr *attr = &table_attr->flow_attr;
2381 : 0 : enum mlx5dr_table_type tbl_type = get_mlx5dr_table_type(attr, table_attr->specialize,
2382 : : unified_fdb);
2383 : 0 : struct mlx5dr_action_mh_pattern pattern = {
2384 : 0 : .sz = sizeof(struct mlx5_modification_cmd) * acts->mhdr->mhdr_cmds_num
2385 : : };
2386 : 0 : uint16_t mhdr_ix = acts->mhdr->pos;
2387 : 0 : uint32_t flags = mlx5_hw_act_flag[!!attr->group][tbl_type] | MLX5DR_ACTION_FLAG_SHARED;
2388 : :
2389 : 0 : pattern.data = (__be64 *)acts->mhdr->mhdr_cmds;
2390 : 0 : acts->mhdr->action = mlx5dr_action_create_modify_header(priv->dr_ctx, 1,
2391 : : &pattern, 0, flags);
2392 [ # # ]: 0 : if (!acts->mhdr->action)
2393 : 0 : return rte_flow_error_set(error, rte_errno,
2394 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2395 : : "translate modify_header: failed to create DR action");
2396 : 0 : acts->rule_acts[mhdr_ix].action = acts->mhdr->action;
2397 : 0 : return 0;
2398 : : }
2399 : :
2400 : : static int
2401 : 0 : mlx5_create_ipv6_ext_reformat(struct rte_eth_dev *dev,
2402 : : const struct mlx5_flow_template_table_cfg *cfg,
2403 : : struct mlx5_hw_actions *acts,
2404 : : struct rte_flow_actions_template *at,
2405 : : uint8_t *push_data, uint8_t *push_data_m,
2406 : : size_t push_size, uint16_t recom_src,
2407 : : enum mlx5dr_action_type recom_type)
2408 : : {
2409 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
2410 : : bool unified_fdb = is_unified_fdb(priv);
2411 : : const struct rte_flow_template_table_attr *table_attr = &cfg->attr;
2412 : 0 : const struct rte_flow_attr *attr = &table_attr->flow_attr;
2413 : : enum mlx5dr_table_type type =
2414 : 0 : get_mlx5dr_table_type(attr, table_attr->specialize, unified_fdb);
2415 : : struct mlx5_action_construct_data *act_data;
2416 : 0 : struct mlx5dr_action_reformat_header hdr = {0};
2417 : : uint32_t flag, bulk = 0;
2418 : :
2419 : 0 : flag = mlx5_hw_act_flag[!!attr->group][type];
2420 : 0 : acts->push_remove = mlx5_malloc(MLX5_MEM_ZERO,
2421 : : sizeof(*acts->push_remove) + push_size,
2422 : : 0, SOCKET_ID_ANY);
2423 [ # # ]: 0 : if (!acts->push_remove)
2424 : : return -ENOMEM;
2425 : :
2426 [ # # # ]: 0 : switch (recom_type) {
2427 : 0 : case MLX5DR_ACTION_TYP_PUSH_IPV6_ROUTE_EXT:
2428 [ # # ]: 0 : if (!push_data || !push_size)
2429 : 0 : goto err1;
2430 [ # # ]: 0 : if (!push_data_m) {
2431 [ # # ]: 0 : bulk = rte_log2_u32(table_attr->nb_flows);
2432 : : } else {
2433 : 0 : flag |= MLX5DR_ACTION_FLAG_SHARED;
2434 : 0 : acts->push_remove->shared = 1;
2435 : : }
2436 : 0 : acts->push_remove->data_size = push_size;
2437 : 0 : memcpy(acts->push_remove->data, push_data, push_size);
2438 : 0 : hdr.data = push_data;
2439 : 0 : hdr.sz = push_size;
2440 : 0 : break;
2441 : 0 : case MLX5DR_ACTION_TYP_POP_IPV6_ROUTE_EXT:
2442 : 0 : flag |= MLX5DR_ACTION_FLAG_SHARED;
2443 : 0 : acts->push_remove->shared = 1;
2444 : 0 : break;
2445 : : default:
2446 : : break;
2447 : : }
2448 : :
2449 : 0 : acts->push_remove->action =
2450 : 0 : mlx5dr_action_create_reformat_ipv6_ext(priv->dr_ctx,
2451 : : recom_type, &hdr, bulk, flag);
2452 [ # # ]: 0 : if (!acts->push_remove->action)
2453 : 0 : goto err1;
2454 : 0 : acts->rule_acts[at->recom_off].action = acts->push_remove->action;
2455 : 0 : acts->rule_acts[at->recom_off].ipv6_ext.header = acts->push_remove->data;
2456 : 0 : acts->rule_acts[at->recom_off].ipv6_ext.offset = 0;
2457 : 0 : acts->push_remove_pos = at->recom_off;
2458 [ # # ]: 0 : if (!acts->push_remove->shared) {
2459 : 0 : act_data = __flow_hw_act_data_push_append(dev, acts,
2460 : : RTE_FLOW_ACTION_TYPE_IPV6_EXT_PUSH,
2461 : : recom_src, at->recom_off, push_size);
2462 : : if (!act_data)
2463 : 0 : goto err;
2464 : : }
2465 : : return 0;
2466 : : err:
2467 [ # # ]: 0 : if (acts->push_remove->action)
2468 : 0 : mlx5dr_action_destroy(acts->push_remove->action);
2469 : 0 : err1:
2470 [ # # ]: 0 : if (acts->push_remove) {
2471 : 0 : mlx5_free(acts->push_remove);
2472 : 0 : acts->push_remove = NULL;
2473 : : }
2474 : : return -EINVAL;
2475 : : }
2476 : :
2477 : : /**
2478 : : * Translate rte_flow actions to DR action.
2479 : : *
2480 : : * As the action template has already indicated the actions. Translate
2481 : : * the rte_flow actions to DR action if possbile. So in flow create
2482 : : * stage we will save cycles from handing the actions' organizing.
2483 : : * For the actions with limited information, need to add these to a
2484 : : * list.
2485 : : *
2486 : : * @param[in] dev
2487 : : * Pointer to the rte_eth_dev structure.
2488 : : * @param[in] cfg
2489 : : * Pointer to the table configuration.
2490 : : * @param[in/out] acts
2491 : : * Pointer to the template HW steering DR actions.
2492 : : * @param[in] at
2493 : : * Action template.
2494 : : * @param[in] nt_mode
2495 : : * Non template rule translate.
2496 : : * @param[out] error
2497 : : * Pointer to error structure.
2498 : : *
2499 : : * @return
2500 : : * 0 on success, a negative errno otherwise and rte_errno is set.
2501 : : */
2502 : : static int
2503 : 0 : __flow_hw_translate_actions_template(struct rte_eth_dev *dev,
2504 : : const struct mlx5_flow_template_table_cfg *cfg,
2505 : : struct mlx5_hw_actions *acts,
2506 : : struct rte_flow_actions_template *at,
2507 : : struct mlx5_tbl_multi_pattern_ctx *mp_ctx,
2508 : : bool nt_mode,
2509 : : struct rte_flow_error *error)
2510 : : {
2511 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
2512 : 0 : struct mlx5_hca_attr *hca_attr = &priv->sh->cdev->config.hca_attr;
2513 : 0 : const struct rte_flow_template_table_attr *table_attr = &cfg->attr;
2514 : 0 : const struct rte_flow_attr *attr = &table_attr->flow_attr;
2515 : 0 : struct rte_flow_action *actions = at->actions;
2516 : 0 : struct rte_flow_action *masks = at->masks;
2517 : : enum mlx5dr_action_type refmt_type = MLX5DR_ACTION_TYP_LAST;
2518 : : enum mlx5dr_action_type recom_type = MLX5DR_ACTION_TYP_LAST;
2519 : : const struct rte_flow_action_raw_encap *raw_encap_data;
2520 : : const struct rte_flow_action_ipv6_ext_push *ipv6_ext_data;
2521 : : const struct rte_flow_item *enc_item = NULL, *enc_item_m = NULL;
2522 : : uint16_t reformat_src = 0, recom_src = 0;
2523 : : uint8_t *encap_data = NULL, *encap_data_m = NULL;
2524 : : uint8_t *push_data = NULL, *push_data_m = NULL;
2525 : : size_t data_size = 0, push_size = 0;
2526 : : struct mlx5_hw_modify_header_action mhdr = { 0 };
2527 : 0 : struct rte_flow_error sub_error = {
2528 : : .type = RTE_FLOW_ERROR_TYPE_NONE,
2529 : : .cause = NULL,
2530 : : .message = NULL,
2531 : : };
2532 : : bool actions_end = false;
2533 : : uint32_t type;
2534 : : bool reformat_used = false;
2535 : : bool recom_used = false;
2536 : : unsigned int of_vlan_offset;
2537 : : uint16_t jump_pos;
2538 : : uint32_t ct_idx;
2539 : : int ret, err;
2540 : 0 : uint32_t target_grp = 0;
2541 : : bool unified_fdb = is_unified_fdb(priv);
2542 : :
2543 : : flow_hw_modify_field_init(&mhdr, at);
2544 : 0 : type = get_mlx5dr_table_type(attr, cfg->attr.specialize, unified_fdb);
2545 [ # # ]: 0 : for (; !actions_end; actions++, masks++) {
2546 : 0 : uint64_t pos = actions - at->actions;
2547 : 0 : uint16_t src_pos = pos - at->src_off[pos];
2548 : 0 : uint16_t dr_pos = at->dr_off[pos];
2549 : :
2550 [ # # # # : 0 : switch ((int)actions->type) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
2551 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT_LIST:
2552 [ # # ]: 0 : if (!attr->group) {
2553 : 0 : DRV_LOG(ERR, "Indirect action is not supported in root table.");
2554 : 0 : goto err;
2555 : : }
2556 : 0 : ret = table_template_translate_indirect_list
2557 : : (dev, actions, masks, acts, src_pos, dr_pos);
2558 [ # # ]: 0 : if (ret)
2559 : 0 : goto err;
2560 : : break;
2561 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT:
2562 [ # # ]: 0 : if (!attr->group) {
2563 : 0 : DRV_LOG(ERR, "Indirect action is not supported in root table.");
2564 : 0 : goto err;
2565 : : }
2566 [ # # # # ]: 0 : if (actions->conf && masks->conf) {
2567 [ # # # # : 0 : if (flow_hw_shared_action_translate
# # # ]
2568 : : (dev, actions, acts, src_pos, dr_pos))
2569 : 0 : goto err;
2570 : 0 : } else if (__flow_hw_act_data_indirect_append
2571 : : (priv, acts, RTE_FLOW_ACTION_TYPE_INDIRECT,
2572 : : masks->type, src_pos, dr_pos)){
2573 : 0 : goto err;
2574 : : }
2575 : : break;
2576 : : case RTE_FLOW_ACTION_TYPE_VOID:
2577 : : break;
2578 : 0 : case RTE_FLOW_ACTION_TYPE_DROP:
2579 : 0 : acts->rule_acts[dr_pos].action =
2580 : 0 : priv->hw_drop[!!attr->group];
2581 : 0 : break;
2582 : 0 : case RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:
2583 [ # # ]: 0 : if (!attr->group) {
2584 : 0 : DRV_LOG(ERR, "Port representor is not supported in root table.");
2585 : 0 : goto err;
2586 : : }
2587 : 0 : acts->rule_acts[dr_pos].action = priv->hw_def_miss;
2588 : 0 : break;
2589 : 0 : case RTE_FLOW_ACTION_TYPE_FLAG:
2590 : 0 : acts->mark = true;
2591 : 0 : acts->rule_acts[dr_pos].tag.value =
2592 : : mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
2593 : 0 : acts->rule_acts[dr_pos].action =
2594 : 0 : priv->hw_tag[!!attr->group];
2595 : 0 : rte_atomic_fetch_add_explicit(&priv->hws_mark_refcnt, 1,
2596 : : rte_memory_order_relaxed);
2597 : 0 : flow_hw_rxq_flag_set(dev, true);
2598 : 0 : break;
2599 : 0 : case RTE_FLOW_ACTION_TYPE_MARK:
2600 : 0 : acts->mark = true;
2601 [ # # ]: 0 : if (masks->conf &&
2602 : : ((const struct rte_flow_action_mark *)
2603 [ # # ]: 0 : masks->conf)->id)
2604 : 0 : acts->rule_acts[dr_pos].tag.value =
2605 : : mlx5_flow_mark_set
2606 : : (((const struct rte_flow_action_mark *)
2607 [ # # ]: 0 : (actions->conf))->id);
2608 : : else if (__flow_hw_act_data_general_append(priv, acts,
2609 : : actions->type,
2610 : : src_pos, dr_pos))
2611 : 0 : goto err;
2612 : 0 : acts->rule_acts[dr_pos].action =
2613 : 0 : priv->hw_tag[!!attr->group];
2614 : 0 : rte_atomic_fetch_add_explicit(&priv->hws_mark_refcnt, 1,
2615 : : rte_memory_order_relaxed);
2616 : 0 : flow_hw_rxq_flag_set(dev, true);
2617 : 0 : break;
2618 : 0 : case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
2619 : 0 : acts->rule_acts[dr_pos].action =
2620 : 0 : priv->hw_push_vlan[type];
2621 [ # # # # ]: 0 : if (is_template_masked_push_vlan(masks->conf))
2622 : 0 : acts->rule_acts[dr_pos].push_vlan.vlan_hdr =
2623 : : vlan_hdr_to_be32(actions);
2624 : : else if (__flow_hw_act_data_general_append
2625 : : (priv, acts, actions->type,
2626 : : src_pos, dr_pos))
2627 : 0 : goto err;
2628 : : of_vlan_offset = is_of_vlan_pcp_present(actions) ?
2629 [ # # ]: 0 : MLX5_HW_VLAN_PUSH_PCP_IDX :
2630 : : MLX5_HW_VLAN_PUSH_VID_IDX;
2631 : 0 : actions += of_vlan_offset;
2632 : 0 : masks += of_vlan_offset;
2633 : 0 : break;
2634 : 0 : case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
2635 : 0 : acts->rule_acts[dr_pos].action =
2636 : 0 : priv->hw_pop_vlan[type];
2637 : 0 : break;
2638 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP:
2639 [ # # ]: 0 : if (masks->conf &&
2640 : : ((const struct rte_flow_action_jump *)
2641 [ # # ]: 0 : masks->conf)->group) {
2642 : 0 : uint32_t jump_group =
2643 : : ((const struct rte_flow_action_jump *)
2644 : 0 : actions->conf)->group;
2645 : 0 : acts->jump = flow_hw_jump_action_register
2646 : : (dev, cfg, jump_group, &sub_error);
2647 [ # # ]: 0 : if (!acts->jump)
2648 : 0 : goto err;
2649 : 0 : acts->rule_acts[dr_pos].action = (!!attr->group) ?
2650 [ # # ]: 0 : acts->jump->hws_action :
2651 : : acts->jump->root_action;
2652 : : } else if (__flow_hw_act_data_general_append
2653 : : (priv, acts, actions->type,
2654 : : src_pos, dr_pos)){
2655 : 0 : goto err;
2656 : : }
2657 : : break;
2658 : 0 : case RTE_FLOW_ACTION_TYPE_QUEUE:
2659 [ # # ]: 0 : if (masks->conf &&
2660 : : ((const struct rte_flow_action_queue *)
2661 [ # # ]: 0 : masks->conf)->index) {
2662 : 0 : acts->tir = flow_hw_tir_action_register
2663 : 0 : (dev, mlx5_hw_act_flag[!!attr->group][type],
2664 : : actions);
2665 [ # # ]: 0 : if (!acts->tir)
2666 : 0 : goto err;
2667 : 0 : acts->rule_acts[dr_pos].action =
2668 : 0 : acts->tir->action;
2669 : : } else if (__flow_hw_act_data_general_append
2670 : : (priv, acts, actions->type,
2671 : : src_pos, dr_pos)) {
2672 : 0 : goto err;
2673 : : }
2674 : : break;
2675 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
2676 [ # # # # ]: 0 : if (actions->conf && masks->conf) {
2677 : 0 : acts->tir = flow_hw_tir_action_register
2678 : 0 : (dev, mlx5_hw_act_flag[!!attr->group][type],
2679 : : actions);
2680 [ # # ]: 0 : if (!acts->tir)
2681 : 0 : goto err;
2682 : 0 : acts->rule_acts[dr_pos].action =
2683 : 0 : acts->tir->action;
2684 : : } else if (__flow_hw_act_data_general_append
2685 : : (priv, acts, actions->type,
2686 : : src_pos, dr_pos)) {
2687 : 0 : goto err;
2688 : : }
2689 : : break;
2690 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
2691 : : MLX5_ASSERT(!reformat_used);
2692 : 0 : enc_item = MLX5_CONST_ENCAP_ITEM(rte_flow_action_vxlan_encap,
2693 : : actions->conf);
2694 [ # # ]: 0 : if (masks->conf)
2695 : 0 : enc_item_m = MLX5_CONST_ENCAP_ITEM(rte_flow_action_vxlan_encap,
2696 : : masks->conf);
2697 : : reformat_used = true;
2698 : : reformat_src = src_pos;
2699 : : refmt_type = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;
2700 : : break;
2701 : 0 : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
2702 : : MLX5_ASSERT(!reformat_used);
2703 : 0 : enc_item = MLX5_CONST_ENCAP_ITEM(rte_flow_action_nvgre_encap,
2704 : : actions->conf);
2705 [ # # ]: 0 : if (masks->conf)
2706 : 0 : enc_item_m = MLX5_CONST_ENCAP_ITEM(rte_flow_action_nvgre_encap,
2707 : : masks->conf);
2708 : : reformat_used = true;
2709 : : reformat_src = src_pos;
2710 : : refmt_type = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;
2711 : : break;
2712 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
2713 : 0 : raw_encap_data =
2714 : : (const struct rte_flow_action_raw_encap *)
2715 : : masks->conf;
2716 [ # # ]: 0 : if (raw_encap_data)
2717 : 0 : encap_data_m = raw_encap_data->data;
2718 : 0 : raw_encap_data =
2719 : : (const struct rte_flow_action_raw_encap *)
2720 : : actions->conf;
2721 : 0 : encap_data = raw_encap_data->data;
2722 : 0 : data_size = raw_encap_data->size;
2723 [ # # ]: 0 : if (reformat_used) {
2724 : : refmt_type = data_size <
2725 : : MLX5_ENCAPSULATION_DECISION_SIZE ?
2726 [ # # ]: 0 : MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2 :
2727 : : MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3;
2728 : : } else {
2729 : : reformat_used = true;
2730 : : refmt_type =
2731 : : MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;
2732 : : }
2733 : : reformat_src = src_pos;
2734 : : break;
2735 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
2736 : : case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
2737 : : MLX5_ASSERT(!reformat_used);
2738 : : reformat_used = true;
2739 : : refmt_type = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2;
2740 : 0 : break;
2741 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
2742 : : reformat_used = true;
2743 : : refmt_type = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2;
2744 : 0 : break;
2745 : 0 : case RTE_FLOW_ACTION_TYPE_IPV6_EXT_PUSH:
2746 [ # # ]: 0 : if (!hca_attr->flex.query_match_sample_info ||
2747 : 0 : !hca_attr->flex.parse_graph_anchor ||
2748 [ # # ]: 0 : !priv->sh->srh_flex_parser.flex.mapnum) {
2749 : 0 : DRV_LOG(ERR, "SRv6 anchor is not supported.");
2750 : 0 : goto err;
2751 : : }
2752 : : MLX5_ASSERT(!recom_used && !recom_type);
2753 : : recom_used = true;
2754 : : recom_type = MLX5DR_ACTION_TYP_PUSH_IPV6_ROUTE_EXT;
2755 : 0 : ipv6_ext_data =
2756 : : (const struct rte_flow_action_ipv6_ext_push *)masks->conf;
2757 [ # # ]: 0 : if (ipv6_ext_data)
2758 : 0 : push_data_m = ipv6_ext_data->data;
2759 : 0 : ipv6_ext_data =
2760 : : (const struct rte_flow_action_ipv6_ext_push *)actions->conf;
2761 [ # # ]: 0 : if (ipv6_ext_data) {
2762 : 0 : push_data = ipv6_ext_data->data;
2763 : 0 : push_size = ipv6_ext_data->size;
2764 : : }
2765 : : recom_src = src_pos;
2766 : : break;
2767 : 0 : case RTE_FLOW_ACTION_TYPE_IPV6_EXT_REMOVE:
2768 [ # # ]: 0 : if (!hca_attr->flex.query_match_sample_info ||
2769 : 0 : !hca_attr->flex.parse_graph_anchor ||
2770 [ # # ]: 0 : !priv->sh->srh_flex_parser.flex.mapnum) {
2771 : 0 : DRV_LOG(ERR, "SRv6 anchor is not supported.");
2772 : 0 : goto err;
2773 : : }
2774 : : recom_used = true;
2775 : : recom_type = MLX5DR_ACTION_TYP_POP_IPV6_ROUTE_EXT;
2776 : : break;
2777 : 0 : case RTE_FLOW_ACTION_TYPE_SEND_TO_KERNEL:
2778 : 0 : ret = flow_hw_translate_group(dev, cfg, attr->group,
2779 : : &target_grp, &sub_error);
2780 [ # # ]: 0 : if (ret)
2781 : 0 : goto err;
2782 [ # # ]: 0 : if (target_grp == 0) {
2783 : : __flow_hw_action_template_destroy(dev, acts);
2784 : 0 : rte_flow_error_set(&sub_error, ENOTSUP,
2785 : : RTE_FLOW_ERROR_TYPE_ACTION,
2786 : : NULL,
2787 : : "Send to kernel action on root table is not supported in HW steering mode");
2788 : 0 : goto err;
2789 : : }
2790 : 0 : acts->rule_acts[dr_pos].action = priv->hw_send_to_kernel[type];
2791 : 0 : break;
2792 [ # # ]: 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
2793 : : err = flow_hw_modify_field_compile(dev, attr, actions,
2794 : : masks, acts, &mhdr,
2795 : : src_pos, &sub_error);
2796 [ # # ]: 0 : if (err)
2797 : 0 : goto err;
2798 : : break;
2799 : 0 : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
2800 [ # # ]: 0 : if (flow_hw_represented_port_compile
2801 : : (dev, attr, actions,
2802 : : masks, acts, src_pos, dr_pos, &sub_error))
2803 : 0 : goto err;
2804 : : break;
2805 : 0 : case RTE_FLOW_ACTION_TYPE_METER:
2806 : : /*
2807 : : * METER action is compiled to 2 DR actions - ASO_METER and FT.
2808 : : * Calculated DR offset is stored only for ASO_METER and FT
2809 : : * is assumed to be the next action.
2810 : : */
2811 : 0 : jump_pos = dr_pos + 1;
2812 [ # # # # ]: 0 : if (actions->conf && masks->conf &&
2813 : : ((const struct rte_flow_action_meter *)
2814 [ # # ]: 0 : masks->conf)->mtr_id) {
2815 : 0 : err = flow_hw_meter_compile(dev, cfg,
2816 : : dr_pos, jump_pos, actions, acts,
2817 : : &sub_error);
2818 : : if (err)
2819 : 0 : goto err;
2820 : : } else if (__flow_hw_act_data_general_append(priv, acts,
2821 : : actions->type,
2822 : : src_pos,
2823 : : dr_pos))
2824 : 0 : goto err;
2825 : : break;
2826 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
2827 : 0 : ret = flow_hw_translate_group(dev, cfg, attr->group,
2828 : : &target_grp, &sub_error);
2829 [ # # ]: 0 : if (ret)
2830 : 0 : goto err;
2831 [ # # ]: 0 : if (target_grp == 0) {
2832 : : __flow_hw_action_template_destroy(dev, acts);
2833 : 0 : rte_flow_error_set(&sub_error, ENOTSUP,
2834 : : RTE_FLOW_ERROR_TYPE_ACTION,
2835 : : NULL,
2836 : : "Age action on root table is not supported in HW steering mode");
2837 : 0 : goto err;
2838 : : }
2839 : 0 : if (__flow_hw_act_data_general_append(priv, acts,
2840 : : actions->type,
2841 : : src_pos,
2842 : : dr_pos))
2843 : 0 : goto err;
2844 : : break;
2845 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
2846 : 0 : ret = flow_hw_translate_group(dev, cfg, attr->group,
2847 : : &target_grp, &sub_error);
2848 [ # # ]: 0 : if (ret)
2849 : 0 : goto err;
2850 [ # # ]: 0 : if (target_grp == 0) {
2851 : : __flow_hw_action_template_destroy(dev, acts);
2852 : 0 : rte_flow_error_set(&sub_error, ENOTSUP,
2853 : : RTE_FLOW_ERROR_TYPE_ACTION,
2854 : : NULL,
2855 : : "Counter action on root table is not supported in HW steering mode");
2856 : 0 : goto err;
2857 : : }
2858 [ # # ]: 0 : if ((at->action_flags & MLX5_FLOW_ACTION_AGE) ||
2859 : : (at->action_flags & MLX5_FLOW_ACTION_INDIRECT_AGE))
2860 : : /*
2861 : : * When both COUNT and AGE are requested, it is
2862 : : * saved as AGE action which creates also the
2863 : : * counter.
2864 : : */
2865 : : break;
2866 [ # # ]: 0 : if (masks->conf &&
2867 : : ((const struct rte_flow_action_count *)
2868 [ # # ]: 0 : masks->conf)->id) {
2869 [ # # ]: 0 : err = flow_hw_cnt_compile(dev, dr_pos, acts);
2870 : : if (err)
2871 : 0 : goto err;
2872 : 0 : } else if (__flow_hw_act_data_general_append
2873 : : (priv, acts, actions->type,
2874 : : src_pos, dr_pos)) {
2875 : 0 : goto err;
2876 : : }
2877 : : break;
2878 : 0 : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
2879 [ # # ]: 0 : if (masks->conf) {
2880 : 0 : ct_idx = MLX5_INDIRECT_ACTION_IDX_GET(actions->conf);
2881 : : if (flow_hw_ct_compile(dev, MLX5_HW_INV_QUEUE, ct_idx,
2882 : 0 : &acts->rule_acts[dr_pos]))
2883 : 0 : goto err;
2884 : : } else if (__flow_hw_act_data_general_append
2885 : : (priv, acts, actions->type,
2886 : : src_pos, dr_pos)) {
2887 : 0 : goto err;
2888 : : }
2889 : : break;
2890 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
2891 [ # # # # ]: 0 : if (actions->conf && masks->conf &&
2892 : : ((const struct rte_flow_action_meter_mark *)
2893 [ # # ]: 0 : masks->conf)->profile) {
2894 : : err = flow_hw_meter_mark_compile(dev,
2895 : : dr_pos, actions,
2896 : 0 : acts->rule_acts,
2897 : : &acts->mtr_id,
2898 : : MLX5_HW_INV_QUEUE,
2899 : : &sub_error);
2900 : : if (err)
2901 : 0 : goto err;
2902 : : } else if (__flow_hw_act_data_general_append(priv, acts,
2903 : : actions->type,
2904 : : src_pos,
2905 : : dr_pos))
2906 : 0 : goto err;
2907 : : break;
2908 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
2909 : : /* Internal, can be skipped. */
2910 [ # # ]: 0 : if (!!attr->group) {
2911 : 0 : DRV_LOG(ERR, "DEFAULT MISS action is only"
2912 : : " supported in root table.");
2913 : 0 : goto err;
2914 : : }
2915 : 0 : acts->rule_acts[dr_pos].action = priv->hw_def_miss;
2916 : 0 : break;
2917 : 0 : case RTE_FLOW_ACTION_TYPE_NAT64:
2918 [ # # ]: 0 : if (masks->conf &&
2919 [ # # ]: 0 : ((const struct rte_flow_action_nat64 *)masks->conf)->type) {
2920 : 0 : const struct rte_flow_action_nat64 *nat64_c =
2921 : : (const struct rte_flow_action_nat64 *)actions->conf;
2922 : :
2923 : 0 : acts->rule_acts[dr_pos].action =
2924 : 0 : priv->action_nat64[type][nat64_c->type];
2925 : : } else if (__flow_hw_act_data_general_append(priv, acts,
2926 : : actions->type,
2927 : : src_pos, dr_pos))
2928 : 0 : goto err;
2929 : : break;
2930 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
2931 [ # # ]: 0 : if (masks->conf &&
2932 : : ((const struct rte_flow_action_jump_to_table_index *)
2933 [ # # ]: 0 : masks->conf)->table) {
2934 : 0 : struct rte_flow_template_table *jump_table =
2935 : : ((const struct rte_flow_action_jump_to_table_index *)
2936 : 0 : actions->conf)->table;
2937 : 0 : acts->rule_acts[dr_pos].jump_to_matcher.offset =
2938 : : ((const struct rte_flow_action_jump_to_table_index *)
2939 : 0 : actions->conf)->index;
2940 [ # # ]: 0 : if (likely(!rte_flow_template_table_resizable(dev->data->port_id,
2941 : : &jump_table->cfg.attr))) {
2942 : 0 : acts->rule_acts[dr_pos].action =
2943 : 0 : jump_table->matcher_info[0].jump;
2944 : : } else {
2945 : : uint32_t selector;
2946 : 0 : rte_rwlock_read_lock(&jump_table->matcher_replace_rwlk);
2947 : 0 : selector = jump_table->matcher_selector;
2948 : 0 : acts->rule_acts[dr_pos].action =
2949 : 0 : jump_table->matcher_info[selector].jump;
2950 : : rte_rwlock_read_unlock(&jump_table->matcher_replace_rwlk);
2951 : : }
2952 : : } else if (__flow_hw_act_data_general_append
2953 : : (priv, acts, actions->type,
2954 : : src_pos, dr_pos)){
2955 : 0 : goto err;
2956 : : }
2957 : : break;
2958 : 0 : case RTE_FLOW_ACTION_TYPE_END:
2959 : : actions_end = true;
2960 : 0 : break;
2961 : : default:
2962 : : break;
2963 : : }
2964 : : }
2965 [ # # ]: 0 : if (mhdr.pos != UINT16_MAX) {
2966 : 0 : ret = mlx5_tbl_translate_modify_header(dev, cfg, acts, mp_ctx, &mhdr, &sub_error);
2967 [ # # ]: 0 : if (ret)
2968 : 0 : goto err;
2969 [ # # # # ]: 0 : if (!nt_mode && mhdr.shared) {
2970 : 0 : ret = mlx5_tbl_ensure_shared_modify_header(dev, cfg, acts, &sub_error);
2971 [ # # ]: 0 : if (ret)
2972 : 0 : goto err;
2973 : : }
2974 : : }
2975 [ # # ]: 0 : if (reformat_used) {
2976 : 0 : ret = mlx5_tbl_translate_reformat(priv, acts, at,
2977 : : enc_item, enc_item_m,
2978 : : encap_data, encap_data_m,
2979 : : mp_ctx, data_size,
2980 : : reformat_src,
2981 : : refmt_type, &sub_error);
2982 [ # # ]: 0 : if (ret)
2983 : 0 : goto err;
2984 [ # # # # ]: 0 : if (!nt_mode && acts->encap_decap->shared) {
2985 : 0 : ret = mlx5_tbl_create_reformat_action(priv, table_attr, acts, at,
2986 : : encap_data, data_size,
2987 : : refmt_type);
2988 [ # # ]: 0 : if (ret)
2989 : 0 : goto err;
2990 : : }
2991 : : }
2992 [ # # ]: 0 : if (recom_used) {
2993 : : MLX5_ASSERT(at->recom_off != UINT16_MAX);
2994 : 0 : ret = mlx5_create_ipv6_ext_reformat(dev, cfg, acts, at, push_data,
2995 : : push_data_m, push_size, recom_src,
2996 : : recom_type);
2997 [ # # ]: 0 : if (ret)
2998 : 0 : goto err;
2999 : : }
3000 : : return 0;
3001 : 0 : err:
3002 : : /* If rte_errno was not initialized and reached error state. */
3003 [ # # ]: 0 : if (!rte_errno)
3004 : 0 : rte_errno = EINVAL;
3005 : 0 : err = rte_errno;
3006 : : __flow_hw_action_template_destroy(dev, acts);
3007 [ # # # # ]: 0 : if (error != NULL && sub_error.type != RTE_FLOW_ERROR_TYPE_NONE) {
3008 : : rte_memcpy(error, &sub_error, sizeof(sub_error));
3009 : 0 : return -EINVAL;
3010 : : }
3011 : 0 : return rte_flow_error_set(error, err,
3012 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3013 : : "fail to create rte table");
3014 : : }
3015 : :
3016 : : /**
3017 : : * Translate rte_flow actions to DR action.
3018 : : *
3019 : : * As the action template has already indicated the actions. Translate
3020 : : * the rte_flow actions to DR action if possible. So in flow create
3021 : : * stage we will save cycles from handing the actions' organizing.
3022 : : * For the actions with limited information, need to add these to a
3023 : : * list.
3024 : : *
3025 : : * @param[in] dev
3026 : : * Pointer to the rte_eth_dev structure.
3027 : : * @param[in] cfg
3028 : : * Pointer to the table configuration.
3029 : : * @param[in/out] acts
3030 : : * Pointer to the template HW steering DR actions.
3031 : : * @param[in] at
3032 : : * Action template.
3033 : : * @param[out] error
3034 : : * Pointer to error structure.
3035 : : *
3036 : : * @return
3037 : : * 0 on success, a negative errno otherwise and rte_errno is set.
3038 : : */
3039 : : static int
3040 : : flow_hw_translate_actions_template(struct rte_eth_dev *dev,
3041 : : const struct mlx5_flow_template_table_cfg *cfg,
3042 : : struct mlx5_hw_actions *acts,
3043 : : struct rte_flow_actions_template *at,
3044 : : struct mlx5_tbl_multi_pattern_ctx *mp_ctx,
3045 : : struct rte_flow_error *error)
3046 : : {
3047 : 0 : return __flow_hw_translate_actions_template(dev, cfg, acts, at, mp_ctx, false, error);
3048 : : }
3049 : :
3050 : : static __rte_always_inline struct mlx5dr_rule_action *
3051 : : flow_hw_get_dr_action_buffer(struct mlx5_priv *priv,
3052 : : struct rte_flow_template_table *table,
3053 : : uint8_t action_template_index,
3054 : : uint32_t queue)
3055 : : {
3056 : 0 : uint32_t offset = action_template_index * priv->nb_queue + queue;
3057 : :
3058 : 0 : return &table->rule_acts[offset].acts[0];
3059 : : }
3060 : :
3061 : : static void
3062 : 0 : flow_hw_populate_rule_acts_caches(struct rte_eth_dev *dev,
3063 : : struct rte_flow_template_table *table,
3064 : : uint8_t at_idx)
3065 : : {
3066 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
3067 : : uint32_t q;
3068 : :
3069 [ # # ]: 0 : for (q = 0; q < priv->nb_queue; ++q) {
3070 : : struct mlx5dr_rule_action *rule_acts =
3071 : 0 : flow_hw_get_dr_action_buffer(priv, table, at_idx, q);
3072 : :
3073 [ # # ]: 0 : rte_memcpy(rule_acts, table->ats[at_idx].acts.rule_acts,
3074 : : sizeof(table->ats[at_idx].acts.rule_acts));
3075 : : }
3076 : 0 : }
3077 : :
3078 : : /**
3079 : : * Translate rte_flow actions to DR action.
3080 : : *
3081 : : * @param[in] dev
3082 : : * Pointer to the rte_eth_dev structure.
3083 : : * @param[in] tbl
3084 : : * Pointer to the flow template table.
3085 : : * @param[out] error
3086 : : * Pointer to error structure.
3087 : : *
3088 : : * @return
3089 : : * 0 on success, negative value otherwise and rte_errno is set.
3090 : : */
3091 : : static int
3092 : 0 : flow_hw_translate_all_actions_templates(struct rte_eth_dev *dev,
3093 : : struct rte_flow_template_table *tbl,
3094 : : struct rte_flow_error *error)
3095 : : {
3096 : : int ret;
3097 : : uint32_t i;
3098 : :
3099 [ # # ]: 0 : for (i = 0; i < tbl->nb_action_templates; i++) {
3100 [ # # ]: 0 : if (flow_hw_translate_actions_template(dev, &tbl->cfg,
3101 : : &tbl->ats[i].acts,
3102 : : tbl->ats[i].action_template,
3103 : : &tbl->mpctx, error))
3104 : 0 : goto err;
3105 : 0 : flow_hw_populate_rule_acts_caches(dev, tbl, i);
3106 : : }
3107 [ # # ]: 0 : ret = mlx5_tbl_multi_pattern_process(dev, tbl, &tbl->mpctx.segments[0],
3108 : : rte_log2_u32(tbl->cfg.attr.nb_flows),
3109 : : error);
3110 [ # # ]: 0 : if (ret)
3111 : 0 : goto err;
3112 : : return 0;
3113 : : err:
3114 [ # # ]: 0 : while (i--)
3115 : 0 : __flow_hw_action_template_destroy(dev, &tbl->ats[i].acts);
3116 : : return -1;
3117 : : }
3118 : :
3119 : : /**
3120 : : * Get shared indirect action.
3121 : : *
3122 : : * @param[in] dev
3123 : : * Pointer to the rte_eth_dev data structure.
3124 : : * @param[in] act_data
3125 : : * Pointer to the recorded action construct data.
3126 : : * @param[in] item_flags
3127 : : * The matcher itme_flags used for RSS lookup.
3128 : : * @param[in] rule_act
3129 : : * Pointer to the shared action's destination rule DR action.
3130 : : *
3131 : : * @return
3132 : : * 0 on success, negative value otherwise and rte_errno is set.
3133 : : */
3134 : : static __rte_always_inline int
3135 : : flow_hw_shared_action_get(struct rte_eth_dev *dev,
3136 : : struct mlx5_action_construct_data *act_data,
3137 : : const uint64_t item_flags,
3138 : : struct mlx5dr_rule_action *rule_act)
3139 : : {
3140 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
3141 : 0 : struct mlx5_flow_rss_desc rss_desc = { 0 };
3142 : 0 : uint64_t hash_fields = 0;
3143 : : uint32_t hrxq_idx = 0;
3144 : : struct mlx5_hrxq *hrxq = NULL;
3145 : : int act_type = act_data->type;
3146 : :
3147 : : switch (act_type) {
3148 : : case MLX5_RTE_FLOW_ACTION_TYPE_RSS:
3149 : 0 : rss_desc.level = act_data->shared_rss.level;
3150 : 0 : rss_desc.types = act_data->shared_rss.types;
3151 : 0 : rss_desc.symmetric_hash_function = act_data->shared_rss.symmetric_hash_function;
3152 : 0 : flow_dv_hashfields_set(item_flags, &rss_desc, &hash_fields);
3153 : 0 : hrxq_idx = flow_dv_action_rss_hrxq_lookup
3154 : : (dev, act_data->shared_rss.idx, hash_fields);
3155 [ # # # # : 0 : if (hrxq_idx)
# # # # #
# # # # #
# # # # #
# ]
3156 : 0 : hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
3157 : : hrxq_idx);
3158 [ # # # # : 0 : if (hrxq) {
# # # # #
# # # # #
# # # # #
# ]
3159 : 0 : rule_act->action = hrxq->action;
3160 : : return 0;
3161 : : }
3162 : : break;
3163 : : default:
3164 : : DRV_LOG(WARNING, "Unsupported shared action type:%d",
3165 : : act_data->type);
3166 : : break;
3167 : : }
3168 : : return -1;
3169 : : }
3170 : :
3171 : : static void
3172 : 0 : flow_hw_construct_quota(struct mlx5_priv *priv,
3173 : : struct mlx5dr_rule_action *rule_act, uint32_t qid)
3174 : : {
3175 : 0 : rule_act->action = priv->quota_ctx.dr_action;
3176 : 0 : rule_act->aso_meter.offset = qid - 1;
3177 : 0 : rule_act->aso_meter.init_color =
3178 : : MLX5DR_ACTION_ASO_METER_COLOR_GREEN;
3179 : 0 : }
3180 : :
3181 : : /**
3182 : : * Construct shared indirect action.
3183 : : *
3184 : : * @param[in] dev
3185 : : * Pointer to the rte_eth_dev data structure.
3186 : : * @param[in] queue
3187 : : * The flow creation queue index.
3188 : : * @param[in] action
3189 : : * Pointer to the shared indirect rte_flow action.
3190 : : * @param[in] table
3191 : : * Pointer to the flow table.
3192 : : * @param[in] item_flags
3193 : : * Item flags.
3194 : : * @param[in] action_flags
3195 : : * Actions bit-map detected in this template.
3196 : : * @param[in, out] flow
3197 : : * Pointer to the flow containing the counter.
3198 : : * @param[in] rule_act
3199 : : * Pointer to the shared action's destination rule DR action.
3200 : : *
3201 : : * @return
3202 : : * 0 on success, negative value otherwise and rte_errno is set.
3203 : : */
3204 : : static __rte_always_inline int
3205 : : flow_hw_shared_action_construct(struct rte_eth_dev *dev, uint32_t queue,
3206 : : const struct rte_flow_action *action,
3207 : : struct rte_flow_template_table *table __rte_unused,
3208 : : const uint64_t item_flags, uint64_t action_flags,
3209 : : struct rte_flow_hw *flow,
3210 : : struct mlx5dr_rule_action *rule_act)
3211 : : {
3212 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
3213 : 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
3214 : : struct mlx5_action_construct_data act_data;
3215 : : struct mlx5_shared_action_rss *shared_rss;
3216 : : struct mlx5_aso_mtr *aso_mtr;
3217 : : struct mlx5_age_info *age_info;
3218 : : struct mlx5_hws_age_param *param;
3219 : : struct rte_flow_hw_aux *aux;
3220 : 0 : uint32_t act_idx = (uint32_t)(uintptr_t)action->conf;
3221 : 0 : uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
3222 : 0 : uint32_t idx = act_idx &
3223 : : ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
3224 : : cnt_id_t age_cnt;
3225 : :
3226 : : memset(&act_data, 0, sizeof(act_data));
3227 [ # # # # : 0 : switch (type) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3228 : 0 : case MLX5_INDIRECT_ACTION_TYPE_RSS:
3229 : 0 : act_data.type = MLX5_RTE_FLOW_ACTION_TYPE_RSS;
3230 : 0 : shared_rss = mlx5_ipool_get
3231 : 0 : (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
3232 [ # # # # : 0 : if (!shared_rss)
# # # # #
# ]
3233 : : return -1;
3234 : 0 : act_data.shared_rss.idx = idx;
3235 : 0 : act_data.shared_rss.level = shared_rss->origin.level;
3236 : 0 : act_data.shared_rss.types = !shared_rss->origin.types ?
3237 [ # # # # : 0 : RTE_ETH_RSS_IP :
# # # # #
# ]
3238 : : shared_rss->origin.types;
3239 : 0 : act_data.shared_rss.symmetric_hash_function =
3240 : 0 : MLX5_RSS_IS_SYMM(shared_rss->origin.func);
3241 : :
3242 : : if (flow_hw_shared_action_get
3243 : : (dev, &act_data, item_flags, rule_act))
3244 : : return -1;
3245 : : break;
3246 : 0 : case MLX5_INDIRECT_ACTION_TYPE_COUNT:
3247 : 0 : if (mlx5_hws_cnt_pool_get_action_offset(priv->hws_cpool,
3248 : : act_idx,
3249 : : &rule_act->action,
3250 : : &rule_act->counter.offset))
3251 : : return -1;
3252 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_CNT_ID;
3253 : 0 : flow->cnt_id = act_idx;
3254 : : break;
3255 : 0 : case MLX5_INDIRECT_ACTION_TYPE_AGE:
3256 : 0 : aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
3257 : : /*
3258 : : * Save the index with the indirect type, to recognize
3259 : : * it in flow destroy.
3260 : : */
3261 : : mlx5_flow_hw_aux_set_age_idx(flow, aux, act_idx);
3262 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_AGE_IDX;
3263 [ # # # # : 0 : if (action_flags & MLX5_FLOW_ACTION_INDIRECT_COUNT)
# # # # #
# ]
3264 : : /*
3265 : : * The mutual update for idirect AGE & COUNT will be
3266 : : * performed later after we have ID for both of them.
3267 : : */
3268 : : break;
3269 : 0 : age_info = GET_PORT_AGE_INFO(priv);
3270 : 0 : param = mlx5_ipool_get(age_info->ages_ipool, idx);
3271 [ # # # # : 0 : if (param == NULL)
# # # # #
# ]
3272 : : return -1;
3273 [ # # # # : 0 : if (action_flags & MLX5_FLOW_ACTION_COUNT) {
# # # # #
# ]
3274 [ # # # # : 0 : if (mlx5_hws_cnt_pool_get(priv->hws_cpool,
# # # # #
# # # # #
# # # # #
# ]
3275 : : ¶m->queue_id, &age_cnt,
3276 : : idx) < 0)
3277 : : return -1;
3278 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_CNT_ID;
3279 : 0 : flow->cnt_id = age_cnt;
3280 : 0 : param->nb_cnts++;
3281 : : } else {
3282 : : /*
3283 : : * Get the counter of this indirect AGE or create one
3284 : : * if doesn't exist.
3285 : : */
3286 : : age_cnt = mlx5_hws_age_cnt_get(priv, param, idx);
3287 [ # # # # : 0 : if (age_cnt == 0)
# # # # #
# ]
3288 : : return -1;
3289 : : }
3290 : 0 : if (mlx5_hws_cnt_pool_get_action_offset(priv->hws_cpool,
3291 : : age_cnt, &rule_act->action,
3292 : : &rule_act->counter.offset))
3293 : : return -1;
3294 : : break;
3295 : : case MLX5_INDIRECT_ACTION_TYPE_CT:
3296 : : if (flow_hw_ct_compile(dev, queue, idx, rule_act))
3297 : : return -1;
3298 : : break;
3299 : 0 : case MLX5_INDIRECT_ACTION_TYPE_METER_MARK:
3300 : : /* Find ASO object. */
3301 : 0 : aso_mtr = mlx5_ipool_get(pool->idx_pool, idx);
3302 [ # # # # : 0 : if (!aso_mtr)
# # # # #
# ]
3303 : : return -1;
3304 : 0 : rule_act->action = pool->action;
3305 : 0 : rule_act->aso_meter.offset = aso_mtr->offset;
3306 : : break;
3307 : 0 : case MLX5_INDIRECT_ACTION_TYPE_QUOTA:
3308 : 0 : flow_hw_construct_quota(priv, rule_act, idx);
3309 : : break;
3310 : 0 : default:
3311 : 0 : DRV_LOG(WARNING, "Unsupported shared action type:%d", type);
3312 : : break;
3313 : : }
3314 : : return 0;
3315 : : }
3316 : :
3317 : : static __rte_always_inline int
3318 : : flow_hw_mhdr_cmd_is_nop(const struct mlx5_modification_cmd *cmd)
3319 : : {
3320 : : struct mlx5_modification_cmd cmd_he = {
3321 : 0 : .data0 = rte_be_to_cpu_32(cmd->data0),
3322 : : .data1 = 0,
3323 : : };
3324 : :
3325 : 0 : return cmd_he.action_type == MLX5_MODIFICATION_TYPE_NOP;
3326 : : }
3327 : :
3328 : : /**
3329 : : * Construct flow action array.
3330 : : *
3331 : : * For action template contains dynamic actions, these actions need to
3332 : : * be updated according to the rte_flow action during flow creation.
3333 : : *
3334 : : * @param[in] dev
3335 : : * Pointer to the rte_eth_dev structure.
3336 : : * @param[in] job
3337 : : * Pointer to job descriptor.
3338 : : * @param[in] hw_acts
3339 : : * Pointer to translated actions from template.
3340 : : * @param[in] it_idx
3341 : : * Item template index the action template refer to.
3342 : : * @param[in] actions
3343 : : * Array of rte_flow action need to be checked.
3344 : : * @param[in] rule_acts
3345 : : * Array of DR rule actions to be used during flow creation..
3346 : : * @param[in] acts_num
3347 : : * Pointer to the real acts_num flow has.
3348 : : *
3349 : : * @return
3350 : : * 0 on success, negative value otherwise and rte_errno is set.
3351 : : */
3352 : : static __rte_always_inline int
3353 : : flow_hw_modify_field_construct(struct mlx5_modification_cmd *mhdr_cmd,
3354 : : struct mlx5_action_construct_data *act_data,
3355 : : const struct mlx5_hw_actions *hw_acts,
3356 : : const struct rte_flow_action *action)
3357 : : {
3358 : 0 : const struct rte_flow_action_modify_field *mhdr_action = action->conf;
3359 : 0 : uint8_t values[16] = { 0 };
3360 : : unaligned_uint32_t *value_p;
3361 : : uint32_t i;
3362 : : struct field_modify_info *field;
3363 : :
3364 [ # # # # : 0 : if (!hw_acts->mhdr)
# # # # #
# ]
3365 : : return -1;
3366 [ # # # # : 0 : if (hw_acts->mhdr->shared || act_data->modify_header.shared)
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3367 : : return 0;
3368 : : MLX5_ASSERT(mhdr_action->operation == RTE_FLOW_MODIFY_SET ||
3369 : : mhdr_action->operation == RTE_FLOW_MODIFY_ADD);
3370 [ # # # # : 0 : if (mhdr_action->src.field != RTE_FLOW_FIELD_VALUE &&
# # # # #
# ]
3371 : : mhdr_action->src.field != RTE_FLOW_FIELD_POINTER)
3372 : : return 0;
3373 [ # # # # : 0 : if (mhdr_action->src.field == RTE_FLOW_FIELD_VALUE)
# # # # #
# ]
3374 [ # # # # : 0 : rte_memcpy(values, &mhdr_action->src.value, sizeof(values));
# # # # #
# ]
3375 : : else
3376 [ # # # # : 0 : rte_memcpy(values, mhdr_action->src.pvalue, sizeof(values));
# # # # #
# ]
3377 [ # # # # : 0 : if (mhdr_action->dst.field == RTE_FLOW_FIELD_META ||
# # # # #
# ]
3378 [ # # # # : 0 : mhdr_action->dst.field == RTE_FLOW_FIELD_TAG ||
# # # # #
# ]
3379 [ # # # # : 0 : mhdr_action->dst.field == RTE_FLOW_FIELD_METER_COLOR ||
# # # # #
# ]
3380 : : mhdr_action->dst.field == (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG) {
3381 : 0 : uint8_t tag_index = flow_tag_index_get(&mhdr_action->dst);
3382 : :
3383 : : value_p = (unaligned_uint32_t *)values;
3384 [ # # # # : 0 : if (mhdr_action->dst.field == RTE_FLOW_FIELD_TAG &&
# # # # #
# # # # #
# # # # #
# ]
3385 : : tag_index == RTE_PMD_MLX5_LINEAR_HASH_TAG_INDEX)
3386 [ # # # # : 0 : *value_p = rte_cpu_to_be_32(*value_p << 16);
# # # # #
# ]
3387 : : else
3388 [ # # # # : 0 : *value_p = rte_cpu_to_be_32(*value_p);
# # # # #
# ]
3389 [ # # # # : 0 : } else if (mhdr_action->dst.field == RTE_FLOW_FIELD_GTP_PSC_QFI ||
# # # # #
# ]
3390 : : mhdr_action->dst.field == RTE_FLOW_FIELD_GENEVE_OPT_TYPE) {
3391 : : uint32_t tmp;
3392 : :
3393 : : /*
3394 : : * Both QFI and Geneve option type are passed as an uint8_t integer,
3395 : : * but it is accessed through a 2nd least significant byte of a 32-bit
3396 : : * field in modify header command.
3397 : : */
3398 : 0 : tmp = values[0];
3399 : : value_p = (unaligned_uint32_t *)values;
3400 [ # # # # : 0 : *value_p = rte_cpu_to_be_32(tmp << 8);
# # # # #
# ]
3401 : : }
3402 : 0 : i = act_data->modify_header.mhdr_cmds_off;
3403 : 0 : field = act_data->modify_header.field;
3404 : : do {
3405 : : uint32_t off_b;
3406 : : uint32_t mask;
3407 : : uint32_t data;
3408 : : const uint8_t *mask_src;
3409 : :
3410 [ # # # # : 0 : if (i >= act_data->modify_header.mhdr_cmds_end)
# # # # #
# # # # #
# # # # #
# ]
3411 : : return -1;
3412 [ # # # # : 0 : if (flow_hw_mhdr_cmd_is_nop(&mhdr_cmd[i])) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3413 : 0 : ++i;
3414 : 0 : continue;
3415 : : }
3416 : 0 : mask_src = (const uint8_t *)act_data->modify_header.mask;
3417 : 0 : mask = flow_dv_fetch_field(mask_src + field->offset, field->size);
3418 [ # # # # : 0 : if (!mask) {
# # # # #
# # # # #
# # # # #
# ]
3419 : 0 : ++field;
3420 : 0 : continue;
3421 : : }
3422 : 0 : off_b = rte_bsf32(mask);
3423 : 0 : data = flow_dv_fetch_field(values + field->offset, field->size);
3424 : : /*
3425 : : * IPv6 DSCP uses OUT_IPV6_TRAFFIC_CLASS as ID but it starts from 2
3426 : : * bits left. Shift the data left for IPv6 DSCP
3427 : : */
3428 [ # # # # : 0 : if (field->id == MLX5_MODI_OUT_IPV6_TRAFFIC_CLASS &&
# # # # #
# # # #
# ]
3429 [ # # # # : 0 : mhdr_action->dst.field == RTE_FLOW_FIELD_IPV6_DSCP)
# # ]
3430 : 0 : data <<= MLX5_IPV6_HDR_DSCP_SHIFT;
3431 : 0 : data = (data & mask) >> off_b;
3432 [ # # # # : 0 : mhdr_cmd[i++].data1 = rte_cpu_to_be_32(data);
# # # # #
# # # # #
# # # # #
# ]
3433 : 0 : ++field;
3434 [ # # # # : 0 : } while (field->size);
# # # # #
# # # # #
# # # # #
# ]
3435 : : return 0;
3436 : : }
3437 : :
3438 : : /**
3439 : : * Release any actions allocated for the flow rule during actions construction.
3440 : : *
3441 : : * @param[in] flow
3442 : : * Pointer to flow structure.
3443 : : */
3444 : : static void
3445 : 0 : flow_hw_release_actions(struct rte_eth_dev *dev,
3446 : : uint32_t queue,
3447 : : struct rte_flow_hw *flow)
3448 : : {
3449 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
3450 : 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
3451 : 0 : struct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
3452 : :
3453 [ # # ]: 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_FATE_JUMP)
3454 : 0 : flow_hw_jump_release(dev, flow->jump);
3455 [ # # ]: 0 : else if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_FATE_HRXQ)
3456 : 0 : mlx5_hrxq_obj_release(dev, flow->hrxq);
3457 [ # # ]: 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_CNT_ID)
3458 : 0 : flow_hw_age_count_release(priv, queue, flow, NULL);
3459 [ # # ]: 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_MTR_ID)
3460 : 0 : mlx5_ipool_free(pool->idx_pool, mlx5_flow_hw_aux_get_mtr_id(flow, aux));
3461 : 0 : }
3462 : :
3463 : : /**
3464 : : * Construct flow action array.
3465 : : *
3466 : : * For action template contains dynamic actions, these actions need to
3467 : : * be updated according to the rte_flow action during flow creation.
3468 : : *
3469 : : * @param[in] dev
3470 : : * Pointer to the rte_eth_dev structure.
3471 : : * @param[in] flow
3472 : : * Pointer to flow structure.
3473 : : * @param[in] ap
3474 : : * Pointer to container for temporarily constructed actions' parameters.
3475 : : * @param[in] hw_acts
3476 : : * Pointer to translated actions from template.
3477 : : * @param[in] items_flags
3478 : : * Item flags.
3479 : : * @param[in] table
3480 : : * Pointer to the template table.
3481 : : * @param[in] actions
3482 : : * Array of rte_flow action need to be checked.
3483 : : * @param[in] rule_acts
3484 : : * Array of DR rule actions to be used during flow creation..
3485 : : * @param[in] acts_num
3486 : : * Pointer to the real acts_num flow has.
3487 : : *
3488 : : * @return
3489 : : * 0 on success, negative value otherwise and rte_errno is set.
3490 : : */
3491 : : static __rte_always_inline int
3492 : : flow_hw_actions_construct(struct rte_eth_dev *dev,
3493 : : struct rte_flow_hw *flow,
3494 : : struct mlx5_flow_hw_action_params *ap,
3495 : : const struct mlx5_hw_action_template *hw_at,
3496 : : uint64_t item_flags,
3497 : : struct rte_flow_template_table *table,
3498 : : const struct rte_flow_action actions[],
3499 : : struct mlx5dr_rule_action *rule_acts,
3500 : : uint32_t queue,
3501 : : struct rte_flow_error *error)
3502 : : {
3503 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
3504 : 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
3505 : : struct mlx5_action_construct_data *act_data;
3506 : 0 : const struct rte_flow_actions_template *at = hw_at->action_template;
3507 : : const struct mlx5_hw_actions *hw_acts = &hw_at->acts;
3508 : : const struct rte_flow_action *action;
3509 : : const struct rte_flow_action_raw_encap *raw_encap_data;
3510 : : const struct rte_flow_action_ipv6_ext_push *ipv6_push;
3511 : : const struct rte_flow_item *enc_item = NULL;
3512 : : const struct rte_flow_action_ethdev *port_action = NULL;
3513 : : const struct rte_flow_action_meter *meter = NULL;
3514 : : const struct rte_flow_action_age *age = NULL;
3515 : : const struct rte_flow_action_nat64 *nat64_c = NULL;
3516 : 0 : struct rte_flow_attr attr = {
3517 : : .ingress = 1,
3518 : : };
3519 : : uint32_t ft_flag;
3520 : : int ret;
3521 : 0 : size_t encap_len = 0;
3522 : : uint32_t age_idx = 0;
3523 : : uint32_t mtr_idx = 0;
3524 : : struct mlx5_aso_mtr *aso_mtr;
3525 : : struct mlx5_multi_pattern_segment *mp_segment = NULL;
3526 : : struct rte_flow_hw_aux *aux;
3527 : :
3528 : 0 : attr.group = table->grp->group_id;
3529 : 0 : ft_flag = mlx5_hw_act_flag[!!table->grp->group_id][table->type];
3530 : 0 : if (table->type >= MLX5DR_TABLE_TYPE_FDB && table->type < MLX5DR_TABLE_TYPE_MAX) {
3531 : 0 : attr.transfer = 1;
3532 : : attr.ingress = 1;
3533 [ # # # # : 0 : } else if (table->type == MLX5DR_TABLE_TYPE_NIC_TX) {
# # # # #
# ]
3534 : 0 : attr.egress = 1;
3535 : 0 : attr.ingress = 0;
3536 : : } else {
3537 : : attr.ingress = 1;
3538 : : }
3539 [ # # # # : 0 : if (hw_acts->mhdr && hw_acts->mhdr->mhdr_cmds_num > 0 && !hw_acts->mhdr->shared) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3540 : 0 : uint16_t pos = hw_acts->mhdr->pos;
3541 : :
3542 : 0 : mp_segment = mlx5_multi_pattern_segment_find(table, flow->res_idx);
3543 [ # # # # : 0 : if (!mp_segment || !mp_segment->mhdr_action)
# # # # #
# # # # #
# # # # #
# ]
3544 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3545 : : NULL, "No modify header action found");
3546 : 0 : rule_acts[pos].action = mp_segment->mhdr_action;
3547 : : /* offset is relative to DR action */
3548 : 0 : rule_acts[pos].modify_header.offset =
3549 : 0 : flow->res_idx - mp_segment->head_index;
3550 : 0 : rule_acts[pos].modify_header.data =
3551 : 0 : (uint8_t *)ap->mhdr_cmd;
3552 : : MLX5_ASSERT(hw_acts->mhdr->mhdr_cmds_num <= MLX5_MHDR_MAX_CMD);
3553 : 0 : rte_memcpy(ap->mhdr_cmd, hw_acts->mhdr->mhdr_cmds,
3554 [ # # # # : 0 : sizeof(*ap->mhdr_cmd) * hw_acts->mhdr->mhdr_cmds_num);
# # # # #
# ]
3555 : : }
3556 [ # # # # : 0 : LIST_FOREACH(act_data, &hw_acts->act_list, next) {
# # # # #
# ]
3557 : : uint32_t jump_group;
3558 : : uint32_t tag;
3559 : : struct mlx5_hw_jump_action *jump;
3560 : : struct mlx5_hrxq *hrxq;
3561 : : uint32_t ct_idx;
3562 : : cnt_id_t cnt_id;
3563 : : uint32_t *cnt_queue;
3564 : : uint32_t mtr_id;
3565 : : struct rte_flow_template_table *jump_table;
3566 : :
3567 : 0 : action = &actions[act_data->action_src];
3568 : : /*
3569 : : * action template construction replaces
3570 : : * OF_SET_VLAN_VID with MODIFY_FIELD
3571 : : */
3572 : 0 : if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)
3573 : : MLX5_ASSERT(act_data->type ==
3574 : : RTE_FLOW_ACTION_TYPE_MODIFY_FIELD);
3575 : : else
3576 : : MLX5_ASSERT(action->type ==
3577 : : RTE_FLOW_ACTION_TYPE_INDIRECT ||
3578 : : (int)action->type == act_data->type);
3579 [ # # # # : 0 : switch ((int)act_data->type) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3580 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT_LIST:
3581 : 0 : act_data->indirect_list_cb(dev, act_data, action,
3582 : 0 : &rule_acts[act_data->action_dst]);
3583 : 0 : break;
3584 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT:
3585 : 0 : if (flow_hw_shared_action_construct
3586 : : (dev, queue, action, table,
3587 : 0 : item_flags, at->action_flags, flow,
3588 [ # # # # : 0 : &rule_acts[act_data->action_dst]))
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3589 : 0 : goto error;
3590 : : break;
3591 : : case RTE_FLOW_ACTION_TYPE_VOID:
3592 : : break;
3593 : 0 : case RTE_FLOW_ACTION_TYPE_MARK:
3594 : 0 : tag = mlx5_flow_mark_set
3595 : : (((const struct rte_flow_action_mark *)
3596 : 0 : (action->conf))->id);
3597 : 0 : rule_acts[act_data->action_dst].tag.value = tag;
3598 : 0 : break;
3599 : 0 : case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
3600 : 0 : rule_acts[act_data->action_dst].push_vlan.vlan_hdr =
3601 : 0 : vlan_hdr_to_be32(action);
3602 : 0 : break;
3603 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP:
3604 : 0 : jump_group = ((const struct rte_flow_action_jump *)
3605 : 0 : action->conf)->group;
3606 : 0 : jump = flow_hw_jump_action_register
3607 : 0 : (dev, &table->cfg, jump_group, NULL);
3608 [ # # # # : 0 : if (!jump)
# # # # #
# ]
3609 : 0 : goto error;
3610 : 0 : rule_acts[act_data->action_dst].action =
3611 [ # # # # : 0 : (!!attr.group) ? jump->hws_action : jump->root_action;
# # # # #
# ]
3612 : 0 : flow->jump = jump;
3613 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_FATE_JUMP;
3614 : 0 : break;
3615 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
3616 : : case RTE_FLOW_ACTION_TYPE_QUEUE:
3617 : 0 : hrxq = flow_hw_tir_action_register(dev, ft_flag, action);
3618 [ # # # # : 0 : if (!hrxq)
# # # # #
# ]
3619 : 0 : goto error;
3620 : 0 : rule_acts[act_data->action_dst].action = hrxq->action;
3621 : 0 : flow->hrxq = hrxq;
3622 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_FATE_HRXQ;
3623 : 0 : break;
3624 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_RSS:
3625 : 0 : if (flow_hw_shared_action_get
3626 : : (dev, act_data, item_flags,
3627 : 0 : &rule_acts[act_data->action_dst]))
3628 : 0 : goto error;
3629 : : break;
3630 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
3631 : 0 : enc_item = ((const struct rte_flow_action_vxlan_encap *)
3632 : 0 : action->conf)->definition;
3633 [ # # # # : 0 : if (flow_dv_convert_encap_data(enc_item, ap->encap_data, &encap_len, NULL))
# # # # #
# ]
3634 : 0 : goto error;
3635 : : break;
3636 : 0 : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
3637 : 0 : enc_item = ((const struct rte_flow_action_nvgre_encap *)
3638 : 0 : action->conf)->definition;
3639 [ # # # # : 0 : if (flow_dv_convert_encap_data(enc_item, ap->encap_data, &encap_len, NULL))
# # # # #
# ]
3640 : 0 : goto error;
3641 : : break;
3642 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
3643 : 0 : raw_encap_data =
3644 : : (const struct rte_flow_action_raw_encap *)
3645 : : action->conf;
3646 : : MLX5_ASSERT(raw_encap_data->size == act_data->encap.len);
3647 [ # # # # : 0 : if (unlikely(act_data->encap.len > MLX5_ENCAP_MAX_LEN))
# # # # #
# ]
3648 : : return -1;
3649 [ # # # # : 0 : rte_memcpy(ap->encap_data, raw_encap_data->data, act_data->encap.len);
# # # # #
# ]
3650 : : break;
3651 : 0 : case RTE_FLOW_ACTION_TYPE_IPV6_EXT_PUSH:
3652 : 0 : ipv6_push =
3653 : : (const struct rte_flow_action_ipv6_ext_push *)action->conf;
3654 : : MLX5_ASSERT(ipv6_push->size == act_data->ipv6_ext.len);
3655 [ # # # # : 0 : if (unlikely(act_data->ipv6_ext.len > MLX5_PUSH_MAX_LEN))
# # # # #
# ]
3656 : : return -1;
3657 [ # # # # : 0 : rte_memcpy(ap->ipv6_push_data, ipv6_push->data,
# # # # #
# ]
3658 : : act_data->ipv6_ext.len);
3659 : : break;
3660 : 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
3661 [ # # # # : 0 : if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)
# # # # #
# ]
3662 : 0 : ret = flow_hw_set_vlan_vid_construct(dev, ap->mhdr_cmd,
3663 : : act_data,
3664 : : hw_acts,
3665 : : action);
3666 : : else
3667 [ # # # # : 0 : ret = flow_hw_modify_field_construct(ap->mhdr_cmd,
# # # # #
# ]
3668 : : act_data,
3669 : : hw_acts,
3670 : : action);
3671 [ # # # # : 0 : if (ret)
# # # # #
# ]
3672 : 0 : goto error;
3673 : : break;
3674 : 0 : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
3675 : 0 : port_action = action->conf;
3676 [ # # # # : 0 : if (!priv->hw_vport[port_action->port_id])
# # # # #
# ]
3677 : 0 : goto error;
3678 : 0 : rule_acts[act_data->action_dst].action =
3679 : : priv->hw_vport[port_action->port_id];
3680 : 0 : break;
3681 : 0 : case RTE_FLOW_ACTION_TYPE_QUOTA:
3682 : 0 : flow_hw_construct_quota(priv,
3683 : 0 : rule_acts + act_data->action_dst,
3684 : : act_data->shared_meter.id);
3685 : 0 : break;
3686 : 0 : case RTE_FLOW_ACTION_TYPE_METER:
3687 : 0 : meter = action->conf;
3688 : 0 : mtr_id = meter->mtr_id;
3689 : 0 : aso_mtr = mlx5_aso_meter_by_idx(priv, mtr_id);
3690 : 0 : rule_acts[act_data->action_dst].action =
3691 : 0 : priv->mtr_bulk.action;
3692 : 0 : rule_acts[act_data->action_dst].aso_meter.offset =
3693 : 0 : aso_mtr->offset;
3694 : 0 : jump = flow_hw_jump_action_register
3695 : 0 : (dev, &table->cfg, aso_mtr->fm.group, NULL);
3696 [ # # # # : 0 : if (!jump)
# # # # #
# ]
3697 : 0 : goto error;
3698 : : MLX5_ASSERT
3699 : : (!rule_acts[act_data->action_dst + 1].action);
3700 : 0 : rule_acts[act_data->action_dst + 1].action =
3701 [ # # # # : 0 : (!!attr.group) ? jump->hws_action :
# # # # #
# ]
3702 : : jump->root_action;
3703 : 0 : flow->jump = jump;
3704 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_FATE_JUMP;
3705 [ # # # # : 0 : if (mlx5_aso_mtr_wait(priv, aso_mtr, true))
# # # # #
# ]
3706 : 0 : goto error;
3707 : : break;
3708 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
3709 : 0 : aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
3710 : 0 : age = action->conf;
3711 : : /*
3712 : : * First, create the AGE parameter, then create its
3713 : : * counter later:
3714 : : * Regular counter - in next case.
3715 : : * Indirect counter - update it after the loop.
3716 : : */
3717 : 0 : age_idx = mlx5_hws_age_action_create(priv, queue, 0,
3718 : : age,
3719 : : flow->res_idx,
3720 : : error);
3721 [ # # # # : 0 : if (age_idx == 0)
# # # # #
# ]
3722 : 0 : goto error;
3723 : : mlx5_flow_hw_aux_set_age_idx(flow, aux, age_idx);
3724 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_AGE_IDX;
3725 [ # # # # : 0 : if (at->action_flags & MLX5_FLOW_ACTION_INDIRECT_COUNT)
# # # # #
# ]
3726 : : /*
3727 : : * When AGE uses indirect counter, no need to
3728 : : * create counter but need to update it with the
3729 : : * AGE parameter, will be done after the loop.
3730 : : */
3731 : : break;
3732 : : /* Fall-through. */
3733 : : case RTE_FLOW_ACTION_TYPE_COUNT:
3734 : : cnt_queue = mlx5_hws_cnt_get_queue(priv, &queue);
3735 : : ret = mlx5_hws_cnt_pool_get(priv->hws_cpool, cnt_queue, &cnt_id, age_idx);
3736 [ # # # # : 0 : if (ret != 0) {
# # # # #
# ]
3737 : 0 : rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_ACTION,
3738 : : action, "Failed to allocate flow counter");
3739 : 0 : goto error;
3740 : : }
3741 : 0 : ret = mlx5_hws_cnt_pool_get_action_offset
3742 : : (priv->hws_cpool,
3743 : : cnt_id,
3744 : : &rule_acts[act_data->action_dst].action,
3745 : 0 : &rule_acts[act_data->action_dst].counter.offset
3746 : : );
3747 : : if (ret != 0)
3748 : : goto error;
3749 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_CNT_ID;
3750 : 0 : flow->cnt_id = cnt_id;
3751 : 0 : break;
3752 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
3753 : 0 : ret = mlx5_hws_cnt_pool_get_action_offset
3754 : : (priv->hws_cpool,
3755 : : act_data->shared_counter.id,
3756 : : &rule_acts[act_data->action_dst].action,
3757 : 0 : &rule_acts[act_data->action_dst].counter.offset
3758 : : );
3759 : : if (ret != 0)
3760 : : goto error;
3761 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_CNT_ID;
3762 : 0 : flow->cnt_id = act_data->shared_counter.id;
3763 : 0 : break;
3764 : 0 : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
3765 : 0 : ct_idx = MLX5_INDIRECT_ACTION_IDX_GET(action->conf);
3766 : 0 : if (flow_hw_ct_compile(dev, queue, ct_idx,
3767 : 0 : &rule_acts[act_data->action_dst]))
3768 : 0 : goto error;
3769 : : break;
3770 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_METER_MARK:
3771 : 0 : mtr_id = act_data->shared_meter.id &
3772 : : ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
3773 : : /* Find ASO object. */
3774 : 0 : aso_mtr = mlx5_ipool_get(pool->idx_pool, mtr_id);
3775 [ # # # # : 0 : if (!aso_mtr)
# # # # #
# ]
3776 : 0 : goto error;
3777 : 0 : rule_acts[act_data->action_dst].action =
3778 : 0 : pool->action;
3779 : 0 : rule_acts[act_data->action_dst].aso_meter.offset =
3780 : 0 : aso_mtr->offset;
3781 : 0 : break;
3782 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
3783 : : /*
3784 : : * Allocate meter directly will slow down flow
3785 : : * insertion rate.
3786 : : */
3787 : : ret = flow_hw_meter_mark_compile(dev,
3788 : 0 : act_data->action_dst, action,
3789 : : rule_acts, &mtr_idx, MLX5_HW_INV_QUEUE, error);
3790 : : if (ret != 0)
3791 : 0 : goto error;
3792 : 0 : aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
3793 : : mlx5_flow_hw_aux_set_mtr_id(flow, aux, mtr_idx);
3794 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_MTR_ID;
3795 : 0 : break;
3796 : 0 : case RTE_FLOW_ACTION_TYPE_NAT64:
3797 : 0 : nat64_c = action->conf;
3798 : : MLX5_ASSERT(table->type < MLX5DR_TABLE_TYPE_MAX);
3799 : 0 : rule_acts[act_data->action_dst].action =
3800 : 0 : priv->action_nat64[table->type][nat64_c->type];
3801 : 0 : break;
3802 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
3803 : 0 : jump_table = ((const struct rte_flow_action_jump_to_table_index *)
3804 : 0 : action->conf)->table;
3805 [ # # # # : 0 : if (likely(!rte_flow_template_table_resizable(dev->data->port_id,
# # # # #
# ]
3806 : : &table->cfg.attr))) {
3807 : 0 : rule_acts[act_data->action_dst].action =
3808 : 0 : jump_table->matcher_info[0].jump;
3809 : : } else {
3810 : : uint32_t selector;
3811 : 0 : rte_rwlock_read_lock(&table->matcher_replace_rwlk);
3812 : 0 : selector = table->matcher_selector;
3813 : 0 : rule_acts[act_data->action_dst].action =
3814 : 0 : jump_table->matcher_info[selector].jump;
3815 : 0 : rte_rwlock_read_unlock(&table->matcher_replace_rwlk);
3816 : : }
3817 : 0 : rule_acts[act_data->action_dst].jump_to_matcher.offset =
3818 : : ((const struct rte_flow_action_jump_to_table_index *)
3819 : 0 : action->conf)->index;
3820 : 0 : break;
3821 : : default:
3822 : : break;
3823 : : }
3824 : : }
3825 [ # # # # : 0 : if (at->action_flags & MLX5_FLOW_ACTION_INDIRECT_COUNT) {
# # # # #
# ]
3826 : : /* If indirect count is used, then CNT_ID flag should be set. */
3827 : : MLX5_ASSERT(flow->flags & MLX5_FLOW_HW_FLOW_FLAG_CNT_ID);
3828 [ # # # # : 0 : if (at->action_flags & MLX5_FLOW_ACTION_INDIRECT_AGE) {
# # # # #
# ]
3829 : : /* If indirect AGE is used, then AGE_IDX flag should be set. */
3830 : : MLX5_ASSERT(flow->flags & MLX5_FLOW_HW_FLOW_FLAG_AGE_IDX);
3831 : 0 : aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
3832 : 0 : age_idx = mlx5_flow_hw_aux_get_age_idx(flow, aux) &
3833 : : MLX5_HWS_AGE_IDX_MASK;
3834 [ # # # # : 0 : if (mlx5_hws_cnt_age_get(priv->hws_cpool, flow->cnt_id) != age_idx)
# # # # #
# # # # #
# # # # #
# ]
3835 : : /*
3836 : : * This is first use of this indirect counter
3837 : : * for this indirect AGE, need to increase the
3838 : : * number of counters.
3839 : : */
3840 : : mlx5_hws_age_nb_cnt_increase(priv, age_idx);
3841 : : }
3842 : : /*
3843 : : * Update this indirect counter the indirect/direct AGE in which
3844 : : * using it.
3845 : : */
3846 [ # # # # : 0 : mlx5_hws_cnt_age_set(priv->hws_cpool, flow->cnt_id, age_idx);
# # # # #
# ]
3847 : : }
3848 [ # # # # : 0 : if (hw_acts->encap_decap && !hw_acts->encap_decap->shared) {
# # # # #
# # # # #
# # # # #
# ]
3849 [ # # # # : 0 : int ix = mlx5_multi_pattern_reformat_to_index(hw_acts->encap_decap->action_type);
# # # # #
# ]
3850 : 0 : struct mlx5dr_rule_action *ra = &rule_acts[hw_acts->encap_decap_pos];
3851 : :
3852 [ # # # # : 0 : if (ix < 0)
# # # # #
# ]
3853 : 0 : goto error;
3854 [ # # # # : 0 : if (!mp_segment)
# # # # #
# ]
3855 : 0 : mp_segment = mlx5_multi_pattern_segment_find(table, flow->res_idx);
3856 [ # # # # : 0 : if (!mp_segment || !mp_segment->reformat_action[ix])
# # # # #
# # # # #
# # # # #
# ]
3857 : 0 : goto error;
3858 : 0 : ra->action = mp_segment->reformat_action[ix];
3859 : : /* reformat offset is relative to selected DR action */
3860 : 0 : ra->reformat.offset = flow->res_idx - mp_segment->head_index;
3861 : 0 : ra->reformat.data = ap->encap_data;
3862 : : }
3863 [ # # # # : 0 : if (hw_acts->push_remove && !hw_acts->push_remove->shared) {
# # # # #
# # # # #
# # # # #
# ]
3864 : 0 : rule_acts[hw_acts->push_remove_pos].ipv6_ext.offset =
3865 : 0 : flow->res_idx - 1;
3866 : 0 : rule_acts[hw_acts->push_remove_pos].ipv6_ext.header = ap->ipv6_push_data;
3867 : : }
3868 [ # # # # : 0 : if (mlx5_hws_cnt_id_valid(hw_acts->cnt_id)) {
# # # # #
# ]
3869 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_CNT_ID;
3870 : 0 : flow->cnt_id = hw_acts->cnt_id;
3871 : : }
3872 : : return 0;
3873 : :
3874 : 0 : error:
3875 : 0 : flow_hw_release_actions(dev, queue, flow);
3876 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3877 : : NULL, "Action construction failed");
3878 : : }
3879 : :
3880 : : static const struct rte_flow_item *
3881 : 0 : flow_hw_get_rule_items(struct rte_eth_dev *dev,
3882 : : const struct rte_flow_template_table *table,
3883 : : const struct rte_flow_item items[],
3884 : : uint8_t pattern_template_index,
3885 : : struct mlx5_flow_hw_pattern_params *pp)
3886 : : {
3887 : 0 : struct rte_flow_pattern_template *pt = table->its[pattern_template_index];
3888 : :
3889 : : /* Only one implicit item can be added to flow rule pattern. */
3890 : : MLX5_ASSERT(!pt->implicit_port || !pt->implicit_tag);
3891 : : /* At least one item was allocated in pattern params for items. */
3892 : : MLX5_ASSERT(MLX5_HW_MAX_ITEMS >= 1);
3893 [ # # ]: 0 : if (pt->implicit_port) {
3894 [ # # ]: 0 : if (pt->orig_item_nb + 1 > MLX5_HW_MAX_ITEMS) {
3895 : 0 : rte_errno = ENOMEM;
3896 : 0 : return NULL;
3897 : : }
3898 : : /* Set up represented port item in pattern params. */
3899 : 0 : pp->port_spec = (struct rte_flow_item_ethdev){
3900 : 0 : .port_id = dev->data->port_id,
3901 : : };
3902 : 0 : pp->items[0] = (struct rte_flow_item){
3903 : : .type = RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT,
3904 : 0 : .spec = &pp->port_spec,
3905 : : };
3906 [ # # ]: 0 : rte_memcpy(&pp->items[1], items, sizeof(*items) * pt->orig_item_nb);
3907 : 0 : return pp->items;
3908 [ # # ]: 0 : } else if (pt->implicit_tag) {
3909 [ # # ]: 0 : if (pt->orig_item_nb + 1 > MLX5_HW_MAX_ITEMS) {
3910 : 0 : rte_errno = ENOMEM;
3911 : 0 : return NULL;
3912 : : }
3913 : : /* Set up tag item in pattern params. */
3914 : 0 : pp->tag_spec = (struct rte_flow_item_tag){
3915 : : .data = flow_hw_tx_tag_regc_value(dev),
3916 : : };
3917 : 0 : pp->items[0] = (struct rte_flow_item){
3918 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_TAG,
3919 : 0 : .spec = &pp->tag_spec,
3920 : : };
3921 : 0 : rte_memcpy(&pp->items[1], items, sizeof(*items) * pt->orig_item_nb);
3922 : 0 : return pp->items;
3923 : : } else {
3924 : : return items;
3925 : : }
3926 : : }
3927 : :
3928 : : /**
3929 : : * Enqueue HW steering flow creation.
3930 : : *
3931 : : * The flow will be applied to the HW only if the postpone bit is not set or
3932 : : * the extra push function is called.
3933 : : * The flow creation status should be checked from dequeue result.
3934 : : *
3935 : : * @param[in] dev
3936 : : * Pointer to the rte_eth_dev structure.
3937 : : * @param[in] queue
3938 : : * The queue to create the flow.
3939 : : * @param[in] attr
3940 : : * Pointer to the flow operation attributes.
3941 : : * @param[in] table
3942 : : * Pointer to the template table.
3943 : : * @param[in] insertion_type
3944 : : * Insertion type for flow rules.
3945 : : * @param[in] rule_index
3946 : : * The item pattern flow follows from the table.
3947 : : * @param[in] items
3948 : : * Items with flow spec value.
3949 : : * @param[in] pattern_template_index
3950 : : * The item pattern flow follows from the table.
3951 : : * @param[in] actions
3952 : : * Action with flow spec value.
3953 : : * @param[in] action_template_index
3954 : : * The action pattern flow follows from the table.
3955 : : * @param[in] user_data
3956 : : * Pointer to the user_data.
3957 : : * @param[out] error
3958 : : * Pointer to error structure.
3959 : : *
3960 : : * @return
3961 : : * Flow pointer on success, NULL otherwise and rte_errno is set.
3962 : : */
3963 : : static __rte_always_inline struct rte_flow *
3964 : : flow_hw_async_flow_create_generic(struct rte_eth_dev *dev,
3965 : : uint32_t queue,
3966 : : const struct rte_flow_op_attr *attr,
3967 : : struct rte_flow_template_table *table,
3968 : : enum rte_flow_table_insertion_type insertion_type,
3969 : : uint32_t rule_index,
3970 : : const struct rte_flow_item items[],
3971 : : uint8_t pattern_template_index,
3972 : : const struct rte_flow_action actions[],
3973 : : uint8_t action_template_index,
3974 : : void *user_data,
3975 : : struct rte_flow_error *error)
3976 : : {
3977 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
3978 : 0 : struct mlx5dr_rule_attr rule_attr = {
3979 : : .queue_id = queue,
3980 : : .user_data = user_data,
3981 : 0 : .burst = attr->postpone,
3982 : : };
3983 : : struct mlx5dr_rule_action *rule_acts;
3984 : : struct rte_flow_hw *flow = NULL;
3985 : : const struct rte_flow_item *rule_items;
3986 : 0 : struct rte_flow_error sub_error = { 0 };
3987 : 0 : uint32_t flow_idx = 0;
3988 : 0 : uint32_t res_idx = 0;
3989 : : int ret;
3990 : :
3991 : 0 : if (mlx5_fp_debug_enabled()) {
3992 [ # # # # : 0 : if (flow_hw_async_create_validate(dev, queue, table, insertion_type, rule_index,
# # ]
3993 : : items, pattern_template_index, actions, action_template_index, error))
3994 : : return NULL;
3995 : : }
3996 : 0 : flow = mlx5_ipool_malloc(table->flow, &flow_idx);
3997 [ # # # # : 0 : if (!flow) {
# # ]
3998 : 0 : rte_errno = ENOMEM;
3999 : 0 : goto error;
4000 : : }
4001 : : rule_acts = flow_hw_get_dr_action_buffer(priv, table, action_template_index, queue);
4002 : : /*
4003 : : * Set the table here in order to know the destination table
4004 : : * when free the flow afterward.
4005 : : */
4006 : 0 : flow->table = table;
4007 : 0 : flow->mt_idx = pattern_template_index;
4008 : 0 : flow->idx = flow_idx;
4009 [ # # # # : 0 : if (table->resource) {
# # ]
4010 : 0 : mlx5_ipool_malloc(table->resource, &res_idx);
4011 [ # # # # : 0 : if (!res_idx) {
# # ]
4012 : 0 : rte_errno = ENOMEM;
4013 : 0 : goto error;
4014 : : }
4015 : 0 : flow->res_idx = res_idx;
4016 : : } else {
4017 : 0 : flow->res_idx = flow_idx;
4018 : : }
4019 : 0 : flow->flags = 0;
4020 : : /*
4021 : : * Set the flow operation type here in order to know if the flow memory
4022 : : * should be freed or not when get the result from dequeue.
4023 : : */
4024 : 0 : flow->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_CREATE;
4025 : 0 : flow->user_data = user_data;
4026 : 0 : rule_attr.user_data = flow;
4027 : : /*
4028 : : * Indexed pool returns 1-based indices, but mlx5dr expects 0-based indices
4029 : : * for rule insertion hints.
4030 : : */
4031 [ # # # # ]: 0 : flow->rule_idx = (rule_index == UINT32_MAX) ? flow->res_idx - 1 : rule_index;
4032 : 0 : rule_attr.rule_idx = flow->rule_idx;
4033 : : /*
4034 : : * Construct the flow actions based on the input actions.
4035 : : * The implicitly appended action is always fixed, like metadata
4036 : : * copy action from FDB to NIC Rx.
4037 : : * No need to copy and contrust a new "actions" list based on the
4038 : : * user's input, in order to save the cost.
4039 : : */
4040 [ # # # # : 0 : if (flow_hw_actions_construct(dev, flow, &priv->hw_q[queue].ap,
# # ]
4041 : 0 : &table->ats[action_template_index],
4042 [ # # # # : 0 : table->its[pattern_template_index]->item_flags,
# # ]
4043 : : flow->table, actions,
4044 : : rule_acts, queue, &sub_error))
4045 : 0 : goto error;
4046 : 0 : rule_items = flow_hw_get_rule_items(dev, table, items,
4047 : 0 : pattern_template_index, &priv->hw_q[queue].pp);
4048 [ # # # # : 0 : if (!rule_items)
# # ]
4049 : 0 : goto error;
4050 [ # # # # : 0 : if (likely(!rte_flow_template_table_resizable(dev->data->port_id, &table->cfg.attr))) {
# # ]
4051 : 0 : ret = mlx5dr_rule_create(table->matcher_info[0].matcher,
4052 : : pattern_template_index, rule_items,
4053 : : action_template_index, rule_acts,
4054 : : &rule_attr,
4055 : 0 : (struct mlx5dr_rule *)flow->rule);
4056 : : } else {
4057 : 0 : struct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
4058 : : uint32_t selector;
4059 : :
4060 : 0 : flow->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_CREATE;
4061 : 0 : rte_rwlock_read_lock(&table->matcher_replace_rwlk);
4062 : 0 : selector = table->matcher_selector;
4063 : 0 : ret = mlx5dr_rule_create(table->matcher_info[selector].matcher,
4064 : : pattern_template_index, rule_items,
4065 : : action_template_index, rule_acts,
4066 : : &rule_attr,
4067 : 0 : (struct mlx5dr_rule *)flow->rule);
4068 : 0 : rte_rwlock_read_unlock(&table->matcher_replace_rwlk);
4069 : 0 : aux->matcher_selector = selector;
4070 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_MATCHER_SELECTOR;
4071 : : }
4072 [ # # # # : 0 : if (likely(!ret)) {
# # ]
4073 : 0 : flow_hw_q_inc_flow_ops(priv, queue);
4074 : 0 : return (struct rte_flow *)flow;
4075 : : }
4076 : 0 : error:
4077 [ # # # # : 0 : if (table->resource && res_idx)
# # # # #
# # # ]
4078 : 0 : mlx5_ipool_free(table->resource, res_idx);
4079 [ # # # # : 0 : if (flow_idx)
# # ]
4080 : 0 : mlx5_ipool_free(table->flow, flow_idx);
4081 [ # # # # : 0 : if (sub_error.cause != RTE_FLOW_ERROR_TYPE_NONE && error != NULL)
# # # # #
# # # ]
4082 : 0 : *error = sub_error;
4083 : : else
4084 : 0 : rte_flow_error_set(error, rte_errno,
4085 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4086 : : "fail to create rte flow");
4087 : : return NULL;
4088 : : }
4089 : :
4090 : : static struct rte_flow *
4091 : 0 : flow_hw_async_flow_create(struct rte_eth_dev *dev,
4092 : : uint32_t queue,
4093 : : const struct rte_flow_op_attr *attr,
4094 : : struct rte_flow_template_table *table,
4095 : : const struct rte_flow_item items[],
4096 : : uint8_t pattern_template_index,
4097 : : const struct rte_flow_action actions[],
4098 : : uint8_t action_template_index,
4099 : : void *user_data,
4100 : : struct rte_flow_error *error)
4101 : : {
4102 : : uint32_t rule_index = UINT32_MAX;
4103 : :
4104 [ # # ]: 0 : return flow_hw_async_flow_create_generic(dev, queue, attr, table,
4105 : : RTE_FLOW_TABLE_INSERTION_TYPE_PATTERN, rule_index,
4106 : : items, pattern_template_index, actions, action_template_index,
4107 : : user_data, error);
4108 : : }
4109 : :
4110 : : static struct rte_flow *
4111 : 0 : flow_hw_async_flow_create_by_index(struct rte_eth_dev *dev,
4112 : : uint32_t queue,
4113 : : const struct rte_flow_op_attr *attr,
4114 : : struct rte_flow_template_table *table,
4115 : : uint32_t rule_index,
4116 : : const struct rte_flow_action actions[],
4117 : : uint8_t action_template_index,
4118 : : void *user_data,
4119 : : struct rte_flow_error *error)
4120 : : {
4121 : 0 : struct rte_flow_item items[] = {{.type = RTE_FLOW_ITEM_TYPE_END,}};
4122 : : uint8_t pattern_template_index = 0;
4123 : :
4124 [ # # ]: 0 : return flow_hw_async_flow_create_generic(dev, queue, attr, table,
4125 : : RTE_FLOW_TABLE_INSERTION_TYPE_INDEX, rule_index,
4126 : : items, pattern_template_index, actions, action_template_index,
4127 : : user_data, error);
4128 : : }
4129 : :
4130 : : static struct rte_flow *
4131 : 0 : flow_hw_async_flow_create_by_index_with_pattern(struct rte_eth_dev *dev,
4132 : : uint32_t queue,
4133 : : const struct rte_flow_op_attr *attr,
4134 : : struct rte_flow_template_table *table,
4135 : : uint32_t rule_index,
4136 : : const struct rte_flow_item items[],
4137 : : uint8_t pattern_template_index,
4138 : : const struct rte_flow_action actions[],
4139 : : uint8_t action_template_index,
4140 : : void *user_data,
4141 : : struct rte_flow_error *error)
4142 : : {
4143 [ # # ]: 0 : return flow_hw_async_flow_create_generic(dev, queue, attr, table,
4144 : : RTE_FLOW_TABLE_INSERTION_TYPE_INDEX_WITH_PATTERN, rule_index,
4145 : : items, pattern_template_index, actions, action_template_index,
4146 : : user_data, error);
4147 : : }
4148 : :
4149 : : /**
4150 : : * Enqueue HW steering flow update.
4151 : : *
4152 : : * The flow will be applied to the HW only if the postpone bit is not set or
4153 : : * the extra push function is called.
4154 : : * The flow destruction status should be checked from dequeue result.
4155 : : *
4156 : : * @param[in] dev
4157 : : * Pointer to the rte_eth_dev structure.
4158 : : * @param[in] queue
4159 : : * The queue to destroy the flow.
4160 : : * @param[in] attr
4161 : : * Pointer to the flow operation attributes.
4162 : : * @param[in] flow
4163 : : * Pointer to the flow to be destroyed.
4164 : : * @param[in] actions
4165 : : * Action with flow spec value.
4166 : : * @param[in] action_template_index
4167 : : * The action pattern flow follows from the table.
4168 : : * @param[in] user_data
4169 : : * Pointer to the user_data.
4170 : : * @param[out] error
4171 : : * Pointer to error structure.
4172 : : *
4173 : : * @return
4174 : : * 0 on success, negative value otherwise and rte_errno is set.
4175 : : */
4176 : : static int
4177 : 0 : flow_hw_async_flow_update(struct rte_eth_dev *dev,
4178 : : uint32_t queue,
4179 : : const struct rte_flow_op_attr *attr,
4180 : : struct rte_flow *flow,
4181 : : const struct rte_flow_action actions[],
4182 : : uint8_t action_template_index,
4183 : : void *user_data,
4184 : : struct rte_flow_error *error)
4185 : : {
4186 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4187 : 0 : struct mlx5dr_rule_attr rule_attr = {
4188 : : .queue_id = queue,
4189 : : .user_data = user_data,
4190 : 0 : .burst = attr->postpone,
4191 : : };
4192 : : struct mlx5dr_rule_action *rule_acts;
4193 : : struct rte_flow_hw *of = (struct rte_flow_hw *)flow;
4194 : : struct rte_flow_hw *nf;
4195 : : struct rte_flow_hw_aux *aux;
4196 : 0 : struct rte_flow_template_table *table = of->table;
4197 : 0 : uint32_t res_idx = 0;
4198 : : int ret;
4199 : :
4200 [ # # ]: 0 : if (mlx5_fp_debug_enabled()) {
4201 [ # # ]: 0 : if (flow_hw_async_update_validate(dev, queue, of, actions, action_template_index,
4202 : : error))
4203 : 0 : return -rte_errno;
4204 : : }
4205 : 0 : aux = mlx5_flow_hw_aux(dev->data->port_id, of);
4206 [ # # ]: 0 : nf = &aux->upd_flow;
4207 : : memset(nf, 0, sizeof(struct rte_flow_hw));
4208 : 0 : rule_acts = flow_hw_get_dr_action_buffer(priv, table, action_template_index, queue);
4209 : : /*
4210 : : * Set the table here in order to know the destination table
4211 : : * when free the flow afterwards.
4212 : : */
4213 : 0 : nf->table = table;
4214 : 0 : nf->mt_idx = of->mt_idx;
4215 : 0 : nf->idx = of->idx;
4216 [ # # ]: 0 : if (table->resource) {
4217 : 0 : mlx5_ipool_malloc(table->resource, &res_idx);
4218 [ # # ]: 0 : if (!res_idx) {
4219 : 0 : rte_errno = ENOMEM;
4220 : 0 : goto error;
4221 : : }
4222 : 0 : nf->res_idx = res_idx;
4223 : : } else {
4224 : 0 : nf->res_idx = of->res_idx;
4225 : : }
4226 : 0 : nf->flags = 0;
4227 : : /* Indicate the construction function to set the proper fields. */
4228 : 0 : nf->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE;
4229 : : /*
4230 : : * Indexed pool returns 1-based indices, but mlx5dr expects 0-based indices
4231 : : * for rule insertion hints.
4232 : : * If there is only one STE, the update will be atomic by nature.
4233 : : */
4234 : 0 : nf->rule_idx = nf->res_idx - 1;
4235 : 0 : rule_attr.rule_idx = nf->rule_idx;
4236 : : /*
4237 : : * Construct the flow actions based on the input actions.
4238 : : * The implicitly appended action is always fixed, like metadata
4239 : : * copy action from FDB to NIC Rx.
4240 : : * No need to copy and contrust a new "actions" list based on the
4241 : : * user's input, in order to save the cost.
4242 : : */
4243 [ # # ]: 0 : if (flow_hw_actions_construct(dev, nf, &priv->hw_q[queue].ap,
4244 : 0 : &table->ats[action_template_index],
4245 [ # # ]: 0 : table->its[nf->mt_idx]->item_flags,
4246 : : table, actions,
4247 : : rule_acts, queue, error)) {
4248 : 0 : rte_errno = EINVAL;
4249 : 0 : goto error;
4250 : : }
4251 : : /*
4252 : : * Set the flow operation type here in order to know if the flow memory
4253 : : * should be freed or not when get the result from dequeue.
4254 : : */
4255 : 0 : of->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE;
4256 : 0 : of->user_data = user_data;
4257 : 0 : of->flags |= MLX5_FLOW_HW_FLOW_FLAG_UPD_FLOW;
4258 : 0 : rule_attr.user_data = of;
4259 : 0 : ret = mlx5dr_rule_action_update((struct mlx5dr_rule *)of->rule,
4260 : : action_template_index, rule_acts, &rule_attr);
4261 [ # # ]: 0 : if (likely(!ret)) {
4262 : 0 : flow_hw_q_inc_flow_ops(priv, queue);
4263 : 0 : return 0;
4264 : : }
4265 : 0 : error:
4266 [ # # # # ]: 0 : if (table->resource && res_idx)
4267 : 0 : mlx5_ipool_free(table->resource, res_idx);
4268 : 0 : return rte_flow_error_set(error, rte_errno,
4269 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4270 : : "fail to update rte flow");
4271 : : }
4272 : :
4273 : : /**
4274 : : * Enqueue HW steering flow destruction.
4275 : : *
4276 : : * The flow will be applied to the HW only if the postpone bit is not set or
4277 : : * the extra push function is called.
4278 : : * The flow destruction status should be checked from dequeue result.
4279 : : *
4280 : : * @param[in] dev
4281 : : * Pointer to the rte_eth_dev structure.
4282 : : * @param[in] queue
4283 : : * The queue to destroy the flow.
4284 : : * @param[in] attr
4285 : : * Pointer to the flow operation attributes.
4286 : : * @param[in] flow
4287 : : * Pointer to the flow to be destroyed.
4288 : : * @param[in] user_data
4289 : : * Pointer to the user_data.
4290 : : * @param[out] error
4291 : : * Pointer to error structure.
4292 : : *
4293 : : * @return
4294 : : * 0 on success, negative value otherwise and rte_errno is set.
4295 : : */
4296 : : static int
4297 : 0 : flow_hw_async_flow_destroy(struct rte_eth_dev *dev,
4298 : : uint32_t queue,
4299 : : const struct rte_flow_op_attr *attr,
4300 : : struct rte_flow *flow,
4301 : : void *user_data,
4302 : : struct rte_flow_error *error)
4303 : : {
4304 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4305 : 0 : struct mlx5dr_rule_attr rule_attr = {
4306 : : .queue_id = queue,
4307 : : .user_data = user_data,
4308 : 0 : .burst = attr->postpone,
4309 : : };
4310 : : struct rte_flow_hw *fh = (struct rte_flow_hw *)flow;
4311 : 0 : bool resizable = rte_flow_template_table_resizable(dev->data->port_id,
4312 : 0 : &fh->table->cfg.attr);
4313 : : int ret;
4314 : :
4315 : : if (mlx5_fp_debug_enabled()) {
4316 : : if (flow_hw_async_destroy_validate(dev, queue, fh, error))
4317 : : return -rte_errno;
4318 : : }
4319 [ # # ]: 0 : fh->operation_type = !resizable ?
4320 : : MLX5_FLOW_HW_FLOW_OP_TYPE_DESTROY :
4321 : : MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_DESTROY;
4322 : 0 : fh->user_data = user_data;
4323 : 0 : rule_attr.user_data = fh;
4324 : 0 : rule_attr.rule_idx = fh->rule_idx;
4325 : 0 : ret = mlx5dr_rule_destroy((struct mlx5dr_rule *)fh->rule, &rule_attr);
4326 [ # # ]: 0 : if (ret) {
4327 : 0 : return rte_flow_error_set(error, rte_errno,
4328 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4329 : : "fail to destroy rte flow");
4330 : : }
4331 : : flow_hw_q_inc_flow_ops(priv, queue);
4332 : 0 : return 0;
4333 : : }
4334 : :
4335 : : /**
4336 : : * Release the AGE and counter for given flow.
4337 : : *
4338 : : * @param[in] priv
4339 : : * Pointer to the port private data structure.
4340 : : * @param[in] queue
4341 : : * The queue to release the counter.
4342 : : * @param[in, out] flow
4343 : : * Pointer to the flow containing the counter.
4344 : : * @param[out] error
4345 : : * Pointer to error structure.
4346 : : */
4347 : : static void
4348 : 0 : flow_hw_age_count_release(struct mlx5_priv *priv, uint32_t queue,
4349 : : struct rte_flow_hw *flow,
4350 : : struct rte_flow_error *error)
4351 : : {
4352 : 0 : struct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(priv->dev_data->port_id, flow);
4353 : : uint32_t *cnt_queue;
4354 : 0 : uint32_t age_idx = aux->orig.age_idx;
4355 : :
4356 : : MLX5_ASSERT(flow->flags & MLX5_FLOW_HW_FLOW_FLAG_CNT_ID);
4357 [ # # # # ]: 0 : if (mlx5_hws_cnt_is_shared(priv->hws_cpool, flow->cnt_id)) {
4358 [ # # # # ]: 0 : if ((flow->flags & MLX5_FLOW_HW_FLOW_FLAG_AGE_IDX) &&
4359 : : !mlx5_hws_age_is_indirect(age_idx)) {
4360 : : /* Remove this AGE parameter from indirect counter. */
4361 : : mlx5_hws_cnt_age_set(priv->hws_cpool, flow->cnt_id, 0);
4362 : : /* Release the AGE parameter. */
4363 : 0 : mlx5_hws_age_action_destroy(priv, age_idx, error);
4364 : : }
4365 : 0 : return;
4366 : : }
4367 : : cnt_queue = mlx5_hws_cnt_get_queue(priv, &queue);
4368 : : /* Put the counter first to reduce the race risk in BG thread. */
4369 [ # # ]: 0 : mlx5_hws_cnt_pool_put(priv->hws_cpool, cnt_queue, &flow->cnt_id);
4370 [ # # ]: 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_AGE_IDX) {
4371 [ # # ]: 0 : if (mlx5_hws_age_is_indirect(age_idx)) {
4372 : 0 : uint32_t idx = age_idx & MLX5_HWS_AGE_IDX_MASK;
4373 : :
4374 : : mlx5_hws_age_nb_cnt_decrease(priv, idx);
4375 : : } else {
4376 : : /* Release the AGE parameter. */
4377 : 0 : mlx5_hws_age_action_destroy(priv, age_idx, error);
4378 : : }
4379 : : }
4380 : : }
4381 : :
4382 : : static __rte_always_inline void
4383 : : flow_hw_pull_legacy_indirect_comp(struct rte_eth_dev *dev, struct mlx5_hw_q_job *job,
4384 : : uint32_t queue)
4385 : : {
4386 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4387 : : struct mlx5_aso_ct_action *aso_ct;
4388 : : struct mlx5_aso_mtr *aso_mtr;
4389 : : uint32_t type, idx;
4390 : :
4391 [ # # ]: 0 : if (MLX5_INDIRECT_ACTION_TYPE_GET(job->action) ==
4392 : : MLX5_INDIRECT_ACTION_TYPE_QUOTA) {
4393 : 0 : mlx5_quota_async_completion(dev, queue, job);
4394 [ # # ]: 0 : } else if (job->type == MLX5_HW_Q_JOB_TYPE_DESTROY) {
4395 : : type = MLX5_INDIRECT_ACTION_TYPE_GET(job->action);
4396 [ # # ]: 0 : if (type == MLX5_INDIRECT_ACTION_TYPE_METER_MARK) {
4397 : 0 : idx = MLX5_INDIRECT_ACTION_IDX_GET(job->action);
4398 : 0 : mlx5_ipool_free(priv->hws_mpool->idx_pool, idx);
4399 : : }
4400 [ # # ]: 0 : } else if (job->type == MLX5_HW_Q_JOB_TYPE_CREATE) {
4401 : : type = MLX5_INDIRECT_ACTION_TYPE_GET(job->action);
4402 [ # # ]: 0 : if (type == MLX5_INDIRECT_ACTION_TYPE_METER_MARK) {
4403 : 0 : idx = MLX5_INDIRECT_ACTION_IDX_GET(job->action);
4404 : 0 : aso_mtr = mlx5_ipool_get(priv->hws_mpool->idx_pool, idx);
4405 : 0 : aso_mtr->state = ASO_METER_READY;
4406 [ # # ]: 0 : } else if (type == MLX5_INDIRECT_ACTION_TYPE_CT) {
4407 : 0 : idx = MLX5_INDIRECT_ACTION_IDX_GET(job->action);
4408 : 0 : aso_ct = mlx5_ipool_get(priv->hws_ctpool->cts, idx);
4409 : 0 : aso_ct->state = ASO_CONNTRACK_READY;
4410 : : }
4411 [ # # ]: 0 : } else if (job->type == MLX5_HW_Q_JOB_TYPE_QUERY) {
4412 : : type = MLX5_INDIRECT_ACTION_TYPE_GET(job->action);
4413 [ # # ]: 0 : if (type == MLX5_INDIRECT_ACTION_TYPE_CT) {
4414 : 0 : idx = MLX5_INDIRECT_ACTION_IDX_GET(job->action);
4415 : 0 : aso_ct = mlx5_ipool_get(priv->hws_ctpool->cts, idx);
4416 : 0 : mlx5_aso_ct_obj_analyze(job->query.user,
4417 : 0 : job->query.hw);
4418 : 0 : aso_ct->state = ASO_CONNTRACK_READY;
4419 : : }
4420 : : }
4421 : : }
4422 : :
4423 : : static __rte_always_inline int
4424 : : mlx5_hw_pull_flow_transfer_comp(struct rte_eth_dev *dev,
4425 : : uint32_t queue, struct rte_flow_op_result res[],
4426 : : uint16_t n_res)
4427 : : {
4428 : : uint32_t size, i;
4429 : 0 : struct rte_flow_hw *flow = NULL;
4430 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4431 : 0 : struct rte_ring *ring = priv->hw_q[queue].flow_transfer_completed;
4432 : :
4433 : 0 : size = RTE_MIN(rte_ring_count(ring), n_res);
4434 [ # # ]: 0 : for (i = 0; i < size; i++) {
4435 [ # # # # : 0 : res[i].status = RTE_FLOW_OP_SUCCESS;
# ]
4436 : : rte_ring_dequeue(ring, (void **)&flow);
4437 : 0 : res[i].user_data = flow->user_data;
4438 : : flow_hw_q_dec_flow_ops(priv, queue);
4439 : : }
4440 : 0 : return (int)size;
4441 : : }
4442 : :
4443 : : static inline int
4444 : 0 : __flow_hw_pull_indir_action_comp(struct rte_eth_dev *dev,
4445 : : uint32_t queue,
4446 : : struct rte_flow_op_result res[],
4447 : : uint16_t n_res)
4448 : :
4449 : : {
4450 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4451 : 0 : struct rte_ring *r = priv->hw_q[queue].indir_cq;
4452 : 0 : void *user_data = NULL;
4453 : : int ret_comp, i;
4454 : :
4455 : 0 : ret_comp = (int)rte_ring_count(r);
4456 : 0 : if (ret_comp > n_res)
4457 : : ret_comp = n_res;
4458 [ # # ]: 0 : for (i = 0; i < ret_comp; i++) {
4459 : : rte_ring_dequeue(r, &user_data);
4460 : 0 : res[i].user_data = user_data;
4461 : 0 : res[i].status = RTE_FLOW_OP_SUCCESS;
4462 : : }
4463 [ # # ]: 0 : if (!priv->shared_host) {
4464 [ # # # # ]: 0 : if (ret_comp < n_res && priv->hws_mpool)
4465 : 0 : ret_comp += mlx5_aso_pull_completion(&priv->hws_mpool->sq[queue],
4466 : 0 : &res[ret_comp], n_res - ret_comp);
4467 [ # # # # ]: 0 : if (ret_comp < n_res && priv->hws_ctpool)
4468 : 0 : ret_comp += mlx5_aso_pull_completion(&priv->ct_mng->aso_sqs[queue],
4469 : 0 : &res[ret_comp], n_res - ret_comp);
4470 : : }
4471 [ # # # # ]: 0 : if (ret_comp < n_res && priv->quota_ctx.sq)
4472 : 0 : ret_comp += mlx5_aso_pull_completion(&priv->quota_ctx.sq[queue],
4473 : 0 : &res[ret_comp],
4474 : 0 : n_res - ret_comp);
4475 [ # # ]: 0 : for (i = 0; i < ret_comp; i++) {
4476 : 0 : struct mlx5_hw_q_job *job = (struct mlx5_hw_q_job *)res[i].user_data;
4477 : :
4478 : : /* Restore user data. */
4479 : 0 : res[i].user_data = job->user_data;
4480 [ # # ]: 0 : if (job->indirect_type == MLX5_HW_INDIRECT_TYPE_LEGACY)
4481 : : flow_hw_pull_legacy_indirect_comp(dev, job, queue);
4482 : : /*
4483 : : * Current PMD supports 2 indirect action list types - MIRROR and REFORMAT.
4484 : : * These indirect list types do not post WQE to create action.
4485 : : * Future indirect list types that do post WQE will add
4486 : : * completion handlers here.
4487 : : */
4488 : : flow_hw_job_put(priv, job, queue);
4489 : : }
4490 : 0 : return ret_comp;
4491 : : }
4492 : :
4493 : : static __rte_always_inline void
4494 : : hw_cmpl_flow_update_or_destroy(struct rte_eth_dev *dev,
4495 : : struct rte_flow_hw *flow,
4496 : : uint32_t queue, struct rte_flow_error *error)
4497 : : {
4498 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4499 : 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
4500 : 0 : struct rte_flow_template_table *table = flow->table;
4501 : : /* Release the original resource index in case of update. */
4502 : 0 : uint32_t res_idx = flow->res_idx;
4503 : :
4504 [ # # ]: 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAGS_ALL) {
4505 : 0 : struct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
4506 : :
4507 [ # # # # : 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_FATE_JUMP)
# # ]
4508 : 0 : flow_hw_jump_release(dev, flow->jump);
4509 [ # # # # : 0 : else if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_FATE_HRXQ)
# # ]
4510 : 0 : mlx5_hrxq_obj_release(dev, flow->hrxq);
4511 [ # # # # : 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_CNT_ID)
# # ]
4512 : 0 : flow_hw_age_count_release(priv, queue, flow, error);
4513 [ # # # # : 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_MTR_ID)
# # ]
4514 : 0 : mlx5_ipool_free(pool->idx_pool, aux->orig.mtr_id);
4515 [ # # # # : 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_UPD_FLOW) {
# # ]
4516 [ # # # # : 0 : struct rte_flow_hw *upd_flow = &aux->upd_flow;
# # ]
4517 : :
4518 : : rte_memcpy(flow, upd_flow, offsetof(struct rte_flow_hw, rule));
4519 : 0 : aux->orig = aux->upd;
4520 : 0 : flow->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_CREATE;
4521 [ # # # # : 0 : if (!flow->nt_rule && table->resource)
# # # # #
# # # ]
4522 : 0 : mlx5_ipool_free(table->resource, res_idx);
4523 : : }
4524 : : }
4525 [ # # # # : 0 : if (flow->operation_type == MLX5_FLOW_HW_FLOW_OP_TYPE_DESTROY ||
# # ]
4526 : : flow->operation_type == MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_DESTROY) {
4527 [ # # # # : 0 : if (!flow->nt_rule) {
# # ]
4528 [ # # # # : 0 : if (table->resource)
# # ]
4529 : 0 : mlx5_ipool_free(table->resource, res_idx);
4530 : 0 : mlx5_ipool_free(table->flow, flow->idx);
4531 : : }
4532 : : }
4533 : : }
4534 : :
4535 : : static __rte_always_inline void
4536 : : hw_cmpl_resizable_tbl(struct rte_eth_dev *dev,
4537 : : struct rte_flow_hw *flow,
4538 : : uint32_t queue, enum rte_flow_op_status status,
4539 : : struct rte_flow_error *error)
4540 : : {
4541 : 0 : struct rte_flow_template_table *table = flow->table;
4542 : 0 : struct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
4543 : 0 : uint32_t selector = aux->matcher_selector;
4544 : 0 : uint32_t other_selector = (selector + 1) & 1;
4545 : :
4546 : : MLX5_ASSERT(flow->flags & MLX5_FLOW_HW_FLOW_FLAG_MATCHER_SELECTOR);
4547 [ # # # # ]: 0 : switch (flow->operation_type) {
4548 : 0 : case MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_CREATE:
4549 : 0 : rte_atomic_fetch_add_explicit
4550 : : (&table->matcher_info[selector].refcnt, 1,
4551 : : rte_memory_order_relaxed);
4552 : 0 : break;
4553 : 0 : case MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_DESTROY:
4554 [ # # ]: 0 : rte_atomic_fetch_sub_explicit
4555 : : (&table->matcher_info[selector].refcnt, 1,
4556 : : rte_memory_order_relaxed);
4557 : : hw_cmpl_flow_update_or_destroy(dev, flow, queue, error);
4558 : : break;
4559 : 0 : case MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_MOVE:
4560 [ # # ]: 0 : if (status == RTE_FLOW_OP_SUCCESS) {
4561 : 0 : rte_atomic_fetch_sub_explicit
4562 : : (&table->matcher_info[selector].refcnt, 1,
4563 : : rte_memory_order_relaxed);
4564 : 0 : rte_atomic_fetch_add_explicit
4565 : : (&table->matcher_info[other_selector].refcnt, 1,
4566 : : rte_memory_order_relaxed);
4567 : 0 : aux->matcher_selector = other_selector;
4568 : : }
4569 : : break;
4570 : : default:
4571 : : break;
4572 : : }
4573 : : }
4574 : :
4575 : : /**
4576 : : * Pull the enqueued flows.
4577 : : *
4578 : : * For flows enqueued from creation/destruction, the status should be
4579 : : * checked from the dequeue result.
4580 : : *
4581 : : * @param[in] dev
4582 : : * Pointer to the rte_eth_dev structure.
4583 : : * @param[in] queue
4584 : : * The queue to pull the result.
4585 : : * @param[in/out] res
4586 : : * Array to save the results.
4587 : : * @param[in] n_res
4588 : : * Available result with the array.
4589 : : * @param[out] error
4590 : : * Pointer to error structure.
4591 : : *
4592 : : * @return
4593 : : * Result number on success, negative value otherwise and rte_errno is set.
4594 : : */
4595 : : static int
4596 : 0 : flow_hw_pull(struct rte_eth_dev *dev,
4597 : : uint32_t queue,
4598 : : struct rte_flow_op_result res[],
4599 : : uint16_t n_res,
4600 : : struct rte_flow_error *error)
4601 : : {
4602 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4603 : : int ret, i;
4604 : :
4605 : : /* 1. Pull the flow completion. */
4606 : 0 : ret = mlx5dr_send_queue_poll(priv->dr_ctx, queue, res, n_res);
4607 [ # # ]: 0 : if (ret < 0)
4608 : 0 : return rte_flow_error_set(error, rte_errno,
4609 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4610 : : "fail to query flow queue");
4611 [ # # ]: 0 : for (i = 0; i < ret; i++) {
4612 : 0 : struct rte_flow_hw *flow = res[i].user_data;
4613 : :
4614 : : /* Restore user data. */
4615 : 0 : res[i].user_data = flow->user_data;
4616 [ # # # ]: 0 : switch (flow->operation_type) {
4617 : : case MLX5_FLOW_HW_FLOW_OP_TYPE_DESTROY:
4618 : : case MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE:
4619 : : hw_cmpl_flow_update_or_destroy(dev, flow, queue, error);
4620 : : break;
4621 : 0 : case MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_CREATE:
4622 : : case MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_DESTROY:
4623 : : case MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_MOVE:
4624 : 0 : hw_cmpl_resizable_tbl(dev, flow, queue, res[i].status, error);
4625 : : break;
4626 : : default:
4627 : : break;
4628 : : }
4629 : : flow_hw_q_dec_flow_ops(priv, queue);
4630 : : }
4631 : : /* 2. Pull indirect action comp. */
4632 [ # # ]: 0 : if (ret < n_res)
4633 : 0 : ret += __flow_hw_pull_indir_action_comp(dev, queue, &res[ret],
4634 : 0 : n_res - ret);
4635 [ # # ]: 0 : if (ret < n_res)
4636 : 0 : ret += mlx5_hw_pull_flow_transfer_comp(dev, queue, &res[ret],
4637 : 0 : n_res - ret);
4638 : :
4639 : : return ret;
4640 : : }
4641 : :
4642 : : static uint32_t
4643 : 0 : mlx5_hw_push_queue(struct rte_ring *pending_q, struct rte_ring *cmpl_q)
4644 : : {
4645 : 0 : void *job = NULL;
4646 : : uint32_t i, size = rte_ring_count(pending_q);
4647 : :
4648 [ # # ]: 0 : for (i = 0; i < size; i++) {
4649 : : rte_ring_dequeue(pending_q, &job);
4650 [ # # # # : 0 : rte_ring_enqueue(cmpl_q, job);
# ]
4651 : : }
4652 : 0 : return size;
4653 : : }
4654 : :
4655 : : static inline uint32_t
4656 : 0 : __flow_hw_push_action(struct rte_eth_dev *dev,
4657 : : uint32_t queue)
4658 : : {
4659 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4660 : 0 : struct mlx5_hw_q *hw_q = &priv->hw_q[queue];
4661 : :
4662 : 0 : mlx5_hw_push_queue(hw_q->indir_iq, hw_q->indir_cq);
4663 : 0 : mlx5_hw_push_queue(hw_q->flow_transfer_pending,
4664 : : hw_q->flow_transfer_completed);
4665 [ # # ]: 0 : if (!priv->shared_host) {
4666 [ # # ]: 0 : if (priv->hws_ctpool)
4667 : 0 : mlx5_aso_push_wqe(priv->sh,
4668 : 0 : &priv->ct_mng->aso_sqs[queue]);
4669 [ # # ]: 0 : if (priv->hws_mpool)
4670 : 0 : mlx5_aso_push_wqe(priv->sh,
4671 : 0 : &priv->hws_mpool->sq[queue]);
4672 : : }
4673 : 0 : return flow_hw_q_pending(priv, queue);
4674 : : }
4675 : :
4676 : : static int
4677 : 0 : __flow_hw_push(struct rte_eth_dev *dev,
4678 : : uint32_t queue,
4679 : : struct rte_flow_error *error)
4680 : : {
4681 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4682 : : int ret, num;
4683 : :
4684 : 0 : num = __flow_hw_push_action(dev, queue);
4685 : 0 : ret = mlx5dr_send_queue_action(priv->dr_ctx, queue,
4686 : : MLX5DR_SEND_QUEUE_ACTION_DRAIN_ASYNC);
4687 [ # # ]: 0 : if (ret) {
4688 : 0 : rte_flow_error_set(error, rte_errno,
4689 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4690 : : "fail to push flows");
4691 : 0 : return ret;
4692 : : }
4693 : : return num;
4694 : : }
4695 : :
4696 : : /**
4697 : : * Push the enqueued flows to HW.
4698 : : *
4699 : : * Force apply all the enqueued flows to the HW.
4700 : : *
4701 : : * @param[in] dev
4702 : : * Pointer to the rte_eth_dev structure.
4703 : : * @param[in] queue
4704 : : * The queue to push the flow.
4705 : : * @param[out] error
4706 : : * Pointer to error structure.
4707 : : *
4708 : : * @return
4709 : : * 0 on success, negative value otherwise and rte_errno is set.
4710 : : */
4711 : : static int
4712 : 0 : flow_hw_push(struct rte_eth_dev *dev,
4713 : : uint32_t queue, struct rte_flow_error *error)
4714 : : {
4715 : 0 : int ret = __flow_hw_push(dev, queue, error);
4716 : :
4717 : 0 : return ret >= 0 ? 0 : ret;
4718 : : }
4719 : :
4720 : : /**
4721 : : * Drain the enqueued flows' completion.
4722 : : *
4723 : : * @param[in] dev
4724 : : * Pointer to the rte_eth_dev structure.
4725 : : * @param[in] queue
4726 : : * The queue to pull the flow.
4727 : : * @param[out] error
4728 : : * Pointer to error structure.
4729 : : *
4730 : : * @return
4731 : : * 0 on success, negative value otherwise and rte_errno is set.
4732 : : */
4733 : : static int
4734 : 0 : __flow_hw_pull_comp(struct rte_eth_dev *dev,
4735 : : uint32_t queue, struct rte_flow_error *error)
4736 : : {
4737 : : struct rte_flow_op_result comp[BURST_THR];
4738 : : int ret, i, empty_loop = 0;
4739 : : uint32_t pending_rules;
4740 : :
4741 : 0 : ret = __flow_hw_push(dev, queue, error);
4742 [ # # ]: 0 : if (ret < 0)
4743 : : return ret;
4744 : 0 : pending_rules = ret;
4745 [ # # ]: 0 : while (pending_rules) {
4746 : 0 : ret = flow_hw_pull(dev, queue, comp, BURST_THR, error);
4747 [ # # ]: 0 : if (ret < 0)
4748 : : return -1;
4749 [ # # ]: 0 : if (!ret) {
4750 : 0 : rte_delay_us_sleep(MLX5_ASO_WQE_CQE_RESPONSE_DELAY);
4751 [ # # ]: 0 : if (++empty_loop > 5) {
4752 : 0 : DRV_LOG(WARNING, "No available dequeue %u, quit.", pending_rules);
4753 : 0 : break;
4754 : : }
4755 : 0 : continue;
4756 : : }
4757 [ # # ]: 0 : for (i = 0; i < ret; i++) {
4758 [ # # ]: 0 : if (comp[i].status == RTE_FLOW_OP_ERROR)
4759 : 0 : DRV_LOG(WARNING, "Flow flush get error CQE.");
4760 : : }
4761 : : /*
4762 : : * Indirect **SYNC** METER_MARK and CT actions do not
4763 : : * remove completion after WQE post.
4764 : : * That implementation avoids HW timeout.
4765 : : * The completion is removed before the following WQE post.
4766 : : * However, HWS queue updates do not reflect that behaviour.
4767 : : * Therefore, during port destruction sync queue may have
4768 : : * pending completions.
4769 : : */
4770 : 0 : pending_rules -= RTE_MIN(pending_rules, (uint32_t)ret);
4771 : : empty_loop = 0;
4772 : : }
4773 : : return 0;
4774 : : }
4775 : :
4776 : : /**
4777 : : * Flush created flows.
4778 : : *
4779 : : * @param[in] dev
4780 : : * Pointer to the rte_eth_dev structure.
4781 : : * @param[out] error
4782 : : * Pointer to error structure.
4783 : : *
4784 : : * @return
4785 : : * 0 on success, negative value otherwise and rte_errno is set.
4786 : : */
4787 : : int
4788 : 0 : flow_hw_q_flow_flush(struct rte_eth_dev *dev,
4789 : : struct rte_flow_error *error)
4790 : : {
4791 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4792 : 0 : struct mlx5_hw_q *hw_q = &priv->hw_q[MLX5_DEFAULT_FLUSH_QUEUE];
4793 : : struct rte_flow_template_table *tbl;
4794 : : struct rte_flow_hw *flow;
4795 : 0 : struct rte_flow_op_attr attr = {
4796 : : .postpone = 0,
4797 : : };
4798 : : uint32_t pending_rules = 0;
4799 : : uint32_t queue;
4800 : : uint32_t fidx;
4801 : :
4802 : : /*
4803 : : * Ensure to push and dequeue all the enqueued flow
4804 : : * creation/destruction jobs in case user forgot to
4805 : : * dequeue. Or the enqueued created flows will be
4806 : : * leaked. The forgotten dequeues would also cause
4807 : : * flow flush get extra CQEs as expected and pending_rules
4808 : : * be minus value.
4809 : : */
4810 [ # # ]: 0 : for (queue = 0; queue < priv->nb_queue; queue++) {
4811 [ # # ]: 0 : if (__flow_hw_pull_comp(dev, queue, error))
4812 : : return -1;
4813 : : }
4814 : : /* Flush flow per-table from MLX5_DEFAULT_FLUSH_QUEUE. */
4815 [ # # ]: 0 : LIST_FOREACH(tbl, &priv->flow_hw_tbl, next) {
4816 [ # # ]: 0 : if (!tbl->cfg.external)
4817 : 0 : continue;
4818 [ # # ]: 0 : MLX5_IPOOL_FOREACH(tbl->flow, fidx, flow) {
4819 [ # # ]: 0 : if (flow_hw_async_flow_destroy(dev,
4820 : : MLX5_DEFAULT_FLUSH_QUEUE,
4821 : : &attr,
4822 : : (struct rte_flow *)flow,
4823 : : NULL,
4824 : : error))
4825 : : return -1;
4826 : 0 : pending_rules++;
4827 : : /* Drain completion with queue size. */
4828 [ # # ]: 0 : if (pending_rules >= hw_q->size) {
4829 [ # # ]: 0 : if (__flow_hw_pull_comp(dev,
4830 : : MLX5_DEFAULT_FLUSH_QUEUE,
4831 : : error))
4832 : : return -1;
4833 : : pending_rules = 0;
4834 : : }
4835 : : }
4836 : : }
4837 : : /* Drain left completion. */
4838 [ # # # # ]: 0 : if (pending_rules &&
4839 : 0 : __flow_hw_pull_comp(dev, MLX5_DEFAULT_FLUSH_QUEUE, error))
4840 : 0 : return -1;
4841 : : return 0;
4842 : : }
4843 : :
4844 : : static int
4845 : 0 : mlx5_tbl_multi_pattern_process(struct rte_eth_dev *dev,
4846 : : struct rte_flow_template_table *tbl,
4847 : : struct mlx5_multi_pattern_segment *segment,
4848 : : uint32_t bulk_size,
4849 : : struct rte_flow_error *error)
4850 : : {
4851 : : int ret = 0;
4852 : : uint32_t i;
4853 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4854 : : bool unified_fdb = is_unified_fdb(priv);
4855 : : struct mlx5_tbl_multi_pattern_ctx *mpctx = &tbl->mpctx;
4856 : : const struct rte_flow_template_table_attr *table_attr = &tbl->cfg.attr;
4857 : 0 : const struct rte_flow_attr *attr = &table_attr->flow_attr;
4858 : : enum mlx5dr_table_type type =
4859 : 0 : get_mlx5dr_table_type(attr, table_attr->specialize, unified_fdb);
4860 : 0 : uint32_t flags = mlx5_hw_act_flag[!!attr->group][type];
4861 : : struct mlx5dr_action *dr_action = NULL;
4862 : :
4863 [ # # ]: 0 : for (i = 0; i < MLX5_MULTIPATTERN_ENCAP_NUM; i++) {
4864 [ # # ]: 0 : typeof(mpctx->reformat[0]) *reformat = mpctx->reformat + i;
4865 : : enum mlx5dr_action_type reformat_type =
4866 : : mlx5_multi_pattern_reformat_index_to_type(i);
4867 : :
4868 [ # # ]: 0 : if (!reformat->elements_num)
4869 : 0 : continue;
4870 : : dr_action = reformat_type == MLX5DR_ACTION_TYP_INSERT_HEADER ?
4871 : : mlx5dr_action_create_insert_header
4872 : : (priv->dr_ctx, reformat->elements_num,
4873 : : reformat->insert_hdr, bulk_size, flags) :
4874 : 0 : mlx5dr_action_create_reformat
4875 : : (priv->dr_ctx, reformat_type, reformat->elements_num,
4876 : 0 : reformat->reformat_hdr, bulk_size, flags);
4877 [ # # ]: 0 : if (!dr_action) {
4878 : 0 : ret = rte_flow_error_set(error, rte_errno,
4879 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4880 : : NULL,
4881 : : "failed to create multi-pattern encap action");
4882 : 0 : goto error;
4883 : : }
4884 : 0 : segment->reformat_action[i] = dr_action;
4885 : : }
4886 [ # # ]: 0 : if (mpctx->mh.elements_num) {
4887 : : typeof(mpctx->mh) *mh = &mpctx->mh;
4888 : 0 : dr_action = mlx5dr_action_create_modify_header
4889 : 0 : (priv->dr_ctx, mpctx->mh.elements_num, mh->pattern,
4890 : : bulk_size, flags);
4891 [ # # ]: 0 : if (!dr_action) {
4892 : 0 : ret = rte_flow_error_set(error, rte_errno,
4893 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4894 : : NULL, "failed to create multi-pattern header modify action");
4895 : 0 : goto error;
4896 : : }
4897 : 0 : segment->mhdr_action = dr_action;
4898 : : }
4899 [ # # ]: 0 : if (dr_action) {
4900 : 0 : segment->capacity = RTE_BIT32(bulk_size);
4901 [ # # ]: 0 : if (segment != &mpctx->segments[MLX5_MAX_TABLE_RESIZE_NUM - 1])
4902 : 0 : segment[1].head_index = segment->head_index + segment->capacity;
4903 : : }
4904 : : return 0;
4905 : 0 : error:
4906 : 0 : mlx5_destroy_multi_pattern_segment(segment);
4907 : 0 : return ret;
4908 : : }
4909 : :
4910 : : static int
4911 : 0 : mlx5_hw_build_template_table(struct rte_eth_dev *dev,
4912 : : uint8_t nb_action_templates,
4913 : : struct rte_flow_actions_template *action_templates[],
4914 : : struct mlx5dr_action_template *at[],
4915 : : struct rte_flow_template_table *tbl,
4916 : : struct rte_flow_error *error)
4917 : : {
4918 : : int ret;
4919 : : uint8_t i;
4920 : :
4921 [ # # ]: 0 : for (i = 0; i < nb_action_templates; i++) {
4922 : 0 : uint32_t refcnt = rte_atomic_fetch_add_explicit(&action_templates[i]->refcnt, 1,
4923 : : rte_memory_order_relaxed) + 1;
4924 : :
4925 [ # # ]: 0 : if (refcnt <= 1) {
4926 : 0 : rte_flow_error_set(error, EINVAL,
4927 : : RTE_FLOW_ERROR_TYPE_ACTION,
4928 : : &action_templates[i], "invalid AT refcount");
4929 : 0 : goto at_error;
4930 : : }
4931 : 0 : at[i] = action_templates[i]->tmpl;
4932 : 0 : tbl->ats[i].action_template = action_templates[i];
4933 : 0 : LIST_INIT(&tbl->ats[i].acts.act_list);
4934 : : /* do NOT translate table action if `dev` was not started */
4935 [ # # ]: 0 : if (!dev->data->dev_started)
4936 : 0 : continue;
4937 : 0 : ret = flow_hw_translate_actions_template(dev, &tbl->cfg,
4938 : : &tbl->ats[i].acts,
4939 : : action_templates[i],
4940 : : &tbl->mpctx, error);
4941 [ # # ]: 0 : if (ret) {
4942 : 0 : i++;
4943 : 0 : goto at_error;
4944 : : }
4945 : 0 : flow_hw_populate_rule_acts_caches(dev, tbl, i);
4946 : : }
4947 [ # # ]: 0 : tbl->nb_action_templates = nb_action_templates;
4948 [ # # ]: 0 : if (mlx5_is_multi_pattern_active(&tbl->mpctx)) {
4949 [ # # ]: 0 : ret = mlx5_tbl_multi_pattern_process(dev, tbl,
4950 : : &tbl->mpctx.segments[0],
4951 : : rte_log2_u32(tbl->cfg.attr.nb_flows),
4952 : : error);
4953 [ # # ]: 0 : if (ret)
4954 : 0 : goto at_error;
4955 : : }
4956 : : return 0;
4957 : :
4958 : : at_error:
4959 [ # # ]: 0 : while (i--) {
4960 : 0 : __flow_hw_action_template_destroy(dev, &tbl->ats[i].acts);
4961 : 0 : rte_atomic_fetch_sub_explicit(&action_templates[i]->refcnt,
4962 : : 1, rte_memory_order_relaxed);
4963 : : }
4964 : 0 : return rte_errno;
4965 : : }
4966 : :
4967 : : static bool
4968 : : flow_hw_validate_template_domain(const struct rte_flow_attr *table_attr,
4969 : : uint32_t ingress, uint32_t egress, uint32_t transfer)
4970 : : {
4971 : 0 : if (table_attr->ingress)
4972 : : return ingress != 0;
4973 [ # # # # ]: 0 : else if (table_attr->egress)
4974 : : return egress != 0;
4975 : : else
4976 : 0 : return transfer;
4977 : : }
4978 : :
4979 : : static bool
4980 : : flow_hw_validate_table_domain(const struct rte_flow_attr *table_attr)
4981 : : {
4982 : 0 : return table_attr->ingress + table_attr->egress + table_attr->transfer
4983 : : == 1;
4984 : : }
4985 : :
4986 : : /**
4987 : : * Create flow table.
4988 : : *
4989 : : * The input item and action templates will be binded to the table.
4990 : : * Flow memory will also be allocated. Matcher will be created based
4991 : : * on the item template. Action will be translated to the dedicated
4992 : : * DR action if possible.
4993 : : *
4994 : : * @param[in] dev
4995 : : * Pointer to the rte_eth_dev structure.
4996 : : * @param[in] table_cfg
4997 : : * Pointer to the table configuration.
4998 : : * @param[in] item_templates
4999 : : * Item template array to be binded to the table.
5000 : : * @param[in] nb_item_templates
5001 : : * Number of item template.
5002 : : * @param[in] action_templates
5003 : : * Action template array to be binded to the table.
5004 : : * @param[in] nb_action_templates
5005 : : * Number of action template.
5006 : : * @param[out] error
5007 : : * Pointer to error structure.
5008 : : *
5009 : : * @return
5010 : : * Table on success, NULL otherwise and rte_errno is set.
5011 : : */
5012 : : static struct rte_flow_template_table *
5013 : 0 : flow_hw_table_create(struct rte_eth_dev *dev,
5014 : : const struct mlx5_flow_template_table_cfg *table_cfg,
5015 : : struct rte_flow_pattern_template *item_templates[],
5016 : : uint8_t nb_item_templates,
5017 : : struct rte_flow_actions_template *action_templates[],
5018 : : uint8_t nb_action_templates,
5019 : : struct rte_flow_error *error)
5020 : : {
5021 : 0 : struct rte_flow_error sub_error = {
5022 : : .type = RTE_FLOW_ERROR_TYPE_NONE,
5023 : : .cause = NULL,
5024 : : .message = NULL,
5025 : : };
5026 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
5027 : : bool unified_fdb = is_unified_fdb(priv);
5028 : 0 : struct mlx5dr_matcher_attr matcher_attr = {0};
5029 : 0 : struct mlx5dr_action_jump_to_matcher_attr jump_attr = {
5030 : : .type = MLX5DR_ACTION_JUMP_TO_MATCHER_BY_INDEX,
5031 : : .matcher = NULL,
5032 : : };
5033 : : struct rte_flow_template_table *tbl = NULL;
5034 : : struct mlx5_flow_group *grp;
5035 : : struct mlx5dr_match_template *mt[MLX5_HW_TBL_MAX_ITEM_TEMPLATE];
5036 : : struct mlx5dr_action_template *at[MLX5_HW_TBL_MAX_ACTION_TEMPLATE];
5037 : 0 : const struct rte_flow_template_table_attr *attr = &table_cfg->attr;
5038 : 0 : struct rte_flow_attr flow_attr = attr->flow_attr;
5039 : 0 : uint32_t specialize = table_cfg->attr.specialize;
5040 : 0 : struct mlx5_flow_cb_ctx ctx = {
5041 : : .dev = dev,
5042 : : .error = &sub_error,
5043 : : .data = &flow_attr,
5044 : : .data2 = &specialize,
5045 : : };
5046 : 0 : struct mlx5_indexed_pool_config cfg = {
5047 : : .trunk_size = 1 << 12,
5048 : : .per_core_cache = 1 << 13,
5049 : : .need_lock = 1,
5050 : 0 : .release_mem_en = !!priv->sh->config.reclaim_mode,
5051 : : .malloc = mlx5_malloc,
5052 : : .free = mlx5_free,
5053 : : .type = "mlx5_hw_table_flow",
5054 : : };
5055 : : struct mlx5_list_entry *ge;
5056 : : uint32_t i = 0, max_tpl = MLX5_HW_TBL_MAX_ITEM_TEMPLATE;
5057 [ # # ]: 0 : uint32_t nb_flows = rte_align32pow2(attr->nb_flows);
5058 : 0 : bool port_started = !!dev->data->dev_started;
5059 : : bool rpool_needed;
5060 : : size_t tbl_mem_size;
5061 : : enum mlx5dr_table_type table_type;
5062 : : int err;
5063 : :
5064 [ # # ]: 0 : if (!flow_hw_validate_table_domain(&attr->flow_attr)) {
5065 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ATTR,
5066 : : NULL, "invalid table domain attributes");
5067 : 0 : return NULL;
5068 : : }
5069 [ # # ]: 0 : for (i = 0; i < nb_item_templates; i++) {
5070 : : const struct rte_flow_pattern_template_attr *pt_attr =
5071 : 0 : &item_templates[i]->attr;
5072 : : bool match = flow_hw_validate_template_domain(&attr->flow_attr,
5073 : 0 : pt_attr->ingress,
5074 : 0 : pt_attr->egress,
5075 [ # # ]: 0 : pt_attr->transfer);
5076 [ # # ]: 0 : if (!match) {
5077 : 0 : rte_flow_error_set(error, EINVAL,
5078 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5079 : : NULL, "pattern template domain does not match table");
5080 : 0 : return NULL;
5081 : : }
5082 [ # # # # ]: 0 : if (item_templates[i]->item_flags & MLX5_FLOW_LAYER_ECPRI &&
5083 : 0 : !mlx5_flex_parser_ecpri_exist(dev))
5084 [ # # ]: 0 : if (mlx5_flex_parser_ecpri_alloc(dev)) {
5085 : 0 : rte_flow_error_set(error, EIO,
5086 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5087 : : NULL,
5088 : : "failed to create Flex parser "
5089 : : "profile for ECPRI");
5090 : 0 : goto error;
5091 : : }
5092 : : }
5093 [ # # ]: 0 : for (i = 0; i < nb_action_templates; i++) {
5094 : 0 : const struct rte_flow_actions_template *at = action_templates[i];
5095 : : bool match = flow_hw_validate_template_domain(&attr->flow_attr,
5096 : 0 : at->attr.ingress,
5097 : 0 : at->attr.egress,
5098 [ # # ]: 0 : at->attr.transfer);
5099 [ # # ]: 0 : if (!match) {
5100 : 0 : rte_flow_error_set(error, EINVAL,
5101 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5102 : : NULL, "action template domain does not match table");
5103 : 0 : return NULL;
5104 : : }
5105 : : }
5106 : : /* HWS layer accepts only 1 item template with root table. */
5107 [ # # ]: 0 : if (!attr->flow_attr.group)
5108 : : max_tpl = 1;
5109 : 0 : cfg.max_idx = nb_flows;
5110 [ # # ]: 0 : cfg.size = !rte_flow_template_table_resizable(dev->data->port_id, attr) ?
5111 : : mlx5_flow_hw_entry_size() :
5112 : : mlx5_flow_hw_auxed_entry_size();
5113 : : /* For table has very limited flows, disable cache. */
5114 [ # # ]: 0 : if (nb_flows < cfg.trunk_size) {
5115 : 0 : cfg.per_core_cache = 0;
5116 : 0 : cfg.trunk_size = nb_flows;
5117 [ # # ]: 0 : } else if (nb_flows <= MLX5_HW_IPOOL_SIZE_THRESHOLD) {
5118 : 0 : cfg.per_core_cache = MLX5_HW_IPOOL_CACHE_MIN;
5119 : : }
5120 : : /* Check if we requires too many templates. */
5121 [ # # # # ]: 0 : if (nb_item_templates > max_tpl ||
5122 : : nb_action_templates > MLX5_HW_TBL_MAX_ACTION_TEMPLATE) {
5123 : 0 : rte_errno = EINVAL;
5124 : 0 : goto error;
5125 : : }
5126 : : /*
5127 : : * Amount of memory required for rte_flow_template_table struct:
5128 : : * - Size of the struct itself.
5129 : : * - VLA of DR rule action containers at the end =
5130 : : * number of actions templates * number of queues * size of DR rule actions container.
5131 : : */
5132 : : tbl_mem_size = sizeof(*tbl);
5133 : 0 : tbl_mem_size += nb_action_templates * priv->nb_queue * sizeof(tbl->rule_acts[0]);
5134 : : /* Allocate the table memory. */
5135 : 0 : tbl = mlx5_malloc(MLX5_MEM_ZERO, tbl_mem_size, RTE_CACHE_LINE_SIZE, rte_socket_id());
5136 [ # # ]: 0 : if (!tbl)
5137 : 0 : goto error;
5138 : 0 : tbl->cfg = *table_cfg;
5139 : : /* Allocate flow indexed pool. */
5140 : 0 : tbl->flow = mlx5_ipool_create(&cfg);
5141 [ # # ]: 0 : if (!tbl->flow)
5142 : 0 : goto error;
5143 : : /* Allocate table of auxiliary flow rule structs. */
5144 : 0 : tbl->flow_aux = mlx5_malloc(MLX5_MEM_ZERO, sizeof(struct rte_flow_hw_aux) * nb_flows,
5145 : 0 : RTE_CACHE_LINE_SIZE, rte_dev_numa_node(dev->device));
5146 [ # # ]: 0 : if (!tbl->flow_aux)
5147 : 0 : goto error;
5148 : : /* Register the flow group. */
5149 : 0 : ge = mlx5_hlist_register(priv->sh->groups, attr->flow_attr.group, &ctx);
5150 [ # # ]: 0 : if (!ge)
5151 : 0 : goto error;
5152 : : grp = container_of(ge, struct mlx5_flow_group, entry);
5153 : : /* Verify unified fdb sub domains consistency */
5154 : 0 : table_type = get_mlx5dr_table_type(&flow_attr, specialize, unified_fdb);
5155 [ # # ]: 0 : if (table_type != grp->type) {
5156 : 0 : DRV_LOG(ERR, "Table type (%u) does not match group id (%u) type (%u)",
5157 : : table_type, grp->group_id, grp->type);
5158 : 0 : rte_errno = EINVAL;
5159 : 0 : goto error;
5160 : : }
5161 : 0 : tbl->grp = grp;
5162 : : /* Prepare matcher information. */
5163 : 0 : matcher_attr.resizable = !!rte_flow_template_table_resizable
5164 : 0 : (dev->data->port_id, &table_cfg->attr);
5165 : 0 : matcher_attr.optimize_flow_src = MLX5DR_MATCHER_FLOW_SRC_ANY;
5166 : 0 : matcher_attr.priority = attr->flow_attr.priority;
5167 : 0 : matcher_attr.optimize_using_rule_idx = true;
5168 : 0 : matcher_attr.mode = MLX5DR_MATCHER_RESOURCE_MODE_RULE;
5169 [ # # ]: 0 : matcher_attr.insert_mode = flow_hw_matcher_insert_mode_get(attr->insertion_type);
5170 [ # # ]: 0 : if (matcher_attr.insert_mode == MLX5DR_MATCHER_INSERT_BY_INDEX) {
5171 [ # # ]: 0 : if (attr->insertion_type == RTE_FLOW_TABLE_INSERTION_TYPE_INDEX_WITH_PATTERN) {
5172 : 0 : matcher_attr.isolated = true;
5173 : 0 : matcher_attr.match_mode = MLX5DR_MATCHER_MATCH_MODE_DEFAULT;
5174 : : } else {
5175 : 0 : matcher_attr.isolated = false;
5176 : 0 : matcher_attr.match_mode = MLX5DR_MATCHER_MATCH_MODE_ALWAYS_HIT;
5177 : : }
5178 : : }
5179 [ # # ]: 0 : if (attr->hash_func == RTE_FLOW_TABLE_HASH_FUNC_CRC16) {
5180 : 0 : DRV_LOG(ERR, "16-bit checksum hash type is not supported");
5181 : 0 : rte_errno = ENOTSUP;
5182 : 0 : goto it_error;
5183 : : }
5184 [ # # ]: 0 : matcher_attr.distribute_mode = flow_hw_matcher_distribute_mode_get(attr->hash_func);
5185 : 0 : matcher_attr.rule.num_log = rte_log2_u32(nb_flows);
5186 : : /* Parse hints information. */
5187 [ # # ]: 0 : if (attr->specialize) {
5188 : : uint32_t val = RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_WIRE_ORIG |
5189 : : RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_VPORT_ORIG;
5190 : :
5191 [ # # ]: 0 : if ((attr->specialize & val) == val) {
5192 : 0 : DRV_LOG(ERR, "Invalid hint value %x",
5193 : : attr->specialize);
5194 : 0 : rte_errno = EINVAL;
5195 : 0 : goto it_error;
5196 : : }
5197 [ # # ]: 0 : if (attr->specialize &
5198 : : RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_WIRE_ORIG) {
5199 : 0 : matcher_attr.optimize_flow_src =
5200 : : MLX5DR_MATCHER_FLOW_SRC_WIRE;
5201 [ # # ]: 0 : } else if (attr->specialize &
5202 : : RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_VPORT_ORIG) {
5203 : 0 : matcher_attr.optimize_flow_src =
5204 : : MLX5DR_MATCHER_FLOW_SRC_VPORT;
5205 : : }
5206 : : }
5207 : : /* Build the item template. */
5208 [ # # ]: 0 : for (i = 0; i < nb_item_templates; i++) {
5209 : : uint32_t ret;
5210 : :
5211 [ # # # # ]: 0 : if ((flow_attr.ingress && !item_templates[i]->attr.ingress) ||
5212 [ # # # # ]: 0 : (flow_attr.egress && !item_templates[i]->attr.egress) ||
5213 [ # # # # ]: 0 : (flow_attr.transfer && !item_templates[i]->attr.transfer)) {
5214 : 0 : DRV_LOG(ERR, "pattern template and template table attribute mismatch");
5215 : 0 : rte_errno = EINVAL;
5216 : 0 : goto it_error;
5217 : : }
5218 [ # # ]: 0 : if (item_templates[i]->item_flags & MLX5_FLOW_ITEM_COMPARE)
5219 : 0 : matcher_attr.mode = MLX5DR_MATCHER_RESOURCE_MODE_HTABLE;
5220 : 0 : ret = rte_atomic_fetch_add_explicit(&item_templates[i]->refcnt, 1,
5221 : : rte_memory_order_relaxed) + 1;
5222 [ # # ]: 0 : if (ret <= 1) {
5223 : 0 : rte_errno = EINVAL;
5224 : 0 : goto it_error;
5225 : : }
5226 : 0 : mt[i] = item_templates[i]->mt;
5227 : 0 : tbl->its[i] = item_templates[i];
5228 : : }
5229 : 0 : tbl->nb_item_templates = nb_item_templates;
5230 : : /* Build the action template. */
5231 : 0 : err = mlx5_hw_build_template_table(dev, nb_action_templates,
5232 : : action_templates, at, tbl, &sub_error);
5233 [ # # ]: 0 : if (err) {
5234 : : i = nb_item_templates;
5235 : 0 : goto it_error;
5236 : : }
5237 : 0 : tbl->matcher_info[0].matcher = mlx5dr_matcher_create
5238 : 0 : (tbl->grp->tbl, mt, nb_item_templates, at, nb_action_templates, &matcher_attr);
5239 [ # # ]: 0 : if (!tbl->matcher_info[0].matcher)
5240 : 0 : goto at_error;
5241 : 0 : tbl->matcher_attr = matcher_attr;
5242 : 0 : tbl->type = table_type;
5243 [ # # ]: 0 : if (matcher_attr.isolated) {
5244 : 0 : jump_attr.matcher = tbl->matcher_info[0].matcher;
5245 : 0 : tbl->matcher_info[0].jump = mlx5dr_action_create_jump_to_matcher(priv->dr_ctx,
5246 : 0 : &jump_attr, mlx5_hw_act_flag[!!attr->flow_attr.group][tbl->type]);
5247 [ # # ]: 0 : if (!tbl->matcher_info[0].jump)
5248 : 0 : goto jtm_error;
5249 : : }
5250 : : /*
5251 : : * Only the matcher supports update and needs more than 1 WQE, an additional
5252 : : * index is needed. Or else the flow index can be reused.
5253 : : */
5254 [ # # # # ]: 0 : rpool_needed = mlx5dr_matcher_is_updatable(tbl->matcher_info[0].matcher) &&
5255 : 0 : mlx5dr_matcher_is_dependent(tbl->matcher_info[0].matcher);
5256 [ # # ]: 0 : if (rpool_needed) {
5257 : : /* Allocate rule indexed pool. */
5258 : 0 : cfg.size = 0;
5259 : 0 : cfg.type = "mlx5_hw_table_rule";
5260 : 0 : cfg.max_idx += priv->hw_q[0].size;
5261 : 0 : tbl->resource = mlx5_ipool_create(&cfg);
5262 [ # # ]: 0 : if (!tbl->resource)
5263 : 0 : goto res_error;
5264 : : }
5265 [ # # ]: 0 : if (port_started)
5266 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->flow_hw_tbl, tbl, next);
5267 : : else
5268 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->flow_hw_tbl_ongo, tbl, next);
5269 : : rte_rwlock_init(&tbl->matcher_replace_rwlk);
5270 : 0 : return tbl;
5271 : : res_error:
5272 [ # # ]: 0 : if (tbl->matcher_info[0].jump)
5273 : 0 : mlx5dr_action_destroy(tbl->matcher_info[0].jump);
5274 : 0 : jtm_error:
5275 [ # # ]: 0 : if (tbl->matcher_info[0].matcher)
5276 : 0 : (void)mlx5dr_matcher_destroy(tbl->matcher_info[0].matcher);
5277 : 0 : at_error:
5278 [ # # ]: 0 : for (i = 0; i < nb_action_templates; i++) {
5279 : 0 : __flow_hw_action_template_destroy(dev, &tbl->ats[i].acts);
5280 : 0 : rte_atomic_fetch_sub_explicit(&action_templates[i]->refcnt,
5281 : : 1, rte_memory_order_relaxed);
5282 : : }
5283 : : i = nb_item_templates;
5284 : : it_error:
5285 [ # # ]: 0 : while (i--)
5286 : 0 : rte_atomic_fetch_sub_explicit(&item_templates[i]->refcnt,
5287 : : 1, rte_memory_order_relaxed);
5288 : 0 : error:
5289 : 0 : err = rte_errno;
5290 [ # # ]: 0 : if (tbl) {
5291 [ # # ]: 0 : if (tbl->grp)
5292 : 0 : mlx5_hlist_unregister(priv->sh->groups,
5293 : : &tbl->grp->entry);
5294 [ # # ]: 0 : if (tbl->flow_aux)
5295 : 0 : mlx5_free(tbl->flow_aux);
5296 [ # # ]: 0 : if (tbl->flow)
5297 : 0 : mlx5_ipool_destroy(tbl->flow);
5298 : 0 : mlx5_free(tbl);
5299 : : }
5300 [ # # ]: 0 : if (error != NULL) {
5301 [ # # ]: 0 : if (sub_error.type == RTE_FLOW_ERROR_TYPE_NONE)
5302 : 0 : rte_flow_error_set(error, err, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5303 : : "Failed to create template table");
5304 : : else
5305 : : rte_memcpy(error, &sub_error, sizeof(sub_error));
5306 : : }
5307 : : return NULL;
5308 : : }
5309 : :
5310 : : /**
5311 : : * Update flow template table.
5312 : : *
5313 : : * @param[in] dev
5314 : : * Pointer to the rte_eth_dev structure.
5315 : : * @param[out] error
5316 : : * Pointer to error structure.
5317 : : *
5318 : : * @return
5319 : : * 0 on success, negative value otherwise and rte_errno is set.
5320 : : */
5321 : : int
5322 : 0 : flow_hw_table_update(struct rte_eth_dev *dev,
5323 : : struct rte_flow_error *error)
5324 : : {
5325 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
5326 : : struct rte_flow_template_table *tbl;
5327 : :
5328 [ # # ]: 0 : while ((tbl = LIST_FIRST(&priv->flow_hw_tbl_ongo)) != NULL) {
5329 [ # # ]: 0 : if (flow_hw_translate_all_actions_templates(dev, tbl, error))
5330 : : return -1;
5331 [ # # ]: 0 : LIST_REMOVE(tbl, next);
5332 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->flow_hw_tbl, tbl, next);
5333 : : }
5334 : : return 0;
5335 : : }
5336 : :
5337 : : static inline int
5338 : 0 : __translate_group(struct rte_eth_dev *dev,
5339 : : const struct rte_flow_attr *flow_attr,
5340 : : bool external,
5341 : : uint32_t group,
5342 : : uint32_t *table_group,
5343 : : struct rte_flow_error *error)
5344 : : {
5345 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
5346 : 0 : struct mlx5_sh_config *config = &priv->sh->config;
5347 : :
5348 [ # # ]: 0 : if (config->dv_esw_en &&
5349 [ # # # # ]: 0 : priv->fdb_def_rule &&
5350 [ # # ]: 0 : external &&
5351 : : flow_attr->transfer) {
5352 [ # # ]: 0 : if (group > MLX5_HW_MAX_TRANSFER_GROUP)
5353 : 0 : return rte_flow_error_set(error, EINVAL,
5354 : : RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5355 : : NULL,
5356 : : "group index not supported");
5357 : 0 : *table_group = group + 1;
5358 [ # # ]: 0 : } else if (config->dv_esw_en &&
5359 [ # # # # : 0 : (config->repr_matching || config->dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS) &&
# # ]
5360 [ # # ]: 0 : external &&
5361 : : flow_attr->egress) {
5362 : : /*
5363 : : * On E-Switch setups, default egress flow rules are inserted to allow
5364 : : * representor matching and/or preserving metadata across steering domains.
5365 : : * These flow rules are inserted in group 0 and this group is reserved by PMD
5366 : : * for these purposes.
5367 : : *
5368 : : * As a result, if representor matching or extended metadata mode is enabled,
5369 : : * group provided by the user must be incremented to avoid inserting flow rules
5370 : : * in group 0.
5371 : : */
5372 [ # # ]: 0 : if (group > MLX5_HW_MAX_EGRESS_GROUP)
5373 : 0 : return rte_flow_error_set(error, EINVAL,
5374 : : RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5375 : : NULL,
5376 : : "group index not supported");
5377 : 0 : *table_group = group + 1;
5378 : : } else {
5379 : 0 : *table_group = group;
5380 : : }
5381 : : return 0;
5382 : : }
5383 : :
5384 : : /**
5385 : : * Translates group index specified by the user in @p attr to internal
5386 : : * group index.
5387 : : *
5388 : : * Translation is done by incrementing group index, so group n becomes n + 1.
5389 : : *
5390 : : * @param[in] dev
5391 : : * Pointer to Ethernet device.
5392 : : * @param[in] cfg
5393 : : * Pointer to the template table configuration.
5394 : : * @param[in] group
5395 : : * Currently used group index (table group or jump destination).
5396 : : * @param[out] table_group
5397 : : * Pointer to output group index.
5398 : : * @param[out] error
5399 : : * Pointer to error structure.
5400 : : *
5401 : : * @return
5402 : : * 0 on success. Otherwise, returns negative error code, rte_errno is set
5403 : : * and error structure is filled.
5404 : : */
5405 : : static int
5406 : : flow_hw_translate_group(struct rte_eth_dev *dev,
5407 : : const struct mlx5_flow_template_table_cfg *cfg,
5408 : : uint32_t group,
5409 : : uint32_t *table_group,
5410 : : struct rte_flow_error *error)
5411 : : {
5412 : 0 : const struct rte_flow_attr *flow_attr = &cfg->attr.flow_attr;
5413 : :
5414 : 0 : return __translate_group(dev, flow_attr, cfg->external, group, table_group, error);
5415 : : }
5416 : :
5417 : : /**
5418 : : * Create flow table.
5419 : : *
5420 : : * This function is a wrapper over @ref flow_hw_table_create(), which translates parameters
5421 : : * provided by user to proper internal values.
5422 : : *
5423 : : * @param[in] dev
5424 : : * Pointer to Ethernet device.
5425 : : * @param[in] attr
5426 : : * Pointer to the table attributes.
5427 : : * @param[in] item_templates
5428 : : * Item template array to be binded to the table.
5429 : : * @param[in] nb_item_templates
5430 : : * Number of item templates.
5431 : : * @param[in] action_templates
5432 : : * Action template array to be binded to the table.
5433 : : * @param[in] nb_action_templates
5434 : : * Number of action templates.
5435 : : * @param[out] error
5436 : : * Pointer to error structure.
5437 : : *
5438 : : * @return
5439 : : * Table on success, Otherwise, returns negative error code, rte_errno is set
5440 : : * and error structure is filled.
5441 : : */
5442 : : static struct rte_flow_template_table *
5443 : 0 : flow_hw_template_table_create(struct rte_eth_dev *dev,
5444 : : const struct rte_flow_template_table_attr *attr,
5445 : : struct rte_flow_pattern_template *item_templates[],
5446 : : uint8_t nb_item_templates,
5447 : : struct rte_flow_actions_template *action_templates[],
5448 : : uint8_t nb_action_templates,
5449 : : struct rte_flow_error *error)
5450 : : {
5451 : 0 : struct mlx5_flow_template_table_cfg cfg = {
5452 : : .attr = *attr,
5453 : : .external = true,
5454 : : };
5455 : 0 : uint32_t group = attr->flow_attr.group;
5456 : :
5457 [ # # ]: 0 : if (flow_hw_translate_group(dev, &cfg, group, &cfg.attr.flow_attr.group, error))
5458 : : return NULL;
5459 [ # # # # ]: 0 : if (!cfg.attr.flow_attr.group &&
5460 : 0 : rte_flow_template_table_resizable(dev->data->port_id, attr)) {
5461 : 0 : rte_flow_error_set(error, EINVAL,
5462 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5463 : : "table cannot be resized: invalid group");
5464 : 0 : return NULL;
5465 : : }
5466 : 0 : return flow_hw_table_create(dev, &cfg, item_templates, nb_item_templates,
5467 : : action_templates, nb_action_templates, error);
5468 : : }
5469 : :
5470 : : static void
5471 : 0 : mlx5_destroy_multi_pattern_segment(struct mlx5_multi_pattern_segment *segment)
5472 : : {
5473 : : int i;
5474 : :
5475 [ # # ]: 0 : if (segment->mhdr_action)
5476 : 0 : mlx5dr_action_destroy(segment->mhdr_action);
5477 [ # # ]: 0 : for (i = 0; i < MLX5_MULTIPATTERN_ENCAP_NUM; i++) {
5478 [ # # ]: 0 : if (segment->reformat_action[i])
5479 : 0 : mlx5dr_action_destroy(segment->reformat_action[i]);
5480 : : }
5481 : 0 : segment->capacity = 0;
5482 : 0 : }
5483 : :
5484 : : static void
5485 : : flow_hw_destroy_table_multi_pattern_ctx(struct rte_flow_template_table *table)
5486 : : {
5487 : : int sx;
5488 : :
5489 [ # # ]: 0 : for (sx = 0; sx < MLX5_MAX_TABLE_RESIZE_NUM; sx++)
5490 : 0 : mlx5_destroy_multi_pattern_segment(table->mpctx.segments + sx);
5491 : : }
5492 : : /**
5493 : : * Destroy flow table.
5494 : : *
5495 : : * @param[in] dev
5496 : : * Pointer to the rte_eth_dev structure.
5497 : : * @param[in] table
5498 : : * Pointer to the table to be destroyed.
5499 : : * @param[out] error
5500 : : * Pointer to error structure.
5501 : : *
5502 : : * @return
5503 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
5504 : : */
5505 : : static int
5506 : 0 : flow_hw_table_destroy(struct rte_eth_dev *dev,
5507 : : struct rte_flow_template_table *table,
5508 : : struct rte_flow_error *error)
5509 : : {
5510 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
5511 : : int i;
5512 : 0 : uint32_t fidx = 1;
5513 : 0 : uint32_t ridx = 1;
5514 : :
5515 : : /* Build ipool allocated object bitmap. */
5516 [ # # ]: 0 : if (table->resource)
5517 : 0 : mlx5_ipool_flush_cache(table->resource);
5518 : 0 : mlx5_ipool_flush_cache(table->flow);
5519 : : /* Check if ipool has allocated objects. */
5520 [ # # # # ]: 0 : if (table->refcnt ||
5521 : 0 : mlx5_ipool_get_next(table->flow, &fidx) ||
5522 [ # # # # ]: 0 : (table->resource && mlx5_ipool_get_next(table->resource, &ridx))) {
5523 : 0 : DRV_LOG(WARNING, "Table %p is still in use.", (void *)table);
5524 : 0 : return rte_flow_error_set(error, EBUSY,
5525 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5526 : : NULL,
5527 : : "table is in use");
5528 : : }
5529 [ # # ]: 0 : LIST_REMOVE(table, next);
5530 [ # # ]: 0 : for (i = 0; i < table->nb_item_templates; i++)
5531 : 0 : rte_atomic_fetch_sub_explicit(&table->its[i]->refcnt,
5532 : : 1, rte_memory_order_relaxed);
5533 [ # # ]: 0 : for (i = 0; i < table->nb_action_templates; i++) {
5534 : 0 : __flow_hw_action_template_destroy(dev, &table->ats[i].acts);
5535 : 0 : rte_atomic_fetch_sub_explicit(&table->ats[i].action_template->refcnt,
5536 : : 1, rte_memory_order_relaxed);
5537 : : }
5538 : : flow_hw_destroy_table_multi_pattern_ctx(table);
5539 [ # # ]: 0 : if (table->matcher_info[0].jump)
5540 : 0 : mlx5dr_action_destroy(table->matcher_info[0].jump);
5541 [ # # ]: 0 : if (table->matcher_info[0].matcher)
5542 : 0 : mlx5dr_matcher_destroy(table->matcher_info[0].matcher);
5543 [ # # ]: 0 : if (table->matcher_info[1].jump)
5544 : 0 : mlx5dr_action_destroy(table->matcher_info[1].jump);
5545 [ # # ]: 0 : if (table->matcher_info[1].matcher)
5546 : 0 : mlx5dr_matcher_destroy(table->matcher_info[1].matcher);
5547 : 0 : mlx5_hlist_unregister(priv->sh->groups, &table->grp->entry);
5548 [ # # ]: 0 : if (table->resource)
5549 : 0 : mlx5_ipool_destroy(table->resource);
5550 : 0 : mlx5_free(table->flow_aux);
5551 : 0 : mlx5_ipool_destroy(table->flow);
5552 : 0 : mlx5_free(table);
5553 : 0 : return 0;
5554 : : }
5555 : :
5556 : : /**
5557 : : * Parse group's miss actions.
5558 : : *
5559 : : * @param[in] dev
5560 : : * Pointer to the rte_eth_dev structure.
5561 : : * @param[in] cfg
5562 : : * Pointer to the table_cfg structure.
5563 : : * @param[in] actions
5564 : : * Array of actions to perform on group miss. Supported types:
5565 : : * RTE_FLOW_ACTION_TYPE_JUMP, RTE_FLOW_ACTION_TYPE_VOID, RTE_FLOW_ACTION_TYPE_END.
5566 : : * @param[out] dst_group_id
5567 : : * Pointer to destination group id output. will be set to 0 if actions is END,
5568 : : * otherwise will be set to destination group id.
5569 : : * @param[out] error
5570 : : * Pointer to error structure.
5571 : : *
5572 : : * @return
5573 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
5574 : : */
5575 : :
5576 : : static int
5577 : 0 : flow_hw_group_parse_miss_actions(struct rte_eth_dev *dev,
5578 : : struct mlx5_flow_template_table_cfg *cfg,
5579 : : const struct rte_flow_action actions[],
5580 : : uint32_t *dst_group_id,
5581 : : struct rte_flow_error *error)
5582 : : {
5583 : : const struct rte_flow_action_jump *jump_conf;
5584 : 0 : uint32_t temp = 0;
5585 : : uint32_t i;
5586 : :
5587 [ # # ]: 0 : for (i = 0; actions[i].type != RTE_FLOW_ACTION_TYPE_END; i++) {
5588 [ # # # ]: 0 : switch (actions[i].type) {
5589 : 0 : case RTE_FLOW_ACTION_TYPE_VOID:
5590 : 0 : continue;
5591 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP:
5592 [ # # ]: 0 : if (temp)
5593 : 0 : return rte_flow_error_set(error, ENOTSUP,
5594 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, actions,
5595 : : "Miss actions can contain only a single JUMP");
5596 : :
5597 : 0 : jump_conf = (const struct rte_flow_action_jump *)actions[i].conf;
5598 [ # # ]: 0 : if (!jump_conf)
5599 : 0 : return rte_flow_error_set(error, EINVAL,
5600 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5601 : : jump_conf, "Jump conf must not be NULL");
5602 : :
5603 [ # # ]: 0 : if (flow_hw_translate_group(dev, cfg, jump_conf->group, &temp, error))
5604 : 0 : return -rte_errno;
5605 : :
5606 [ # # ]: 0 : if (!temp)
5607 : 0 : return rte_flow_error_set(error, EINVAL,
5608 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5609 : : "Failed to set group miss actions - Invalid target group");
5610 : : break;
5611 : 0 : default:
5612 : 0 : return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
5613 : : &actions[i], "Unsupported default miss action type");
5614 : : }
5615 : : }
5616 : :
5617 : 0 : *dst_group_id = temp;
5618 : 0 : return 0;
5619 : : }
5620 : :
5621 : : /**
5622 : : * Set group's miss group.
5623 : : *
5624 : : * @param[in] dev
5625 : : * Pointer to the rte_eth_dev structure.
5626 : : * @param[in] cfg
5627 : : * Pointer to the table_cfg structure.
5628 : : * @param[in] src_grp
5629 : : * Pointer to source group structure.
5630 : : * if NULL, a new group will be created based on group id from cfg->attr.flow_attr.group.
5631 : : * @param[in] dst_grp
5632 : : * Pointer to destination group structure.
5633 : : * @param[out] error
5634 : : * Pointer to error structure.
5635 : : *
5636 : : * @return
5637 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
5638 : : */
5639 : :
5640 : : static int
5641 : 0 : flow_hw_group_set_miss_group(struct rte_eth_dev *dev,
5642 : : struct mlx5_flow_template_table_cfg *cfg,
5643 : : struct mlx5_flow_group *src_grp,
5644 : : struct mlx5_flow_group *dst_grp,
5645 : : struct rte_flow_error *error)
5646 : : {
5647 : 0 : struct rte_flow_error sub_error = {
5648 : : .type = RTE_FLOW_ERROR_TYPE_NONE,
5649 : : .cause = NULL,
5650 : : .message = NULL,
5651 : : };
5652 : 0 : struct mlx5_flow_cb_ctx ctx = {
5653 : : .dev = dev,
5654 : : .error = &sub_error,
5655 : 0 : .data = &cfg->attr.flow_attr,
5656 : 0 : .data2 = &cfg->attr.specialize,
5657 : : };
5658 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
5659 : : struct mlx5_list_entry *ge;
5660 : : bool ref = false;
5661 : : int ret;
5662 : :
5663 [ # # ]: 0 : if (!dst_grp)
5664 : : return -EINVAL;
5665 : :
5666 : : /* If group doesn't exist - needs to be created. */
5667 [ # # ]: 0 : if (!src_grp) {
5668 : 0 : ge = mlx5_hlist_register(priv->sh->groups, cfg->attr.flow_attr.group, &ctx);
5669 [ # # ]: 0 : if (!ge)
5670 : 0 : return -rte_errno;
5671 : :
5672 : : src_grp = container_of(ge, struct mlx5_flow_group, entry);
5673 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->flow_hw_grp, src_grp, next);
5674 : : ref = true;
5675 [ # # ]: 0 : } else if (!src_grp->miss_group) {
5676 : : /* If group exists, but has no miss actions - need to increase ref_cnt. */
5677 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->flow_hw_grp, src_grp, next);
5678 : 0 : src_grp->entry.ref_cnt++;
5679 : : ref = true;
5680 : : }
5681 : :
5682 : 0 : ret = mlx5dr_table_set_default_miss(src_grp->tbl, dst_grp->tbl);
5683 [ # # ]: 0 : if (ret)
5684 : 0 : goto mlx5dr_error;
5685 : :
5686 : : /* If group existed and had old miss actions - ref_cnt is already correct.
5687 : : * However, need to reduce ref counter for old miss group.
5688 : : */
5689 [ # # ]: 0 : if (src_grp->miss_group)
5690 : 0 : mlx5_hlist_unregister(priv->sh->groups, &src_grp->miss_group->entry);
5691 : :
5692 : 0 : src_grp->miss_group = dst_grp;
5693 : 0 : return 0;
5694 : :
5695 : : mlx5dr_error:
5696 : : /* Reduce src_grp ref_cnt back & remove from grp list in case of mlx5dr error */
5697 [ # # ]: 0 : if (ref) {
5698 : 0 : mlx5_hlist_unregister(priv->sh->groups, &src_grp->entry);
5699 [ # # ]: 0 : LIST_REMOVE(src_grp, next);
5700 : : }
5701 : :
5702 : 0 : return rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5703 : : "Failed to set group miss actions");
5704 : : }
5705 : :
5706 : : /**
5707 : : * Unset group's miss group.
5708 : : *
5709 : : * @param[in] dev
5710 : : * Pointer to the rte_eth_dev structure.
5711 : : * @param[in] grp
5712 : : * Pointer to group structure.
5713 : : * @param[out] error
5714 : : * Pointer to error structure.
5715 : : *
5716 : : * @return
5717 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
5718 : : */
5719 : :
5720 : : static int
5721 : 0 : flow_hw_group_unset_miss_group(struct rte_eth_dev *dev,
5722 : : struct mlx5_flow_group *grp,
5723 : : struct rte_flow_error *error)
5724 : : {
5725 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
5726 : : int ret;
5727 : :
5728 : : /* If group doesn't exist - no need to change anything. */
5729 [ # # ]: 0 : if (!grp)
5730 : : return 0;
5731 : :
5732 : : /* If group exists, but miss actions is already default behavior -
5733 : : * no need to change anything.
5734 : : */
5735 [ # # ]: 0 : if (!grp->miss_group)
5736 : : return 0;
5737 : :
5738 : 0 : ret = mlx5dr_table_set_default_miss(grp->tbl, NULL);
5739 [ # # ]: 0 : if (ret)
5740 : 0 : return rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5741 : : "Failed to unset group miss actions");
5742 : :
5743 : 0 : mlx5_hlist_unregister(priv->sh->groups, &grp->miss_group->entry);
5744 : 0 : grp->miss_group = NULL;
5745 : :
5746 [ # # ]: 0 : LIST_REMOVE(grp, next);
5747 : 0 : mlx5_hlist_unregister(priv->sh->groups, &grp->entry);
5748 : :
5749 : 0 : return 0;
5750 : : }
5751 : :
5752 : : /**
5753 : : * Set group miss actions.
5754 : : *
5755 : : * @param[in] dev
5756 : : * Pointer to the rte_eth_dev structure.
5757 : : * @param[in] group_id
5758 : : * Group id.
5759 : : * @param[in] attr
5760 : : * Pointer to group attributes structure.
5761 : : * @param[in] actions
5762 : : * Array of actions to perform on group miss. Supported types:
5763 : : * RTE_FLOW_ACTION_TYPE_JUMP, RTE_FLOW_ACTION_TYPE_VOID, RTE_FLOW_ACTION_TYPE_END.
5764 : : * @param[out] error
5765 : : * Pointer to error structure.
5766 : : *
5767 : : * @return
5768 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
5769 : : */
5770 : :
5771 : : static int
5772 : 0 : flow_hw_group_set_miss_actions(struct rte_eth_dev *dev,
5773 : : uint32_t group_id,
5774 : : const struct rte_flow_group_attr *attr,
5775 : : const struct rte_flow_action actions[],
5776 : : struct rte_flow_error *error)
5777 : : {
5778 : 0 : struct rte_flow_error sub_error = {
5779 : : .type = RTE_FLOW_ERROR_TYPE_NONE,
5780 : : .cause = NULL,
5781 : : .message = NULL,
5782 : : };
5783 : 0 : struct mlx5_flow_template_table_cfg cfg = {
5784 : : .external = true,
5785 : : .attr = {
5786 : : .flow_attr = {
5787 : : .group = group_id,
5788 : 0 : .ingress = attr->ingress,
5789 : 0 : .egress = attr->egress,
5790 : 0 : .transfer = attr->transfer,
5791 : : },
5792 : : },
5793 : : };
5794 : 0 : struct mlx5_flow_cb_ctx ctx = {
5795 : : .dev = dev,
5796 : : .error = &sub_error,
5797 : : .data = &cfg.attr.flow_attr,
5798 : : .data2 = &cfg.attr.specialize,
5799 : : };
5800 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
5801 : : struct mlx5_flow_group *src_grp = NULL;
5802 : : struct mlx5_flow_group *dst_grp = NULL;
5803 : : struct mlx5_list_entry *ge;
5804 : 0 : uint32_t dst_group_id = 0;
5805 : : int ret;
5806 : :
5807 [ # # ]: 0 : if (flow_hw_translate_group(dev, &cfg, group_id, &group_id, error))
5808 : 0 : return -rte_errno;
5809 : :
5810 [ # # ]: 0 : if (!group_id)
5811 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5812 : : NULL, "Failed to set group miss actions - invalid group id");
5813 : :
5814 : 0 : ret = flow_hw_group_parse_miss_actions(dev, &cfg, actions, &dst_group_id, error);
5815 [ # # ]: 0 : if (ret)
5816 : 0 : return -rte_errno;
5817 : :
5818 [ # # ]: 0 : if (dst_group_id == group_id) {
5819 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5820 : : NULL, "Failed to set group miss actions - target group id must differ from group_id");
5821 : : }
5822 : :
5823 : 0 : cfg.attr.flow_attr.group = group_id;
5824 : 0 : ge = mlx5_hlist_lookup(priv->sh->groups, group_id, &ctx);
5825 [ # # ]: 0 : if (ge)
5826 : : src_grp = container_of(ge, struct mlx5_flow_group, entry);
5827 : :
5828 [ # # ]: 0 : if (dst_group_id) {
5829 : : /* Increase ref_cnt for new miss group. */
5830 : 0 : cfg.attr.flow_attr.group = dst_group_id;
5831 : 0 : ge = mlx5_hlist_register(priv->sh->groups, dst_group_id, &ctx);
5832 [ # # ]: 0 : if (!ge)
5833 : 0 : return -rte_errno;
5834 : :
5835 : : dst_grp = container_of(ge, struct mlx5_flow_group, entry);
5836 : :
5837 : 0 : cfg.attr.flow_attr.group = group_id;
5838 : 0 : ret = flow_hw_group_set_miss_group(dev, &cfg, src_grp, dst_grp, error);
5839 [ # # ]: 0 : if (ret)
5840 : 0 : goto error;
5841 : : } else {
5842 : 0 : return flow_hw_group_unset_miss_group(dev, src_grp, error);
5843 : : }
5844 : :
5845 : : return 0;
5846 : :
5847 : : error:
5848 : : if (dst_grp)
5849 : 0 : mlx5_hlist_unregister(priv->sh->groups, &dst_grp->entry);
5850 : 0 : return -rte_errno;
5851 : : }
5852 : :
5853 : : static bool
5854 : : flow_hw_modify_field_is_used(const struct rte_flow_action_modify_field *action,
5855 : : enum rte_flow_field_id field)
5856 : : {
5857 [ # # # # : 0 : return action->src.field == field || action->dst.field == field;
# # # # #
# # # # #
# # # # #
# # # # #
# # # # ]
5858 : : }
5859 : :
5860 : : static bool
5861 : : flow_hw_modify_field_is_geneve_opt(enum rte_flow_field_id field)
5862 : : {
5863 : : return field == RTE_FLOW_FIELD_GENEVE_OPT_TYPE ||
5864 : 0 : field == RTE_FLOW_FIELD_GENEVE_OPT_CLASS ||
5865 : : field == RTE_FLOW_FIELD_GENEVE_OPT_DATA;
5866 : : }
5867 : :
5868 : : static bool
5869 : 0 : flow_hw_modify_field_is_add_dst_valid(const struct rte_flow_action_modify_field *conf)
5870 : : {
5871 [ # # ]: 0 : if (conf->operation != RTE_FLOW_MODIFY_ADD)
5872 : : return true;
5873 [ # # ]: 0 : if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
5874 : : conf->src.field == RTE_FLOW_FIELD_VALUE)
5875 : : return true;
5876 [ # # ]: 0 : switch (conf->dst.field) {
5877 : : case RTE_FLOW_FIELD_IPV4_TTL:
5878 : : case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
5879 : : case RTE_FLOW_FIELD_TCP_SEQ_NUM:
5880 : : case RTE_FLOW_FIELD_TCP_ACK_NUM:
5881 : : case RTE_FLOW_FIELD_TAG:
5882 : : case RTE_FLOW_FIELD_META:
5883 : : case RTE_FLOW_FIELD_FLEX_ITEM:
5884 : : case RTE_FLOW_FIELD_TCP_DATA_OFFSET:
5885 : : case RTE_FLOW_FIELD_IPV4_IHL:
5886 : : case RTE_FLOW_FIELD_IPV4_TOTAL_LEN:
5887 : : case RTE_FLOW_FIELD_IPV6_PAYLOAD_LEN:
5888 : : return true;
5889 : : default:
5890 : : break;
5891 : : }
5892 : 0 : return false;
5893 : : }
5894 : :
5895 : : /**
5896 : : * Validate the level value for modify field action.
5897 : : *
5898 : : * @param[in] data
5899 : : * Pointer to the rte_flow_field_data structure either src or dst.
5900 : : * @param[in] inner_supported
5901 : : * Indicator whether inner should be supported.
5902 : : * @param[out] error
5903 : : * Pointer to error structure.
5904 : : *
5905 : : * @return
5906 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
5907 : : */
5908 : : static int
5909 : 0 : flow_hw_validate_modify_field_level(const struct rte_flow_field_data *data,
5910 : : bool inner_supported,
5911 : : struct rte_flow_error *error)
5912 : : {
5913 [ # # # # : 0 : switch ((int)data->field) {
# ]
5914 : : case RTE_FLOW_FIELD_START:
5915 : : case RTE_FLOW_FIELD_VLAN_TYPE:
5916 : : case RTE_FLOW_FIELD_RANDOM:
5917 : : case RTE_FLOW_FIELD_FLEX_ITEM:
5918 : : /*
5919 : : * Level shouldn't be valid since field isn't supported or
5920 : : * doesn't use 'level'.
5921 : : */
5922 : : break;
5923 : : case RTE_FLOW_FIELD_MARK:
5924 : : case RTE_FLOW_FIELD_META:
5925 : : case RTE_FLOW_FIELD_METER_COLOR:
5926 : : case RTE_FLOW_FIELD_HASH_RESULT:
5927 : : /* For meta data fields encapsulation level is don't-care. */
5928 : : break;
5929 : 0 : case RTE_FLOW_FIELD_TAG:
5930 : : case MLX5_RTE_FLOW_FIELD_META_REG:
5931 : : /*
5932 : : * The tag array for RTE_FLOW_FIELD_TAG type is provided using
5933 : : * 'tag_index' field. In old API, it was provided using 'level'
5934 : : * field and it is still supported for backwards compatibility.
5935 : : * Therefore, for meta tag field only, level is matter. It is
5936 : : * taken as tag index when 'tag_index' field isn't set, and
5937 : : * return error otherwise.
5938 : : */
5939 [ # # ]: 0 : if (data->level > 0) {
5940 [ # # ]: 0 : if (data->tag_index > 0)
5941 : 0 : return rte_flow_error_set(error, EINVAL,
5942 : : RTE_FLOW_ERROR_TYPE_ACTION,
5943 : : data,
5944 : : "tag array can be provided using 'level' or 'tag_index' fields, not both");
5945 : 0 : DRV_LOG(WARNING,
5946 : : "tag array provided in 'level' field instead of 'tag_index' field.");
5947 : : }
5948 : : break;
5949 : 0 : case RTE_FLOW_FIELD_MAC_DST:
5950 : : case RTE_FLOW_FIELD_MAC_SRC:
5951 : : case RTE_FLOW_FIELD_MAC_TYPE:
5952 : : case RTE_FLOW_FIELD_IPV4_IHL:
5953 : : case RTE_FLOW_FIELD_IPV4_TOTAL_LEN:
5954 : : case RTE_FLOW_FIELD_IPV4_DSCP:
5955 : : case RTE_FLOW_FIELD_IPV4_ECN:
5956 : : case RTE_FLOW_FIELD_IPV4_TTL:
5957 : : case RTE_FLOW_FIELD_IPV4_SRC:
5958 : : case RTE_FLOW_FIELD_IPV4_DST:
5959 : : case RTE_FLOW_FIELD_IPV6_TRAFFIC_CLASS:
5960 : : case RTE_FLOW_FIELD_IPV6_FLOW_LABEL:
5961 : : case RTE_FLOW_FIELD_IPV6_PAYLOAD_LEN:
5962 : : case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
5963 : : case RTE_FLOW_FIELD_IPV6_SRC:
5964 : : case RTE_FLOW_FIELD_IPV6_DST:
5965 : : case RTE_FLOW_FIELD_TCP_PORT_SRC:
5966 : : case RTE_FLOW_FIELD_TCP_PORT_DST:
5967 : : case RTE_FLOW_FIELD_TCP_FLAGS:
5968 : : case RTE_FLOW_FIELD_TCP_DATA_OFFSET:
5969 : : case RTE_FLOW_FIELD_UDP_PORT_SRC:
5970 : : case RTE_FLOW_FIELD_UDP_PORT_DST:
5971 [ # # ]: 0 : if (data->level > 2)
5972 : 0 : return rte_flow_error_set(error, ENOTSUP,
5973 : : RTE_FLOW_ERROR_TYPE_ACTION,
5974 : : data,
5975 : : "second inner header fields modification is not supported");
5976 [ # # ]: 0 : if (inner_supported)
5977 : : break;
5978 : : /* Fallthrough */
5979 : : case RTE_FLOW_FIELD_VLAN_ID:
5980 : : case RTE_FLOW_FIELD_IPV4_PROTO:
5981 : : case RTE_FLOW_FIELD_IPV6_PROTO:
5982 : : case RTE_FLOW_FIELD_IPV6_DSCP:
5983 : : case RTE_FLOW_FIELD_IPV6_ECN:
5984 : : case RTE_FLOW_FIELD_TCP_SEQ_NUM:
5985 : : case RTE_FLOW_FIELD_TCP_ACK_NUM:
5986 : : case RTE_FLOW_FIELD_ESP_PROTO:
5987 : : case RTE_FLOW_FIELD_ESP_SPI:
5988 : : case RTE_FLOW_FIELD_ESP_SEQ_NUM:
5989 : : case RTE_FLOW_FIELD_VXLAN_VNI:
5990 : : case RTE_FLOW_FIELD_VXLAN_LAST_RSVD:
5991 : : case RTE_FLOW_FIELD_GENEVE_VNI:
5992 : : case RTE_FLOW_FIELD_GENEVE_OPT_TYPE:
5993 : : case RTE_FLOW_FIELD_GENEVE_OPT_CLASS:
5994 : : case RTE_FLOW_FIELD_GENEVE_OPT_DATA:
5995 : : case RTE_FLOW_FIELD_GTP_TEID:
5996 : : case RTE_FLOW_FIELD_GTP_PSC_QFI:
5997 [ # # ]: 0 : if (data->level > 1)
5998 : 0 : return rte_flow_error_set(error, ENOTSUP,
5999 : : RTE_FLOW_ERROR_TYPE_ACTION,
6000 : : data,
6001 : : "inner header fields modification is not supported");
6002 : : break;
6003 : 0 : case RTE_FLOW_FIELD_MPLS:
6004 [ # # ]: 0 : if (data->level == 1)
6005 : 0 : return rte_flow_error_set(error, ENOTSUP,
6006 : : RTE_FLOW_ERROR_TYPE_ACTION,
6007 : : data,
6008 : : "outer MPLS header modification is not supported");
6009 [ # # ]: 0 : if (data->level > 2)
6010 : 0 : return rte_flow_error_set(error, ENOTSUP,
6011 : : RTE_FLOW_ERROR_TYPE_ACTION,
6012 : : data,
6013 : : "inner MPLS header modification is not supported");
6014 : : break;
6015 : 0 : case RTE_FLOW_FIELD_POINTER:
6016 : : case RTE_FLOW_FIELD_VALUE:
6017 : : default:
6018 : : MLX5_ASSERT(false);
6019 : : }
6020 : : return 0;
6021 : : }
6022 : :
6023 : : static int
6024 : 0 : flow_hw_validate_action_modify_field(struct rte_eth_dev *dev,
6025 : : const struct rte_flow_action *action,
6026 : : const struct rte_flow_action *mask,
6027 : : struct rte_flow_error *error)
6028 : : {
6029 : 0 : const struct rte_flow_action_modify_field *action_conf = action->conf;
6030 : 0 : const struct rte_flow_action_modify_field *mask_conf = mask->conf;
6031 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6032 : 0 : struct mlx5_hca_attr *attr = &priv->sh->cdev->config.hca_attr;
6033 : : int ret;
6034 : :
6035 [ # # ]: 0 : if (!mask_conf)
6036 : 0 : return rte_flow_error_set(error, EINVAL,
6037 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6038 : : "modify_field mask conf is missing");
6039 [ # # ]: 0 : if (action_conf->operation != mask_conf->operation)
6040 : 0 : return rte_flow_error_set(error, EINVAL,
6041 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6042 : : "modify_field operation mask and template are not equal");
6043 [ # # ]: 0 : if (action_conf->dst.field != mask_conf->dst.field)
6044 : 0 : return rte_flow_error_set(error, EINVAL,
6045 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6046 : : "destination field mask and template are not equal");
6047 : 0 : if (action_conf->dst.field == RTE_FLOW_FIELD_POINTER ||
6048 [ # # ]: 0 : action_conf->dst.field == RTE_FLOW_FIELD_VALUE ||
6049 : : action_conf->dst.field == RTE_FLOW_FIELD_HASH_RESULT)
6050 : 0 : return rte_flow_error_set(error, EINVAL,
6051 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6052 : : "immediate value, pointer and hash result cannot be used as destination");
6053 : 0 : ret = flow_hw_validate_modify_field_level(&action_conf->dst, false, error);
6054 [ # # ]: 0 : if (ret)
6055 : : return ret;
6056 [ # # # # ]: 0 : if (action_conf->dst.field != RTE_FLOW_FIELD_FLEX_ITEM &&
6057 : : !flow_hw_modify_field_is_geneve_opt(action_conf->dst.field)) {
6058 [ # # ]: 0 : if (action_conf->dst.tag_index &&
6059 : : !flow_modify_field_support_tag_array(action_conf->dst.field))
6060 : 0 : return rte_flow_error_set(error, EINVAL,
6061 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6062 : : "destination tag index is not supported");
6063 [ # # ]: 0 : if (action_conf->dst.class_id)
6064 : 0 : return rte_flow_error_set(error, EINVAL,
6065 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6066 : : "destination class id is not supported");
6067 : : }
6068 [ # # ]: 0 : if (mask_conf->dst.level != UINT8_MAX)
6069 : 0 : return rte_flow_error_set(error, EINVAL,
6070 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6071 : : "destination encapsulation level must be fully masked");
6072 [ # # ]: 0 : if (mask_conf->dst.offset != UINT32_MAX)
6073 : 0 : return rte_flow_error_set(error, EINVAL,
6074 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6075 : : "destination offset level must be fully masked");
6076 [ # # ]: 0 : if (action_conf->src.field != mask_conf->src.field)
6077 : 0 : return rte_flow_error_set(error, EINVAL,
6078 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6079 : : "destination field mask and template are not equal");
6080 [ # # ]: 0 : if (action_conf->src.field != RTE_FLOW_FIELD_POINTER &&
6081 : : action_conf->src.field != RTE_FLOW_FIELD_VALUE) {
6082 [ # # # # ]: 0 : if (action_conf->src.field != RTE_FLOW_FIELD_FLEX_ITEM &&
6083 : : !flow_hw_modify_field_is_geneve_opt(action_conf->src.field)) {
6084 [ # # ]: 0 : if (action_conf->src.tag_index &&
6085 : : !flow_modify_field_support_tag_array(action_conf->src.field))
6086 : 0 : return rte_flow_error_set(error, EINVAL,
6087 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6088 : : "source tag index is not supported");
6089 [ # # ]: 0 : if (action_conf->src.class_id)
6090 : 0 : return rte_flow_error_set(error, EINVAL,
6091 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6092 : : "source class id is not supported");
6093 : : }
6094 [ # # ]: 0 : if (mask_conf->src.level != UINT8_MAX)
6095 : 0 : return rte_flow_error_set(error, EINVAL,
6096 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6097 : : "source encapsulation level must be fully masked");
6098 [ # # ]: 0 : if (mask_conf->src.offset != UINT32_MAX)
6099 : 0 : return rte_flow_error_set(error, EINVAL,
6100 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6101 : : "source offset level must be fully masked");
6102 : 0 : ret = flow_hw_validate_modify_field_level(&action_conf->src, true, error);
6103 [ # # ]: 0 : if (ret)
6104 : : return ret;
6105 : : }
6106 [ # # ]: 0 : if ((action_conf->dst.field == RTE_FLOW_FIELD_TAG &&
6107 [ # # # # ]: 0 : action_conf->dst.tag_index >= MLX5_FLOW_HW_TAGS_MAX &&
6108 : 0 : action_conf->dst.tag_index != RTE_PMD_MLX5_LINEAR_HASH_TAG_INDEX) ||
6109 [ # # ]: 0 : (action_conf->src.field == RTE_FLOW_FIELD_TAG &&
6110 [ # # # # ]: 0 : action_conf->src.tag_index >= MLX5_FLOW_HW_TAGS_MAX &&
6111 : : action_conf->src.tag_index != RTE_PMD_MLX5_LINEAR_HASH_TAG_INDEX))
6112 : 0 : return rte_flow_error_set(error, EINVAL,
6113 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6114 : : "tag index is out of range");
6115 [ # # # # ]: 0 : if ((action_conf->dst.field == RTE_FLOW_FIELD_TAG &&
6116 [ # # # # ]: 0 : flow_hw_get_reg_id(dev, RTE_FLOW_ITEM_TYPE_TAG, action_conf->dst.tag_index) == REG_NON) ||
6117 [ # # ]: 0 : (action_conf->src.field == RTE_FLOW_FIELD_TAG &&
6118 [ # # ]: 0 : flow_hw_get_reg_id(dev, RTE_FLOW_ITEM_TYPE_TAG, action_conf->src.tag_index) == REG_NON))
6119 : 0 : return rte_flow_error_set(error, EINVAL,
6120 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6121 : : "tag index is out of range");
6122 [ # # ]: 0 : if (mask_conf->width != UINT32_MAX)
6123 : 0 : return rte_flow_error_set(error, EINVAL,
6124 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6125 : : "modify_field width field must be fully masked");
6126 [ # # ]: 0 : if (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_START))
6127 : 0 : return rte_flow_error_set(error, EINVAL,
6128 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6129 : : "modifying arbitrary place in a packet is not supported");
6130 [ # # ]: 0 : if (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_VLAN_TYPE))
6131 : 0 : return rte_flow_error_set(error, EINVAL,
6132 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6133 : : "modifying vlan_type is not supported");
6134 [ # # ]: 0 : if (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_RANDOM))
6135 : 0 : return rte_flow_error_set(error, EINVAL,
6136 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6137 : : "modifying random value is not supported");
6138 : : /**
6139 : : * Geneve VNI modification is supported only when Geneve header is
6140 : : * parsed natively. When GENEVE options are supported, they both Geneve
6141 : : * and options headers are parsed as a flex parser.
6142 : : */
6143 [ # # ]: 0 : if (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_GENEVE_VNI) &&
6144 [ # # ]: 0 : attr->geneve_tlv_opt)
6145 : 0 : return rte_flow_error_set(error, EINVAL,
6146 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6147 : : "modifying Geneve VNI is not supported when GENEVE opt is supported");
6148 [ # # # # ]: 0 : if (priv->tlv_options == NULL &&
6149 [ # # ]: 0 : (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_GENEVE_OPT_TYPE) ||
6150 [ # # ]: 0 : flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_GENEVE_OPT_CLASS) ||
6151 : : flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_GENEVE_OPT_DATA)))
6152 : 0 : return rte_flow_error_set(error, EINVAL,
6153 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6154 : : "modifying Geneve TLV option is supported only after parser configuration");
6155 : : /* Due to HW bug, tunnel MPLS header is read only. */
6156 [ # # ]: 0 : if (action_conf->dst.field == RTE_FLOW_FIELD_MPLS)
6157 : 0 : return rte_flow_error_set(error, EINVAL,
6158 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6159 : : "MPLS cannot be used as destination");
6160 : : /* ADD_FIELD is not supported for all the fields. */
6161 [ # # ]: 0 : if (!flow_hw_modify_field_is_add_dst_valid(action_conf))
6162 : 0 : return rte_flow_error_set(error, EINVAL,
6163 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6164 : : "invalid add_field destination");
6165 : : return 0;
6166 : : }
6167 : :
6168 : : static int
6169 : 0 : flow_hw_validate_action_port_representor(struct rte_eth_dev *dev __rte_unused,
6170 : : const struct rte_flow_actions_template_attr *attr,
6171 : : const struct rte_flow_action *action,
6172 : : const struct rte_flow_action *mask,
6173 : : struct rte_flow_error *error)
6174 : : {
6175 : : const struct rte_flow_action_ethdev *action_conf = NULL;
6176 : : const struct rte_flow_action_ethdev *mask_conf = NULL;
6177 : :
6178 : : /* If transfer is set, port has been validated as proxy port. */
6179 [ # # ]: 0 : if (!attr->transfer)
6180 : 0 : return rte_flow_error_set(error, EINVAL,
6181 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6182 : : "cannot use port_representor actions"
6183 : : " without an E-Switch");
6184 [ # # ]: 0 : if (!action || !mask)
6185 : 0 : return rte_flow_error_set(error, EINVAL,
6186 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6187 : : "actiona and mask configuration must be set");
6188 : 0 : action_conf = action->conf;
6189 : 0 : mask_conf = mask->conf;
6190 [ # # # # : 0 : if (!mask_conf || mask_conf->port_id != MLX5_REPRESENTED_PORT_ESW_MGR ||
# # ]
6191 [ # # ]: 0 : !action_conf || action_conf->port_id != MLX5_REPRESENTED_PORT_ESW_MGR)
6192 : 0 : return rte_flow_error_set(error, EINVAL,
6193 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6194 : : "only eswitch manager port 0xffff is"
6195 : : " supported");
6196 : : return 0;
6197 : : }
6198 : :
6199 : : static int
6200 : 0 : flow_hw_validate_target_port_id(struct rte_eth_dev *dev,
6201 : : uint16_t target_port_id)
6202 : : {
6203 : : struct mlx5_priv *port_priv;
6204 : : struct mlx5_priv *dev_priv;
6205 : :
6206 [ # # ]: 0 : if (target_port_id == MLX5_REPRESENTED_PORT_ESW_MGR)
6207 : : return 0;
6208 : :
6209 : 0 : port_priv = mlx5_port_to_eswitch_info(target_port_id, false);
6210 [ # # ]: 0 : if (!port_priv) {
6211 : 0 : rte_errno = EINVAL;
6212 : 0 : DRV_LOG(ERR, "Port %u Failed to obtain E-Switch info for port %u",
6213 : : dev->data->port_id, target_port_id);
6214 : 0 : return -rte_errno;
6215 : : }
6216 : :
6217 : 0 : dev_priv = mlx5_dev_to_eswitch_info(dev);
6218 [ # # ]: 0 : if (!dev_priv) {
6219 : 0 : rte_errno = EINVAL;
6220 : 0 : DRV_LOG(ERR, "Port %u Failed to obtain E-Switch info for transfer proxy",
6221 : : dev->data->port_id);
6222 : 0 : return -rte_errno;
6223 : : }
6224 : :
6225 [ # # ]: 0 : if (port_priv->domain_id != dev_priv->domain_id) {
6226 : 0 : rte_errno = EINVAL;
6227 : 0 : DRV_LOG(ERR, "Port %u Failed to obtain E-Switch info for transfer proxy",
6228 : : dev->data->port_id);
6229 : 0 : return -rte_errno;
6230 : : }
6231 : :
6232 : : return 0;
6233 : : }
6234 : :
6235 : : static int
6236 : 0 : flow_hw_validate_action_represented_port(struct rte_eth_dev *dev,
6237 : : const struct rte_flow_action *action,
6238 : : const struct rte_flow_action *mask,
6239 : : struct rte_flow_error *error)
6240 : : {
6241 : 0 : const struct rte_flow_action_ethdev *action_conf = action->conf;
6242 : 0 : const struct rte_flow_action_ethdev *mask_conf = mask->conf;
6243 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6244 : :
6245 [ # # ]: 0 : if (!priv->sh->config.dv_esw_en)
6246 : 0 : return rte_flow_error_set(error, EINVAL,
6247 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6248 : : "cannot use represented_port actions"
6249 : : " without an E-Switch");
6250 [ # # # # ]: 0 : if (mask_conf && mask_conf->port_id) {
6251 [ # # ]: 0 : if (!action_conf)
6252 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
6253 : : action, "port index was not provided");
6254 : :
6255 [ # # ]: 0 : if (flow_hw_validate_target_port_id(dev, action_conf->port_id))
6256 : 0 : return rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
6257 : : action, "port index is invalid");
6258 : : }
6259 : : return 0;
6260 : : }
6261 : :
6262 : : /**
6263 : : * Validate AGE action.
6264 : : *
6265 : : * @param[in] dev
6266 : : * Pointer to rte_eth_dev structure.
6267 : : * @param[in] action
6268 : : * Pointer to the indirect action.
6269 : : * @param[in] action_flags
6270 : : * Holds the actions detected until now.
6271 : : * @param[in] fixed_cnt
6272 : : * Indicator if this list has a fixed COUNT action.
6273 : : * @param[out] error
6274 : : * Pointer to error structure.
6275 : : *
6276 : : * @return
6277 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
6278 : : */
6279 : : static int
6280 : 0 : flow_hw_validate_action_age(struct rte_eth_dev *dev,
6281 : : const struct rte_flow_action *action,
6282 : : uint64_t action_flags, bool fixed_cnt,
6283 : : struct rte_flow_error *error)
6284 : : {
6285 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6286 : 0 : struct mlx5_age_info *age_info = GET_PORT_AGE_INFO(priv);
6287 : :
6288 [ # # ]: 0 : if (!priv->sh->cdev->config.devx)
6289 : 0 : return rte_flow_error_set(error, ENOTSUP,
6290 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6291 : : NULL, "AGE action not supported");
6292 [ # # ]: 0 : if (age_info->ages_ipool == NULL)
6293 : 0 : return rte_flow_error_set(error, EINVAL,
6294 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6295 : : "aging pool not initialized");
6296 [ # # ]: 0 : if ((action_flags & MLX5_FLOW_ACTION_AGE) ||
6297 : : (action_flags & MLX5_FLOW_ACTION_INDIRECT_AGE))
6298 : 0 : return rte_flow_error_set(error, EINVAL,
6299 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6300 : : "duplicate AGE actions set");
6301 [ # # ]: 0 : if (fixed_cnt)
6302 : 0 : return rte_flow_error_set(error, EINVAL,
6303 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6304 : : "AGE and fixed COUNT combination is not supported");
6305 : : return 0;
6306 : : }
6307 : :
6308 : : /**
6309 : : * Validate count action.
6310 : : *
6311 : : * @param[in] dev
6312 : : * Pointer to rte_eth_dev structure.
6313 : : * @param[in] action
6314 : : * Pointer to the indirect action.
6315 : : * @param[in] mask
6316 : : * Pointer to the indirect action mask.
6317 : : * @param[in] action_flags
6318 : : * Holds the actions detected until now.
6319 : : * @param[out] error
6320 : : * Pointer to error structure.
6321 : : *
6322 : : * @return
6323 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
6324 : : */
6325 : : static int
6326 : 0 : flow_hw_validate_action_count(struct rte_eth_dev *dev,
6327 : : const struct rte_flow_action *action,
6328 : : const struct rte_flow_action *mask,
6329 : : uint64_t action_flags,
6330 : : struct rte_flow_error *error)
6331 : : {
6332 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6333 : 0 : const struct rte_flow_action_count *count = mask->conf;
6334 : :
6335 [ # # ]: 0 : if (!priv->sh->cdev->config.devx)
6336 : 0 : return rte_flow_error_set(error, ENOTSUP,
6337 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6338 : : "count action not supported");
6339 [ # # ]: 0 : if (!priv->hws_cpool)
6340 : 0 : return rte_flow_error_set(error, EINVAL,
6341 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6342 : : "counters pool not initialized");
6343 [ # # ]: 0 : if ((action_flags & MLX5_FLOW_ACTION_COUNT) ||
6344 : : (action_flags & MLX5_FLOW_ACTION_INDIRECT_COUNT))
6345 : 0 : return rte_flow_error_set(error, EINVAL,
6346 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6347 : : "duplicate count actions set");
6348 [ # # # # : 0 : if (count && count->id && (action_flags & MLX5_FLOW_ACTION_AGE))
# # ]
6349 : 0 : return rte_flow_error_set(error, EINVAL,
6350 : : RTE_FLOW_ERROR_TYPE_ACTION, mask,
6351 : : "AGE and COUNT action shared by mask combination is not supported");
6352 : : return 0;
6353 : : }
6354 : :
6355 : : /**
6356 : : * Validate meter_mark action.
6357 : : *
6358 : : * @param[in] dev
6359 : : * Pointer to rte_eth_dev structure.
6360 : : * @param[in] action
6361 : : * Pointer to the indirect action.
6362 : : * @param[in] indirect
6363 : : * If true, then provided action was passed using an indirect action.
6364 : : * @param[out] error
6365 : : * Pointer to error structure.
6366 : : *
6367 : : * @return
6368 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
6369 : : */
6370 : : static int
6371 : 0 : flow_hw_validate_action_meter_mark(struct rte_eth_dev *dev,
6372 : : const struct rte_flow_action *action,
6373 : : bool indirect,
6374 : : struct rte_flow_error *error)
6375 : : {
6376 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6377 : :
6378 : : RTE_SET_USED(action);
6379 : :
6380 [ # # ]: 0 : if (!priv->sh->cdev->config.devx)
6381 : 0 : return rte_flow_error_set(error, ENOTSUP,
6382 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6383 : : "meter_mark action not supported");
6384 [ # # # # ]: 0 : if (!indirect && priv->shared_host)
6385 : 0 : return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, action,
6386 : : "meter_mark action can only be used on host port");
6387 [ # # ]: 0 : if (!priv->hws_mpool)
6388 : 0 : return rte_flow_error_set(error, EINVAL,
6389 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6390 : : "meter_mark pool not initialized");
6391 : : return 0;
6392 : : }
6393 : :
6394 : : /**
6395 : : * Validate indirect action.
6396 : : *
6397 : : * @param[in] dev
6398 : : * Pointer to rte_eth_dev structure.
6399 : : * @param[in] action
6400 : : * Pointer to the indirect action.
6401 : : * @param[in] mask
6402 : : * Pointer to the indirect action mask.
6403 : : * @param[in, out] action_flags
6404 : : * Holds the actions detected until now.
6405 : : * @param[in, out] fixed_cnt
6406 : : * Pointer to indicator if this list has a fixed COUNT action.
6407 : : * @param[out] error
6408 : : * Pointer to error structure.
6409 : : *
6410 : : * @return
6411 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
6412 : : */
6413 : : static int
6414 : 0 : flow_hw_validate_action_indirect(struct rte_eth_dev *dev,
6415 : : const struct rte_flow_action *action,
6416 : : const struct rte_flow_action *mask,
6417 : : uint64_t *action_flags, bool *fixed_cnt,
6418 : : struct rte_flow_error *error)
6419 : : {
6420 : : uint32_t type;
6421 : : int ret;
6422 : :
6423 [ # # ]: 0 : if (!mask)
6424 : 0 : return rte_flow_error_set(error, EINVAL,
6425 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6426 : : "Unable to determine indirect action type without a mask specified");
6427 : 0 : type = mask->type;
6428 [ # # # # : 0 : switch (type) {
# # # ]
6429 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
6430 : 0 : ret = flow_hw_validate_action_meter_mark(dev, mask, true, error);
6431 [ # # ]: 0 : if (ret < 0)
6432 : : return ret;
6433 : 0 : *action_flags |= MLX5_FLOW_ACTION_METER;
6434 : 0 : break;
6435 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
6436 : : /* TODO: Validation logic (same as flow_hw_actions_validate) */
6437 : 0 : *action_flags |= MLX5_FLOW_ACTION_RSS;
6438 : 0 : break;
6439 : 0 : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
6440 : : /* TODO: Validation logic (same as flow_hw_actions_validate) */
6441 : 0 : *action_flags |= MLX5_FLOW_ACTION_CT;
6442 : 0 : break;
6443 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
6444 [ # # # # ]: 0 : if (action->conf && mask->conf) {
6445 [ # # ]: 0 : if ((*action_flags & MLX5_FLOW_ACTION_AGE) ||
6446 : : (*action_flags & MLX5_FLOW_ACTION_INDIRECT_AGE))
6447 : : /*
6448 : : * AGE cannot use indirect counter which is
6449 : : * shared with enother flow rules.
6450 : : */
6451 : 0 : return rte_flow_error_set(error, EINVAL,
6452 : : RTE_FLOW_ERROR_TYPE_ACTION,
6453 : : NULL,
6454 : : "AGE and fixed COUNT combination is not supported");
6455 : 0 : *fixed_cnt = true;
6456 : : }
6457 : 0 : ret = flow_hw_validate_action_count(dev, action, mask,
6458 : : *action_flags, error);
6459 [ # # ]: 0 : if (ret < 0)
6460 : : return ret;
6461 : 0 : *action_flags |= MLX5_FLOW_ACTION_INDIRECT_COUNT;
6462 : 0 : break;
6463 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
6464 : 0 : ret = flow_hw_validate_action_age(dev, action, *action_flags,
6465 : 0 : *fixed_cnt, error);
6466 [ # # ]: 0 : if (ret < 0)
6467 : : return ret;
6468 : 0 : *action_flags |= MLX5_FLOW_ACTION_INDIRECT_AGE;
6469 : 0 : break;
6470 : 0 : case RTE_FLOW_ACTION_TYPE_QUOTA:
6471 : : /* TODO: add proper quota verification */
6472 : 0 : *action_flags |= MLX5_FLOW_ACTION_QUOTA;
6473 : 0 : break;
6474 : 0 : default:
6475 : 0 : DRV_LOG(WARNING, "Unsupported shared action type: %d", type);
6476 : 0 : return rte_flow_error_set(error, ENOTSUP,
6477 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, mask,
6478 : : "Unsupported indirect action type");
6479 : : }
6480 : : return 0;
6481 : : }
6482 : :
6483 : : /**
6484 : : * Validate ipv6_ext_push action.
6485 : : *
6486 : : * @param[in] dev
6487 : : * Pointer to rte_eth_dev structure.
6488 : : * @param[in] action
6489 : : * Pointer to the indirect action.
6490 : : * @param[out] error
6491 : : * Pointer to error structure.
6492 : : *
6493 : : * @return
6494 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
6495 : : */
6496 : : static int
6497 : 0 : flow_hw_validate_action_ipv6_ext_push(struct rte_eth_dev *dev __rte_unused,
6498 : : const struct rte_flow_action *action,
6499 : : struct rte_flow_error *error)
6500 : : {
6501 : 0 : const struct rte_flow_action_ipv6_ext_push *raw_push_data = action->conf;
6502 : :
6503 [ # # # # : 0 : if (!raw_push_data || !raw_push_data->size || !raw_push_data->data)
# # ]
6504 : 0 : return rte_flow_error_set(error, EINVAL,
6505 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6506 : : "invalid ipv6_ext_push data");
6507 [ # # # # ]: 0 : if (raw_push_data->type != IPPROTO_ROUTING ||
6508 : : raw_push_data->size > MLX5_PUSH_MAX_LEN)
6509 : 0 : return rte_flow_error_set(error, EINVAL,
6510 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6511 : : "Unsupported ipv6_ext_push type or length");
6512 : : return 0;
6513 : : }
6514 : :
6515 : : /**
6516 : : * Process `... / raw_decap / raw_encap / ...` actions sequence.
6517 : : * The PMD handles the sequence as a single encap or decap reformat action,
6518 : : * depending on the raw_encap configuration.
6519 : : *
6520 : : * The function assumes that the raw_decap / raw_encap location
6521 : : * in actions template list complies with relative HWS actions order:
6522 : : * for the required reformat configuration:
6523 : : * ENCAP configuration must appear before [JUMP|DROP|PORT]
6524 : : * DECAP configuration must appear at the template head.
6525 : : */
6526 : : static uint64_t
6527 : : mlx5_decap_encap_reformat_type(const struct rte_flow_action *actions,
6528 : : uint32_t encap_ind, uint64_t flags)
6529 : : {
6530 : 0 : const struct rte_flow_action_raw_encap *encap = actions[encap_ind].conf;
6531 : :
6532 [ # # ]: 0 : if ((flags & MLX5_FLOW_ACTION_DECAP) == 0)
6533 : : return MLX5_FLOW_ACTION_ENCAP;
6534 [ # # ]: 0 : if (actions[encap_ind - 1].type != RTE_FLOW_ACTION_TYPE_RAW_DECAP)
6535 : : return MLX5_FLOW_ACTION_ENCAP;
6536 : 0 : return encap->size >= MLX5_ENCAPSULATION_DECISION_SIZE ?
6537 [ # # ]: 0 : MLX5_FLOW_ACTION_ENCAP : MLX5_FLOW_ACTION_DECAP;
6538 : : }
6539 : :
6540 : : enum mlx5_hw_indirect_list_relative_position {
6541 : : MLX5_INDIRECT_LIST_POSITION_UNKNOWN = -1,
6542 : : MLX5_INDIRECT_LIST_POSITION_BEFORE_MH = 0,
6543 : : MLX5_INDIRECT_LIST_POSITION_AFTER_MH,
6544 : : };
6545 : :
6546 : : static enum mlx5_hw_indirect_list_relative_position
6547 : 0 : mlx5_hw_indirect_list_mh_position(const struct rte_flow_action *action)
6548 : : {
6549 : 0 : const struct rte_flow_action_indirect_list *conf = action->conf;
6550 [ # # # # ]: 0 : enum mlx5_indirect_list_type list_type = mlx5_get_indirect_list_type(conf->handle);
6551 : : enum mlx5_hw_indirect_list_relative_position pos = MLX5_INDIRECT_LIST_POSITION_UNKNOWN;
6552 : : const union {
6553 : : struct mlx5_indlst_legacy *legacy;
6554 : : struct mlx5_hw_encap_decap_action *reformat;
6555 : : struct rte_flow_action_list_handle *handle;
6556 : : } h = { .handle = conf->handle};
6557 : :
6558 [ # # # # ]: 0 : switch (list_type) {
6559 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY:
6560 [ # # # ]: 0 : switch (h.legacy->legacy_type) {
6561 : : case RTE_FLOW_ACTION_TYPE_AGE:
6562 : : case RTE_FLOW_ACTION_TYPE_COUNT:
6563 : : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
6564 : : case RTE_FLOW_ACTION_TYPE_METER_MARK:
6565 : : case RTE_FLOW_ACTION_TYPE_QUOTA:
6566 : : pos = MLX5_INDIRECT_LIST_POSITION_BEFORE_MH;
6567 : : break;
6568 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
6569 : : pos = MLX5_INDIRECT_LIST_POSITION_AFTER_MH;
6570 : 0 : break;
6571 : 0 : default:
6572 : : pos = MLX5_INDIRECT_LIST_POSITION_UNKNOWN;
6573 : 0 : break;
6574 : : }
6575 : : break;
6576 : : case MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR:
6577 : : pos = MLX5_INDIRECT_LIST_POSITION_AFTER_MH;
6578 : : break;
6579 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT:
6580 [ # # # ]: 0 : switch (h.reformat->action_type) {
6581 : : case MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2:
6582 : : case MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2:
6583 : : pos = MLX5_INDIRECT_LIST_POSITION_BEFORE_MH;
6584 : : break;
6585 : 0 : case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2:
6586 : : case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3:
6587 : : pos = MLX5_INDIRECT_LIST_POSITION_AFTER_MH;
6588 : 0 : break;
6589 : 0 : default:
6590 : : pos = MLX5_INDIRECT_LIST_POSITION_UNKNOWN;
6591 : 0 : break;
6592 : : }
6593 : : break;
6594 : 0 : default:
6595 : : pos = MLX5_INDIRECT_LIST_POSITION_UNKNOWN;
6596 : 0 : break;
6597 : : }
6598 : 0 : return pos;
6599 : : }
6600 : :
6601 : : #define MLX5_HW_EXPAND_MH_FAILED 0xffff
6602 : :
6603 : : static inline uint16_t
6604 : 0 : flow_hw_template_expand_modify_field(struct rte_flow_action actions[],
6605 : : struct rte_flow_action masks[],
6606 : : const struct rte_flow_action *mf_actions,
6607 : : const struct rte_flow_action *mf_masks,
6608 : : uint64_t flags, uint32_t act_num,
6609 : : uint32_t mf_num)
6610 : : {
6611 : : uint32_t i, tail;
6612 : :
6613 : : MLX5_ASSERT(actions && masks);
6614 : : MLX5_ASSERT(mf_num > 0);
6615 [ # # ]: 0 : if (flags & MLX5_FLOW_ACTION_MODIFY_FIELD) {
6616 : : /*
6617 : : * Application action template already has Modify Field.
6618 : : * It's location will be used in DR.
6619 : : * Expanded MF action can be added before the END.
6620 : : */
6621 : 0 : i = act_num - 1;
6622 : 0 : goto insert;
6623 : : }
6624 : : /**
6625 : : * Locate the first action positioned BEFORE the new MF.
6626 : : *
6627 : : * Search for a place to insert modify header
6628 : : * from the END action backwards:
6629 : : * 1. END is always present in actions array
6630 : : * 2. END location is always at action[act_num - 1]
6631 : : * 3. END always positioned AFTER modify field location
6632 : : *
6633 : : * Relative actions order is the same for RX, TX and FDB.
6634 : : *
6635 : : * Current actions order (draft-3)
6636 : : * @see action_order_arr[]
6637 : : */
6638 [ # # ]: 0 : for (i = act_num - 2; (int)i >= 0; i--) {
6639 : : enum mlx5_hw_indirect_list_relative_position pos;
6640 : 0 : enum rte_flow_action_type type = actions[i].type;
6641 : : uint64_t reformat_type;
6642 : :
6643 [ # # ]: 0 : if (type == RTE_FLOW_ACTION_TYPE_INDIRECT)
6644 : 0 : type = masks[i].type;
6645 [ # # # # ]: 0 : switch (type) {
6646 : : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
6647 : : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
6648 : : case RTE_FLOW_ACTION_TYPE_DROP:
6649 : : case RTE_FLOW_ACTION_TYPE_SEND_TO_KERNEL:
6650 : : case RTE_FLOW_ACTION_TYPE_JUMP:
6651 : : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
6652 : : case RTE_FLOW_ACTION_TYPE_QUEUE:
6653 : : case RTE_FLOW_ACTION_TYPE_RSS:
6654 : : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
6655 : : case RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:
6656 : : case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
6657 : : case RTE_FLOW_ACTION_TYPE_VOID:
6658 : : case RTE_FLOW_ACTION_TYPE_END:
6659 : : break;
6660 : : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
6661 : : reformat_type =
6662 : : mlx5_decap_encap_reformat_type(actions, i,
6663 : : flags);
6664 : : if (reformat_type == MLX5_FLOW_ACTION_DECAP) {
6665 : 0 : i++;
6666 : 0 : goto insert;
6667 : : }
6668 [ # # ]: 0 : if (actions[i - 1].type == RTE_FLOW_ACTION_TYPE_RAW_DECAP)
6669 : : i--;
6670 : : break;
6671 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT_LIST:
6672 : 0 : pos = mlx5_hw_indirect_list_mh_position(&actions[i]);
6673 [ # # ]: 0 : if (pos == MLX5_INDIRECT_LIST_POSITION_UNKNOWN)
6674 : : return MLX5_HW_EXPAND_MH_FAILED;
6675 [ # # ]: 0 : if (pos == MLX5_INDIRECT_LIST_POSITION_BEFORE_MH)
6676 : 0 : goto insert;
6677 : : break;
6678 : 0 : default:
6679 : 0 : i++; /* new MF inserted AFTER actions[i] */
6680 : 0 : goto insert;
6681 : : }
6682 : : }
6683 : : i = 0;
6684 : 0 : insert:
6685 : 0 : tail = act_num - i; /* num action to move */
6686 : 0 : memmove(actions + i + mf_num, actions + i, sizeof(actions[0]) * tail);
6687 : 0 : memcpy(actions + i, mf_actions, sizeof(actions[0]) * mf_num);
6688 : 0 : memmove(masks + i + mf_num, masks + i, sizeof(masks[0]) * tail);
6689 : : memcpy(masks + i, mf_masks, sizeof(masks[0]) * mf_num);
6690 : 0 : return i;
6691 : : }
6692 : :
6693 : : static int
6694 : 0 : flow_hw_validate_action_push_vlan(struct rte_eth_dev *dev,
6695 : : const
6696 : : struct rte_flow_actions_template_attr *attr,
6697 : : const struct rte_flow_action *action,
6698 : : const struct rte_flow_action *mask,
6699 : : struct rte_flow_error *error)
6700 : : {
6701 : : #define X_FIELD(ptr, t, f) (((ptr)->conf) && ((t *)((ptr)->conf))->f)
6702 : :
6703 : 0 : const bool masked_push =
6704 [ # # # # ]: 0 : X_FIELD(mask + MLX5_HW_VLAN_PUSH_TYPE_IDX,
6705 : : const struct rte_flow_action_of_push_vlan, ethertype);
6706 : : bool masked_param;
6707 : :
6708 : : /*
6709 : : * Mandatory actions order:
6710 : : * OF_PUSH_VLAN / OF_SET_VLAN_VID [ / OF_SET_VLAN_PCP ]
6711 : : */
6712 : : RTE_SET_USED(dev);
6713 : : RTE_SET_USED(attr);
6714 : : /* Check that mark matches OF_PUSH_VLAN */
6715 [ # # ]: 0 : if (mask[MLX5_HW_VLAN_PUSH_TYPE_IDX].type !=
6716 : : RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN)
6717 : 0 : return rte_flow_error_set(error, EINVAL,
6718 : : RTE_FLOW_ERROR_TYPE_ACTION,
6719 : : action, "OF_PUSH_VLAN: mask does not match");
6720 : : /* Check that the second template and mask items are SET_VLAN_VID */
6721 [ # # ]: 0 : if (action[MLX5_HW_VLAN_PUSH_VID_IDX].type !=
6722 : 0 : RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID ||
6723 [ # # ]: 0 : mask[MLX5_HW_VLAN_PUSH_VID_IDX].type !=
6724 : : RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)
6725 : 0 : return rte_flow_error_set(error, EINVAL,
6726 : : RTE_FLOW_ERROR_TYPE_ACTION,
6727 : : action, "OF_PUSH_VLAN: invalid actions order");
6728 [ # # # # ]: 0 : masked_param = X_FIELD(mask + MLX5_HW_VLAN_PUSH_VID_IDX,
6729 : : const struct rte_flow_action_of_set_vlan_vid,
6730 : : vlan_vid);
6731 : : /*
6732 : : * PMD requires OF_SET_VLAN_VID mask to must match OF_PUSH_VLAN
6733 : : */
6734 [ # # ]: 0 : if (masked_push ^ masked_param)
6735 : 0 : return rte_flow_error_set(error, EINVAL,
6736 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6737 : : "OF_SET_VLAN_VID: mask does not match OF_PUSH_VLAN");
6738 [ # # ]: 0 : if (is_of_vlan_pcp_present(action)) {
6739 [ # # ]: 0 : if (mask[MLX5_HW_VLAN_PUSH_PCP_IDX].type !=
6740 : : RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)
6741 : 0 : return rte_flow_error_set(error, EINVAL,
6742 : : RTE_FLOW_ERROR_TYPE_ACTION,
6743 : : action, "OF_SET_VLAN_PCP: missing mask configuration");
6744 [ # # # # ]: 0 : masked_param = X_FIELD(mask + MLX5_HW_VLAN_PUSH_PCP_IDX,
6745 : : const struct
6746 : : rte_flow_action_of_set_vlan_pcp,
6747 : : vlan_pcp);
6748 : : /*
6749 : : * PMD requires OF_SET_VLAN_PCP mask to must match OF_PUSH_VLAN
6750 : : */
6751 [ # # ]: 0 : if (masked_push ^ masked_param)
6752 : 0 : return rte_flow_error_set(error, EINVAL,
6753 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6754 : : "OF_SET_VLAN_PCP: mask does not match OF_PUSH_VLAN");
6755 : : }
6756 : : return 0;
6757 : : #undef X_FIELD
6758 : : }
6759 : :
6760 : : static int
6761 : 0 : flow_hw_validate_action_default_miss(struct rte_eth_dev *dev,
6762 : : const struct rte_flow_actions_template_attr *attr,
6763 : : uint64_t action_flags,
6764 : : struct rte_flow_error *error)
6765 : : {
6766 : : /*
6767 : : * The private DEFAULT_MISS action is used internally for LACP in control
6768 : : * flows. So this validation can be ignored. It can be kept right now since
6769 : : * the validation will be done only once.
6770 : : */
6771 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6772 : :
6773 [ # # ]: 0 : if (!attr->ingress || attr->egress || attr->transfer)
6774 : 0 : return rte_flow_error_set(error, EINVAL,
6775 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6776 : : "DEFAULT MISS is only supported in ingress.");
6777 [ # # ]: 0 : if (!priv->hw_def_miss)
6778 : 0 : return rte_flow_error_set(error, EINVAL,
6779 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6780 : : "DEFAULT MISS action does not exist.");
6781 [ # # ]: 0 : if (action_flags & MLX5_FLOW_FATE_ACTIONS)
6782 : 0 : return rte_flow_error_set(error, EINVAL,
6783 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6784 : : "DEFAULT MISS should be the only termination.");
6785 : : return 0;
6786 : : }
6787 : :
6788 : : static int
6789 : 0 : flow_hw_validate_action_nat64(struct rte_eth_dev *dev,
6790 : : const struct rte_flow_actions_template_attr *attr,
6791 : : const struct rte_flow_action *action,
6792 : : const struct rte_flow_action *mask,
6793 : : uint64_t action_flags,
6794 : : struct rte_flow_error *error)
6795 : : {
6796 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6797 : : const struct rte_flow_action_nat64 *nat64_c;
6798 : : enum rte_flow_nat64_type cov_type;
6799 : :
6800 : : RTE_SET_USED(action_flags);
6801 [ # # # # ]: 0 : if (mask->conf && ((const struct rte_flow_action_nat64 *)mask->conf)->type) {
6802 : 0 : nat64_c = (const struct rte_flow_action_nat64 *)action->conf;
6803 : 0 : cov_type = nat64_c->type;
6804 [ # # # # ]: 0 : if ((attr->ingress && !priv->action_nat64[MLX5DR_TABLE_TYPE_NIC_RX][cov_type]) ||
6805 [ # # # # ]: 0 : (attr->egress && !priv->action_nat64[MLX5DR_TABLE_TYPE_NIC_TX][cov_type]))
6806 : 0 : goto err_out;
6807 [ # # ]: 0 : if (attr->transfer) {
6808 [ # # ]: 0 : if (!is_unified_fdb(priv)) {
6809 [ # # ]: 0 : if (!priv->action_nat64[MLX5DR_TABLE_TYPE_FDB][cov_type])
6810 : 0 : goto err_out;
6811 : : } else {
6812 [ # # ]: 0 : if (!priv->action_nat64[MLX5DR_TABLE_TYPE_FDB_RX][cov_type] ||
6813 [ # # ]: 0 : !priv->action_nat64[MLX5DR_TABLE_TYPE_FDB_TX][cov_type] ||
6814 [ # # ]: 0 : !priv->action_nat64[MLX5DR_TABLE_TYPE_FDB_UNIFIED][cov_type])
6815 : 0 : goto err_out;
6816 : : }
6817 : : }
6818 : : } else {
6819 : : /*
6820 : : * Usually, the actions will be used on both directions. For non-masked actions,
6821 : : * both directions' actions will be checked.
6822 : : */
6823 [ # # ]: 0 : if (attr->ingress)
6824 [ # # ]: 0 : if (!priv->action_nat64[MLX5DR_TABLE_TYPE_NIC_RX][RTE_FLOW_NAT64_6TO4] ||
6825 [ # # ]: 0 : !priv->action_nat64[MLX5DR_TABLE_TYPE_NIC_RX][RTE_FLOW_NAT64_4TO6])
6826 : 0 : goto err_out;
6827 [ # # ]: 0 : if (attr->egress)
6828 [ # # ]: 0 : if (!priv->action_nat64[MLX5DR_TABLE_TYPE_NIC_TX][RTE_FLOW_NAT64_6TO4] ||
6829 [ # # ]: 0 : !priv->action_nat64[MLX5DR_TABLE_TYPE_NIC_TX][RTE_FLOW_NAT64_4TO6])
6830 : 0 : goto err_out;
6831 [ # # ]: 0 : if (attr->transfer) {
6832 [ # # ]: 0 : if (!is_unified_fdb(priv)) {
6833 : 0 : if (!priv->action_nat64[MLX5DR_TABLE_TYPE_FDB]
6834 [ # # ]: 0 : [RTE_FLOW_NAT64_6TO4] ||
6835 : : !priv->action_nat64[MLX5DR_TABLE_TYPE_FDB]
6836 [ # # ]: 0 : [RTE_FLOW_NAT64_4TO6])
6837 : 0 : goto err_out;
6838 : : } else {
6839 : 0 : if (!priv->action_nat64[MLX5DR_TABLE_TYPE_FDB_RX]
6840 [ # # ]: 0 : [RTE_FLOW_NAT64_6TO4] ||
6841 : : !priv->action_nat64[MLX5DR_TABLE_TYPE_FDB_RX]
6842 [ # # ]: 0 : [RTE_FLOW_NAT64_4TO6] ||
6843 : : !priv->action_nat64[MLX5DR_TABLE_TYPE_FDB_TX]
6844 [ # # ]: 0 : [RTE_FLOW_NAT64_6TO4] ||
6845 : : !priv->action_nat64[MLX5DR_TABLE_TYPE_FDB_TX]
6846 [ # # ]: 0 : [RTE_FLOW_NAT64_4TO6] ||
6847 : : !priv->action_nat64[MLX5DR_TABLE_TYPE_FDB_UNIFIED]
6848 [ # # ]: 0 : [RTE_FLOW_NAT64_6TO4] ||
6849 : : !priv->action_nat64[MLX5DR_TABLE_TYPE_FDB_UNIFIED]
6850 [ # # ]: 0 : [RTE_FLOW_NAT64_4TO6])
6851 : 0 : goto err_out;
6852 : : }
6853 : : }
6854 : : }
6855 : : return 0;
6856 : 0 : err_out:
6857 : 0 : return rte_flow_error_set(error, EOPNOTSUPP, RTE_FLOW_ERROR_TYPE_ACTION,
6858 : : NULL, "NAT64 action is not supported.");
6859 : : }
6860 : :
6861 : : static int
6862 : 0 : flow_hw_validate_action_jump(struct rte_eth_dev *dev,
6863 : : const struct rte_flow_actions_template_attr *attr,
6864 : : const struct rte_flow_action *action,
6865 : : const struct rte_flow_action *mask,
6866 : : struct rte_flow_error *error)
6867 : : {
6868 : 0 : const struct rte_flow_action_jump *m = mask->conf;
6869 : 0 : const struct rte_flow_action_jump *v = action->conf;
6870 : 0 : struct mlx5_flow_template_table_cfg cfg = {
6871 : : .external = true,
6872 : : .attr = {
6873 : : .flow_attr = {
6874 : 0 : .ingress = attr->ingress,
6875 : 0 : .egress = attr->egress,
6876 : 0 : .transfer = attr->transfer,
6877 : : },
6878 : : },
6879 : : };
6880 : 0 : uint32_t t_group = 0;
6881 : :
6882 [ # # # # ]: 0 : if (!m || !m->group)
6883 : : return 0;
6884 [ # # ]: 0 : if (!v)
6885 : 0 : return rte_flow_error_set(error, EINVAL,
6886 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6887 : : "Invalid jump action configuration");
6888 [ # # ]: 0 : if (flow_hw_translate_group(dev, &cfg, v->group, &t_group, error))
6889 : 0 : return -rte_errno;
6890 [ # # ]: 0 : if (t_group == 0)
6891 : 0 : return rte_flow_error_set(error, EINVAL,
6892 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6893 : : "Unsupported action - jump to root table");
6894 : : return 0;
6895 : : }
6896 : :
6897 : : static int
6898 : 0 : mlx5_flow_validate_action_jump_to_table_index(const struct rte_flow_action *action,
6899 : : const struct rte_flow_action *mask,
6900 : : struct rte_flow_error *error)
6901 : : {
6902 : 0 : const struct rte_flow_action_jump_to_table_index *m = mask->conf;
6903 : 0 : const struct rte_flow_action_jump_to_table_index *v = action->conf;
6904 : : struct mlx5dr_action *jump_action;
6905 : : uint32_t t_group = 0;
6906 : :
6907 [ # # # # ]: 0 : if (!m || !m->table)
6908 : : return 0;
6909 [ # # ]: 0 : if (!v)
6910 : 0 : return rte_flow_error_set(error, EINVAL,
6911 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6912 : : "Invalid jump to matcher action configuration");
6913 : 0 : t_group = v->table->grp->group_id;
6914 [ # # ]: 0 : if (t_group == 0)
6915 : 0 : return rte_flow_error_set(error, EINVAL,
6916 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6917 : : "Unsupported action - jump to root table");
6918 [ # # ]: 0 : if (likely(!rte_flow_template_table_resizable(0, &v->table->cfg.attr))) {
6919 : 0 : jump_action = v->table->matcher_info[0].jump;
6920 : : } else {
6921 : : uint32_t selector;
6922 : 0 : rte_rwlock_read_lock(&v->table->matcher_replace_rwlk);
6923 : 0 : selector = v->table->matcher_selector;
6924 : 0 : jump_action = v->table->matcher_info[selector].jump;
6925 : : rte_rwlock_read_unlock(&v->table->matcher_replace_rwlk);
6926 : : }
6927 [ # # ]: 0 : if (jump_action == NULL)
6928 : 0 : return rte_flow_error_set(error, EINVAL,
6929 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6930 : : "Unsupported action - table is not an rule array");
6931 : : return 0;
6932 : : }
6933 : :
6934 : : static int
6935 : 0 : mlx5_hw_validate_action_mark(struct rte_eth_dev *dev,
6936 : : const struct rte_flow_action *template_action,
6937 : : const struct rte_flow_action *template_mask,
6938 : : uint64_t action_flags,
6939 : : const struct rte_flow_actions_template_attr *template_attr,
6940 : : struct rte_flow_error *error)
6941 : : {
6942 : 0 : const struct rte_flow_action_mark *mark_mask = template_mask->conf;
6943 : : const struct rte_flow_action *action =
6944 [ # # # # ]: 0 : mark_mask && mark_mask->id ? template_action :
6945 : 0 : &(const struct rte_flow_action) {
6946 : : .type = RTE_FLOW_ACTION_TYPE_MARK,
6947 : 0 : .conf = &(const struct rte_flow_action_mark) {
6948 : : .id = MLX5_FLOW_MARK_MAX - 1
6949 : : }
6950 : : };
6951 : 0 : const struct rte_flow_attr attr = {
6952 : 0 : .ingress = template_attr->ingress,
6953 : 0 : .egress = template_attr->egress,
6954 : 0 : .transfer = template_attr->transfer
6955 : : };
6956 : :
6957 : 0 : return mlx5_flow_validate_action_mark(dev, action, action_flags,
6958 : : &attr, error);
6959 : : }
6960 : :
6961 : : static int
6962 : 0 : mlx5_hw_validate_action_queue(struct rte_eth_dev *dev,
6963 : : const struct rte_flow_action *template_action,
6964 : : const struct rte_flow_action *template_mask,
6965 : : const struct rte_flow_actions_template_attr *template_attr,
6966 : : uint64_t action_flags,
6967 : : struct rte_flow_error *error)
6968 : : {
6969 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6970 : 0 : const struct rte_flow_action_queue *queue_mask = template_mask->conf;
6971 : 0 : const struct rte_flow_attr attr = {
6972 : 0 : .ingress = template_attr->ingress,
6973 : 0 : .egress = template_attr->egress,
6974 : 0 : .transfer = template_attr->transfer
6975 : : };
6976 [ # # # # ]: 0 : bool masked = queue_mask != NULL && queue_mask->index;
6977 : :
6978 [ # # # # : 0 : if (template_attr->egress || (template_attr->transfer && !priv->jump_fdb_rx_en))
# # ]
6979 : 0 : return rte_flow_error_set(error, EINVAL,
6980 : : RTE_FLOW_ERROR_TYPE_ATTR, NULL,
6981 : : "QUEUE action supported for ingress only");
6982 [ # # ]: 0 : if (masked)
6983 : 0 : return mlx5_flow_validate_action_queue(template_action, action_flags, dev,
6984 : : &attr, error);
6985 : : else
6986 : : return 0;
6987 : : }
6988 : :
6989 : : static int
6990 : 0 : mlx5_hw_validate_action_rss(struct rte_eth_dev *dev,
6991 : : const struct rte_flow_action *template_action,
6992 : : const struct rte_flow_action *template_mask,
6993 : : const struct rte_flow_actions_template_attr *template_attr,
6994 : : __rte_unused uint64_t action_flags,
6995 : : struct rte_flow_error *error)
6996 : : {
6997 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6998 : 0 : const struct rte_flow_action_rss *mask = template_mask->conf;
6999 : :
7000 [ # # # # : 0 : if (template_attr->egress || (template_attr->transfer && !priv->jump_fdb_rx_en))
# # ]
7001 : 0 : return rte_flow_error_set(error, EINVAL,
7002 : : RTE_FLOW_ERROR_TYPE_ATTR, NULL,
7003 : : "RSS action supported for ingress only");
7004 [ # # ]: 0 : if (mask != NULL)
7005 : 0 : return mlx5_validate_action_rss(dev, template_action, error);
7006 : : else
7007 : : return 0;
7008 : : }
7009 : :
7010 : : static int
7011 : 0 : mlx5_hw_validate_action_l2_encap(struct rte_eth_dev *dev,
7012 : : const struct rte_flow_action *template_action,
7013 : : const struct rte_flow_action *template_mask,
7014 : : const struct rte_flow_actions_template_attr *template_attr,
7015 : : uint64_t action_flags,
7016 : : struct rte_flow_error *error)
7017 : : {
7018 : 0 : const struct rte_flow_action_vxlan_encap default_action_conf = {
7019 : : .definition = (struct rte_flow_item *)
7020 : 0 : (struct rte_flow_item [1]) {
7021 : : [0] = { .type = RTE_FLOW_ITEM_TYPE_END }
7022 : : }
7023 : : };
7024 : 0 : const struct rte_flow_action *action = template_mask->conf ?
7025 [ # # ]: 0 : template_action : &(const struct rte_flow_action) {
7026 : 0 : .type = template_mask->type,
7027 : : .conf = &default_action_conf
7028 : : };
7029 : 0 : const struct rte_flow_attr attr = {
7030 : 0 : .ingress = template_attr->ingress,
7031 : 0 : .egress = template_attr->egress,
7032 : 0 : .transfer = template_attr->transfer
7033 : : };
7034 : :
7035 : 0 : return mlx5_flow_dv_validate_action_l2_encap(dev, action_flags, action,
7036 : : &attr, error);
7037 : : }
7038 : :
7039 : : static int
7040 : 0 : mlx5_hw_validate_action_l2_decap(struct rte_eth_dev *dev,
7041 : : const struct rte_flow_action *template_action,
7042 : : const struct rte_flow_action *template_mask,
7043 : : const struct rte_flow_actions_template_attr *template_attr,
7044 : : uint64_t action_flags,
7045 : : struct rte_flow_error *error)
7046 : : {
7047 : 0 : const struct rte_flow_action_vxlan_encap default_action_conf = {
7048 : : .definition = (struct rte_flow_item *)
7049 : 0 : (struct rte_flow_item [1]) {
7050 : : [0] = { .type = RTE_FLOW_ITEM_TYPE_END }
7051 : : }
7052 : : };
7053 : 0 : const struct rte_flow_action *action = template_mask->conf ?
7054 [ # # ]: 0 : template_action : &(const struct rte_flow_action) {
7055 : 0 : .type = template_mask->type,
7056 : : .conf = &default_action_conf
7057 : : };
7058 : 0 : const struct rte_flow_attr attr = {
7059 : 0 : .ingress = template_attr->ingress,
7060 : 0 : .egress = template_attr->egress,
7061 : 0 : .transfer = template_attr->transfer
7062 : : };
7063 : : uint64_t item_flags =
7064 : 0 : action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
7065 [ # # ]: 0 : MLX5_FLOW_LAYER_VXLAN : 0;
7066 : :
7067 : 0 : return mlx5_flow_dv_validate_action_decap(dev, action_flags, action,
7068 : : item_flags, &attr, error);
7069 : : }
7070 : :
7071 : : static int
7072 : : mlx5_hw_validate_action_conntrack(struct rte_eth_dev *dev,
7073 : : const struct rte_flow_action *template_action,
7074 : : const struct rte_flow_action *template_mask,
7075 : : const struct rte_flow_actions_template_attr *template_attr,
7076 : : uint64_t action_flags,
7077 : : struct rte_flow_error *error)
7078 : : {
7079 : : RTE_SET_USED(template_action);
7080 : : RTE_SET_USED(template_mask);
7081 : : RTE_SET_USED(template_attr);
7082 : 0 : return mlx5_flow_dv_validate_action_aso_ct(dev, action_flags,
7083 : : MLX5_FLOW_LAYER_OUTER_L4_TCP,
7084 : : false, error);
7085 : : }
7086 : :
7087 : : static int
7088 : 0 : flow_hw_validate_action_raw_encap(const struct rte_flow_action *action,
7089 : : const struct rte_flow_action *mask,
7090 : : struct rte_flow_error *error)
7091 : : {
7092 : 0 : const struct rte_flow_action_raw_encap *mask_conf = mask->conf;
7093 : 0 : const struct rte_flow_action_raw_encap *action_conf = action->conf;
7094 : :
7095 [ # # # # ]: 0 : if (!mask_conf || !mask_conf->size)
7096 : 0 : return rte_flow_error_set(error, EINVAL,
7097 : : RTE_FLOW_ERROR_TYPE_ACTION, mask,
7098 : : "raw_encap: size must be masked");
7099 [ # # # # ]: 0 : if (!action_conf || !action_conf->size)
7100 : 0 : return rte_flow_error_set(error, EINVAL,
7101 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
7102 : : "raw_encap: invalid action configuration");
7103 [ # # # # ]: 0 : if (mask_conf->data && !action_conf->data)
7104 : 0 : return rte_flow_error_set(error, EINVAL,
7105 : : RTE_FLOW_ERROR_TYPE_ACTION,
7106 : : action, "raw_encap: masked data is missing");
7107 : : return 0;
7108 : : }
7109 : :
7110 : :
7111 : : static int
7112 : 0 : flow_hw_validate_action_raw_reformat(struct rte_eth_dev *dev,
7113 : : const struct rte_flow_action *template_action,
7114 : : const struct rte_flow_action *template_mask,
7115 : : const struct
7116 : : rte_flow_actions_template_attr *template_attr,
7117 : : uint64_t *action_flags,
7118 : : struct rte_flow_error *error)
7119 : : {
7120 : : const struct rte_flow_action *encap_action = NULL;
7121 : : const struct rte_flow_action *encap_mask = NULL;
7122 : : const struct rte_flow_action_raw_decap *raw_decap = NULL;
7123 : : const struct rte_flow_action_raw_encap *raw_encap = NULL;
7124 : 0 : const struct rte_flow_attr attr = {
7125 : 0 : .ingress = template_attr->ingress,
7126 : 0 : .egress = template_attr->egress,
7127 : 0 : .transfer = template_attr->transfer
7128 : : };
7129 : : uint64_t item_flags = 0;
7130 : 0 : int ret, actions_n = 0;
7131 : :
7132 [ # # ]: 0 : if (template_action->type == RTE_FLOW_ACTION_TYPE_RAW_DECAP) {
7133 : 0 : raw_decap = template_mask->conf ?
7134 [ # # ]: 0 : template_action->conf : &empty_decap;
7135 [ # # ]: 0 : if ((template_action + 1)->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7136 [ # # ]: 0 : if ((template_mask + 1)->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP)
7137 : 0 : return rte_flow_error_set(error, EINVAL,
7138 : : RTE_FLOW_ERROR_TYPE_ACTION,
7139 : 0 : template_mask + 1, "invalid mask type");
7140 : 0 : encap_action = template_action + 1;
7141 : 0 : encap_mask = template_mask + 1;
7142 : : }
7143 : : } else {
7144 : : encap_action = template_action;
7145 : : encap_mask = template_mask;
7146 : : }
7147 [ # # ]: 0 : if (encap_action) {
7148 : 0 : raw_encap = encap_action->conf;
7149 : 0 : ret = flow_hw_validate_action_raw_encap(encap_action,
7150 : : encap_mask, error);
7151 [ # # ]: 0 : if (ret)
7152 : : return ret;
7153 : : }
7154 : 0 : return mlx5_flow_dv_validate_action_raw_encap_decap(dev, raw_decap,
7155 : : raw_encap, &attr,
7156 : : action_flags,
7157 : : &actions_n,
7158 : : template_action,
7159 : : item_flags, error);
7160 : : }
7161 : :
7162 : :
7163 : :
7164 : : static int
7165 : 0 : mlx5_flow_hw_actions_validate(struct rte_eth_dev *dev,
7166 : : const struct rte_flow_actions_template_attr *attr,
7167 : : const struct rte_flow_action actions[],
7168 : : const struct rte_flow_action masks[],
7169 : : uint64_t *act_flags,
7170 : : struct rte_flow_error *error)
7171 : : {
7172 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
7173 : : const struct rte_flow_action_count *count_mask = NULL;
7174 : 0 : bool fixed_cnt = false;
7175 : 0 : uint64_t action_flags = 0;
7176 : : bool actions_end = false;
7177 : : uint16_t i;
7178 : : int ret;
7179 : : const struct rte_flow_action_ipv6_ext_remove *remove_data;
7180 : :
7181 [ # # ]: 0 : if (!mlx5_hw_ctx_validate(dev, error))
7182 : 0 : return -rte_errno;
7183 : : /* FDB actions are only valid to proxy port. */
7184 [ # # # # : 0 : if (attr->transfer && (!priv->sh->config.dv_esw_en || !priv->master))
# # ]
7185 : 0 : return rte_flow_error_set(error, EINVAL,
7186 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7187 : : NULL,
7188 : : "transfer actions are only valid to proxy port");
7189 [ # # ]: 0 : for (i = 0; !actions_end; ++i) {
7190 : 0 : const struct rte_flow_action *action = &actions[i];
7191 : 0 : const struct rte_flow_action *mask = &masks[i];
7192 : :
7193 : : MLX5_ASSERT(i < MLX5_HW_MAX_ACTS);
7194 [ # # ]: 0 : if (action->type != RTE_FLOW_ACTION_TYPE_INDIRECT &&
7195 [ # # ]: 0 : action->type != mask->type)
7196 : 0 : return rte_flow_error_set(error, ENOTSUP,
7197 : : RTE_FLOW_ERROR_TYPE_ACTION,
7198 : : action,
7199 : : "mask type does not match action type");
7200 [ # # # # : 0 : switch ((int)action->type) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # #
# ]
7201 : : case RTE_FLOW_ACTION_TYPE_VOID:
7202 : 0 : break;
7203 : : case RTE_FLOW_ACTION_TYPE_INDIRECT_LIST:
7204 : : break;
7205 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT:
7206 : 0 : ret = flow_hw_validate_action_indirect(dev, action,
7207 : : mask,
7208 : : &action_flags,
7209 : : &fixed_cnt,
7210 : : error);
7211 [ # # ]: 0 : if (ret < 0)
7212 : 0 : return ret;
7213 : : break;
7214 : 0 : case RTE_FLOW_ACTION_TYPE_FLAG:
7215 : : /* TODO: Validation logic */
7216 : 0 : action_flags |= MLX5_FLOW_ACTION_FLAG;
7217 : 0 : break;
7218 : 0 : case RTE_FLOW_ACTION_TYPE_MARK:
7219 : 0 : ret = mlx5_hw_validate_action_mark(dev, action, mask,
7220 : : action_flags,
7221 : : attr, error);
7222 [ # # ]: 0 : if (ret)
7223 : 0 : return ret;
7224 : 0 : action_flags |= MLX5_FLOW_ACTION_MARK;
7225 : 0 : break;
7226 : 0 : case RTE_FLOW_ACTION_TYPE_DROP:
7227 : 0 : ret = mlx5_flow_validate_action_drop
7228 : : (dev, action_flags,
7229 : 0 : &(struct rte_flow_attr){.egress = attr->egress},
7230 : : error);
7231 [ # # ]: 0 : if (ret)
7232 : 0 : return ret;
7233 : 0 : action_flags |= MLX5_FLOW_ACTION_DROP;
7234 : 0 : break;
7235 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP:
7236 : : /* Only validate the jump to root table in template stage. */
7237 : 0 : ret = flow_hw_validate_action_jump(dev, attr, action, mask, error);
7238 [ # # ]: 0 : if (ret)
7239 : 0 : return ret;
7240 : 0 : action_flags |= MLX5_FLOW_ACTION_JUMP;
7241 : 0 : break;
7242 : : #ifdef HAVE_MLX5DV_DR_ACTION_CREATE_DEST_ROOT_TABLE
7243 : : case RTE_FLOW_ACTION_TYPE_SEND_TO_KERNEL: {
7244 : : bool res;
7245 : :
7246 : : if (priv->shared_host)
7247 : : return rte_flow_error_set(error, ENOTSUP,
7248 : : RTE_FLOW_ERROR_TYPE_ACTION,
7249 : : action,
7250 : : "action not supported in guest port");
7251 : : if (attr->ingress) {
7252 : : res = priv->hw_send_to_kernel[MLX5DR_TABLE_TYPE_NIC_RX];
7253 : : } else if (attr->egress) {
7254 : : res = priv->hw_send_to_kernel[MLX5DR_TABLE_TYPE_NIC_TX];
7255 : : } else {
7256 : : if (!is_unified_fdb(priv))
7257 : : res = priv->hw_send_to_kernel[MLX5DR_TABLE_TYPE_FDB];
7258 : : else
7259 : : res =
7260 : : priv->hw_send_to_kernel[MLX5DR_TABLE_TYPE_FDB_RX] &&
7261 : : priv->hw_send_to_kernel[MLX5DR_TABLE_TYPE_FDB_TX] &&
7262 : : priv->hw_send_to_kernel[MLX5DR_TABLE_TYPE_FDB_UNIFIED];
7263 : : }
7264 : : if (!res)
7265 : : return rte_flow_error_set(error, ENOTSUP,
7266 : : RTE_FLOW_ERROR_TYPE_ACTION,
7267 : : action,
7268 : : "action is not available");
7269 : :
7270 : : action_flags |= MLX5_FLOW_ACTION_SEND_TO_KERNEL;
7271 : : break;
7272 : : }
7273 : : #endif
7274 : 0 : case RTE_FLOW_ACTION_TYPE_QUEUE:
7275 : 0 : ret = mlx5_hw_validate_action_queue(dev, action, mask,
7276 : : attr, action_flags,
7277 : : error);
7278 [ # # ]: 0 : if (ret)
7279 : 0 : return ret;
7280 : 0 : action_flags |= MLX5_FLOW_ACTION_QUEUE;
7281 : 0 : break;
7282 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
7283 : 0 : ret = mlx5_hw_validate_action_rss(dev, action, mask,
7284 : : attr, action_flags,
7285 : : error);
7286 [ # # ]: 0 : if (ret)
7287 : 0 : return ret;
7288 : 0 : action_flags |= MLX5_FLOW_ACTION_RSS;
7289 : 0 : break;
7290 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7291 : : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7292 : 0 : ret = mlx5_hw_validate_action_l2_encap(dev, action, mask,
7293 : : attr, action_flags,
7294 : : error);
7295 [ # # ]: 0 : if (ret)
7296 : 0 : return ret;
7297 : 0 : action_flags |= MLX5_FLOW_ACTION_ENCAP;
7298 : 0 : break;
7299 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7300 : : case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7301 : 0 : ret = mlx5_hw_validate_action_l2_decap(dev, action, mask,
7302 : : attr, action_flags,
7303 : : error);
7304 [ # # ]: 0 : if (ret)
7305 : 0 : return ret;
7306 : 0 : action_flags |= MLX5_FLOW_ACTION_DECAP;
7307 : 0 : break;
7308 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7309 : : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7310 : 0 : ret = flow_hw_validate_action_raw_reformat(dev, action,
7311 : : mask, attr,
7312 : : &action_flags,
7313 : : error);
7314 [ # # ]: 0 : if (ret)
7315 : 0 : return ret;
7316 [ # # ]: 0 : if (action->type == RTE_FLOW_ACTION_TYPE_RAW_DECAP &&
7317 [ # # ]: 0 : (action + 1)->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7318 : 0 : action_flags |= MLX5_FLOW_XCAP_ACTIONS;
7319 : 0 : i++;
7320 : : }
7321 : : break;
7322 : 0 : case RTE_FLOW_ACTION_TYPE_IPV6_EXT_PUSH:
7323 : 0 : ret = flow_hw_validate_action_ipv6_ext_push(dev, action, error);
7324 [ # # ]: 0 : if (ret < 0)
7325 : 0 : return ret;
7326 : 0 : action_flags |= MLX5_FLOW_ACTION_IPV6_ROUTING_PUSH;
7327 : 0 : break;
7328 : 0 : case RTE_FLOW_ACTION_TYPE_IPV6_EXT_REMOVE:
7329 : 0 : remove_data = action->conf;
7330 : : /* Remove action must be shared. */
7331 [ # # # # ]: 0 : if (remove_data->type != IPPROTO_ROUTING || !mask) {
7332 : 0 : DRV_LOG(ERR, "Only supports shared IPv6 routing remove");
7333 : 0 : return -EINVAL;
7334 : : }
7335 : 0 : action_flags |= MLX5_FLOW_ACTION_IPV6_ROUTING_REMOVE;
7336 : 0 : break;
7337 : 0 : case RTE_FLOW_ACTION_TYPE_METER:
7338 : : /* TODO: Validation logic */
7339 : 0 : action_flags |= MLX5_FLOW_ACTION_METER;
7340 : 0 : break;
7341 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
7342 : 0 : ret = flow_hw_validate_action_meter_mark(dev, action, false, error);
7343 [ # # ]: 0 : if (ret < 0)
7344 : 0 : return ret;
7345 : 0 : action_flags |= MLX5_FLOW_ACTION_METER;
7346 : 0 : break;
7347 : 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
7348 : 0 : ret = flow_hw_validate_action_modify_field(dev, action, mask,
7349 : : error);
7350 [ # # ]: 0 : if (ret < 0)
7351 : 0 : return ret;
7352 : 0 : action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
7353 : 0 : break;
7354 : 0 : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
7355 : 0 : ret = flow_hw_validate_action_represented_port
7356 : : (dev, action, mask, error);
7357 [ # # ]: 0 : if (ret < 0)
7358 : 0 : return ret;
7359 : 0 : action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7360 : 0 : break;
7361 : 0 : case RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:
7362 : 0 : ret = flow_hw_validate_action_port_representor
7363 : : (dev, attr, action, mask, error);
7364 [ # # ]: 0 : if (ret < 0)
7365 : 0 : return ret;
7366 : 0 : action_flags |= MLX5_FLOW_ACTION_PORT_REPRESENTOR;
7367 : 0 : break;
7368 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
7369 [ # # # # ]: 0 : if (count_mask && count_mask->id)
7370 : 0 : fixed_cnt = true;
7371 : 0 : ret = flow_hw_validate_action_age(dev, action,
7372 : : action_flags,
7373 : : fixed_cnt, error);
7374 [ # # ]: 0 : if (ret < 0)
7375 : 0 : return ret;
7376 : 0 : action_flags |= MLX5_FLOW_ACTION_AGE;
7377 : 0 : break;
7378 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
7379 : 0 : ret = flow_hw_validate_action_count(dev, action, mask,
7380 : : action_flags,
7381 : : error);
7382 [ # # ]: 0 : if (ret < 0)
7383 : 0 : return ret;
7384 : 0 : count_mask = mask->conf;
7385 : 0 : action_flags |= MLX5_FLOW_ACTION_COUNT;
7386 : 0 : break;
7387 : 0 : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
7388 : 0 : ret = mlx5_hw_validate_action_conntrack(dev, action, mask,
7389 : : attr, action_flags,
7390 : : error);
7391 [ # # ]: 0 : if (ret)
7392 : 0 : return ret;
7393 : 0 : action_flags |= MLX5_FLOW_ACTION_CT;
7394 : 0 : break;
7395 : 0 : case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7396 : 0 : action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7397 : 0 : break;
7398 : 0 : case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7399 : 0 : action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7400 : 0 : break;
7401 : 0 : case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7402 : 0 : ret = flow_hw_validate_action_push_vlan
7403 : : (dev, attr, action, mask, error);
7404 [ # # ]: 0 : if (ret != 0)
7405 : 0 : return ret;
7406 : 0 : i += is_of_vlan_pcp_present(action) ?
7407 [ # # ]: 0 : MLX5_HW_VLAN_PUSH_PCP_IDX :
7408 : : MLX5_HW_VLAN_PUSH_VID_IDX;
7409 : 0 : action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7410 : 0 : break;
7411 : 0 : case RTE_FLOW_ACTION_TYPE_NAT64:
7412 : 0 : ret = flow_hw_validate_action_nat64(dev, attr, action, mask,
7413 : : action_flags, error);
7414 [ # # ]: 0 : if (ret != 0)
7415 : 0 : return ret;
7416 : 0 : action_flags |= MLX5_FLOW_ACTION_NAT64;
7417 : 0 : break;
7418 : 0 : case RTE_FLOW_ACTION_TYPE_END:
7419 : : actions_end = true;
7420 : 0 : break;
7421 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
7422 : 0 : ret = flow_hw_validate_action_default_miss(dev, attr,
7423 : : action_flags, error);
7424 [ # # ]: 0 : if (ret < 0)
7425 : 0 : return ret;
7426 : 0 : action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
7427 : 0 : break;
7428 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
7429 : 0 : ret = mlx5_flow_validate_action_jump_to_table_index(action, mask, error);
7430 [ # # ]: 0 : if (ret < 0)
7431 : 0 : return ret;
7432 : 0 : action_flags |= MLX5_FLOW_ACTION_JUMP_TO_TABLE_INDEX;
7433 : 0 : break;
7434 : 0 : default:
7435 : 0 : return rte_flow_error_set(error, ENOTSUP,
7436 : : RTE_FLOW_ERROR_TYPE_ACTION,
7437 : : action,
7438 : : "action not supported in template API");
7439 : : }
7440 : : }
7441 [ # # ]: 0 : if (act_flags != NULL)
7442 : 0 : *act_flags = action_flags;
7443 : : return 0;
7444 : : }
7445 : :
7446 : : static int
7447 : 0 : flow_hw_actions_validate(struct rte_eth_dev *dev,
7448 : : const struct rte_flow_actions_template_attr *attr,
7449 : : const struct rte_flow_action actions[],
7450 : : const struct rte_flow_action masks[],
7451 : : struct rte_flow_error *error)
7452 : : {
7453 : 0 : return mlx5_flow_hw_actions_validate(dev, attr, actions, masks, NULL, error);
7454 : : }
7455 : :
7456 : :
7457 : : static enum mlx5dr_action_type mlx5_hw_dr_action_types[] = {
7458 : : [RTE_FLOW_ACTION_TYPE_MARK] = MLX5DR_ACTION_TYP_TAG,
7459 : : [RTE_FLOW_ACTION_TYPE_FLAG] = MLX5DR_ACTION_TYP_TAG,
7460 : : [RTE_FLOW_ACTION_TYPE_DROP] = MLX5DR_ACTION_TYP_DROP,
7461 : : [RTE_FLOW_ACTION_TYPE_JUMP] = MLX5DR_ACTION_TYP_TBL,
7462 : : [RTE_FLOW_ACTION_TYPE_QUEUE] = MLX5DR_ACTION_TYP_TIR,
7463 : : [RTE_FLOW_ACTION_TYPE_RSS] = MLX5DR_ACTION_TYP_TIR,
7464 : : [RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP] = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2,
7465 : : [RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP] = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2,
7466 : : [RTE_FLOW_ACTION_TYPE_VXLAN_DECAP] = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2,
7467 : : [RTE_FLOW_ACTION_TYPE_NVGRE_DECAP] = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2,
7468 : : [RTE_FLOW_ACTION_TYPE_MODIFY_FIELD] = MLX5DR_ACTION_TYP_MODIFY_HDR,
7469 : : [RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT] = MLX5DR_ACTION_TYP_VPORT,
7470 : : [RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR] = MLX5DR_ACTION_TYP_MISS,
7471 : : [RTE_FLOW_ACTION_TYPE_CONNTRACK] = MLX5DR_ACTION_TYP_ASO_CT,
7472 : : [RTE_FLOW_ACTION_TYPE_OF_POP_VLAN] = MLX5DR_ACTION_TYP_POP_VLAN,
7473 : : [RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN] = MLX5DR_ACTION_TYP_PUSH_VLAN,
7474 : : [RTE_FLOW_ACTION_TYPE_SEND_TO_KERNEL] = MLX5DR_ACTION_TYP_DEST_ROOT,
7475 : : [RTE_FLOW_ACTION_TYPE_IPV6_EXT_PUSH] = MLX5DR_ACTION_TYP_PUSH_IPV6_ROUTE_EXT,
7476 : : [RTE_FLOW_ACTION_TYPE_IPV6_EXT_REMOVE] = MLX5DR_ACTION_TYP_POP_IPV6_ROUTE_EXT,
7477 : : [RTE_FLOW_ACTION_TYPE_NAT64] = MLX5DR_ACTION_TYP_NAT64,
7478 : : [RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX] = MLX5DR_ACTION_TYP_JUMP_TO_MATCHER,
7479 : : };
7480 : :
7481 : : static inline void
7482 : : action_template_set_type(struct rte_flow_actions_template *at,
7483 : : enum mlx5dr_action_type *action_types,
7484 : : unsigned int action_src, uint16_t *curr_off,
7485 : : enum mlx5dr_action_type type)
7486 : : {
7487 : 0 : at->dr_off[action_src] = *curr_off;
7488 : 0 : action_types[*curr_off] = type;
7489 : 0 : *curr_off = *curr_off + 1;
7490 : 0 : }
7491 : :
7492 : : static int
7493 : 0 : flow_hw_dr_actions_template_handle_shared(int type, uint32_t action_src,
7494 : : enum mlx5dr_action_type *action_types,
7495 : : uint16_t *curr_off, uint16_t *cnt_off,
7496 : : struct rte_flow_actions_template *at)
7497 : : {
7498 [ # # # # : 0 : switch (type) {
# ]
7499 : : case RTE_FLOW_ACTION_TYPE_RSS:
7500 : : action_template_set_type(at, action_types, action_src, curr_off,
7501 : : MLX5DR_ACTION_TYP_TIR);
7502 : : break;
7503 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
7504 : : case RTE_FLOW_ACTION_TYPE_COUNT:
7505 : : /*
7506 : : * Both AGE and COUNT action need counter, the first one fills
7507 : : * the action_types array, and the second only saves the offset.
7508 : : */
7509 [ # # ]: 0 : if (*cnt_off == UINT16_MAX) {
7510 : 0 : *cnt_off = *curr_off;
7511 : : action_template_set_type(at, action_types,
7512 : : action_src, curr_off,
7513 : : MLX5DR_ACTION_TYP_CTR);
7514 : : }
7515 : 0 : at->dr_off[action_src] = *cnt_off;
7516 : 0 : break;
7517 : : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
7518 : : action_template_set_type(at, action_types, action_src, curr_off,
7519 : : MLX5DR_ACTION_TYP_ASO_CT);
7520 : : break;
7521 : : case RTE_FLOW_ACTION_TYPE_QUOTA:
7522 : : case RTE_FLOW_ACTION_TYPE_METER_MARK:
7523 : : action_template_set_type(at, action_types, action_src, curr_off,
7524 : : MLX5DR_ACTION_TYP_ASO_METER);
7525 : : break;
7526 : 0 : default:
7527 : 0 : DRV_LOG(WARNING, "Unsupported shared action type: %d", type);
7528 : 0 : return -EINVAL;
7529 : : }
7530 : : return 0;
7531 : : }
7532 : :
7533 : :
7534 : : static int
7535 : 0 : flow_hw_template_actions_list(struct rte_flow_actions_template *at,
7536 : : unsigned int action_src,
7537 : : enum mlx5dr_action_type *action_types,
7538 : : uint16_t *curr_off, uint16_t *cnt_off)
7539 : : {
7540 : : int ret;
7541 : 0 : const struct rte_flow_action_indirect_list *indlst_conf = at->actions[action_src].conf;
7542 [ # # # # ]: 0 : enum mlx5_indirect_list_type list_type = mlx5_get_indirect_list_type(indlst_conf->handle);
7543 : : const union {
7544 : : struct mlx5_indlst_legacy *legacy;
7545 : : struct rte_flow_action_list_handle *handle;
7546 : : } indlst_obj = { .handle = indlst_conf->handle };
7547 : : enum mlx5dr_action_type type;
7548 : :
7549 [ # # # # ]: 0 : switch (list_type) {
7550 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY:
7551 : 0 : ret = flow_hw_dr_actions_template_handle_shared
7552 : 0 : (indlst_obj.legacy->legacy_type, action_src,
7553 : : action_types, curr_off, cnt_off, at);
7554 [ # # ]: 0 : if (ret)
7555 : 0 : return ret;
7556 : : break;
7557 : : case MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR:
7558 : : action_template_set_type(at, action_types, action_src, curr_off,
7559 : : MLX5DR_ACTION_TYP_DEST_ARRAY);
7560 : : break;
7561 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT:
7562 : 0 : type = ((struct mlx5_hw_encap_decap_action *)
7563 : : (indlst_conf->handle))->action_type;
7564 : : action_template_set_type(at, action_types, action_src, curr_off, type);
7565 : : break;
7566 : 0 : default:
7567 : 0 : DRV_LOG(ERR, "Unsupported indirect list type");
7568 : 0 : return -EINVAL;
7569 : : }
7570 : : return 0;
7571 : : }
7572 : :
7573 : : /**
7574 : : * Create DR action template based on a provided sequence of flow actions.
7575 : : *
7576 : : * @param[in] dev
7577 : : * Pointer to the rte_eth_dev structure.
7578 : : * @param[in] at
7579 : : * Pointer to flow actions template to be updated.
7580 : : * @param[out] action_types
7581 : : * Action types array to be filled.
7582 : : * @param[out] tmpl_flags
7583 : : * Template DR flags to be filled.
7584 : : *
7585 : : * @return
7586 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
7587 : : */
7588 : : static int
7589 : 0 : flow_hw_parse_flow_actions_to_dr_actions(struct rte_eth_dev *dev,
7590 : : struct rte_flow_actions_template *at,
7591 : : enum mlx5dr_action_type action_types[MLX5_HW_MAX_ACTS],
7592 : : uint32_t *tmpl_flags __rte_unused)
7593 : : {
7594 : : unsigned int i;
7595 : : uint16_t curr_off;
7596 : : enum mlx5dr_action_type reformat_act_type = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2;
7597 : : uint16_t reformat_off = UINT16_MAX;
7598 : : uint16_t mhdr_off = UINT16_MAX;
7599 : : uint16_t recom_off = UINT16_MAX;
7600 : 0 : uint16_t cnt_off = UINT16_MAX;
7601 : : enum mlx5dr_action_type recom_type = MLX5DR_ACTION_TYP_LAST;
7602 : : int ret;
7603 : :
7604 [ # # ]: 0 : for (i = 0, curr_off = 0; at->actions[i].type != RTE_FLOW_ACTION_TYPE_END; ++i) {
7605 : : const struct rte_flow_action_raw_encap *raw_encap_data;
7606 : : size_t data_size;
7607 : : enum mlx5dr_action_type type;
7608 : :
7609 [ # # ]: 0 : if (curr_off >= MLX5_HW_MAX_ACTS)
7610 : 0 : goto err_actions_num;
7611 [ # # # # : 0 : switch ((int)at->actions[i].type) {
# # # # #
# # # # #
# # ]
7612 : : case RTE_FLOW_ACTION_TYPE_VOID:
7613 : : break;
7614 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT_LIST:
7615 : 0 : ret = flow_hw_template_actions_list(at, i, action_types,
7616 : : &curr_off, &cnt_off);
7617 [ # # ]: 0 : if (ret)
7618 : 0 : return ret;
7619 : : break;
7620 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT:
7621 : 0 : ret = flow_hw_dr_actions_template_handle_shared
7622 : 0 : (at->masks[i].type, i, action_types,
7623 : : &curr_off, &cnt_off, at);
7624 [ # # ]: 0 : if (ret)
7625 : 0 : return ret;
7626 : : break;
7627 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7628 : : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7629 : : case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7630 : : case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7631 : : MLX5_ASSERT(reformat_off == UINT16_MAX);
7632 : 0 : reformat_off = curr_off++;
7633 : 0 : reformat_act_type = mlx5_hw_dr_action_types[at->actions[i].type];
7634 : 0 : break;
7635 : 0 : case RTE_FLOW_ACTION_TYPE_IPV6_EXT_PUSH:
7636 : : MLX5_ASSERT(recom_off == UINT16_MAX);
7637 : : recom_type = MLX5DR_ACTION_TYP_PUSH_IPV6_ROUTE_EXT;
7638 : 0 : recom_off = curr_off++;
7639 : 0 : break;
7640 : 0 : case RTE_FLOW_ACTION_TYPE_IPV6_EXT_REMOVE:
7641 : : MLX5_ASSERT(recom_off == UINT16_MAX);
7642 : : recom_type = MLX5DR_ACTION_TYP_POP_IPV6_ROUTE_EXT;
7643 : 0 : recom_off = curr_off++;
7644 : 0 : break;
7645 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7646 : 0 : raw_encap_data = at->actions[i].conf;
7647 : 0 : data_size = raw_encap_data->size;
7648 [ # # ]: 0 : if (reformat_off != UINT16_MAX) {
7649 : : reformat_act_type = data_size < MLX5_ENCAPSULATION_DECISION_SIZE ?
7650 [ # # ]: 0 : MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2 :
7651 : : MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3;
7652 : : } else {
7653 : 0 : reformat_off = curr_off++;
7654 : : reformat_act_type = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;
7655 : : }
7656 : : break;
7657 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7658 : 0 : reformat_off = curr_off++;
7659 : : reformat_act_type = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2;
7660 : 0 : break;
7661 : 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
7662 [ # # ]: 0 : if (mhdr_off == UINT16_MAX) {
7663 : 0 : mhdr_off = curr_off++;
7664 : 0 : type = mlx5_hw_dr_action_types[at->actions[i].type];
7665 : 0 : action_types[mhdr_off] = type;
7666 : : }
7667 : : break;
7668 : 0 : case RTE_FLOW_ACTION_TYPE_METER:
7669 : 0 : at->dr_off[i] = curr_off;
7670 : 0 : action_types[curr_off++] = MLX5DR_ACTION_TYP_ASO_METER;
7671 [ # # ]: 0 : if (curr_off >= MLX5_HW_MAX_ACTS)
7672 : 0 : goto err_actions_num;
7673 : 0 : action_types[curr_off++] = MLX5DR_ACTION_TYP_TBL;
7674 : 0 : break;
7675 : 0 : case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7676 : 0 : type = mlx5_hw_dr_action_types[at->actions[i].type];
7677 : 0 : at->dr_off[i] = curr_off;
7678 : 0 : action_types[curr_off++] = type;
7679 : 0 : i += is_of_vlan_pcp_present(at->actions + i) ?
7680 [ # # ]: 0 : MLX5_HW_VLAN_PUSH_PCP_IDX :
7681 : : MLX5_HW_VLAN_PUSH_VID_IDX;
7682 : 0 : break;
7683 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
7684 : 0 : at->dr_off[i] = curr_off;
7685 : 0 : action_types[curr_off++] = MLX5DR_ACTION_TYP_ASO_METER;
7686 [ # # ]: 0 : if (curr_off >= MLX5_HW_MAX_ACTS)
7687 : 0 : goto err_actions_num;
7688 : : break;
7689 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
7690 : : case RTE_FLOW_ACTION_TYPE_COUNT:
7691 : : /*
7692 : : * Both AGE and COUNT action need counter, the first
7693 : : * one fills the action_types array, and the second only
7694 : : * saves the offset.
7695 : : */
7696 [ # # ]: 0 : if (cnt_off == UINT16_MAX) {
7697 : 0 : cnt_off = curr_off++;
7698 : 0 : action_types[cnt_off] = MLX5DR_ACTION_TYP_CTR;
7699 : : }
7700 : 0 : at->dr_off[i] = cnt_off;
7701 : 0 : break;
7702 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
7703 : 0 : at->dr_off[i] = curr_off;
7704 : 0 : action_types[curr_off++] = MLX5DR_ACTION_TYP_MISS;
7705 : 0 : break;
7706 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
7707 : 0 : *tmpl_flags |= MLX5DR_ACTION_TEMPLATE_FLAG_RELAXED_ORDER;
7708 : 0 : at->dr_off[i] = curr_off;
7709 : 0 : action_types[curr_off++] = MLX5DR_ACTION_TYP_JUMP_TO_MATCHER;
7710 : 0 : break;
7711 : 0 : default:
7712 : 0 : type = mlx5_hw_dr_action_types[at->actions[i].type];
7713 : 0 : at->dr_off[i] = curr_off;
7714 : 0 : action_types[curr_off++] = type;
7715 : 0 : break;
7716 : : }
7717 : : }
7718 [ # # ]: 0 : if (curr_off >= MLX5_HW_MAX_ACTS)
7719 : 0 : goto err_actions_num;
7720 [ # # ]: 0 : if (mhdr_off != UINT16_MAX)
7721 : 0 : at->mhdr_off = mhdr_off;
7722 [ # # ]: 0 : if (reformat_off != UINT16_MAX) {
7723 : 0 : at->reformat_off = reformat_off;
7724 : 0 : action_types[reformat_off] = reformat_act_type;
7725 : : }
7726 [ # # ]: 0 : if (recom_off != UINT16_MAX) {
7727 : 0 : at->recom_off = recom_off;
7728 : 0 : action_types[recom_off] = recom_type;
7729 : : }
7730 : 0 : at->dr_actions_num = curr_off;
7731 : :
7732 : : /* Create srh flex parser for remove anchor. */
7733 [ # # ]: 0 : if ((recom_type == MLX5DR_ACTION_TYP_POP_IPV6_ROUTE_EXT ||
7734 [ # # ]: 0 : recom_type == MLX5DR_ACTION_TYP_PUSH_IPV6_ROUTE_EXT) &&
7735 : 0 : (ret = mlx5_alloc_srh_flex_parser(dev))) {
7736 : 0 : DRV_LOG(ERR, "Failed to create srv6 flex parser");
7737 : 0 : return ret;
7738 : : }
7739 : : return 0;
7740 : 0 : err_actions_num:
7741 : 0 : DRV_LOG(ERR, "Number of HW actions (%u) exceeded maximum (%u) allowed in template",
7742 : : curr_off, MLX5_HW_MAX_ACTS);
7743 : 0 : return -EINVAL;
7744 : : }
7745 : :
7746 : : static int
7747 : 0 : flow_hw_set_vlan_vid(struct rte_eth_dev *dev,
7748 : : struct rte_flow_action *ra,
7749 : : struct rte_flow_action *rm,
7750 : : struct rte_flow_action_modify_field *spec,
7751 : : struct rte_flow_action_modify_field *mask,
7752 : : int set_vlan_vid_ix,
7753 : : struct rte_flow_error *error)
7754 : : {
7755 [ # # ]: 0 : const bool masked = rm[set_vlan_vid_ix].conf &&
7756 : : (((const struct rte_flow_action_of_set_vlan_vid *)
7757 [ # # ]: 0 : rm[set_vlan_vid_ix].conf)->vlan_vid != 0);
7758 : 0 : const struct rte_flow_action_of_set_vlan_vid *conf =
7759 : 0 : ra[set_vlan_vid_ix].conf;
7760 : 0 : int width = mlx5_flow_item_field_width(dev, RTE_FLOW_FIELD_VLAN_ID, 0,
7761 : : NULL, error);
7762 : : MLX5_ASSERT(width);
7763 : 0 : *spec = (typeof(*spec)) {
7764 : : .operation = RTE_FLOW_MODIFY_SET,
7765 : : .dst = {
7766 : : .field = RTE_FLOW_FIELD_VLAN_ID,
7767 : : .level = 0, .offset = 0,
7768 : : },
7769 : : .src = {
7770 : : .field = RTE_FLOW_FIELD_VALUE,
7771 : : },
7772 : : .width = width,
7773 : : };
7774 : 0 : *mask = (typeof(*mask)) {
7775 : : .operation = RTE_FLOW_MODIFY_SET,
7776 : : .dst = {
7777 : : .field = RTE_FLOW_FIELD_VLAN_ID,
7778 : : .level = 0xff, .offset = 0xffffffff,
7779 : : },
7780 : : .src = {
7781 : : .field = RTE_FLOW_FIELD_VALUE,
7782 : : },
7783 : : .width = 0xffffffff,
7784 : : };
7785 [ # # ]: 0 : if (masked) {
7786 : 0 : uint32_t mask_val = 0xffffffff;
7787 : :
7788 [ # # ]: 0 : rte_memcpy(spec->src.value, &conf->vlan_vid, sizeof(conf->vlan_vid));
7789 [ # # ]: 0 : rte_memcpy(mask->src.value, &mask_val, sizeof(mask_val));
7790 : : }
7791 : 0 : ra[set_vlan_vid_ix].type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD;
7792 : 0 : ra[set_vlan_vid_ix].conf = spec;
7793 : 0 : rm[set_vlan_vid_ix].type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD;
7794 : 0 : rm[set_vlan_vid_ix].conf = mask;
7795 : 0 : return 0;
7796 : : }
7797 : :
7798 : : static __rte_always_inline int
7799 : : flow_hw_set_vlan_vid_construct(struct rte_eth_dev *dev,
7800 : : struct mlx5_modification_cmd *mhdr_cmd,
7801 : : struct mlx5_action_construct_data *act_data,
7802 : : const struct mlx5_hw_actions *hw_acts,
7803 : : const struct rte_flow_action *action)
7804 : : {
7805 : : struct rte_flow_error error;
7806 : 0 : rte_be16_t vid = ((const struct rte_flow_action_of_set_vlan_vid *)
7807 : 0 : action->conf)->vlan_vid;
7808 : 0 : int width = mlx5_flow_item_field_width(dev, RTE_FLOW_FIELD_VLAN_ID, 0,
7809 : : NULL, &error);
7810 [ # # # # : 0 : struct rte_flow_action_modify_field conf = {
# # # # #
# ]
7811 : : .operation = RTE_FLOW_MODIFY_SET,
7812 : : .dst = {
7813 : : .field = RTE_FLOW_FIELD_VLAN_ID,
7814 : : .level = 0, .offset = 0,
7815 : : },
7816 : : .src = {
7817 : : .field = RTE_FLOW_FIELD_VALUE,
7818 : : },
7819 : : .width = width,
7820 : : };
7821 : : struct rte_flow_action modify_action = {
7822 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
7823 : : .conf = &conf
7824 : : };
7825 : :
7826 : : rte_memcpy(conf.src.value, &vid, sizeof(vid));
7827 : : return flow_hw_modify_field_construct(mhdr_cmd, act_data, hw_acts, &modify_action);
7828 : : }
7829 : :
7830 : : static int
7831 : 0 : flow_hw_flex_item_acquire(struct rte_eth_dev *dev,
7832 : : struct rte_flow_item_flex_handle *handle,
7833 : : uint8_t *flex_item)
7834 : : {
7835 : 0 : int index = mlx5_flex_acquire_index(dev, handle, false);
7836 : :
7837 : : MLX5_ASSERT(index >= 0 && index < (int)(sizeof(uint32_t) * CHAR_BIT));
7838 [ # # ]: 0 : if (index < 0)
7839 : : return -1;
7840 [ # # ]: 0 : if (!(*flex_item & RTE_BIT32(index))) {
7841 : : /* Don't count same flex item again. */
7842 : 0 : if (mlx5_flex_acquire_index(dev, handle, true) != index)
7843 : : MLX5_ASSERT(false);
7844 : 0 : *flex_item |= (uint8_t)RTE_BIT32(index);
7845 : : }
7846 : : return 0;
7847 : : }
7848 : :
7849 : : static void
7850 : 0 : flow_hw_flex_item_release(struct rte_eth_dev *dev, uint8_t *flex_item)
7851 : : {
7852 [ # # ]: 0 : while (*flex_item) {
7853 : 0 : int index = rte_bsf32(*flex_item);
7854 : :
7855 : 0 : mlx5_flex_release_index(dev, index);
7856 : 0 : *flex_item &= ~(uint8_t)RTE_BIT32(index);
7857 : : }
7858 : 0 : }
7859 : : static __rte_always_inline void
7860 : : flow_hw_actions_template_replace_container(const
7861 : : struct rte_flow_action *actions,
7862 : : const
7863 : : struct rte_flow_action *masks,
7864 : : struct rte_flow_action *new_actions,
7865 : : struct rte_flow_action *new_masks,
7866 : : struct rte_flow_action **ra,
7867 : : struct rte_flow_action **rm,
7868 : : uint32_t act_num)
7869 : : {
7870 : 0 : memcpy(new_actions, actions, sizeof(actions[0]) * act_num);
7871 : : memcpy(new_masks, masks, sizeof(masks[0]) * act_num);
7872 : : *ra = (void *)(uintptr_t)new_actions;
7873 : : *rm = (void *)(uintptr_t)new_masks;
7874 : 0 : }
7875 : :
7876 : : /* Action template copies these actions in rte_flow_conv() */
7877 : :
7878 : : static const struct rte_flow_action rx_meta_copy_action = {
7879 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
7880 : : .conf = &(struct rte_flow_action_modify_field){
7881 : : .operation = RTE_FLOW_MODIFY_SET,
7882 : : .dst = {
7883 : : .field = (enum rte_flow_field_id)
7884 : : MLX5_RTE_FLOW_FIELD_META_REG,
7885 : : .tag_index = REG_B,
7886 : : },
7887 : : .src = {
7888 : : .field = (enum rte_flow_field_id)
7889 : : MLX5_RTE_FLOW_FIELD_META_REG,
7890 : : .tag_index = REG_C_1,
7891 : : },
7892 : : .width = 32,
7893 : : }
7894 : : };
7895 : :
7896 : : static const struct rte_flow_action rx_meta_copy_mask = {
7897 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
7898 : : .conf = &(struct rte_flow_action_modify_field){
7899 : : .operation = RTE_FLOW_MODIFY_SET,
7900 : : .dst = {
7901 : : .field = (enum rte_flow_field_id)
7902 : : MLX5_RTE_FLOW_FIELD_META_REG,
7903 : : .level = UINT8_MAX,
7904 : : .tag_index = UINT8_MAX,
7905 : : .offset = UINT32_MAX,
7906 : : },
7907 : : .src = {
7908 : : .field = (enum rte_flow_field_id)
7909 : : MLX5_RTE_FLOW_FIELD_META_REG,
7910 : : .level = UINT8_MAX,
7911 : : .tag_index = UINT8_MAX,
7912 : : .offset = UINT32_MAX,
7913 : : },
7914 : : .width = UINT32_MAX,
7915 : : }
7916 : : };
7917 : :
7918 : : static const struct rte_flow_action quota_color_inc_action = {
7919 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
7920 : : .conf = &(struct rte_flow_action_modify_field) {
7921 : : .operation = RTE_FLOW_MODIFY_ADD,
7922 : : .dst = {
7923 : : .field = RTE_FLOW_FIELD_METER_COLOR,
7924 : : .level = 0, .offset = 0
7925 : : },
7926 : : .src = {
7927 : : .field = RTE_FLOW_FIELD_VALUE,
7928 : : .level = 1,
7929 : : .offset = 0,
7930 : : },
7931 : : .width = 2
7932 : : }
7933 : : };
7934 : :
7935 : : static const struct rte_flow_action quota_color_inc_mask = {
7936 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
7937 : : .conf = &(struct rte_flow_action_modify_field) {
7938 : : .operation = RTE_FLOW_MODIFY_ADD,
7939 : : .dst = {
7940 : : .field = RTE_FLOW_FIELD_METER_COLOR,
7941 : : .level = UINT8_MAX,
7942 : : .tag_index = UINT8_MAX,
7943 : : .offset = UINT32_MAX,
7944 : : },
7945 : : .src = {
7946 : : .field = RTE_FLOW_FIELD_VALUE,
7947 : : .level = 3,
7948 : : .offset = 0
7949 : : },
7950 : : .width = UINT32_MAX
7951 : : }
7952 : : };
7953 : :
7954 : : /**
7955 : : * Create flow action template.
7956 : : *
7957 : : * @param[in] dev
7958 : : * Pointer to the rte_eth_dev structure.
7959 : : * @param[in] attr
7960 : : * Pointer to the action template attributes.
7961 : : * @param[in] actions
7962 : : * Associated actions (list terminated by the END action).
7963 : : * @param[in] masks
7964 : : * List of actions that marks which of the action's member is constant.
7965 : : * @param[in] nt_mode
7966 : : * Non template mode.
7967 : : * @param[out] error
7968 : : * Pointer to error structure.
7969 : : *
7970 : : * @return
7971 : : * Action template pointer on success, NULL otherwise and rte_errno is set.
7972 : : */
7973 : : static struct rte_flow_actions_template *
7974 : 0 : __flow_hw_actions_template_create(struct rte_eth_dev *dev,
7975 : : const struct rte_flow_actions_template_attr *attr,
7976 : : const struct rte_flow_action actions[],
7977 : : const struct rte_flow_action masks[],
7978 : : bool nt_mode,
7979 : : struct rte_flow_error *error)
7980 : : {
7981 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
7982 : : int len, act_len, mask_len;
7983 : : int orig_act_len;
7984 : : unsigned int act_num;
7985 : : unsigned int i;
7986 : : struct rte_flow_actions_template *at = NULL;
7987 : : uint16_t pos;
7988 : 0 : uint64_t action_flags = 0;
7989 : : struct rte_flow_action tmp_action[MLX5_HW_MAX_ACTS];
7990 : : struct rte_flow_action tmp_mask[MLX5_HW_MAX_ACTS];
7991 : : struct rte_flow_action *ra = (void *)(uintptr_t)actions;
7992 : : struct rte_flow_action *rm = (void *)(uintptr_t)masks;
7993 : : int set_vlan_vid_ix = -1;
7994 : 0 : struct rte_flow_action_modify_field set_vlan_vid_spec = {0, };
7995 : 0 : struct rte_flow_action_modify_field set_vlan_vid_mask = {0, };
7996 : : struct rte_flow_action mf_actions[MLX5_HW_MAX_ACTS];
7997 : : struct rte_flow_action mf_masks[MLX5_HW_MAX_ACTS];
7998 : : uint32_t expand_mf_num = 0;
7999 : 0 : uint16_t src_off[MLX5_HW_MAX_ACTS] = {0, };
8000 : 0 : enum mlx5dr_action_type action_types[MLX5_HW_MAX_ACTS] = { MLX5DR_ACTION_TYP_LAST };
8001 : 0 : uint32_t tmpl_flags = 0;
8002 : : int ret;
8003 : :
8004 [ # # # # ]: 0 : if (!nt_mode && mlx5_flow_hw_actions_validate(dev, attr, actions, masks,
8005 : : &action_flags, error))
8006 : : return NULL;
8007 [ # # ]: 0 : for (i = 0; ra[i].type != RTE_FLOW_ACTION_TYPE_END; ++i) {
8008 [ # # # ]: 0 : switch (ra[i].type) {
8009 : : /* OF_PUSH_VLAN *MUST* come before OF_SET_VLAN_VID */
8010 : 0 : case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
8011 : 0 : i += is_of_vlan_pcp_present(ra + i) ?
8012 [ # # ]: 0 : MLX5_HW_VLAN_PUSH_PCP_IDX :
8013 : : MLX5_HW_VLAN_PUSH_VID_IDX;
8014 : 0 : break;
8015 : 0 : case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
8016 : 0 : set_vlan_vid_ix = i;
8017 : 0 : break;
8018 : : default:
8019 : : break;
8020 : : }
8021 : : }
8022 : : /*
8023 : : * Count flow actions to allocate required space for storing DR offsets and to check
8024 : : * if temporary buffer would not be overrun.
8025 : : */
8026 : 0 : act_num = i + 1;
8027 [ # # ]: 0 : if (act_num >= MLX5_HW_MAX_ACTS) {
8028 : 0 : rte_flow_error_set(error, EINVAL,
8029 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL, "Too many actions");
8030 : 0 : return NULL;
8031 : : }
8032 [ # # ]: 0 : if (set_vlan_vid_ix != -1) {
8033 : : /* If temporary action buffer was not used, copy template actions to it */
8034 : : if (ra == actions)
8035 : : flow_hw_actions_template_replace_container(actions,
8036 : : masks,
8037 : : tmp_action,
8038 : : tmp_mask,
8039 : : &ra, &rm,
8040 : : act_num);
8041 : 0 : ret = flow_hw_set_vlan_vid(dev, ra, rm,
8042 : : &set_vlan_vid_spec, &set_vlan_vid_mask,
8043 : : set_vlan_vid_ix, error);
8044 [ # # ]: 0 : if (ret)
8045 : 0 : goto error;
8046 : 0 : action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
8047 : : }
8048 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_QUOTA) {
8049 : 0 : mf_actions[expand_mf_num] = quota_color_inc_action;
8050 : 0 : mf_masks[expand_mf_num] = quota_color_inc_mask;
8051 : : expand_mf_num++;
8052 : : }
8053 [ # # ]: 0 : if (priv->sh->config.dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS &&
8054 : 0 : priv->sh->config.dv_esw_en &&
8055 [ # # ]: 0 : !attr->transfer &&
8056 [ # # ]: 0 : (action_flags & (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS))) {
8057 : : /* Insert META copy */
8058 : 0 : mf_actions[expand_mf_num] = rx_meta_copy_action;
8059 : 0 : mf_masks[expand_mf_num] = rx_meta_copy_mask;
8060 : 0 : expand_mf_num++;
8061 : : }
8062 [ # # ]: 0 : if (expand_mf_num) {
8063 [ # # ]: 0 : if (act_num + expand_mf_num > MLX5_HW_MAX_ACTS) {
8064 : 0 : rte_flow_error_set(error, E2BIG,
8065 : : RTE_FLOW_ERROR_TYPE_ACTION,
8066 : : NULL, "cannot expand: too many actions");
8067 : 0 : return NULL;
8068 : : }
8069 [ # # ]: 0 : if (ra == actions)
8070 : : flow_hw_actions_template_replace_container(actions,
8071 : : masks,
8072 : : tmp_action,
8073 : : tmp_mask,
8074 : : &ra, &rm,
8075 : : act_num);
8076 : : /* Application should make sure only one Q/RSS exist in one rule. */
8077 : 0 : pos = flow_hw_template_expand_modify_field(ra, rm,
8078 : : mf_actions,
8079 : : mf_masks,
8080 : : action_flags,
8081 : : act_num,
8082 : : expand_mf_num);
8083 [ # # ]: 0 : if (pos == MLX5_HW_EXPAND_MH_FAILED) {
8084 : 0 : rte_flow_error_set(error, ENOMEM,
8085 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8086 : : NULL, "modify header expansion failed");
8087 : 0 : return NULL;
8088 : : }
8089 : : act_num += expand_mf_num;
8090 [ # # ]: 0 : for (i = pos + expand_mf_num; i < act_num; i++)
8091 : 0 : src_off[i] += expand_mf_num;
8092 : 0 : action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
8093 : : }
8094 : 0 : act_len = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, NULL, 0, ra, error);
8095 [ # # ]: 0 : if (act_len <= 0)
8096 : : return NULL;
8097 : 0 : len = RTE_ALIGN(act_len, 16);
8098 : 0 : mask_len = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, NULL, 0, rm, error);
8099 [ # # ]: 0 : if (mask_len <= 0)
8100 : : return NULL;
8101 : 0 : len += RTE_ALIGN(mask_len, 16);
8102 : 0 : len += RTE_ALIGN(act_num * sizeof(*at->dr_off), 16);
8103 : 0 : len += RTE_ALIGN(act_num * sizeof(*at->src_off), 16);
8104 : 0 : orig_act_len = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, NULL, 0, actions, error);
8105 [ # # ]: 0 : if (orig_act_len <= 0)
8106 : : return NULL;
8107 : 0 : len += RTE_ALIGN(orig_act_len, 16);
8108 : 0 : at = mlx5_malloc(MLX5_MEM_ZERO, len + sizeof(*at),
8109 : 0 : RTE_CACHE_LINE_SIZE, rte_socket_id());
8110 [ # # ]: 0 : if (!at) {
8111 : 0 : rte_flow_error_set(error, ENOMEM,
8112 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8113 : : NULL,
8114 : : "cannot allocate action template");
8115 : 0 : return NULL;
8116 : : }
8117 : : /* Actions part is in the first part. */
8118 : 0 : at->attr = *attr;
8119 : 0 : at->actions = (struct rte_flow_action *)(at + 1);
8120 : 0 : act_len = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, at->actions,
8121 : : len, ra, error);
8122 [ # # ]: 0 : if (act_len <= 0)
8123 : 0 : goto error;
8124 : : /* Masks part is in the second part. */
8125 : 0 : at->masks = (struct rte_flow_action *)(((uint8_t *)at->actions) + act_len);
8126 : 0 : mask_len = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, at->masks,
8127 : 0 : len - act_len, rm, error);
8128 [ # # ]: 0 : if (mask_len <= 0)
8129 : 0 : goto error;
8130 : : /* DR actions offsets in the third part. */
8131 : 0 : at->dr_off = (uint16_t *)((uint8_t *)at->masks + mask_len);
8132 : 0 : at->src_off = RTE_PTR_ADD(at->dr_off,
8133 : : RTE_ALIGN(act_num * sizeof(*at->dr_off), 16));
8134 : : memcpy(at->src_off, src_off, act_num * sizeof(at->src_off[0]));
8135 : 0 : at->orig_actions = RTE_PTR_ADD(at->src_off,
8136 : : RTE_ALIGN(act_num * sizeof(*at->src_off), 16));
8137 : 0 : orig_act_len = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, at->orig_actions, orig_act_len,
8138 : : actions, error);
8139 [ # # ]: 0 : if (orig_act_len <= 0)
8140 : 0 : goto error;
8141 : 0 : at->actions_num = act_num;
8142 [ # # ]: 0 : for (i = 0; i < at->actions_num; ++i)
8143 : 0 : at->dr_off[i] = UINT16_MAX;
8144 : 0 : at->reformat_off = UINT16_MAX;
8145 : 0 : at->mhdr_off = UINT16_MAX;
8146 : 0 : at->recom_off = UINT16_MAX;
8147 [ # # ]: 0 : for (i = 0; actions->type != RTE_FLOW_ACTION_TYPE_END;
8148 : 0 : actions++, masks++, i++) {
8149 : : const struct rte_flow_action_modify_field *info;
8150 : :
8151 [ # # # ]: 0 : switch (actions->type) {
8152 : : /*
8153 : : * mlx5 PMD hacks indirect action index directly to the action conf.
8154 : : * The rte_flow_conv() function copies the content from conf pointer.
8155 : : * Need to restore the indirect action index from action conf here.
8156 : : */
8157 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT:
8158 : 0 : at->actions[i].conf = ra[i].conf;
8159 : 0 : at->masks[i].conf = rm[i].conf;
8160 : 0 : break;
8161 : 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
8162 : 0 : info = actions->conf;
8163 [ # # # # ]: 0 : if ((info->dst.field == RTE_FLOW_FIELD_FLEX_ITEM &&
8164 : 0 : flow_hw_flex_item_acquire(dev, info->dst.flex_handle,
8165 : 0 : &at->flex_item)) ||
8166 [ # # # # ]: 0 : (info->src.field == RTE_FLOW_FIELD_FLEX_ITEM &&
8167 : 0 : flow_hw_flex_item_acquire(dev, info->src.flex_handle,
8168 : : &at->flex_item)))
8169 : 0 : goto error;
8170 : : break;
8171 : : default:
8172 : : break;
8173 : : }
8174 : : }
8175 : 0 : ret = flow_hw_parse_flow_actions_to_dr_actions(dev, at, action_types, &tmpl_flags);
8176 [ # # ]: 0 : if (ret)
8177 : 0 : goto error;
8178 : 0 : at->action_flags = action_flags;
8179 : : /* In non template mode there is no need to create the dr template. */
8180 [ # # ]: 0 : if (nt_mode)
8181 : : return at;
8182 : 0 : at->tmpl = mlx5dr_action_template_create(action_types, tmpl_flags);
8183 [ # # ]: 0 : if (!at->tmpl) {
8184 : 0 : DRV_LOG(ERR, "Failed to create DR action template: %d", rte_errno);
8185 : 0 : goto error;
8186 : : }
8187 : 0 : rte_atomic_fetch_add_explicit(&at->refcnt, 1, rte_memory_order_relaxed);
8188 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->flow_hw_at, at, next);
8189 : 0 : return at;
8190 : 0 : error:
8191 : : if (at) {
8192 : 0 : mlx5_free(at);
8193 : : }
8194 : 0 : rte_flow_error_set(error, rte_errno,
8195 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8196 : : "Failed to create action template");
8197 : 0 : return NULL;
8198 : : }
8199 : :
8200 : : /**
8201 : : * Create flow action template.
8202 : : *
8203 : : * @param[in] dev
8204 : : * Pointer to the rte_eth_dev structure.
8205 : : * @param[in] attr
8206 : : * Pointer to the action template attributes.
8207 : : * @param[in] actions
8208 : : * Associated actions (list terminated by the END action).
8209 : : * @param[in] masks
8210 : : * List of actions that marks which of the action's member is constant.
8211 : : * @param[out] error
8212 : : * Pointer to error structure.
8213 : : *
8214 : : * @return
8215 : : * Action template pointer on success, NULL otherwise and rte_errno is set.
8216 : : */
8217 : : static struct rte_flow_actions_template *
8218 : 0 : flow_hw_actions_template_create(struct rte_eth_dev *dev,
8219 : : const struct rte_flow_actions_template_attr *attr,
8220 : : const struct rte_flow_action actions[],
8221 : : const struct rte_flow_action masks[],
8222 : : struct rte_flow_error *error)
8223 : : {
8224 : 0 : return __flow_hw_actions_template_create(dev, attr, actions, masks, false, error);
8225 : : }
8226 : :
8227 : : /**
8228 : : * Destroy flow action template.
8229 : : *
8230 : : * @param[in] dev
8231 : : * Pointer to the rte_eth_dev structure.
8232 : : * @param[in] template
8233 : : * Pointer to the action template to be destroyed.
8234 : : * @param[out] error
8235 : : * Pointer to error structure.
8236 : : *
8237 : : * @return
8238 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
8239 : : */
8240 : : static int
8241 : 0 : flow_hw_actions_template_destroy(struct rte_eth_dev *dev,
8242 : : struct rte_flow_actions_template *template,
8243 : : struct rte_flow_error *error __rte_unused)
8244 : : {
8245 : : uint64_t flag = MLX5_FLOW_ACTION_IPV6_ROUTING_REMOVE |
8246 : : MLX5_FLOW_ACTION_IPV6_ROUTING_PUSH;
8247 : :
8248 [ # # ]: 0 : if (rte_atomic_load_explicit(&template->refcnt, rte_memory_order_relaxed) > 1) {
8249 : 0 : DRV_LOG(WARNING, "Action template %p is still in use.",
8250 : : (void *)template);
8251 : 0 : return rte_flow_error_set(error, EBUSY,
8252 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8253 : : NULL,
8254 : : "action template is in use");
8255 : : }
8256 [ # # ]: 0 : if (template->action_flags & flag)
8257 : 0 : mlx5_free_srh_flex_parser(dev);
8258 [ # # ]: 0 : LIST_REMOVE(template, next);
8259 : 0 : flow_hw_flex_item_release(dev, &template->flex_item);
8260 [ # # ]: 0 : if (template->tmpl)
8261 : 0 : mlx5dr_action_template_destroy(template->tmpl);
8262 : 0 : mlx5_free(template);
8263 : 0 : return 0;
8264 : : }
8265 : :
8266 : : static struct rte_flow_item *
8267 : 0 : flow_hw_prepend_item(const struct rte_flow_item *items,
8268 : : const uint32_t nb_items,
8269 : : const struct rte_flow_item *new_item,
8270 : : struct rte_flow_error *error)
8271 : : {
8272 : : struct rte_flow_item *copied_items;
8273 : : size_t size;
8274 : :
8275 : : /* Allocate new array of items. */
8276 : 0 : size = sizeof(*copied_items) * (nb_items + 1);
8277 : 0 : copied_items = mlx5_malloc(MLX5_MEM_ZERO, size, 0, rte_socket_id());
8278 [ # # ]: 0 : if (!copied_items) {
8279 : 0 : rte_flow_error_set(error, ENOMEM,
8280 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8281 : : NULL,
8282 : : "cannot allocate item template");
8283 : 0 : return NULL;
8284 : : }
8285 : : /* Put new item at the beginning and copy the rest. */
8286 : 0 : copied_items[0] = *new_item;
8287 [ # # ]: 0 : rte_memcpy(&copied_items[1], items, sizeof(*items) * nb_items);
8288 : : return copied_items;
8289 : : }
8290 : :
8291 : : static int
8292 : 0 : flow_hw_item_compare_field_validate(enum rte_flow_field_id arg_field,
8293 : : enum rte_flow_field_id base_field,
8294 : : struct rte_flow_error *error)
8295 : : {
8296 [ # # # ]: 0 : switch (arg_field) {
8297 : : case RTE_FLOW_FIELD_TAG:
8298 : : case RTE_FLOW_FIELD_META:
8299 : : case RTE_FLOW_FIELD_ESP_SEQ_NUM:
8300 : : break;
8301 : 0 : case RTE_FLOW_FIELD_RANDOM:
8302 [ # # ]: 0 : if (base_field == RTE_FLOW_FIELD_VALUE)
8303 : : return 0;
8304 : 0 : return rte_flow_error_set(error, EINVAL,
8305 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8306 : : NULL,
8307 : : "compare random is supported only with immediate value");
8308 : 0 : default:
8309 : 0 : return rte_flow_error_set(error, ENOTSUP,
8310 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8311 : : NULL,
8312 : : "compare item argument field is not supported");
8313 : : }
8314 [ # # ]: 0 : switch (base_field) {
8315 : : case RTE_FLOW_FIELD_TAG:
8316 : : case RTE_FLOW_FIELD_META:
8317 : : case RTE_FLOW_FIELD_VALUE:
8318 : : case RTE_FLOW_FIELD_ESP_SEQ_NUM:
8319 : : break;
8320 : 0 : default:
8321 : 0 : return rte_flow_error_set(error, ENOTSUP,
8322 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8323 : : NULL,
8324 : : "compare item base field is not supported");
8325 : : }
8326 : : return 0;
8327 : : }
8328 : :
8329 : : static inline uint32_t
8330 : : flow_hw_item_compare_width_supported(enum rte_flow_field_id field)
8331 : : {
8332 [ # # # ]: 0 : switch (field) {
8333 : : case RTE_FLOW_FIELD_TAG:
8334 : : case RTE_FLOW_FIELD_META:
8335 : : case RTE_FLOW_FIELD_ESP_SEQ_NUM:
8336 : : return 32;
8337 : 0 : case RTE_FLOW_FIELD_RANDOM:
8338 : 0 : return 16;
8339 : : default:
8340 : : break;
8341 : : }
8342 : 0 : return 0;
8343 : : }
8344 : :
8345 : : static int
8346 : 0 : flow_hw_validate_item_compare(const struct rte_flow_item *item,
8347 : : struct rte_flow_error *error)
8348 : : {
8349 : 0 : const struct rte_flow_item_compare *comp_m = item->mask;
8350 : 0 : const struct rte_flow_item_compare *comp_v = item->spec;
8351 : : int ret;
8352 : :
8353 [ # # ]: 0 : if (unlikely(!comp_m))
8354 : 0 : return rte_flow_error_set(error, EINVAL,
8355 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8356 : : NULL,
8357 : : "compare item mask is missing");
8358 [ # # ]: 0 : if (comp_m->width != UINT32_MAX)
8359 : 0 : return rte_flow_error_set(error, EINVAL,
8360 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8361 : : NULL,
8362 : : "compare item only support full mask");
8363 : 0 : ret = flow_hw_item_compare_field_validate(comp_m->a.field,
8364 : 0 : comp_m->b.field, error);
8365 [ # # ]: 0 : if (ret < 0)
8366 : : return ret;
8367 [ # # ]: 0 : if (comp_v) {
8368 : : uint32_t width;
8369 : :
8370 [ # # ]: 0 : if (comp_v->operation != comp_m->operation ||
8371 [ # # ]: 0 : comp_v->a.field != comp_m->a.field ||
8372 [ # # ]: 0 : comp_v->b.field != comp_m->b.field)
8373 : 0 : return rte_flow_error_set(error, EINVAL,
8374 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8375 : : NULL,
8376 : : "compare item spec/mask not matching");
8377 : : width = flow_hw_item_compare_width_supported(comp_v->a.field);
8378 : : MLX5_ASSERT(width > 0);
8379 [ # # ]: 0 : if ((comp_v->width & comp_m->width) != width)
8380 : 0 : return rte_flow_error_set(error, EINVAL,
8381 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8382 : : NULL,
8383 : : "compare item only support full mask");
8384 : : }
8385 : : return 0;
8386 : : }
8387 : :
8388 : : static inline int
8389 : : mlx5_hw_validate_item_nsh(struct rte_eth_dev *dev,
8390 : : const struct rte_flow_item *item,
8391 : : struct rte_flow_error *error)
8392 : : {
8393 : 0 : return mlx5_flow_validate_item_nsh(dev, item, error);
8394 : : }
8395 : :
8396 : : static bool
8397 : : mlx5_hw_flow_tunnel_ip_check(uint64_t last_item, uint64_t *item_flags)
8398 : : {
8399 : : bool tunnel;
8400 : :
8401 [ # # # # ]: 0 : if (last_item == MLX5_FLOW_LAYER_OUTER_L3_IPV4) {
8402 : : tunnel = true;
8403 : 0 : *item_flags |= MLX5_FLOW_LAYER_IPIP;
8404 : 0 : } else if (last_item == MLX5_FLOW_LAYER_OUTER_L3_IPV6 ||
8405 [ # # # # ]: 0 : last_item == MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT) {
8406 : : tunnel = true;
8407 : 0 : *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
8408 : : } else {
8409 : : tunnel = false;
8410 : : }
8411 : : return tunnel;
8412 : : }
8413 : :
8414 : : const struct rte_flow_item_ipv4 hws_nic_ipv4_mask = {
8415 : : .hdr = {
8416 : : .version = 0xf,
8417 : : .ihl = 0xf,
8418 : : .type_of_service = 0xff,
8419 : : .total_length = RTE_BE16(0xffff),
8420 : : .packet_id = RTE_BE16(0xffff),
8421 : : .fragment_offset = RTE_BE16(0xffff),
8422 : : .time_to_live = 0xff,
8423 : : .next_proto_id = 0xff,
8424 : : .src_addr = RTE_BE32(0xffffffff),
8425 : : .dst_addr = RTE_BE32(0xffffffff),
8426 : : },
8427 : : };
8428 : :
8429 : : const struct rte_flow_item_ipv6 hws_nic_ipv6_mask = {
8430 : : .hdr = {
8431 : : .vtc_flow = RTE_BE32(0xffffffff),
8432 : : .payload_len = RTE_BE16(0xffff),
8433 : : .proto = 0xff,
8434 : : .hop_limits = 0xff,
8435 : : .src_addr = RTE_IPV6_MASK_FULL,
8436 : : .dst_addr = RTE_IPV6_MASK_FULL,
8437 : : },
8438 : : .has_frag_ext = 1,
8439 : : };
8440 : :
8441 : : const struct rte_flow_item_ecpri hws_nic_ecpri_mask = {
8442 : : .hdr = {
8443 : : .common = {
8444 : : .u32 = RTE_BE32(0xffffffff),
8445 : : },
8446 : : .dummy[0] = 0xffffffff,
8447 : : },
8448 : : };
8449 : :
8450 : :
8451 : : static int
8452 : 0 : flow_hw_validate_item_ptype(const struct rte_flow_item *item,
8453 : : struct rte_flow_error *error)
8454 : : {
8455 : 0 : const struct rte_flow_item_ptype *ptype = item->mask;
8456 : :
8457 : : /* HWS does not allow empty PTYPE mask */
8458 [ # # ]: 0 : if (!ptype)
8459 : 0 : return rte_flow_error_set(error, EINVAL,
8460 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8461 : : NULL, "empty ptype mask");
8462 [ # # ]: 0 : if (!(ptype->packet_type &
8463 : : (RTE_PTYPE_L2_MASK | RTE_PTYPE_L3_MASK | RTE_PTYPE_L4_MASK |
8464 : : RTE_PTYPE_INNER_L2_MASK | RTE_PTYPE_INNER_L3_MASK |
8465 : : RTE_PTYPE_INNER_L4_MASK)))
8466 : 0 : return rte_flow_error_set(error, ENOTSUP,
8467 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8468 : : NULL, "ptype mask not supported");
8469 : : return 0;
8470 : : }
8471 : :
8472 : : struct mlx5_hw_pattern_validation_ctx {
8473 : : const struct rte_flow_item *geneve_item;
8474 : : const struct rte_flow_item *flex_item;
8475 : : };
8476 : :
8477 : : static int
8478 : 0 : flow_hw_pattern_validate(struct rte_eth_dev *dev,
8479 : : const struct rte_flow_pattern_template_attr *attr,
8480 : : const struct rte_flow_item items[],
8481 : : uint64_t *item_flags,
8482 : : struct rte_flow_error *error)
8483 : : {
8484 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
8485 : : const struct rte_flow_item *item;
8486 : : const struct rte_flow_item *gtp_item = NULL;
8487 : : const struct rte_flow_item *gre_item = NULL;
8488 : 0 : const struct rte_flow_attr flow_attr = {
8489 : 0 : .ingress = attr->ingress,
8490 : 0 : .egress = attr->egress,
8491 : 0 : .transfer = attr->transfer
8492 : : };
8493 : : int ret, tag_idx;
8494 : : uint32_t tag_bitmap = 0;
8495 : : uint64_t last_item = 0;
8496 : :
8497 [ # # ]: 0 : if (!mlx5_hw_ctx_validate(dev, error))
8498 : 0 : return -rte_errno;
8499 [ # # ]: 0 : if (!attr->ingress && !attr->egress && !attr->transfer)
8500 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ATTR, NULL,
8501 : : "at least one of the direction attributes"
8502 : : " must be specified");
8503 [ # # ]: 0 : if (priv->sh->config.dv_esw_en) {
8504 : : MLX5_ASSERT(priv->master || priv->representor);
8505 [ # # ]: 0 : if (priv->master) {
8506 [ # # ]: 0 : if ((attr->ingress && attr->egress) ||
8507 [ # # ]: 0 : (attr->ingress && attr->transfer) ||
8508 [ # # ]: 0 : (attr->egress && attr->transfer))
8509 : 0 : return rte_flow_error_set(error, EINVAL,
8510 : : RTE_FLOW_ERROR_TYPE_ATTR, NULL,
8511 : : "only one direction attribute at once"
8512 : : " can be used on transfer proxy port");
8513 : : } else {
8514 [ # # ]: 0 : if (attr->transfer)
8515 : 0 : return rte_flow_error_set(error, EINVAL,
8516 : : RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER, NULL,
8517 : : "transfer attribute cannot be used with"
8518 : : " port representors");
8519 [ # # ]: 0 : if (attr->ingress && attr->egress)
8520 : 0 : return rte_flow_error_set(error, EINVAL,
8521 : : RTE_FLOW_ERROR_TYPE_ATTR, NULL,
8522 : : "ingress and egress direction attributes"
8523 : : " cannot be used at the same time on"
8524 : : " port representors");
8525 : : }
8526 : : } else {
8527 [ # # ]: 0 : if (attr->transfer)
8528 : 0 : return rte_flow_error_set(error, EINVAL,
8529 : : RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER, NULL,
8530 : : "transfer attribute cannot be used when"
8531 : : " E-Switch is disabled");
8532 : : }
8533 [ # # ]: 0 : for (item = items; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
8534 : 0 : bool tunnel = *item_flags & MLX5_FLOW_LAYER_TUNNEL;
8535 : :
8536 [ # # # # : 0 : switch ((int)item->type) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # #
# ]
8537 : 0 : case RTE_FLOW_ITEM_TYPE_PTYPE:
8538 : 0 : ret = flow_hw_validate_item_ptype(item, error);
8539 [ # # ]: 0 : if (ret)
8540 : 0 : return ret;
8541 : : last_item = MLX5_FLOW_ITEM_PTYPE;
8542 : : break;
8543 : 0 : case RTE_FLOW_ITEM_TYPE_TAG:
8544 : : {
8545 : 0 : const struct rte_flow_item_tag *tag =
8546 : : (const struct rte_flow_item_tag *)item->spec;
8547 : :
8548 [ # # ]: 0 : if (tag == NULL)
8549 : 0 : return rte_flow_error_set(error, EINVAL,
8550 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8551 : : NULL,
8552 : : "Tag spec is NULL");
8553 [ # # ]: 0 : if (tag->index >= MLX5_FLOW_HW_TAGS_MAX &&
8554 : : tag->index != RTE_PMD_MLX5_LINEAR_HASH_TAG_INDEX)
8555 : 0 : return rte_flow_error_set(error, EINVAL,
8556 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8557 : : NULL,
8558 : : "Invalid tag index");
8559 [ # # ]: 0 : tag_idx = flow_hw_get_reg_id(dev, RTE_FLOW_ITEM_TYPE_TAG, tag->index);
8560 [ # # ]: 0 : if (tag_idx == REG_NON)
8561 : 0 : return rte_flow_error_set(error, EINVAL,
8562 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8563 : : NULL,
8564 : : "Unsupported tag index");
8565 [ # # ]: 0 : if (tag_bitmap & (1 << tag_idx))
8566 : 0 : return rte_flow_error_set(error, EINVAL,
8567 : : RTE_FLOW_ERROR_TYPE_ITEM,
8568 : : NULL,
8569 : : "Duplicated tag index");
8570 : 0 : tag_bitmap |= 1 << tag_idx;
8571 : : last_item = MLX5_FLOW_ITEM_TAG;
8572 : 0 : break;
8573 : : }
8574 : 0 : case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
8575 : : {
8576 : 0 : const struct rte_flow_item_tag *tag =
8577 : : (const struct rte_flow_item_tag *)item->spec;
8578 : 0 : uint16_t regcs = (uint8_t)priv->sh->cdev->config.hca_attr.set_reg_c;
8579 : :
8580 [ # # ]: 0 : if (!((1 << (tag->index - REG_C_0)) & regcs))
8581 : 0 : return rte_flow_error_set(error, EINVAL,
8582 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8583 : : NULL,
8584 : : "Unsupported internal tag index");
8585 [ # # ]: 0 : if (tag_bitmap & (1 << tag->index))
8586 : 0 : return rte_flow_error_set(error, EINVAL,
8587 : : RTE_FLOW_ERROR_TYPE_ITEM,
8588 : : NULL,
8589 : : "Duplicated tag index");
8590 : 0 : tag_bitmap |= 1 << tag->index;
8591 : 0 : break;
8592 : : }
8593 : 0 : case RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT:
8594 [ # # # # ]: 0 : if (attr->ingress && priv->sh->config.repr_matching)
8595 : 0 : return rte_flow_error_set(error, EINVAL,
8596 : : RTE_FLOW_ERROR_TYPE_ITEM, NULL,
8597 : : "represented port item cannot be used"
8598 : : " when ingress attribute is set");
8599 [ # # ]: 0 : if (attr->egress)
8600 : 0 : return rte_flow_error_set(error, EINVAL,
8601 : : RTE_FLOW_ERROR_TYPE_ITEM, NULL,
8602 : : "represented port item cannot be used"
8603 : : " when egress attribute is set");
8604 : : last_item = MLX5_FLOW_ITEM_REPRESENTED_PORT;
8605 : : break;
8606 : 0 : case RTE_FLOW_ITEM_TYPE_META:
8607 : : /* ingress + group 0 is not supported */
8608 : 0 : *item_flags |= MLX5_FLOW_ITEM_METADATA;
8609 : 0 : break;
8610 : : case RTE_FLOW_ITEM_TYPE_METER_COLOR:
8611 : : {
8612 : : int reg = flow_hw_get_reg_id(dev,
8613 : : RTE_FLOW_ITEM_TYPE_METER_COLOR,
8614 : : 0);
8615 [ # # ]: 0 : if (reg == REG_NON)
8616 : 0 : return rte_flow_error_set(error, EINVAL,
8617 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8618 : : NULL,
8619 : : "Unsupported meter color register");
8620 [ # # ]: 0 : if (*item_flags &
8621 : : (MLX5_FLOW_ITEM_QUOTA | MLX5_FLOW_LAYER_ASO_CT))
8622 : 0 : return rte_flow_error_set
8623 : : (error, EINVAL,
8624 : : RTE_FLOW_ERROR_TYPE_ITEM, NULL, "Only one ASO item is supported");
8625 : : last_item = MLX5_FLOW_ITEM_METER_COLOR;
8626 : : break;
8627 : : }
8628 : 0 : case RTE_FLOW_ITEM_TYPE_AGGR_AFFINITY:
8629 : : {
8630 [ # # ]: 0 : if (!priv->sh->lag_rx_port_affinity_en)
8631 : 0 : return rte_flow_error_set(error, EINVAL,
8632 : : RTE_FLOW_ERROR_TYPE_ITEM, NULL,
8633 : : "Unsupported aggregated affinity with Older FW");
8634 [ # # # # : 0 : if ((attr->transfer && priv->fdb_def_rule) || attr->egress)
# # ]
8635 : 0 : return rte_flow_error_set(error, EINVAL,
8636 : : RTE_FLOW_ERROR_TYPE_ITEM, NULL,
8637 : : "Aggregated affinity item not supported"
8638 : : " with egress or transfer"
8639 : : " attribute");
8640 : : last_item = MLX5_FLOW_ITEM_AGGR_AFFINITY;
8641 : : break;
8642 : : }
8643 : 0 : case RTE_FLOW_ITEM_TYPE_GENEVE:
8644 : : last_item = MLX5_FLOW_LAYER_GENEVE;
8645 : 0 : break;
8646 : 0 : case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
8647 : : {
8648 : : last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
8649 : 0 : ret = mlx5_flow_geneve_tlv_option_validate(priv, item,
8650 : : error);
8651 [ # # ]: 0 : if (ret < 0)
8652 : 0 : return ret;
8653 : : break;
8654 : : }
8655 : 0 : case RTE_FLOW_ITEM_TYPE_COMPARE:
8656 : : {
8657 : : last_item = MLX5_FLOW_ITEM_COMPARE;
8658 : 0 : ret = flow_hw_validate_item_compare(item, error);
8659 [ # # ]: 0 : if (ret)
8660 : 0 : return ret;
8661 : : break;
8662 : : }
8663 : 0 : case RTE_FLOW_ITEM_TYPE_ETH:
8664 : 0 : ret = mlx5_flow_validate_item_eth(dev, item,
8665 : : *item_flags,
8666 : : true, error);
8667 [ # # ]: 0 : if (ret < 0)
8668 : 0 : return ret;
8669 [ # # ]: 0 : last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
8670 : : MLX5_FLOW_LAYER_OUTER_L2;
8671 : : break;
8672 : 0 : case RTE_FLOW_ITEM_TYPE_VLAN:
8673 : 0 : ret = mlx5_flow_dv_validate_item_vlan(item, *item_flags,
8674 : : dev, error);
8675 [ # # ]: 0 : if (ret < 0)
8676 : 0 : return ret;
8677 [ # # ]: 0 : last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
8678 : : MLX5_FLOW_LAYER_OUTER_VLAN;
8679 : : break;
8680 : : case RTE_FLOW_ITEM_TYPE_IPV4:
8681 : 0 : tunnel |= mlx5_hw_flow_tunnel_ip_check(last_item,
8682 : : item_flags);
8683 : 0 : ret = mlx5_flow_dv_validate_item_ipv4(dev, item,
8684 : : *item_flags,
8685 : : last_item, 0,
8686 : : &hws_nic_ipv4_mask,
8687 : : error);
8688 [ # # ]: 0 : if (ret)
8689 : 0 : return ret;
8690 [ # # ]: 0 : last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
8691 : : MLX5_FLOW_LAYER_OUTER_L3_IPV4;
8692 : : break;
8693 : : case RTE_FLOW_ITEM_TYPE_IPV6:
8694 : 0 : tunnel |= mlx5_hw_flow_tunnel_ip_check(last_item,
8695 : : item_flags);
8696 : 0 : ret = mlx5_flow_validate_item_ipv6(dev, item,
8697 : : *item_flags,
8698 : : last_item, 0,
8699 : : &hws_nic_ipv6_mask,
8700 : : error);
8701 [ # # ]: 0 : if (ret < 0)
8702 : 0 : return ret;
8703 [ # # ]: 0 : last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
8704 : : MLX5_FLOW_LAYER_OUTER_L3_IPV6;
8705 : : break;
8706 : 0 : case RTE_FLOW_ITEM_TYPE_UDP:
8707 : 0 : ret = mlx5_flow_validate_item_udp(dev, item,
8708 : : *item_flags,
8709 : : 0xff, error);
8710 [ # # ]: 0 : if (ret)
8711 : 0 : return ret;
8712 [ # # ]: 0 : last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
8713 : : MLX5_FLOW_LAYER_OUTER_L4_UDP;
8714 : : break;
8715 : 0 : case RTE_FLOW_ITEM_TYPE_TCP:
8716 : 0 : ret = mlx5_flow_validate_item_tcp
8717 : : (dev, item, *item_flags,
8718 : : 0xff, &nic_tcp_mask, error);
8719 [ # # ]: 0 : if (ret < 0)
8720 : 0 : return ret;
8721 [ # # ]: 0 : last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
8722 : : MLX5_FLOW_LAYER_OUTER_L4_TCP;
8723 : : break;
8724 : 0 : case RTE_FLOW_ITEM_TYPE_GTP:
8725 : : gtp_item = item;
8726 : 0 : ret = mlx5_flow_dv_validate_item_gtp(dev, gtp_item,
8727 : : *item_flags, error);
8728 [ # # ]: 0 : if (ret < 0)
8729 : 0 : return ret;
8730 : : last_item = MLX5_FLOW_LAYER_GTP;
8731 : : break;
8732 : 0 : case RTE_FLOW_ITEM_TYPE_GTP_PSC:
8733 : 0 : ret = mlx5_flow_dv_validate_item_gtp_psc(dev, item,
8734 : : last_item,
8735 : : gtp_item,
8736 : : false, error);
8737 [ # # ]: 0 : if (ret < 0)
8738 : 0 : return ret;
8739 : : last_item = MLX5_FLOW_LAYER_GTP_PSC;
8740 : : break;
8741 : 0 : case RTE_FLOW_ITEM_TYPE_VXLAN:
8742 : 0 : ret = mlx5_flow_validate_item_vxlan(dev, 0, item,
8743 : : *item_flags,
8744 : : false, error);
8745 [ # # ]: 0 : if (ret < 0)
8746 : 0 : return ret;
8747 : : last_item = MLX5_FLOW_LAYER_VXLAN;
8748 : : break;
8749 : 0 : case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
8750 : 0 : ret = mlx5_flow_validate_item_vxlan_gpe(item,
8751 : : *item_flags,
8752 : : dev, error);
8753 [ # # ]: 0 : if (ret < 0)
8754 : 0 : return ret;
8755 : : last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
8756 : : break;
8757 : 0 : case RTE_FLOW_ITEM_TYPE_MPLS:
8758 : 0 : ret = mlx5_flow_validate_item_mpls(dev, item,
8759 : : *item_flags,
8760 : : last_item, error);
8761 [ # # ]: 0 : if (ret < 0)
8762 : 0 : return ret;
8763 : : last_item = MLX5_FLOW_LAYER_MPLS;
8764 : : break;
8765 : 0 : case MLX5_RTE_FLOW_ITEM_TYPE_SQ:
8766 : : case RTE_FLOW_ITEM_TYPE_TX_QUEUE:
8767 : : last_item = MLX5_FLOW_ITEM_SQ;
8768 : 0 : break;
8769 : 0 : case RTE_FLOW_ITEM_TYPE_GRE:
8770 : 0 : ret = mlx5_flow_validate_item_gre(dev, item,
8771 : : *item_flags,
8772 : : 0xff, error);
8773 [ # # ]: 0 : if (ret < 0)
8774 : 0 : return ret;
8775 : : gre_item = item;
8776 : : last_item = MLX5_FLOW_LAYER_GRE;
8777 : : break;
8778 : 0 : case RTE_FLOW_ITEM_TYPE_GRE_KEY:
8779 [ # # ]: 0 : if (!(*item_flags & MLX5_FLOW_LAYER_GRE))
8780 : 0 : return rte_flow_error_set
8781 : : (error, EINVAL,
8782 : : RTE_FLOW_ERROR_TYPE_ITEM, item, "GRE item is missing");
8783 : 0 : ret = mlx5_flow_validate_item_gre_key
8784 : : (dev, item, *item_flags, gre_item, error);
8785 [ # # ]: 0 : if (ret < 0)
8786 : 0 : return ret;
8787 : : last_item = MLX5_FLOW_LAYER_GRE_KEY;
8788 : : break;
8789 : 0 : case RTE_FLOW_ITEM_TYPE_GRE_OPTION:
8790 [ # # ]: 0 : if (!(*item_flags & MLX5_FLOW_LAYER_GRE))
8791 : 0 : return rte_flow_error_set
8792 : : (error, EINVAL,
8793 : : RTE_FLOW_ERROR_TYPE_ITEM, item, "GRE item is missing");
8794 : 0 : ret = mlx5_flow_validate_item_gre_option(dev, item,
8795 : : *item_flags,
8796 : : &flow_attr,
8797 : : gre_item,
8798 : : error);
8799 [ # # ]: 0 : if (ret < 0)
8800 : 0 : return ret;
8801 : : last_item = MLX5_FLOW_LAYER_GRE;
8802 : : break;
8803 : 0 : case RTE_FLOW_ITEM_TYPE_NVGRE:
8804 : 0 : ret = mlx5_flow_validate_item_nvgre(dev, item,
8805 : : *item_flags, 0xff,
8806 : : error);
8807 [ # # ]: 0 : if (ret)
8808 : 0 : return ret;
8809 : : last_item = MLX5_FLOW_LAYER_NVGRE;
8810 : : break;
8811 : 0 : case RTE_FLOW_ITEM_TYPE_ICMP:
8812 : 0 : ret = mlx5_flow_validate_item_icmp(dev, item,
8813 : : *item_flags, 0xff,
8814 : : error);
8815 [ # # ]: 0 : if (ret < 0)
8816 : 0 : return ret;
8817 : : last_item = MLX5_FLOW_LAYER_ICMP;
8818 : : break;
8819 : 0 : case RTE_FLOW_ITEM_TYPE_ICMP6:
8820 : 0 : ret = mlx5_flow_validate_item_icmp6(dev, item,
8821 : : *item_flags, 0xff,
8822 : : error);
8823 [ # # ]: 0 : if (ret < 0)
8824 : 0 : return ret;
8825 : : last_item = MLX5_FLOW_LAYER_ICMP6;
8826 : : break;
8827 : 0 : case RTE_FLOW_ITEM_TYPE_ICMP6_ECHO_REQUEST:
8828 : : case RTE_FLOW_ITEM_TYPE_ICMP6_ECHO_REPLY:
8829 : 0 : ret = mlx5_flow_validate_item_icmp6_echo(dev, item,
8830 : : *item_flags,
8831 : : 0xff, error);
8832 [ # # ]: 0 : if (ret < 0)
8833 : 0 : return ret;
8834 : : last_item = MLX5_FLOW_LAYER_ICMP6;
8835 : : break;
8836 : 0 : case RTE_FLOW_ITEM_TYPE_CONNTRACK:
8837 [ # # ]: 0 : if (*item_flags &
8838 : : (MLX5_FLOW_ITEM_QUOTA | MLX5_FLOW_LAYER_ASO_CT))
8839 : 0 : return rte_flow_error_set
8840 : : (error, EINVAL,
8841 : : RTE_FLOW_ERROR_TYPE_ITEM, NULL, "Only one ASO item is supported");
8842 : 0 : ret = mlx5_flow_dv_validate_item_aso_ct(dev, item,
8843 : : item_flags,
8844 : : error);
8845 [ # # ]: 0 : if (ret < 0)
8846 : 0 : return ret;
8847 : : break;
8848 : 0 : case RTE_FLOW_ITEM_TYPE_QUOTA:
8849 [ # # ]: 0 : if (*item_flags &
8850 : : (MLX5_FLOW_ITEM_METER_COLOR |
8851 : : MLX5_FLOW_LAYER_ASO_CT))
8852 : 0 : return rte_flow_error_set
8853 : : (error, EINVAL,
8854 : : RTE_FLOW_ERROR_TYPE_ITEM, NULL, "Only one ASO item is supported");
8855 : : last_item = MLX5_FLOW_ITEM_QUOTA;
8856 : : break;
8857 : 0 : case RTE_FLOW_ITEM_TYPE_ESP:
8858 : 0 : ret = mlx5_flow_os_validate_item_esp(dev, item,
8859 : : *item_flags, 0xff,
8860 : : error);
8861 [ # # ]: 0 : if (ret < 0)
8862 : 0 : return ret;
8863 : : last_item = MLX5_FLOW_ITEM_ESP;
8864 : : break;
8865 : 0 : case RTE_FLOW_ITEM_TYPE_IPV6_ROUTING_EXT:
8866 : : last_item = tunnel ?
8867 [ # # ]: 0 : MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT :
8868 : : MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT;
8869 : : break;
8870 : 0 : case RTE_FLOW_ITEM_TYPE_FLEX:
8871 : : /* match mlx5dr_definer_conv_items_to_hl() */
8872 : : last_item = tunnel ?
8873 [ # # ]: 0 : MLX5_FLOW_ITEM_INNER_FLEX :
8874 : : MLX5_FLOW_ITEM_OUTER_FLEX;
8875 : : break;
8876 : 0 : case RTE_FLOW_ITEM_TYPE_RANDOM:
8877 : : last_item = MLX5_FLOW_ITEM_RANDOM;
8878 : 0 : break;
8879 : 0 : case RTE_FLOW_ITEM_TYPE_NSH:
8880 : : last_item = MLX5_FLOW_ITEM_NSH;
8881 : : ret = mlx5_hw_validate_item_nsh(dev, item, error);
8882 [ # # ]: 0 : if (ret < 0)
8883 : 0 : return ret;
8884 : : break;
8885 : : case RTE_FLOW_ITEM_TYPE_INTEGRITY:
8886 : : /*
8887 : : * Integrity flow item validation require access to
8888 : : * both item mask and spec.
8889 : : * Current HWS model allows item mask in pattern
8890 : : * template and item spec in flow rule.
8891 : : */
8892 : : break;
8893 : 0 : case RTE_FLOW_ITEM_TYPE_ECPRI:
8894 : 0 : ret = mlx5_flow_validate_item_ecpri(dev, item, *item_flags, last_item,
8895 : : RTE_ETHER_TYPE_ECPRI,
8896 : : &hws_nic_ecpri_mask, error);
8897 [ # # ]: 0 : if (ret < 0)
8898 : 0 : return ret;
8899 : 0 : *item_flags |= MLX5_FLOW_LAYER_ECPRI;
8900 : 0 : break;
8901 : : case RTE_FLOW_ITEM_TYPE_IB_BTH:
8902 : : case RTE_FLOW_ITEM_TYPE_VOID:
8903 : : case RTE_FLOW_ITEM_TYPE_END:
8904 : : break;
8905 : 0 : default:
8906 : 0 : return rte_flow_error_set(error, EINVAL,
8907 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8908 : : NULL,
8909 : : "Unsupported item type");
8910 : : }
8911 : 0 : *item_flags |= last_item;
8912 : : }
8913 : 0 : return 1 + RTE_PTR_DIFF(item, items) / sizeof(item[0]);
8914 : : }
8915 : :
8916 : : /*
8917 : : * Verify that the tested flow patterns fits STE size limit in HWS group.
8918 : : *
8919 : : *
8920 : : * Return values:
8921 : : * 0 : Tested patterns fit STE size limit
8922 : : * -EINVAL : Invalid parameters detected
8923 : : * -E2BIG : Tested patterns exceed STE size limit
8924 : : */
8925 : : static int
8926 : 0 : pattern_template_validate(struct rte_eth_dev *dev,
8927 : : struct rte_flow_pattern_template *pt[],
8928 : : uint32_t pt_num,
8929 : : struct rte_flow_error *error)
8930 : : {
8931 : 0 : struct mlx5_flow_template_table_cfg tbl_cfg = {
8932 : : .attr = {
8933 : : .nb_flows = 64,
8934 : : .insertion_type = RTE_FLOW_TABLE_INSERTION_TYPE_PATTERN,
8935 : : .hash_func = RTE_FLOW_TABLE_HASH_FUNC_DEFAULT,
8936 : : .flow_attr = {
8937 : : .group = 1,
8938 : 0 : .ingress = pt[0]->attr.ingress,
8939 : 0 : .egress = pt[0]->attr.egress,
8940 : 0 : .transfer = pt[0]->attr.transfer
8941 : : }
8942 : : }
8943 : : };
8944 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
8945 : : struct rte_flow_actions_template *action_template;
8946 : : struct rte_flow_template_table *tmpl_tbl;
8947 : : int ret;
8948 : :
8949 [ # # ]: 0 : if (pt[0]->attr.ingress) {
8950 : 0 : action_template =
8951 : 0 : priv->action_template_drop[MLX5DR_TABLE_TYPE_NIC_RX];
8952 [ # # ]: 0 : } else if (pt[0]->attr.egress) {
8953 : 0 : action_template =
8954 : 0 : priv->action_template_drop[MLX5DR_TABLE_TYPE_NIC_TX];
8955 [ # # ]: 0 : } else if (pt[0]->attr.transfer) {
8956 : 0 : action_template =
8957 : 0 : priv->action_template_drop[MLX5DR_TABLE_TYPE_FDB];
8958 : : } else {
8959 : : ret = EINVAL;
8960 : 0 : goto end;
8961 : : }
8962 : :
8963 [ # # ]: 0 : if (pt[0]->item_flags & MLX5_FLOW_ITEM_COMPARE)
8964 : 0 : tbl_cfg.attr.nb_flows = 1;
8965 : 0 : tmpl_tbl = flow_hw_table_create(dev, &tbl_cfg, pt, pt_num,
8966 : : &action_template, 1, error);
8967 [ # # ]: 0 : if (tmpl_tbl) {
8968 : : ret = 0;
8969 : 0 : flow_hw_table_destroy(dev, tmpl_tbl, error);
8970 : : } else {
8971 [ # # # ]: 0 : switch (rte_errno) {
8972 : : case E2BIG:
8973 : : ret = E2BIG;
8974 : : break;
8975 : : case ENOTSUP:
8976 : : ret = EINVAL;
8977 : : break;
8978 : : default:
8979 : : ret = 0;
8980 : : break;
8981 : : }
8982 : : }
8983 : : end:
8984 : : if (ret)
8985 : 0 : rte_flow_error_set(error, ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8986 : : NULL, "failed to validate pattern template");
8987 : 0 : return -ret;
8988 : : }
8989 : :
8990 : : /**
8991 : : * Create flow item template.
8992 : : *
8993 : : * @param[in] dev
8994 : : * Pointer to the rte_eth_dev structure.
8995 : : * @param[in] attr
8996 : : * Pointer to the item template attributes.
8997 : : * @param[in] items
8998 : : * The template item pattern.
8999 : : * @param[out] error
9000 : : * Pointer to error structure.
9001 : : *
9002 : : * @return
9003 : : * Item template pointer on success, NULL otherwise and rte_errno is set.
9004 : : */
9005 : : static struct rte_flow_pattern_template *
9006 : 0 : flow_hw_pattern_template_create(struct rte_eth_dev *dev,
9007 : : const struct rte_flow_pattern_template_attr *attr,
9008 : : const struct rte_flow_item items[],
9009 : : struct rte_flow_error *error)
9010 : : {
9011 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
9012 : : struct rte_flow_pattern_template *it;
9013 : : struct rte_flow_item *copied_items = NULL;
9014 : : const struct rte_flow_item *tmpl_items;
9015 : 0 : uint64_t orig_item_nb, item_flags = 0;
9016 : 0 : struct rte_flow_item port = {
9017 : : .type = RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT,
9018 : : .mask = &rte_flow_item_ethdev_mask,
9019 : : };
9020 : 0 : struct rte_flow_item_tag tag_v = {
9021 : : .data = 0,
9022 : : .index = REG_C_0,
9023 : : };
9024 : 0 : struct rte_flow_item_tag tag_m = {
9025 : : .data = flow_hw_tx_tag_regc_mask(dev),
9026 : : .index = 0xff,
9027 : : };
9028 : 0 : struct rte_flow_item tag = {
9029 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_TAG,
9030 : : .spec = &tag_v,
9031 : : .mask = &tag_m,
9032 : : .last = NULL
9033 : : };
9034 : : int it_items_size;
9035 : : unsigned int i = 0;
9036 : : int rc;
9037 : :
9038 : : /* Validate application items only */
9039 : 0 : rc = flow_hw_pattern_validate(dev, attr, items, &item_flags, error);
9040 [ # # ]: 0 : if (rc < 0)
9041 : : return NULL;
9042 : 0 : orig_item_nb = rc;
9043 [ # # # # ]: 0 : if (priv->sh->config.dv_esw_en &&
9044 : : priv->sh->config.repr_matching &&
9045 [ # # ]: 0 : attr->ingress && !attr->egress && !attr->transfer) {
9046 : 0 : copied_items = flow_hw_prepend_item(items, orig_item_nb, &port, error);
9047 [ # # ]: 0 : if (!copied_items)
9048 : : return NULL;
9049 : : tmpl_items = copied_items;
9050 [ # # # # ]: 0 : } else if (priv->sh->config.dv_esw_en &&
9051 : : priv->sh->config.repr_matching &&
9052 [ # # ]: 0 : !attr->ingress && attr->egress && !attr->transfer) {
9053 [ # # ]: 0 : if (item_flags & MLX5_FLOW_ITEM_SQ) {
9054 : 0 : DRV_LOG(DEBUG, "Port %u omitting implicit REG_C_0 match for egress "
9055 : : "pattern template", dev->data->port_id);
9056 : : tmpl_items = items;
9057 : 0 : goto setup_pattern_template;
9058 : : }
9059 : 0 : copied_items = flow_hw_prepend_item(items, orig_item_nb, &tag, error);
9060 [ # # ]: 0 : if (!copied_items)
9061 : : return NULL;
9062 : : tmpl_items = copied_items;
9063 : : } else {
9064 : : tmpl_items = items;
9065 : : }
9066 : 0 : setup_pattern_template:
9067 : 0 : it = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*it), 0, rte_socket_id());
9068 [ # # ]: 0 : if (!it) {
9069 : 0 : rte_flow_error_set(error, ENOMEM,
9070 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9071 : : NULL,
9072 : : "cannot allocate item template");
9073 : 0 : goto error;
9074 : : }
9075 : 0 : it->attr = *attr;
9076 : 0 : it->item_flags = item_flags;
9077 : 0 : it->orig_item_nb = orig_item_nb;
9078 : 0 : it_items_size = rte_flow_conv(RTE_FLOW_CONV_OP_PATTERN, NULL, 0, tmpl_items, error);
9079 [ # # ]: 0 : if (it_items_size <= 0) {
9080 : 0 : rte_flow_error_set(error, ENOMEM,
9081 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9082 : : NULL,
9083 : : "Failed to determine buffer size for pattern");
9084 : 0 : goto error;
9085 : : }
9086 : 0 : it_items_size = RTE_ALIGN(it_items_size, 16);
9087 : 0 : it->items = mlx5_malloc(MLX5_MEM_ZERO, it_items_size, 0, rte_dev_numa_node(dev->device));
9088 [ # # ]: 0 : if (it->items == NULL) {
9089 : 0 : rte_flow_error_set(error, ENOMEM,
9090 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9091 : : NULL,
9092 : : "Cannot allocate memory for pattern");
9093 : 0 : goto error;
9094 : : }
9095 : 0 : rc = rte_flow_conv(RTE_FLOW_CONV_OP_PATTERN, it->items, it_items_size, tmpl_items, error);
9096 [ # # ]: 0 : if (rc <= 0) {
9097 : 0 : rte_flow_error_set(error, ENOMEM,
9098 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9099 : : NULL,
9100 : : "Failed to store pattern");
9101 : 0 : goto error;
9102 : : }
9103 : 0 : it->mt = mlx5dr_match_template_create(tmpl_items, attr->relaxed_matching);
9104 [ # # ]: 0 : if (!it->mt) {
9105 : 0 : rte_flow_error_set(error, rte_errno,
9106 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9107 : : NULL,
9108 : : "cannot create match template");
9109 : 0 : goto error;
9110 : : }
9111 [ # # ]: 0 : if (copied_items) {
9112 [ # # ]: 0 : if (attr->ingress)
9113 : 0 : it->implicit_port = true;
9114 [ # # ]: 0 : else if (attr->egress)
9115 : 0 : it->implicit_tag = true;
9116 : 0 : mlx5_free(copied_items);
9117 : : copied_items = NULL;
9118 : : }
9119 : : /* Either inner or outer, can't both. */
9120 [ # # ]: 0 : if (it->item_flags & (MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT |
9121 : : MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT)) {
9122 [ # # ]: 0 : if (((it->item_flags & MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT) &&
9123 [ # # ]: 0 : (it->item_flags & MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT)) ||
9124 : 0 : (mlx5_alloc_srh_flex_parser(dev))) {
9125 : 0 : rte_flow_error_set(error, rte_errno,
9126 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9127 : : "cannot create IPv6 routing extension support");
9128 : 0 : goto error;
9129 : : }
9130 : : }
9131 [ # # ]: 0 : if (it->item_flags & MLX5_FLOW_ITEM_FLEX) {
9132 [ # # ]: 0 : for (i = 0; items[i].type != RTE_FLOW_ITEM_TYPE_END; i++) {
9133 : 0 : const struct rte_flow_item_flex *spec = items[i].spec;
9134 : : struct rte_flow_item_flex_handle *handle;
9135 : :
9136 [ # # ]: 0 : if (items[i].type != RTE_FLOW_ITEM_TYPE_FLEX)
9137 : 0 : continue;
9138 : 0 : handle = spec->handle;
9139 [ # # ]: 0 : if (flow_hw_flex_item_acquire(dev, handle,
9140 : 0 : &it->flex_item)) {
9141 : 0 : rte_flow_error_set(error, EINVAL,
9142 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9143 : : NULL, "cannot create hw FLEX item");
9144 : 0 : goto error;
9145 : : }
9146 : : }
9147 : : }
9148 [ # # ]: 0 : if (it->item_flags & MLX5_FLOW_LAYER_GENEVE_OPT) {
9149 [ # # ]: 0 : for (i = 0; items[i].type != RTE_FLOW_ITEM_TYPE_END; i++) {
9150 : 0 : const struct rte_flow_item_geneve_opt *spec =
9151 : : items[i].spec;
9152 : :
9153 [ # # ]: 0 : if (items[i].type != RTE_FLOW_ITEM_TYPE_GENEVE_OPT)
9154 : 0 : continue;
9155 [ # # ]: 0 : if (mlx5_geneve_tlv_option_register(priv, spec,
9156 : 0 : &it->geneve_opt_mng)) {
9157 : 0 : rte_flow_error_set(error, EINVAL,
9158 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9159 : : NULL, "cannot register GENEVE TLV option");
9160 : 0 : goto error;
9161 : : }
9162 : : }
9163 : : }
9164 : 0 : rte_atomic_fetch_add_explicit(&it->refcnt, 1, rte_memory_order_relaxed);
9165 : 0 : rc = pattern_template_validate(dev, &it, 1, error);
9166 [ # # ]: 0 : if (rc)
9167 : 0 : goto error;
9168 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->flow_hw_itt, it, next);
9169 : 0 : return it;
9170 : 0 : error:
9171 [ # # ]: 0 : if (it) {
9172 [ # # ]: 0 : if (it->flex_item)
9173 : 0 : flow_hw_flex_item_release(dev, &it->flex_item);
9174 [ # # ]: 0 : if (it->geneve_opt_mng.nb_options)
9175 : 0 : mlx5_geneve_tlv_options_unregister(priv, &it->geneve_opt_mng);
9176 [ # # ]: 0 : if (it->mt)
9177 : 0 : claim_zero(mlx5dr_match_template_destroy(it->mt));
9178 : 0 : mlx5_free(it->items);
9179 : 0 : mlx5_free(it);
9180 : : }
9181 [ # # ]: 0 : if (copied_items)
9182 : 0 : mlx5_free(copied_items);
9183 : : return NULL;
9184 : : }
9185 : :
9186 : : /**
9187 : : * Destroy flow item template.
9188 : : *
9189 : : * @param[in] dev
9190 : : * Pointer to the rte_eth_dev structure.
9191 : : * @param[in] template
9192 : : * Pointer to the item template to be destroyed.
9193 : : * @param[out] error
9194 : : * Pointer to error structure.
9195 : : *
9196 : : * @return
9197 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
9198 : : */
9199 : : static int
9200 : 0 : flow_hw_pattern_template_destroy(struct rte_eth_dev *dev,
9201 : : struct rte_flow_pattern_template *template,
9202 : : struct rte_flow_error *error __rte_unused)
9203 : : {
9204 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
9205 : :
9206 [ # # ]: 0 : if (rte_atomic_load_explicit(&template->refcnt, rte_memory_order_relaxed) > 1) {
9207 : 0 : DRV_LOG(WARNING, "Item template %p is still in use.",
9208 : : (void *)template);
9209 : 0 : return rte_flow_error_set(error, EBUSY,
9210 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9211 : : NULL,
9212 : : "item template is in use");
9213 : : }
9214 [ # # ]: 0 : if (template->item_flags & (MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT |
9215 : : MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT))
9216 : 0 : mlx5_free_srh_flex_parser(dev);
9217 [ # # ]: 0 : LIST_REMOVE(template, next);
9218 : 0 : flow_hw_flex_item_release(dev, &template->flex_item);
9219 : 0 : mlx5_geneve_tlv_options_unregister(priv, &template->geneve_opt_mng);
9220 : 0 : claim_zero(mlx5dr_match_template_destroy(template->mt));
9221 : 0 : mlx5_free(template->items);
9222 : 0 : mlx5_free(template);
9223 : 0 : return 0;
9224 : : }
9225 : :
9226 : : /*
9227 : : * Get information about HWS pre-configurable resources.
9228 : : *
9229 : : * @param[in] dev
9230 : : * Pointer to the rte_eth_dev structure.
9231 : : * @param[out] port_info
9232 : : * Pointer to port information.
9233 : : * @param[out] queue_info
9234 : : * Pointer to queue information.
9235 : : * @param[out] error
9236 : : * Pointer to error structure.
9237 : : *
9238 : : * @return
9239 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
9240 : : */
9241 : : static int
9242 : 0 : flow_hw_info_get(struct rte_eth_dev *dev,
9243 : : struct rte_flow_port_info *port_info,
9244 : : struct rte_flow_queue_info *queue_info,
9245 : : struct rte_flow_error *error __rte_unused)
9246 : : {
9247 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
9248 : 0 : uint16_t port_id = dev->data->port_id;
9249 : : struct rte_mtr_capabilities mtr_cap;
9250 : : int ret;
9251 : :
9252 : : memset(port_info, 0, sizeof(*port_info));
9253 : : /* Queue size is unlimited from low-level. */
9254 : 0 : port_info->max_nb_queues = UINT32_MAX;
9255 : 0 : queue_info->max_size = UINT32_MAX;
9256 : :
9257 : : memset(&mtr_cap, 0, sizeof(struct rte_mtr_capabilities));
9258 : 0 : ret = rte_mtr_capabilities_get(port_id, &mtr_cap, NULL);
9259 [ # # ]: 0 : if (!ret)
9260 : 0 : port_info->max_nb_meters = mtr_cap.n_max;
9261 : 0 : port_info->max_nb_counters = priv->sh->hws_max_nb_counters;
9262 : 0 : port_info->max_nb_aging_objects = port_info->max_nb_counters;
9263 : 0 : return 0;
9264 : : }
9265 : :
9266 : : /**
9267 : : * Create group callback.
9268 : : *
9269 : : * @param[in] tool_ctx
9270 : : * Pointer to the hash list related context.
9271 : : * @param[in] cb_ctx
9272 : : * Pointer to the group creation context.
9273 : : *
9274 : : * @return
9275 : : * Group entry on success, NULL otherwise and rte_errno is set.
9276 : : */
9277 : : struct mlx5_list_entry *
9278 : 0 : flow_hw_grp_create_cb(void *tool_ctx, void *cb_ctx)
9279 : : {
9280 : : struct mlx5_dev_ctx_shared *sh = tool_ctx;
9281 : : struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9282 : 0 : struct rte_eth_dev *dev = ctx->dev;
9283 : 0 : struct rte_flow_attr *attr = (struct rte_flow_attr *)ctx->data;
9284 : 0 : uint32_t *specialize = (uint32_t *)ctx->data2;
9285 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
9286 : : bool unified_fdb = is_unified_fdb(priv);
9287 : 0 : struct mlx5dr_table_attr dr_tbl_attr = {0};
9288 : 0 : struct rte_flow_error *error = ctx->error;
9289 : : struct mlx5_flow_group *grp_data;
9290 : : struct mlx5dr_table *tbl = NULL;
9291 : : struct mlx5dr_action *jump;
9292 : : uint32_t hws_flags;
9293 : 0 : uint32_t idx = 0;
9294 [ # # # # : 0 : MKSTR(matcher_name, "%s_%s_%u_%u_matcher_list",
# # # # ]
9295 : : attr->transfer ? "FDB" : "NIC", attr->egress ? "egress" : "ingress",
9296 : : attr->group, idx);
9297 : :
9298 : 0 : grp_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_HW_GRP], &idx);
9299 [ # # ]: 0 : if (!grp_data) {
9300 : 0 : rte_flow_error_set(error, ENOMEM,
9301 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9302 : : NULL,
9303 : : "cannot allocate flow table data entry");
9304 : 0 : return NULL;
9305 : : }
9306 : 0 : dr_tbl_attr.level = attr->group;
9307 : 0 : dr_tbl_attr.type = get_mlx5dr_table_type(attr, *specialize, unified_fdb);
9308 : 0 : tbl = mlx5dr_table_create(priv->dr_ctx, &dr_tbl_attr);
9309 [ # # ]: 0 : if (!tbl)
9310 : 0 : goto error;
9311 : 0 : grp_data->tbl = tbl;
9312 [ # # ]: 0 : if (attr->group) {
9313 : 0 : hws_flags = mlx5_hw_act_dest_table_flag[dr_tbl_attr.type];
9314 : : /* For case of jump from FDB Tx to FDB Rx as it is supported now. */
9315 [ # # # # ]: 0 : if (priv->jump_fdb_rx_en &&
9316 : : dr_tbl_attr.type == MLX5DR_TABLE_TYPE_FDB_RX)
9317 : 0 : hws_flags |= MLX5DR_ACTION_FLAG_HWS_FDB_TX;
9318 : : /* Jump action be used by non-root table. */
9319 : 0 : jump = mlx5dr_action_create_dest_table
9320 : : (priv->dr_ctx, tbl,
9321 : : hws_flags);
9322 [ # # ]: 0 : if (!jump)
9323 : 0 : goto error;
9324 : 0 : grp_data->jump.hws_action = jump;
9325 : : /* Jump action be used by root table. */
9326 : 0 : jump = mlx5dr_action_create_dest_table
9327 : : (priv->dr_ctx, tbl,
9328 : : mlx5_hw_act_flag[MLX5_HW_ACTION_FLAG_ROOT]
9329 : 0 : [dr_tbl_attr.type]);
9330 [ # # ]: 0 : if (!jump)
9331 : 0 : goto error;
9332 : 0 : grp_data->jump.root_action = jump;
9333 : : }
9334 : :
9335 : 0 : grp_data->matchers = mlx5_list_create(matcher_name, sh, true,
9336 : : flow_matcher_create_cb,
9337 : : flow_matcher_match_cb,
9338 : : flow_matcher_remove_cb,
9339 : : flow_matcher_clone_cb,
9340 : : flow_matcher_clone_free_cb);
9341 : 0 : grp_data->dev = dev;
9342 : 0 : grp_data->idx = idx;
9343 : 0 : grp_data->group_id = attr->group;
9344 : 0 : grp_data->type = dr_tbl_attr.type;
9345 : 0 : return &grp_data->entry;
9346 : 0 : error:
9347 [ # # ]: 0 : if (grp_data->jump.root_action)
9348 : 0 : mlx5dr_action_destroy(grp_data->jump.root_action);
9349 [ # # ]: 0 : if (grp_data->jump.hws_action)
9350 : 0 : mlx5dr_action_destroy(grp_data->jump.hws_action);
9351 [ # # ]: 0 : if (tbl)
9352 : 0 : mlx5dr_table_destroy(tbl);
9353 [ # # ]: 0 : if (idx)
9354 : 0 : mlx5_ipool_free(sh->ipool[MLX5_IPOOL_HW_GRP], idx);
9355 : 0 : rte_flow_error_set(error, ENOMEM,
9356 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9357 : : NULL,
9358 : : "cannot allocate flow dr table");
9359 : 0 : return NULL;
9360 : : }
9361 : :
9362 : : /**
9363 : : * Remove group callback.
9364 : : *
9365 : : * @param[in] tool_ctx
9366 : : * Pointer to the hash list related context.
9367 : : * @param[in] entry
9368 : : * Pointer to the entry to be removed.
9369 : : */
9370 : : void
9371 : 0 : flow_hw_grp_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
9372 : : {
9373 : : struct mlx5_dev_ctx_shared *sh = tool_ctx;
9374 : : struct mlx5_flow_group *grp_data =
9375 : : container_of(entry, struct mlx5_flow_group, entry);
9376 : :
9377 : : MLX5_ASSERT(entry && sh);
9378 : : /* To use the wrapper glue functions instead. */
9379 [ # # ]: 0 : if (grp_data->jump.hws_action)
9380 : 0 : mlx5dr_action_destroy(grp_data->jump.hws_action);
9381 [ # # ]: 0 : if (grp_data->jump.root_action)
9382 : 0 : mlx5dr_action_destroy(grp_data->jump.root_action);
9383 : 0 : mlx5_list_destroy(grp_data->matchers);
9384 : 0 : mlx5dr_table_destroy(grp_data->tbl);
9385 : 0 : mlx5_ipool_free(sh->ipool[MLX5_IPOOL_HW_GRP], grp_data->idx);
9386 : 0 : }
9387 : :
9388 : : /**
9389 : : * Match group callback.
9390 : : *
9391 : : * @param[in] tool_ctx
9392 : : * Pointer to the hash list related context.
9393 : : * @param[in] entry
9394 : : * Pointer to the group to be matched.
9395 : : * @param[in] cb_ctx
9396 : : * Pointer to the group matching context.
9397 : : *
9398 : : * @return
9399 : : * 0 on matched, 1 on miss matched.
9400 : : */
9401 : : int
9402 : 0 : flow_hw_grp_match_cb(void *tool_ctx __rte_unused, struct mlx5_list_entry *entry,
9403 : : void *cb_ctx)
9404 : : {
9405 : : struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9406 : : struct mlx5_flow_group *grp_data =
9407 : : container_of(entry, struct mlx5_flow_group, entry);
9408 : 0 : struct rte_flow_attr *attr =
9409 : : (struct rte_flow_attr *)ctx->data;
9410 : :
9411 : 0 : return (grp_data->dev != ctx->dev) ||
9412 [ # # ]: 0 : (grp_data->group_id != attr->group) ||
9413 [ # # # # ]: 0 : ((grp_data->type < MLX5DR_TABLE_TYPE_FDB) &&
9414 [ # # ]: 0 : attr->transfer) ||
9415 [ # # ]: 0 : ((grp_data->type != MLX5DR_TABLE_TYPE_NIC_TX) &&
9416 [ # # # # ]: 0 : attr->egress) ||
9417 [ # # ]: 0 : ((grp_data->type != MLX5DR_TABLE_TYPE_NIC_RX) &&
9418 : : attr->ingress);
9419 : : }
9420 : :
9421 : : /**
9422 : : * Clone group entry callback.
9423 : : *
9424 : : * @param[in] tool_ctx
9425 : : * Pointer to the hash list related context.
9426 : : * @param[in] entry
9427 : : * Pointer to the group to be matched.
9428 : : * @param[in] cb_ctx
9429 : : * Pointer to the group matching context.
9430 : : *
9431 : : * @return
9432 : : * 0 on matched, 1 on miss matched.
9433 : : */
9434 : : struct mlx5_list_entry *
9435 : 0 : flow_hw_grp_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
9436 : : void *cb_ctx)
9437 : : {
9438 : : struct mlx5_dev_ctx_shared *sh = tool_ctx;
9439 : : struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9440 : : struct mlx5_flow_group *grp_data;
9441 : 0 : struct rte_flow_error *error = ctx->error;
9442 : 0 : uint32_t idx = 0;
9443 : :
9444 : 0 : grp_data = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_HW_GRP], &idx);
9445 [ # # ]: 0 : if (!grp_data) {
9446 : 0 : rte_flow_error_set(error, ENOMEM,
9447 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9448 : : NULL,
9449 : : "cannot allocate flow table data entry");
9450 : 0 : return NULL;
9451 : : }
9452 : : memcpy(grp_data, oentry, sizeof(*grp_data));
9453 : 0 : grp_data->idx = idx;
9454 : 0 : return &grp_data->entry;
9455 : : }
9456 : :
9457 : : /**
9458 : : * Free cloned group entry callback.
9459 : : *
9460 : : * @param[in] tool_ctx
9461 : : * Pointer to the hash list related context.
9462 : : * @param[in] entry
9463 : : * Pointer to the group to be freed.
9464 : : */
9465 : : void
9466 : 0 : flow_hw_grp_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
9467 : : {
9468 : : struct mlx5_dev_ctx_shared *sh = tool_ctx;
9469 : : struct mlx5_flow_group *grp_data =
9470 : : container_of(entry, struct mlx5_flow_group, entry);
9471 : :
9472 : 0 : mlx5_ipool_free(sh->ipool[MLX5_IPOOL_HW_GRP], grp_data->idx);
9473 : 0 : }
9474 : :
9475 : : /**
9476 : : * Create and cache a vport action for given @p dev port. vport actions
9477 : : * cache is used in HWS with FDB flows.
9478 : : *
9479 : : * This function does not create any function if proxy port for @p dev port
9480 : : * was not configured for HW Steering.
9481 : : *
9482 : : * This function assumes that E-Switch is enabled and PMD is running with
9483 : : * HW Steering configured.
9484 : : *
9485 : : * @param dev
9486 : : * Pointer to Ethernet device which will be the action destination.
9487 : : *
9488 : : * @return
9489 : : * 0 on success, positive value otherwise.
9490 : : */
9491 : : int
9492 : 0 : flow_hw_create_vport_action(struct rte_eth_dev *dev)
9493 : : {
9494 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
9495 : : struct rte_eth_dev *proxy_dev;
9496 : : struct mlx5_priv *proxy_priv;
9497 : 0 : uint16_t port_id = dev->data->port_id;
9498 : 0 : uint16_t proxy_port_id = port_id;
9499 : : int ret;
9500 : :
9501 : 0 : ret = mlx5_flow_pick_transfer_proxy(dev, &proxy_port_id, NULL);
9502 [ # # ]: 0 : if (ret)
9503 : : return ret;
9504 : 0 : proxy_dev = &rte_eth_devices[proxy_port_id];
9505 : 0 : proxy_priv = proxy_dev->data->dev_private;
9506 [ # # ]: 0 : if (!proxy_priv->hw_vport)
9507 : : return 0;
9508 [ # # ]: 0 : if (proxy_priv->hw_vport[port_id]) {
9509 : 0 : DRV_LOG(ERR, "port %u HWS vport action already created",
9510 : : port_id);
9511 : 0 : return -EINVAL;
9512 : : }
9513 [ # # ]: 0 : proxy_priv->hw_vport[port_id] = mlx5dr_action_create_dest_vport
9514 : : (proxy_priv->dr_ctx, priv->dev_port,
9515 : : is_unified_fdb(priv) ?
9516 : : (MLX5DR_ACTION_FLAG_HWS_FDB_RX |
9517 : : MLX5DR_ACTION_FLAG_HWS_FDB_TX |
9518 : : MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED) :
9519 : : MLX5DR_ACTION_FLAG_HWS_FDB);
9520 [ # # ]: 0 : if (!proxy_priv->hw_vport[port_id]) {
9521 : 0 : DRV_LOG(ERR, "port %u unable to create HWS vport action",
9522 : : port_id);
9523 : 0 : return -EINVAL;
9524 : : }
9525 : : return 0;
9526 : : }
9527 : :
9528 : : /**
9529 : : * Destroys the vport action associated with @p dev device
9530 : : * from actions' cache.
9531 : : *
9532 : : * This function does not destroy any action if there is no action cached
9533 : : * for @p dev or proxy port was not configured for HW Steering.
9534 : : *
9535 : : * This function assumes that E-Switch is enabled and PMD is running with
9536 : : * HW Steering configured.
9537 : : *
9538 : : * @param dev
9539 : : * Pointer to Ethernet device which will be the action destination.
9540 : : */
9541 : : void
9542 : 0 : flow_hw_destroy_vport_action(struct rte_eth_dev *dev)
9543 : : {
9544 : : struct rte_eth_dev *proxy_dev;
9545 : : struct mlx5_priv *proxy_priv;
9546 : 0 : uint16_t port_id = dev->data->port_id;
9547 : 0 : uint16_t proxy_port_id = port_id;
9548 : :
9549 [ # # ]: 0 : if (mlx5_flow_pick_transfer_proxy(dev, &proxy_port_id, NULL))
9550 : 0 : return;
9551 : 0 : proxy_dev = &rte_eth_devices[proxy_port_id];
9552 : 0 : proxy_priv = proxy_dev->data->dev_private;
9553 [ # # # # ]: 0 : if (!proxy_priv->hw_vport || !proxy_priv->hw_vport[port_id])
9554 : : return;
9555 : 0 : mlx5dr_action_destroy(proxy_priv->hw_vport[port_id]);
9556 : 0 : proxy_priv->hw_vport[port_id] = NULL;
9557 : : }
9558 : :
9559 : : static int
9560 : 0 : flow_hw_create_vport_actions(struct mlx5_priv *priv)
9561 : : {
9562 : : uint16_t port_id;
9563 : :
9564 : : MLX5_ASSERT(!priv->hw_vport);
9565 : : bool unified_fdb = is_unified_fdb(priv);
9566 : 0 : priv->hw_vport = mlx5_malloc(MLX5_MEM_ZERO,
9567 : : sizeof(*priv->hw_vport) * RTE_MAX_ETHPORTS,
9568 : : 0, SOCKET_ID_ANY);
9569 [ # # ]: 0 : if (!priv->hw_vport)
9570 : : return -ENOMEM;
9571 : 0 : DRV_LOG(DEBUG, "port %u :: creating vport actions", priv->dev_data->port_id);
9572 : 0 : DRV_LOG(DEBUG, "port %u :: domain_id=%u", priv->dev_data->port_id, priv->domain_id);
9573 [ # # ]: 0 : MLX5_ETH_FOREACH_DEV(port_id, NULL) {
9574 : 0 : struct mlx5_priv *port_priv = rte_eth_devices[port_id].data->dev_private;
9575 : :
9576 [ # # ]: 0 : if (!port_priv ||
9577 [ # # ]: 0 : port_priv->domain_id != priv->domain_id)
9578 : 0 : continue;
9579 : 0 : DRV_LOG(DEBUG, "port %u :: for port_id=%u, calling mlx5dr_action_create_dest_vport() with ibport=%u",
9580 : : priv->dev_data->port_id, port_id, port_priv->dev_port);
9581 [ # # ]: 0 : priv->hw_vport[port_id] = mlx5dr_action_create_dest_vport
9582 : : (priv->dr_ctx, port_priv->dev_port,
9583 : : unified_fdb ?
9584 : : (MLX5DR_ACTION_FLAG_HWS_FDB_RX |
9585 : : MLX5DR_ACTION_FLAG_HWS_FDB_TX |
9586 : : MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED) :
9587 : : MLX5DR_ACTION_FLAG_HWS_FDB);
9588 : 0 : DRV_LOG(DEBUG, "port %u :: priv->hw_vport[%u]=%p",
9589 : : priv->dev_data->port_id, port_id, (void *)priv->hw_vport[port_id]);
9590 [ # # ]: 0 : if (!priv->hw_vport[port_id])
9591 : : return -EINVAL;
9592 : : }
9593 : : return 0;
9594 : : }
9595 : :
9596 : : static void
9597 : 0 : flow_hw_free_vport_actions(struct mlx5_priv *priv)
9598 : : {
9599 : : uint16_t port_id;
9600 : :
9601 [ # # ]: 0 : if (!priv->hw_vport)
9602 : : return;
9603 [ # # ]: 0 : for (port_id = 0; port_id < RTE_MAX_ETHPORTS; ++port_id)
9604 [ # # ]: 0 : if (priv->hw_vport[port_id])
9605 : 0 : mlx5dr_action_destroy(priv->hw_vport[port_id]);
9606 : 0 : mlx5_free(priv->hw_vport);
9607 : 0 : priv->hw_vport = NULL;
9608 : : }
9609 : :
9610 : : #ifdef HAVE_MLX5DV_DR_ACTION_CREATE_DEST_ROOT_TABLE
9611 : : static __rte_always_inline void
9612 : : _create_send_to_kernel_actions(struct mlx5_priv *priv, int type)
9613 : : {
9614 : : int action_flag;
9615 : :
9616 : : action_flag = mlx5_hw_act_flag[1][type];
9617 : : priv->hw_send_to_kernel[type] =
9618 : : mlx5dr_action_create_dest_root(priv->dr_ctx,
9619 : : MLX5_HW_LOWEST_PRIO_ROOT,
9620 : : action_flag);
9621 : : if (!priv->hw_send_to_kernel[type])
9622 : : DRV_LOG(WARNING, "Unable to create HWS send to kernel action");
9623 : : }
9624 : : #endif
9625 : :
9626 : : static void
9627 : : flow_hw_create_send_to_kernel_actions(__rte_unused struct mlx5_priv *priv,
9628 : : __rte_unused bool is_proxy)
9629 : : {
9630 : : #ifdef HAVE_MLX5DV_DR_ACTION_CREATE_DEST_ROOT_TABLE
9631 : : int i, from, to;
9632 : : bool unified_fdb = is_unified_fdb(priv);
9633 : :
9634 : : for (i = MLX5DR_TABLE_TYPE_NIC_RX; i <= MLX5DR_TABLE_TYPE_NIC_TX; i++)
9635 : : _create_send_to_kernel_actions(priv, i);
9636 : :
9637 : : if (is_proxy) {
9638 : : from = unified_fdb ? MLX5DR_TABLE_TYPE_FDB_RX : MLX5DR_TABLE_TYPE_FDB;
9639 : : to = unified_fdb ? MLX5DR_TABLE_TYPE_FDB_UNIFIED : MLX5DR_TABLE_TYPE_FDB;
9640 : : for (i = from; i <= to; i++)
9641 : : _create_send_to_kernel_actions(priv, i);
9642 : : }
9643 : : #endif
9644 : : }
9645 : :
9646 : : static void
9647 : 0 : flow_hw_destroy_send_to_kernel_action(struct mlx5_priv *priv)
9648 : : {
9649 : : int i;
9650 : :
9651 [ # # ]: 0 : for (i = MLX5DR_TABLE_TYPE_NIC_RX; i < MLX5DR_TABLE_TYPE_MAX; i++) {
9652 [ # # ]: 0 : if (priv->hw_send_to_kernel[i]) {
9653 : 0 : mlx5dr_action_destroy(priv->hw_send_to_kernel[i]);
9654 : 0 : priv->hw_send_to_kernel[i] = NULL;
9655 : : }
9656 : : }
9657 : 0 : }
9658 : :
9659 : : static bool
9660 : : flow_hw_should_create_nat64_actions(struct mlx5_priv *priv)
9661 : : {
9662 : : int i;
9663 : :
9664 : : /* Check if all registers are available. */
9665 [ # # ]: 0 : for (i = 0; i < MLX5_FLOW_NAT64_REGS_MAX; ++i)
9666 [ # # ]: 0 : if (priv->sh->registers.nat64_regs[i] == REG_NON)
9667 : : return false;
9668 : :
9669 : : return true;
9670 : : }
9671 : :
9672 : : static void
9673 : 0 : flow_hw_destroy_nat64_actions(struct mlx5_priv *priv)
9674 : : {
9675 : : uint32_t i;
9676 : :
9677 [ # # ]: 0 : for (i = MLX5DR_TABLE_TYPE_NIC_RX; i < MLX5DR_TABLE_TYPE_MAX; i++) {
9678 [ # # ]: 0 : if (priv->action_nat64[i][RTE_FLOW_NAT64_6TO4]) {
9679 : 0 : (void)mlx5dr_action_destroy(priv->action_nat64[i][RTE_FLOW_NAT64_6TO4]);
9680 : 0 : priv->action_nat64[i][RTE_FLOW_NAT64_6TO4] = NULL;
9681 : : }
9682 [ # # ]: 0 : if (priv->action_nat64[i][RTE_FLOW_NAT64_4TO6]) {
9683 : 0 : (void)mlx5dr_action_destroy(priv->action_nat64[i][RTE_FLOW_NAT64_4TO6]);
9684 : 0 : priv->action_nat64[i][RTE_FLOW_NAT64_4TO6] = NULL;
9685 : : }
9686 : : }
9687 : 0 : }
9688 : :
9689 : : static int
9690 : 0 : _create_nat64_actions(struct mlx5_priv *priv,
9691 : : struct mlx5dr_action_nat64_attr *attr,
9692 : : int type,
9693 : : struct rte_flow_error *error)
9694 : : {
9695 : 0 : const uint32_t flags[MLX5DR_TABLE_TYPE_MAX] = {
9696 : : MLX5DR_ACTION_FLAG_HWS_RX | MLX5DR_ACTION_FLAG_SHARED,
9697 : : MLX5DR_ACTION_FLAG_HWS_TX | MLX5DR_ACTION_FLAG_SHARED,
9698 : : MLX5DR_ACTION_FLAG_HWS_FDB | MLX5DR_ACTION_FLAG_SHARED,
9699 : : MLX5DR_ACTION_FLAG_HWS_FDB_RX | MLX5DR_ACTION_FLAG_SHARED,
9700 : : MLX5DR_ACTION_FLAG_HWS_FDB_TX | MLX5DR_ACTION_FLAG_SHARED,
9701 : : MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED | MLX5DR_ACTION_FLAG_SHARED,
9702 : : };
9703 : : struct mlx5dr_action *act;
9704 : :
9705 : 0 : attr->flags = (enum mlx5dr_action_nat64_flags)
9706 : : (MLX5DR_ACTION_NAT64_V6_TO_V4 | MLX5DR_ACTION_NAT64_BACKUP_ADDR);
9707 : 0 : act = mlx5dr_action_create_nat64(priv->dr_ctx, attr, flags[type]);
9708 [ # # ]: 0 : if (!act)
9709 : 0 : return rte_flow_error_set(error, rte_errno,
9710 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9711 : : "Failed to create v6 to v4 action.");
9712 : 0 : priv->action_nat64[type][RTE_FLOW_NAT64_6TO4] = act;
9713 : 0 : attr->flags = (enum mlx5dr_action_nat64_flags)
9714 : : (MLX5DR_ACTION_NAT64_V4_TO_V6 | MLX5DR_ACTION_NAT64_BACKUP_ADDR);
9715 : 0 : act = mlx5dr_action_create_nat64(priv->dr_ctx, attr, flags[type]);
9716 [ # # ]: 0 : if (!act)
9717 : 0 : return rte_flow_error_set(error, rte_errno,
9718 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9719 : : "Failed to create v4 to v6 action.");
9720 : 0 : priv->action_nat64[type][RTE_FLOW_NAT64_4TO6] = act;
9721 : 0 : return 0;
9722 : : }
9723 : :
9724 : : static int
9725 : 0 : flow_hw_create_nat64_actions(struct mlx5_priv *priv, struct rte_flow_error *error)
9726 : : {
9727 : : struct mlx5dr_action_nat64_attr attr;
9728 : : uint8_t regs[MLX5_FLOW_NAT64_REGS_MAX];
9729 : : uint32_t i, from, to;
9730 : : int rc;
9731 : : bool unified_fdb = is_unified_fdb(priv);
9732 : :
9733 : 0 : attr.registers = regs;
9734 : : /* Try to use 3 registers by default. */
9735 : 0 : attr.num_of_registers = MLX5_FLOW_NAT64_REGS_MAX;
9736 [ # # ]: 0 : for (i = 0; i < MLX5_FLOW_NAT64_REGS_MAX; i++) {
9737 : : MLX5_ASSERT(priv->sh->registers.nat64_regs[i] != REG_NON);
9738 : 0 : regs[i] = mlx5_convert_reg_to_field(priv->sh->registers.nat64_regs[i]);
9739 : : }
9740 [ # # ]: 0 : for (i = MLX5DR_TABLE_TYPE_NIC_RX; i <= MLX5DR_TABLE_TYPE_NIC_TX; i++) {
9741 : 0 : rc = _create_nat64_actions(priv, &attr, i, error);
9742 [ # # ]: 0 : if (rc)
9743 : 0 : return rc;
9744 : : }
9745 [ # # ]: 0 : if (priv->sh->config.dv_esw_en) {
9746 [ # # ]: 0 : from = unified_fdb ? MLX5DR_TABLE_TYPE_FDB_RX :
9747 : : MLX5DR_TABLE_TYPE_FDB;
9748 [ # # ]: 0 : to = unified_fdb ? MLX5DR_TABLE_TYPE_FDB_UNIFIED :
9749 : : MLX5DR_TABLE_TYPE_FDB;
9750 : :
9751 [ # # ]: 0 : for (i = from; i <= to; i++) {
9752 : 0 : rc = _create_nat64_actions(priv, &attr, i, error);
9753 [ # # ]: 0 : if (rc)
9754 : 0 : return rc;
9755 : : }
9756 : : }
9757 : : return 0;
9758 : : }
9759 : :
9760 : : /**
9761 : : * Create an egress pattern template matching on source SQ.
9762 : : *
9763 : : * @param dev
9764 : : * Pointer to Ethernet device.
9765 : : * @param[out] error
9766 : : * Pointer to error structure.
9767 : : *
9768 : : * @return
9769 : : * Pointer to pattern template on success. NULL otherwise, and rte_errno is set.
9770 : : */
9771 : : static struct rte_flow_pattern_template *
9772 : 0 : flow_hw_create_tx_repr_sq_pattern_tmpl(struct rte_eth_dev *dev, struct rte_flow_error *error)
9773 : : {
9774 : 0 : struct rte_flow_pattern_template_attr attr = {
9775 : : .relaxed_matching = 0,
9776 : : .egress = 1,
9777 : : };
9778 : 0 : struct mlx5_rte_flow_item_sq sq_mask = {
9779 : : .queue = UINT32_MAX,
9780 : : };
9781 : 0 : struct rte_flow_item items[] = {
9782 : : {
9783 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_SQ,
9784 : : .mask = &sq_mask,
9785 : : },
9786 : : {
9787 : : .type = RTE_FLOW_ITEM_TYPE_END,
9788 : : },
9789 : : };
9790 : :
9791 : 0 : return flow_hw_pattern_template_create(dev, &attr, items, error);
9792 : : }
9793 : :
9794 : : static __rte_always_inline uint32_t
9795 : : flow_hw_tx_tag_regc_mask(struct rte_eth_dev *dev)
9796 : : {
9797 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
9798 : 0 : uint32_t mask = priv->sh->dv_regc0_mask;
9799 : :
9800 : : /* Mask is verified during device initialization. Sanity checking here. */
9801 : : MLX5_ASSERT(mask != 0);
9802 : : /*
9803 : : * Availability of sufficient number of bits in REG_C_0 is verified on initialization.
9804 : : * Sanity checking here.
9805 : : */
9806 : : MLX5_ASSERT(rte_popcount32(mask) >= rte_popcount32(priv->vport_meta_mask));
9807 : : return mask;
9808 : : }
9809 : :
9810 : : static __rte_always_inline uint32_t
9811 : : flow_hw_tx_tag_regc_value(struct rte_eth_dev *dev)
9812 : : {
9813 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
9814 : : uint32_t tag;
9815 : :
9816 : : /* Mask is verified during device initialization. Sanity checking here. */
9817 : : MLX5_ASSERT(priv->vport_meta_mask != 0);
9818 [ # # ]: 0 : tag = priv->vport_meta_tag >> (rte_bsf32(priv->vport_meta_mask));
9819 : : /*
9820 : : * Availability of sufficient number of bits in REG_C_0 is verified on initialization.
9821 : : * Sanity checking here.
9822 : : */
9823 : : MLX5_ASSERT((tag & priv->sh->dv_regc0_mask) == tag);
9824 : : return tag;
9825 : : }
9826 : :
9827 : : static void
9828 : : flow_hw_update_action_mask(struct rte_flow_action *action,
9829 : : struct rte_flow_action *mask,
9830 : : enum rte_flow_action_type type,
9831 : : void *conf_v,
9832 : : void *conf_m)
9833 : : {
9834 : 0 : action->type = type;
9835 : 0 : action->conf = conf_v;
9836 : 0 : mask->type = type;
9837 : 0 : mask->conf = conf_m;
9838 : : }
9839 : :
9840 : : /**
9841 : : * Create an egress actions template with MODIFY_FIELD action for setting unused REG_C_0 bits
9842 : : * to vport tag and JUMP action to group 1.
9843 : : *
9844 : : * If extended metadata mode is enabled, then MODIFY_FIELD action for copying software metadata
9845 : : * to REG_C_1 is added as well.
9846 : : *
9847 : : * @param dev
9848 : : * Pointer to Ethernet device.
9849 : : * @param[out] error
9850 : : * Pointer to error structure.
9851 : : *
9852 : : * @return
9853 : : * Pointer to actions template on success. NULL otherwise, and rte_errno is set.
9854 : : */
9855 : : static struct rte_flow_actions_template *
9856 : 0 : flow_hw_create_tx_repr_tag_jump_acts_tmpl(struct rte_eth_dev *dev,
9857 : : struct rte_flow_error *error)
9858 : : {
9859 [ # # ]: 0 : uint32_t tag_mask = flow_hw_tx_tag_regc_mask(dev);
9860 : 0 : uint32_t tag_value = flow_hw_tx_tag_regc_value(dev);
9861 : 0 : struct rte_flow_actions_template_attr attr = {
9862 : : .egress = 1,
9863 : : };
9864 [ # # ]: 0 : struct rte_flow_action_modify_field set_tag_v = {
9865 : : .operation = RTE_FLOW_MODIFY_SET,
9866 : : .dst = {
9867 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
9868 : : .tag_index = REG_C_0,
9869 : : .offset = rte_bsf32(tag_mask),
9870 : : },
9871 : : .src = {
9872 : : .field = RTE_FLOW_FIELD_VALUE,
9873 : : },
9874 : : .width = rte_popcount32(tag_mask),
9875 : : };
9876 : 0 : struct rte_flow_action_modify_field set_tag_m = {
9877 : : .operation = RTE_FLOW_MODIFY_SET,
9878 : : .dst = {
9879 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
9880 : : .level = UINT8_MAX,
9881 : : .tag_index = UINT8_MAX,
9882 : : .offset = UINT32_MAX,
9883 : : },
9884 : : .src = {
9885 : : .field = RTE_FLOW_FIELD_VALUE,
9886 : : },
9887 : : .width = UINT32_MAX,
9888 : : };
9889 : 0 : struct rte_flow_action_modify_field copy_metadata_v = {
9890 : : .operation = RTE_FLOW_MODIFY_SET,
9891 : : .dst = {
9892 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
9893 : : .tag_index = REG_C_1,
9894 : : },
9895 : : .src = {
9896 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
9897 : : .tag_index = REG_A,
9898 : : },
9899 : : .width = 32,
9900 : : };
9901 : 0 : struct rte_flow_action_modify_field copy_metadata_m = {
9902 : : .operation = RTE_FLOW_MODIFY_SET,
9903 : : .dst = {
9904 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
9905 : : .level = UINT8_MAX,
9906 : : .tag_index = UINT8_MAX,
9907 : : .offset = UINT32_MAX,
9908 : : },
9909 : : .src = {
9910 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
9911 : : .level = UINT8_MAX,
9912 : : .tag_index = UINT8_MAX,
9913 : : .offset = UINT32_MAX,
9914 : : },
9915 : : .width = UINT32_MAX,
9916 : : };
9917 : 0 : struct rte_flow_action_jump jump_v = {
9918 : : .group = MLX5_HW_LOWEST_USABLE_GROUP,
9919 : : };
9920 : 0 : struct rte_flow_action_jump jump_m = {
9921 : : .group = UINT32_MAX,
9922 : : };
9923 : 0 : struct rte_flow_action actions_v[4] = { { 0 } };
9924 [ # # ]: 0 : struct rte_flow_action actions_m[4] = { { 0 } };
9925 : : unsigned int idx = 0;
9926 : :
9927 : : rte_memcpy(set_tag_v.src.value, &tag_value, sizeof(tag_value));
9928 : : rte_memcpy(set_tag_m.src.value, &tag_mask, sizeof(tag_mask));
9929 : : flow_hw_update_action_mask(&actions_v[idx], &actions_m[idx],
9930 : : RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
9931 : : &set_tag_v, &set_tag_m);
9932 : : idx++;
9933 [ # # ]: 0 : if (MLX5_SH(dev)->config.dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS) {
9934 : : flow_hw_update_action_mask(&actions_v[idx], &actions_m[idx],
9935 : : RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
9936 : : ©_metadata_v, ©_metadata_m);
9937 : : idx++;
9938 : : }
9939 : : flow_hw_update_action_mask(&actions_v[idx], &actions_m[idx], RTE_FLOW_ACTION_TYPE_JUMP,
9940 : : &jump_v, &jump_m);
9941 : 0 : idx++;
9942 : : flow_hw_update_action_mask(&actions_v[idx], &actions_m[idx], RTE_FLOW_ACTION_TYPE_END,
9943 : : NULL, NULL);
9944 : : idx++;
9945 : : MLX5_ASSERT(idx <= RTE_DIM(actions_v));
9946 : 0 : return flow_hw_actions_template_create(dev, &attr, actions_v, actions_m, error);
9947 : : }
9948 : :
9949 : : static void
9950 : 0 : flow_hw_cleanup_tx_repr_tagging(struct rte_eth_dev *dev)
9951 : : {
9952 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
9953 : :
9954 [ # # ]: 0 : if (priv->hw_tx_repr_tagging_tbl) {
9955 : 0 : flow_hw_table_destroy(dev, priv->hw_tx_repr_tagging_tbl, NULL);
9956 : 0 : priv->hw_tx_repr_tagging_tbl = NULL;
9957 : : }
9958 [ # # ]: 0 : if (priv->hw_tx_repr_tagging_at) {
9959 : 0 : flow_hw_actions_template_destroy(dev, priv->hw_tx_repr_tagging_at, NULL);
9960 : 0 : priv->hw_tx_repr_tagging_at = NULL;
9961 : : }
9962 [ # # ]: 0 : if (priv->hw_tx_repr_tagging_pt) {
9963 : 0 : flow_hw_pattern_template_destroy(dev, priv->hw_tx_repr_tagging_pt, NULL);
9964 : 0 : priv->hw_tx_repr_tagging_pt = NULL;
9965 : : }
9966 : 0 : }
9967 : :
9968 : : /**
9969 : : * Setup templates and table used to create default Tx flow rules. These default rules
9970 : : * allow for matching Tx representor traffic using a vport tag placed in unused bits of
9971 : : * REG_C_0 register.
9972 : : *
9973 : : * @param dev
9974 : : * Pointer to Ethernet device.
9975 : : * @param[out] error
9976 : : * Pointer to error structure.
9977 : : *
9978 : : * @return
9979 : : * 0 on success, negative errno value otherwise.
9980 : : */
9981 : : static int
9982 : 0 : flow_hw_setup_tx_repr_tagging(struct rte_eth_dev *dev, struct rte_flow_error *error)
9983 : : {
9984 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
9985 : 0 : struct rte_flow_template_table_attr attr = {
9986 : : .flow_attr = {
9987 : : .group = 0,
9988 : : .priority = MLX5_HW_LOWEST_PRIO_ROOT,
9989 : : .egress = 1,
9990 : : },
9991 : : .nb_flows = MLX5_HW_CTRL_FLOW_NB_RULES,
9992 : : };
9993 : 0 : struct mlx5_flow_template_table_cfg cfg = {
9994 : : .attr = attr,
9995 : : .external = false,
9996 : : };
9997 : :
9998 : : MLX5_ASSERT(priv->sh->config.dv_esw_en);
9999 : : MLX5_ASSERT(priv->sh->config.repr_matching);
10000 : 0 : priv->hw_tx_repr_tagging_pt =
10001 : 0 : flow_hw_create_tx_repr_sq_pattern_tmpl(dev, error);
10002 [ # # ]: 0 : if (!priv->hw_tx_repr_tagging_pt)
10003 : 0 : goto err;
10004 : 0 : priv->hw_tx_repr_tagging_at =
10005 : 0 : flow_hw_create_tx_repr_tag_jump_acts_tmpl(dev, error);
10006 [ # # ]: 0 : if (!priv->hw_tx_repr_tagging_at)
10007 : 0 : goto err;
10008 : 0 : priv->hw_tx_repr_tagging_tbl = flow_hw_table_create(dev, &cfg,
10009 : : &priv->hw_tx_repr_tagging_pt, 1,
10010 : : &priv->hw_tx_repr_tagging_at, 1,
10011 : : error);
10012 [ # # ]: 0 : if (!priv->hw_tx_repr_tagging_tbl)
10013 : 0 : goto err;
10014 : : return 0;
10015 : 0 : err:
10016 : 0 : flow_hw_cleanup_tx_repr_tagging(dev);
10017 : 0 : return -rte_errno;
10018 : : }
10019 : :
10020 : : static uint32_t
10021 : : flow_hw_esw_mgr_regc_marker_mask(struct rte_eth_dev *dev)
10022 : : {
10023 : 0 : uint32_t mask = MLX5_SH(dev)->dv_regc0_mask;
10024 : :
10025 : : /* Mask is verified during device initialization. */
10026 : : MLX5_ASSERT(mask != 0);
10027 : : return mask;
10028 : : }
10029 : :
10030 : : static uint32_t
10031 : : flow_hw_esw_mgr_regc_marker(struct rte_eth_dev *dev)
10032 : : {
10033 : 0 : uint32_t mask = MLX5_SH(dev)->dv_regc0_mask;
10034 : :
10035 : : /* Mask is verified during device initialization. */
10036 : : MLX5_ASSERT(mask != 0);
10037 : 0 : return RTE_BIT32(rte_bsf32(mask));
10038 : : }
10039 : :
10040 : : /**
10041 : : * Creates a flow pattern template used to match on E-Switch Manager.
10042 : : * This template is used to set up a table for SQ miss default flow.
10043 : : *
10044 : : * @param dev
10045 : : * Pointer to Ethernet device.
10046 : : * @param error
10047 : : * Pointer to error structure.
10048 : : *
10049 : : * @return
10050 : : * Pointer to flow pattern template on success, NULL otherwise.
10051 : : */
10052 : : static struct rte_flow_pattern_template *
10053 : 0 : flow_hw_create_ctrl_esw_mgr_pattern_template(struct rte_eth_dev *dev,
10054 : : struct rte_flow_error *error)
10055 : : {
10056 : 0 : struct rte_flow_pattern_template_attr attr = {
10057 : : .relaxed_matching = 0,
10058 : : .transfer = 1,
10059 : : };
10060 : 0 : struct rte_flow_item_ethdev port_spec = {
10061 : : .port_id = MLX5_REPRESENTED_PORT_ESW_MGR,
10062 : : };
10063 : 0 : struct rte_flow_item_ethdev port_mask = {
10064 : : .port_id = UINT16_MAX,
10065 : : };
10066 : 0 : struct mlx5_rte_flow_item_sq sq_mask = {
10067 : : .queue = UINT32_MAX,
10068 : : };
10069 : 0 : struct rte_flow_item items[] = {
10070 : : {
10071 : : .type = RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT,
10072 : : .spec = &port_spec,
10073 : : .mask = &port_mask,
10074 : : },
10075 : : {
10076 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_SQ,
10077 : : .mask = &sq_mask,
10078 : : },
10079 : : {
10080 : : .type = RTE_FLOW_ITEM_TYPE_END,
10081 : : },
10082 : : };
10083 : :
10084 : 0 : return flow_hw_pattern_template_create(dev, &attr, items, error);
10085 : : }
10086 : :
10087 : : /**
10088 : : * Creates a flow pattern template used to match REG_C_0 and a SQ.
10089 : : * Matching on REG_C_0 is set up to match on all bits usable by user-space.
10090 : : * If traffic was sent from E-Switch Manager, then all usable bits will be set to 0,
10091 : : * except the least significant bit, which will be set to 1.
10092 : : *
10093 : : * This template is used to set up a table for SQ miss default flow.
10094 : : *
10095 : : * @param dev
10096 : : * Pointer to Ethernet device.
10097 : : * @param error
10098 : : * Pointer to error structure.
10099 : : *
10100 : : * @return
10101 : : * Pointer to flow pattern template on success, NULL otherwise.
10102 : : */
10103 : : static struct rte_flow_pattern_template *
10104 : 0 : flow_hw_create_ctrl_regc_sq_pattern_template(struct rte_eth_dev *dev,
10105 : : struct rte_flow_error *error)
10106 : : {
10107 : 0 : struct rte_flow_pattern_template_attr attr = {
10108 : : .relaxed_matching = 0,
10109 : : .transfer = 1,
10110 : : };
10111 : 0 : struct rte_flow_item_tag reg_c0_spec = {
10112 : : .index = (uint8_t)REG_C_0,
10113 : : };
10114 : 0 : struct rte_flow_item_tag reg_c0_mask = {
10115 : : .index = 0xff,
10116 : : .data = flow_hw_esw_mgr_regc_marker_mask(dev),
10117 : : };
10118 : 0 : struct mlx5_rte_flow_item_sq queue_mask = {
10119 : : .queue = UINT32_MAX,
10120 : : };
10121 : 0 : struct rte_flow_item items[] = {
10122 : : {
10123 : : .type = (enum rte_flow_item_type)
10124 : : MLX5_RTE_FLOW_ITEM_TYPE_TAG,
10125 : : .spec = ®_c0_spec,
10126 : : .mask = ®_c0_mask,
10127 : : },
10128 : : {
10129 : : .type = (enum rte_flow_item_type)
10130 : : MLX5_RTE_FLOW_ITEM_TYPE_SQ,
10131 : : .mask = &queue_mask,
10132 : : },
10133 : : {
10134 : : .type = RTE_FLOW_ITEM_TYPE_END,
10135 : : },
10136 : : };
10137 : :
10138 : 0 : return flow_hw_pattern_template_create(dev, &attr, items, error);
10139 : : }
10140 : :
10141 : : /**
10142 : : * Creates a flow pattern template with unmasked represented port matching.
10143 : : * This template is used to set up a table for default transfer flows
10144 : : * directing packets to group 1.
10145 : : *
10146 : : * @param dev
10147 : : * Pointer to Ethernet device.
10148 : : * @param error
10149 : : * Pointer to error structure.
10150 : : *
10151 : : * @return
10152 : : * Pointer to flow pattern template on success, NULL otherwise.
10153 : : */
10154 : : static struct rte_flow_pattern_template *
10155 : 0 : flow_hw_create_ctrl_port_pattern_template(struct rte_eth_dev *dev,
10156 : : struct rte_flow_error *error)
10157 : : {
10158 : 0 : struct rte_flow_pattern_template_attr attr = {
10159 : : .relaxed_matching = 0,
10160 : : .transfer = 1,
10161 : : };
10162 : 0 : struct rte_flow_item_ethdev port_mask = {
10163 : : .port_id = UINT16_MAX,
10164 : : };
10165 : 0 : struct rte_flow_item items[] = {
10166 : : {
10167 : : .type = RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT,
10168 : : .mask = &port_mask,
10169 : : },
10170 : : {
10171 : : .type = RTE_FLOW_ITEM_TYPE_END,
10172 : : },
10173 : : };
10174 : :
10175 : 0 : return flow_hw_pattern_template_create(dev, &attr, items, error);
10176 : : }
10177 : :
10178 : : /*
10179 : : * Creating a flow pattern template with all ETH packets matching.
10180 : : * This template is used to set up a table for default Tx copy (Tx metadata
10181 : : * to REG_C_1) flow rule usage.
10182 : : *
10183 : : * @param dev
10184 : : * Pointer to Ethernet device.
10185 : : * @param error
10186 : : * Pointer to error structure.
10187 : : *
10188 : : * @return
10189 : : * Pointer to flow pattern template on success, NULL otherwise.
10190 : : */
10191 : : static struct rte_flow_pattern_template *
10192 : 0 : flow_hw_create_tx_default_mreg_copy_pattern_template(struct rte_eth_dev *dev,
10193 : : struct rte_flow_error *error)
10194 : : {
10195 : 0 : struct rte_flow_pattern_template_attr tx_pa_attr = {
10196 : : .relaxed_matching = 0,
10197 : : .egress = 1,
10198 : : };
10199 : 0 : struct rte_flow_item_eth promisc = {
10200 : : .hdr.dst_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
10201 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
10202 : : .hdr.ether_type = 0,
10203 : : };
10204 : 0 : struct rte_flow_item eth_all[] = {
10205 : : [0] = {
10206 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
10207 : : .spec = &promisc,
10208 : : .mask = &promisc,
10209 : : },
10210 : : [1] = {
10211 : : .type = RTE_FLOW_ITEM_TYPE_END,
10212 : : },
10213 : : };
10214 : :
10215 : 0 : return flow_hw_pattern_template_create(dev, &tx_pa_attr, eth_all, error);
10216 : : }
10217 : :
10218 : : /*
10219 : : * Creating a flow pattern template with all LACP packets matching, only for NIC
10220 : : * ingress domain.
10221 : : *
10222 : : * @param dev
10223 : : * Pointer to Ethernet device.
10224 : : * @param error
10225 : : * Pointer to error structure.
10226 : : *
10227 : : * @return
10228 : : * Pointer to flow pattern template on success, NULL otherwise.
10229 : : */
10230 : : static struct rte_flow_pattern_template *
10231 : 0 : flow_hw_create_lacp_rx_pattern_template(struct rte_eth_dev *dev, struct rte_flow_error *error)
10232 : : {
10233 : 0 : struct rte_flow_pattern_template_attr pa_attr = {
10234 : : .relaxed_matching = 0,
10235 : : .ingress = 1,
10236 : : };
10237 : 0 : struct rte_flow_item_eth lacp_mask = {
10238 : : .dst.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
10239 : : .src.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
10240 : : .type = 0xFFFF,
10241 : : };
10242 : 0 : struct rte_flow_item eth_all[] = {
10243 : : [0] = {
10244 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
10245 : : .mask = &lacp_mask,
10246 : : },
10247 : : [1] = {
10248 : : .type = RTE_FLOW_ITEM_TYPE_END,
10249 : : },
10250 : : };
10251 : 0 : return flow_hw_pattern_template_create(dev, &pa_attr, eth_all, error);
10252 : : }
10253 : :
10254 : : /**
10255 : : * Creates a flow actions template with modify field action and masked jump action.
10256 : : * Modify field action sets the least significant bit of REG_C_0 (usable by user-space)
10257 : : * to 1, meaning that packet was originated from E-Switch Manager. Jump action
10258 : : * transfers steering to group 1.
10259 : : *
10260 : : * @param dev
10261 : : * Pointer to Ethernet device.
10262 : : * @param error
10263 : : * Pointer to error structure.
10264 : : *
10265 : : * @return
10266 : : * Pointer to flow actions template on success, NULL otherwise.
10267 : : */
10268 : : static struct rte_flow_actions_template *
10269 : 0 : flow_hw_create_ctrl_regc_jump_actions_template(struct rte_eth_dev *dev,
10270 : : struct rte_flow_error *error)
10271 : : {
10272 [ # # ]: 0 : uint32_t marker_mask = flow_hw_esw_mgr_regc_marker_mask(dev);
10273 : 0 : uint32_t marker_bits = flow_hw_esw_mgr_regc_marker(dev);
10274 : 0 : struct rte_flow_actions_template_attr attr = {
10275 : : .transfer = 1,
10276 : : };
10277 [ # # ]: 0 : struct rte_flow_action_modify_field set_reg_v = {
10278 : : .operation = RTE_FLOW_MODIFY_SET,
10279 : : .dst = {
10280 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
10281 : : .tag_index = REG_C_0,
10282 : : },
10283 : : .src = {
10284 : : .field = RTE_FLOW_FIELD_VALUE,
10285 : : },
10286 : : .width = rte_popcount32(marker_mask),
10287 : : };
10288 : 0 : struct rte_flow_action_modify_field set_reg_m = {
10289 : : .operation = RTE_FLOW_MODIFY_SET,
10290 : : .dst = {
10291 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
10292 : : .level = UINT8_MAX,
10293 : : .tag_index = UINT8_MAX,
10294 : : .offset = UINT32_MAX,
10295 : : },
10296 : : .src = {
10297 : : .field = RTE_FLOW_FIELD_VALUE,
10298 : : },
10299 : : .width = UINT32_MAX,
10300 : : };
10301 : 0 : struct rte_flow_action_jump jump_v = {
10302 : : .group = MLX5_HW_LOWEST_USABLE_GROUP,
10303 : : };
10304 : 0 : struct rte_flow_action_jump jump_m = {
10305 : : .group = UINT32_MAX,
10306 : : };
10307 : 0 : struct rte_flow_action actions_v[] = {
10308 : : {
10309 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
10310 : : .conf = &set_reg_v,
10311 : : },
10312 : : {
10313 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
10314 : : .conf = &jump_v,
10315 : : },
10316 : : {
10317 : : .type = RTE_FLOW_ACTION_TYPE_END,
10318 : : }
10319 : : };
10320 : 0 : struct rte_flow_action actions_m[] = {
10321 : : {
10322 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
10323 : : .conf = &set_reg_m,
10324 : : },
10325 : : {
10326 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
10327 : : .conf = &jump_m,
10328 : : },
10329 : : {
10330 : : .type = RTE_FLOW_ACTION_TYPE_END,
10331 : : }
10332 : : };
10333 : :
10334 [ # # ]: 0 : set_reg_v.dst.offset = rte_bsf32(marker_mask);
10335 : : rte_memcpy(set_reg_v.src.value, &marker_bits, sizeof(marker_bits));
10336 : : rte_memcpy(set_reg_m.src.value, &marker_mask, sizeof(marker_mask));
10337 : 0 : return flow_hw_actions_template_create(dev, &attr, actions_v, actions_m, error);
10338 : : }
10339 : :
10340 : : /**
10341 : : * Creates a flow actions template with an unmasked JUMP action. Flows
10342 : : * based on this template will perform a jump to some group. This template
10343 : : * is used to set up tables for control flows.
10344 : : *
10345 : : * @param dev
10346 : : * Pointer to Ethernet device.
10347 : : * @param group
10348 : : * Destination group for this action template.
10349 : : * @param error
10350 : : * Pointer to error structure.
10351 : : *
10352 : : * @return
10353 : : * Pointer to flow actions template on success, NULL otherwise.
10354 : : */
10355 : : static struct rte_flow_actions_template *
10356 : 0 : flow_hw_create_ctrl_jump_actions_template(struct rte_eth_dev *dev,
10357 : : uint32_t group,
10358 : : struct rte_flow_error *error)
10359 : : {
10360 : 0 : struct rte_flow_actions_template_attr attr = {
10361 : : .transfer = 1,
10362 : : };
10363 : 0 : struct rte_flow_action_jump jump_v = {
10364 : : .group = group,
10365 : : };
10366 : 0 : struct rte_flow_action_jump jump_m = {
10367 : : .group = UINT32_MAX,
10368 : : };
10369 : 0 : struct rte_flow_action actions_v[] = {
10370 : : {
10371 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
10372 : : .conf = &jump_v,
10373 : : },
10374 : : {
10375 : : .type = RTE_FLOW_ACTION_TYPE_END,
10376 : : }
10377 : : };
10378 : 0 : struct rte_flow_action actions_m[] = {
10379 : : {
10380 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
10381 : : .conf = &jump_m,
10382 : : },
10383 : : {
10384 : : .type = RTE_FLOW_ACTION_TYPE_END,
10385 : : }
10386 : : };
10387 : :
10388 : 0 : return flow_hw_actions_template_create(dev, &attr, actions_v,
10389 : : actions_m, error);
10390 : : }
10391 : :
10392 : : /**
10393 : : * Creates a flow action template with a unmasked REPRESENTED_PORT action.
10394 : : * It is used to create control flow tables.
10395 : : *
10396 : : * @param dev
10397 : : * Pointer to Ethernet device.
10398 : : * @param error
10399 : : * Pointer to error structure.
10400 : : *
10401 : : * @return
10402 : : * Pointer to flow action template on success, NULL otherwise.
10403 : : */
10404 : : static struct rte_flow_actions_template *
10405 : 0 : flow_hw_create_ctrl_port_actions_template(struct rte_eth_dev *dev,
10406 : : struct rte_flow_error *error)
10407 : : {
10408 : 0 : struct rte_flow_actions_template_attr attr = {
10409 : : .transfer = 1,
10410 : : };
10411 : 0 : struct rte_flow_action_ethdev port_v = {
10412 : : .port_id = 0,
10413 : : };
10414 : 0 : struct rte_flow_action actions_v[] = {
10415 : : {
10416 : : .type = RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT,
10417 : : .conf = &port_v,
10418 : : },
10419 : : {
10420 : : .type = RTE_FLOW_ACTION_TYPE_END,
10421 : : }
10422 : : };
10423 : 0 : struct rte_flow_action_ethdev port_m = {
10424 : : .port_id = 0,
10425 : : };
10426 : 0 : struct rte_flow_action actions_m[] = {
10427 : : {
10428 : : .type = RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT,
10429 : : .conf = &port_m,
10430 : : },
10431 : : {
10432 : : .type = RTE_FLOW_ACTION_TYPE_END,
10433 : : }
10434 : : };
10435 : :
10436 : 0 : return flow_hw_actions_template_create(dev, &attr, actions_v, actions_m, error);
10437 : : }
10438 : :
10439 : : /*
10440 : : * Creating an actions template to use header modify action for register
10441 : : * copying. This template is used to set up a table for copy flow.
10442 : : *
10443 : : * @param dev
10444 : : * Pointer to Ethernet device.
10445 : : * @param error
10446 : : * Pointer to error structure.
10447 : : *
10448 : : * @return
10449 : : * Pointer to flow actions template on success, NULL otherwise.
10450 : : */
10451 : : static struct rte_flow_actions_template *
10452 : 0 : flow_hw_create_tx_default_mreg_copy_actions_template(struct rte_eth_dev *dev,
10453 : : struct rte_flow_error *error)
10454 : : {
10455 : 0 : struct rte_flow_actions_template_attr tx_act_attr = {
10456 : : .egress = 1,
10457 : : };
10458 : 0 : const struct rte_flow_action_modify_field mreg_action = {
10459 : : .operation = RTE_FLOW_MODIFY_SET,
10460 : : .dst = {
10461 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
10462 : : .tag_index = REG_C_1,
10463 : : },
10464 : : .src = {
10465 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
10466 : : .tag_index = REG_A,
10467 : : },
10468 : : .width = 32,
10469 : : };
10470 : 0 : const struct rte_flow_action_modify_field mreg_mask = {
10471 : : .operation = RTE_FLOW_MODIFY_SET,
10472 : : .dst = {
10473 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
10474 : : .level = UINT8_MAX,
10475 : : .tag_index = UINT8_MAX,
10476 : : .offset = UINT32_MAX,
10477 : : },
10478 : : .src = {
10479 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
10480 : : .level = UINT8_MAX,
10481 : : .tag_index = UINT8_MAX,
10482 : : .offset = UINT32_MAX,
10483 : : },
10484 : : .width = UINT32_MAX,
10485 : : };
10486 : 0 : const struct rte_flow_action_jump jump_action = {
10487 : : .group = 1,
10488 : : };
10489 : 0 : const struct rte_flow_action_jump jump_mask = {
10490 : : .group = UINT32_MAX,
10491 : : };
10492 : 0 : const struct rte_flow_action actions[] = {
10493 : : [0] = {
10494 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
10495 : : .conf = &mreg_action,
10496 : : },
10497 : : [1] = {
10498 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
10499 : : .conf = &jump_action,
10500 : : },
10501 : : [2] = {
10502 : : .type = RTE_FLOW_ACTION_TYPE_END,
10503 : : },
10504 : : };
10505 : 0 : const struct rte_flow_action masks[] = {
10506 : : [0] = {
10507 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
10508 : : .conf = &mreg_mask,
10509 : : },
10510 : : [1] = {
10511 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
10512 : : .conf = &jump_mask,
10513 : : },
10514 : : [2] = {
10515 : : .type = RTE_FLOW_ACTION_TYPE_END,
10516 : : },
10517 : : };
10518 : :
10519 : 0 : return flow_hw_actions_template_create(dev, &tx_act_attr, actions,
10520 : : masks, error);
10521 : : }
10522 : :
10523 : : /*
10524 : : * Creating an actions template to use default miss to re-route packets to the
10525 : : * kernel driver stack.
10526 : : * On root table, only DEFAULT_MISS action can be used.
10527 : : *
10528 : : * @param dev
10529 : : * Pointer to Ethernet device.
10530 : : * @param error
10531 : : * Pointer to error structure.
10532 : : *
10533 : : * @return
10534 : : * Pointer to flow actions template on success, NULL otherwise.
10535 : : */
10536 : : static struct rte_flow_actions_template *
10537 : 0 : flow_hw_create_lacp_rx_actions_template(struct rte_eth_dev *dev, struct rte_flow_error *error)
10538 : : {
10539 : 0 : struct rte_flow_actions_template_attr act_attr = {
10540 : : .ingress = 1,
10541 : : };
10542 : 0 : const struct rte_flow_action actions[] = {
10543 : : [0] = {
10544 : : .type = (enum rte_flow_action_type)
10545 : : MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS,
10546 : : },
10547 : : [1] = {
10548 : : .type = RTE_FLOW_ACTION_TYPE_END,
10549 : : },
10550 : : };
10551 : :
10552 : 0 : return flow_hw_actions_template_create(dev, &act_attr, actions, actions, error);
10553 : : }
10554 : :
10555 : : /**
10556 : : * Creates a control flow table used to transfer traffic from E-Switch Manager
10557 : : * and TX queues from group 0 to group 1.
10558 : : *
10559 : : * @param dev
10560 : : * Pointer to Ethernet device.
10561 : : * @param it
10562 : : * Pointer to flow pattern template.
10563 : : * @param at
10564 : : * Pointer to flow actions template.
10565 : : * @param error
10566 : : * Pointer to error structure.
10567 : : *
10568 : : * @return
10569 : : * Pointer to flow table on success, NULL otherwise.
10570 : : */
10571 : : static struct rte_flow_template_table*
10572 : 0 : flow_hw_create_ctrl_sq_miss_root_table(struct rte_eth_dev *dev,
10573 : : struct rte_flow_pattern_template *it,
10574 : : struct rte_flow_actions_template *at,
10575 : : struct rte_flow_error *error)
10576 : : {
10577 : 0 : struct rte_flow_template_table_attr attr = {
10578 : : .flow_attr = {
10579 : : .group = 0,
10580 : : .priority = MLX5_HW_LOWEST_PRIO_ROOT,
10581 : : .ingress = 0,
10582 : : .egress = 0,
10583 : : .transfer = 1,
10584 : : },
10585 : : .nb_flows = MLX5_HW_CTRL_FLOW_NB_RULES,
10586 : : };
10587 : 0 : struct mlx5_flow_template_table_cfg cfg = {
10588 : : .attr = attr,
10589 : : .external = false,
10590 : : };
10591 : :
10592 : 0 : return flow_hw_table_create(dev, &cfg, &it, 1, &at, 1, error);
10593 : : }
10594 : :
10595 : :
10596 : : /**
10597 : : * Creates a control flow table used to transfer traffic from E-Switch Manager
10598 : : * and TX queues from group 0 to group 1.
10599 : : *
10600 : : * @param dev
10601 : : * Pointer to Ethernet device.
10602 : : * @param it
10603 : : * Pointer to flow pattern template.
10604 : : * @param at
10605 : : * Pointer to flow actions template.
10606 : : * @param error
10607 : : * Pointer to error structure.
10608 : : *
10609 : : * @return
10610 : : * Pointer to flow table on success, NULL otherwise.
10611 : : */
10612 : : static struct rte_flow_template_table*
10613 : 0 : flow_hw_create_ctrl_sq_miss_table(struct rte_eth_dev *dev,
10614 : : struct rte_flow_pattern_template *it,
10615 : : struct rte_flow_actions_template *at,
10616 : : struct rte_flow_error *error)
10617 : : {
10618 : 0 : struct rte_flow_template_table_attr attr = {
10619 : : .flow_attr = {
10620 : : .group = 1,
10621 : : .priority = MLX5_HW_LOWEST_PRIO_NON_ROOT,
10622 : : .ingress = 0,
10623 : : .egress = 0,
10624 : : .transfer = 1,
10625 : : },
10626 : : .nb_flows = MLX5_HW_CTRL_FLOW_NB_RULES,
10627 : : };
10628 : 0 : struct mlx5_flow_template_table_cfg cfg = {
10629 : : .attr = attr,
10630 : : .external = false,
10631 : : };
10632 : :
10633 : 0 : return flow_hw_table_create(dev, &cfg, &it, 1, &at, 1, error);
10634 : : }
10635 : :
10636 : : /*
10637 : : * Creating the default Tx metadata copy table on NIC Tx group 0.
10638 : : *
10639 : : * @param dev
10640 : : * Pointer to Ethernet device.
10641 : : * @param pt
10642 : : * Pointer to flow pattern template.
10643 : : * @param at
10644 : : * Pointer to flow actions template.
10645 : : * @param error
10646 : : * Pointer to error structure.
10647 : : *
10648 : : * @return
10649 : : * Pointer to flow table on success, NULL otherwise.
10650 : : */
10651 : : static struct rte_flow_template_table*
10652 : 0 : flow_hw_create_tx_default_mreg_copy_table(struct rte_eth_dev *dev,
10653 : : struct rte_flow_pattern_template *pt,
10654 : : struct rte_flow_actions_template *at,
10655 : : struct rte_flow_error *error)
10656 : : {
10657 : 0 : struct rte_flow_template_table_attr tx_tbl_attr = {
10658 : : .flow_attr = {
10659 : : .group = 0, /* Root */
10660 : : .priority = MLX5_HW_LOWEST_PRIO_ROOT,
10661 : : .egress = 1,
10662 : : },
10663 : : .nb_flows = 1, /* One default flow rule for all. */
10664 : : };
10665 : 0 : struct mlx5_flow_template_table_cfg tx_tbl_cfg = {
10666 : : .attr = tx_tbl_attr,
10667 : : .external = false,
10668 : : };
10669 : :
10670 : 0 : return flow_hw_table_create(dev, &tx_tbl_cfg, &pt, 1, &at, 1, error);
10671 : : }
10672 : :
10673 : : /**
10674 : : * Creates a control flow table used to transfer traffic
10675 : : * from group 0 to group 1.
10676 : : *
10677 : : * @param dev
10678 : : * Pointer to Ethernet device.
10679 : : * @param it
10680 : : * Pointer to flow pattern template.
10681 : : * @param at
10682 : : * Pointer to flow actions template.
10683 : : * @param error
10684 : : * Pointer to error structure.
10685 : : *
10686 : : * @return
10687 : : * Pointer to flow table on success, NULL otherwise.
10688 : : */
10689 : : static struct rte_flow_template_table *
10690 : 0 : flow_hw_create_ctrl_jump_table(struct rte_eth_dev *dev,
10691 : : struct rte_flow_pattern_template *it,
10692 : : struct rte_flow_actions_template *at,
10693 : : struct rte_flow_error *error)
10694 : : {
10695 : 0 : struct rte_flow_template_table_attr attr = {
10696 : : .flow_attr = {
10697 : : .group = 0,
10698 : : .priority = 0,
10699 : : .ingress = 0,
10700 : : .egress = 0,
10701 : : .transfer = 1,
10702 : : },
10703 : : .nb_flows = MLX5_HW_CTRL_FLOW_NB_RULES,
10704 : : };
10705 : 0 : struct mlx5_flow_template_table_cfg cfg = {
10706 : : .attr = attr,
10707 : : .external = false,
10708 : : };
10709 : :
10710 : 0 : return flow_hw_table_create(dev, &cfg, &it, 1, &at, 1, error);
10711 : : }
10712 : :
10713 : : /**
10714 : : * Cleans up all template tables and pattern, and actions templates used for
10715 : : * FDB control flow rules.
10716 : : *
10717 : : * @param dev
10718 : : * Pointer to Ethernet device.
10719 : : */
10720 : : static void
10721 : 0 : flow_hw_cleanup_ctrl_fdb_tables(struct rte_eth_dev *dev)
10722 : : {
10723 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
10724 : : struct mlx5_flow_hw_ctrl_fdb *hw_ctrl_fdb;
10725 : :
10726 [ # # ]: 0 : if (!priv->hw_ctrl_fdb)
10727 : : return;
10728 : : hw_ctrl_fdb = priv->hw_ctrl_fdb;
10729 : : /* Clean up templates used for LACP default miss table. */
10730 [ # # ]: 0 : if (hw_ctrl_fdb->hw_lacp_rx_tbl)
10731 : 0 : claim_zero(flow_hw_table_destroy(dev, hw_ctrl_fdb->hw_lacp_rx_tbl, NULL));
10732 [ # # ]: 0 : if (hw_ctrl_fdb->lacp_rx_actions_tmpl)
10733 : 0 : claim_zero(flow_hw_actions_template_destroy(dev, hw_ctrl_fdb->lacp_rx_actions_tmpl,
10734 : : NULL));
10735 [ # # ]: 0 : if (hw_ctrl_fdb->lacp_rx_items_tmpl)
10736 : 0 : claim_zero(flow_hw_pattern_template_destroy(dev, hw_ctrl_fdb->lacp_rx_items_tmpl,
10737 : : NULL));
10738 : : /* Clean up templates used for default Tx metadata copy. */
10739 [ # # ]: 0 : if (hw_ctrl_fdb->hw_tx_meta_cpy_tbl)
10740 : 0 : claim_zero(flow_hw_table_destroy(dev, hw_ctrl_fdb->hw_tx_meta_cpy_tbl, NULL));
10741 [ # # ]: 0 : if (hw_ctrl_fdb->tx_meta_actions_tmpl)
10742 : 0 : claim_zero(flow_hw_actions_template_destroy(dev, hw_ctrl_fdb->tx_meta_actions_tmpl,
10743 : : NULL));
10744 [ # # ]: 0 : if (hw_ctrl_fdb->tx_meta_items_tmpl)
10745 : 0 : claim_zero(flow_hw_pattern_template_destroy(dev, hw_ctrl_fdb->tx_meta_items_tmpl,
10746 : : NULL));
10747 : : /* Clean up templates used for default FDB jump rule. */
10748 [ # # ]: 0 : if (hw_ctrl_fdb->hw_esw_zero_tbl)
10749 : 0 : claim_zero(flow_hw_table_destroy(dev, hw_ctrl_fdb->hw_esw_zero_tbl, NULL));
10750 [ # # ]: 0 : if (hw_ctrl_fdb->jump_one_actions_tmpl)
10751 : 0 : claim_zero(flow_hw_actions_template_destroy(dev, hw_ctrl_fdb->jump_one_actions_tmpl,
10752 : : NULL));
10753 [ # # ]: 0 : if (hw_ctrl_fdb->port_items_tmpl)
10754 : 0 : claim_zero(flow_hw_pattern_template_destroy(dev, hw_ctrl_fdb->port_items_tmpl,
10755 : : NULL));
10756 : : /* Clean up templates used for default SQ miss flow rules - non-root table. */
10757 [ # # ]: 0 : if (hw_ctrl_fdb->hw_esw_sq_miss_tbl)
10758 : 0 : claim_zero(flow_hw_table_destroy(dev, hw_ctrl_fdb->hw_esw_sq_miss_tbl, NULL));
10759 [ # # ]: 0 : if (hw_ctrl_fdb->regc_sq_items_tmpl)
10760 : 0 : claim_zero(flow_hw_pattern_template_destroy(dev, hw_ctrl_fdb->regc_sq_items_tmpl,
10761 : : NULL));
10762 [ # # ]: 0 : if (hw_ctrl_fdb->port_actions_tmpl)
10763 : 0 : claim_zero(flow_hw_actions_template_destroy(dev, hw_ctrl_fdb->port_actions_tmpl,
10764 : : NULL));
10765 : : /* Clean up templates used for default SQ miss flow rules - root table. */
10766 [ # # ]: 0 : if (hw_ctrl_fdb->hw_esw_sq_miss_root_tbl)
10767 : 0 : claim_zero(flow_hw_table_destroy(dev, hw_ctrl_fdb->hw_esw_sq_miss_root_tbl, NULL));
10768 [ # # ]: 0 : if (hw_ctrl_fdb->regc_jump_actions_tmpl)
10769 : 0 : claim_zero(flow_hw_actions_template_destroy(dev,
10770 : : hw_ctrl_fdb->regc_jump_actions_tmpl, NULL));
10771 [ # # ]: 0 : if (hw_ctrl_fdb->esw_mgr_items_tmpl)
10772 : 0 : claim_zero(flow_hw_pattern_template_destroy(dev, hw_ctrl_fdb->esw_mgr_items_tmpl,
10773 : : NULL));
10774 : : /* Clean up templates structure for FDB control flow rules. */
10775 : 0 : mlx5_free(hw_ctrl_fdb);
10776 : 0 : priv->hw_ctrl_fdb = NULL;
10777 : : }
10778 : :
10779 : : /*
10780 : : * Create a table on the root group to for the LACP traffic redirecting.
10781 : : *
10782 : : * @param dev
10783 : : * Pointer to Ethernet device.
10784 : : * @param it
10785 : : * Pointer to flow pattern template.
10786 : : * @param at
10787 : : * Pointer to flow actions template.
10788 : : *
10789 : : * @return
10790 : : * Pointer to flow table on success, NULL otherwise.
10791 : : */
10792 : : static struct rte_flow_template_table *
10793 : 0 : flow_hw_create_lacp_rx_table(struct rte_eth_dev *dev,
10794 : : struct rte_flow_pattern_template *it,
10795 : : struct rte_flow_actions_template *at,
10796 : : struct rte_flow_error *error)
10797 : : {
10798 : 0 : struct rte_flow_template_table_attr attr = {
10799 : : .flow_attr = {
10800 : : .group = 0,
10801 : : .priority = 0,
10802 : : .ingress = 1,
10803 : : .egress = 0,
10804 : : .transfer = 0,
10805 : : },
10806 : : .nb_flows = 1,
10807 : : };
10808 : 0 : struct mlx5_flow_template_table_cfg cfg = {
10809 : : .attr = attr,
10810 : : .external = false,
10811 : : };
10812 : :
10813 : 0 : return flow_hw_table_create(dev, &cfg, &it, 1, &at, 1, error);
10814 : : }
10815 : :
10816 : : /**
10817 : : * Creates a set of flow tables used to create control flows used
10818 : : * when E-Switch is engaged.
10819 : : *
10820 : : * @param dev
10821 : : * Pointer to Ethernet device.
10822 : : * @param error
10823 : : * Pointer to error structure.
10824 : : *
10825 : : * @return
10826 : : * 0 on success, negative values otherwise
10827 : : */
10828 : : static int
10829 : 0 : flow_hw_create_ctrl_tables(struct rte_eth_dev *dev, struct rte_flow_error *error)
10830 : : {
10831 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
10832 : : struct mlx5_flow_hw_ctrl_fdb *hw_ctrl_fdb;
10833 : 0 : uint32_t xmeta = priv->sh->config.dv_xmeta_en;
10834 : 0 : uint32_t repr_matching = priv->sh->config.repr_matching;
10835 : 0 : uint32_t fdb_def_rule = priv->sh->config.fdb_def_rule;
10836 : :
10837 : : MLX5_ASSERT(priv->hw_ctrl_fdb == NULL);
10838 : 0 : hw_ctrl_fdb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*hw_ctrl_fdb), 0, SOCKET_ID_ANY);
10839 [ # # ]: 0 : if (!hw_ctrl_fdb) {
10840 : 0 : DRV_LOG(ERR, "port %u failed to allocate memory for FDB control flow templates",
10841 : : dev->data->port_id);
10842 : 0 : rte_errno = ENOMEM;
10843 : 0 : goto err;
10844 : : }
10845 : 0 : priv->hw_ctrl_fdb = hw_ctrl_fdb;
10846 [ # # ]: 0 : if (fdb_def_rule) {
10847 : : /* Create templates and table for default SQ miss flow rules - root table. */
10848 : 0 : hw_ctrl_fdb->esw_mgr_items_tmpl =
10849 : 0 : flow_hw_create_ctrl_esw_mgr_pattern_template(dev, error);
10850 [ # # ]: 0 : if (!hw_ctrl_fdb->esw_mgr_items_tmpl) {
10851 : 0 : DRV_LOG(ERR, "port %u failed to create E-Switch Manager item"
10852 : : " template for control flows", dev->data->port_id);
10853 : 0 : goto err;
10854 : : }
10855 : 0 : hw_ctrl_fdb->regc_jump_actions_tmpl =
10856 : 0 : flow_hw_create_ctrl_regc_jump_actions_template(dev, error);
10857 [ # # ]: 0 : if (!hw_ctrl_fdb->regc_jump_actions_tmpl) {
10858 : 0 : DRV_LOG(ERR, "port %u failed to create REG_C set and jump action template"
10859 : : " for control flows", dev->data->port_id);
10860 : 0 : goto err;
10861 : : }
10862 : 0 : hw_ctrl_fdb->hw_esw_sq_miss_root_tbl =
10863 : 0 : flow_hw_create_ctrl_sq_miss_root_table
10864 : : (dev, hw_ctrl_fdb->esw_mgr_items_tmpl,
10865 : : hw_ctrl_fdb->regc_jump_actions_tmpl, error);
10866 [ # # ]: 0 : if (!hw_ctrl_fdb->hw_esw_sq_miss_root_tbl) {
10867 : 0 : DRV_LOG(ERR, "port %u failed to create table for default sq miss (root table)"
10868 : : " for control flows", dev->data->port_id);
10869 : 0 : goto err;
10870 : : }
10871 : : /* Create templates and table for default SQ miss flow rules - non-root table. */
10872 : 0 : hw_ctrl_fdb->regc_sq_items_tmpl =
10873 : 0 : flow_hw_create_ctrl_regc_sq_pattern_template(dev, error);
10874 [ # # ]: 0 : if (!hw_ctrl_fdb->regc_sq_items_tmpl) {
10875 : 0 : DRV_LOG(ERR, "port %u failed to create SQ item template for"
10876 : : " control flows", dev->data->port_id);
10877 : 0 : goto err;
10878 : : }
10879 : 0 : hw_ctrl_fdb->port_actions_tmpl =
10880 : 0 : flow_hw_create_ctrl_port_actions_template(dev, error);
10881 [ # # ]: 0 : if (!hw_ctrl_fdb->port_actions_tmpl) {
10882 : 0 : DRV_LOG(ERR, "port %u failed to create port action template"
10883 : : " for control flows", dev->data->port_id);
10884 : 0 : goto err;
10885 : : }
10886 : 0 : hw_ctrl_fdb->hw_esw_sq_miss_tbl =
10887 : 0 : flow_hw_create_ctrl_sq_miss_table
10888 : : (dev, hw_ctrl_fdb->regc_sq_items_tmpl,
10889 : : hw_ctrl_fdb->port_actions_tmpl, error);
10890 [ # # ]: 0 : if (!hw_ctrl_fdb->hw_esw_sq_miss_tbl) {
10891 : 0 : DRV_LOG(ERR, "port %u failed to create table for default sq miss (non-root table)"
10892 : : " for control flows", dev->data->port_id);
10893 : 0 : goto err;
10894 : : }
10895 : : /* Create templates and table for default FDB jump flow rules. */
10896 : 0 : hw_ctrl_fdb->port_items_tmpl =
10897 : 0 : flow_hw_create_ctrl_port_pattern_template(dev, error);
10898 [ # # ]: 0 : if (!hw_ctrl_fdb->port_items_tmpl) {
10899 : 0 : DRV_LOG(ERR, "port %u failed to create SQ item template for"
10900 : : " control flows", dev->data->port_id);
10901 : 0 : goto err;
10902 : : }
10903 : 0 : hw_ctrl_fdb->jump_one_actions_tmpl =
10904 : 0 : flow_hw_create_ctrl_jump_actions_template
10905 : : (dev, MLX5_HW_LOWEST_USABLE_GROUP, error);
10906 [ # # ]: 0 : if (!hw_ctrl_fdb->jump_one_actions_tmpl) {
10907 : 0 : DRV_LOG(ERR, "port %u failed to create jump action template"
10908 : : " for control flows", dev->data->port_id);
10909 : 0 : goto err;
10910 : : }
10911 : 0 : hw_ctrl_fdb->hw_esw_zero_tbl = flow_hw_create_ctrl_jump_table
10912 : : (dev, hw_ctrl_fdb->port_items_tmpl,
10913 : : hw_ctrl_fdb->jump_one_actions_tmpl, error);
10914 [ # # ]: 0 : if (!hw_ctrl_fdb->hw_esw_zero_tbl) {
10915 : 0 : DRV_LOG(ERR, "port %u failed to create table for default jump to group 1"
10916 : : " for control flows", dev->data->port_id);
10917 : 0 : goto err;
10918 : : }
10919 : : }
10920 : : /* Create templates and table for default Tx metadata copy flow rule. */
10921 [ # # ]: 0 : if (!repr_matching && xmeta == MLX5_XMETA_MODE_META32_HWS) {
10922 : 0 : hw_ctrl_fdb->tx_meta_items_tmpl =
10923 : 0 : flow_hw_create_tx_default_mreg_copy_pattern_template(dev, error);
10924 [ # # ]: 0 : if (!hw_ctrl_fdb->tx_meta_items_tmpl) {
10925 : 0 : DRV_LOG(ERR, "port %u failed to Tx metadata copy pattern"
10926 : : " template for control flows", dev->data->port_id);
10927 : 0 : goto err;
10928 : : }
10929 : 0 : hw_ctrl_fdb->tx_meta_actions_tmpl =
10930 : 0 : flow_hw_create_tx_default_mreg_copy_actions_template(dev, error);
10931 [ # # ]: 0 : if (!hw_ctrl_fdb->tx_meta_actions_tmpl) {
10932 : 0 : DRV_LOG(ERR, "port %u failed to Tx metadata copy actions"
10933 : : " template for control flows", dev->data->port_id);
10934 : 0 : goto err;
10935 : : }
10936 : 0 : hw_ctrl_fdb->hw_tx_meta_cpy_tbl =
10937 : 0 : flow_hw_create_tx_default_mreg_copy_table
10938 : : (dev, hw_ctrl_fdb->tx_meta_items_tmpl,
10939 : : hw_ctrl_fdb->tx_meta_actions_tmpl, error);
10940 [ # # ]: 0 : if (!hw_ctrl_fdb->hw_tx_meta_cpy_tbl) {
10941 : 0 : DRV_LOG(ERR, "port %u failed to create table for default"
10942 : : " Tx metadata copy flow rule", dev->data->port_id);
10943 : 0 : goto err;
10944 : : }
10945 : : }
10946 : : /* Create LACP default miss table. */
10947 [ # # # # : 0 : if (!priv->sh->config.lacp_by_user && priv->pf_bond >= 0 && priv->master) {
# # ]
10948 : 0 : hw_ctrl_fdb->lacp_rx_items_tmpl =
10949 : 0 : flow_hw_create_lacp_rx_pattern_template(dev, error);
10950 [ # # ]: 0 : if (!hw_ctrl_fdb->lacp_rx_items_tmpl) {
10951 : 0 : DRV_LOG(ERR, "port %u failed to create pattern template"
10952 : : " for LACP Rx traffic", dev->data->port_id);
10953 : 0 : goto err;
10954 : : }
10955 : 0 : hw_ctrl_fdb->lacp_rx_actions_tmpl =
10956 : 0 : flow_hw_create_lacp_rx_actions_template(dev, error);
10957 [ # # ]: 0 : if (!hw_ctrl_fdb->lacp_rx_actions_tmpl) {
10958 : 0 : DRV_LOG(ERR, "port %u failed to create actions template"
10959 : : " for LACP Rx traffic", dev->data->port_id);
10960 : 0 : goto err;
10961 : : }
10962 : 0 : hw_ctrl_fdb->hw_lacp_rx_tbl = flow_hw_create_lacp_rx_table
10963 : : (dev, hw_ctrl_fdb->lacp_rx_items_tmpl,
10964 : : hw_ctrl_fdb->lacp_rx_actions_tmpl, error);
10965 [ # # ]: 0 : if (!hw_ctrl_fdb->hw_lacp_rx_tbl) {
10966 : 0 : DRV_LOG(ERR, "port %u failed to create template table for"
10967 : : " for LACP Rx traffic", dev->data->port_id);
10968 : 0 : goto err;
10969 : : }
10970 : : }
10971 : : return 0;
10972 : :
10973 : 0 : err:
10974 : 0 : flow_hw_cleanup_ctrl_fdb_tables(dev);
10975 : 0 : return -EINVAL;
10976 : : }
10977 : :
10978 : : static void
10979 : 0 : flow_hw_ct_mng_destroy(struct rte_eth_dev *dev,
10980 : : struct mlx5_aso_ct_pools_mng *ct_mng)
10981 : : {
10982 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
10983 : :
10984 : 0 : mlx5_aso_ct_queue_uninit(priv->sh, ct_mng);
10985 : 0 : mlx5_free(ct_mng);
10986 : 0 : }
10987 : :
10988 : : static void
10989 : 0 : flow_hw_ct_pool_destroy(struct rte_eth_dev *dev,
10990 : : struct mlx5_aso_ct_pool *pool)
10991 : : {
10992 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
10993 : :
10994 [ # # ]: 0 : if (pool->dr_action)
10995 : 0 : mlx5dr_action_destroy(pool->dr_action);
10996 [ # # ]: 0 : if (!priv->shared_host) {
10997 [ # # ]: 0 : if (pool->devx_obj)
10998 : 0 : claim_zero(mlx5_devx_cmd_destroy(pool->devx_obj));
10999 [ # # ]: 0 : if (pool->cts)
11000 : 0 : mlx5_ipool_destroy(pool->cts);
11001 : : }
11002 : 0 : mlx5_free(pool);
11003 : 0 : }
11004 : :
11005 : : static struct mlx5_aso_ct_pool *
11006 : 0 : flow_hw_ct_pool_create(struct rte_eth_dev *dev,
11007 : : uint32_t nb_conn_tracks)
11008 : : {
11009 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
11010 : : struct mlx5_aso_ct_pool *pool;
11011 : : struct mlx5_devx_obj *obj;
11012 : : uint32_t nb_cts = rte_align32pow2(nb_conn_tracks);
11013 : : uint32_t log_obj_size = rte_log2_u32(nb_cts);
11014 : 0 : struct mlx5_indexed_pool_config cfg = {
11015 : : .size = sizeof(struct mlx5_aso_ct_action),
11016 : : .trunk_size = 1 << 12,
11017 : : .per_core_cache = 1 << 13,
11018 : : .need_lock = 1,
11019 : 0 : .release_mem_en = !!priv->sh->config.reclaim_mode,
11020 : : .malloc = mlx5_malloc,
11021 : : .free = mlx5_free,
11022 : : .type = "mlx5_hw_ct_action",
11023 : : };
11024 : : int reg_id;
11025 : : uint32_t flags = 0;
11026 : :
11027 : 0 : pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
11028 [ # # ]: 0 : if (!pool) {
11029 : 0 : rte_errno = ENOMEM;
11030 : 0 : return NULL;
11031 : : }
11032 [ # # ]: 0 : if (!priv->shared_host) {
11033 : : /*
11034 : : * No need for local cache if CT number is a small number. Since
11035 : : * flow insertion rate will be very limited in that case. Here let's
11036 : : * set the number to less than default trunk size 4K.
11037 : : */
11038 [ # # ]: 0 : if (nb_cts <= cfg.trunk_size) {
11039 : 0 : cfg.per_core_cache = 0;
11040 : 0 : cfg.trunk_size = nb_cts;
11041 [ # # ]: 0 : } else if (nb_cts <= MLX5_HW_IPOOL_SIZE_THRESHOLD) {
11042 : 0 : cfg.per_core_cache = MLX5_HW_IPOOL_CACHE_MIN;
11043 : : }
11044 : 0 : cfg.max_idx = nb_cts;
11045 : 0 : pool->cts = mlx5_ipool_create(&cfg);
11046 [ # # ]: 0 : if (!pool->cts)
11047 : 0 : goto err;
11048 : 0 : obj = mlx5_devx_cmd_create_conn_track_offload_obj(priv->sh->cdev->ctx,
11049 : 0 : priv->sh->cdev->pdn,
11050 : : log_obj_size);
11051 [ # # ]: 0 : if (!obj) {
11052 : 0 : rte_errno = ENODATA;
11053 : 0 : DRV_LOG(ERR, "Failed to create conn_track_offload_obj using DevX.");
11054 : 0 : goto err;
11055 : : }
11056 : 0 : pool->devx_obj = obj;
11057 : : } else {
11058 : : struct rte_eth_dev *host_dev = priv->shared_host;
11059 : 0 : struct mlx5_priv *host_priv = host_dev->data->dev_private;
11060 : :
11061 : 0 : pool->devx_obj = host_priv->hws_ctpool->devx_obj;
11062 : 0 : pool->cts = host_priv->hws_ctpool->cts;
11063 : : MLX5_ASSERT(pool->cts);
11064 : : MLX5_ASSERT(!nb_conn_tracks);
11065 : : }
11066 : 0 : reg_id = mlx5_flow_get_reg_id(dev, MLX5_ASO_CONNTRACK, 0, NULL);
11067 : : flags |= MLX5DR_ACTION_FLAG_HWS_RX | MLX5DR_ACTION_FLAG_HWS_TX;
11068 [ # # # # ]: 0 : if (priv->sh->config.dv_esw_en && priv->master) {
11069 : 0 : flags |= ((is_unified_fdb(priv)) ?
11070 : : (MLX5DR_ACTION_FLAG_HWS_FDB_RX |
11071 : : MLX5DR_ACTION_FLAG_HWS_FDB_TX |
11072 [ # # ]: 0 : MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED) :
11073 : : MLX5DR_ACTION_FLAG_HWS_FDB);
11074 : : }
11075 : 0 : pool->dr_action = mlx5dr_action_create_aso_ct(priv->dr_ctx,
11076 : 0 : (struct mlx5dr_devx_obj *)pool->devx_obj,
11077 : 0 : reg_id - REG_C_0, flags);
11078 [ # # ]: 0 : if (!pool->dr_action)
11079 : 0 : goto err;
11080 : 0 : pool->sq = priv->ct_mng->aso_sqs;
11081 : : /* Assign the last extra ASO SQ as public SQ. */
11082 : 0 : pool->shared_sq = &priv->ct_mng->aso_sqs[priv->nb_queue - 1];
11083 : 0 : return pool;
11084 : 0 : err:
11085 : 0 : flow_hw_ct_pool_destroy(dev, pool);
11086 : 0 : return NULL;
11087 : : }
11088 : :
11089 : : static int
11090 : 0 : mlx5_flow_ct_init(struct rte_eth_dev *dev,
11091 : : uint32_t nb_conn_tracks,
11092 : : uint16_t nb_queue)
11093 : : {
11094 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11095 : : uint32_t mem_size;
11096 : : int ret = -ENOMEM;
11097 : :
11098 [ # # ]: 0 : if (!priv->shared_host) {
11099 : 0 : mem_size = sizeof(struct mlx5_aso_sq) * nb_queue +
11100 : : sizeof(*priv->ct_mng);
11101 : 0 : priv->ct_mng = mlx5_malloc(MLX5_MEM_ZERO, mem_size,
11102 : : RTE_CACHE_LINE_SIZE,
11103 : : SOCKET_ID_ANY);
11104 [ # # ]: 0 : if (!priv->ct_mng)
11105 : 0 : goto err;
11106 : 0 : ret = mlx5_aso_ct_queue_init(priv->sh, priv->ct_mng,
11107 : : nb_queue);
11108 [ # # ]: 0 : if (ret)
11109 : 0 : goto err;
11110 : : }
11111 : 0 : priv->hws_ctpool = flow_hw_ct_pool_create(dev, nb_conn_tracks);
11112 [ # # ]: 0 : if (!priv->hws_ctpool)
11113 : 0 : goto err;
11114 : 0 : priv->sh->ct_aso_en = 1;
11115 : 0 : return 0;
11116 : :
11117 : 0 : err:
11118 [ # # ]: 0 : if (priv->hws_ctpool) {
11119 : 0 : flow_hw_ct_pool_destroy(dev, priv->hws_ctpool);
11120 : 0 : priv->hws_ctpool = NULL;
11121 : : }
11122 [ # # ]: 0 : if (priv->ct_mng) {
11123 : 0 : flow_hw_ct_mng_destroy(dev, priv->ct_mng);
11124 : 0 : priv->ct_mng = NULL;
11125 : : }
11126 : : return ret;
11127 : : }
11128 : :
11129 : : static void
11130 : 0 : flow_hw_destroy_vlan(struct rte_eth_dev *dev)
11131 : : {
11132 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11133 : : enum mlx5dr_table_type i;
11134 : :
11135 [ # # ]: 0 : for (i = MLX5DR_TABLE_TYPE_NIC_RX; i < MLX5DR_TABLE_TYPE_MAX; i++) {
11136 [ # # ]: 0 : if (priv->hw_pop_vlan[i]) {
11137 : 0 : mlx5dr_action_destroy(priv->hw_pop_vlan[i]);
11138 : 0 : priv->hw_pop_vlan[i] = NULL;
11139 : : }
11140 [ # # ]: 0 : if (priv->hw_push_vlan[i]) {
11141 : 0 : mlx5dr_action_destroy(priv->hw_push_vlan[i]);
11142 : 0 : priv->hw_push_vlan[i] = NULL;
11143 : : }
11144 : : }
11145 : 0 : }
11146 : :
11147 : : static int
11148 : 0 : _create_vlan(struct mlx5_priv *priv, enum mlx5dr_table_type type)
11149 : : {
11150 : 0 : const enum mlx5dr_action_flags flags[MLX5DR_TABLE_TYPE_MAX] = {
11151 : : MLX5DR_ACTION_FLAG_HWS_RX,
11152 : : MLX5DR_ACTION_FLAG_HWS_TX,
11153 : : MLX5DR_ACTION_FLAG_HWS_FDB,
11154 : : MLX5DR_ACTION_FLAG_HWS_FDB_RX,
11155 : : MLX5DR_ACTION_FLAG_HWS_FDB_TX,
11156 : : MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED,
11157 : : };
11158 : :
11159 : : /* rte_errno is set in the mlx5dr_action* functions. */
11160 : 0 : priv->hw_pop_vlan[type] =
11161 : 0 : mlx5dr_action_create_pop_vlan(priv->dr_ctx, flags[type]);
11162 [ # # ]: 0 : if (!priv->hw_pop_vlan[type])
11163 : 0 : return -rte_errno;
11164 : 0 : priv->hw_push_vlan[type] =
11165 : 0 : mlx5dr_action_create_push_vlan(priv->dr_ctx, flags[type]);
11166 [ # # ]: 0 : if (!priv->hw_push_vlan[type])
11167 : 0 : return -rte_errno;
11168 : : return 0;
11169 : : }
11170 : :
11171 : : static int
11172 : 0 : flow_hw_create_vlan(struct rte_eth_dev *dev)
11173 : : {
11174 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11175 : : enum mlx5dr_table_type i, from, to;
11176 : : int rc;
11177 : : bool unified_fdb = is_unified_fdb(priv);
11178 : :
11179 [ # # ]: 0 : for (i = MLX5DR_TABLE_TYPE_NIC_RX; i <= MLX5DR_TABLE_TYPE_NIC_TX; i++) {
11180 : 0 : rc = _create_vlan(priv, i);
11181 [ # # ]: 0 : if (rc)
11182 : 0 : return rc;
11183 : : }
11184 [ # # ]: 0 : from = unified_fdb ? MLX5DR_TABLE_TYPE_FDB_RX : MLX5DR_TABLE_TYPE_FDB;
11185 [ # # ]: 0 : to = unified_fdb ? MLX5DR_TABLE_TYPE_FDB_UNIFIED : MLX5DR_TABLE_TYPE_FDB;
11186 [ # # # # ]: 0 : if (priv->sh->config.dv_esw_en && priv->master) {
11187 [ # # ]: 0 : for (i = from; i <= to; i++) {
11188 : 0 : rc = _create_vlan(priv, i);
11189 [ # # ]: 0 : if (rc)
11190 : 0 : return rc;
11191 : : }
11192 : : }
11193 : : return 0;
11194 : : }
11195 : :
11196 : : static void
11197 : 0 : flow_hw_cleanup_ctrl_rx_tables(struct rte_eth_dev *dev)
11198 : : {
11199 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11200 : : unsigned int i;
11201 : : unsigned int j;
11202 : :
11203 [ # # ]: 0 : if (!priv->hw_ctrl_rx)
11204 : : return;
11205 [ # # ]: 0 : for (i = 0; i < MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_MAX; ++i) {
11206 [ # # ]: 0 : for (j = 0; j < MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX; ++j) {
11207 : 0 : struct rte_flow_template_table *tbl = priv->hw_ctrl_rx->tables[i][j].tbl;
11208 : 0 : struct rte_flow_pattern_template *pt = priv->hw_ctrl_rx->tables[i][j].pt;
11209 : :
11210 [ # # ]: 0 : if (tbl)
11211 : 0 : claim_zero(flow_hw_table_destroy(dev, tbl, NULL));
11212 [ # # ]: 0 : if (pt)
11213 : 0 : claim_zero(flow_hw_pattern_template_destroy(dev, pt, NULL));
11214 : : }
11215 : : }
11216 [ # # ]: 0 : for (i = 0; i < MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX; ++i) {
11217 : 0 : struct rte_flow_actions_template *at = priv->hw_ctrl_rx->rss[i];
11218 : :
11219 [ # # ]: 0 : if (at)
11220 : 0 : claim_zero(flow_hw_actions_template_destroy(dev, at, NULL));
11221 : : }
11222 : 0 : mlx5_free(priv->hw_ctrl_rx);
11223 : 0 : priv->hw_ctrl_rx = NULL;
11224 : : }
11225 : :
11226 : : static uint64_t
11227 : : flow_hw_ctrl_rx_rss_type_hash_types(const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
11228 : : {
11229 : : switch (rss_type) {
11230 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_NON_IP:
11231 : : return 0;
11232 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4:
11233 : : return RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_FRAG_IPV4 | RTE_ETH_RSS_NONFRAG_IPV4_OTHER;
11234 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_UDP:
11235 : : return RTE_ETH_RSS_NONFRAG_IPV4_UDP;
11236 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_TCP:
11237 : : return RTE_ETH_RSS_NONFRAG_IPV4_TCP;
11238 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6:
11239 : : return RTE_ETH_RSS_IPV6 | RTE_ETH_RSS_FRAG_IPV6 | RTE_ETH_RSS_NONFRAG_IPV6_OTHER;
11240 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_UDP:
11241 : : return RTE_ETH_RSS_NONFRAG_IPV6_UDP | RTE_ETH_RSS_IPV6_UDP_EX;
11242 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_TCP:
11243 : : return RTE_ETH_RSS_NONFRAG_IPV6_TCP | RTE_ETH_RSS_IPV6_TCP_EX;
11244 : : default:
11245 : : /* Should not reach here. */
11246 : : MLX5_ASSERT(false);
11247 : : return 0;
11248 : : }
11249 : : }
11250 : :
11251 : : static struct rte_flow_actions_template *
11252 : 0 : flow_hw_create_ctrl_rx_rss_template(struct rte_eth_dev *dev,
11253 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
11254 : : {
11255 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11256 : 0 : struct rte_flow_actions_template_attr attr = {
11257 : : .ingress = 1,
11258 : : };
11259 : : uint16_t queue[RTE_MAX_QUEUES_PER_PORT];
11260 : 0 : struct rte_flow_action_rss rss_conf = {
11261 : : .func = RTE_ETH_HASH_FUNCTION_DEFAULT,
11262 : : .level = 0,
11263 : : .types = 0,
11264 : 0 : .key_len = priv->rss_conf.rss_key_len,
11265 : 0 : .key = priv->rss_conf.rss_key,
11266 : 0 : .queue_num = priv->reta_idx_n,
11267 : : .queue = queue,
11268 : : };
11269 : 0 : struct rte_flow_action actions[] = {
11270 : : {
11271 : : .type = RTE_FLOW_ACTION_TYPE_RSS,
11272 : : .conf = &rss_conf,
11273 : : },
11274 : : {
11275 : : .type = RTE_FLOW_ACTION_TYPE_END,
11276 : : }
11277 : : };
11278 [ # # ]: 0 : struct rte_flow_action masks[] = {
11279 : : {
11280 : : .type = RTE_FLOW_ACTION_TYPE_RSS,
11281 : : .conf = &rss_conf,
11282 : : },
11283 : : {
11284 : : .type = RTE_FLOW_ACTION_TYPE_END,
11285 : : }
11286 : : };
11287 : : struct rte_flow_actions_template *at;
11288 : : struct rte_flow_error error;
11289 : : unsigned int i;
11290 : :
11291 : : MLX5_ASSERT(priv->reta_idx_n > 0 && priv->reta_idx);
11292 : : /* Select proper RSS hash types and based on that configure the actions template. */
11293 : 0 : rss_conf.types = flow_hw_ctrl_rx_rss_type_hash_types(rss_type);
11294 [ # # ]: 0 : if (rss_conf.types) {
11295 [ # # ]: 0 : for (i = 0; i < priv->reta_idx_n; ++i)
11296 : 0 : queue[i] = (*priv->reta_idx)[i];
11297 : : } else {
11298 : 0 : rss_conf.queue_num = 1;
11299 : 0 : queue[0] = (*priv->reta_idx)[0];
11300 : : }
11301 : : at = flow_hw_actions_template_create(dev, &attr, actions, masks, &error);
11302 [ # # ]: 0 : if (!at)
11303 [ # # ]: 0 : DRV_LOG(ERR,
11304 : : "Failed to create ctrl flow actions template: rte_errno(%d), type(%d): %s",
11305 : : rte_errno, error.type,
11306 : : error.message ? error.message : "(no stated reason)");
11307 : 0 : return at;
11308 : : }
11309 : :
11310 : : static uint32_t ctrl_rx_rss_priority_map[MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX] = {
11311 : : [MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_NON_IP] = MLX5_HW_CTRL_RX_PRIO_L2,
11312 : : [MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4] = MLX5_HW_CTRL_RX_PRIO_L3,
11313 : : [MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_UDP] = MLX5_HW_CTRL_RX_PRIO_L4,
11314 : : [MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_TCP] = MLX5_HW_CTRL_RX_PRIO_L4,
11315 : : [MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6] = MLX5_HW_CTRL_RX_PRIO_L3,
11316 : : [MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_UDP] = MLX5_HW_CTRL_RX_PRIO_L4,
11317 : : [MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_TCP] = MLX5_HW_CTRL_RX_PRIO_L4,
11318 : : };
11319 : :
11320 : : static uint32_t ctrl_rx_nb_flows_map[MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_MAX] = {
11321 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL] = 1,
11322 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL_MCAST] = 1,
11323 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST] = 1,
11324 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST_VLAN] = MLX5_MAX_VLAN_IDS,
11325 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST] = 1,
11326 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST_VLAN] = MLX5_MAX_VLAN_IDS,
11327 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST] = 1,
11328 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST_VLAN] = MLX5_MAX_VLAN_IDS,
11329 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC] = MLX5_MAX_UC_MAC_ADDRESSES,
11330 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN] =
11331 : : MLX5_MAX_UC_MAC_ADDRESSES * MLX5_MAX_VLAN_IDS,
11332 : : };
11333 : :
11334 : : static struct rte_flow_template_table_attr
11335 : : flow_hw_get_ctrl_rx_table_attr(enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type,
11336 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
11337 : : {
11338 : 0 : return (struct rte_flow_template_table_attr){
11339 : : .flow_attr = {
11340 : : .group = 0,
11341 : 0 : .priority = ctrl_rx_rss_priority_map[rss_type],
11342 : : .ingress = 1,
11343 : : },
11344 : 0 : .nb_flows = ctrl_rx_nb_flows_map[eth_pattern_type],
11345 : : };
11346 : : }
11347 : :
11348 : : static struct rte_flow_item
11349 : : flow_hw_get_ctrl_rx_eth_item(const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type)
11350 : : {
11351 : : struct rte_flow_item item = {
11352 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
11353 : : .mask = NULL,
11354 : : };
11355 : :
11356 : 0 : switch (eth_pattern_type) {
11357 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL:
11358 : : item.mask = &ctrl_rx_eth_promisc_mask;
11359 : : break;
11360 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL_MCAST:
11361 : : item.mask = &ctrl_rx_eth_mcast_mask;
11362 : 0 : break;
11363 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST:
11364 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST_VLAN:
11365 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC:
11366 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN:
11367 : : item.mask = &ctrl_rx_eth_dmac_mask;
11368 : 0 : break;
11369 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST:
11370 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST_VLAN:
11371 : : item.mask = &ctrl_rx_eth_ipv4_mcast_mask;
11372 : 0 : break;
11373 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST:
11374 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST_VLAN:
11375 : : item.mask = &ctrl_rx_eth_ipv6_mcast_mask;
11376 : 0 : break;
11377 : 0 : default:
11378 : : /* Should not reach here - ETH mask must be present. */
11379 : : item.type = RTE_FLOW_ITEM_TYPE_END;
11380 : : MLX5_ASSERT(false);
11381 : 0 : break;
11382 : : }
11383 : 0 : return item;
11384 : : }
11385 : :
11386 : : static struct rte_flow_item
11387 : : flow_hw_get_ctrl_rx_vlan_item(const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type)
11388 : : {
11389 : : struct rte_flow_item item = {
11390 : : .type = RTE_FLOW_ITEM_TYPE_VOID,
11391 : : .mask = NULL,
11392 : : };
11393 : :
11394 [ # # ]: 0 : switch (eth_pattern_type) {
11395 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST_VLAN:
11396 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST_VLAN:
11397 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST_VLAN:
11398 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN:
11399 : : item.type = RTE_FLOW_ITEM_TYPE_VLAN;
11400 : : item.mask = &rte_flow_item_vlan_mask;
11401 : 0 : break;
11402 : : default:
11403 : : /* Nothing to update. */
11404 : : break;
11405 : : }
11406 : 0 : return item;
11407 : : }
11408 : :
11409 : : static struct rte_flow_item
11410 : : flow_hw_get_ctrl_rx_l3_item(const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
11411 : : {
11412 : : struct rte_flow_item item = {
11413 : : .type = RTE_FLOW_ITEM_TYPE_VOID,
11414 : : .mask = NULL,
11415 : : };
11416 : :
11417 [ # # # ]: 0 : switch (rss_type) {
11418 : 0 : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4:
11419 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_UDP:
11420 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_TCP:
11421 : : item.type = RTE_FLOW_ITEM_TYPE_IPV4;
11422 : 0 : break;
11423 : 0 : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6:
11424 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_UDP:
11425 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_TCP:
11426 : : item.type = RTE_FLOW_ITEM_TYPE_IPV6;
11427 : 0 : break;
11428 : : default:
11429 : : /* Nothing to update. */
11430 : : break;
11431 : : }
11432 : 0 : return item;
11433 : : }
11434 : :
11435 : : static struct rte_flow_item
11436 : : flow_hw_get_ctrl_rx_l4_item(const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
11437 : : {
11438 : : struct rte_flow_item item = {
11439 : : .type = RTE_FLOW_ITEM_TYPE_VOID,
11440 : : .mask = NULL,
11441 : : };
11442 : :
11443 [ # # # ]: 0 : switch (rss_type) {
11444 : 0 : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_UDP:
11445 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_UDP:
11446 : : item.type = RTE_FLOW_ITEM_TYPE_UDP;
11447 : 0 : break;
11448 : 0 : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_TCP:
11449 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_TCP:
11450 : : item.type = RTE_FLOW_ITEM_TYPE_TCP;
11451 : 0 : break;
11452 : : default:
11453 : : /* Nothing to update. */
11454 : : break;
11455 : : }
11456 : 0 : return item;
11457 : : }
11458 : :
11459 : : static struct rte_flow_pattern_template *
11460 : 0 : flow_hw_create_ctrl_rx_pattern_template
11461 : : (struct rte_eth_dev *dev,
11462 : : const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type,
11463 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
11464 : : {
11465 : 0 : const struct rte_flow_pattern_template_attr attr = {
11466 : : .relaxed_matching = 0,
11467 : : .ingress = 1,
11468 : : };
11469 [ # # # # : 0 : struct rte_flow_item items[] = {
# # ]
11470 : : /* Matching patterns */
11471 : : flow_hw_get_ctrl_rx_eth_item(eth_pattern_type),
11472 : : flow_hw_get_ctrl_rx_vlan_item(eth_pattern_type),
11473 : : flow_hw_get_ctrl_rx_l3_item(rss_type),
11474 : : flow_hw_get_ctrl_rx_l4_item(rss_type),
11475 : : /* Terminate pattern */
11476 : : { .type = RTE_FLOW_ITEM_TYPE_END }
11477 : : };
11478 : :
11479 : 0 : return flow_hw_pattern_template_create(dev, &attr, items, NULL);
11480 : : }
11481 : :
11482 : : static int
11483 : 0 : flow_hw_create_ctrl_rx_tables(struct rte_eth_dev *dev)
11484 : : {
11485 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11486 : : unsigned int i;
11487 : : unsigned int j;
11488 : : int ret;
11489 : :
11490 : : MLX5_ASSERT(!priv->hw_ctrl_rx);
11491 : 0 : priv->hw_ctrl_rx = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*priv->hw_ctrl_rx),
11492 : 0 : RTE_CACHE_LINE_SIZE, rte_socket_id());
11493 [ # # ]: 0 : if (!priv->hw_ctrl_rx) {
11494 : 0 : DRV_LOG(ERR, "Failed to allocate memory for Rx control flow tables");
11495 : 0 : rte_errno = ENOMEM;
11496 : 0 : return -rte_errno;
11497 : : }
11498 : : /* Create all pattern template variants. */
11499 [ # # ]: 0 : for (i = 0; i < MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_MAX; ++i) {
11500 : : enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type = i;
11501 : :
11502 [ # # ]: 0 : for (j = 0; j < MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX; ++j) {
11503 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type = j;
11504 : : struct rte_flow_template_table_attr attr;
11505 : : struct rte_flow_pattern_template *pt;
11506 : :
11507 : : attr = flow_hw_get_ctrl_rx_table_attr(eth_pattern_type, rss_type);
11508 : 0 : pt = flow_hw_create_ctrl_rx_pattern_template(dev, eth_pattern_type,
11509 : : rss_type);
11510 [ # # ]: 0 : if (!pt)
11511 : 0 : goto err;
11512 : 0 : priv->hw_ctrl_rx->tables[i][j].attr = attr;
11513 : 0 : priv->hw_ctrl_rx->tables[i][j].pt = pt;
11514 : : }
11515 : : }
11516 : : return 0;
11517 : : err:
11518 : 0 : ret = rte_errno;
11519 : 0 : flow_hw_cleanup_ctrl_rx_tables(dev);
11520 : 0 : rte_errno = ret;
11521 : 0 : return -ret;
11522 : : }
11523 : :
11524 : : void
11525 : 0 : mlx5_flow_hw_cleanup_ctrl_rx_templates(struct rte_eth_dev *dev)
11526 : : {
11527 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11528 : : struct mlx5_flow_hw_ctrl_rx *hw_ctrl_rx;
11529 : : unsigned int i;
11530 : : unsigned int j;
11531 : :
11532 [ # # ]: 0 : if (!priv->dr_ctx)
11533 : : return;
11534 [ # # ]: 0 : if (!priv->hw_ctrl_rx)
11535 : : return;
11536 : : hw_ctrl_rx = priv->hw_ctrl_rx;
11537 [ # # ]: 0 : for (i = 0; i < MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_MAX; ++i) {
11538 [ # # ]: 0 : for (j = 0; j < MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX; ++j) {
11539 : : struct mlx5_flow_hw_ctrl_rx_table *tmpls = &hw_ctrl_rx->tables[i][j];
11540 : :
11541 [ # # ]: 0 : if (tmpls->tbl) {
11542 : 0 : claim_zero(flow_hw_table_destroy(dev, tmpls->tbl, NULL));
11543 : 0 : tmpls->tbl = NULL;
11544 : : }
11545 : : }
11546 : : }
11547 [ # # ]: 0 : for (j = 0; j < MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX; ++j) {
11548 [ # # ]: 0 : if (hw_ctrl_rx->rss[j]) {
11549 : 0 : claim_zero(flow_hw_actions_template_destroy(dev, hw_ctrl_rx->rss[j], NULL));
11550 : 0 : hw_ctrl_rx->rss[j] = NULL;
11551 : : }
11552 : : }
11553 : : }
11554 : :
11555 : : /**
11556 : : * Copy the provided HWS configuration to a newly allocated buffer.
11557 : : *
11558 : : * @param[in] port_attr
11559 : : * Port configuration attributes.
11560 : : * @param[in] nb_queue
11561 : : * Number of queue.
11562 : : * @param[in] queue_attr
11563 : : * Array that holds attributes for each flow queue.
11564 : : * @param[in] nt_mode
11565 : : * Non template mode.
11566 : : *
11567 : : * @return
11568 : : * Pointer to copied HWS configuration is returned on success.
11569 : : * Otherwise, NULL is returned and rte_errno is set.
11570 : : */
11571 : : static struct mlx5_flow_hw_attr *
11572 : 0 : flow_hw_alloc_copy_config(const struct rte_flow_port_attr *port_attr,
11573 : : const uint16_t nb_queue,
11574 : : const struct rte_flow_queue_attr *queue_attr[],
11575 : : bool nt_mode,
11576 : : struct rte_flow_error *error)
11577 : : {
11578 : : struct mlx5_flow_hw_attr *hw_attr;
11579 : : size_t hw_attr_size;
11580 : : unsigned int i;
11581 : :
11582 : 0 : hw_attr_size = sizeof(*hw_attr) + nb_queue * sizeof(*hw_attr->queue_attr);
11583 : 0 : hw_attr = mlx5_malloc(MLX5_MEM_ZERO, hw_attr_size, 0, SOCKET_ID_ANY);
11584 [ # # ]: 0 : if (!hw_attr) {
11585 : 0 : rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11586 : : "Not enough memory to store configuration");
11587 : 0 : return NULL;
11588 : : }
11589 : 0 : memcpy(&hw_attr->port_attr, port_attr, sizeof(*port_attr));
11590 : 0 : hw_attr->nb_queue = nb_queue;
11591 : : /* Queue attributes are placed after the mlx5_flow_hw_attr. */
11592 : 0 : hw_attr->queue_attr = (struct rte_flow_queue_attr *)(hw_attr + 1);
11593 [ # # ]: 0 : for (i = 0; i < nb_queue; ++i)
11594 : 0 : memcpy(&hw_attr->queue_attr[i], queue_attr[i], sizeof(hw_attr->queue_attr[i]));
11595 : 0 : hw_attr->nt_mode = nt_mode;
11596 : 0 : return hw_attr;
11597 : : }
11598 : :
11599 : : /**
11600 : : * Compares the preserved HWS configuration with the provided one.
11601 : : *
11602 : : * @param[in] hw_attr
11603 : : * Pointer to preserved HWS configuration.
11604 : : * @param[in] new_pa
11605 : : * Port configuration attributes to compare.
11606 : : * @param[in] new_nbq
11607 : : * Number of queues to compare.
11608 : : * @param[in] new_qa
11609 : : * Array that holds attributes for each flow queue.
11610 : : *
11611 : : * @return
11612 : : * True if configurations are the same, false otherwise.
11613 : : */
11614 : : static bool
11615 : 0 : flow_hw_compare_config(const struct mlx5_flow_hw_attr *hw_attr,
11616 : : const struct rte_flow_port_attr *new_pa,
11617 : : const uint16_t new_nbq,
11618 : : const struct rte_flow_queue_attr *new_qa[])
11619 : : {
11620 : : const struct rte_flow_port_attr *old_pa = &hw_attr->port_attr;
11621 : 0 : const uint16_t old_nbq = hw_attr->nb_queue;
11622 : 0 : const struct rte_flow_queue_attr *old_qa = hw_attr->queue_attr;
11623 : : unsigned int i;
11624 : :
11625 [ # # ]: 0 : if (old_pa->nb_counters != new_pa->nb_counters ||
11626 [ # # ]: 0 : old_pa->nb_aging_objects != new_pa->nb_aging_objects ||
11627 [ # # ]: 0 : old_pa->nb_meters != new_pa->nb_meters ||
11628 [ # # ]: 0 : old_pa->nb_conn_tracks != new_pa->nb_conn_tracks ||
11629 [ # # ]: 0 : old_pa->flags != new_pa->flags)
11630 : : return false;
11631 [ # # ]: 0 : if (old_nbq != new_nbq)
11632 : : return false;
11633 [ # # ]: 0 : for (i = 0; i < old_nbq; ++i)
11634 [ # # ]: 0 : if (old_qa[i].size != new_qa[i]->size)
11635 : : return false;
11636 : : return true;
11637 : : }
11638 : :
11639 : : /*
11640 : : * No need to explicitly release drop action templates on port stop.
11641 : : * Drop action templates release with other action templates during
11642 : : * mlx5_dev_close -> flow_hw_resource_release -> flow_hw_actions_template_destroy
11643 : : */
11644 : : static void
11645 : 0 : flow_hw_action_template_drop_release(struct rte_eth_dev *dev)
11646 : : {
11647 : : int i;
11648 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11649 : :
11650 [ # # ]: 0 : for (i = 0; i < MLX5DR_TABLE_TYPE_MAX; i++) {
11651 [ # # ]: 0 : if (!priv->action_template_drop[i])
11652 : 0 : continue;
11653 : 0 : flow_hw_actions_template_destroy(dev,
11654 : : priv->action_template_drop[i],
11655 : : NULL);
11656 : 0 : priv->action_template_drop[i] = NULL;
11657 : : }
11658 : 0 : }
11659 : :
11660 : : static int
11661 : 0 : flow_hw_action_template_drop_init(struct rte_eth_dev *dev,
11662 : : struct rte_flow_error *error)
11663 : : {
11664 : : uint32_t i, from, to;
11665 : 0 : const struct rte_flow_action drop[2] = {
11666 : : [0] = { .type = RTE_FLOW_ACTION_TYPE_DROP },
11667 : : [1] = { .type = RTE_FLOW_ACTION_TYPE_END },
11668 : : };
11669 : : const struct rte_flow_action *actions = drop;
11670 : : const struct rte_flow_action *masks = drop;
11671 : 0 : const struct rte_flow_actions_template_attr attr[MLX5DR_TABLE_TYPE_MAX] = {
11672 : : [MLX5DR_TABLE_TYPE_NIC_RX] = { .ingress = 1 },
11673 : : [MLX5DR_TABLE_TYPE_NIC_TX] = { .egress = 1 },
11674 : : [MLX5DR_TABLE_TYPE_FDB] = { .transfer = 1 },
11675 : : [MLX5DR_TABLE_TYPE_FDB_RX] = { .transfer = 1 },
11676 : : [MLX5DR_TABLE_TYPE_FDB_TX] = { .transfer = 1 },
11677 : : [MLX5DR_TABLE_TYPE_FDB_UNIFIED] = { .transfer = 1 },
11678 : : };
11679 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11680 : :
11681 : : from = MLX5DR_TABLE_TYPE_NIC_RX;
11682 : : to = MLX5DR_TABLE_TYPE_NIC_TX;
11683 [ # # ]: 0 : for (i = from; i <= to; i++) {
11684 : 0 : priv->action_template_drop[i] =
11685 : 0 : flow_hw_actions_template_create(dev, &attr[i], actions, masks, error);
11686 [ # # ]: 0 : if (!priv->action_template_drop[i])
11687 : : return -1;
11688 : : }
11689 : :
11690 [ # # # # ]: 0 : if (!(priv->sh->config.dv_esw_en && priv->master))
11691 : : return 0;
11692 : :
11693 : : from = MLX5DR_TABLE_TYPE_FDB;
11694 [ # # ]: 0 : to = is_unified_fdb(priv) ? MLX5DR_TABLE_TYPE_FDB_UNIFIED : MLX5DR_TABLE_TYPE_FDB;
11695 [ # # ]: 0 : for (i = from; i <= to; i++) {
11696 : 0 : priv->action_template_drop[i] =
11697 : 0 : flow_hw_actions_template_create(dev, &attr[i], actions, masks, error);
11698 [ # # ]: 0 : if (!priv->action_template_drop[i])
11699 : : return -1;
11700 : : }
11701 : : return 0;
11702 : : }
11703 : :
11704 : : static void
11705 : 0 : __flow_hw_resource_release(struct rte_eth_dev *dev, bool ctx_close)
11706 : : {
11707 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11708 : : struct rte_flow_template_table *tbl, *temp_tbl;
11709 : : struct rte_flow_pattern_template *it, *temp_it;
11710 : : struct rte_flow_actions_template *at, *temp_at;
11711 : : struct mlx5_flow_group *grp, *temp_grp;
11712 : : uint32_t i;
11713 : :
11714 : 0 : flow_hw_rxq_flag_set(dev, false);
11715 : 0 : flow_hw_flush_all_ctrl_flows(dev);
11716 : 0 : flow_hw_cleanup_ctrl_fdb_tables(dev);
11717 : 0 : flow_hw_cleanup_tx_repr_tagging(dev);
11718 : 0 : flow_hw_cleanup_ctrl_rx_tables(dev);
11719 : 0 : flow_hw_action_template_drop_release(dev);
11720 : 0 : grp = LIST_FIRST(&priv->flow_hw_grp);
11721 [ # # ]: 0 : while (grp) {
11722 : 0 : temp_grp = LIST_NEXT(grp, next);
11723 : 0 : claim_zero(flow_hw_group_unset_miss_group(dev, grp, NULL));
11724 : : grp = temp_grp;
11725 : : }
11726 : 0 : tbl = LIST_FIRST(&priv->flow_hw_tbl_ongo);
11727 [ # # ]: 0 : while (tbl) {
11728 : 0 : temp_tbl = LIST_NEXT(tbl, next);
11729 : 0 : claim_zero(flow_hw_table_destroy(dev, tbl, NULL));
11730 : : tbl = temp_tbl;
11731 : : }
11732 : 0 : tbl = LIST_FIRST(&priv->flow_hw_tbl);
11733 [ # # ]: 0 : while (tbl) {
11734 : 0 : temp_tbl = LIST_NEXT(tbl, next);
11735 : 0 : claim_zero(flow_hw_table_destroy(dev, tbl, NULL));
11736 : : tbl = temp_tbl;
11737 : : }
11738 : 0 : it = LIST_FIRST(&priv->flow_hw_itt);
11739 [ # # ]: 0 : while (it) {
11740 : 0 : temp_it = LIST_NEXT(it, next);
11741 : 0 : claim_zero(flow_hw_pattern_template_destroy(dev, it, NULL));
11742 : : it = temp_it;
11743 : : }
11744 : 0 : at = LIST_FIRST(&priv->flow_hw_at);
11745 [ # # ]: 0 : while (at) {
11746 : 0 : temp_at = LIST_NEXT(at, next);
11747 : 0 : claim_zero(flow_hw_actions_template_destroy(dev, at, NULL));
11748 : : at = temp_at;
11749 : : }
11750 [ # # ]: 0 : for (i = 0; i < MLX5_HW_ACTION_FLAG_MAX; i++) {
11751 [ # # ]: 0 : if (priv->hw_drop[i])
11752 : 0 : mlx5dr_action_destroy(priv->hw_drop[i]);
11753 [ # # ]: 0 : if (priv->hw_tag[i])
11754 : 0 : mlx5dr_action_destroy(priv->hw_tag[i]);
11755 : : }
11756 [ # # ]: 0 : if (priv->hw_def_miss)
11757 : 0 : mlx5dr_action_destroy(priv->hw_def_miss);
11758 : 0 : flow_hw_destroy_nat64_actions(priv);
11759 : 0 : flow_hw_destroy_vlan(dev);
11760 : 0 : flow_hw_destroy_send_to_kernel_action(priv);
11761 : 0 : flow_hw_free_vport_actions(priv);
11762 [ # # ]: 0 : if (priv->acts_ipool) {
11763 : 0 : mlx5_ipool_destroy(priv->acts_ipool);
11764 : 0 : priv->acts_ipool = NULL;
11765 : : }
11766 [ # # ]: 0 : if (priv->hws_age_req)
11767 : 0 : mlx5_hws_age_pool_destroy(priv);
11768 [ # # # # ]: 0 : if (!priv->shared_host && priv->hws_cpool) {
11769 : 0 : mlx5_hws_cnt_pool_destroy(priv->sh, priv->hws_cpool);
11770 : 0 : priv->hws_cpool = NULL;
11771 : : }
11772 [ # # ]: 0 : if (priv->hws_ctpool) {
11773 : 0 : flow_hw_ct_pool_destroy(dev, priv->hws_ctpool);
11774 : 0 : priv->hws_ctpool = NULL;
11775 : : }
11776 [ # # ]: 0 : if (priv->ct_mng) {
11777 : 0 : flow_hw_ct_mng_destroy(dev, priv->ct_mng);
11778 : 0 : priv->ct_mng = NULL;
11779 : : }
11780 : 0 : mlx5_flow_quota_destroy(dev);
11781 [ # # ]: 0 : if (priv->hw_q) {
11782 [ # # ]: 0 : for (i = 0; i < priv->nb_queue; i++) {
11783 : 0 : struct mlx5_hw_q *hwq = &priv->hw_q[i];
11784 : 0 : rte_ring_free(hwq->indir_iq);
11785 : 0 : rte_ring_free(hwq->indir_cq);
11786 : 0 : rte_ring_free(hwq->flow_transfer_pending);
11787 : 0 : rte_ring_free(hwq->flow_transfer_completed);
11788 : : }
11789 : 0 : mlx5_free(priv->hw_q);
11790 : 0 : priv->hw_q = NULL;
11791 : : }
11792 [ # # ]: 0 : if (ctx_close) {
11793 [ # # ]: 0 : if (priv->dr_ctx) {
11794 : 0 : claim_zero(mlx5dr_context_close(priv->dr_ctx));
11795 : 0 : priv->dr_ctx = NULL;
11796 : : }
11797 : : }
11798 [ # # ]: 0 : if (priv->shared_host) {
11799 : 0 : struct mlx5_priv *host_priv = priv->shared_host->data->dev_private;
11800 : 0 : rte_atomic_fetch_sub_explicit(&host_priv->shared_refcnt, 1,
11801 : : rte_memory_order_relaxed);
11802 : 0 : priv->shared_host = NULL;
11803 : : }
11804 [ # # ]: 0 : if (priv->hw_attr) {
11805 : 0 : mlx5_free(priv->hw_attr);
11806 : 0 : priv->hw_attr = NULL;
11807 : : }
11808 : 0 : priv->nb_queue = 0;
11809 : 0 : }
11810 : :
11811 : : static __rte_always_inline struct rte_ring *
11812 : : mlx5_hwq_ring_create(uint16_t port_id, uint32_t queue, uint32_t size, const char *str)
11813 : : {
11814 : : char mz_name[RTE_MEMZONE_NAMESIZE];
11815 : :
11816 : : snprintf(mz_name, sizeof(mz_name), "port_%u_%s_%u", port_id, str, queue);
11817 : 0 : return rte_ring_create(mz_name, size, SOCKET_ID_ANY,
11818 : : RING_F_SP_ENQ | RING_F_SC_DEQ | RING_F_EXACT_SZ);
11819 : : }
11820 : :
11821 : : static int
11822 : 0 : flow_hw_validate_attributes(const struct rte_flow_port_attr *port_attr,
11823 : : uint16_t nb_queue,
11824 : : const struct rte_flow_queue_attr *queue_attr[],
11825 : : bool nt_mode, struct rte_flow_error *error)
11826 : : {
11827 : : uint32_t size;
11828 : : unsigned int i;
11829 : :
11830 [ # # ]: 0 : if (port_attr == NULL)
11831 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11832 : : "Port attributes must be non-NULL");
11833 : :
11834 [ # # ]: 0 : if (nb_queue == 0 && !nt_mode)
11835 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11836 : : "At least one flow queue is required");
11837 : :
11838 [ # # ]: 0 : if (queue_attr == NULL)
11839 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11840 : : "Queue attributes must be non-NULL");
11841 : :
11842 : 0 : size = queue_attr[0]->size;
11843 [ # # ]: 0 : for (i = 1; i < nb_queue; ++i) {
11844 [ # # ]: 0 : if (queue_attr[i]->size != size)
11845 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11846 : : NULL,
11847 : : "All flow queues must have the same size");
11848 : : }
11849 : :
11850 : : return 0;
11851 : : }
11852 : :
11853 : : /**
11854 : : * Configure port HWS resources.
11855 : : *
11856 : : * @param[in] dev
11857 : : * Pointer to the rte_eth_dev structure.
11858 : : * @param[in] port_attr
11859 : : * Port configuration attributes.
11860 : : * @param[in] nb_queue
11861 : : * Number of queue.
11862 : : * @param[in] queue_attr
11863 : : * Array that holds attributes for each flow queue.
11864 : : * @param[in] nt_mode
11865 : : * Non-template mode.
11866 : : * @param[out] error
11867 : : * Pointer to error structure.
11868 : : *
11869 : : * @return
11870 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
11871 : : */
11872 : : static int
11873 : 0 : __flow_hw_configure(struct rte_eth_dev *dev,
11874 : : const struct rte_flow_port_attr *port_attr,
11875 : : uint16_t nb_queue,
11876 : : const struct rte_flow_queue_attr *queue_attr[],
11877 : : bool nt_mode,
11878 : : struct rte_flow_error *error)
11879 : : {
11880 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11881 : : struct mlx5_priv *host_priv = NULL;
11882 : 0 : struct mlx5dr_context_attr dr_ctx_attr = {0};
11883 : : struct mlx5_hw_q *hw_q;
11884 : : struct mlx5_hw_q_job *job = NULL;
11885 : : uint32_t mem_size, i, j;
11886 : 0 : struct mlx5_indexed_pool_config cfg = {
11887 : : .size = sizeof(struct mlx5_action_construct_data),
11888 : : .trunk_size = 4096,
11889 : : .need_lock = 1,
11890 : 0 : .release_mem_en = !!priv->sh->config.reclaim_mode,
11891 : : .malloc = mlx5_malloc,
11892 : : .free = mlx5_free,
11893 : : .type = "mlx5_hw_action_construct_data",
11894 : : };
11895 : : /*
11896 : : * Adds one queue to be used by PMD.
11897 : : * The last queue will be used by the PMD.
11898 : : */
11899 : : uint16_t nb_q_updated = 0;
11900 : : struct rte_flow_queue_attr **_queue_attr = NULL;
11901 : 0 : struct rte_flow_queue_attr ctrl_queue_attr = {0};
11902 [ # # # # ]: 0 : bool is_proxy = !!(priv->sh->config.dv_esw_en && priv->master);
11903 : : bool unified_fdb = is_unified_fdb(priv);
11904 : : int ret = 0;
11905 : : uint32_t action_flags;
11906 : : bool strict_queue = false;
11907 : :
11908 : 0 : error->type = RTE_FLOW_ERROR_TYPE_NONE;
11909 [ # # ]: 0 : if (mlx5dr_rule_get_handle_size() != MLX5_DR_RULE_SIZE) {
11910 : 0 : rte_errno = EINVAL;
11911 : 0 : goto err;
11912 : : }
11913 [ # # ]: 0 : if (flow_hw_validate_attributes(port_attr, nb_queue, queue_attr, nt_mode, error))
11914 : 0 : return -rte_errno;
11915 : : /*
11916 : : * Calling rte_flow_configure() again is allowed if
11917 : : * provided configuration matches the initially provided one,
11918 : : * or previous configuration was default non template one.
11919 : : */
11920 [ # # ]: 0 : if (priv->dr_ctx) {
11921 : : MLX5_ASSERT(priv->hw_attr != NULL);
11922 [ # # ]: 0 : for (i = 0; i < priv->nb_queue; i++) {
11923 : 0 : hw_q = &priv->hw_q[i];
11924 : : /* Make sure all queues are empty. */
11925 [ # # ]: 0 : if (hw_q->size != hw_q->job_idx) {
11926 : 0 : rte_errno = EBUSY;
11927 : 0 : goto err;
11928 : : }
11929 : : }
11930 : : /* If previous configuration was not default non template mode config. */
11931 [ # # ]: 0 : if (!priv->hw_attr->nt_mode) {
11932 [ # # ]: 0 : if (flow_hw_compare_config(priv->hw_attr, port_attr, nb_queue, queue_attr))
11933 : : return 0;
11934 : : else
11935 : 0 : return rte_flow_error_set(error, ENOTSUP,
11936 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11937 : : "Changing HWS configuration attributes "
11938 : : "is not supported");
11939 : : }
11940 : : /* Reconfiguration, need to release all resources from previous allocation. */
11941 : 0 : __flow_hw_resource_release(dev, true);
11942 : : }
11943 : 0 : priv->hw_attr = flow_hw_alloc_copy_config(port_attr, nb_queue, queue_attr, nt_mode, error);
11944 [ # # ]: 0 : if (!priv->hw_attr) {
11945 : 0 : ret = -rte_errno;
11946 : 0 : goto err;
11947 : : }
11948 : 0 : ctrl_queue_attr.size = queue_attr[0]->size;
11949 : 0 : nb_q_updated = nb_queue + 1;
11950 : 0 : _queue_attr = mlx5_malloc(MLX5_MEM_ZERO,
11951 : : nb_q_updated *
11952 : : sizeof(struct rte_flow_queue_attr *),
11953 : : 64, SOCKET_ID_ANY);
11954 [ # # ]: 0 : if (!_queue_attr) {
11955 : 0 : rte_errno = ENOMEM;
11956 : 0 : goto err;
11957 : : }
11958 : :
11959 : 0 : memcpy(_queue_attr, queue_attr, sizeof(void *) * nb_queue);
11960 : 0 : _queue_attr[nb_queue] = &ctrl_queue_attr;
11961 : 0 : priv->acts_ipool = mlx5_ipool_create(&cfg);
11962 [ # # ]: 0 : if (!priv->acts_ipool)
11963 : 0 : goto err;
11964 : : /* Allocate the queue job descriptor LIFO. */
11965 : 0 : mem_size = sizeof(priv->hw_q[0]) * nb_q_updated;
11966 [ # # ]: 0 : for (i = 0; i < nb_q_updated; i++) {
11967 : 0 : mem_size += (sizeof(struct mlx5_hw_q_job *) +
11968 : 0 : sizeof(struct mlx5_hw_q_job)) * _queue_attr[i]->size;
11969 : : }
11970 : 0 : priv->hw_q = mlx5_malloc(MLX5_MEM_ZERO, mem_size,
11971 : : 64, SOCKET_ID_ANY);
11972 [ # # ]: 0 : if (!priv->hw_q) {
11973 : 0 : rte_errno = ENOMEM;
11974 : 0 : goto err;
11975 : : }
11976 [ # # ]: 0 : for (i = 0; i < nb_q_updated; i++) {
11977 : 0 : priv->hw_q[i].job_idx = _queue_attr[i]->size;
11978 : 0 : priv->hw_q[i].size = _queue_attr[i]->size;
11979 : 0 : priv->hw_q[i].ongoing_flow_ops = 0;
11980 [ # # ]: 0 : if (i == 0)
11981 : 0 : priv->hw_q[i].job = (struct mlx5_hw_q_job **)
11982 : 0 : &priv->hw_q[nb_q_updated];
11983 : : else
11984 : 0 : priv->hw_q[i].job = (struct mlx5_hw_q_job **)&job[_queue_attr[i - 1]->size];
11985 : 0 : job = (struct mlx5_hw_q_job *)
11986 : 0 : &priv->hw_q[i].job[_queue_attr[i]->size];
11987 [ # # ]: 0 : for (j = 0; j < _queue_attr[i]->size; j++)
11988 : 0 : priv->hw_q[i].job[j] = &job[j];
11989 : : /* Notice ring name length is limited. */
11990 : 0 : priv->hw_q[i].indir_cq = mlx5_hwq_ring_create
11991 : 0 : (dev->data->port_id, i, _queue_attr[i]->size, "indir_act_cq");
11992 [ # # ]: 0 : if (!priv->hw_q[i].indir_cq)
11993 : 0 : goto err;
11994 : 0 : priv->hw_q[i].indir_iq = mlx5_hwq_ring_create
11995 : 0 : (dev->data->port_id, i, _queue_attr[i]->size, "indir_act_iq");
11996 [ # # ]: 0 : if (!priv->hw_q[i].indir_iq)
11997 : 0 : goto err;
11998 : 0 : priv->hw_q[i].flow_transfer_pending = mlx5_hwq_ring_create
11999 : 0 : (dev->data->port_id, i, _queue_attr[i]->size, "tx_pending");
12000 [ # # ]: 0 : if (!priv->hw_q[i].flow_transfer_pending)
12001 : 0 : goto err;
12002 : 0 : priv->hw_q[i].flow_transfer_completed = mlx5_hwq_ring_create
12003 : 0 : (dev->data->port_id, i, _queue_attr[i]->size, "tx_done");
12004 [ # # ]: 0 : if (!priv->hw_q[i].flow_transfer_completed)
12005 : 0 : goto err;
12006 : : }
12007 : 0 : dr_ctx_attr.pd = priv->sh->cdev->pd;
12008 : 0 : dr_ctx_attr.queues = nb_q_updated;
12009 : : /* Assign initial value of STC numbers for representors. */
12010 [ # # ]: 0 : if (priv->representor)
12011 : 0 : dr_ctx_attr.initial_log_stc_memory = MLX5_REPR_STC_MEMORY_LOG;
12012 : : /* Queue size should all be the same. Take the first one. */
12013 : 0 : dr_ctx_attr.queue_size = _queue_attr[0]->size;
12014 [ # # ]: 0 : if (port_attr->flags & RTE_FLOW_PORT_FLAG_SHARE_INDIRECT) {
12015 : : struct rte_eth_dev *host_dev = NULL;
12016 : : uint16_t port_id;
12017 : :
12018 : : MLX5_ASSERT(rte_eth_dev_is_valid_port(port_attr->host_port_id));
12019 [ # # ]: 0 : if (is_proxy) {
12020 : 0 : DRV_LOG(ERR, "cross vHCA shared mode not supported "
12021 : : "for E-Switch confgiurations");
12022 : 0 : rte_errno = ENOTSUP;
12023 : 0 : goto err;
12024 : : }
12025 [ # # ]: 0 : MLX5_ETH_FOREACH_DEV(port_id, dev->device) {
12026 [ # # ]: 0 : if (port_id == port_attr->host_port_id) {
12027 : 0 : host_dev = &rte_eth_devices[port_id];
12028 : 0 : break;
12029 : : }
12030 : : }
12031 [ # # ]: 0 : if (!host_dev || host_dev == dev ||
12032 [ # # # # ]: 0 : !host_dev->data || !host_dev->data->dev_private) {
12033 : 0 : DRV_LOG(ERR, "Invalid cross vHCA host port %u",
12034 : : port_attr->host_port_id);
12035 : 0 : rte_errno = EINVAL;
12036 : 0 : goto err;
12037 : : }
12038 : : host_priv = host_dev->data->dev_private;
12039 [ # # ]: 0 : if (host_priv->sh->cdev->ctx == priv->sh->cdev->ctx) {
12040 : 0 : DRV_LOG(ERR, "Sibling ports %u and %u do not "
12041 : : "require cross vHCA sharing mode",
12042 : : dev->data->port_id, port_attr->host_port_id);
12043 : 0 : rte_errno = EINVAL;
12044 : 0 : goto err;
12045 : : }
12046 [ # # ]: 0 : if (host_priv->shared_host) {
12047 : 0 : DRV_LOG(ERR, "Host port %u is not the sharing base",
12048 : : port_attr->host_port_id);
12049 : 0 : rte_errno = EINVAL;
12050 : 0 : goto err;
12051 : : }
12052 [ # # ]: 0 : if (port_attr->nb_counters ||
12053 [ # # ]: 0 : port_attr->nb_aging_objects ||
12054 [ # # ]: 0 : port_attr->nb_meters ||
12055 [ # # ]: 0 : port_attr->nb_conn_tracks) {
12056 : 0 : DRV_LOG(ERR,
12057 : : "Object numbers on guest port must be zeros");
12058 : 0 : rte_errno = EINVAL;
12059 : 0 : goto err;
12060 : : }
12061 : 0 : dr_ctx_attr.shared_ibv_ctx = host_priv->sh->cdev->ctx;
12062 : 0 : priv->shared_host = host_dev;
12063 : 0 : rte_atomic_fetch_add_explicit(&host_priv->shared_refcnt, 1,
12064 : : rte_memory_order_relaxed);
12065 : : }
12066 : : /* Set backward compatibale mode to support non template RTE FLOW API.*/
12067 : 0 : dr_ctx_attr.bwc = true;
12068 : 0 : priv->dr_ctx = mlx5dr_context_open(priv->sh->cdev->ctx, &dr_ctx_attr);
12069 : : /* rte_errno has been updated by HWS layer. */
12070 [ # # ]: 0 : if (!priv->dr_ctx)
12071 : 0 : goto err;
12072 : 0 : priv->nb_queue = nb_q_updated;
12073 : 0 : ret = flow_hw_action_template_drop_init(dev, error);
12074 [ # # ]: 0 : if (ret)
12075 : 0 : goto err;
12076 : 0 : ret = flow_hw_create_ctrl_rx_tables(dev);
12077 [ # # ]: 0 : if (ret) {
12078 : 0 : rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12079 : : "Failed to set up Rx control flow templates");
12080 : 0 : goto err;
12081 : : }
12082 : : /* Initialize quotas */
12083 [ # # # # : 0 : if (port_attr->nb_quotas || (host_priv && host_priv->quota_ctx.devx_obj)) {
# # ]
12084 : 0 : ret = mlx5_flow_quota_init(dev, port_attr->nb_quotas);
12085 [ # # ]: 0 : if (ret) {
12086 : 0 : rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12087 : : "Failed to initialize quota.");
12088 : 0 : goto err;
12089 : : }
12090 : : }
12091 : : /* Initialize meter library*/
12092 [ # # # # : 0 : if (port_attr->nb_meters || (host_priv && host_priv->hws_mpool))
# # ]
12093 [ # # ]: 0 : if (mlx5_flow_meter_init(dev, port_attr->nb_meters, 0, 0, nb_q_updated))
12094 : 0 : goto err;
12095 : : /* Add global actions. */
12096 [ # # ]: 0 : for (i = 0; i < MLX5_HW_ACTION_FLAG_MAX; i++) {
12097 : : uint32_t act_flags = 0;
12098 : 0 : uint32_t tag_flags = mlx5_hw_act_flag[i][0];
12099 : :
12100 : 0 : act_flags = mlx5_hw_act_flag[i][MLX5DR_TABLE_TYPE_NIC_RX] |
12101 : 0 : mlx5_hw_act_flag[i][MLX5DR_TABLE_TYPE_NIC_TX];
12102 [ # # ]: 0 : if (is_proxy) {
12103 : : /* Tag action is valid only in FDB_Rx domain. */
12104 [ # # ]: 0 : if (unified_fdb) {
12105 : 0 : act_flags |=
12106 : 0 : (mlx5_hw_act_flag[i][MLX5DR_TABLE_TYPE_FDB_RX] |
12107 : 0 : mlx5_hw_act_flag[i][MLX5DR_TABLE_TYPE_FDB_TX] |
12108 : 0 : mlx5_hw_act_flag[i][MLX5DR_TABLE_TYPE_FDB_UNIFIED]);
12109 [ # # ]: 0 : if (i == MLX5_HW_ACTION_FLAG_NONE_ROOT)
12110 : 0 : tag_flags |= mlx5_hw_act_flag[i][MLX5DR_TABLE_TYPE_FDB_RX];
12111 : : } else {
12112 : 0 : act_flags |= mlx5_hw_act_flag[i][MLX5DR_TABLE_TYPE_FDB];
12113 [ # # ]: 0 : if (i == MLX5_HW_ACTION_FLAG_NONE_ROOT)
12114 : 0 : tag_flags |= mlx5_hw_act_flag[i][MLX5DR_TABLE_TYPE_FDB];
12115 : : }
12116 : : }
12117 : 0 : priv->hw_drop[i] = mlx5dr_action_create_dest_drop(priv->dr_ctx, act_flags);
12118 [ # # ]: 0 : if (!priv->hw_drop[i])
12119 : 0 : goto err;
12120 : 0 : priv->hw_tag[i] = mlx5dr_action_create_tag
12121 : : (priv->dr_ctx, tag_flags);
12122 [ # # ]: 0 : if (!priv->hw_tag[i])
12123 : 0 : goto err;
12124 : : }
12125 [ # # # # ]: 0 : if (priv->sh->config.dv_esw_en && priv->sh->config.repr_matching) {
12126 : 0 : ret = flow_hw_setup_tx_repr_tagging(dev, error);
12127 [ # # ]: 0 : if (ret)
12128 : 0 : goto err;
12129 : : }
12130 : : /*
12131 : : * DEFAULT_MISS action have different behaviors in different domains.
12132 : : * In FDB, it will steering the packets to the E-switch manager.
12133 : : * In NIC Rx root, it will steering the packet to the kernel driver stack.
12134 : : * An action with all bits set in the flag can be created and the HWS
12135 : : * layer will translate it properly when being used in different rules.
12136 : : */
12137 : : action_flags = MLX5DR_ACTION_FLAG_ROOT_RX | MLX5DR_ACTION_FLAG_HWS_RX |
12138 : : MLX5DR_ACTION_FLAG_ROOT_TX | MLX5DR_ACTION_FLAG_HWS_TX;
12139 [ # # ]: 0 : if (is_proxy) {
12140 [ # # ]: 0 : if (unified_fdb)
12141 : : action_flags |=
12142 : : (MLX5DR_ACTION_FLAG_ROOT_FDB |
12143 : : MLX5DR_ACTION_FLAG_HWS_FDB_RX |
12144 : : MLX5DR_ACTION_FLAG_HWS_FDB_TX |
12145 : : MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED);
12146 : : else
12147 : : action_flags |=
12148 : : (MLX5DR_ACTION_FLAG_ROOT_FDB |
12149 : : MLX5DR_ACTION_FLAG_HWS_FDB);
12150 : : }
12151 : 0 : priv->hw_def_miss = mlx5dr_action_create_default_miss(priv->dr_ctx, action_flags);
12152 [ # # ]: 0 : if (!priv->hw_def_miss)
12153 : 0 : goto err;
12154 [ # # ]: 0 : if (is_proxy) {
12155 : 0 : ret = flow_hw_create_vport_actions(priv);
12156 [ # # ]: 0 : if (ret) {
12157 : 0 : rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12158 : : NULL, "Failed to create vport actions.");
12159 : 0 : goto err;
12160 : : }
12161 : 0 : ret = flow_hw_create_ctrl_tables(dev, error);
12162 [ # # ]: 0 : if (ret) {
12163 : 0 : rte_errno = -ret;
12164 : 0 : goto err;
12165 : : }
12166 : : }
12167 : : if (!priv->shared_host)
12168 : : flow_hw_create_send_to_kernel_actions(priv, is_proxy);
12169 [ # # # # : 0 : if (port_attr->nb_conn_tracks || (host_priv && host_priv->hws_ctpool)) {
# # ]
12170 [ # # ]: 0 : if (mlx5_flow_ct_init(dev, port_attr->nb_conn_tracks, nb_q_updated))
12171 : 0 : goto err;
12172 : : }
12173 [ # # # # : 0 : if (port_attr->nb_counters || (host_priv && host_priv->hws_cpool)) {
# # ]
12174 [ # # ]: 0 : struct mlx5_hws_cnt_pool *hws_cpool = host_priv ? host_priv->hws_cpool : NULL;
12175 : :
12176 : 0 : ret = mlx5_hws_cnt_pool_create(dev, port_attr->nb_counters,
12177 : : nb_queue, hws_cpool, error);
12178 [ # # ]: 0 : if (ret)
12179 : 0 : goto err;
12180 : : }
12181 [ # # ]: 0 : if (port_attr->nb_aging_objects) {
12182 [ # # ]: 0 : if (port_attr->nb_counters == 0) {
12183 : : /*
12184 : : * Aging management uses counter. Number counters
12185 : : * requesting should take into account a counter for
12186 : : * each flow rules containing AGE without counter.
12187 : : */
12188 : 0 : DRV_LOG(ERR, "Port %u AGE objects are requested (%u) "
12189 : : "without counters requesting.",
12190 : : dev->data->port_id,
12191 : : port_attr->nb_aging_objects);
12192 : 0 : rte_errno = EINVAL;
12193 : 0 : goto err;
12194 : : }
12195 [ # # ]: 0 : if (port_attr->flags & RTE_FLOW_PORT_FLAG_SHARE_INDIRECT) {
12196 : 0 : DRV_LOG(ERR, "Aging is not supported "
12197 : : "in cross vHCA sharing mode");
12198 : : ret = -ENOTSUP;
12199 : 0 : goto err;
12200 : : }
12201 : 0 : strict_queue = !!(port_attr->flags & RTE_FLOW_PORT_FLAG_STRICT_QUEUE);
12202 : 0 : ret = mlx5_hws_age_pool_init(dev, port_attr->nb_aging_objects,
12203 : : nb_queue, strict_queue);
12204 [ # # ]: 0 : if (ret < 0)
12205 : 0 : goto err;
12206 : : }
12207 : 0 : ret = flow_hw_create_vlan(dev);
12208 [ # # ]: 0 : if (ret) {
12209 : 0 : rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12210 : : NULL, "Failed to VLAN actions.");
12211 : 0 : goto err;
12212 : : }
12213 [ # # ]: 0 : if (flow_hw_should_create_nat64_actions(priv)) {
12214 [ # # ]: 0 : if (flow_hw_create_nat64_actions(priv, error))
12215 : 0 : goto err;
12216 : : } else {
12217 : 0 : DRV_LOG(WARNING, "Cannot create NAT64 action on port %u, "
12218 : : "please check the FW version. NAT64 will not be supported.",
12219 : : dev->data->port_id);
12220 : : }
12221 : : if (_queue_attr)
12222 : 0 : mlx5_free(_queue_attr);
12223 [ # # ]: 0 : if (port_attr->flags & RTE_FLOW_PORT_FLAG_STRICT_QUEUE)
12224 : 0 : priv->hws_strict_queue = 1;
12225 : 0 : dev->flow_fp_ops = &mlx5_flow_hw_fp_ops;
12226 : 0 : return 0;
12227 : 0 : err:
12228 : 0 : __flow_hw_resource_release(dev, true);
12229 [ # # ]: 0 : if (_queue_attr)
12230 : 0 : mlx5_free(_queue_attr);
12231 : : /* Do not overwrite the internal errno information. */
12232 [ # # # # ]: 0 : if (ret && error->type != RTE_FLOW_ERROR_TYPE_NONE)
12233 : : return ret;
12234 : 0 : return rte_flow_error_set(error, rte_errno,
12235 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12236 : : "fail to configure port");
12237 : : }
12238 : :
12239 : : /**
12240 : : * Configure port HWS resources.
12241 : : *
12242 : : * @param[in] dev
12243 : : * Pointer to the rte_eth_dev structure.
12244 : : * @param[in] port_attr
12245 : : * Port configuration attributes.
12246 : : * @param[in] nb_queue
12247 : : * Number of queue.
12248 : : * @param[in] queue_attr
12249 : : * Array that holds attributes for each flow queue.
12250 : : * @param[out] error
12251 : : * Pointer to error structure.
12252 : : *
12253 : : * @return
12254 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
12255 : : */
12256 : : static int
12257 : 0 : flow_hw_configure(struct rte_eth_dev *dev,
12258 : : const struct rte_flow_port_attr *port_attr,
12259 : : uint16_t nb_queue,
12260 : : const struct rte_flow_queue_attr *queue_attr[],
12261 : : struct rte_flow_error *error)
12262 : : {
12263 : 0 : struct rte_flow_error shadow_error = {0, };
12264 : :
12265 [ # # ]: 0 : if (!error)
12266 : : error = &shadow_error;
12267 : 0 : return __flow_hw_configure(dev, port_attr, nb_queue, queue_attr, false, error);
12268 : : }
12269 : :
12270 : : /**
12271 : : * Release HWS resources.
12272 : : *
12273 : : * @param[in] dev
12274 : : * Pointer to the rte_eth_dev structure.
12275 : : */
12276 : : void
12277 : 0 : flow_hw_resource_release(struct rte_eth_dev *dev)
12278 : : {
12279 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12280 : :
12281 [ # # ]: 0 : if (!priv->dr_ctx)
12282 : : return;
12283 : 0 : __flow_hw_resource_release(dev, false);
12284 : : }
12285 : :
12286 : : /* Sets vport tag and mask, for given port, used in HWS rules. */
12287 : : void
12288 : 0 : flow_hw_set_port_info(struct rte_eth_dev *dev)
12289 : : {
12290 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12291 : 0 : uint16_t port_id = dev->data->port_id;
12292 : : struct flow_hw_port_info *info;
12293 : :
12294 : : MLX5_ASSERT(port_id < RTE_MAX_ETHPORTS);
12295 : 0 : info = &mlx5_flow_hw_port_infos[port_id];
12296 : 0 : info->regc_mask = priv->vport_meta_mask;
12297 [ # # ]: 0 : info->regc_value = priv->vport_meta_tag;
12298 [ # # ]: 0 : info->is_wire = mlx5_is_port_on_mpesw_device(priv) ? priv->mpesw_uplink : priv->master;
12299 : 0 : }
12300 : :
12301 : : /* Clears vport tag and mask used for HWS rules. */
12302 : : void
12303 : 0 : flow_hw_clear_port_info(struct rte_eth_dev *dev)
12304 : : {
12305 : 0 : uint16_t port_id = dev->data->port_id;
12306 : : struct flow_hw_port_info *info;
12307 : :
12308 : : MLX5_ASSERT(port_id < RTE_MAX_ETHPORTS);
12309 : 0 : info = &mlx5_flow_hw_port_infos[port_id];
12310 : 0 : info->regc_mask = 0;
12311 : 0 : info->regc_value = 0;
12312 : 0 : info->is_wire = 0;
12313 : 0 : }
12314 : :
12315 : : static int
12316 : 0 : flow_hw_conntrack_destroy(struct rte_eth_dev *dev,
12317 : : uint32_t idx,
12318 : : struct rte_flow_error *error)
12319 : : {
12320 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12321 : 0 : struct mlx5_aso_ct_pool *pool = priv->hws_ctpool;
12322 : : struct mlx5_aso_ct_action *ct;
12323 : :
12324 [ # # ]: 0 : if (priv->shared_host)
12325 : 0 : return rte_flow_error_set(error, ENOTSUP,
12326 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12327 : : NULL,
12328 : : "CT destruction is not allowed to guest port");
12329 : 0 : ct = mlx5_ipool_get(pool->cts, idx);
12330 [ # # ]: 0 : if (!ct) {
12331 : 0 : return rte_flow_error_set(error, EINVAL,
12332 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12333 : : NULL,
12334 : : "Invalid CT destruction index");
12335 : : }
12336 : 0 : rte_atomic_store_explicit(&ct->state, ASO_CONNTRACK_FREE,
12337 : : rte_memory_order_relaxed);
12338 : 0 : mlx5_ipool_free(pool->cts, idx);
12339 : 0 : return 0;
12340 : : }
12341 : :
12342 : : static int
12343 : 0 : flow_hw_conntrack_query(struct rte_eth_dev *dev, uint32_t queue, uint32_t idx,
12344 : : struct rte_flow_action_conntrack *profile,
12345 : : void *user_data, bool push,
12346 : : struct rte_flow_error *error)
12347 : : {
12348 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12349 : 0 : struct mlx5_aso_ct_pool *pool = priv->hws_ctpool;
12350 : : struct mlx5_aso_ct_action *ct;
12351 : :
12352 [ # # ]: 0 : if (priv->shared_host)
12353 : 0 : return rte_flow_error_set(error, ENOTSUP,
12354 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12355 : : NULL,
12356 : : "CT query is not allowed to guest port");
12357 : 0 : ct = mlx5_ipool_get(pool->cts, idx);
12358 [ # # ]: 0 : if (!ct) {
12359 : 0 : return rte_flow_error_set(error, EINVAL,
12360 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12361 : : NULL,
12362 : : "Invalid CT query index");
12363 : : }
12364 : 0 : profile->peer_port = ct->peer;
12365 : 0 : profile->is_original_dir = ct->is_original;
12366 [ # # ]: 0 : if (mlx5_aso_ct_query_by_wqe(priv->sh, queue, ct, profile, user_data, push))
12367 : 0 : return rte_flow_error_set(error, EIO,
12368 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12369 : : NULL,
12370 : : "Failed to query CT context");
12371 : : return 0;
12372 : : }
12373 : :
12374 : :
12375 : : static int
12376 : 0 : flow_hw_conntrack_update(struct rte_eth_dev *dev, uint32_t queue,
12377 : : const struct rte_flow_modify_conntrack *action_conf,
12378 : : uint32_t idx, void *user_data, bool push,
12379 : : struct rte_flow_error *error)
12380 : : {
12381 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12382 : 0 : struct mlx5_aso_ct_pool *pool = priv->hws_ctpool;
12383 : : struct mlx5_aso_ct_action *ct;
12384 : : const struct rte_flow_action_conntrack *new_prf;
12385 : : int ret = 0;
12386 : :
12387 [ # # ]: 0 : if (priv->shared_host)
12388 : 0 : return rte_flow_error_set(error, ENOTSUP,
12389 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12390 : : NULL,
12391 : : "CT update is not allowed to guest port");
12392 : 0 : ct = mlx5_ipool_get(pool->cts, idx);
12393 [ # # ]: 0 : if (!ct) {
12394 : 0 : return rte_flow_error_set(error, EINVAL,
12395 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12396 : : NULL,
12397 : : "Invalid CT update index");
12398 : : }
12399 : 0 : new_prf = &action_conf->new_ct;
12400 [ # # ]: 0 : if (action_conf->direction)
12401 : 0 : ct->is_original = !!new_prf->is_original_dir;
12402 [ # # ]: 0 : if (action_conf->state) {
12403 : : /* Only validate the profile when it needs to be updated. */
12404 : 0 : ret = mlx5_validate_action_ct(dev, new_prf, error);
12405 [ # # ]: 0 : if (ret)
12406 : : return ret;
12407 : 0 : ret = mlx5_aso_ct_update_by_wqe(priv->sh, queue, ct, new_prf,
12408 : : user_data, push);
12409 [ # # ]: 0 : if (ret)
12410 : 0 : return rte_flow_error_set(error, EIO,
12411 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12412 : : NULL,
12413 : : "Failed to send CT context update WQE");
12414 [ # # ]: 0 : if (queue != MLX5_HW_INV_QUEUE)
12415 : : return 0;
12416 : : /* Block until ready or a failure in synchronous mode. */
12417 : 0 : ret = mlx5_aso_ct_available(priv->sh, queue, ct);
12418 [ # # ]: 0 : if (ret)
12419 : 0 : rte_flow_error_set(error, rte_errno,
12420 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12421 : : NULL,
12422 : : "Timeout to get the CT update");
12423 : : }
12424 : : return ret;
12425 : : }
12426 : :
12427 : : static struct rte_flow_action_handle *
12428 : 0 : flow_hw_conntrack_create(struct rte_eth_dev *dev, uint32_t queue,
12429 : : const struct rte_flow_action_conntrack *pro,
12430 : : void *user_data, bool push,
12431 : : struct rte_flow_error *error)
12432 : : {
12433 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12434 : 0 : struct mlx5_aso_ct_pool *pool = priv->hws_ctpool;
12435 : : struct mlx5_aso_ct_action *ct;
12436 : 0 : uint32_t ct_idx = 0;
12437 : : int ret;
12438 : : bool async = !!(queue != MLX5_HW_INV_QUEUE);
12439 : :
12440 [ # # ]: 0 : if (priv->shared_host) {
12441 : 0 : rte_flow_error_set(error, ENOTSUP,
12442 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12443 : : NULL,
12444 : : "CT create is not allowed to guest port");
12445 : 0 : return NULL;
12446 : : }
12447 [ # # ]: 0 : if (!pool) {
12448 : 0 : rte_flow_error_set(error, EINVAL,
12449 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12450 : : "CT is not enabled");
12451 : 0 : return 0;
12452 : : }
12453 : 0 : ct = mlx5_ipool_zmalloc(pool->cts, &ct_idx);
12454 [ # # ]: 0 : if (!ct) {
12455 : 0 : rte_flow_error_set(error, rte_errno,
12456 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12457 : : "Failed to allocate CT object");
12458 : 0 : return 0;
12459 : : }
12460 : 0 : ct->offset = ct_idx - 1;
12461 : 0 : ct->is_original = !!pro->is_original_dir;
12462 : 0 : ct->peer = pro->peer_port;
12463 : 0 : ct->pool = pool;
12464 [ # # ]: 0 : if (mlx5_aso_ct_update_by_wqe(priv->sh, queue, ct, pro, user_data, push)) {
12465 : 0 : mlx5_ipool_free(pool->cts, ct_idx);
12466 : 0 : rte_flow_error_set(error, EBUSY,
12467 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12468 : : "Failed to update CT");
12469 : 0 : return 0;
12470 : : }
12471 [ # # ]: 0 : if (!async) {
12472 : 0 : ret = mlx5_aso_ct_available(priv->sh, queue, ct);
12473 [ # # ]: 0 : if (ret) {
12474 : 0 : mlx5_ipool_free(pool->cts, ct_idx);
12475 : 0 : rte_flow_error_set(error, rte_errno,
12476 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12477 : : NULL,
12478 : : "Timeout to get the CT update");
12479 : 0 : return 0;
12480 : : }
12481 : : }
12482 : 0 : return MLX5_INDIRECT_ACT_HWS_CT_GEN_IDX(ct_idx);
12483 : : }
12484 : :
12485 : : /**
12486 : : * Validate shared action.
12487 : : *
12488 : : * @param[in] dev
12489 : : * Pointer to the rte_eth_dev structure.
12490 : : * @param[in] queue
12491 : : * Which queue to be used.
12492 : : * @param[in] attr
12493 : : * Operation attribute.
12494 : : * @param[in] conf
12495 : : * Indirect action configuration.
12496 : : * @param[in] action
12497 : : * rte_flow action detail.
12498 : : * @param[in] user_data
12499 : : * Pointer to the user_data.
12500 : : * @param[out] error
12501 : : * Pointer to error structure.
12502 : : *
12503 : : * @return
12504 : : * 0 on success, otherwise negative errno value.
12505 : : */
12506 : : static int
12507 : 0 : flow_hw_action_handle_validate(struct rte_eth_dev *dev, uint32_t queue,
12508 : : const struct rte_flow_op_attr *attr,
12509 : : const struct rte_flow_indir_action_conf *conf,
12510 : : const struct rte_flow_action *action,
12511 : : void *user_data,
12512 : : struct rte_flow_error *error)
12513 : : {
12514 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12515 : :
12516 : : RTE_SET_USED(attr);
12517 : : RTE_SET_USED(queue);
12518 : : RTE_SET_USED(user_data);
12519 [ # # # # : 0 : switch (action->type) {
# # # ]
12520 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
12521 [ # # ]: 0 : if (!priv->hws_age_req) {
12522 [ # # ]: 0 : if (flow_hw_allocate_actions(dev, MLX5_FLOW_ACTION_AGE,
12523 : : error))
12524 : 0 : return rte_flow_error_set
12525 : : (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
12526 : : NULL, "aging pool not initialized");
12527 : : }
12528 : : break;
12529 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
12530 [ # # ]: 0 : if (!priv->hws_cpool) {
12531 [ # # ]: 0 : if (flow_hw_allocate_actions(dev, MLX5_FLOW_ACTION_COUNT,
12532 : : error))
12533 : 0 : return rte_flow_error_set
12534 : : (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
12535 : : NULL, "counters pool not initialized");
12536 : : }
12537 : : break;
12538 : 0 : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
12539 [ # # ]: 0 : if (priv->hws_ctpool == NULL) {
12540 [ # # ]: 0 : if (flow_hw_allocate_actions(dev, MLX5_FLOW_ACTION_CT,
12541 : : error))
12542 : 0 : return rte_flow_error_set
12543 : : (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
12544 : : NULL, "CT pool not initialized");
12545 : : }
12546 : 0 : return mlx5_validate_action_ct(dev, action->conf, error);
12547 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
12548 : 0 : return flow_hw_validate_action_meter_mark(dev, action, true, error);
12549 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
12550 : 0 : return flow_dv_action_validate(dev, conf, action, error);
12551 : : case RTE_FLOW_ACTION_TYPE_QUOTA:
12552 : : return 0;
12553 : 0 : default:
12554 : 0 : return rte_flow_error_set(error, ENOTSUP,
12555 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12556 : : "action type not supported");
12557 : : }
12558 : : return 0;
12559 : : }
12560 : :
12561 : : static __rte_always_inline bool
12562 : : flow_hw_action_push(const struct rte_flow_op_attr *attr)
12563 : : {
12564 [ # # # # : 0 : return attr ? !attr->postpone : true;
# # # # #
# # # #
# ]
12565 : : }
12566 : :
12567 : : static __rte_always_inline struct mlx5_hw_q_job *
12568 : : flow_hw_action_job_init(struct mlx5_priv *priv, uint32_t queue,
12569 : : const struct rte_flow_action_handle *handle,
12570 : : void *user_data, void *query_data,
12571 : : enum mlx5_hw_job_type type,
12572 : : enum mlx5_hw_indirect_type indirect_type,
12573 : : struct rte_flow_error *error)
12574 : : {
12575 : : struct mlx5_hw_q_job *job;
12576 : :
12577 [ # # # # : 0 : if (queue == MLX5_HW_INV_QUEUE)
# # # # #
# # # #
# ]
12578 [ # # # # : 0 : queue = CTRL_QUEUE_ID(priv);
# # # # #
# # # ]
12579 : : job = flow_hw_job_get(priv, queue);
12580 [ # # # # : 0 : if (!job) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # ]
12581 : 0 : rte_flow_error_set(error, ENOMEM,
12582 : : RTE_FLOW_ERROR_TYPE_ACTION_NUM, NULL,
12583 : : "Action destroy failed due to queue full.");
12584 : 0 : return NULL;
12585 : : }
12586 : 0 : job->type = type;
12587 : 0 : job->action = handle;
12588 : 0 : job->user_data = user_data;
12589 : 0 : job->query.user = query_data;
12590 [ # # # # : 0 : job->indirect_type = indirect_type;
# # # # #
# # # ]
12591 : 0 : return job;
12592 : : }
12593 : :
12594 : : struct mlx5_hw_q_job *
12595 [ # # ]: 0 : mlx5_flow_action_job_init(struct mlx5_priv *priv, uint32_t queue,
12596 : : const struct rte_flow_action_handle *handle,
12597 : : void *user_data, void *query_data,
12598 : : enum mlx5_hw_job_type type,
12599 : : struct rte_flow_error *error)
12600 : : {
12601 : 0 : return flow_hw_action_job_init(priv, queue, handle, user_data, query_data,
12602 : : type, MLX5_HW_INDIRECT_TYPE_LEGACY, error);
12603 : : }
12604 : :
12605 : : static __rte_always_inline void
12606 : : flow_hw_action_finalize(struct rte_eth_dev *dev, uint32_t queue,
12607 : : struct mlx5_hw_q_job *job,
12608 : : bool push, bool aso, bool status)
12609 : : {
12610 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12611 : :
12612 [ # # ]: 0 : if (queue == MLX5_HW_INV_QUEUE)
12613 : 0 : queue = CTRL_QUEUE_ID(priv);
12614 [ # # # # : 0 : if (likely(status)) {
# # # # #
# # # ]
12615 : : /* 1. add new job to a queue */
12616 [ # # # # : 0 : if (!aso)
# # # # #
# ]
12617 [ # # # # : 0 : rte_ring_enqueue(push ?
# # # # #
# # # #
# ]
12618 : 0 : priv->hw_q[queue].indir_cq :
12619 : 0 : priv->hw_q[queue].indir_iq,
12620 : : job);
12621 : : /* 2. send pending jobs */
12622 [ # # # # : 0 : if (push)
# # # # #
# # # #
# ]
12623 : 0 : __flow_hw_push_action(dev, queue);
12624 : : } else {
12625 : : flow_hw_job_put(priv, job, queue);
12626 : : }
12627 : : }
12628 : :
12629 : : /**
12630 : : * Create shared action.
12631 : : *
12632 : : * @param[in] dev
12633 : : * Pointer to the rte_eth_dev structure.
12634 : : * @param[in] queue
12635 : : * Which queue to be used.
12636 : : * @param[in] attr
12637 : : * Operation attribute.
12638 : : * @param[in] conf
12639 : : * Indirect action configuration.
12640 : : * @param[in] action
12641 : : * rte_flow action detail.
12642 : : * @param[in] user_data
12643 : : * Pointer to the user_data.
12644 : : * @param[out] error
12645 : : * Pointer to error structure.
12646 : : *
12647 : : * @return
12648 : : * Action handle on success, NULL otherwise and rte_errno is set.
12649 : : */
12650 : : static struct rte_flow_action_handle *
12651 : 0 : flow_hw_action_handle_create(struct rte_eth_dev *dev, uint32_t queue,
12652 : : const struct rte_flow_op_attr *attr,
12653 : : const struct rte_flow_indir_action_conf *conf,
12654 : : const struct rte_flow_action *action,
12655 : : void *user_data,
12656 : : struct rte_flow_error *error)
12657 : : {
12658 : : struct rte_flow_action_handle *handle = NULL;
12659 : : struct mlx5_hw_q_job *job = NULL;
12660 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
12661 : : const struct rte_flow_action_age *age;
12662 : : struct mlx5_aso_mtr *aso_mtr;
12663 : : cnt_id_t cnt_id;
12664 : : uint32_t age_idx;
12665 : : bool push = flow_hw_action_push(attr);
12666 : : bool aso = false;
12667 : 0 : bool force_job = action->type == RTE_FLOW_ACTION_TYPE_METER_MARK;
12668 : :
12669 [ # # ]: 0 : if (!mlx5_hw_ctx_validate(dev, error))
12670 : : return NULL;
12671 [ # # ]: 0 : if (attr || force_job) {
12672 : : job = flow_hw_action_job_init(priv, queue, NULL, user_data,
12673 : : NULL, MLX5_HW_Q_JOB_TYPE_CREATE,
12674 : : MLX5_HW_INDIRECT_TYPE_LEGACY, error);
12675 : : if (!job)
12676 : 0 : return NULL;
12677 : : }
12678 [ # # # # : 0 : switch (action->type) {
# # # ]
12679 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
12680 [ # # ]: 0 : if (priv->hws_strict_queue) {
12681 : 0 : struct mlx5_age_info *info = GET_PORT_AGE_INFO(priv);
12682 : :
12683 [ # # ]: 0 : if (queue >= info->hw_q_age->nb_rings) {
12684 : 0 : rte_flow_error_set(error, EINVAL,
12685 : : RTE_FLOW_ERROR_TYPE_ACTION,
12686 : : NULL,
12687 : : "Invalid queue ID for indirect AGE.");
12688 : 0 : rte_errno = EINVAL;
12689 : 0 : return NULL;
12690 : : }
12691 : : }
12692 : 0 : age = action->conf;
12693 : 0 : age_idx = mlx5_hws_age_action_create(priv, queue, true, age,
12694 : : 0, error);
12695 [ # # ]: 0 : if (age_idx == 0) {
12696 : 0 : rte_flow_error_set(error, ENODEV,
12697 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12698 : : "AGE are not configured!");
12699 : : } else {
12700 : 0 : age_idx = (MLX5_INDIRECT_ACTION_TYPE_AGE <<
12701 : : MLX5_INDIRECT_ACTION_TYPE_OFFSET) | age_idx;
12702 : 0 : handle =
12703 : 0 : (struct rte_flow_action_handle *)(uintptr_t)age_idx;
12704 : : }
12705 : : break;
12706 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
12707 [ # # ]: 0 : if (mlx5_hws_cnt_shared_get(priv->hws_cpool, &cnt_id, 0))
12708 : 0 : rte_flow_error_set(error, ENODEV,
12709 : : RTE_FLOW_ERROR_TYPE_ACTION,
12710 : : NULL,
12711 : : "counter are not configured!");
12712 : : else
12713 : 0 : handle = (struct rte_flow_action_handle *)
12714 : 0 : (uintptr_t)cnt_id;
12715 : : break;
12716 : 0 : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
12717 : : aso = true;
12718 : 0 : handle = flow_hw_conntrack_create(dev, queue, action->conf, job,
12719 : : push, error);
12720 : 0 : break;
12721 [ # # ]: 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
12722 : : aso = true;
12723 : : aso_mtr = flow_hw_meter_mark_alloc(dev, queue, action, job, push, error);
12724 : : if (!aso_mtr)
12725 : : break;
12726 : 0 : handle = (void *)(uintptr_t)job->action;
12727 : 0 : break;
12728 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
12729 : 0 : handle = flow_dv_action_create(dev, conf, action, error);
12730 : 0 : break;
12731 : 0 : case RTE_FLOW_ACTION_TYPE_QUOTA:
12732 : : aso = true;
12733 : 0 : handle = mlx5_quota_alloc(dev, queue, action->conf,
12734 : : job, push, error);
12735 : 0 : break;
12736 : 0 : default:
12737 : 0 : rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
12738 : : NULL, "action type not supported");
12739 : 0 : break;
12740 : : }
12741 [ # # ]: 0 : if (job && !force_job) {
12742 : 0 : job->action = handle;
12743 [ # # ]: 0 : flow_hw_action_finalize(dev, queue, job, push, aso,
12744 : : handle != NULL);
12745 : : }
12746 : : return handle;
12747 : : }
12748 : :
12749 : : static int
12750 : 0 : mlx5_flow_update_meter_mark(struct rte_eth_dev *dev, uint32_t queue,
12751 : : const struct rte_flow_update_meter_mark *upd_meter_mark,
12752 : : uint32_t idx, bool push,
12753 : : struct mlx5_hw_q_job *job, struct rte_flow_error *error)
12754 : : {
12755 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12756 : 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
12757 : : const struct rte_flow_action_meter_mark *meter_mark = &upd_meter_mark->meter_mark;
12758 : 0 : struct mlx5_aso_mtr *aso_mtr = mlx5_ipool_get(pool->idx_pool, idx);
12759 : : struct mlx5_flow_meter_info *fm;
12760 : :
12761 [ # # ]: 0 : if (!aso_mtr)
12762 : 0 : return rte_flow_error_set(error, EINVAL,
12763 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12764 : : NULL, "Invalid meter_mark update index");
12765 : : fm = &aso_mtr->fm;
12766 [ # # ]: 0 : if (upd_meter_mark->profile_valid)
12767 : 0 : fm->profile = (struct mlx5_flow_meter_profile *)
12768 : 0 : (meter_mark->profile);
12769 [ # # ]: 0 : if (upd_meter_mark->color_mode_valid)
12770 : 0 : fm->color_aware = meter_mark->color_mode;
12771 [ # # ]: 0 : if (upd_meter_mark->state_valid)
12772 : 0 : fm->is_enable = meter_mark->state;
12773 [ # # ]: 0 : aso_mtr->state = (queue == MLX5_HW_INV_QUEUE) ?
12774 : : ASO_METER_WAIT : ASO_METER_WAIT_ASYNC;
12775 : : /* Update ASO flow meter by wqe. */
12776 [ # # ]: 0 : if (mlx5_aso_meter_update_by_wqe(priv, queue,
12777 : : aso_mtr, &priv->mtr_bulk, job, push))
12778 : 0 : return rte_flow_error_set(error, EINVAL,
12779 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12780 : : NULL, "Unable to update ASO meter WQE");
12781 : : /* Wait for ASO object completion. */
12782 [ # # # # ]: 0 : if (queue == MLX5_HW_INV_QUEUE &&
12783 : 0 : mlx5_aso_mtr_wait(priv, aso_mtr, true))
12784 : 0 : return rte_flow_error_set(error, EINVAL,
12785 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12786 : : NULL, "Unable to wait for ASO meter CQE");
12787 : : return 0;
12788 : : }
12789 : :
12790 : : /**
12791 : : * Update shared action.
12792 : : *
12793 : : * @param[in] dev
12794 : : * Pointer to the rte_eth_dev structure.
12795 : : * @param[in] queue
12796 : : * Which queue to be used.
12797 : : * @param[in] attr
12798 : : * Operation attribute.
12799 : : * @param[in] handle
12800 : : * Action handle to be updated.
12801 : : * @param[in] update
12802 : : * Update value.
12803 : : * @param[in] user_data
12804 : : * Pointer to the user_data.
12805 : : * @param[out] error
12806 : : * Pointer to error structure.
12807 : : *
12808 : : * @return
12809 : : * 0 on success, negative value otherwise and rte_errno is set.
12810 : : */
12811 : : static int
12812 : 0 : flow_hw_action_handle_update(struct rte_eth_dev *dev, uint32_t queue,
12813 : : const struct rte_flow_op_attr *attr,
12814 : : struct rte_flow_action_handle *handle,
12815 : : const void *update,
12816 : : void *user_data,
12817 : : struct rte_flow_error *error)
12818 : : {
12819 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12820 : : const struct rte_flow_modify_conntrack *ct_conf =
12821 : : (const struct rte_flow_modify_conntrack *)update;
12822 : : struct mlx5_hw_q_job *job = NULL;
12823 : 0 : uint32_t act_idx = (uint32_t)(uintptr_t)handle;
12824 : 0 : uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
12825 [ # # ]: 0 : uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
12826 : : int ret = 0;
12827 : : bool push = flow_hw_action_push(attr);
12828 : : bool aso = false;
12829 : 0 : bool force_job = type == MLX5_INDIRECT_ACTION_TYPE_METER_MARK;
12830 : :
12831 [ # # ]: 0 : if (attr || force_job) {
12832 : : job = flow_hw_action_job_init(priv, queue, handle, user_data,
12833 : : NULL, MLX5_HW_Q_JOB_TYPE_UPDATE,
12834 : : MLX5_HW_INDIRECT_TYPE_LEGACY, error);
12835 : : if (!job)
12836 : 0 : return -rte_errno;
12837 : : }
12838 [ # # # # : 0 : switch (type) {
# # ]
12839 : 0 : case MLX5_INDIRECT_ACTION_TYPE_AGE:
12840 : 0 : ret = mlx5_hws_age_action_update(priv, idx, update, error);
12841 : 0 : break;
12842 : 0 : case MLX5_INDIRECT_ACTION_TYPE_CT:
12843 [ # # ]: 0 : if (ct_conf->state)
12844 : : aso = true;
12845 : 0 : ret = flow_hw_conntrack_update(dev, queue, update, idx,
12846 : : job, push, error);
12847 : 0 : break;
12848 : 0 : case MLX5_INDIRECT_ACTION_TYPE_METER_MARK:
12849 : : aso = true;
12850 : 0 : ret = mlx5_flow_update_meter_mark(dev, queue, update, idx, push,
12851 : : job, error);
12852 : 0 : break;
12853 : 0 : case MLX5_INDIRECT_ACTION_TYPE_RSS:
12854 : 0 : ret = flow_dv_action_update(dev, handle, update, error);
12855 : 0 : break;
12856 : 0 : case MLX5_INDIRECT_ACTION_TYPE_QUOTA:
12857 : : aso = true;
12858 : 0 : ret = mlx5_quota_query_update(dev, queue, handle, update, NULL,
12859 : : job, push, error);
12860 : 0 : break;
12861 : 0 : default:
12862 : : ret = -ENOTSUP;
12863 : 0 : rte_flow_error_set(error, ENOTSUP,
12864 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12865 : : "action type not supported");
12866 : 0 : break;
12867 : : }
12868 [ # # ]: 0 : if (job && !force_job)
12869 [ # # ]: 0 : flow_hw_action_finalize(dev, queue, job, push, aso, ret == 0);
12870 : : return ret;
12871 : : }
12872 : :
12873 : : /**
12874 : : * Destroy shared action.
12875 : : *
12876 : : * @param[in] dev
12877 : : * Pointer to the rte_eth_dev structure.
12878 : : * @param[in] queue
12879 : : * Which queue to be used.
12880 : : * @param[in] attr
12881 : : * Operation attribute.
12882 : : * @param[in] handle
12883 : : * Action handle to be destroyed.
12884 : : * @param[in] user_data
12885 : : * Pointer to the user_data.
12886 : : * @param[out] error
12887 : : * Pointer to error structure.
12888 : : *
12889 : : * @return
12890 : : * 0 on success, negative value otherwise and rte_errno is set.
12891 : : */
12892 : : static int
12893 : 0 : flow_hw_action_handle_destroy(struct rte_eth_dev *dev, uint32_t queue,
12894 : : const struct rte_flow_op_attr *attr,
12895 : : struct rte_flow_action_handle *handle,
12896 : : void *user_data,
12897 : : struct rte_flow_error *error)
12898 : : {
12899 : 0 : uint32_t act_idx = (uint32_t)(uintptr_t)handle;
12900 : 0 : uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
12901 : 0 : uint32_t age_idx = act_idx & MLX5_HWS_AGE_IDX_MASK;
12902 : : uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
12903 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12904 [ # # ]: 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
12905 : : struct mlx5_hw_q_job *job = NULL;
12906 : : struct mlx5_aso_mtr *aso_mtr;
12907 : : struct mlx5_flow_meter_info *fm;
12908 : : bool push = flow_hw_action_push(attr);
12909 : : bool aso = false;
12910 : : int ret = 0;
12911 : 0 : bool force_job = type == MLX5_INDIRECT_ACTION_TYPE_METER_MARK;
12912 : :
12913 [ # # ]: 0 : if (attr || force_job) {
12914 : : job = flow_hw_action_job_init(priv, queue, handle, user_data,
12915 : : NULL, MLX5_HW_Q_JOB_TYPE_DESTROY,
12916 : : MLX5_HW_INDIRECT_TYPE_LEGACY, error);
12917 : : if (!job)
12918 : 0 : return -rte_errno;
12919 : : }
12920 [ # # # # : 0 : switch (type) {
# # # ]
12921 : 0 : case MLX5_INDIRECT_ACTION_TYPE_AGE:
12922 : 0 : ret = mlx5_hws_age_action_destroy(priv, age_idx, error);
12923 : 0 : break;
12924 : 0 : case MLX5_INDIRECT_ACTION_TYPE_COUNT:
12925 [ # # ]: 0 : age_idx = mlx5_hws_cnt_age_get(priv->hws_cpool, act_idx);
12926 [ # # ]: 0 : if (age_idx != 0)
12927 : : /*
12928 : : * If this counter belongs to indirect AGE, here is the
12929 : : * time to update the AGE.
12930 : : */
12931 : : mlx5_hws_age_nb_cnt_decrease(priv, age_idx);
12932 [ # # ]: 0 : mlx5_hws_cnt_shared_put(priv->hws_cpool, &act_idx);
12933 : : break;
12934 : 0 : case MLX5_INDIRECT_ACTION_TYPE_CT:
12935 : 0 : ret = flow_hw_conntrack_destroy(dev, idx, error);
12936 : 0 : break;
12937 : 0 : case MLX5_INDIRECT_ACTION_TYPE_METER_MARK:
12938 : 0 : aso_mtr = mlx5_ipool_get(pool->idx_pool, idx);
12939 [ # # ]: 0 : if (!aso_mtr) {
12940 : : ret = -EINVAL;
12941 : 0 : rte_flow_error_set(error, EINVAL,
12942 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12943 : : NULL, "Invalid meter_mark destroy index");
12944 : 0 : break;
12945 : : }
12946 : : fm = &aso_mtr->fm;
12947 : 0 : fm->is_enable = 0;
12948 : : /* Update ASO flow meter by wqe. */
12949 [ # # ]: 0 : if (mlx5_aso_meter_update_by_wqe(priv, queue, aso_mtr,
12950 : : &priv->mtr_bulk, job, push)) {
12951 : : ret = -EINVAL;
12952 : 0 : rte_flow_error_set(error, EINVAL,
12953 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12954 : : NULL, "Unable to update ASO meter WQE");
12955 : 0 : break;
12956 : : }
12957 : : /* Wait for ASO object completion. */
12958 [ # # # # ]: 0 : if (queue == MLX5_HW_INV_QUEUE &&
12959 : 0 : mlx5_aso_mtr_wait(priv, aso_mtr, true)) {
12960 : : ret = -EINVAL;
12961 : 0 : rte_flow_error_set(error, EINVAL,
12962 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12963 : : NULL, "Unable to wait for ASO meter CQE");
12964 : 0 : break;
12965 : : }
12966 : : aso = true;
12967 : : break;
12968 : 0 : case MLX5_INDIRECT_ACTION_TYPE_RSS:
12969 : 0 : ret = flow_dv_action_destroy(dev, handle, error);
12970 : 0 : break;
12971 : : case MLX5_INDIRECT_ACTION_TYPE_QUOTA:
12972 : : break;
12973 : 0 : default:
12974 : : ret = -ENOTSUP;
12975 : 0 : rte_flow_error_set(error, ENOTSUP,
12976 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12977 : : "action type not supported");
12978 : 0 : break;
12979 : : }
12980 [ # # ]: 0 : if (job && !force_job)
12981 [ # # ]: 0 : flow_hw_action_finalize(dev, queue, job, push, aso, ret == 0);
12982 : : return ret;
12983 : : }
12984 : :
12985 : : static int
12986 : 0 : flow_hw_query_counter(const struct rte_eth_dev *dev, uint32_t counter,
12987 : : void *data, struct rte_flow_error *error)
12988 : : {
12989 : : struct mlx5_hws_cnt_pool *hpool;
12990 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
12991 : : struct mlx5_hws_cnt *cnt;
12992 : : struct rte_flow_query_count *qc = data;
12993 : : uint32_t iidx;
12994 : : uint64_t pkts, bytes;
12995 : :
12996 [ # # ]: 0 : if (!mlx5_hws_cnt_id_valid(counter))
12997 : 0 : return rte_flow_error_set(error, EINVAL,
12998 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12999 : : "counter are not available");
13000 [ # # ]: 0 : hpool = mlx5_hws_cnt_host_pool(priv->hws_cpool);
13001 : : iidx = mlx5_hws_cnt_iidx(hpool, counter);
13002 : 0 : cnt = &hpool->pool[iidx];
13003 : : __hws_cnt_query_raw(priv->hws_cpool, counter, &pkts, &bytes);
13004 : 0 : qc->hits_set = 1;
13005 : 0 : qc->bytes_set = 1;
13006 : 0 : qc->hits = pkts - cnt->reset.hits;
13007 : 0 : qc->bytes = bytes - cnt->reset.bytes;
13008 [ # # ]: 0 : if (qc->reset) {
13009 : 0 : cnt->reset.bytes = bytes;
13010 : 0 : cnt->reset.hits = pkts;
13011 : : }
13012 : : return 0;
13013 : : }
13014 : :
13015 : : /**
13016 : : * Query a flow rule AGE action for aging information.
13017 : : *
13018 : : * @param[in] dev
13019 : : * Pointer to Ethernet device.
13020 : : * @param[in] age_idx
13021 : : * Index of AGE action parameter.
13022 : : * @param[out] data
13023 : : * Data retrieved by the query.
13024 : : * @param[out] error
13025 : : * Perform verbose error reporting if not NULL.
13026 : : *
13027 : : * @return
13028 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
13029 : : */
13030 : : static int
13031 : 0 : flow_hw_query_age(const struct rte_eth_dev *dev, uint32_t age_idx, void *data,
13032 : : struct rte_flow_error *error)
13033 : : {
13034 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13035 : 0 : struct mlx5_age_info *age_info = GET_PORT_AGE_INFO(priv);
13036 : 0 : struct mlx5_indexed_pool *ipool = age_info->ages_ipool;
13037 : 0 : struct mlx5_hws_age_param *param = mlx5_ipool_get(ipool, age_idx);
13038 : : struct rte_flow_query_age *resp = data;
13039 : :
13040 [ # # # # ]: 0 : if (!param || !param->timeout)
13041 : 0 : return rte_flow_error_set(error, EINVAL,
13042 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13043 : : NULL, "age data not available");
13044 [ # # # ]: 0 : switch (rte_atomic_load_explicit(¶m->state, rte_memory_order_relaxed)) {
13045 : 0 : case HWS_AGE_AGED_OUT_REPORTED:
13046 : : case HWS_AGE_AGED_OUT_NOT_REPORTED:
13047 : 0 : resp->aged = 1;
13048 : 0 : break;
13049 : 0 : case HWS_AGE_CANDIDATE:
13050 : : case HWS_AGE_CANDIDATE_INSIDE_RING:
13051 : 0 : resp->aged = 0;
13052 : 0 : break;
13053 : : case HWS_AGE_FREE:
13054 : : /*
13055 : : * When state is FREE the flow itself should be invalid.
13056 : : * Fall-through.
13057 : : */
13058 : : default:
13059 : : MLX5_ASSERT(0);
13060 : : break;
13061 : : }
13062 : 0 : resp->sec_since_last_hit_valid = !resp->aged;
13063 [ # # ]: 0 : if (resp->sec_since_last_hit_valid)
13064 : 0 : resp->sec_since_last_hit = rte_atomic_load_explicit
13065 : : (¶m->sec_since_last_hit, rte_memory_order_relaxed);
13066 : : return 0;
13067 : : }
13068 : :
13069 : : static int
13070 : 0 : flow_hw_query(struct rte_eth_dev *dev, struct rte_flow *flow,
13071 : : const struct rte_flow_action *actions, void *data,
13072 : : struct rte_flow_error *error)
13073 : : {
13074 : : int ret = -EINVAL;
13075 : : struct rte_flow_hw *hw_flow = (struct rte_flow_hw *)flow;
13076 : : struct rte_flow_hw_aux *aux;
13077 : :
13078 [ # # ]: 0 : for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
13079 [ # # # # ]: 0 : switch (actions->type) {
13080 : : case RTE_FLOW_ACTION_TYPE_VOID:
13081 : : break;
13082 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
13083 [ # # ]: 0 : if (!(hw_flow->flags & MLX5_FLOW_HW_FLOW_FLAG_CNT_ID))
13084 : 0 : return rte_flow_error_set(error, EINVAL,
13085 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13086 : : "counter not defined in the rule");
13087 : 0 : ret = flow_hw_query_counter(dev, hw_flow->cnt_id, data,
13088 : : error);
13089 : 0 : break;
13090 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
13091 [ # # ]: 0 : if (!(hw_flow->flags & MLX5_FLOW_HW_FLOW_FLAG_AGE_IDX))
13092 : 0 : return rte_flow_error_set(error, EINVAL,
13093 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13094 : : "age data not available");
13095 : 0 : aux = mlx5_flow_hw_aux(dev->data->port_id, hw_flow);
13096 : 0 : ret = flow_hw_query_age(dev, mlx5_flow_hw_aux_get_age_idx(hw_flow, aux),
13097 : : data, error);
13098 : 0 : break;
13099 : 0 : default:
13100 : 0 : return rte_flow_error_set(error, ENOTSUP,
13101 : : RTE_FLOW_ERROR_TYPE_ACTION,
13102 : : actions,
13103 : : "action not supported");
13104 : : }
13105 : : }
13106 : : return ret;
13107 : : }
13108 : :
13109 : : /**
13110 : : * Validate indirect action.
13111 : : *
13112 : : * @param[in] dev
13113 : : * Pointer to the Ethernet device structure.
13114 : : * @param[in] conf
13115 : : * Shared action configuration.
13116 : : * @param[in] action
13117 : : * Action specification used to create indirect action.
13118 : : * @param[out] error
13119 : : * Perform verbose error reporting if not NULL. Initialized in case of
13120 : : * error only.
13121 : : *
13122 : : * @return
13123 : : * 0 on success, otherwise negative errno value.
13124 : : */
13125 : : static int
13126 : 0 : flow_hw_action_validate(struct rte_eth_dev *dev,
13127 : : const struct rte_flow_indir_action_conf *conf,
13128 : : const struct rte_flow_action *action,
13129 : : struct rte_flow_error *err)
13130 : : {
13131 : 0 : struct rte_flow_error shadow_error = {0, };
13132 : :
13133 [ # # ]: 0 : if (!err)
13134 : : err = &shadow_error;
13135 : 0 : return flow_hw_action_handle_validate(dev, MLX5_HW_INV_QUEUE, NULL,
13136 : : conf, action, NULL, err);
13137 : : }
13138 : :
13139 : : /**
13140 : : * Create indirect action.
13141 : : *
13142 : : * @param[in] dev
13143 : : * Pointer to the Ethernet device structure.
13144 : : * @param[in] conf
13145 : : * Shared action configuration.
13146 : : * @param[in] action
13147 : : * Action specification used to create indirect action.
13148 : : * @param[out] error
13149 : : * Perform verbose error reporting if not NULL. Initialized in case of
13150 : : * error only.
13151 : : *
13152 : : * @return
13153 : : * A valid shared action handle in case of success, NULL otherwise and
13154 : : * rte_errno is set.
13155 : : */
13156 : : static struct rte_flow_action_handle *
13157 : 0 : flow_hw_action_create(struct rte_eth_dev *dev,
13158 : : const struct rte_flow_indir_action_conf *conf,
13159 : : const struct rte_flow_action *action,
13160 : : struct rte_flow_error *err)
13161 : : {
13162 : 0 : return flow_hw_action_handle_create(dev, MLX5_HW_INV_QUEUE,
13163 : : NULL, conf, action, NULL, err);
13164 : : }
13165 : :
13166 : : /**
13167 : : * Destroy the indirect action.
13168 : : * Release action related resources on the NIC and the memory.
13169 : : * Lock free, (mutex should be acquired by caller).
13170 : : * Dispatcher for action type specific call.
13171 : : *
13172 : : * @param[in] dev
13173 : : * Pointer to the Ethernet device structure.
13174 : : * @param[in] handle
13175 : : * The indirect action object handle to be removed.
13176 : : * @param[out] error
13177 : : * Perform verbose error reporting if not NULL. Initialized in case of
13178 : : * error only.
13179 : : *
13180 : : * @return
13181 : : * 0 on success, otherwise negative errno value.
13182 : : */
13183 : : static int
13184 : 0 : flow_hw_action_destroy(struct rte_eth_dev *dev,
13185 : : struct rte_flow_action_handle *handle,
13186 : : struct rte_flow_error *error)
13187 : : {
13188 : 0 : return flow_hw_action_handle_destroy(dev, MLX5_HW_INV_QUEUE,
13189 : : NULL, handle, NULL, error);
13190 : : }
13191 : :
13192 : : /**
13193 : : * Updates in place shared action configuration.
13194 : : *
13195 : : * @param[in] dev
13196 : : * Pointer to the Ethernet device structure.
13197 : : * @param[in] handle
13198 : : * The indirect action object handle to be updated.
13199 : : * @param[in] update
13200 : : * Action specification used to modify the action pointed by *handle*.
13201 : : * *update* could be of same type with the action pointed by the *handle*
13202 : : * handle argument, or some other structures like a wrapper, depending on
13203 : : * the indirect action type.
13204 : : * @param[out] error
13205 : : * Perform verbose error reporting if not NULL. Initialized in case of
13206 : : * error only.
13207 : : *
13208 : : * @return
13209 : : * 0 on success, otherwise negative errno value.
13210 : : */
13211 : : static int
13212 : 0 : flow_hw_action_update(struct rte_eth_dev *dev,
13213 : : struct rte_flow_action_handle *handle,
13214 : : const void *update,
13215 : : struct rte_flow_error *err)
13216 : : {
13217 : 0 : return flow_hw_action_handle_update(dev, MLX5_HW_INV_QUEUE,
13218 : : NULL, handle, update, NULL, err);
13219 : : }
13220 : :
13221 : : static int
13222 : 0 : flow_hw_action_handle_query(struct rte_eth_dev *dev, uint32_t queue,
13223 : : const struct rte_flow_op_attr *attr,
13224 : : const struct rte_flow_action_handle *handle,
13225 : : void *data, void *user_data,
13226 : : struct rte_flow_error *error)
13227 : : {
13228 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13229 : : struct mlx5_hw_q_job *job = NULL;
13230 : 0 : uint32_t act_idx = (uint32_t)(uintptr_t)handle;
13231 : 0 : uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
13232 [ # # ]: 0 : uint32_t idx = MLX5_INDIRECT_ACTION_IDX_GET(handle);
13233 : : uint32_t age_idx = act_idx & MLX5_HWS_AGE_IDX_MASK;
13234 : : int ret;
13235 : : bool push = flow_hw_action_push(attr);
13236 : : bool aso = false;
13237 : :
13238 [ # # ]: 0 : if (attr) {
13239 : : job = flow_hw_action_job_init(priv, queue, handle, user_data,
13240 : : data, MLX5_HW_Q_JOB_TYPE_QUERY,
13241 : : MLX5_HW_INDIRECT_TYPE_LEGACY, error);
13242 : : if (!job)
13243 : 0 : return -rte_errno;
13244 : : }
13245 [ # # # # : 0 : switch (type) {
# ]
13246 : 0 : case MLX5_INDIRECT_ACTION_TYPE_AGE:
13247 : 0 : ret = flow_hw_query_age(dev, age_idx, data, error);
13248 : 0 : break;
13249 : 0 : case MLX5_INDIRECT_ACTION_TYPE_COUNT:
13250 : 0 : ret = flow_hw_query_counter(dev, act_idx, data, error);
13251 : 0 : break;
13252 : 0 : case MLX5_INDIRECT_ACTION_TYPE_CT:
13253 : : aso = true;
13254 [ # # ]: 0 : if (job)
13255 : 0 : job->query.user = data;
13256 : 0 : ret = flow_hw_conntrack_query(dev, queue, idx, data,
13257 : : job, push, error);
13258 : 0 : break;
13259 : 0 : case MLX5_INDIRECT_ACTION_TYPE_QUOTA:
13260 : : aso = true;
13261 : 0 : ret = mlx5_quota_query(dev, queue, handle, data,
13262 : : job, push, error);
13263 : 0 : break;
13264 : 0 : default:
13265 : : ret = -ENOTSUP;
13266 : 0 : rte_flow_error_set(error, ENOTSUP,
13267 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13268 : : "action type not supported");
13269 : 0 : break;
13270 : : }
13271 [ # # ]: 0 : if (job)
13272 [ # # ]: 0 : flow_hw_action_finalize(dev, queue, job, push, aso, ret == 0);
13273 : : return ret;
13274 : : }
13275 : :
13276 : : static int
13277 : 0 : flow_hw_async_action_handle_query_update
13278 : : (struct rte_eth_dev *dev, uint32_t queue,
13279 : : const struct rte_flow_op_attr *attr,
13280 : : struct rte_flow_action_handle *handle,
13281 : : const void *update, void *query,
13282 : : enum rte_flow_query_update_mode qu_mode,
13283 : : void *user_data, struct rte_flow_error *error)
13284 : : {
13285 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
13286 : : bool push = flow_hw_action_push(attr);
13287 : : bool aso = false;
13288 : : struct mlx5_hw_q_job *job = NULL;
13289 : : int ret = 0;
13290 : :
13291 [ # # ]: 0 : if (attr) {
13292 : : job = flow_hw_action_job_init(priv, queue, handle, user_data,
13293 : : query,
13294 : : MLX5_HW_Q_JOB_TYPE_UPDATE_QUERY,
13295 : : MLX5_HW_INDIRECT_TYPE_LEGACY, error);
13296 : : if (!job)
13297 : 0 : return -rte_errno;
13298 : : }
13299 [ # # ]: 0 : switch (MLX5_INDIRECT_ACTION_TYPE_GET(handle)) {
13300 : 0 : case MLX5_INDIRECT_ACTION_TYPE_QUOTA:
13301 [ # # ]: 0 : if (qu_mode != RTE_FLOW_QU_QUERY_FIRST) {
13302 : 0 : ret = rte_flow_error_set
13303 : : (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION_CONF,
13304 : : NULL, "quota action must query before update");
13305 : 0 : break;
13306 : : }
13307 : : aso = true;
13308 : 0 : ret = mlx5_quota_query_update(dev, queue, handle,
13309 : : update, query, job, push, error);
13310 : 0 : break;
13311 : 0 : default:
13312 : 0 : ret = rte_flow_error_set(error, ENOTSUP,
13313 : : RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, "update and query not supportred");
13314 : : }
13315 [ # # ]: 0 : if (job)
13316 [ # # ]: 0 : flow_hw_action_finalize(dev, queue, job, push, aso, ret == 0);
13317 : : return ret;
13318 : : }
13319 : :
13320 : : static int
13321 : 0 : flow_hw_action_query(struct rte_eth_dev *dev,
13322 : : const struct rte_flow_action_handle *handle, void *data,
13323 : : struct rte_flow_error *error)
13324 : : {
13325 : 0 : return flow_hw_action_handle_query(dev, MLX5_HW_INV_QUEUE, NULL,
13326 : : handle, data, NULL, error);
13327 : : }
13328 : :
13329 : : static int
13330 : 0 : flow_hw_action_query_update(struct rte_eth_dev *dev,
13331 : : struct rte_flow_action_handle *handle,
13332 : : const void *update, void *query,
13333 : : enum rte_flow_query_update_mode qu_mode,
13334 : : struct rte_flow_error *error)
13335 : : {
13336 : 0 : return flow_hw_async_action_handle_query_update(dev, MLX5_HW_INV_QUEUE,
13337 : : NULL, handle, update,
13338 : : query, qu_mode, NULL,
13339 : : error);
13340 : : }
13341 : :
13342 : : /**
13343 : : * Get aged-out flows of a given port on the given HWS flow queue.
13344 : : *
13345 : : * @param[in] dev
13346 : : * Pointer to the Ethernet device structure.
13347 : : * @param[in] queue_id
13348 : : * Flow queue to query. Ignored when RTE_FLOW_PORT_FLAG_STRICT_QUEUE not set.
13349 : : * @param[in, out] contexts
13350 : : * The address of an array of pointers to the aged-out flows contexts.
13351 : : * @param[in] nb_contexts
13352 : : * The length of context array pointers.
13353 : : * @param[out] error
13354 : : * Perform verbose error reporting if not NULL. Initialized in case of
13355 : : * error only.
13356 : : *
13357 : : * @return
13358 : : * if nb_contexts is 0, return the amount of all aged contexts.
13359 : : * if nb_contexts is not 0 , return the amount of aged flows reported
13360 : : * in the context array, otherwise negative errno value.
13361 : : */
13362 : : static int
13363 : 0 : flow_hw_get_q_aged_flows(struct rte_eth_dev *dev, uint32_t queue_id,
13364 : : void **contexts, uint32_t nb_contexts,
13365 : : struct rte_flow_error *error)
13366 : : {
13367 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13368 : 0 : struct mlx5_age_info *age_info = GET_PORT_AGE_INFO(priv);
13369 : : struct rte_ring *r;
13370 : : int nb_flows = 0;
13371 : :
13372 [ # # ]: 0 : if (nb_contexts && !contexts)
13373 : 0 : return rte_flow_error_set(error, EINVAL,
13374 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13375 : : NULL, "empty context");
13376 [ # # ]: 0 : if (!priv->hws_age_req)
13377 : 0 : return rte_flow_error_set(error, ENOENT,
13378 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13379 : : NULL, "No aging initialized");
13380 [ # # ]: 0 : if (priv->hws_strict_queue) {
13381 [ # # ]: 0 : if (queue_id >= age_info->hw_q_age->nb_rings)
13382 : 0 : return rte_flow_error_set(error, EINVAL,
13383 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13384 : : NULL, "invalid queue id");
13385 : 0 : r = age_info->hw_q_age->aged_lists[queue_id];
13386 : : } else {
13387 : 0 : r = age_info->hw_age.aged_list;
13388 : 0 : MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
13389 : : }
13390 [ # # ]: 0 : if (nb_contexts == 0)
13391 : 0 : return rte_ring_count(r);
13392 [ # # ]: 0 : while ((uint32_t)nb_flows < nb_contexts) {
13393 : : uint32_t age_idx;
13394 : :
13395 : : if (rte_ring_dequeue_elem(r, &age_idx, sizeof(uint32_t)) < 0)
13396 : : break;
13397 : : /* get the AGE context if the aged-out index is still valid. */
13398 : 0 : contexts[nb_flows] = mlx5_hws_age_context_get(priv, age_idx);
13399 [ # # ]: 0 : if (!contexts[nb_flows])
13400 : 0 : continue;
13401 : 0 : nb_flows++;
13402 : : }
13403 : : return nb_flows;
13404 : : }
13405 : :
13406 : : /**
13407 : : * Get aged-out flows.
13408 : : *
13409 : : * This function is relevant only if RTE_FLOW_PORT_FLAG_STRICT_QUEUE isn't set.
13410 : : *
13411 : : * @param[in] dev
13412 : : * Pointer to the Ethernet device structure.
13413 : : * @param[in] contexts
13414 : : * The address of an array of pointers to the aged-out flows contexts.
13415 : : * @param[in] nb_contexts
13416 : : * The length of context array pointers.
13417 : : * @param[out] error
13418 : : * Perform verbose error reporting if not NULL. Initialized in case of
13419 : : * error only.
13420 : : *
13421 : : * @return
13422 : : * how many contexts get in success, otherwise negative errno value.
13423 : : * if nb_contexts is 0, return the amount of all aged contexts.
13424 : : * if nb_contexts is not 0 , return the amount of aged flows reported
13425 : : * in the context array.
13426 : : */
13427 : : static int
13428 : 0 : flow_hw_get_aged_flows(struct rte_eth_dev *dev, void **contexts,
13429 : : uint32_t nb_contexts, struct rte_flow_error *error)
13430 : : {
13431 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13432 : :
13433 [ # # ]: 0 : if (priv->hws_strict_queue)
13434 : 0 : DRV_LOG(WARNING,
13435 : : "port %u get aged flows called in strict queue mode.",
13436 : : dev->data->port_id);
13437 : 0 : return flow_hw_get_q_aged_flows(dev, 0, contexts, nb_contexts, error);
13438 : : }
13439 : : /**
13440 : : * Initialization function for non template API which calls
13441 : : * flow_hw_configure with default values.
13442 : : * Configure non queues cause 1 queue is configured by default for inner usage.
13443 : : *
13444 : : * @param[in] dev
13445 : : * Pointer to the Ethernet device structure.
13446 : : * @param[out] error
13447 : : * Pointer to the error structure.
13448 : : *
13449 : : * @return
13450 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
13451 : : */
13452 : : int
13453 : 0 : flow_hw_init(struct rte_eth_dev *dev,
13454 : : struct rte_flow_error *error)
13455 : : {
13456 : 0 : const struct rte_flow_port_attr port_attr = {0};
13457 : 0 : const struct rte_flow_queue_attr queue_attr = {.size = MLX5_NT_DEFAULT_QUEUE_SIZE};
13458 : 0 : const struct rte_flow_queue_attr *attr_list = &queue_attr;
13459 : :
13460 : : /**
13461 : : * If user uses template and non template API:
13462 : : * User will call flow_hw_configure and non template
13463 : : * API will use the allocated actions.
13464 : : * Init function will not call flow_hw_configure.
13465 : : *
13466 : : * If user uses only non template API's:
13467 : : * Init function will call flow_hw_configure.
13468 : : * It will not allocate memory for actions.
13469 : : * When needed allocation, it will handle same as for SWS today,
13470 : : * meaning using bulk allocations and resize as needed.
13471 : : */
13472 : : /* Configure hws with default values. */
13473 : 0 : DRV_LOG(DEBUG, "Apply default configuration, zero number of queues, inner control queue size is %u",
13474 : : MLX5_NT_DEFAULT_QUEUE_SIZE);
13475 : 0 : return __flow_hw_configure(dev, &port_attr, 0, &attr_list, true, error);
13476 : : }
13477 : :
13478 : 0 : static int flow_hw_prepare(struct rte_eth_dev *dev,
13479 : : const struct rte_flow_action actions[] __rte_unused,
13480 : : enum mlx5_flow_type type,
13481 : : struct rte_flow_hw **flow,
13482 : : struct rte_flow_error *error)
13483 : : {
13484 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13485 : 0 : uint32_t idx = 0;
13486 : :
13487 : : /*
13488 : : * Notice pool idx size = (sizeof(struct rte_flow_hw)
13489 : : * + sizeof(struct rte_flow_nt2hws)) for HWS mode.
13490 : : */
13491 : 0 : *flow = mlx5_ipool_zmalloc(priv->flows[type], &idx);
13492 [ # # ]: 0 : if (!(*flow))
13493 : 0 : return rte_flow_error_set(error, ENOMEM,
13494 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13495 : : "cannot allocate flow memory");
13496 : : /* Allocating 2 structures in one pool slot, updating nt2hw pointer.*/
13497 : 0 : (*flow)->nt2hws = (struct rte_flow_nt2hws *)
13498 : 0 : ((uintptr_t)(*flow) + sizeof(struct rte_flow_hw));
13499 : 0 : (*flow)->idx = idx;
13500 : 0 : (*flow)->nt2hws->flow_aux = mlx5_malloc(MLX5_MEM_ZERO, sizeof(struct rte_flow_hw_aux),
13501 : 0 : RTE_CACHE_LINE_SIZE, rte_dev_numa_node(dev->device));
13502 [ # # ]: 0 : if (!(*flow)->nt2hws->flow_aux)
13503 : 0 : return rte_flow_error_set(error, ENOMEM,
13504 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13505 : : "cannot allocate flow aux memory");
13506 : : return 0;
13507 : : }
13508 : :
13509 : : static inline void
13510 : 0 : flow_hw_set_dv_fields(struct rte_flow_template_table_attr *table_attr, uint32_t fdb_unified_en,
13511 : : bool *root, uint8_t *ft_type, uint64_t *flags)
13512 : : {
13513 [ # # ]: 0 : if (table_attr->flow_attr.transfer)
13514 : 0 : *ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
13515 : : else
13516 : 0 : *ft_type = table_attr->flow_attr.egress ?
13517 : 0 : MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
13518 : : MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
13519 : 0 : uint32_t group = table_attr->flow_attr.group;
13520 : 0 : *root = group ? 0 : 1;
13521 : 0 : *flags = mlx5_hw_act_flag[!!group][get_mlx5dr_table_type(&table_attr->flow_attr,
13522 : : table_attr->specialize,
13523 : : fdb_unified_en)];
13524 : 0 : }
13525 : :
13526 : : static int
13527 : 0 : flow_hw_modify_hdr_resource_register
13528 : : (struct rte_eth_dev *dev,
13529 : : struct rte_flow_template_table *table,
13530 : : struct mlx5_hw_actions *hw_acts,
13531 : : struct rte_flow_hw *dev_flow,
13532 : : struct rte_flow_error *error)
13533 : : {
13534 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
13535 : : bool unified_fdb = is_unified_fdb(priv);
13536 : 0 : struct rte_flow_template_table_attr *table_attr = &table->cfg.attr;
13537 : 0 : struct mlx5_flow_dv_modify_hdr_resource *dv_resource_ptr = NULL;
13538 : : union {
13539 : : struct mlx5_flow_dv_modify_hdr_resource dv_resource;
13540 : : uint8_t data[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
13541 : : sizeof(struct mlx5_modification_cmd) * MLX5_MHDR_MAX_CMD];
13542 : : } dummy;
13543 : : int ret;
13544 : :
13545 [ # # ]: 0 : if (hw_acts->mhdr) {
13546 : 0 : dummy.dv_resource.actions_num = hw_acts->mhdr->mhdr_cmds_num;
13547 : 0 : memcpy(dummy.dv_resource.actions, hw_acts->mhdr->mhdr_cmds,
13548 : 0 : sizeof(struct mlx5_modification_cmd) * dummy.dv_resource.actions_num);
13549 : : } else {
13550 : : return 0;
13551 : : }
13552 : 0 : flow_hw_set_dv_fields(table_attr, unified_fdb,
13553 : : &dummy.dv_resource.root, &dummy.dv_resource.ft_type,
13554 : : &dummy.dv_resource.flags);
13555 : 0 : dummy.dv_resource.flags |= MLX5DR_ACTION_FLAG_SHARED;
13556 : 0 : ret = __flow_modify_hdr_resource_register(dev, &dummy.dv_resource,
13557 : : &dv_resource_ptr, error);
13558 [ # # ]: 0 : if (ret)
13559 : : return ret;
13560 : : MLX5_ASSERT(dv_resource_ptr);
13561 : 0 : dev_flow->nt2hws->modify_hdr = dv_resource_ptr;
13562 : : /* keep action for the rule construction. */
13563 : 0 : hw_acts->rule_acts[hw_acts->mhdr->pos].action = dv_resource_ptr->action;
13564 : : /* Bulk size is 1, so index is 1. */
13565 : 0 : dev_flow->res_idx = 1;
13566 : 0 : return 0;
13567 : : }
13568 : :
13569 : : static int
13570 : 0 : flow_hw_encap_decap_resource_register
13571 : : (struct rte_eth_dev *dev,
13572 : : struct rte_flow_template_table *table,
13573 : : struct mlx5_hw_actions *hw_acts,
13574 : : struct rte_flow_hw *dev_flow,
13575 : : struct rte_flow_error *error)
13576 : : {
13577 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
13578 : : bool unified_fdb = is_unified_fdb(priv);
13579 : 0 : struct rte_flow_template_table_attr *table_attr = &table->cfg.attr;
13580 : 0 : struct mlx5_flow_dv_encap_decap_resource *dv_resource_ptr = NULL;
13581 : : struct mlx5_flow_dv_encap_decap_resource dv_resource;
13582 : : struct mlx5_tbl_multi_pattern_ctx *mpctx = &table->mpctx;
13583 : : int ret;
13584 : : bool is_root;
13585 : : int ix;
13586 : :
13587 [ # # ]: 0 : if (hw_acts->encap_decap)
13588 : 0 : dv_resource.reformat_type = hw_acts->encap_decap->action_type;
13589 : : else
13590 : : return 0;
13591 : 0 : flow_hw_set_dv_fields(table_attr, unified_fdb, &is_root, &dv_resource.ft_type,
13592 : : &dv_resource.flags);
13593 [ # # ]: 0 : ix = mlx5_bwc_multi_pattern_reformat_to_index((enum mlx5dr_action_type)
13594 : : dv_resource.reformat_type);
13595 : : if (ix < 0)
13596 : 0 : return ix;
13597 [ # # ]: 0 : if (hw_acts->encap_decap->shared) {
13598 : 0 : dv_resource.size = hw_acts->encap_decap->data_size;
13599 : : MLX5_ASSERT(dv_resource.size <= MLX5_ENCAP_MAX_LEN);
13600 : 0 : memcpy(&dv_resource.buf, hw_acts->encap_decap->data, dv_resource.size);
13601 : 0 : dv_resource.flags |= MLX5DR_ACTION_FLAG_SHARED;
13602 : : } else {
13603 : 0 : typeof(mpctx->reformat[0]) *reformat = mpctx->reformat + ix;
13604 [ # # ]: 0 : if (!reformat->elements_num)
13605 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
13606 : : NULL, "No reformat action exist in the table.");
13607 : 0 : dv_resource.size = reformat->reformat_hdr->sz;
13608 : : MLX5_ASSERT(dv_resource.size <= MLX5_ENCAP_MAX_LEN);
13609 : 0 : memcpy(&dv_resource.buf, reformat->reformat_hdr->data, dv_resource.size);
13610 : : }
13611 : 0 : ret = __flow_encap_decap_resource_register(dev, &dv_resource, is_root,
13612 : : &dv_resource_ptr, error);
13613 [ # # ]: 0 : if (ret)
13614 : : return ret;
13615 : : MLX5_ASSERT(dv_resource_ptr);
13616 : 0 : dev_flow->nt2hws->rix_encap_decap = dv_resource_ptr->idx;
13617 : : /* keep action for the rule construction. */
13618 [ # # ]: 0 : if (hw_acts->encap_decap->shared)
13619 : 0 : hw_acts->rule_acts[hw_acts->encap_decap_pos].action = dv_resource_ptr->action;
13620 : : else
13621 : 0 : mpctx->segments[0].reformat_action[ix] = dv_resource_ptr->action;
13622 : : /* Bulk size is 1, so index is 1. */
13623 : 0 : dev_flow->res_idx = 1;
13624 : 0 : return 0;
13625 : : }
13626 : :
13627 : : static enum rte_flow_action_type
13628 : : flow_nta_get_indirect_action_type(const struct rte_flow_action *action)
13629 : : {
13630 [ # # ]: 0 : switch (MLX5_INDIRECT_ACTION_TYPE_GET(action->conf)) {
13631 : : case MLX5_INDIRECT_ACTION_TYPE_RSS:
13632 : : return RTE_FLOW_ACTION_TYPE_RSS;
13633 : : case MLX5_INDIRECT_ACTION_TYPE_AGE:
13634 : : return RTE_FLOW_ACTION_TYPE_AGE;
13635 : : case MLX5_INDIRECT_ACTION_TYPE_COUNT:
13636 : : return RTE_FLOW_ACTION_TYPE_COUNT;
13637 : : case MLX5_INDIRECT_ACTION_TYPE_CT:
13638 : : return RTE_FLOW_ACTION_TYPE_CONNTRACK;
13639 : : default:
13640 : : break;
13641 : : }
13642 : : return RTE_FLOW_ACTION_TYPE_END;
13643 : : }
13644 : :
13645 : : static void
13646 : : flow_nta_set_mh_mask_conf(const struct rte_flow_action_modify_field *action_conf,
13647 : : struct rte_flow_action_modify_field *mask_conf)
13648 : : {
13649 : : memset(mask_conf, 0xff, sizeof(*mask_conf));
13650 : 0 : mask_conf->operation = action_conf->operation;
13651 : 0 : mask_conf->dst.field = action_conf->dst.field;
13652 : 0 : mask_conf->src.field = action_conf->src.field;
13653 : : }
13654 : :
13655 : : union actions_conf {
13656 : : struct rte_flow_action_modify_field modify_field;
13657 : : struct rte_flow_action_raw_encap raw_encap;
13658 : : struct rte_flow_action_vxlan_encap vxlan_encap;
13659 : : struct rte_flow_action_nvgre_encap nvgre_encap;
13660 : : };
13661 : :
13662 : : static int
13663 : 0 : flow_nta_build_template_mask(const struct rte_flow_action actions[],
13664 : : struct rte_flow_action masks[MLX5_HW_MAX_ACTS],
13665 : : union actions_conf mask_conf[MLX5_HW_MAX_ACTS])
13666 : : {
13667 : : int i;
13668 : :
13669 [ # # # # ]: 0 : for (i = 0; i == 0 || actions[i - 1].type != RTE_FLOW_ACTION_TYPE_END; i++) {
13670 : 0 : const struct rte_flow_action *action = &actions[i];
13671 : 0 : struct rte_flow_action *mask = &masks[i];
13672 : 0 : union actions_conf *conf = &mask_conf[i];
13673 : :
13674 : 0 : mask->type = action->type;
13675 [ # # # # : 0 : switch (action->type) {
# # # ]
13676 : : case RTE_FLOW_ACTION_TYPE_INDIRECT:
13677 : 0 : mask->type = flow_nta_get_indirect_action_type(action);
13678 [ # # ]: 0 : if (!mask->type)
13679 : : return -EINVAL;
13680 : : break;
13681 : 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
13682 : 0 : flow_nta_set_mh_mask_conf(action->conf, (void *)conf);
13683 : 0 : mask->conf = conf;
13684 : 0 : break;
13685 : : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
13686 : : /* This mask will set this action as shared. */
13687 : : memset(conf, 0xff, sizeof(struct rte_flow_action_raw_encap));
13688 : 0 : mask->conf = conf;
13689 : 0 : break;
13690 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
13691 : : /* This mask will set this action as shared. */
13692 : 0 : conf->vxlan_encap.definition =
13693 : : ((const struct rte_flow_action_vxlan_encap *)
13694 : 0 : action->conf)->definition;
13695 : 0 : mask->conf = conf;
13696 : 0 : break;
13697 : 0 : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
13698 : : /* This mask will set this action as shared. */
13699 : 0 : conf->nvgre_encap.definition =
13700 : : ((const struct rte_flow_action_nvgre_encap *)
13701 : 0 : action->conf)->definition;
13702 : 0 : mask->conf = conf;
13703 : 0 : break;
13704 : : case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
13705 : : memset(conf, 0xff, sizeof(struct rte_flow_action_of_set_vlan_vid));
13706 : 0 : mask->conf = conf;
13707 : 0 : break;
13708 : : default:
13709 : : break;
13710 : : }
13711 : : }
13712 : : return 0;
13713 : : #undef NTA_CHECK_CONF_BUF_SIZE
13714 : : }
13715 : :
13716 : : static int
13717 : 0 : flow_hw_translate_flow_actions(struct rte_eth_dev *dev,
13718 : : const struct rte_flow_attr *attr,
13719 : : const struct rte_flow_action actions[],
13720 : : struct rte_flow_hw *flow,
13721 : : struct mlx5_flow_hw_action_params *ap,
13722 : : struct mlx5_hw_actions *hw_acts,
13723 : : uint64_t item_flags, uint64_t action_flags,
13724 : : bool external,
13725 : : struct rte_flow_error *error)
13726 : : {
13727 : : int ret = 0;
13728 : 0 : uint32_t src_group = 0;
13729 : : enum mlx5dr_table_type table_type;
13730 : : struct mlx5_flow_group grp;
13731 : : struct rte_flow_actions_template *at = NULL;
13732 : 0 : struct rte_flow_actions_template_attr template_attr = {
13733 : 0 : .egress = attr->egress,
13734 : 0 : .ingress = attr->ingress,
13735 : 0 : .transfer = attr->transfer,
13736 : : };
13737 : : struct rte_flow_action masks[MLX5_HW_MAX_ACTS];
13738 : : union actions_conf mask_conf[MLX5_HW_MAX_ACTS];
13739 : :
13740 : : RTE_SET_USED(action_flags);
13741 : : memset(masks, 0, sizeof(masks));
13742 : : memset(mask_conf, 0, sizeof(mask_conf));
13743 : : /* Only set the needed fields explicitly. */
13744 : 0 : struct mlx5_flow_workspace *wks = mlx5_flow_push_thread_workspace();
13745 : : struct rte_flow_template_table *table;
13746 : :
13747 : : /*
13748 : : * Notice All direct actions will be unmasked,
13749 : : * except for modify header and encap,
13750 : : * and therefore will be parsed as part of action construct.
13751 : : * Modify header is always shared in HWS,
13752 : : * encap is masked such that it will be treated as shared.
13753 : : * shared actions will be parsed as part of template translation
13754 : : * and not during action construct.
13755 : : */
13756 [ # # ]: 0 : if (!wks)
13757 : 0 : return rte_flow_error_set(error, ENOMEM,
13758 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13759 : : NULL,
13760 : : "failed to push flow workspace");
13761 : 0 : table = wks->table;
13762 : 0 : flow_nta_build_template_mask(actions, masks, mask_conf);
13763 : : /* The group in the attribute translation was done in advance. */
13764 : 0 : ret = __translate_group(dev, attr, external, attr->group, &src_group, error);
13765 [ # # ]: 0 : if (ret)
13766 : : return ret;
13767 [ # # ]: 0 : if (attr->transfer)
13768 : : table_type = MLX5DR_TABLE_TYPE_FDB;
13769 [ # # ]: 0 : else if (attr->egress)
13770 : : table_type = MLX5DR_TABLE_TYPE_NIC_TX;
13771 : : else
13772 : : table_type = MLX5DR_TABLE_TYPE_NIC_RX;
13773 : 0 : at = __flow_hw_actions_template_create(dev, &template_attr, actions, masks, true, error);
13774 [ # # ]: 0 : if (!at) {
13775 : 0 : ret = -rte_errno;
13776 : 0 : goto end;
13777 : : }
13778 : 0 : grp.group_id = src_group;
13779 : 0 : table->grp = &grp;
13780 : 0 : table->type = table_type;
13781 : 0 : table->cfg.external = external;
13782 : 0 : table->nb_action_templates = 1;
13783 : 0 : memcpy(&table->cfg.attr.flow_attr, attr, sizeof(*attr));
13784 : 0 : table->cfg.attr.flow_attr.group = src_group;
13785 : 0 : table->ats[0].action_template = at;
13786 : 0 : ret = __flow_hw_translate_actions_template(dev, &table->cfg, hw_acts, at,
13787 : : &table->mpctx, true, error);
13788 [ # # ]: 0 : if (ret)
13789 : 0 : goto end;
13790 : : /* handle bulk actions register. */
13791 : 0 : ret = flow_hw_encap_decap_resource_register(dev, table, hw_acts, flow, error);
13792 [ # # ]: 0 : if (ret)
13793 : 0 : goto end;
13794 : 0 : ret = flow_hw_modify_hdr_resource_register(dev, table, hw_acts, flow, error);
13795 [ # # ]: 0 : if (ret)
13796 : 0 : goto end;
13797 : 0 : table->ats[0].acts = *hw_acts;
13798 : 0 : ret = flow_hw_actions_construct(dev, flow, ap,
13799 : : &table->ats[0], item_flags, table,
13800 [ # # ]: 0 : actions, hw_acts->rule_acts, 0, error);
13801 [ # # ]: 0 : if (ret)
13802 : 0 : goto end;
13803 : 0 : goto end;
13804 : 0 : end:
13805 [ # # ]: 0 : if (ret)
13806 : : /* Make sure that there is no garbage in the actions. */
13807 : 0 : __flow_hw_action_template_destroy(dev, hw_acts);
13808 : : else
13809 : 0 : __flow_hw_act_data_flush(dev, hw_acts);
13810 [ # # ]: 0 : if (at)
13811 : 0 : mlx5_free(at);
13812 : 0 : mlx5_flow_pop_thread_workspace();
13813 : 0 : return ret;
13814 : : }
13815 : :
13816 : : static int
13817 : 0 : flow_hw_unregister_matcher(struct rte_eth_dev *dev,
13818 : : struct mlx5_flow_dv_matcher *matcher)
13819 : : {
13820 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13821 : 0 : struct mlx5_flow_group *group = matcher->group;
13822 : : int ret = 0;
13823 : :
13824 [ # # ]: 0 : if (group) {
13825 [ # # ]: 0 : if (matcher->matcher_object)
13826 : 0 : ret |= mlx5_list_unregister(group->matchers, &matcher->entry);
13827 : 0 : ret |= mlx5_hlist_unregister(priv->sh->groups, &group->entry);
13828 : : }
13829 : 0 : return ret;
13830 : : }
13831 : :
13832 : 0 : static int flow_hw_register_matcher(struct rte_eth_dev *dev,
13833 : : const struct rte_flow_attr *attr,
13834 : : const struct rte_flow_item items[],
13835 : : bool external,
13836 : : struct rte_flow_hw *flow,
13837 : : struct mlx5_flow_dv_matcher *matcher,
13838 : : struct rte_flow_error *error)
13839 : : {
13840 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13841 : 0 : struct rte_flow_error sub_error = {
13842 : : .type = RTE_FLOW_ERROR_TYPE_NONE,
13843 : : .cause = NULL,
13844 : : .message = NULL,
13845 : : };
13846 : 0 : struct rte_flow_attr flow_attr = *attr;
13847 : 0 : uint32_t specialize = 0; /* No unified FDB. */
13848 : 0 : struct mlx5_flow_cb_ctx ctx = {
13849 : : .dev = dev,
13850 : : .error = &sub_error,
13851 : : .data = &flow_attr,
13852 : : .data2 = &specialize,
13853 : : };
13854 : : void *items_ptr = &items;
13855 : 0 : struct mlx5_flow_cb_ctx matcher_ctx = {
13856 : : .error = &sub_error,
13857 : : .data = matcher,
13858 : : .data2 = items_ptr,
13859 : : };
13860 : : struct mlx5_list_entry *group_entry = NULL;
13861 : : struct mlx5_list_entry *matcher_entry = NULL;
13862 : : struct mlx5_flow_dv_matcher *resource;
13863 : : struct mlx5_list *matchers_list;
13864 : : struct mlx5_flow_group *flow_group;
13865 : : int ret;
13866 : :
13867 : :
13868 : 0 : matcher->crc = rte_raw_cksum((const void *)matcher->mask.buf,
13869 : : matcher->mask.size);
13870 : 0 : matcher->priority = attr->priority;
13871 : 0 : ret = __translate_group(dev, attr, external, attr->group, &flow_attr.group, error);
13872 [ # # ]: 0 : if (ret)
13873 : : return ret;
13874 : :
13875 : : /* Register the flow group. */
13876 : 0 : group_entry = mlx5_hlist_register(priv->sh->groups, flow_attr.group, &ctx);
13877 [ # # ]: 0 : if (!group_entry)
13878 : 0 : goto error;
13879 : : flow_group = container_of(group_entry, struct mlx5_flow_group, entry);
13880 : :
13881 : 0 : matchers_list = flow_group->matchers;
13882 : 0 : matcher->group = flow_group;
13883 : 0 : matcher_entry = mlx5_list_register(matchers_list, &matcher_ctx);
13884 [ # # ]: 0 : if (!matcher_entry)
13885 : 0 : goto error;
13886 : : resource = container_of(matcher_entry, typeof(*resource), entry);
13887 : 0 : flow->nt2hws->matcher = resource;
13888 : 0 : return 0;
13889 : :
13890 : 0 : error:
13891 [ # # ]: 0 : if (group_entry)
13892 : 0 : mlx5_hlist_unregister(priv->sh->groups, group_entry);
13893 [ # # ]: 0 : if (error) {
13894 [ # # ]: 0 : if (sub_error.type != RTE_FLOW_ERROR_TYPE_NONE)
13895 : : rte_memcpy(error, &sub_error, sizeof(sub_error));
13896 : : }
13897 : 0 : return rte_flow_error_set(error, ENOMEM,
13898 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13899 : : NULL, "fail to register matcher");
13900 : : }
13901 : :
13902 : : static int
13903 : 0 : flow_hw_allocate_actions(struct rte_eth_dev *dev,
13904 : : uint64_t action_flags,
13905 : : struct rte_flow_error *error)
13906 : : {
13907 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13908 : : int ret;
13909 : : uint obj_num;
13910 : :
13911 : 0 : error->type = RTE_FLOW_ERROR_TYPE_NONE;
13912 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_AGE) {
13913 : : /* If no age objects were previously allocated. */
13914 [ # # ]: 0 : if (!priv->hws_age_req) {
13915 : : /* If no counters were previously allocated. */
13916 [ # # ]: 0 : if (!priv->hws_cpool) {
13917 : 0 : obj_num = MLX5_CNT_NT_MAX(priv);
13918 : 0 : ret = mlx5_hws_cnt_pool_create(dev, obj_num,
13919 : 0 : priv->nb_queue,
13920 : : NULL, error);
13921 [ # # ]: 0 : if (ret)
13922 : 0 : goto err;
13923 : : }
13924 : : /* Allocate same number of counters. */
13925 : 0 : ret = mlx5_hws_age_pool_init(dev, priv->hws_cpool->cfg.request_num,
13926 : 0 : priv->nb_queue, false);
13927 [ # # ]: 0 : if (ret)
13928 : 0 : goto err;
13929 : : }
13930 : : }
13931 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_COUNT) {
13932 : : /* If no counters were previously allocated. */
13933 [ # # ]: 0 : if (!priv->hws_cpool) {
13934 : 0 : obj_num = MLX5_CNT_NT_MAX(priv);
13935 : 0 : ret = mlx5_hws_cnt_pool_create(dev, obj_num,
13936 : 0 : priv->nb_queue, NULL,
13937 : : error);
13938 [ # # ]: 0 : if (ret)
13939 : 0 : goto err;
13940 : : }
13941 : : }
13942 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_CT) {
13943 : : /* If no CT were previously allocated. */
13944 [ # # ]: 0 : if (!priv->hws_ctpool) {
13945 : 0 : obj_num = MLX5_CT_NT_MAX(priv);
13946 : 0 : ret = mlx5_flow_ct_init(dev, obj_num, priv->nb_queue);
13947 [ # # ]: 0 : if (ret)
13948 : 0 : goto err;
13949 : : }
13950 : : }
13951 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_METER) {
13952 : : /* If no meters were previously allocated. */
13953 [ # # ]: 0 : if (!priv->hws_mpool) {
13954 : 0 : obj_num = MLX5_MTR_NT_MAX(priv);
13955 : 0 : ret = mlx5_flow_meter_init(dev, obj_num, 0, 0,
13956 : : priv->nb_queue);
13957 [ # # ]: 0 : if (ret)
13958 : 0 : goto err;
13959 : : }
13960 : : }
13961 : : return 0;
13962 : 0 : err:
13963 [ # # ]: 0 : if (ret && error->type != RTE_FLOW_ERROR_TYPE_NONE)
13964 : : return ret;
13965 : 0 : return rte_flow_error_set(error, ret,
13966 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13967 : : NULL, "fail to allocate actions");
13968 : : }
13969 : :
13970 : 0 : static int flow_hw_apply(const struct rte_flow_item items[],
13971 : : struct mlx5dr_rule_action rule_actions[],
13972 : : struct rte_flow_hw *flow,
13973 : : struct rte_flow_error *error)
13974 : : {
13975 : : struct mlx5dr_bwc_rule *rule = NULL;
13976 : :
13977 : 0 : rule = mlx5dr_bwc_rule_create((struct mlx5dr_bwc_matcher *)
13978 : 0 : flow->nt2hws->matcher->matcher_object,
13979 : : items, rule_actions);
13980 : 0 : flow->nt2hws->nt_rule = rule;
13981 [ # # ]: 0 : if (!rule) {
13982 : 0 : return rte_flow_error_set(error, EINVAL,
13983 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13984 : : NULL, "fail to create rte flow");
13985 : : }
13986 : : return 0;
13987 : : }
13988 : :
13989 : : #ifdef HAVE_MLX5_HWS_SUPPORT
13990 : : /**
13991 : : * Create a flow.
13992 : : *
13993 : : * @param[in] dev
13994 : : * Pointer to Ethernet device.
13995 : : * @param[in] type
13996 : : * Flow type.
13997 : : * @param[in] attr
13998 : : * Flow rule attributes.
13999 : : * @param[in] items
14000 : : * Pattern specification (list terminated by the END pattern item).
14001 : : * @param[in] actions
14002 : : * Associated actions (list terminated by the END action).
14003 : : * @param[in] external
14004 : : * This flow rule is created by request external to PMD.
14005 : : * @param[out] flow
14006 : : * Flow pointer
14007 : : * @param[out] error
14008 : : * Perform verbose error reporting if not NULL.
14009 : : *
14010 : : * @return
14011 : : * 0 on success, negative errno value otherwise and rte_errno set.
14012 : : */
14013 : : int
14014 : 0 : flow_hw_create_flow(struct rte_eth_dev *dev, enum mlx5_flow_type type,
14015 : : const struct rte_flow_attr *attr,
14016 : : const struct rte_flow_item items[],
14017 : : const struct rte_flow_action actions[],
14018 : : uint64_t item_flags, uint64_t action_flags, bool external,
14019 : : struct rte_flow_hw **flow, struct rte_flow_error *error)
14020 : : {
14021 : : int ret;
14022 : 0 : struct mlx5_hw_actions hw_act = { { NULL } };
14023 : : struct mlx5_flow_hw_action_params ap;
14024 : 0 : struct mlx5_flow_dv_matcher matcher = {
14025 : : .mask = {
14026 : : .size = sizeof(matcher.mask.buf),
14027 : : },
14028 : : };
14029 : : uint32_t tbl_type;
14030 : :
14031 : 0 : struct mlx5_flow_attr flow_attr = {
14032 : 0 : .port_id = dev->data->port_id,
14033 : 0 : .group = attr->group,
14034 : 0 : .priority = attr->priority,
14035 : : .rss_level = 0,
14036 : : .act_flags = action_flags,
14037 : : .tbl_type = 0,
14038 : : };
14039 : :
14040 [ # # ]: 0 : if (attr->transfer)
14041 : : tbl_type = MLX5DR_TABLE_TYPE_FDB;
14042 [ # # ]: 0 : else if (attr->egress)
14043 : : tbl_type = MLX5DR_TABLE_TYPE_NIC_TX;
14044 : : else
14045 : : tbl_type = MLX5DR_TABLE_TYPE_NIC_RX;
14046 : 0 : flow_attr.tbl_type = tbl_type;
14047 : :
14048 : : /* Allocate needed memory. */
14049 : 0 : ret = flow_hw_prepare(dev, actions, type, flow, error);
14050 [ # # ]: 0 : if (ret)
14051 : 0 : goto error;
14052 : :
14053 : : /* TODO TBD flow_hw_handle_tunnel_offload(). */
14054 : 0 : (*flow)->nt_rule = true;
14055 : 0 : (*flow)->nt2hws->matcher = &matcher;
14056 : 0 : ret = __flow_dv_translate_items_hws(items, &flow_attr, &matcher.mask.buf,
14057 : : MLX5_SET_MATCHER_HS_M, NULL,
14058 : : NULL, true, error);
14059 : :
14060 [ # # ]: 0 : if (ret)
14061 : 0 : goto error;
14062 : :
14063 [ # # # # ]: 0 : if (item_flags & MLX5_FLOW_LAYER_ECPRI && !mlx5_flex_parser_ecpri_exist(dev))
14064 [ # # ]: 0 : if (mlx5_flex_parser_ecpri_alloc(dev)) {
14065 : 0 : rte_flow_error_set(error, EIO,
14066 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14067 : : NULL,
14068 : : "failed to create Flex parser "
14069 : : "profile for ECPRI");
14070 : 0 : goto error;
14071 : : }
14072 : 0 : ret = flow_hw_register_matcher(dev, attr, items, external, *flow, &matcher, error);
14073 [ # # ]: 0 : if (ret)
14074 : 0 : goto error;
14075 : :
14076 : : /*
14077 : : * ASO allocation – iterating on actions list to allocate missing resources.
14078 : : * In the future when validate function in hws will be added,
14079 : : * The output actions bit mask instead of
14080 : : * looping on the actions array twice.
14081 : : */
14082 : 0 : ret = flow_hw_allocate_actions(dev, action_flags, error);
14083 [ # # ]: 0 : if (ret)
14084 : 0 : goto error;
14085 : :
14086 : : /* Note: the actions should be saved in the sub-flow rule itself for reference. */
14087 : 0 : ret = flow_hw_translate_flow_actions(dev, attr, actions, *flow, &ap, &hw_act,
14088 : : item_flags, action_flags, external, error);
14089 [ # # ]: 0 : if (ret)
14090 : 0 : goto error;
14091 : :
14092 : : /*
14093 : : * If the flow is external (from application) OR device is started,
14094 : : * OR mreg discover, then apply immediately.
14095 : : */
14096 [ # # # # ]: 0 : if (external || dev->data->dev_started ||
14097 [ # # ]: 0 : (attr->group == MLX5_FLOW_MREG_CP_TABLE_GROUP &&
14098 [ # # ]: 0 : attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR)) {
14099 : 0 : ret = flow_hw_apply(items, hw_act.rule_acts, *flow, error);
14100 [ # # ]: 0 : if (ret)
14101 : 0 : goto error;
14102 : : }
14103 : : ret = 0;
14104 : 0 : error:
14105 : : /*
14106 : : * Release memory allocated.
14107 : : * Cannot use __flow_hw_actions_release(dev, &hw_act);
14108 : : * since it destroys the actions as well.
14109 : : */
14110 [ # # ]: 0 : if (hw_act.encap_decap)
14111 : 0 : mlx5_free(hw_act.encap_decap);
14112 [ # # ]: 0 : if (hw_act.push_remove)
14113 : 0 : mlx5_free(hw_act.push_remove);
14114 [ # # ]: 0 : if (hw_act.mhdr)
14115 : 0 : mlx5_free(hw_act.mhdr);
14116 [ # # ]: 0 : if (ret) {
14117 : : /* release after actual error */
14118 [ # # # # ]: 0 : if ((*flow)->nt2hws && (*flow)->nt2hws->matcher)
14119 : 0 : flow_hw_unregister_matcher(dev, (*flow)->nt2hws->matcher);
14120 : : }
14121 : 0 : return ret;
14122 : : }
14123 : : #endif
14124 : :
14125 : : void
14126 : 0 : flow_hw_destroy(struct rte_eth_dev *dev, struct rte_flow_hw *flow)
14127 : : {
14128 : : int ret;
14129 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14130 : :
14131 [ # # # # ]: 0 : if (!flow || !flow->nt2hws)
14132 : : return;
14133 : :
14134 [ # # ]: 0 : if (flow->nt2hws->nt_rule) {
14135 : 0 : ret = mlx5dr_bwc_rule_destroy(flow->nt2hws->nt_rule);
14136 [ # # ]: 0 : if (ret)
14137 : 0 : DRV_LOG(ERR, "bwc rule destroy failed");
14138 : : }
14139 [ # # ]: 0 : flow->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_DESTROY;
14140 : : /* Notice this function does not handle shared/static actions. */
14141 : : hw_cmpl_flow_update_or_destroy(dev, flow, 0, NULL);
14142 : :
14143 : : /**
14144 : : * TODO: TBD - Release tunnel related memory allocations(mlx5_flow_tunnel_free)
14145 : : * – needed only if supporting tunnel offloads, notice update RX queue flags in SWS.
14146 : : */
14147 : :
14148 : : /**
14149 : : * Notice matcher destroy will take place when matcher's list is destroyed
14150 : : * , same as for DV.
14151 : : */
14152 [ # # ]: 0 : if (flow->nt2hws->flow_aux)
14153 : 0 : mlx5_free(flow->nt2hws->flow_aux);
14154 : :
14155 [ # # ]: 0 : if (flow->nt2hws->rix_encap_decap)
14156 : 0 : flow_encap_decap_resource_release(dev, flow->nt2hws->rix_encap_decap);
14157 [ # # ]: 0 : if (flow->nt2hws->modify_hdr) {
14158 : : MLX5_ASSERT(flow->nt2hws->modify_hdr->action);
14159 : 0 : mlx5_hlist_unregister(priv->sh->modify_cmds,
14160 : : &flow->nt2hws->modify_hdr->entry);
14161 : : }
14162 [ # # ]: 0 : if (flow->nt2hws->matcher)
14163 : 0 : flow_hw_unregister_matcher(dev, flow->nt2hws->matcher);
14164 : : }
14165 : :
14166 : : #ifdef HAVE_MLX5_HWS_SUPPORT
14167 : : /**
14168 : : * Destroy a flow.
14169 : : *
14170 : : * @param[in] dev
14171 : : * Pointer to Ethernet device.
14172 : : * @param[in] type
14173 : : * Flow type.
14174 : : * @param[in] flow_addr
14175 : : * Address of flow to destroy.
14176 : : */
14177 : : void
14178 : 0 : flow_hw_list_destroy(struct rte_eth_dev *dev, enum mlx5_flow_type type,
14179 : : uintptr_t flow_addr)
14180 : : {
14181 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14182 : 0 : struct rte_flow_hw *flow = (struct rte_flow_hw *)flow_addr;
14183 : : struct mlx5_nta_rss_flow_head head = { .slh_first = flow };
14184 : :
14185 [ # # # # : 0 : if (!flow || !flow->nt2hws || flow->nt2hws->chaned_flow)
# # ]
14186 : : return;
14187 : 0 : mlx5_flow_nta_del_copy_action(dev, flow->nt2hws->rix_mreg_copy);
14188 [ # # ]: 0 : while (!SLIST_EMPTY(&head)) {
14189 : : flow = SLIST_FIRST(&head);
14190 : 0 : SLIST_REMOVE_HEAD(&head, nt2hws->next);
14191 : 0 : flow_hw_destroy(dev, flow);
14192 : : /* Release flow memory by idx */
14193 : 0 : mlx5_ipool_free(priv->flows[type], flow->idx);
14194 : : }
14195 : : }
14196 : : #endif
14197 : :
14198 : : /**
14199 : : * Create a flow.
14200 : : *
14201 : : * @param[in] dev
14202 : : * Pointer to Ethernet device.
14203 : : * @param[in] type
14204 : : * Flow type.
14205 : : * @param[in] attr
14206 : : * Flow rule attributes.
14207 : : * @param[in] items
14208 : : * Pattern specification (list terminated by the END pattern item).
14209 : : * @param[in] actions
14210 : : * Associated actions (list terminated by the END action).
14211 : : * @param[in] external
14212 : : * This flow rule is created by request external to PMD.
14213 : : * @param[out] error
14214 : : * Perform verbose error reporting if not NULL.
14215 : : *
14216 : : * @return
14217 : : * A flow addr on success, 0 otherwise and rte_errno is set.
14218 : : */
14219 : 0 : static uintptr_t flow_hw_list_create(struct rte_eth_dev *dev,
14220 : : enum mlx5_flow_type type,
14221 : : const struct rte_flow_attr *attr,
14222 : : const struct rte_flow_item items[],
14223 : : const struct rte_flow_action actions[],
14224 : : bool external,
14225 : : struct rte_flow_error *error)
14226 : : {
14227 : : int ret;
14228 : : int split;
14229 : : int encap_idx;
14230 : 0 : uint32_t cpy_idx = 0;
14231 : 0 : int actions_n = 0;
14232 : 0 : struct rte_flow_hw *flow = NULL;
14233 : 0 : struct rte_flow_hw *prfx_flow = NULL;
14234 : 0 : const struct rte_flow_action *qrss = NULL;
14235 : 0 : const struct rte_flow_action *mark = NULL;
14236 : 0 : uint64_t item_flags = 0;
14237 : 0 : uint64_t action_flags = flow_hw_action_flags_get(actions, &qrss, &mark,
14238 : : &encap_idx, &actions_n, error);
14239 : 0 : struct mlx5_flow_hw_split_resource resource = {
14240 : : .suffix = {
14241 : : .attr = attr,
14242 : : .items = items,
14243 : : .actions = actions,
14244 : : },
14245 : : };
14246 : 0 : struct rte_flow_error shadow_error = {0, };
14247 : 0 : const struct rte_flow_pattern_template_attr pattern_template_attr = {
14248 : : .relaxed_matching = 0,
14249 : 0 : .ingress = attr->ingress,
14250 : 0 : .egress = attr->egress,
14251 : 0 : .transfer = attr->transfer,
14252 : : };
14253 : :
14254 : : /* Validate application items only */
14255 : 0 : ret = flow_hw_pattern_validate(dev, &pattern_template_attr, items,
14256 : : &item_flags, error);
14257 [ # # ]: 0 : if (ret < 0)
14258 : : return 0;
14259 : :
14260 : : RTE_SET_USED(encap_idx);
14261 [ # # ]: 0 : if (!error)
14262 : : error = &shadow_error;
14263 : 0 : split = mlx5_flow_nta_split_metadata(dev, attr, actions, qrss, action_flags,
14264 : : actions_n, external, &resource, error);
14265 [ # # ]: 0 : if (split < 0)
14266 : 0 : return split;
14267 : :
14268 : : /* Update the metadata copy table - MLX5_FLOW_MREG_CP_TABLE_GROUP */
14269 [ # # # # : 0 : if (((attr->ingress && attr->group != MLX5_FLOW_MREG_CP_TABLE_GROUP) ||
# # ]
14270 [ # # ]: 0 : attr->transfer) && external) {
14271 : 0 : ret = mlx5_flow_nta_update_copy_table(dev, &cpy_idx, mark,
14272 : : action_flags, error);
14273 [ # # ]: 0 : if (ret)
14274 : 0 : goto free;
14275 : : }
14276 : :
14277 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_RSS) {
14278 : : const struct rte_flow_action_rss
14279 : 0 : *rss_conf = flow_nta_locate_rss(dev, actions, error);
14280 : 0 : flow = flow_nta_handle_rss(dev, attr, items, actions, rss_conf,
14281 : : item_flags, action_flags, external,
14282 : : type, error);
14283 [ # # ]: 0 : if (flow) {
14284 : 0 : flow->nt2hws->rix_mreg_copy = cpy_idx;
14285 : 0 : cpy_idx = 0;
14286 [ # # ]: 0 : if (!split)
14287 : 0 : return (uintptr_t)flow;
14288 : 0 : goto prefix_flow;
14289 : : }
14290 : 0 : goto free;
14291 : : }
14292 : : /* Create single flow. */
14293 : 0 : ret = flow_hw_create_flow(dev, type, resource.suffix.attr, resource.suffix.items,
14294 : : resource.suffix.actions, item_flags, action_flags,
14295 : : external, &flow, error);
14296 [ # # ]: 0 : if (ret)
14297 : 0 : goto free;
14298 [ # # ]: 0 : if (flow) {
14299 : 0 : flow->nt2hws->rix_mreg_copy = cpy_idx;
14300 : 0 : cpy_idx = 0;
14301 [ # # ]: 0 : if (!split)
14302 : 0 : return (uintptr_t)flow;
14303 : : /* Fall Through to prefix flow creation. */
14304 : : }
14305 : 0 : prefix_flow:
14306 : 0 : ret = flow_hw_create_flow(dev, type, attr, items, resource.prefix.actions,
14307 : : item_flags, action_flags, external, &prfx_flow, error);
14308 [ # # ]: 0 : if (ret)
14309 : 0 : goto free;
14310 [ # # ]: 0 : if (prfx_flow) {
14311 : 0 : prfx_flow->nt2hws->rix_mreg_copy = flow->nt2hws->rix_mreg_copy;
14312 : 0 : flow->nt2hws->chaned_flow = 1;
14313 : 0 : SLIST_INSERT_AFTER(prfx_flow, flow, nt2hws->next);
14314 : 0 : mlx5_flow_nta_split_resource_free(dev, &resource);
14315 : 0 : return (uintptr_t)prfx_flow;
14316 : : }
14317 : 0 : free:
14318 [ # # ]: 0 : if (prfx_flow)
14319 : 0 : flow_hw_list_destroy(dev, type, (uintptr_t)prfx_flow);
14320 [ # # ]: 0 : if (flow)
14321 : 0 : flow_hw_list_destroy(dev, type, (uintptr_t)flow);
14322 [ # # ]: 0 : if (cpy_idx)
14323 : 0 : mlx5_flow_nta_del_copy_action(dev, cpy_idx);
14324 [ # # ]: 0 : if (split > 0)
14325 : 0 : mlx5_flow_nta_split_resource_free(dev, &resource);
14326 : : return 0;
14327 : : }
14328 : :
14329 : : static void
14330 : 0 : mlx5_mirror_destroy_clone(struct rte_eth_dev *dev,
14331 : : struct mlx5_mirror_clone *clone)
14332 : : {
14333 [ # # # ]: 0 : switch (clone->type) {
14334 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
14335 : : case RTE_FLOW_ACTION_TYPE_QUEUE:
14336 : 0 : mlx5_hrxq_release(dev,
14337 : 0 : ((struct mlx5_hrxq *)(clone->action_ctx))->idx);
14338 : 0 : break;
14339 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP:
14340 : 0 : flow_hw_jump_release(dev, clone->action_ctx);
14341 : : break;
14342 : : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
14343 : : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
14344 : : case RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:
14345 : : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
14346 : : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
14347 : : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
14348 : : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
14349 : : default:
14350 : : break;
14351 : : }
14352 : 0 : }
14353 : :
14354 : : void
14355 [ # # ]: 0 : mlx5_hw_mirror_destroy(struct rte_eth_dev *dev, struct mlx5_mirror *mirror)
14356 : : {
14357 : : uint32_t i;
14358 : :
14359 : : mlx5_indirect_list_remove_entry(&mirror->indirect);
14360 [ # # ]: 0 : for (i = 0; i < mirror->clones_num; i++)
14361 : 0 : mlx5_mirror_destroy_clone(dev, &mirror->clone[i]);
14362 [ # # ]: 0 : if (mirror->mirror_action)
14363 : 0 : mlx5dr_action_destroy(mirror->mirror_action);
14364 : 0 : mlx5_free(mirror);
14365 : 0 : }
14366 : :
14367 : : static __rte_always_inline bool
14368 : : mlx5_mirror_terminal_action(const struct rte_flow_action *action)
14369 : : {
14370 : 0 : switch (action->type) {
14371 : : case RTE_FLOW_ACTION_TYPE_JUMP:
14372 : : case RTE_FLOW_ACTION_TYPE_RSS:
14373 : : case RTE_FLOW_ACTION_TYPE_QUEUE:
14374 : : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
14375 : : case RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:
14376 : : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
14377 : : case RTE_FLOW_ACTION_TYPE_DROP:
14378 : : return true;
14379 : : default:
14380 : : break;
14381 : : }
14382 : : return false;
14383 : : }
14384 : :
14385 : : static bool
14386 : 0 : mlx5_mirror_validate_sample_action(struct rte_eth_dev *dev,
14387 : : const struct rte_flow_attr *flow_attr,
14388 : : const struct rte_flow_action *action)
14389 : : {
14390 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14391 : : const struct rte_flow_action_ethdev *port = NULL;
14392 [ # # # # ]: 0 : bool is_proxy = MLX5_HW_PORT_IS_PROXY(priv);
14393 : :
14394 [ # # ]: 0 : if (!action)
14395 : : return false;
14396 [ # # # # : 0 : switch (action->type) {
# ]
14397 : 0 : case RTE_FLOW_ACTION_TYPE_QUEUE:
14398 : : case RTE_FLOW_ACTION_TYPE_RSS:
14399 [ # # ]: 0 : if (flow_attr->transfer)
14400 : : return false;
14401 : : break;
14402 : 0 : case RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:
14403 [ # # # # ]: 0 : if (!is_proxy || !flow_attr->transfer)
14404 : : return false;
14405 : 0 : port = action->conf;
14406 [ # # # # ]: 0 : if (!port || port->port_id != MLX5_REPRESENTED_PORT_ESW_MGR)
14407 : : return false;
14408 : : break;
14409 : 0 : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
14410 : : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
14411 : : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
14412 : : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
14413 : : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
14414 [ # # # # ]: 0 : if (!is_proxy || !flow_attr->transfer)
14415 : : return false;
14416 [ # # ]: 0 : if (action[0].type == RTE_FLOW_ACTION_TYPE_RAW_DECAP &&
14417 [ # # ]: 0 : action[1].type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP)
14418 : : return false;
14419 : : break;
14420 : : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
14421 : : case RTE_FLOW_ACTION_TYPE_JUMP:
14422 : : case RTE_FLOW_ACTION_TYPE_DROP:
14423 : : break;
14424 : : default:
14425 : : return false;
14426 : : }
14427 : 0 : return true;
14428 : : }
14429 : :
14430 : : /**
14431 : : * Valid mirror actions list includes one or two SAMPLE actions
14432 : : * followed by JUMP.
14433 : : *
14434 : : * @return
14435 : : * Number of mirrors *action* list was valid.
14436 : : * -EINVAL otherwise.
14437 : : */
14438 : : static int
14439 : 0 : mlx5_hw_mirror_actions_list_validate(struct rte_eth_dev *dev,
14440 : : const struct rte_flow_attr *flow_attr,
14441 : : const struct rte_flow_action *actions)
14442 : : {
14443 [ # # ]: 0 : if (actions[0].type == RTE_FLOW_ACTION_TYPE_SAMPLE) {
14444 : : int i = 1;
14445 : : bool valid;
14446 : 0 : const struct rte_flow_action_sample *sample = actions[0].conf;
14447 : 0 : valid = mlx5_mirror_validate_sample_action(dev, flow_attr,
14448 : 0 : sample->actions);
14449 [ # # ]: 0 : if (!valid)
14450 : : return -EINVAL;
14451 [ # # ]: 0 : if (actions[1].type == RTE_FLOW_ACTION_TYPE_SAMPLE) {
14452 : : i = 2;
14453 : 0 : sample = actions[1].conf;
14454 : 0 : valid = mlx5_mirror_validate_sample_action(dev, flow_attr,
14455 : 0 : sample->actions);
14456 [ # # ]: 0 : if (!valid)
14457 : : return -EINVAL;
14458 : : }
14459 [ # # ]: 0 : return mlx5_mirror_terminal_action(actions + i) ? i + 1 : -EINVAL;
14460 : : }
14461 : : return -EINVAL;
14462 : : }
14463 : :
14464 : : static int
14465 : 0 : mirror_format_tir(struct rte_eth_dev *dev,
14466 : : struct mlx5_mirror_clone *clone,
14467 : : const struct mlx5_flow_template_table_cfg *table_cfg,
14468 : : const struct rte_flow_action *action,
14469 : : struct mlx5dr_action_dest_attr *dest_attr,
14470 : : struct rte_flow_error *error)
14471 : : {
14472 : : uint32_t hws_flags;
14473 : : enum mlx5dr_table_type table_type;
14474 : : struct mlx5_hrxq *tir_ctx;
14475 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14476 : : bool unified_fdb = is_unified_fdb(priv);
14477 : :
14478 : 0 : table_type = get_mlx5dr_table_type(&table_cfg->attr.flow_attr, table_cfg->attr.specialize,
14479 : : unified_fdb);
14480 : 0 : hws_flags = mlx5_hw_act_flag[MLX5_HW_ACTION_FLAG_NONE_ROOT][table_type];
14481 : 0 : tir_ctx = flow_hw_tir_action_register(dev, hws_flags, action);
14482 [ # # ]: 0 : if (!tir_ctx)
14483 : 0 : return rte_flow_error_set(error, EINVAL,
14484 : : RTE_FLOW_ERROR_TYPE_ACTION,
14485 : : action, "failed to create QUEUE action for mirror clone");
14486 : 0 : dest_attr->dest = tir_ctx->action;
14487 : 0 : clone->action_ctx = tir_ctx;
14488 : 0 : return 0;
14489 : : }
14490 : :
14491 : : static int
14492 : 0 : mirror_format_jump(struct rte_eth_dev *dev,
14493 : : struct mlx5_mirror_clone *clone,
14494 : : const struct mlx5_flow_template_table_cfg *table_cfg,
14495 : : const struct rte_flow_action *action,
14496 : : struct mlx5dr_action_dest_attr *dest_attr,
14497 : : struct rte_flow_error *error)
14498 : : {
14499 : 0 : const struct rte_flow_action_jump *jump_conf = action->conf;
14500 : 0 : struct mlx5_hw_jump_action *jump = flow_hw_jump_action_register
14501 : : (dev, table_cfg,
14502 : 0 : jump_conf->group, error);
14503 : :
14504 [ # # ]: 0 : if (!jump)
14505 : 0 : return rte_flow_error_set(error, EINVAL,
14506 : : RTE_FLOW_ERROR_TYPE_ACTION,
14507 : : action, "failed to create JUMP action for mirror clone");
14508 : 0 : dest_attr->dest = jump->hws_action;
14509 : 0 : clone->action_ctx = jump;
14510 : 0 : return 0;
14511 : : }
14512 : :
14513 : : static int
14514 : : mirror_format_port(struct rte_eth_dev *dev,
14515 : : const struct rte_flow_action *action,
14516 : : struct mlx5dr_action_dest_attr *dest_attr,
14517 : : struct rte_flow_error __rte_unused *error)
14518 : : {
14519 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14520 : 0 : const struct rte_flow_action_ethdev *port_action = action->conf;
14521 : :
14522 : 0 : dest_attr->dest = priv->hw_vport[port_action->port_id];
14523 : : return 0;
14524 : : }
14525 : :
14526 : : static int
14527 : 0 : hw_mirror_clone_reformat(const struct rte_flow_action *actions,
14528 : : struct mlx5dr_action_dest_attr *dest_attr,
14529 : : enum mlx5dr_action_type *action_type,
14530 : : uint8_t *reformat_buf, bool decap)
14531 : : {
14532 : : int ret;
14533 : : const struct rte_flow_item *encap_item = NULL;
14534 : : const struct rte_flow_action_raw_encap *encap_conf = NULL;
14535 : : typeof(dest_attr->reformat) *reformat = &dest_attr->reformat;
14536 : :
14537 [ # # # # ]: 0 : switch (actions[0].type) {
14538 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
14539 : 0 : encap_conf = actions[0].conf;
14540 : 0 : break;
14541 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
14542 : 0 : encap_item = MLX5_CONST_ENCAP_ITEM(rte_flow_action_vxlan_encap,
14543 : : actions);
14544 : 0 : break;
14545 : 0 : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
14546 : 0 : encap_item = MLX5_CONST_ENCAP_ITEM(rte_flow_action_nvgre_encap,
14547 : : actions);
14548 : 0 : break;
14549 : : default:
14550 : : return -EINVAL;
14551 : : }
14552 : 0 : *action_type = decap ?
14553 [ # # ]: 0 : MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3 :
14554 : : MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;
14555 [ # # ]: 0 : if (encap_item) {
14556 : 0 : ret = flow_dv_convert_encap_data(encap_item, reformat_buf,
14557 : : &reformat->reformat_data_sz, NULL);
14558 [ # # ]: 0 : if (ret)
14559 : : return -EINVAL;
14560 : 0 : reformat->reformat_data = reformat_buf;
14561 : : } else {
14562 : 0 : reformat->reformat_data = (void *)(uintptr_t)encap_conf->data;
14563 : 0 : reformat->reformat_data_sz = encap_conf->size;
14564 : : }
14565 : : return 0;
14566 : : }
14567 : :
14568 : : static int
14569 : 0 : hw_mirror_format_clone(struct rte_eth_dev *dev,
14570 : : struct mlx5_mirror_clone *clone,
14571 : : const struct mlx5_flow_template_table_cfg *table_cfg,
14572 : : const struct rte_flow_action *actions,
14573 : : struct mlx5dr_action_dest_attr *dest_attr,
14574 : : uint8_t *reformat_buf, struct rte_flow_error *error)
14575 : : {
14576 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14577 : : int ret;
14578 : : uint32_t i;
14579 : : bool decap_seen = false;
14580 : :
14581 [ # # ]: 0 : for (i = 0; actions[i].type != RTE_FLOW_ACTION_TYPE_END; i++) {
14582 : 0 : dest_attr->action_type[i] = mlx5_hw_dr_action_types[actions[i].type];
14583 [ # # # # : 0 : switch (actions[i].type) {
# # # # ]
14584 : 0 : case RTE_FLOW_ACTION_TYPE_QUEUE:
14585 : : case RTE_FLOW_ACTION_TYPE_RSS:
14586 : 0 : ret = mirror_format_tir(dev, clone, table_cfg,
14587 : : &actions[i], dest_attr, error);
14588 [ # # ]: 0 : if (ret)
14589 : 0 : return ret;
14590 : : break;
14591 : 0 : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
14592 : : ret = mirror_format_port(dev, &actions[i],
14593 : : dest_attr, error);
14594 : : if (ret)
14595 : : return ret;
14596 : : break;
14597 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP:
14598 : 0 : ret = mirror_format_jump(dev, clone, table_cfg,
14599 : : &actions[i], dest_attr, error);
14600 [ # # ]: 0 : if (ret)
14601 : 0 : return ret;
14602 : : break;
14603 : 0 : case RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:
14604 : 0 : dest_attr->dest = priv->hw_def_miss;
14605 : 0 : break;
14606 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
14607 : : decap_seen = true;
14608 : 0 : break;
14609 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
14610 : : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
14611 : : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
14612 : 0 : ret = hw_mirror_clone_reformat(&actions[i], dest_attr,
14613 : : &dest_attr->action_type[i],
14614 : : reformat_buf, decap_seen);
14615 [ # # ]: 0 : if (ret < 0)
14616 : 0 : return rte_flow_error_set(error, EINVAL,
14617 : : RTE_FLOW_ERROR_TYPE_ACTION,
14618 : : &actions[i],
14619 : : "failed to create reformat action");
14620 : : break;
14621 : : case RTE_FLOW_ACTION_TYPE_DROP:
14622 : : break;
14623 : 0 : default:
14624 : 0 : return rte_flow_error_set(error, EINVAL,
14625 : : RTE_FLOW_ERROR_TYPE_ACTION,
14626 : : &actions[i], "unsupported sample action");
14627 : : }
14628 : 0 : clone->type = actions->type;
14629 : : }
14630 : 0 : dest_attr->action_type[i] = MLX5DR_ACTION_TYP_LAST;
14631 : 0 : return 0;
14632 : : }
14633 : :
14634 : : static struct rte_flow_action_list_handle *
14635 : 0 : mlx5_hw_mirror_handle_create(struct rte_eth_dev *dev,
14636 : : const struct mlx5_flow_template_table_cfg *table_cfg,
14637 : : const struct rte_flow_action *actions,
14638 : : struct rte_flow_error *error)
14639 : : {
14640 : : uint32_t hws_flags;
14641 : : int ret = 0, i, clones_num;
14642 : : struct mlx5_mirror *mirror;
14643 : : enum mlx5dr_table_type table_type;
14644 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
14645 : : bool unified_fdb = is_unified_fdb(priv);
14646 [ # # ]: 0 : const struct rte_flow_attr *flow_attr = &table_cfg->attr.flow_attr;
14647 : : uint8_t reformat_buf[MLX5_MIRROR_MAX_CLONES_NUM][MLX5_ENCAP_MAX_LEN];
14648 : : struct mlx5dr_action_dest_attr mirror_attr[MLX5_MIRROR_MAX_CLONES_NUM + 1];
14649 : : enum mlx5dr_action_type array_action_types[MLX5_MIRROR_MAX_CLONES_NUM + 1]
14650 : : [MLX5_MIRROR_MAX_SAMPLE_ACTIONS_LEN + 1];
14651 : :
14652 : : memset(mirror_attr, 0, sizeof(mirror_attr));
14653 : : memset(array_action_types, 0, sizeof(array_action_types));
14654 : 0 : table_type = get_mlx5dr_table_type(flow_attr, table_cfg->attr.specialize, unified_fdb);
14655 : 0 : hws_flags = mlx5_hw_act_flag[MLX5_HW_ACTION_FLAG_NONE_ROOT][table_type];
14656 : 0 : clones_num = mlx5_hw_mirror_actions_list_validate(dev, flow_attr,
14657 : : actions);
14658 [ # # ]: 0 : if (clones_num < 0) {
14659 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14660 : : actions, "Invalid mirror list format");
14661 : 0 : return NULL;
14662 : : }
14663 : 0 : mirror = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mirror),
14664 : : 0, SOCKET_ID_ANY);
14665 [ # # ]: 0 : if (!mirror) {
14666 : 0 : rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_ACTION,
14667 : : actions, "Failed to allocate mirror context");
14668 : 0 : return NULL;
14669 : : }
14670 : :
14671 : 0 : mirror->indirect.type = MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR;
14672 : 0 : mirror->clones_num = clones_num;
14673 [ # # ]: 0 : for (i = 0; i < clones_num; i++) {
14674 : : const struct rte_flow_action *clone_actions;
14675 : :
14676 : 0 : mirror_attr[i].action_type = array_action_types[i];
14677 [ # # ]: 0 : if (actions[i].type == RTE_FLOW_ACTION_TYPE_SAMPLE) {
14678 : 0 : const struct rte_flow_action_sample *sample = actions[i].conf;
14679 : :
14680 : 0 : clone_actions = sample->actions;
14681 : : } else {
14682 : : clone_actions = &actions[i];
14683 : : }
14684 : 0 : ret = hw_mirror_format_clone(dev, &mirror->clone[i], table_cfg,
14685 : : clone_actions, &mirror_attr[i],
14686 : 0 : reformat_buf[i], error);
14687 : :
14688 [ # # ]: 0 : if (ret)
14689 : 0 : goto error;
14690 : : }
14691 : 0 : hws_flags |= MLX5DR_ACTION_FLAG_SHARED;
14692 : 0 : mirror->mirror_action = mlx5dr_action_create_dest_array(priv->dr_ctx,
14693 : : clones_num,
14694 : : mirror_attr,
14695 : : hws_flags);
14696 [ # # ]: 0 : if (!mirror->mirror_action) {
14697 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14698 : : actions, "Failed to create HWS mirror action");
14699 : 0 : goto error;
14700 : : }
14701 : :
14702 [ # # ]: 0 : mlx5_indirect_list_add_entry(&priv->indirect_list_head, &mirror->indirect);
14703 : 0 : return (struct rte_flow_action_list_handle *)mirror;
14704 : :
14705 : 0 : error:
14706 : 0 : mlx5_hw_mirror_destroy(dev, mirror);
14707 : 0 : return NULL;
14708 : : }
14709 : :
14710 : : void
14711 : 0 : mlx5_destroy_legacy_indirect(__rte_unused struct rte_eth_dev *dev,
14712 : : struct mlx5_indirect_list *ptr)
14713 : : {
14714 : : struct mlx5_indlst_legacy *obj = (typeof(obj))ptr;
14715 : :
14716 : : switch (obj->legacy_type) {
14717 : : case RTE_FLOW_ACTION_TYPE_METER_MARK:
14718 : : break; /* ASO meters were released in mlx5_flow_meter_flush() */
14719 : : default:
14720 : : break;
14721 : : }
14722 : 0 : mlx5_free(obj);
14723 : 0 : }
14724 : :
14725 : : static struct rte_flow_action_list_handle *
14726 : 0 : mlx5_create_legacy_indlst(struct rte_eth_dev *dev, uint32_t queue,
14727 : : const struct rte_flow_op_attr *attr,
14728 : : const struct rte_flow_indir_action_conf *conf,
14729 : : const struct rte_flow_action *actions,
14730 : : void *user_data, struct rte_flow_error *error)
14731 : : {
14732 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14733 : 0 : struct mlx5_indlst_legacy *indlst_obj = mlx5_malloc(MLX5_MEM_ZERO,
14734 : : sizeof(*indlst_obj),
14735 : : 0, SOCKET_ID_ANY);
14736 : :
14737 [ # # ]: 0 : if (!indlst_obj)
14738 : : return NULL;
14739 : 0 : indlst_obj->handle = flow_hw_action_handle_create(dev, queue, attr, conf,
14740 : : actions, user_data,
14741 : : error);
14742 [ # # ]: 0 : if (!indlst_obj->handle) {
14743 : 0 : mlx5_free(indlst_obj);
14744 : 0 : return NULL;
14745 : : }
14746 : 0 : indlst_obj->legacy_type = actions[0].type;
14747 : 0 : indlst_obj->indirect.type = MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY;
14748 [ # # ]: 0 : mlx5_indirect_list_add_entry(&priv->indirect_list_head, &indlst_obj->indirect);
14749 : 0 : return (struct rte_flow_action_list_handle *)indlst_obj;
14750 : : }
14751 : :
14752 : : static __rte_always_inline enum mlx5_indirect_list_type
14753 : : flow_hw_inlist_type_get(const struct rte_flow_action *actions)
14754 : : {
14755 [ # # # # ]: 0 : switch (actions[0].type) {
14756 : : case RTE_FLOW_ACTION_TYPE_SAMPLE:
14757 : : return MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR;
14758 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
14759 : 0 : return actions[1].type == RTE_FLOW_ACTION_TYPE_END ?
14760 : 0 : MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY :
14761 : : MLX5_INDIRECT_ACTION_LIST_TYPE_ERR;
14762 : : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
14763 : : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
14764 : : return MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT;
14765 : : default:
14766 : : break;
14767 : : }
14768 : : return MLX5_INDIRECT_ACTION_LIST_TYPE_ERR;
14769 : : }
14770 : :
14771 : : static struct rte_flow_action_list_handle*
14772 : 0 : mlx5_hw_decap_encap_handle_create(struct rte_eth_dev *dev,
14773 : : const struct mlx5_flow_template_table_cfg *table_cfg,
14774 : : const struct rte_flow_action *actions,
14775 : : struct rte_flow_error *error)
14776 : : {
14777 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14778 : : const struct rte_flow_attr *flow_attr = &table_cfg->attr.flow_attr;
14779 : : const struct rte_flow_action *encap = NULL;
14780 : : const struct rte_flow_action *decap = NULL;
14781 : 0 : struct rte_flow_indir_action_conf indirect_conf = {
14782 : 0 : .ingress = flow_attr->ingress,
14783 : 0 : .egress = flow_attr->egress,
14784 : 0 : .transfer = flow_attr->transfer,
14785 : : };
14786 : : struct mlx5_hw_encap_decap_action *handle;
14787 : : uint64_t action_flags = 0;
14788 : :
14789 : : /*
14790 : : * Allow
14791 : : * 1. raw_decap / raw_encap / end
14792 : : * 2. raw_encap / end
14793 : : * 3. raw_decap / end
14794 : : */
14795 [ # # ]: 0 : while (actions->type != RTE_FLOW_ACTION_TYPE_END) {
14796 [ # # ]: 0 : if (actions->type == RTE_FLOW_ACTION_TYPE_RAW_DECAP) {
14797 [ # # ]: 0 : if (action_flags) {
14798 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14799 : : actions, "Invalid indirect action list sequence");
14800 : 0 : return NULL;
14801 : : }
14802 : : action_flags |= MLX5_FLOW_ACTION_DECAP;
14803 : : decap = actions;
14804 [ # # ]: 0 : } else if (actions->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
14805 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_ENCAP) {
14806 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14807 : : actions, "Invalid indirect action list sequence");
14808 : 0 : return NULL;
14809 : : }
14810 : 0 : action_flags |= MLX5_FLOW_ACTION_ENCAP;
14811 : : encap = actions;
14812 : : } else {
14813 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14814 : : actions, "Invalid indirect action type in list");
14815 : 0 : return NULL;
14816 : : }
14817 : 0 : actions++;
14818 : : }
14819 [ # # ]: 0 : if (!decap && !encap) {
14820 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14821 : : actions, "Invalid indirect action combinations");
14822 : 0 : return NULL;
14823 : : }
14824 : 0 : handle = mlx5_reformat_action_create(dev, &indirect_conf, encap, decap, error);
14825 [ # # ]: 0 : if (!handle) {
14826 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14827 : : actions, "Failed to create HWS decap_encap action");
14828 : 0 : return NULL;
14829 : : }
14830 : 0 : handle->indirect.type = MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT;
14831 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->indirect_list_head, &handle->indirect, entry);
14832 : 0 : return (struct rte_flow_action_list_handle *)handle;
14833 : : }
14834 : :
14835 : : static struct rte_flow_action_list_handle *
14836 [ # # ]: 0 : flow_hw_async_action_list_handle_create(struct rte_eth_dev *dev, uint32_t queue,
14837 : : const struct rte_flow_op_attr *attr,
14838 : : const struct rte_flow_indir_action_conf *conf,
14839 : : const struct rte_flow_action *actions,
14840 : : void *user_data,
14841 : : struct rte_flow_error *error)
14842 : : {
14843 : : struct mlx5_hw_q_job *job = NULL;
14844 : : bool push = flow_hw_action_push(attr);
14845 : : enum mlx5_indirect_list_type list_type;
14846 : : struct rte_flow_action_list_handle *handle;
14847 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14848 : 0 : const struct mlx5_flow_template_table_cfg table_cfg = {
14849 : : .external = true,
14850 : : .attr = {
14851 : : .flow_attr = {
14852 : 0 : .ingress = conf->ingress,
14853 : 0 : .egress = conf->egress,
14854 : 0 : .transfer = conf->transfer
14855 : : }
14856 : : }
14857 : : };
14858 : :
14859 [ # # ]: 0 : if (!mlx5_hw_ctx_validate(dev, error))
14860 : : return NULL;
14861 [ # # ]: 0 : if (!actions) {
14862 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14863 : : NULL, "No action list");
14864 : 0 : return NULL;
14865 : : }
14866 : : list_type = flow_hw_inlist_type_get(actions);
14867 [ # # ]: 0 : if (list_type == MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY) {
14868 : : /*
14869 : : * Legacy indirect actions already have
14870 : : * async resources management. No need to do it twice.
14871 : : */
14872 : 0 : handle = mlx5_create_legacy_indlst(dev, queue, attr, conf,
14873 : : actions, user_data, error);
14874 : 0 : goto end;
14875 : : }
14876 [ # # ]: 0 : if (attr) {
14877 : : job = flow_hw_action_job_init(priv, queue, NULL, user_data,
14878 : : NULL, MLX5_HW_Q_JOB_TYPE_CREATE,
14879 : : MLX5_HW_INDIRECT_TYPE_LIST, error);
14880 : : if (!job)
14881 : 0 : return NULL;
14882 : : }
14883 [ # # # ]: 0 : switch (list_type) {
14884 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR:
14885 : 0 : handle = mlx5_hw_mirror_handle_create(dev, &table_cfg,
14886 : : actions, error);
14887 : 0 : break;
14888 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT:
14889 : 0 : handle = mlx5_hw_decap_encap_handle_create(dev, &table_cfg,
14890 : : actions, error);
14891 : 0 : break;
14892 : 0 : default:
14893 : : handle = NULL;
14894 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14895 : : actions, "Invalid list");
14896 : : }
14897 [ # # ]: 0 : if (job) {
14898 : 0 : job->action = handle;
14899 [ # # ]: 0 : flow_hw_action_finalize(dev, queue, job, push, false,
14900 : : handle != NULL);
14901 : : }
14902 : 0 : end:
14903 : : return handle;
14904 : : }
14905 : :
14906 : : static struct rte_flow_action_list_handle *
14907 : 0 : flow_hw_action_list_handle_create(struct rte_eth_dev *dev,
14908 : : const struct rte_flow_indir_action_conf *conf,
14909 : : const struct rte_flow_action *actions,
14910 : : struct rte_flow_error *error)
14911 : : {
14912 : 0 : return flow_hw_async_action_list_handle_create(dev, MLX5_HW_INV_QUEUE,
14913 : : NULL, conf, actions,
14914 : : NULL, error);
14915 : : }
14916 : :
14917 : : static int
14918 [ # # ]: 0 : flow_hw_async_action_list_handle_destroy
14919 : : (struct rte_eth_dev *dev, uint32_t queue,
14920 : : const struct rte_flow_op_attr *attr,
14921 : : struct rte_flow_action_list_handle *handle,
14922 : : void *user_data, struct rte_flow_error *error)
14923 : : {
14924 : : int ret = 0;
14925 : : struct mlx5_hw_q_job *job = NULL;
14926 : : bool push = flow_hw_action_push(attr);
14927 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
14928 : : enum mlx5_indirect_list_type type =
14929 : : mlx5_get_indirect_list_type((void *)handle);
14930 : :
14931 [ # # ]: 0 : if (type == MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY) {
14932 : : struct mlx5_indlst_legacy *legacy = (typeof(legacy))handle;
14933 : :
14934 : 0 : ret = flow_hw_action_handle_destroy(dev, queue, attr,
14935 : : legacy->handle,
14936 : : user_data, error);
14937 : : mlx5_indirect_list_remove_entry(&legacy->indirect);
14938 : 0 : goto end;
14939 : : }
14940 [ # # ]: 0 : if (attr) {
14941 : : job = flow_hw_action_job_init(priv, queue, NULL, user_data,
14942 : : NULL, MLX5_HW_Q_JOB_TYPE_DESTROY,
14943 : : MLX5_HW_INDIRECT_TYPE_LIST, error);
14944 : : if (!job)
14945 : 0 : return rte_errno;
14946 : : }
14947 [ # # # ]: 0 : switch (type) {
14948 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR:
14949 : 0 : mlx5_hw_mirror_destroy(dev, (struct mlx5_mirror *)handle);
14950 : 0 : break;
14951 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT:
14952 [ # # ]: 0 : LIST_REMOVE(&((struct mlx5_hw_encap_decap_action *)handle)->indirect,
14953 : : entry);
14954 : 0 : mlx5_reformat_action_destroy(dev, handle, error);
14955 : 0 : break;
14956 : 0 : default:
14957 : 0 : ret = rte_flow_error_set(error, EINVAL,
14958 : : RTE_FLOW_ERROR_TYPE_ACTION,
14959 : : NULL, "Invalid indirect list handle");
14960 : : }
14961 [ # # ]: 0 : if (job) {
14962 : : flow_hw_action_finalize(dev, queue, job, push, false, true);
14963 : : }
14964 : 0 : end:
14965 : : return ret;
14966 : : }
14967 : :
14968 : : static int
14969 : 0 : flow_hw_action_list_handle_destroy(struct rte_eth_dev *dev,
14970 : : struct rte_flow_action_list_handle *handle,
14971 : : struct rte_flow_error *error)
14972 : : {
14973 : 0 : return flow_hw_async_action_list_handle_destroy(dev, MLX5_HW_INV_QUEUE,
14974 : : NULL, handle, NULL,
14975 : : error);
14976 : : }
14977 : :
14978 : : static int
14979 [ # # ]: 0 : flow_hw_async_action_list_handle_query_update
14980 : : (struct rte_eth_dev *dev, uint32_t queue_id,
14981 : : const struct rte_flow_op_attr *attr,
14982 : : const struct rte_flow_action_list_handle *handle,
14983 : : const void **update, void **query,
14984 : : enum rte_flow_query_update_mode mode,
14985 : : void *user_data, struct rte_flow_error *error)
14986 : : {
14987 : : enum mlx5_indirect_list_type type =
14988 : : mlx5_get_indirect_list_type((const void *)handle);
14989 : :
14990 [ # # ]: 0 : if (type == MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY) {
14991 : : struct mlx5_indlst_legacy *legacy = (void *)(uintptr_t)handle;
14992 : :
14993 [ # # ]: 0 : if (update && query)
14994 : 0 : return flow_hw_async_action_handle_query_update
14995 : : (dev, queue_id, attr, legacy->handle,
14996 : : update, query, mode, user_data, error);
14997 [ # # # # ]: 0 : else if (update && update[0])
14998 : 0 : return flow_hw_action_handle_update(dev, queue_id, attr,
14999 : : legacy->handle, update[0],
15000 : : user_data, error);
15001 [ # # # # ]: 0 : else if (query && query[0])
15002 : 0 : return flow_hw_action_handle_query(dev, queue_id, attr,
15003 : 0 : legacy->handle, query[0],
15004 : : user_data, error);
15005 : : else
15006 : 0 : return rte_flow_error_set(error, EINVAL,
15007 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15008 : : NULL, "invalid legacy handle query_update parameters");
15009 : : }
15010 : : return -ENOTSUP;
15011 : : }
15012 : :
15013 : : static int
15014 : 0 : flow_hw_action_list_handle_query_update(struct rte_eth_dev *dev,
15015 : : const struct rte_flow_action_list_handle *handle,
15016 : : const void **update, void **query,
15017 : : enum rte_flow_query_update_mode mode,
15018 : : struct rte_flow_error *error)
15019 : : {
15020 : 0 : return flow_hw_async_action_list_handle_query_update
15021 : : (dev, MLX5_HW_INV_QUEUE, NULL, handle,
15022 : : update, query, mode, NULL, error);
15023 : : }
15024 : :
15025 : : static int
15026 : 0 : flow_hw_calc_table_hash(struct rte_eth_dev *dev,
15027 : : const struct rte_flow_template_table *table,
15028 : : const struct rte_flow_item pattern[],
15029 : : uint8_t pattern_template_index,
15030 : : uint32_t *hash, struct rte_flow_error *error)
15031 : : {
15032 : : const struct rte_flow_item *items;
15033 : : struct mlx5_flow_hw_pattern_params pp;
15034 : : int res;
15035 : :
15036 : 0 : items = flow_hw_get_rule_items(dev, table, pattern,
15037 : : pattern_template_index,
15038 : : &pp);
15039 : 0 : res = mlx5dr_rule_hash_calculate(mlx5_table_matcher(table), items,
15040 : : pattern_template_index,
15041 : : MLX5DR_RULE_HASH_CALC_MODE_RAW,
15042 : : hash);
15043 [ # # ]: 0 : if (res)
15044 : 0 : return rte_flow_error_set(error, res,
15045 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15046 : : NULL,
15047 : : "hash could not be calculated");
15048 : : return 0;
15049 : : }
15050 : :
15051 : : static int
15052 : 0 : flow_hw_calc_encap_hash(struct rte_eth_dev *dev,
15053 : : const struct rte_flow_item pattern[],
15054 : : enum rte_flow_encap_hash_field dest_field,
15055 : : uint8_t *hash,
15056 : : struct rte_flow_error *error)
15057 : : {
15058 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
15059 : : struct mlx5dr_crc_encap_entropy_hash_fields data;
15060 : 0 : enum mlx5dr_crc_encap_entropy_hash_size res_size =
15061 : : dest_field == RTE_FLOW_ENCAP_HASH_FIELD_SRC_PORT ?
15062 : 0 : MLX5DR_CRC_ENCAP_ENTROPY_HASH_SIZE_16 :
15063 : : MLX5DR_CRC_ENCAP_ENTROPY_HASH_SIZE_8;
15064 : : int res;
15065 : :
15066 : : memset(&data, 0, sizeof(struct mlx5dr_crc_encap_entropy_hash_fields));
15067 : :
15068 [ # # ]: 0 : for (; pattern->type != RTE_FLOW_ITEM_TYPE_END; pattern++) {
15069 [ # # # # : 0 : switch (pattern->type) {
# # # ]
15070 : 0 : case RTE_FLOW_ITEM_TYPE_IPV4:
15071 : 0 : data.dst.ipv4_addr =
15072 : 0 : ((const struct rte_flow_item_ipv4 *)(pattern->spec))->hdr.dst_addr;
15073 : 0 : data.src.ipv4_addr =
15074 : 0 : ((const struct rte_flow_item_ipv4 *)(pattern->spec))->hdr.src_addr;
15075 : 0 : break;
15076 : 0 : case RTE_FLOW_ITEM_TYPE_IPV6:
15077 : : memcpy(data.dst.ipv6_addr,
15078 : 0 : &((const struct rte_flow_item_ipv6 *)(pattern->spec))->hdr.dst_addr,
15079 : : sizeof(data.dst.ipv6_addr));
15080 : : memcpy(data.src.ipv6_addr,
15081 : : &((const struct rte_flow_item_ipv6 *)(pattern->spec))->hdr.src_addr,
15082 : : sizeof(data.src.ipv6_addr));
15083 : : break;
15084 : 0 : case RTE_FLOW_ITEM_TYPE_UDP:
15085 : 0 : data.next_protocol = IPPROTO_UDP;
15086 : 0 : data.dst_port =
15087 : 0 : ((const struct rte_flow_item_udp *)(pattern->spec))->hdr.dst_port;
15088 : 0 : data.src_port =
15089 : 0 : ((const struct rte_flow_item_udp *)(pattern->spec))->hdr.src_port;
15090 : 0 : break;
15091 : 0 : case RTE_FLOW_ITEM_TYPE_TCP:
15092 : 0 : data.next_protocol = IPPROTO_TCP;
15093 : 0 : data.dst_port =
15094 : 0 : ((const struct rte_flow_item_tcp *)(pattern->spec))->hdr.dst_port;
15095 : 0 : data.src_port =
15096 : 0 : ((const struct rte_flow_item_tcp *)(pattern->spec))->hdr.src_port;
15097 : 0 : break;
15098 : 0 : case RTE_FLOW_ITEM_TYPE_ICMP:
15099 : 0 : data.next_protocol = IPPROTO_ICMP;
15100 : 0 : break;
15101 : 0 : case RTE_FLOW_ITEM_TYPE_ICMP6:
15102 : 0 : data.next_protocol = IPPROTO_ICMPV6;
15103 : 0 : break;
15104 : : default:
15105 : : break;
15106 : : }
15107 : : }
15108 : 0 : res = mlx5dr_crc_encap_entropy_hash_calc(priv->dr_ctx, &data, hash, res_size);
15109 [ # # ]: 0 : if (res)
15110 : 0 : return rte_flow_error_set(error, res,
15111 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15112 : : NULL, "error while calculating encap hash");
15113 : : return 0;
15114 : : }
15115 : :
15116 : : static int
15117 : 0 : flow_hw_table_resize_multi_pattern_actions(struct rte_eth_dev *dev,
15118 : : struct rte_flow_template_table *table,
15119 : : uint32_t nb_flows,
15120 : : struct rte_flow_error *error)
15121 : : {
15122 : 0 : struct mlx5_multi_pattern_segment *segment = table->mpctx.segments;
15123 : : uint32_t bulk_size;
15124 : : int i, ret;
15125 : :
15126 : : /**
15127 : : * Segment always allocates Modify Header Argument Objects number in
15128 : : * powers of 2.
15129 : : * On resize, PMD adds minimal required argument objects number.
15130 : : * For example, if table size was 10, it allocated 16 argument objects.
15131 : : * Resize to 15 will not add new objects.
15132 : : */
15133 : 0 : for (i = 1;
15134 [ # # # # ]: 0 : i < MLX5_MAX_TABLE_RESIZE_NUM && segment->capacity;
15135 : 0 : i++, segment++) {
15136 : : /* keep the devtools/checkpatches.sh happy */
15137 : : }
15138 [ # # ]: 0 : if (i == MLX5_MAX_TABLE_RESIZE_NUM)
15139 : 0 : return rte_flow_error_set(error, EINVAL,
15140 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15141 : : table, "too many resizes");
15142 [ # # ]: 0 : if (segment->head_index - 1 >= nb_flows)
15143 : : return 0;
15144 [ # # ]: 0 : bulk_size = rte_align32pow2(nb_flows - segment->head_index + 1);
15145 : 0 : ret = mlx5_tbl_multi_pattern_process(dev, table, segment,
15146 : : rte_log2_u32(bulk_size),
15147 : : error);
15148 [ # # ]: 0 : if (ret)
15149 : 0 : return rte_flow_error_set(error, EINVAL,
15150 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15151 : : table, "too many resizes");
15152 : : return i;
15153 : : }
15154 : :
15155 : : static int
15156 : 0 : flow_hw_table_resize(struct rte_eth_dev *dev,
15157 : : struct rte_flow_template_table *table,
15158 : : uint32_t nb_flows,
15159 : : struct rte_flow_error *error)
15160 : : {
15161 : : struct mlx5dr_action_template *at[MLX5_HW_TBL_MAX_ACTION_TEMPLATE];
15162 : : struct mlx5dr_match_template *mt[MLX5_HW_TBL_MAX_ITEM_TEMPLATE];
15163 : 0 : struct mlx5dr_matcher_attr matcher_attr = table->matcher_attr;
15164 : 0 : struct mlx5dr_action_jump_to_matcher_attr jump_attr = {
15165 : : .type = MLX5DR_ACTION_JUMP_TO_MATCHER_BY_INDEX,
15166 : : .matcher = NULL,
15167 : : };
15168 : : struct mlx5_multi_pattern_segment *segment = NULL;
15169 : : struct mlx5dr_matcher *matcher = NULL;
15170 : : struct mlx5dr_action *jump = NULL;
15171 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
15172 : 0 : uint32_t i, selector = table->matcher_selector;
15173 : 0 : uint32_t other_selector = (selector + 1) & 1;
15174 : : int ret;
15175 : :
15176 [ # # ]: 0 : if (!rte_flow_template_table_resizable(dev->data->port_id, &table->cfg.attr))
15177 : 0 : return rte_flow_error_set(error, EINVAL,
15178 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15179 : : table, "no resizable attribute");
15180 [ # # ]: 0 : if (table->matcher_info[other_selector].matcher)
15181 : 0 : return rte_flow_error_set(error, EINVAL,
15182 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15183 : : table, "last table resize was not completed");
15184 [ # # ]: 0 : if (nb_flows <= table->cfg.attr.nb_flows)
15185 : 0 : return rte_flow_error_set(error, EINVAL,
15186 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15187 : : table, "shrinking table is not supported");
15188 : 0 : ret = mlx5_ipool_resize(table->flow, nb_flows, error);
15189 [ # # ]: 0 : if (ret)
15190 : : return ret;
15191 : : /*
15192 : : * A resizable matcher doesn't support rule update. In this case, the ipool
15193 : : * for the resource is not created and there is no need to resize it.
15194 : : */
15195 : : MLX5_ASSERT(!table->resource);
15196 [ # # ]: 0 : if (mlx5_is_multi_pattern_active(&table->mpctx)) {
15197 : 0 : ret = flow_hw_table_resize_multi_pattern_actions(dev, table, nb_flows, error);
15198 [ # # ]: 0 : if (ret < 0)
15199 : : return ret;
15200 [ # # ]: 0 : if (ret > 0)
15201 : 0 : segment = table->mpctx.segments + ret;
15202 : : }
15203 [ # # ]: 0 : for (i = 0; i < table->nb_item_templates; i++)
15204 : 0 : mt[i] = table->its[i]->mt;
15205 [ # # ]: 0 : for (i = 0; i < table->nb_action_templates; i++)
15206 : 0 : at[i] = table->ats[i].action_template->tmpl;
15207 : : nb_flows = rte_align32pow2(nb_flows);
15208 : 0 : matcher_attr.rule.num_log = rte_log2_u32(nb_flows);
15209 : 0 : matcher = mlx5dr_matcher_create(table->grp->tbl, mt,
15210 : : table->nb_item_templates, at,
15211 : : table->nb_action_templates,
15212 : : &matcher_attr);
15213 [ # # ]: 0 : if (!matcher) {
15214 : 0 : ret = rte_flow_error_set(error, rte_errno,
15215 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15216 : : table, "failed to create new matcher");
15217 : 0 : goto error;
15218 : : }
15219 [ # # ]: 0 : if (matcher_attr.isolated) {
15220 : 0 : jump_attr.matcher = matcher;
15221 : 0 : jump = mlx5dr_action_create_jump_to_matcher(priv->dr_ctx, &jump_attr,
15222 : 0 : mlx5_hw_act_flag[!!table->cfg.attr.flow_attr.group][table->type]);
15223 [ # # ]: 0 : if (!jump) {
15224 : 0 : ret = rte_flow_error_set(error, rte_errno,
15225 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15226 : : table, "failed to create jump to matcher action");
15227 : 0 : goto error;
15228 : : }
15229 : : }
15230 : 0 : rte_rwlock_write_lock(&table->matcher_replace_rwlk);
15231 : 0 : ret = mlx5dr_matcher_resize_set_target
15232 : : (table->matcher_info[selector].matcher, matcher);
15233 [ # # ]: 0 : if (ret) {
15234 : : rte_rwlock_write_unlock(&table->matcher_replace_rwlk);
15235 : 0 : ret = rte_flow_error_set(error, rte_errno,
15236 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15237 : : table, "failed to initiate matcher swap");
15238 : 0 : goto error;
15239 : : }
15240 : 0 : table->cfg.attr.nb_flows = nb_flows;
15241 : 0 : table->matcher_info[other_selector].matcher = matcher;
15242 : 0 : table->matcher_info[other_selector].jump = jump;
15243 : 0 : table->matcher_selector = other_selector;
15244 : 0 : rte_atomic_store_explicit(&table->matcher_info[other_selector].refcnt,
15245 : : 0, rte_memory_order_relaxed);
15246 : : rte_rwlock_write_unlock(&table->matcher_replace_rwlk);
15247 : 0 : return 0;
15248 : 0 : error:
15249 [ # # ]: 0 : if (segment)
15250 : 0 : mlx5_destroy_multi_pattern_segment(segment);
15251 [ # # ]: 0 : if (jump)
15252 : 0 : mlx5dr_action_destroy(jump);
15253 [ # # ]: 0 : if (matcher) {
15254 : 0 : ret = mlx5dr_matcher_destroy(matcher);
15255 : 0 : return rte_flow_error_set(error, rte_errno,
15256 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15257 : : table, "failed to destroy new matcher");
15258 : : }
15259 : : return ret;
15260 : : }
15261 : :
15262 : : static int
15263 : 0 : flow_hw_table_resize_complete(__rte_unused struct rte_eth_dev *dev,
15264 : : struct rte_flow_template_table *table,
15265 : : struct rte_flow_error *error)
15266 : : {
15267 : : int ret;
15268 : 0 : uint32_t selector = table->matcher_selector;
15269 : 0 : uint32_t other_selector = (selector + 1) & 1;
15270 : : struct mlx5_matcher_info *matcher_info = &table->matcher_info[other_selector];
15271 : : uint32_t matcher_refcnt;
15272 : :
15273 [ # # ]: 0 : if (!rte_flow_template_table_resizable(dev->data->port_id, &table->cfg.attr))
15274 : 0 : return rte_flow_error_set(error, EINVAL,
15275 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15276 : : table, "no resizable attribute");
15277 : 0 : matcher_refcnt = rte_atomic_load_explicit(&matcher_info->refcnt,
15278 : : rte_memory_order_relaxed);
15279 [ # # # # ]: 0 : if (!matcher_info->matcher || matcher_refcnt)
15280 : 0 : return rte_flow_error_set(error, EBUSY,
15281 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15282 : : table, "cannot complete table resize");
15283 [ # # ]: 0 : if (matcher_info->jump)
15284 : 0 : mlx5dr_action_destroy(matcher_info->jump);
15285 : 0 : ret = mlx5dr_matcher_destroy(matcher_info->matcher);
15286 [ # # ]: 0 : if (ret)
15287 : 0 : return rte_flow_error_set(error, rte_errno,
15288 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15289 : : table, "failed to destroy retired matcher");
15290 : 0 : matcher_info->matcher = NULL;
15291 : 0 : return 0;
15292 : : }
15293 : :
15294 : : static int
15295 : 0 : flow_hw_update_resized(struct rte_eth_dev *dev, uint32_t queue,
15296 : : const struct rte_flow_op_attr *attr,
15297 : : struct rte_flow *flow, void *user_data,
15298 : : struct rte_flow_error *error)
15299 : : {
15300 : : int ret;
15301 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
15302 : : struct rte_flow_hw *hw_flow = (struct rte_flow_hw *)flow;
15303 : 0 : struct rte_flow_template_table *table = hw_flow->table;
15304 : 0 : struct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(dev->data->port_id, hw_flow);
15305 : 0 : uint32_t table_selector = table->matcher_selector;
15306 : 0 : uint32_t rule_selector = aux->matcher_selector;
15307 : : uint32_t other_selector;
15308 : : struct mlx5dr_matcher *other_matcher;
15309 : 0 : struct mlx5dr_rule_attr rule_attr = {
15310 : : .queue_id = queue,
15311 : 0 : .burst = attr->postpone,
15312 : : };
15313 : :
15314 : : MLX5_ASSERT(hw_flow->flags & MLX5_FLOW_HW_FLOW_FLAG_MATCHER_SELECTOR);
15315 : : /**
15316 : : * mlx5dr_matcher_resize_rule_move() accepts original table matcher -
15317 : : * the one that was used BEFORE table resize.
15318 : : * Since the function is called AFTER table resize,
15319 : : * `table->matcher_selector` always points to the new matcher and
15320 : : * `aux->matcher_selector` points to a matcher used to create the flow.
15321 : : */
15322 : : other_selector = rule_selector == table_selector ?
15323 [ # # ]: 0 : (rule_selector + 1) & 1 : rule_selector;
15324 : 0 : other_matcher = table->matcher_info[other_selector].matcher;
15325 [ # # ]: 0 : if (!other_matcher)
15326 : 0 : return rte_flow_error_set(error, EINVAL,
15327 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
15328 : : "no active table resize");
15329 : 0 : hw_flow->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_MOVE;
15330 : 0 : hw_flow->user_data = user_data;
15331 : 0 : rule_attr.user_data = hw_flow;
15332 [ # # ]: 0 : if (rule_selector == table_selector) {
15333 : 0 : struct rte_ring *ring = !attr->postpone ?
15334 [ # # ]: 0 : priv->hw_q[queue].flow_transfer_completed :
15335 : 0 : priv->hw_q[queue].flow_transfer_pending;
15336 : 0 : rte_ring_enqueue(ring, hw_flow);
15337 : : flow_hw_q_inc_flow_ops(priv, queue);
15338 : 0 : return 0;
15339 : : }
15340 : 0 : ret = mlx5dr_matcher_resize_rule_move(other_matcher,
15341 : 0 : (struct mlx5dr_rule *)hw_flow->rule,
15342 : : &rule_attr);
15343 [ # # ]: 0 : if (ret) {
15344 : 0 : return rte_flow_error_set(error, rte_errno,
15345 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
15346 : : "flow transfer failed");
15347 : : }
15348 : : flow_hw_q_inc_flow_ops(priv, queue);
15349 : 0 : return 0;
15350 : : }
15351 : :
15352 : : /**
15353 : : * Internal validation function. For validating both actions and items.
15354 : : *
15355 : : * @param[in] dev
15356 : : * Pointer to the rte_eth_dev structure.
15357 : : * @param[in] attr
15358 : : * Pointer to the flow attributes.
15359 : : * @param[in] items
15360 : : * Pointer to the list of items.
15361 : : * @param[in] actions
15362 : : * Pointer to the list of actions.
15363 : : * @param[in] external
15364 : : * This flow rule is created by request external to PMD.
15365 : : * @param[in] hairpin
15366 : : * Number of hairpin TX actions, 0 means classic flow.
15367 : : * @param[out] error
15368 : : * Pointer to the error structure.
15369 : : *
15370 : : * @return
15371 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
15372 : : */
15373 : : static int
15374 : 0 : flow_hw_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
15375 : : const struct rte_flow_item items[],
15376 : : const struct rte_flow_action actions[] __rte_unused,
15377 : : bool external, int hairpin __rte_unused,
15378 : : struct rte_flow_error *error)
15379 : : {
15380 : 0 : const struct rte_flow_pattern_template_attr pattern_template_attr = {
15381 : : .relaxed_matching = 0,
15382 : 0 : .ingress = attr->ingress,
15383 : 0 : .egress = attr->egress,
15384 : 0 : .transfer = attr->transfer,
15385 : : };
15386 : 0 : uint64_t item_flags = 0;
15387 : : int ret = 0;
15388 : :
15389 [ # # ]: 0 : if (external) {
15390 : : /* Validate application items only */
15391 : 0 : ret = flow_hw_pattern_validate(dev, &pattern_template_attr, items,
15392 : : &item_flags, error);
15393 [ # # ]: 0 : if (ret < 0)
15394 : 0 : return -rte_errno;
15395 : : }
15396 : : return 0;
15397 : : }
15398 : :
15399 : : const struct mlx5_flow_driver_ops mlx5_flow_hw_drv_ops = {
15400 : : .list_create = flow_hw_list_create,
15401 : : .list_destroy = flow_hw_list_destroy,
15402 : : .validate = flow_hw_validate,
15403 : : .info_get = flow_hw_info_get,
15404 : : .configure = flow_hw_configure,
15405 : : .pattern_validate = flow_hw_pattern_validate,
15406 : : .pattern_template_create = flow_hw_pattern_template_create,
15407 : : .pattern_template_destroy = flow_hw_pattern_template_destroy,
15408 : : .actions_validate = flow_hw_actions_validate,
15409 : : .actions_template_create = flow_hw_actions_template_create,
15410 : : .actions_template_destroy = flow_hw_actions_template_destroy,
15411 : : .template_table_create = flow_hw_template_table_create,
15412 : : .template_table_destroy = flow_hw_table_destroy,
15413 : : .table_resize = flow_hw_table_resize,
15414 : : .group_set_miss_actions = flow_hw_group_set_miss_actions,
15415 : : .async_flow_create = flow_hw_async_flow_create,
15416 : : .async_flow_create_by_index = flow_hw_async_flow_create_by_index,
15417 : : .async_flow_update = flow_hw_async_flow_update,
15418 : : .async_flow_destroy = flow_hw_async_flow_destroy,
15419 : : .flow_update_resized = flow_hw_update_resized,
15420 : : .table_resize_complete = flow_hw_table_resize_complete,
15421 : : .pull = flow_hw_pull,
15422 : : .push = flow_hw_push,
15423 : : .async_action_create = flow_hw_action_handle_create,
15424 : : .async_action_destroy = flow_hw_action_handle_destroy,
15425 : : .async_action_update = flow_hw_action_handle_update,
15426 : : .async_action_query_update = flow_hw_async_action_handle_query_update,
15427 : : .async_action_query = flow_hw_action_handle_query,
15428 : : .action_validate = flow_hw_action_validate,
15429 : : .action_create = flow_hw_action_create,
15430 : : .action_destroy = flow_hw_action_destroy,
15431 : : .action_update = flow_hw_action_update,
15432 : : .action_query = flow_hw_action_query,
15433 : : .action_query_update = flow_hw_action_query_update,
15434 : : .action_list_handle_create = flow_hw_action_list_handle_create,
15435 : : .action_list_handle_destroy = flow_hw_action_list_handle_destroy,
15436 : : .action_list_handle_query_update =
15437 : : flow_hw_action_list_handle_query_update,
15438 : : .async_action_list_handle_create =
15439 : : flow_hw_async_action_list_handle_create,
15440 : : .async_action_list_handle_destroy =
15441 : : flow_hw_async_action_list_handle_destroy,
15442 : : .async_action_list_handle_query_update =
15443 : : flow_hw_async_action_list_handle_query_update,
15444 : : .query = flow_hw_query,
15445 : : .get_aged_flows = flow_hw_get_aged_flows,
15446 : : .get_q_aged_flows = flow_hw_get_q_aged_flows,
15447 : : .item_create = flow_dv_item_create,
15448 : : .item_release = flow_dv_item_release,
15449 : : .flow_calc_table_hash = flow_hw_calc_table_hash,
15450 : : .flow_calc_encap_hash = flow_hw_calc_encap_hash,
15451 : : };
15452 : :
15453 : : /**
15454 : : * Creates a control flow using flow template API on @p proxy_dev device,
15455 : : * on behalf of @p owner_dev device.
15456 : : *
15457 : : * This function uses locks internally to synchronize access to the
15458 : : * flow queue.
15459 : : *
15460 : : * Created flow is stored in private list associated with @p proxy_dev device.
15461 : : *
15462 : : * @param owner_dev
15463 : : * Pointer to Ethernet device on behalf of which flow is created.
15464 : : * @param proxy_dev
15465 : : * Pointer to Ethernet device on which flow is created.
15466 : : * @param table
15467 : : * Pointer to flow table.
15468 : : * @param items
15469 : : * Pointer to flow rule items.
15470 : : * @param item_template_idx
15471 : : * Index of an item template associated with @p table.
15472 : : * @param actions
15473 : : * Pointer to flow rule actions.
15474 : : * @param action_template_idx
15475 : : * Index of an action template associated with @p table.
15476 : : * @param info
15477 : : * Additional info about control flow rule.
15478 : : * @param external
15479 : : * External ctrl flow.
15480 : : *
15481 : : * @return
15482 : : * 0 on success, negative errno value otherwise and rte_errno set.
15483 : : */
15484 : : static __rte_unused int
15485 : 0 : flow_hw_create_ctrl_flow(struct rte_eth_dev *owner_dev,
15486 : : struct rte_eth_dev *proxy_dev,
15487 : : struct rte_flow_template_table *table,
15488 : : struct rte_flow_item items[],
15489 : : uint8_t item_template_idx,
15490 : : struct rte_flow_action actions[],
15491 : : uint8_t action_template_idx,
15492 : : struct mlx5_ctrl_flow_info *info,
15493 : : bool external)
15494 : : {
15495 : 0 : struct mlx5_priv *priv = proxy_dev->data->dev_private;
15496 : 0 : uint32_t queue = CTRL_QUEUE_ID(priv);
15497 : 0 : struct rte_flow_op_attr op_attr = {
15498 : : .postpone = 0,
15499 : : };
15500 : : struct rte_flow *flow = NULL;
15501 : : struct mlx5_ctrl_flow_entry *entry = NULL;
15502 : : int ret;
15503 : :
15504 : 0 : rte_spinlock_lock(&priv->hw_ctrl_lock);
15505 : 0 : entry = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_SYS, sizeof(*entry),
15506 : : 0, SOCKET_ID_ANY);
15507 [ # # ]: 0 : if (!entry) {
15508 : 0 : DRV_LOG(ERR, "port %u not enough memory to create control flows",
15509 : : proxy_dev->data->port_id);
15510 : 0 : rte_errno = ENOMEM;
15511 : : ret = -rte_errno;
15512 : 0 : goto error;
15513 : : }
15514 : 0 : flow = flow_hw_async_flow_create(proxy_dev, queue, &op_attr, table,
15515 : : items, item_template_idx,
15516 : : actions, action_template_idx,
15517 : : NULL, NULL);
15518 [ # # ]: 0 : if (!flow) {
15519 : 0 : DRV_LOG(ERR, "port %u failed to enqueue create control"
15520 : : " flow operation", proxy_dev->data->port_id);
15521 : 0 : ret = -rte_errno;
15522 : 0 : goto error;
15523 : : }
15524 : 0 : ret = __flow_hw_pull_comp(proxy_dev, queue, NULL);
15525 [ # # ]: 0 : if (ret) {
15526 : 0 : DRV_LOG(ERR, "port %u failed to insert control flow",
15527 : : proxy_dev->data->port_id);
15528 : 0 : rte_errno = EINVAL;
15529 : : ret = -rte_errno;
15530 : 0 : goto error;
15531 : : }
15532 : 0 : entry->owner_dev = owner_dev;
15533 : 0 : entry->flow = flow;
15534 [ # # ]: 0 : if (info)
15535 : 0 : entry->info = *info;
15536 : : else
15537 : 0 : entry->info.type = MLX5_CTRL_FLOW_TYPE_GENERAL;
15538 [ # # ]: 0 : if (external)
15539 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->hw_ext_ctrl_flows, entry, next);
15540 : : else
15541 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->hw_ctrl_flows, entry, next);
15542 : : rte_spinlock_unlock(&priv->hw_ctrl_lock);
15543 : 0 : return 0;
15544 : 0 : error:
15545 [ # # ]: 0 : if (entry)
15546 : 0 : mlx5_free(entry);
15547 : : rte_spinlock_unlock(&priv->hw_ctrl_lock);
15548 : 0 : return ret;
15549 : : }
15550 : :
15551 : : /**
15552 : : * Destroys a control flow @p flow using flow template API on @p dev device.
15553 : : *
15554 : : * This function uses locks internally to synchronize access to the
15555 : : * flow queue.
15556 : : *
15557 : : * If the @p flow is stored on any private list/pool, then caller must free up
15558 : : * the relevant resources.
15559 : : *
15560 : : * @param dev
15561 : : * Pointer to Ethernet device.
15562 : : * @param flow
15563 : : * Pointer to flow rule.
15564 : : *
15565 : : * @return
15566 : : * 0 on success, non-zero value otherwise.
15567 : : */
15568 : : static int
15569 : 0 : flow_hw_destroy_ctrl_flow(struct rte_eth_dev *dev, struct rte_flow *flow)
15570 : : {
15571 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
15572 : 0 : uint32_t queue = CTRL_QUEUE_ID(priv);
15573 : 0 : struct rte_flow_op_attr op_attr = {
15574 : : .postpone = 0,
15575 : : };
15576 : : int ret;
15577 : :
15578 : 0 : rte_spinlock_lock(&priv->hw_ctrl_lock);
15579 : 0 : ret = flow_hw_async_flow_destroy(dev, queue, &op_attr, flow, NULL, NULL);
15580 [ # # ]: 0 : if (ret) {
15581 : 0 : DRV_LOG(ERR, "port %u failed to enqueue destroy control"
15582 : : " flow operation", dev->data->port_id);
15583 : 0 : goto exit;
15584 : : }
15585 : 0 : ret = __flow_hw_pull_comp(dev, queue, NULL);
15586 [ # # ]: 0 : if (ret) {
15587 : 0 : DRV_LOG(ERR, "port %u failed to destroy control flow",
15588 : : dev->data->port_id);
15589 : 0 : rte_errno = EINVAL;
15590 : : ret = -rte_errno;
15591 : 0 : goto exit;
15592 : : }
15593 : 0 : exit:
15594 : : rte_spinlock_unlock(&priv->hw_ctrl_lock);
15595 : 0 : return ret;
15596 : : }
15597 : :
15598 : : /**
15599 : : * Destroys control flows created on behalf of @p owner device on @p dev device.
15600 : : *
15601 : : * @param dev
15602 : : * Pointer to Ethernet device on which control flows were created.
15603 : : * @param owner
15604 : : * Pointer to Ethernet device owning control flows.
15605 : : *
15606 : : * @return
15607 : : * 0 on success, otherwise negative error code is returned and
15608 : : * rte_errno is set.
15609 : : */
15610 : : static int
15611 : 0 : flow_hw_flush_ctrl_flows_owned_by(struct rte_eth_dev *dev, struct rte_eth_dev *owner)
15612 : : {
15613 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
15614 : : struct mlx5_ctrl_flow_entry *cf;
15615 : : struct mlx5_ctrl_flow_entry *cf_next;
15616 : : int ret;
15617 : :
15618 : 0 : cf = LIST_FIRST(&priv->hw_ctrl_flows);
15619 [ # # ]: 0 : while (cf != NULL) {
15620 : 0 : cf_next = LIST_NEXT(cf, next);
15621 [ # # ]: 0 : if (cf->owner_dev == owner) {
15622 : 0 : ret = flow_hw_destroy_ctrl_flow(dev, cf->flow);
15623 [ # # ]: 0 : if (ret) {
15624 : 0 : rte_errno = ret;
15625 : 0 : return -ret;
15626 : : }
15627 [ # # ]: 0 : LIST_REMOVE(cf, next);
15628 : 0 : mlx5_free(cf);
15629 : : }
15630 : : cf = cf_next;
15631 : : }
15632 : : return 0;
15633 : : }
15634 : :
15635 : : /**
15636 : : * Destroys control flows created for @p owner_dev device.
15637 : : *
15638 : : * @param owner_dev
15639 : : * Pointer to Ethernet device owning control flows.
15640 : : *
15641 : : * @return
15642 : : * 0 on success, otherwise negative error code is returned and
15643 : : * rte_errno is set.
15644 : : */
15645 : : int
15646 : 0 : mlx5_flow_hw_flush_ctrl_flows(struct rte_eth_dev *owner_dev)
15647 : : {
15648 : 0 : struct mlx5_priv *owner_priv = owner_dev->data->dev_private;
15649 : : struct rte_eth_dev *proxy_dev;
15650 : 0 : uint16_t owner_port_id = owner_dev->data->port_id;
15651 : 0 : uint16_t proxy_port_id = owner_dev->data->port_id;
15652 : : int ret;
15653 : :
15654 : : /* Flush all flows created by this port for itself. */
15655 : 0 : ret = flow_hw_flush_ctrl_flows_owned_by(owner_dev, owner_dev);
15656 [ # # ]: 0 : if (ret)
15657 : : return ret;
15658 : : /* Flush all flows created for this port on proxy port. */
15659 [ # # ]: 0 : if (owner_priv->sh->config.dv_esw_en) {
15660 : 0 : ret = rte_flow_pick_transfer_proxy(owner_port_id, &proxy_port_id, NULL);
15661 [ # # ]: 0 : if (ret == -ENODEV) {
15662 : 0 : DRV_LOG(DEBUG, "Unable to find transfer proxy port for port %u. It was "
15663 : : "probably closed. Control flows were cleared.",
15664 : : owner_port_id);
15665 : 0 : rte_errno = 0;
15666 : 0 : return 0;
15667 [ # # ]: 0 : } else if (ret) {
15668 : 0 : DRV_LOG(ERR, "Unable to find proxy port for port %u (ret = %d)",
15669 : : owner_port_id, ret);
15670 : 0 : return ret;
15671 : : }
15672 : 0 : proxy_dev = &rte_eth_devices[proxy_port_id];
15673 : : } else {
15674 : : proxy_dev = owner_dev;
15675 : : }
15676 : 0 : return flow_hw_flush_ctrl_flows_owned_by(proxy_dev, owner_dev);
15677 : : }
15678 : :
15679 : : /**
15680 : : * Destroys all control flows created on @p dev device.
15681 : : *
15682 : : * @param owner_dev
15683 : : * Pointer to Ethernet device.
15684 : : *
15685 : : * @return
15686 : : * 0 on success, otherwise negative error code is returned and
15687 : : * rte_errno is set.
15688 : : */
15689 : : static int
15690 : 0 : flow_hw_flush_all_ctrl_flows(struct rte_eth_dev *dev)
15691 : : {
15692 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
15693 : : struct mlx5_ctrl_flow_entry *cf;
15694 : : struct mlx5_ctrl_flow_entry *cf_next;
15695 : : int ret;
15696 : :
15697 : 0 : cf = LIST_FIRST(&priv->hw_ctrl_flows);
15698 [ # # ]: 0 : while (cf != NULL) {
15699 : 0 : cf_next = LIST_NEXT(cf, next);
15700 : 0 : ret = flow_hw_destroy_ctrl_flow(dev, cf->flow);
15701 [ # # ]: 0 : if (ret) {
15702 : 0 : rte_errno = ret;
15703 : 0 : return -ret;
15704 : : }
15705 [ # # ]: 0 : LIST_REMOVE(cf, next);
15706 : 0 : mlx5_free(cf);
15707 : : cf = cf_next;
15708 : : }
15709 : 0 : cf = LIST_FIRST(&priv->hw_ext_ctrl_flows);
15710 [ # # ]: 0 : while (cf != NULL) {
15711 : 0 : cf_next = LIST_NEXT(cf, next);
15712 : 0 : ret = flow_hw_destroy_ctrl_flow(dev, cf->flow);
15713 [ # # ]: 0 : if (ret) {
15714 : 0 : rte_errno = ret;
15715 : 0 : return -ret;
15716 : : }
15717 [ # # ]: 0 : LIST_REMOVE(cf, next);
15718 : 0 : mlx5_free(cf);
15719 : : cf = cf_next;
15720 : : }
15721 : : return 0;
15722 : : }
15723 : :
15724 : : int
15725 : 0 : mlx5_flow_hw_esw_create_sq_miss_flow(struct rte_eth_dev *dev, uint32_t sqn, bool external)
15726 : : {
15727 : 0 : uint16_t port_id = dev->data->port_id;
15728 : 0 : struct rte_flow_item_ethdev esw_mgr_spec = {
15729 : : .port_id = MLX5_REPRESENTED_PORT_ESW_MGR,
15730 : : };
15731 : 0 : struct rte_flow_item_ethdev esw_mgr_mask = {
15732 : : .port_id = MLX5_REPRESENTED_PORT_ESW_MGR,
15733 : : };
15734 : 0 : struct rte_flow_item_tag reg_c0_spec = {
15735 : : .index = (uint8_t)REG_C_0,
15736 : : .data = flow_hw_esw_mgr_regc_marker(dev),
15737 : : };
15738 : 0 : struct rte_flow_item_tag reg_c0_mask = {
15739 : : .index = 0xff,
15740 : : .data = flow_hw_esw_mgr_regc_marker_mask(dev),
15741 : : };
15742 : 0 : struct mlx5_rte_flow_item_sq sq_spec = {
15743 : : .queue = sqn,
15744 : : };
15745 : 0 : struct rte_flow_action_ethdev port = {
15746 : : .port_id = port_id,
15747 : : };
15748 : 0 : struct rte_flow_item items[3] = { { 0 } };
15749 : 0 : struct rte_flow_action actions[3] = { { 0 } };
15750 : 0 : struct mlx5_ctrl_flow_info flow_info = {
15751 : : .type = MLX5_CTRL_FLOW_TYPE_SQ_MISS_ROOT,
15752 : : .esw_mgr_sq = sqn,
15753 : : };
15754 : : struct rte_eth_dev *proxy_dev;
15755 : : struct mlx5_priv *proxy_priv;
15756 : 0 : uint16_t proxy_port_id = dev->data->port_id;
15757 : : int ret;
15758 : :
15759 : 0 : ret = rte_flow_pick_transfer_proxy(port_id, &proxy_port_id, NULL);
15760 [ # # ]: 0 : if (ret) {
15761 : 0 : DRV_LOG(ERR, "Unable to pick transfer proxy port for port %u. Transfer proxy "
15762 : : "port must be present to create default SQ miss flows.",
15763 : : port_id);
15764 : 0 : return ret;
15765 : : }
15766 : 0 : proxy_dev = &rte_eth_devices[proxy_port_id];
15767 : 0 : proxy_priv = proxy_dev->data->dev_private;
15768 [ # # ]: 0 : if (!proxy_priv->dr_ctx) {
15769 : 0 : DRV_LOG(DEBUG, "Transfer proxy port (port %u) of port %u must be configured "
15770 : : "for HWS to create default SQ miss flows. Default flows will "
15771 : : "not be created.",
15772 : : proxy_port_id, port_id);
15773 : 0 : return 0;
15774 : : }
15775 [ # # ]: 0 : if (!proxy_priv->hw_ctrl_fdb ||
15776 [ # # ]: 0 : !proxy_priv->hw_ctrl_fdb->hw_esw_sq_miss_root_tbl ||
15777 [ # # ]: 0 : !proxy_priv->hw_ctrl_fdb->hw_esw_sq_miss_tbl) {
15778 : 0 : DRV_LOG(ERR, "Transfer proxy port (port %u) of port %u was configured, but "
15779 : : "default flow tables were not created.",
15780 : : proxy_port_id, port_id);
15781 : 0 : rte_errno = ENOMEM;
15782 : 0 : return -rte_errno;
15783 : : }
15784 : : /*
15785 : : * Create a root SQ miss flow rule - match E-Switch Manager and SQ,
15786 : : * and jump to group 1.
15787 : : */
15788 : 0 : items[0] = (struct rte_flow_item){
15789 : : .type = RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT,
15790 : : .spec = &esw_mgr_spec,
15791 : : .mask = &esw_mgr_mask,
15792 : : };
15793 : 0 : items[1] = (struct rte_flow_item){
15794 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_SQ,
15795 : : .spec = &sq_spec,
15796 : : };
15797 : 0 : items[2] = (struct rte_flow_item){
15798 : : .type = RTE_FLOW_ITEM_TYPE_END,
15799 : : };
15800 : 0 : actions[0] = (struct rte_flow_action){
15801 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
15802 : : };
15803 : 0 : actions[1] = (struct rte_flow_action){
15804 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
15805 : : };
15806 : 0 : actions[2] = (struct rte_flow_action) {
15807 : : .type = RTE_FLOW_ACTION_TYPE_END,
15808 : : };
15809 : 0 : ret = flow_hw_create_ctrl_flow(dev, proxy_dev,
15810 : : proxy_priv->hw_ctrl_fdb->hw_esw_sq_miss_root_tbl,
15811 : : items, 0, actions, 0, &flow_info, external);
15812 [ # # ]: 0 : if (ret) {
15813 : 0 : DRV_LOG(ERR, "Port %u failed to create root SQ miss flow rule for SQ %u, ret %d",
15814 : : port_id, sqn, ret);
15815 : 0 : return ret;
15816 : : }
15817 : : /*
15818 : : * Create a non-root SQ miss flow rule - match REG_C_0 marker and SQ,
15819 : : * and forward to port.
15820 : : */
15821 : 0 : items[0] = (struct rte_flow_item){
15822 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_TAG,
15823 : : .spec = ®_c0_spec,
15824 : : .mask = ®_c0_mask,
15825 : : };
15826 : 0 : items[1] = (struct rte_flow_item){
15827 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_SQ,
15828 : : .spec = &sq_spec,
15829 : : };
15830 : 0 : items[2] = (struct rte_flow_item){
15831 : : .type = RTE_FLOW_ITEM_TYPE_END,
15832 : : };
15833 : 0 : actions[0] = (struct rte_flow_action){
15834 : : .type = RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT,
15835 : : .conf = &port,
15836 : : };
15837 : 0 : actions[1] = (struct rte_flow_action){
15838 : : .type = RTE_FLOW_ACTION_TYPE_END,
15839 : : };
15840 : 0 : flow_info.type = MLX5_CTRL_FLOW_TYPE_SQ_MISS;
15841 : 0 : ret = flow_hw_create_ctrl_flow(dev, proxy_dev,
15842 : 0 : proxy_priv->hw_ctrl_fdb->hw_esw_sq_miss_tbl,
15843 : : items, 0, actions, 0, &flow_info, external);
15844 [ # # ]: 0 : if (ret) {
15845 : 0 : DRV_LOG(ERR, "Port %u failed to create HWS SQ miss flow rule for SQ %u, ret %d",
15846 : : port_id, sqn, ret);
15847 : 0 : return ret;
15848 : : }
15849 : : return 0;
15850 : : }
15851 : :
15852 : : static bool
15853 : : flow_hw_is_matching_sq_miss_flow(struct mlx5_ctrl_flow_entry *cf,
15854 : : struct rte_eth_dev *dev,
15855 : : uint32_t sqn)
15856 : : {
15857 : 0 : if (cf->owner_dev != dev)
15858 : : return false;
15859 [ # # # # ]: 0 : if (cf->info.type == MLX5_CTRL_FLOW_TYPE_SQ_MISS_ROOT && cf->info.esw_mgr_sq == sqn)
15860 : : return true;
15861 [ # # # # ]: 0 : if (cf->info.type == MLX5_CTRL_FLOW_TYPE_SQ_MISS && cf->info.esw_mgr_sq == sqn)
15862 : : return true;
15863 : : return false;
15864 : : }
15865 : :
15866 : : int
15867 : 0 : mlx5_flow_hw_esw_destroy_sq_miss_flow(struct rte_eth_dev *dev, uint32_t sqn)
15868 : : {
15869 : 0 : uint16_t port_id = dev->data->port_id;
15870 : 0 : uint16_t proxy_port_id = dev->data->port_id;
15871 : : struct rte_eth_dev *proxy_dev;
15872 : : struct mlx5_priv *proxy_priv;
15873 : : struct mlx5_ctrl_flow_entry *cf;
15874 : : struct mlx5_ctrl_flow_entry *cf_next;
15875 : : int ret;
15876 : :
15877 : 0 : ret = rte_flow_pick_transfer_proxy(port_id, &proxy_port_id, NULL);
15878 [ # # ]: 0 : if (ret) {
15879 : 0 : DRV_LOG(ERR, "Unable to pick transfer proxy port for port %u. Transfer proxy "
15880 : : "port must be present for default SQ miss flow rules to exist.",
15881 : : port_id);
15882 : 0 : return ret;
15883 : : }
15884 : 0 : proxy_dev = &rte_eth_devices[proxy_port_id];
15885 : 0 : proxy_priv = proxy_dev->data->dev_private;
15886 : : /* FDB default flow rules must be enabled. */
15887 : : MLX5_ASSERT(proxy_priv->sh->config.fdb_def_rule);
15888 [ # # ]: 0 : if (!proxy_priv->dr_ctx)
15889 : : return 0;
15890 [ # # ]: 0 : if (!proxy_priv->hw_ctrl_fdb ||
15891 [ # # ]: 0 : !proxy_priv->hw_ctrl_fdb->hw_esw_sq_miss_root_tbl ||
15892 [ # # ]: 0 : !proxy_priv->hw_ctrl_fdb->hw_esw_sq_miss_tbl)
15893 : : return 0;
15894 : 0 : cf = LIST_FIRST(&proxy_priv->hw_ctrl_flows);
15895 [ # # ]: 0 : while (cf != NULL) {
15896 [ # # ]: 0 : cf_next = LIST_NEXT(cf, next);
15897 : : if (flow_hw_is_matching_sq_miss_flow(cf, dev, sqn)) {
15898 : 0 : claim_zero(flow_hw_destroy_ctrl_flow(proxy_dev, cf->flow));
15899 [ # # ]: 0 : LIST_REMOVE(cf, next);
15900 : 0 : mlx5_free(cf);
15901 : : }
15902 : : cf = cf_next;
15903 : : }
15904 : : return 0;
15905 : : }
15906 : :
15907 : : int
15908 : 0 : mlx5_flow_hw_esw_create_default_jump_flow(struct rte_eth_dev *dev)
15909 : : {
15910 : 0 : uint16_t port_id = dev->data->port_id;
15911 : 0 : struct rte_flow_item_ethdev port_spec = {
15912 : : .port_id = port_id,
15913 : : };
15914 : 0 : struct rte_flow_item items[] = {
15915 : : {
15916 : : .type = RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT,
15917 : : .spec = &port_spec,
15918 : : },
15919 : : {
15920 : : .type = RTE_FLOW_ITEM_TYPE_END,
15921 : : },
15922 : : };
15923 : 0 : struct rte_flow_action_jump jump = {
15924 : : .group = 1,
15925 : : };
15926 : 0 : struct rte_flow_action actions[] = {
15927 : : {
15928 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
15929 : : .conf = &jump,
15930 : : },
15931 : : {
15932 : : .type = RTE_FLOW_ACTION_TYPE_END,
15933 : : }
15934 : : };
15935 : 0 : struct mlx5_ctrl_flow_info flow_info = {
15936 : : .type = MLX5_CTRL_FLOW_TYPE_DEFAULT_JUMP,
15937 : : };
15938 : : struct rte_eth_dev *proxy_dev;
15939 : : struct mlx5_priv *proxy_priv;
15940 : 0 : uint16_t proxy_port_id = dev->data->port_id;
15941 : : int ret;
15942 : :
15943 : 0 : ret = rte_flow_pick_transfer_proxy(port_id, &proxy_port_id, NULL);
15944 [ # # ]: 0 : if (ret) {
15945 : 0 : DRV_LOG(ERR, "Unable to pick transfer proxy port for port %u. Transfer proxy "
15946 : : "port must be present to create default FDB jump rule.",
15947 : : port_id);
15948 : 0 : return ret;
15949 : : }
15950 : 0 : proxy_dev = &rte_eth_devices[proxy_port_id];
15951 : 0 : proxy_priv = proxy_dev->data->dev_private;
15952 : : /* FDB default flow rules must be enabled. */
15953 : : MLX5_ASSERT(proxy_priv->sh->config.fdb_def_rule);
15954 [ # # ]: 0 : if (!proxy_priv->dr_ctx) {
15955 : 0 : DRV_LOG(DEBUG, "Transfer proxy port (port %u) of port %u must be configured "
15956 : : "for HWS to create default FDB jump rule. Default rule will "
15957 : : "not be created.",
15958 : : proxy_port_id, port_id);
15959 : 0 : return 0;
15960 : : }
15961 [ # # # # ]: 0 : if (!proxy_priv->hw_ctrl_fdb || !proxy_priv->hw_ctrl_fdb->hw_esw_zero_tbl) {
15962 : 0 : DRV_LOG(ERR, "Transfer proxy port (port %u) of port %u was configured, but "
15963 : : "default flow tables were not created.",
15964 : : proxy_port_id, port_id);
15965 : 0 : rte_errno = EINVAL;
15966 : 0 : return -rte_errno;
15967 : : }
15968 : 0 : return flow_hw_create_ctrl_flow(dev, proxy_dev,
15969 : : proxy_priv->hw_ctrl_fdb->hw_esw_zero_tbl,
15970 : : items, 0, actions, 0, &flow_info, false);
15971 : : }
15972 : :
15973 : : int
15974 : 0 : mlx5_flow_hw_create_tx_default_mreg_copy_flow(struct rte_eth_dev *dev)
15975 : : {
15976 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
15977 : 0 : struct rte_flow_item_eth promisc = {
15978 : : .hdr.dst_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
15979 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
15980 : : .hdr.ether_type = 0,
15981 : : };
15982 : 0 : struct rte_flow_item eth_all[] = {
15983 : : [0] = {
15984 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
15985 : : .spec = &promisc,
15986 : : .mask = &promisc,
15987 : : },
15988 : : [1] = {
15989 : : .type = RTE_FLOW_ITEM_TYPE_END,
15990 : : },
15991 : : };
15992 : 0 : struct rte_flow_action_modify_field mreg_action = {
15993 : : .operation = RTE_FLOW_MODIFY_SET,
15994 : : .dst = {
15995 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
15996 : : .tag_index = REG_C_1,
15997 : : },
15998 : : .src = {
15999 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
16000 : : .tag_index = REG_A,
16001 : : },
16002 : : .width = 32,
16003 : : };
16004 : 0 : struct rte_flow_action copy_reg_action[] = {
16005 : : [0] = {
16006 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
16007 : : .conf = &mreg_action,
16008 : : },
16009 : : [1] = {
16010 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
16011 : : },
16012 : : [2] = {
16013 : : .type = RTE_FLOW_ACTION_TYPE_END,
16014 : : },
16015 : : };
16016 : 0 : struct mlx5_ctrl_flow_info flow_info = {
16017 : : .type = MLX5_CTRL_FLOW_TYPE_TX_META_COPY,
16018 : : };
16019 : :
16020 : : MLX5_ASSERT(priv->master);
16021 [ # # ]: 0 : if (!priv->dr_ctx ||
16022 [ # # ]: 0 : !priv->hw_ctrl_fdb ||
16023 [ # # ]: 0 : !priv->hw_ctrl_fdb->hw_tx_meta_cpy_tbl)
16024 : : return 0;
16025 : 0 : return flow_hw_create_ctrl_flow(dev, dev,
16026 : : priv->hw_ctrl_fdb->hw_tx_meta_cpy_tbl,
16027 : : eth_all, 0, copy_reg_action, 0, &flow_info, false);
16028 : : }
16029 : :
16030 : : int
16031 : 0 : mlx5_flow_hw_tx_repr_matching_flow(struct rte_eth_dev *dev, uint32_t sqn, bool external)
16032 : : {
16033 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16034 : 0 : struct mlx5_rte_flow_item_sq sq_spec = {
16035 : : .queue = sqn,
16036 : : };
16037 : 0 : struct rte_flow_item items[] = {
16038 : : {
16039 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_SQ,
16040 : : .spec = &sq_spec,
16041 : : },
16042 : : {
16043 : : .type = RTE_FLOW_ITEM_TYPE_END,
16044 : : },
16045 : : };
16046 : : /*
16047 : : * Allocate actions array suitable for all cases - extended metadata enabled or not.
16048 : : * With extended metadata there will be an additional MODIFY_FIELD action before JUMP.
16049 : : */
16050 : 0 : struct rte_flow_action actions[] = {
16051 : : { .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD },
16052 : : { .type = RTE_FLOW_ACTION_TYPE_JUMP },
16053 : : { .type = RTE_FLOW_ACTION_TYPE_END },
16054 : : { .type = RTE_FLOW_ACTION_TYPE_END },
16055 : : };
16056 : 0 : struct mlx5_ctrl_flow_info flow_info = {
16057 : : .type = MLX5_CTRL_FLOW_TYPE_TX_REPR_MATCH,
16058 : : .tx_repr_sq = sqn,
16059 : : };
16060 : :
16061 : : /* It is assumed that caller checked for representor matching. */
16062 : : MLX5_ASSERT(priv->sh->config.repr_matching);
16063 [ # # ]: 0 : if (!priv->dr_ctx) {
16064 : 0 : DRV_LOG(DEBUG, "Port %u must be configured for HWS, before creating "
16065 : : "default egress flow rules. Omitting creation.",
16066 : : dev->data->port_id);
16067 : 0 : return 0;
16068 : : }
16069 [ # # ]: 0 : if (!priv->hw_tx_repr_tagging_tbl) {
16070 : 0 : DRV_LOG(ERR, "Port %u is configured for HWS, but table for default "
16071 : : "egress flow rules does not exist.",
16072 : : dev->data->port_id);
16073 : 0 : rte_errno = EINVAL;
16074 : 0 : return -rte_errno;
16075 : : }
16076 : : /*
16077 : : * If extended metadata mode is enabled, then an additional MODIFY_FIELD action must be
16078 : : * placed before terminating JUMP action.
16079 : : */
16080 [ # # ]: 0 : if (priv->sh->config.dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS) {
16081 : 0 : actions[1].type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD;
16082 : 0 : actions[2].type = RTE_FLOW_ACTION_TYPE_JUMP;
16083 : : }
16084 : 0 : return flow_hw_create_ctrl_flow(dev, dev, priv->hw_tx_repr_tagging_tbl,
16085 : : items, 0, actions, 0, &flow_info, external);
16086 : : }
16087 : :
16088 : : int
16089 : 0 : mlx5_flow_hw_lacp_rx_flow(struct rte_eth_dev *dev)
16090 : : {
16091 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16092 : 0 : struct rte_flow_item_eth lacp_item = {
16093 : : .type = RTE_BE16(RTE_ETHER_TYPE_SLOW),
16094 : : };
16095 : 0 : struct rte_flow_item eth_lacp[] = {
16096 : : [0] = {
16097 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
16098 : : .spec = &lacp_item,
16099 : : .mask = &lacp_item,
16100 : : },
16101 : : [1] = {
16102 : : .type = RTE_FLOW_ITEM_TYPE_END,
16103 : : },
16104 : : };
16105 : 0 : struct rte_flow_action miss_action[] = {
16106 : : [0] = {
16107 : : .type = (enum rte_flow_action_type)
16108 : : MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS,
16109 : : },
16110 : : [1] = {
16111 : : .type = RTE_FLOW_ACTION_TYPE_END,
16112 : : },
16113 : : };
16114 : 0 : struct mlx5_ctrl_flow_info flow_info = {
16115 : : .type = MLX5_CTRL_FLOW_TYPE_LACP_RX,
16116 : : };
16117 : :
16118 [ # # # # : 0 : if (!priv->dr_ctx || !priv->hw_ctrl_fdb || !priv->hw_ctrl_fdb->hw_lacp_rx_tbl)
# # ]
16119 : : return 0;
16120 : 0 : return flow_hw_create_ctrl_flow(dev, dev,
16121 : : priv->hw_ctrl_fdb->hw_lacp_rx_tbl,
16122 : : eth_lacp, 0, miss_action, 0, &flow_info, false);
16123 : : }
16124 : :
16125 : : static uint32_t
16126 : : __calc_pattern_flags(const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type)
16127 : : {
16128 : : switch (eth_pattern_type) {
16129 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL:
16130 : : return MLX5_CTRL_PROMISCUOUS;
16131 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL_MCAST:
16132 : : return MLX5_CTRL_ALL_MULTICAST;
16133 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST:
16134 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST_VLAN:
16135 : : return MLX5_CTRL_BROADCAST;
16136 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST:
16137 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST_VLAN:
16138 : : return MLX5_CTRL_IPV4_MULTICAST;
16139 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST:
16140 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST_VLAN:
16141 : : return MLX5_CTRL_IPV6_MULTICAST;
16142 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC:
16143 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN:
16144 : : return MLX5_CTRL_DMAC;
16145 : : default:
16146 : : /* Should not reach here. */
16147 : : MLX5_ASSERT(false);
16148 : : return 0;
16149 : : }
16150 : : }
16151 : :
16152 : : static uint32_t
16153 : : __calc_vlan_flags(const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type)
16154 : : {
16155 [ # # ]: 0 : switch (eth_pattern_type) {
16156 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST_VLAN:
16157 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST_VLAN:
16158 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST_VLAN:
16159 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN:
16160 : : return MLX5_CTRL_VLAN_FILTER;
16161 : 0 : default:
16162 : 0 : return 0;
16163 : : }
16164 : : }
16165 : :
16166 : : static bool
16167 [ # # ]: 0 : eth_pattern_type_is_requested(const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type,
16168 : : uint32_t flags)
16169 : : {
16170 : : uint32_t pattern_flags = __calc_pattern_flags(eth_pattern_type);
16171 : : uint32_t vlan_flags = __calc_vlan_flags(eth_pattern_type);
16172 : 0 : bool pattern_requested = !!(pattern_flags & flags);
16173 [ # # # # ]: 0 : bool consider_vlan = vlan_flags || (MLX5_CTRL_VLAN_FILTER & flags);
16174 : 0 : bool vlan_requested = !!(vlan_flags & flags);
16175 : :
16176 [ # # ]: 0 : if (consider_vlan)
16177 : 0 : return pattern_requested && vlan_requested;
16178 : : else
16179 : : return pattern_requested;
16180 : : }
16181 : :
16182 : : static bool
16183 : : rss_type_is_requested(struct mlx5_priv *priv,
16184 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
16185 : : {
16186 : 0 : struct rte_flow_actions_template *at = priv->hw_ctrl_rx->rss[rss_type];
16187 : : unsigned int i;
16188 : :
16189 [ # # # # ]: 0 : for (i = 0; at->actions[i].type != RTE_FLOW_ACTION_TYPE_END; ++i) {
16190 [ # # # # ]: 0 : if (at->actions[i].type == RTE_FLOW_ACTION_TYPE_RSS) {
16191 : 0 : const struct rte_flow_action_rss *rss = at->actions[i].conf;
16192 : 0 : uint64_t rss_types = rss->types;
16193 : :
16194 [ # # # # ]: 0 : if ((rss_types & priv->rss_conf.rss_hf) != rss_types)
16195 : : return false;
16196 : : }
16197 : : }
16198 : : return true;
16199 : : }
16200 : :
16201 : : static const struct rte_flow_item_eth *
16202 : : __get_eth_spec(const enum mlx5_flow_ctrl_rx_eth_pattern_type pattern)
16203 : : {
16204 : 0 : switch (pattern) {
16205 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL:
16206 : : return &ctrl_rx_eth_promisc_spec;
16207 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL_MCAST:
16208 : 0 : return &ctrl_rx_eth_mcast_spec;
16209 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST:
16210 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST_VLAN:
16211 : 0 : return &ctrl_rx_eth_bcast_spec;
16212 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST:
16213 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST_VLAN:
16214 : 0 : return &ctrl_rx_eth_ipv4_mcast_spec;
16215 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST:
16216 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST_VLAN:
16217 : 0 : return &ctrl_rx_eth_ipv6_mcast_spec;
16218 : 0 : default:
16219 : : /* This case should not be reached. */
16220 : : MLX5_ASSERT(false);
16221 : 0 : return NULL;
16222 : : }
16223 : : }
16224 : :
16225 : : static int
16226 [ # # # # : 0 : __flow_hw_ctrl_flows_single(struct rte_eth_dev *dev,
# # ]
16227 : : struct rte_flow_template_table *tbl,
16228 : : const enum mlx5_flow_ctrl_rx_eth_pattern_type pattern_type,
16229 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
16230 : : {
16231 : : const struct rte_flow_item_eth *eth_spec = __get_eth_spec(pattern_type);
16232 : : struct rte_flow_item items[5];
16233 : 0 : struct rte_flow_action actions[] = {
16234 : : { .type = RTE_FLOW_ACTION_TYPE_RSS },
16235 : : { .type = RTE_FLOW_ACTION_TYPE_END },
16236 : : };
16237 : 0 : struct mlx5_ctrl_flow_info flow_info = {
16238 : : .type = MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS,
16239 : : };
16240 : :
16241 [ # # ]: 0 : if (!eth_spec)
16242 : : return -EINVAL;
16243 : : memset(items, 0, sizeof(items));
16244 : 0 : items[0] = (struct rte_flow_item){
16245 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
16246 : : .spec = eth_spec,
16247 : : };
16248 [ # # # ]: 0 : items[1] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_VOID };
16249 [ # # # ]: 0 : items[2] = flow_hw_get_ctrl_rx_l3_item(rss_type);
16250 : 0 : items[3] = flow_hw_get_ctrl_rx_l4_item(rss_type);
16251 : 0 : items[4] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_END };
16252 : : /* Without VLAN filtering, only a single flow rule must be created. */
16253 : 0 : return flow_hw_create_ctrl_flow(dev, dev, tbl, items, 0, actions, 0, &flow_info, false);
16254 : : }
16255 : :
16256 : : static int
16257 : 0 : __flow_hw_ctrl_flows_single_vlan(struct rte_eth_dev *dev,
16258 : : struct rte_flow_template_table *tbl,
16259 : : const enum mlx5_flow_ctrl_rx_eth_pattern_type pattern_type,
16260 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
16261 : : {
16262 [ # # # # : 0 : struct mlx5_priv *priv = dev->data->dev_private;
# # ]
16263 : : const struct rte_flow_item_eth *eth_spec = __get_eth_spec(pattern_type);
16264 : : struct rte_flow_item items[5];
16265 : 0 : struct rte_flow_action actions[] = {
16266 : : { .type = RTE_FLOW_ACTION_TYPE_RSS },
16267 : : { .type = RTE_FLOW_ACTION_TYPE_END },
16268 : : };
16269 : 0 : struct mlx5_ctrl_flow_info flow_info = {
16270 : : .type = MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS,
16271 : : };
16272 : : unsigned int i;
16273 : :
16274 [ # # ]: 0 : if (!eth_spec)
16275 : : return -EINVAL;
16276 : : memset(items, 0, sizeof(items));
16277 : 0 : items[0] = (struct rte_flow_item){
16278 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
16279 : : .spec = eth_spec,
16280 : : };
16281 : : /* Optional VLAN for now will be VOID - will be filled later. */
16282 [ # # # ]: 0 : items[1] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_VLAN };
16283 [ # # # ]: 0 : items[2] = flow_hw_get_ctrl_rx_l3_item(rss_type);
16284 : 0 : items[3] = flow_hw_get_ctrl_rx_l4_item(rss_type);
16285 : 0 : items[4] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_END };
16286 : : /* Since VLAN filtering is done, create a single flow rule for each registered vid. */
16287 [ # # ]: 0 : for (i = 0; i < priv->vlan_filter_n; ++i) {
16288 : 0 : uint16_t vlan = priv->vlan_filter[i];
16289 : 0 : struct rte_flow_item_vlan vlan_spec = {
16290 [ # # ]: 0 : .hdr.vlan_tci = rte_cpu_to_be_16(vlan),
16291 : : };
16292 : :
16293 : 0 : items[1].spec = &vlan_spec;
16294 [ # # ]: 0 : if (flow_hw_create_ctrl_flow(dev, dev,
16295 : : tbl, items, 0, actions, 0, &flow_info, false))
16296 : 0 : return -rte_errno;
16297 : : }
16298 : : return 0;
16299 : : }
16300 : :
16301 : : static int
16302 : 0 : __flow_hw_ctrl_flows_unicast_create(struct rte_eth_dev *dev,
16303 : : struct rte_flow_template_table *tbl,
16304 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type,
16305 : : const struct rte_ether_addr *addr)
16306 : : {
16307 : 0 : struct rte_flow_item_eth eth_spec = {
16308 : : .hdr.dst_addr = *addr,
16309 : : };
16310 : : struct rte_flow_item items[5];
16311 : 0 : struct rte_flow_action actions[] = {
16312 : : { .type = RTE_FLOW_ACTION_TYPE_RSS },
16313 : : { .type = RTE_FLOW_ACTION_TYPE_END },
16314 : : };
16315 [ # # # ]: 0 : struct mlx5_ctrl_flow_info flow_info = {
16316 : : .type = MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC,
16317 : : .uc = {
16318 : : .dmac = *addr,
16319 : : },
16320 : : };
16321 : :
16322 : : memset(items, 0, sizeof(items));
16323 : 0 : items[0] = (struct rte_flow_item){
16324 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
16325 : : .spec = ð_spec,
16326 : : };
16327 [ # # # ]: 0 : items[1] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_VOID };
16328 [ # # # ]: 0 : items[2] = flow_hw_get_ctrl_rx_l3_item(rss_type);
16329 : 0 : items[3] = flow_hw_get_ctrl_rx_l4_item(rss_type);
16330 : 0 : items[4] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_END };
16331 : :
16332 [ # # ]: 0 : if (flow_hw_create_ctrl_flow(dev, dev, tbl, items, 0, actions, 0, &flow_info, false))
16333 : 0 : return -rte_errno;
16334 : :
16335 : : return 0;
16336 : : }
16337 : :
16338 : : static int
16339 : 0 : __flow_hw_ctrl_flows_unicast(struct rte_eth_dev *dev,
16340 : : struct rte_flow_template_table *tbl,
16341 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
16342 : : {
16343 : : unsigned int i;
16344 : : int ret;
16345 : :
16346 [ # # ]: 0 : for (i = 0; i < MLX5_MAX_MAC_ADDRESSES; ++i) {
16347 [ # # ]: 0 : struct rte_ether_addr *mac = &dev->data->mac_addrs[i];
16348 : :
16349 [ # # ]: 0 : if (rte_is_zero_ether_addr(mac))
16350 : 0 : continue;
16351 : :
16352 : 0 : ret = __flow_hw_ctrl_flows_unicast_create(dev, tbl, rss_type, mac);
16353 [ # # ]: 0 : if (ret < 0)
16354 : 0 : return ret;
16355 : : }
16356 : : return 0;
16357 : : }
16358 : :
16359 : : static int
16360 : 0 : __flow_hw_ctrl_flows_unicast_vlan_create(struct rte_eth_dev *dev,
16361 : : struct rte_flow_template_table *tbl,
16362 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type,
16363 : : const struct rte_ether_addr *addr,
16364 : : const uint16_t vid)
16365 : : {
16366 : 0 : struct rte_flow_item_eth eth_spec = {
16367 : : .hdr.dst_addr = *addr,
16368 : : };
16369 : 0 : struct rte_flow_item_vlan vlan_spec = {
16370 [ # # ]: 0 : .tci = rte_cpu_to_be_16(vid),
16371 : : };
16372 : : struct rte_flow_item items[5];
16373 : 0 : struct rte_flow_action actions[] = {
16374 : : { .type = RTE_FLOW_ACTION_TYPE_RSS },
16375 : : { .type = RTE_FLOW_ACTION_TYPE_END },
16376 : : };
16377 [ # # # ]: 0 : struct mlx5_ctrl_flow_info flow_info = {
16378 : : .type = MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC_VLAN,
16379 : : .uc = {
16380 : : .dmac = *addr,
16381 : : .vlan = vid,
16382 : : },
16383 : : };
16384 : :
16385 : : memset(items, 0, sizeof(items));
16386 : 0 : items[0] = (struct rte_flow_item){
16387 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
16388 : : .spec = ð_spec,
16389 : : };
16390 [ # # # ]: 0 : items[1] = (struct rte_flow_item){
16391 : : .type = RTE_FLOW_ITEM_TYPE_VLAN,
16392 : : .spec = &vlan_spec,
16393 : : };
16394 [ # # # ]: 0 : items[2] = flow_hw_get_ctrl_rx_l3_item(rss_type);
16395 : 0 : items[3] = flow_hw_get_ctrl_rx_l4_item(rss_type);
16396 : 0 : items[4] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_END };
16397 : :
16398 [ # # ]: 0 : if (flow_hw_create_ctrl_flow(dev, dev, tbl, items, 0, actions, 0, &flow_info, false))
16399 : 0 : return -rte_errno;
16400 : :
16401 : : return 0;
16402 : : }
16403 : :
16404 : : static int
16405 : 0 : __flow_hw_ctrl_flows_unicast_vlan(struct rte_eth_dev *dev,
16406 : : struct rte_flow_template_table *tbl,
16407 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
16408 : : {
16409 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16410 : : unsigned int i;
16411 : : unsigned int j;
16412 : :
16413 [ # # ]: 0 : for (i = 0; i < MLX5_MAX_MAC_ADDRESSES; ++i) {
16414 [ # # ]: 0 : struct rte_ether_addr *mac = &dev->data->mac_addrs[i];
16415 : :
16416 [ # # ]: 0 : if (rte_is_zero_ether_addr(mac))
16417 : 0 : continue;
16418 : :
16419 [ # # ]: 0 : for (j = 0; j < priv->vlan_filter_n; ++j) {
16420 : 0 : uint16_t vlan = priv->vlan_filter[j];
16421 : : int ret;
16422 : :
16423 : 0 : ret = __flow_hw_ctrl_flows_unicast_vlan_create(dev, tbl, rss_type,
16424 : : mac, vlan);
16425 [ # # ]: 0 : if (ret < 0)
16426 : 0 : return ret;
16427 : : }
16428 : : }
16429 : : return 0;
16430 : : }
16431 : :
16432 : : static int
16433 : 0 : __flow_hw_ctrl_flows(struct rte_eth_dev *dev,
16434 : : struct rte_flow_template_table *tbl,
16435 : : const enum mlx5_flow_ctrl_rx_eth_pattern_type pattern_type,
16436 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
16437 : : {
16438 [ # # # # : 0 : switch (pattern_type) {
# ]
16439 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL:
16440 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL_MCAST:
16441 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST:
16442 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST:
16443 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST:
16444 : 0 : return __flow_hw_ctrl_flows_single(dev, tbl, pattern_type, rss_type);
16445 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST_VLAN:
16446 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST_VLAN:
16447 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST_VLAN:
16448 : 0 : return __flow_hw_ctrl_flows_single_vlan(dev, tbl, pattern_type, rss_type);
16449 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC:
16450 : 0 : return __flow_hw_ctrl_flows_unicast(dev, tbl, rss_type);
16451 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN:
16452 : 0 : return __flow_hw_ctrl_flows_unicast_vlan(dev, tbl, rss_type);
16453 : 0 : default:
16454 : : /* Should not reach here. */
16455 : : MLX5_ASSERT(false);
16456 : 0 : rte_errno = EINVAL;
16457 : 0 : return -EINVAL;
16458 : : }
16459 : : }
16460 : :
16461 : :
16462 : : int
16463 : 0 : mlx5_flow_hw_ctrl_flows(struct rte_eth_dev *dev, uint32_t flags)
16464 : : {
16465 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16466 : : struct mlx5_flow_hw_ctrl_rx *hw_ctrl_rx;
16467 : : unsigned int i;
16468 : : int j;
16469 : : int ret = 0;
16470 : :
16471 : : RTE_SET_USED(priv);
16472 : : RTE_SET_USED(flags);
16473 [ # # ]: 0 : if (!priv->dr_ctx) {
16474 : 0 : DRV_LOG(DEBUG, "port %u Control flow rules will not be created. "
16475 : : "HWS needs to be configured beforehand.",
16476 : : dev->data->port_id);
16477 : 0 : return 0;
16478 : : }
16479 [ # # ]: 0 : if (!priv->hw_ctrl_rx) {
16480 : 0 : DRV_LOG(ERR, "port %u Control flow rules templates were not created.",
16481 : : dev->data->port_id);
16482 : 0 : rte_errno = EINVAL;
16483 : 0 : return -rte_errno;
16484 : : }
16485 : : hw_ctrl_rx = priv->hw_ctrl_rx;
16486 [ # # ]: 0 : for (i = 0; i < MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_MAX; ++i) {
16487 : : const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type = i;
16488 : :
16489 [ # # ]: 0 : if (!eth_pattern_type_is_requested(eth_pattern_type, flags))
16490 : 0 : continue;
16491 [ # # ]: 0 : for (j = 0; j < MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX; ++j) {
16492 : 0 : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type = j;
16493 : : struct rte_flow_actions_template *at;
16494 : : struct mlx5_flow_hw_ctrl_rx_table *tmpls = &hw_ctrl_rx->tables[i][j];
16495 : 0 : const struct mlx5_flow_template_table_cfg cfg = {
16496 : : .attr = tmpls->attr,
16497 : : .external = 0,
16498 : : };
16499 : :
16500 [ # # ]: 0 : if (!hw_ctrl_rx->rss[rss_type]) {
16501 : 0 : at = flow_hw_create_ctrl_rx_rss_template(dev, rss_type);
16502 [ # # ]: 0 : if (!at)
16503 : 0 : return -rte_errno;
16504 : 0 : hw_ctrl_rx->rss[rss_type] = at;
16505 : : } else {
16506 : 0 : at = hw_ctrl_rx->rss[rss_type];
16507 : : }
16508 [ # # ]: 0 : if (!rss_type_is_requested(priv, rss_type))
16509 : 0 : continue;
16510 [ # # ]: 0 : if (!tmpls->tbl) {
16511 : 0 : tmpls->tbl = flow_hw_table_create(dev, &cfg,
16512 : : &tmpls->pt, 1, &at, 1, NULL);
16513 [ # # ]: 0 : if (!tmpls->tbl) {
16514 : 0 : DRV_LOG(ERR, "port %u Failed to create template table "
16515 : : "for control flow rules. Unable to create "
16516 : : "control flow rules.",
16517 : : dev->data->port_id);
16518 : 0 : return -rte_errno;
16519 : : }
16520 : : }
16521 : :
16522 : 0 : ret = __flow_hw_ctrl_flows(dev, tmpls->tbl, eth_pattern_type, rss_type);
16523 [ # # ]: 0 : if (ret) {
16524 : 0 : DRV_LOG(ERR, "port %u Failed to create control flow rule.",
16525 : : dev->data->port_id);
16526 : 0 : return ret;
16527 : : }
16528 : : }
16529 : : }
16530 : : return 0;
16531 : : }
16532 : :
16533 : : static int
16534 : 0 : mlx5_flow_hw_ctrl_flow_single(struct rte_eth_dev *dev,
16535 : : const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type,
16536 : : const struct rte_ether_addr *addr,
16537 : : const uint16_t vlan)
16538 : : {
16539 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16540 : : struct mlx5_flow_hw_ctrl_rx *hw_ctrl_rx;
16541 : : unsigned int j;
16542 : : int ret = 0;
16543 : :
16544 [ # # ]: 0 : if (!priv->dr_ctx) {
16545 : 0 : DRV_LOG(DEBUG, "port %u Control flow rules will not be created. "
16546 : : "HWS needs to be configured beforehand.",
16547 : : dev->data->port_id);
16548 : 0 : return 0;
16549 : : }
16550 [ # # ]: 0 : if (!priv->hw_ctrl_rx) {
16551 : 0 : DRV_LOG(ERR, "port %u Control flow rules templates were not created.",
16552 : : dev->data->port_id);
16553 : 0 : rte_errno = EINVAL;
16554 : 0 : return -rte_errno;
16555 : : }
16556 : : hw_ctrl_rx = priv->hw_ctrl_rx;
16557 : :
16558 : : /* TODO: this part should be somehow refactored. It's common with common flow creation. */
16559 [ # # ]: 0 : for (j = 0; j < MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX; ++j) {
16560 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type = j;
16561 : : const unsigned int pti = eth_pattern_type;
16562 : : struct rte_flow_actions_template *at;
16563 : : struct mlx5_flow_hw_ctrl_rx_table *tmpls = &hw_ctrl_rx->tables[pti][j];
16564 : 0 : const struct mlx5_flow_template_table_cfg cfg = {
16565 : : .attr = tmpls->attr,
16566 : : .external = 0,
16567 : : };
16568 : :
16569 [ # # ]: 0 : if (!hw_ctrl_rx->rss[rss_type]) {
16570 : 0 : at = flow_hw_create_ctrl_rx_rss_template(dev, rss_type);
16571 [ # # ]: 0 : if (!at)
16572 : 0 : return -rte_errno;
16573 : 0 : hw_ctrl_rx->rss[rss_type] = at;
16574 : : } else {
16575 : 0 : at = hw_ctrl_rx->rss[rss_type];
16576 : : }
16577 [ # # ]: 0 : if (!rss_type_is_requested(priv, rss_type))
16578 : 0 : continue;
16579 [ # # ]: 0 : if (!tmpls->tbl) {
16580 : 0 : tmpls->tbl = flow_hw_table_create(dev, &cfg,
16581 : : &tmpls->pt, 1, &at, 1, NULL);
16582 [ # # ]: 0 : if (!tmpls->tbl) {
16583 : 0 : DRV_LOG(ERR, "port %u Failed to create template table "
16584 : : "for control flow rules. Unable to create "
16585 : : "control flow rules.",
16586 : : dev->data->port_id);
16587 : 0 : return -rte_errno;
16588 : : }
16589 : : }
16590 : :
16591 : : MLX5_ASSERT(eth_pattern_type == MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC ||
16592 : : eth_pattern_type == MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN);
16593 : :
16594 [ # # ]: 0 : if (eth_pattern_type == MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC)
16595 : 0 : ret = __flow_hw_ctrl_flows_unicast_create(dev, tmpls->tbl, rss_type, addr);
16596 : : else
16597 : 0 : ret = __flow_hw_ctrl_flows_unicast_vlan_create(dev, tmpls->tbl, rss_type,
16598 : : addr, vlan);
16599 [ # # ]: 0 : if (ret) {
16600 : 0 : DRV_LOG(ERR, "port %u Failed to create unicast control flow rule.",
16601 : : dev->data->port_id);
16602 : 0 : return ret;
16603 : : }
16604 : : }
16605 : :
16606 : : return 0;
16607 : : }
16608 : :
16609 : : int
16610 : 0 : mlx5_flow_hw_ctrl_flow_dmac(struct rte_eth_dev *dev,
16611 : : const struct rte_ether_addr *addr)
16612 : : {
16613 : 0 : return mlx5_flow_hw_ctrl_flow_single(dev, MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC,
16614 : : addr, 0);
16615 : : }
16616 : :
16617 : :
16618 : : int
16619 : 0 : mlx5_flow_hw_ctrl_flow_dmac_destroy(struct rte_eth_dev *dev,
16620 : : const struct rte_ether_addr *addr)
16621 : : {
16622 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16623 : : struct mlx5_ctrl_flow_entry *entry;
16624 : : struct mlx5_ctrl_flow_entry *tmp;
16625 : : int ret;
16626 : :
16627 : : /*
16628 : : * HWS does not have automatic RSS flow expansion,
16629 : : * so each variant of the control flow rule is a separate entry in the list.
16630 : : * In that case, the whole list must be traversed.
16631 : : */
16632 : 0 : entry = LIST_FIRST(&priv->hw_ctrl_flows);
16633 [ # # ]: 0 : while (entry != NULL) {
16634 : 0 : tmp = LIST_NEXT(entry, next);
16635 : :
16636 [ # # # # ]: 0 : if (entry->info.type != MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC ||
16637 : : !rte_is_same_ether_addr(addr, &entry->info.uc.dmac)) {
16638 : : entry = tmp;
16639 : 0 : continue;
16640 : : }
16641 : :
16642 : 0 : ret = flow_hw_destroy_ctrl_flow(dev, entry->flow);
16643 [ # # ]: 0 : LIST_REMOVE(entry, next);
16644 : 0 : mlx5_free(entry);
16645 [ # # ]: 0 : if (ret)
16646 : 0 : return ret;
16647 : :
16648 : : entry = tmp;
16649 : : }
16650 : : return 0;
16651 : : }
16652 : :
16653 : : int
16654 : 0 : mlx5_flow_hw_ctrl_flow_dmac_vlan(struct rte_eth_dev *dev,
16655 : : const struct rte_ether_addr *addr,
16656 : : const uint16_t vlan)
16657 : : {
16658 : 0 : return mlx5_flow_hw_ctrl_flow_single(dev, MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN,
16659 : : addr, vlan);
16660 : : }
16661 : :
16662 : : int
16663 : 0 : mlx5_flow_hw_ctrl_flow_dmac_vlan_destroy(struct rte_eth_dev *dev,
16664 : : const struct rte_ether_addr *addr,
16665 : : const uint16_t vlan)
16666 : : {
16667 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16668 : : struct mlx5_ctrl_flow_entry *entry;
16669 : : struct mlx5_ctrl_flow_entry *tmp;
16670 : : int ret;
16671 : :
16672 : : /*
16673 : : * HWS does not have automatic RSS flow expansion,
16674 : : * so each variant of the control flow rule is a separate entry in the list.
16675 : : * In that case, the whole list must be traversed.
16676 : : */
16677 : 0 : entry = LIST_FIRST(&priv->hw_ctrl_flows);
16678 [ # # ]: 0 : while (entry != NULL) {
16679 : 0 : tmp = LIST_NEXT(entry, next);
16680 : :
16681 [ # # # # ]: 0 : if (entry->info.type != MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC_VLAN ||
16682 : 0 : !rte_is_same_ether_addr(addr, &entry->info.uc.dmac) ||
16683 [ # # ]: 0 : vlan != entry->info.uc.vlan) {
16684 : : entry = tmp;
16685 : 0 : continue;
16686 : : }
16687 : :
16688 : 0 : ret = flow_hw_destroy_ctrl_flow(dev, entry->flow);
16689 [ # # ]: 0 : LIST_REMOVE(entry, next);
16690 : 0 : mlx5_free(entry);
16691 [ # # ]: 0 : if (ret)
16692 : 0 : return ret;
16693 : :
16694 : : entry = tmp;
16695 : : }
16696 : : return 0;
16697 : : }
16698 : :
16699 : : struct mlx5_ecpri_parser_profile *
16700 : 0 : flow_hw_get_ecpri_parser_profile(void *dr_ctx)
16701 : : {
16702 : : uint16_t port_id;
16703 : : bool found = false;
16704 : : struct mlx5_priv *priv;
16705 : :
16706 [ # # ]: 0 : MLX5_ETH_FOREACH_DEV(port_id, NULL) {
16707 : 0 : priv = rte_eth_devices[port_id].data->dev_private;
16708 [ # # ]: 0 : if (priv->dr_ctx == dr_ctx) {
16709 : : found = true;
16710 : : break;
16711 : : }
16712 : : }
16713 [ # # ]: 0 : if (found)
16714 : 0 : return &priv->sh->ecpri_parser;
16715 : 0 : rte_errno = ENODEV;
16716 : 0 : return NULL;
16717 : : }
16718 : :
16719 : :
16720 : : static __rte_always_inline uint32_t
16721 : : mlx5_reformat_domain_to_tbl_type(const struct rte_flow_indir_action_conf *domain,
16722 : : bool fdb_unified_en)
16723 : : {
16724 : : uint32_t tbl_type;
16725 : :
16726 [ # # ]: 0 : if (domain->transfer)
16727 : : tbl_type = (fdb_unified_en ?
16728 : : (MLX5DR_ACTION_FLAG_HWS_FDB_RX |
16729 : : MLX5DR_ACTION_FLAG_HWS_FDB_TX |
16730 [ # # ]: 0 : MLX5DR_ACTION_FLAG_HWS_FDB_UNIFIED) :
16731 : : MLX5DR_ACTION_FLAG_HWS_FDB);
16732 [ # # ]: 0 : else if (domain->egress)
16733 : : tbl_type = MLX5DR_ACTION_FLAG_HWS_TX;
16734 [ # # ]: 0 : else if (domain->ingress)
16735 : : tbl_type = MLX5DR_ACTION_FLAG_HWS_RX;
16736 : : else
16737 : : tbl_type = UINT32_MAX;
16738 : : return tbl_type;
16739 : : }
16740 : :
16741 : : static struct mlx5_hw_encap_decap_action *
16742 : 0 : __mlx5_reformat_create(struct rte_eth_dev *dev,
16743 : : const struct rte_flow_action_raw_encap *encap_conf,
16744 : : const struct rte_flow_indir_action_conf *domain,
16745 : : enum mlx5dr_action_type type)
16746 : : {
16747 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
16748 : : struct mlx5_hw_encap_decap_action *handle;
16749 : : struct mlx5dr_action_reformat_header hdr;
16750 : : uint32_t flags;
16751 : : bool unified_fdb = is_unified_fdb(priv);
16752 : :
16753 : : flags = mlx5_reformat_domain_to_tbl_type(domain, unified_fdb);
16754 : 0 : flags |= (uint32_t)MLX5DR_ACTION_FLAG_SHARED;
16755 [ # # ]: 0 : if (flags == UINT32_MAX) {
16756 : 0 : DRV_LOG(ERR, "Reformat: invalid indirect action configuration");
16757 : 0 : return NULL;
16758 : : }
16759 : : /* Allocate new list entry. */
16760 : 0 : handle = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*handle), 0, SOCKET_ID_ANY);
16761 [ # # ]: 0 : if (!handle) {
16762 : 0 : DRV_LOG(ERR, "Reformat: failed to allocate reformat entry");
16763 : 0 : return NULL;
16764 : : }
16765 : 0 : handle->action_type = type;
16766 [ # # ]: 0 : hdr.sz = encap_conf ? encap_conf->size : 0;
16767 [ # # ]: 0 : hdr.data = encap_conf ? encap_conf->data : NULL;
16768 : 0 : handle->action = mlx5dr_action_create_reformat(priv->dr_ctx,
16769 : : type, 1, &hdr, 0, flags);
16770 [ # # ]: 0 : if (!handle->action) {
16771 : 0 : DRV_LOG(ERR, "Reformat: failed to create reformat action");
16772 : 0 : mlx5_free(handle);
16773 : 0 : return NULL;
16774 : : }
16775 : : return handle;
16776 : : }
16777 : :
16778 : : /**
16779 : : * Create mlx5 reformat action.
16780 : : *
16781 : : * @param[in] dev
16782 : : * Pointer to rte_eth_dev structure.
16783 : : * @param[in] conf
16784 : : * Pointer to the indirect action parameters.
16785 : : * @param[in] encap_action
16786 : : * Pointer to the raw_encap action configuration.
16787 : : * @param[in] decap_action
16788 : : * Pointer to the raw_decap action configuration.
16789 : : * @param[out] error
16790 : : * Pointer to error structure.
16791 : : *
16792 : : * @return
16793 : : * A valid shared action handle in case of success, NULL otherwise and
16794 : : * rte_errno is set.
16795 : : */
16796 : : struct mlx5_hw_encap_decap_action*
16797 : 0 : mlx5_reformat_action_create(struct rte_eth_dev *dev,
16798 : : const struct rte_flow_indir_action_conf *conf,
16799 : : const struct rte_flow_action *encap_action,
16800 : : const struct rte_flow_action *decap_action,
16801 : : struct rte_flow_error *error)
16802 : : {
16803 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16804 : : struct mlx5_hw_encap_decap_action *handle;
16805 : : const struct rte_flow_action_raw_encap *encap = NULL;
16806 : : const struct rte_flow_action_raw_decap *decap = NULL;
16807 : : enum mlx5dr_action_type type = MLX5DR_ACTION_TYP_LAST;
16808 : :
16809 : : MLX5_ASSERT(!encap_action || encap_action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP);
16810 : : MLX5_ASSERT(!decap_action || decap_action->type == RTE_FLOW_ACTION_TYPE_RAW_DECAP);
16811 [ # # ]: 0 : if (priv->sh->config.dv_flow_en != 2) {
16812 : 0 : rte_flow_error_set(error, ENOTSUP,
16813 : : RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
16814 : : "Reformat: hardware does not support");
16815 : 0 : return NULL;
16816 : : }
16817 [ # # # # ]: 0 : if (!conf || (conf->transfer + conf->egress + conf->ingress != 1)) {
16818 : 0 : rte_flow_error_set(error, EINVAL,
16819 : : RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
16820 : : "Reformat: domain should be specified");
16821 : 0 : return NULL;
16822 : : }
16823 [ # # # # : 0 : if ((encap_action && !encap_action->conf) || (decap_action && !decap_action->conf)) {
# # # # ]
16824 : 0 : rte_flow_error_set(error, EINVAL,
16825 : : RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
16826 : : "Reformat: missed action configuration");
16827 : 0 : return NULL;
16828 : : }
16829 [ # # ]: 0 : if (encap_action && !decap_action) {
16830 : 0 : encap = (const struct rte_flow_action_raw_encap *)encap_action->conf;
16831 [ # # ]: 0 : if (!encap->size || encap->size > MLX5_ENCAP_MAX_LEN ||
16832 : : encap->size < MLX5_ENCAPSULATION_DECISION_SIZE) {
16833 : 0 : rte_flow_error_set(error, EINVAL,
16834 : : RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
16835 : : "Reformat: Invalid encap length");
16836 : 0 : return NULL;
16837 : : }
16838 : : type = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;
16839 [ # # ]: 0 : } else if (decap_action && !encap_action) {
16840 : 0 : decap = (const struct rte_flow_action_raw_decap *)decap_action->conf;
16841 [ # # ]: 0 : if (!decap->size || decap->size < MLX5_ENCAPSULATION_DECISION_SIZE) {
16842 : 0 : rte_flow_error_set(error, EINVAL,
16843 : : RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
16844 : : "Reformat: Invalid decap length");
16845 : 0 : return NULL;
16846 : : }
16847 : : type = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2;
16848 [ # # ]: 0 : } else if (encap_action && decap_action) {
16849 : 0 : decap = (const struct rte_flow_action_raw_decap *)decap_action->conf;
16850 : 0 : encap = (const struct rte_flow_action_raw_encap *)encap_action->conf;
16851 [ # # ]: 0 : if (decap->size < MLX5_ENCAPSULATION_DECISION_SIZE &&
16852 [ # # # # ]: 0 : encap->size >= MLX5_ENCAPSULATION_DECISION_SIZE &&
16853 : : encap->size <= MLX5_ENCAP_MAX_LEN) {
16854 : : type = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3;
16855 [ # # ]: 0 : } else if (decap->size >= MLX5_ENCAPSULATION_DECISION_SIZE &&
16856 [ # # ]: 0 : encap->size < MLX5_ENCAPSULATION_DECISION_SIZE) {
16857 : : type = MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2;
16858 : : } else {
16859 : 0 : rte_flow_error_set(error, EINVAL,
16860 : : RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
16861 : : "Reformat: Invalid decap & encap length");
16862 : 0 : return NULL;
16863 : : }
16864 [ # # ]: 0 : } else if (!encap_action && !decap_action) {
16865 : 0 : rte_flow_error_set(error, EINVAL,
16866 : : RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
16867 : : "Reformat: Invalid decap & encap configurations");
16868 : 0 : return NULL;
16869 : : }
16870 [ # # ]: 0 : if (!priv->dr_ctx) {
16871 : 0 : rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
16872 : : encap_action, "Reformat: HWS not supported");
16873 : 0 : return NULL;
16874 : : }
16875 : 0 : handle = __mlx5_reformat_create(dev, encap, conf, type);
16876 [ # # ]: 0 : if (!handle) {
16877 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
16878 : : "Reformat: failed to create indirect action");
16879 : 0 : return NULL;
16880 : : }
16881 : : return handle;
16882 : : }
16883 : :
16884 : : /**
16885 : : * Destroy the indirect reformat action.
16886 : : * Release action related resources on the NIC and the memory.
16887 : : * Lock free, (mutex should be acquired by caller).
16888 : : *
16889 : : * @param[in] dev
16890 : : * Pointer to the Ethernet device structure.
16891 : : * @param[in] handle
16892 : : * The indirect action list handle to be removed.
16893 : : * @param[out] error
16894 : : * Perform verbose error reporting if not NULL. Initialized in case of
16895 : : * error only.
16896 : : *
16897 : : * @return
16898 : : * 0 on success, otherwise negative errno value.
16899 : : */
16900 : : int
16901 : 0 : mlx5_reformat_action_destroy(struct rte_eth_dev *dev,
16902 : : struct rte_flow_action_list_handle *handle,
16903 : : struct rte_flow_error *error)
16904 : : {
16905 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16906 : : struct mlx5_hw_encap_decap_action *action;
16907 : :
16908 : : action = (struct mlx5_hw_encap_decap_action *)handle;
16909 [ # # # # ]: 0 : if (!priv->dr_ctx || !action)
16910 : 0 : return rte_flow_error_set(error, ENOTSUP,
16911 : : RTE_FLOW_ERROR_TYPE_ACTION, handle,
16912 : : "Reformat: invalid action handle");
16913 : 0 : mlx5dr_action_destroy(action->action);
16914 : 0 : mlx5_free(handle);
16915 : 0 : return 0;
16916 : : }
16917 : :
16918 : : static bool
16919 : 0 : flow_hw_is_item_masked(const struct rte_flow_item *item)
16920 : : {
16921 : : const uint8_t *byte;
16922 : : int size;
16923 : : int i;
16924 : :
16925 [ # # ]: 0 : if (item->mask == NULL)
16926 : : return false;
16927 : :
16928 [ # # ]: 0 : switch ((int)item->type) {
16929 : : case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
16930 : : size = sizeof(struct rte_flow_item_tag);
16931 : : break;
16932 : : case MLX5_RTE_FLOW_ITEM_TYPE_SQ:
16933 : : size = sizeof(struct mlx5_rte_flow_item_sq);
16934 : : break;
16935 : 0 : default:
16936 : 0 : size = rte_flow_conv(RTE_FLOW_CONV_OP_ITEM_MASK, NULL, 0, item, NULL);
16937 : : /*
16938 : : * Pattern template items are passed to this function.
16939 : : * These items were already validated, so error is not expected.
16940 : : * Also, if mask is NULL, then spec size is bigger than 0 always.
16941 : : */
16942 : : MLX5_ASSERT(size > 0);
16943 : : }
16944 : :
16945 : 0 : byte = (const uint8_t *)item->mask;
16946 [ # # ]: 0 : for (i = 0; i < size; ++i)
16947 [ # # ]: 0 : if (byte[i])
16948 : : return true;
16949 : :
16950 : : return false;
16951 : : }
16952 : :
16953 : : static int
16954 : 0 : flow_hw_validate_rule_pattern(struct rte_eth_dev *dev,
16955 : : const struct rte_flow_template_table *table,
16956 : : const uint8_t pattern_template_idx,
16957 : : const struct rte_flow_item items[],
16958 : : struct rte_flow_error *error)
16959 : : {
16960 : : const struct rte_flow_pattern_template *pt;
16961 : : const struct rte_flow_item *pt_item;
16962 : :
16963 [ # # ]: 0 : if (pattern_template_idx >= table->nb_item_templates)
16964 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
16965 : : "Pattern template index out of range");
16966 : :
16967 : 0 : pt = table->its[pattern_template_idx];
16968 : 0 : pt_item = pt->items;
16969 : :
16970 : : /* If any item was prepended, skip it. */
16971 [ # # ]: 0 : if (pt->implicit_port || pt->implicit_tag)
16972 : 0 : pt_item++;
16973 : :
16974 [ # # ]: 0 : for (; pt_item->type != RTE_FLOW_ITEM_TYPE_END; pt_item++, items++) {
16975 [ # # ]: 0 : if (pt_item->type != items->type)
16976 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM,
16977 : : items, "Item type does not match the template");
16978 : :
16979 : : /*
16980 : : * Assumptions:
16981 : : * - Currently mlx5dr layer contains info on which fields in masks are supported.
16982 : : * - This info is not exposed to PMD directly.
16983 : : * - Because of that, it is assumed that since pattern template is correct,
16984 : : * then, items' masks in pattern template have nonzero values only in
16985 : : * supported fields.
16986 : : * This is known, because a temporary mlx5dr matcher is created during pattern
16987 : : * template creation to validate the template.
16988 : : * - As a result, it is safe to look for nonzero bytes in mask to determine if
16989 : : * item spec is needed in a flow rule.
16990 : : */
16991 [ # # ]: 0 : if (!flow_hw_is_item_masked(pt_item))
16992 : 0 : continue;
16993 : :
16994 [ # # ]: 0 : if (items->spec == NULL)
16995 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
16996 : : items, "Item spec is required");
16997 : :
16998 [ # # # ]: 0 : switch (items->type) {
16999 : : const struct rte_flow_item_ethdev *ethdev;
17000 : : const struct rte_flow_item_tx_queue *tx_queue;
17001 : : struct mlx5_txq_ctrl *txq;
17002 : :
17003 : 0 : case RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT:
17004 : : ethdev = items->spec;
17005 [ # # ]: 0 : if (flow_hw_validate_target_port_id(dev, ethdev->port_id)) {
17006 : 0 : return rte_flow_error_set(error, EINVAL,
17007 : : RTE_FLOW_ERROR_TYPE_ITEM_SPEC, items,
17008 : : "Invalid port");
17009 : : }
17010 : : break;
17011 : 0 : case RTE_FLOW_ITEM_TYPE_TX_QUEUE:
17012 : : tx_queue = items->spec;
17013 [ # # # # ]: 0 : if (mlx5_is_external_txq(dev, tx_queue->tx_queue))
17014 : 0 : continue;
17015 : 0 : txq = mlx5_txq_get(dev, tx_queue->tx_queue);
17016 [ # # ]: 0 : if (!txq)
17017 : 0 : return rte_flow_error_set(error, EINVAL,
17018 : : RTE_FLOW_ERROR_TYPE_ITEM_SPEC, items,
17019 : : "Invalid Tx queue");
17020 : 0 : mlx5_txq_release(dev, tx_queue->tx_queue);
17021 : : default:
17022 : : break;
17023 : : }
17024 : : }
17025 : :
17026 : : return 0;
17027 : : }
17028 : :
17029 : : static bool
17030 : 0 : flow_hw_valid_indirect_action_type(const struct rte_flow_action *user_action,
17031 : : const enum rte_flow_action_type expected_type)
17032 : : {
17033 : 0 : uint32_t user_indirect_type = MLX5_INDIRECT_ACTION_TYPE_GET(user_action->conf);
17034 : : uint32_t expected_indirect_type;
17035 : :
17036 [ # # # # : 0 : switch ((int)expected_type) {
# # # ]
17037 : : case RTE_FLOW_ACTION_TYPE_RSS:
17038 : : case MLX5_RTE_FLOW_ACTION_TYPE_RSS:
17039 : : expected_indirect_type = MLX5_INDIRECT_ACTION_TYPE_RSS;
17040 : : break;
17041 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
17042 : : case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
17043 : : expected_indirect_type = MLX5_INDIRECT_ACTION_TYPE_COUNT;
17044 : 0 : break;
17045 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
17046 : : expected_indirect_type = MLX5_INDIRECT_ACTION_TYPE_AGE;
17047 : 0 : break;
17048 : 0 : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
17049 : : expected_indirect_type = MLX5_INDIRECT_ACTION_TYPE_CT;
17050 : 0 : break;
17051 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
17052 : : case MLX5_RTE_FLOW_ACTION_TYPE_METER_MARK:
17053 : : expected_indirect_type = MLX5_INDIRECT_ACTION_TYPE_METER_MARK;
17054 : 0 : break;
17055 : 0 : case RTE_FLOW_ACTION_TYPE_QUOTA:
17056 : : expected_indirect_type = MLX5_INDIRECT_ACTION_TYPE_QUOTA;
17057 : 0 : break;
17058 : : default:
17059 : : return false;
17060 : : }
17061 : :
17062 : 0 : return user_indirect_type == expected_indirect_type;
17063 : : }
17064 : :
17065 : : static int
17066 : 0 : flow_hw_validate_rule_actions(struct rte_eth_dev *dev,
17067 : : const struct rte_flow_template_table *table,
17068 : : const uint8_t actions_template_idx,
17069 : : const struct rte_flow_action actions[],
17070 : : struct rte_flow_error *error)
17071 : : {
17072 : : const struct rte_flow_actions_template *at;
17073 : : const struct mlx5_hw_actions *hw_acts;
17074 : : const struct mlx5_action_construct_data *act_data;
17075 : : unsigned int idx;
17076 : :
17077 [ # # ]: 0 : if (actions_template_idx >= table->nb_action_templates)
17078 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17079 : : "Actions template index out of range");
17080 : :
17081 : 0 : at = table->ats[actions_template_idx].action_template;
17082 : : hw_acts = &table->ats[actions_template_idx].acts;
17083 : :
17084 [ # # ]: 0 : for (idx = 0; actions[idx].type != RTE_FLOW_ACTION_TYPE_END; ++idx) {
17085 : : const struct rte_flow_action *user_action = &actions[idx];
17086 : 0 : const struct rte_flow_action *tmpl_action = &at->orig_actions[idx];
17087 : :
17088 [ # # ]: 0 : if (user_action->type != tmpl_action->type)
17089 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
17090 : : user_action,
17091 : : "Action type does not match type specified in "
17092 : : "actions template");
17093 : : }
17094 : :
17095 : : /*
17096 : : * Only go through unmasked actions and check if configuration is provided.
17097 : : * Configuration of masked actions is ignored.
17098 : : */
17099 [ # # ]: 0 : LIST_FOREACH(act_data, &hw_acts->act_list, next) {
17100 : : const struct rte_flow_action *user_action;
17101 : :
17102 : 0 : user_action = &actions[act_data->action_src];
17103 : :
17104 : : /* Skip actions which do not require conf. */
17105 [ # # ]: 0 : switch ((int)act_data->type) {
17106 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
17107 : : case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
17108 : : case MLX5_RTE_FLOW_ACTION_TYPE_METER_MARK:
17109 : : case MLX5_RTE_FLOW_ACTION_TYPE_RSS:
17110 : 0 : continue;
17111 : : default:
17112 : : break;
17113 : : }
17114 : :
17115 [ # # ]: 0 : if (user_action->conf == NULL)
17116 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
17117 : : user_action,
17118 : : "Action requires configuration");
17119 : :
17120 [ # # # # : 0 : switch ((int)user_action->type) {
# # ]
17121 : : enum rte_flow_action_type expected_type;
17122 : : const struct rte_flow_action_ethdev *ethdev;
17123 : : const struct rte_flow_action_modify_field *mf;
17124 : :
17125 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT:
17126 : 0 : expected_type = act_data->indirect.expected_type;
17127 [ # # ]: 0 : if (!flow_hw_valid_indirect_action_type(user_action, expected_type))
17128 : 0 : return rte_flow_error_set(error, EINVAL,
17129 : : RTE_FLOW_ERROR_TYPE_ACTION_CONF,
17130 : : user_action,
17131 : : "Indirect action type does not match "
17132 : : "the type specified in the mask");
17133 : : break;
17134 : 0 : case RTE_FLOW_ACTION_TYPE_QUEUE:
17135 [ # # ]: 0 : if (mlx5_flow_validate_target_queue(dev, user_action, error))
17136 : 0 : return -rte_errno;
17137 : : break;
17138 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
17139 [ # # ]: 0 : if (mlx5_validate_action_rss(dev, user_action, error))
17140 : 0 : return -rte_errno;
17141 : : break;
17142 : 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
17143 : : /* TODO: Compare other fields if needed. */
17144 : : mf = user_action->conf;
17145 [ # # ]: 0 : if (mf->operation != act_data->modify_header.action.operation ||
17146 [ # # ]: 0 : mf->src.field != act_data->modify_header.action.src.field ||
17147 [ # # ]: 0 : mf->dst.field != act_data->modify_header.action.dst.field ||
17148 [ # # ]: 0 : mf->width != act_data->modify_header.action.width)
17149 : 0 : return rte_flow_error_set(error, EINVAL,
17150 : : RTE_FLOW_ERROR_TYPE_ACTION_CONF,
17151 : : user_action,
17152 : : "Modify field configuration does not "
17153 : : "match configuration from actions "
17154 : : "template");
17155 : : break;
17156 : 0 : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
17157 : : ethdev = user_action->conf;
17158 [ # # ]: 0 : if (flow_hw_validate_target_port_id(dev, ethdev->port_id)) {
17159 : 0 : return rte_flow_error_set(error, EINVAL,
17160 : : RTE_FLOW_ERROR_TYPE_ACTION_CONF,
17161 : : user_action, "Invalid port");
17162 : : }
17163 : : break;
17164 : : default:
17165 : : break;
17166 : : }
17167 : : }
17168 : :
17169 : : return 0;
17170 : : }
17171 : :
17172 : : static int
17173 : 0 : flow_hw_async_op_validate(struct rte_eth_dev *dev,
17174 : : const uint32_t queue,
17175 : : const struct rte_flow_template_table *table,
17176 : : struct rte_flow_error *error)
17177 : : {
17178 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
17179 : :
17180 : : MLX5_ASSERT(table != NULL);
17181 : :
17182 [ # # # # ]: 0 : if (table->cfg.external && queue >= priv->hw_attr->nb_queue)
17183 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17184 : : "Incorrect queue");
17185 : :
17186 : : return 0;
17187 : : }
17188 : :
17189 : : /**
17190 : : * Validate user input for rte_flow_async_create() implementation.
17191 : : *
17192 : : * If RTE_LIBRTE_MLX5_DEBUG macro is not defined, this function is a no-op.
17193 : : *
17194 : : * @param[in] dev
17195 : : * Pointer to the rte_eth_dev structure.
17196 : : * @param[in] queue
17197 : : * The queue to create the flow.
17198 : : * @param[in] table
17199 : : * Pointer to template table.
17200 : : * @param[in] rule_index
17201 : : * The item pattern flow follows from the table.
17202 : : * @param[in] items
17203 : : * Items with flow spec value.
17204 : : * @param[in] pattern_template_index
17205 : : * The item pattern flow follows from the table.
17206 : : * @param[in] actions
17207 : : * Action with flow spec value.
17208 : : * @param[in] action_template_index
17209 : : * The action pattern flow follows from the table.
17210 : : * @param[out] error
17211 : : * Pointer to error structure.
17212 : : *
17213 : : * @return
17214 : : * 0 if user input is valid.
17215 : : * Negative errno otherwise, rte_errno and error struct is populated.
17216 : : */
17217 : : static int
17218 : 0 : flow_hw_async_create_validate(struct rte_eth_dev *dev,
17219 : : const uint32_t queue,
17220 : : const struct rte_flow_template_table *table,
17221 : : enum rte_flow_table_insertion_type insertion_type,
17222 : : uint32_t rule_index,
17223 : : const struct rte_flow_item items[],
17224 : : const uint8_t pattern_template_index,
17225 : : const struct rte_flow_action actions[],
17226 : : const uint8_t action_template_index,
17227 : : struct rte_flow_error *error)
17228 : : {
17229 [ # # ]: 0 : if (flow_hw_async_op_validate(dev, queue, table, error))
17230 : 0 : return -rte_errno;
17231 : :
17232 [ # # ]: 0 : if (insertion_type != table->cfg.attr.insertion_type)
17233 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
17234 : : NULL, "Flow rule insertion type mismatch with table configuration");
17235 : :
17236 [ # # ]: 0 : if (table->cfg.attr.insertion_type != RTE_FLOW_TABLE_INSERTION_TYPE_PATTERN)
17237 [ # # ]: 0 : if (rule_index >= table->cfg.attr.nb_flows)
17238 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
17239 : : NULL, "Flow rule index exceeds table size");
17240 : :
17241 [ # # ]: 0 : if (table->cfg.attr.insertion_type != RTE_FLOW_TABLE_INSERTION_TYPE_INDEX)
17242 [ # # ]: 0 : if (flow_hw_validate_rule_pattern(dev, table, pattern_template_index, items, error))
17243 : 0 : return -rte_errno;
17244 : :
17245 [ # # ]: 0 : if (flow_hw_validate_rule_actions(dev, table, action_template_index, actions, error))
17246 : 0 : return -rte_errno;
17247 : :
17248 : : return 0;
17249 : : }
17250 : :
17251 : : /**
17252 : : * Validate user input for rte_flow_async_update() implementation.
17253 : : *
17254 : : * If RTE_LIBRTE_MLX5_DEBUG macro is not defined, this function is a no-op.
17255 : : *
17256 : : * @param[in] dev
17257 : : * Pointer to the rte_eth_dev structure.
17258 : : * @param[in] queue
17259 : : * The queue to create the flow.
17260 : : * @param[in] flow
17261 : : * Flow rule to be updated.
17262 : : * @param[in] actions
17263 : : * Action with flow spec value.
17264 : : * @param[in] action_template_index
17265 : : * The action pattern flow follows from the table.
17266 : : * @param[out] error
17267 : : * Pointer to error structure.
17268 : : *
17269 : : * @return
17270 : : * 0 if user input is valid.
17271 : : * Negative errno otherwise, rte_errno and error struct is set.
17272 : : */
17273 : : static int
17274 : 0 : flow_hw_async_update_validate(struct rte_eth_dev *dev,
17275 : : const uint32_t queue,
17276 : : const struct rte_flow_hw *flow,
17277 : : const struct rte_flow_action actions[],
17278 : : const uint8_t action_template_index,
17279 : : struct rte_flow_error *error)
17280 : : {
17281 [ # # ]: 0 : if (flow_hw_async_op_validate(dev, queue, flow->table, error))
17282 : 0 : return -rte_errno;
17283 : :
17284 [ # # ]: 0 : if (flow_hw_validate_rule_actions(dev, flow->table, action_template_index, actions, error))
17285 : 0 : return -rte_errno;
17286 : :
17287 : : return 0;
17288 : : }
17289 : :
17290 : : /**
17291 : : * Validate user input for rte_flow_async_destroy() implementation.
17292 : : *
17293 : : * If RTE_LIBRTE_MLX5_DEBUG macro is not defined, this function is a no-op.
17294 : : *
17295 : : * @param[in] dev
17296 : : * Pointer to the rte_eth_dev structure.
17297 : : * @param[in] queue
17298 : : * The queue to create the flow.
17299 : : * @param[in] flow
17300 : : * Flow rule to be destroyed.
17301 : : * @param[out] error
17302 : : * Pointer to error structure.
17303 : : *
17304 : : * @return
17305 : : * 0 if user input is valid.
17306 : : * Negative errno otherwise, rte_errno and error struct is set.
17307 : : */
17308 : : static int
17309 : : flow_hw_async_destroy_validate(struct rte_eth_dev *dev,
17310 : : const uint32_t queue,
17311 : : const struct rte_flow_hw *flow,
17312 : : struct rte_flow_error *error)
17313 : : {
17314 : : if (flow_hw_async_op_validate(dev, queue, flow->table, error))
17315 : : return -rte_errno;
17316 : :
17317 : : return 0;
17318 : : }
17319 : :
17320 : : static struct rte_flow_fp_ops mlx5_flow_hw_fp_ops = {
17321 : : .async_create = flow_hw_async_flow_create,
17322 : : .async_create_by_index = flow_hw_async_flow_create_by_index,
17323 : : .async_create_by_index_with_pattern = flow_hw_async_flow_create_by_index_with_pattern,
17324 : : .async_actions_update = flow_hw_async_flow_update,
17325 : : .async_destroy = flow_hw_async_flow_destroy,
17326 : : .push = flow_hw_push,
17327 : : .pull = flow_hw_pull,
17328 : : .async_action_handle_create = flow_hw_action_handle_create,
17329 : : .async_action_handle_destroy = flow_hw_action_handle_destroy,
17330 : : .async_action_handle_update = flow_hw_action_handle_update,
17331 : : .async_action_handle_query = flow_hw_action_handle_query,
17332 : : .async_action_handle_query_update = flow_hw_async_action_handle_query_update,
17333 : : .async_action_list_handle_create = flow_hw_async_action_list_handle_create,
17334 : : .async_action_list_handle_destroy = flow_hw_async_action_list_handle_destroy,
17335 : : .async_action_list_handle_query_update =
17336 : : flow_hw_async_action_list_handle_query_update,
17337 : : };
17338 : :
17339 : : #endif
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