Branch data Line data Source code
1 : : /* SPDX-License-Identifier: BSD-3-Clause
2 : : * Copyright 2018 Mellanox Technologies, Ltd
3 : : */
4 : :
5 : : #include <unistd.h>
6 : :
7 : : #include <rte_errno.h>
8 : : #include <rte_malloc.h>
9 : : #include <rte_eal_paging.h>
10 : :
11 : : #include "mlx5_prm.h"
12 : : #include "mlx5_devx_cmds.h"
13 : : #include "mlx5_common_log.h"
14 : : #include "mlx5_malloc.h"
15 : :
16 : : /* FW writes status value to the OUT buffer at offset 00H */
17 : : #define MLX5_FW_STATUS(o) MLX5_GET(general_obj_out_cmd_hdr, (o), status)
18 : : /* FW writes syndrome value to the OUT buffer at offset 04H */
19 : : #define MLX5_FW_SYNDROME(o) MLX5_GET(general_obj_out_cmd_hdr, (o), syndrome)
20 : :
21 : : #define MLX5_DEVX_ERR_RC(x) ((x) > 0 ? -(x) : ((x) < 0 ? (x) : -1))
22 : :
23 : : #define DEVX_DRV_LOG(level, out, reason, param, value) \
24 : : do { \
25 : : /* \
26 : : * Some (old) GCC compilers like 7.5.0 and aarch64 GCC 7.1-2017.08 \
27 : : * do not expand correctly when the macro invoked when the `param` \
28 : : * is `NULL`. \
29 : : * Use `local_param` to avoid direct `NULL` expansion. \
30 : : */ \
31 : : const char *local_param = (const char *)param; \
32 : : \
33 : : rte_errno = errno; \
34 : : if (!local_param) { \
35 : : DRV_LOG(level, \
36 : : "DevX %s failed errno=%d status=%#x syndrome=%#x", \
37 : : (reason), errno, MLX5_FW_STATUS((out)), \
38 : : MLX5_FW_SYNDROME((out))); \
39 : : } else { \
40 : : DRV_LOG(level, \
41 : : "DevX %s %s=%#X failed errno=%d status=%#x syndrome=%#x",\
42 : : (reason), local_param, (value), errno, \
43 : : MLX5_FW_STATUS((out)), MLX5_FW_SYNDROME((out))); \
44 : : } \
45 : : } while (0)
46 : :
47 : : static void *
48 [ # # ]: 0 : mlx5_devx_get_hca_cap(void *ctx, uint32_t *in, uint32_t *out,
49 : : int *err, uint32_t flags)
50 : : {
51 : : const size_t size_in = MLX5_ST_SZ_DW(query_hca_cap_in) * sizeof(int);
52 : : const size_t size_out = MLX5_ST_SZ_DW(query_hca_cap_out) * sizeof(int);
53 : : int rc;
54 : :
55 : : memset(in, 0, size_in);
56 : : memset(out, 0, size_out);
57 [ # # ]: 0 : MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
58 [ # # ]: 0 : MLX5_SET(query_hca_cap_in, in, op_mod, flags);
59 : 0 : rc = mlx5_glue->devx_general_cmd(ctx, in, size_in, out, size_out);
60 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
61 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "HCA capabilities", "func", flags >> 1);
62 [ # # ]: 0 : if (err)
63 [ # # ]: 0 : *err = MLX5_DEVX_ERR_RC(rc);
64 : 0 : return NULL;
65 : : }
66 [ # # ]: 0 : if (err)
67 : 0 : *err = 0;
68 : 0 : return MLX5_ADDR_OF(query_hca_cap_out, out, capability);
69 : : }
70 : :
71 : : /**
72 : : * Perform read access to the registers. Reads data from register
73 : : * and writes ones to the specified buffer.
74 : : *
75 : : * @param[in] ctx
76 : : * Context returned from mlx5 open_device() glue function.
77 : : * @param[in] reg_id
78 : : * Register identifier according to the PRM.
79 : : * @param[in] arg
80 : : * Register access auxiliary parameter according to the PRM.
81 : : * @param[out] data
82 : : * Pointer to the buffer to store read data.
83 : : * @param[in] dw_cnt
84 : : * Buffer size in double words.
85 : : *
86 : : * @return
87 : : * 0 on success, a negative value otherwise.
88 : : */
89 : : int
90 : 0 : mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg,
91 : : uint32_t *data, uint32_t dw_cnt)
92 : : {
93 : 0 : uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0};
94 : 0 : uint32_t out[MLX5_ST_SZ_DW(access_register_out) +
95 : : MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0};
96 : : int rc;
97 : :
98 : : MLX5_ASSERT(data && dw_cnt);
99 : : MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX);
100 [ # # ]: 0 : if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) {
101 : 0 : DRV_LOG(ERR, "Not enough buffer for register read data");
102 : 0 : return -1;
103 : : }
104 : 0 : MLX5_SET(access_register_in, in, opcode,
105 : : MLX5_CMD_OP_ACCESS_REGISTER_USER);
106 : 0 : MLX5_SET(access_register_in, in, op_mod,
107 : : MLX5_ACCESS_REGISTER_IN_OP_MOD_READ);
108 : 0 : MLX5_SET(access_register_in, in, register_id, reg_id);
109 : 0 : MLX5_SET(access_register_in, in, argument, arg);
110 : 0 : rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,
111 : 0 : MLX5_ST_SZ_BYTES(access_register_out) +
112 : : sizeof(uint32_t) * dw_cnt);
113 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
114 [ # # # # ]: 0 : DEVX_DRV_LOG(DEBUG, out, "read access", "NIC register", reg_id);
115 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
116 : : }
117 : 0 : memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)],
118 : : dw_cnt * sizeof(uint32_t));
119 : 0 : return 0;
120 : : }
121 : :
122 : : /**
123 : : * Perform write access to the registers.
124 : : *
125 : : * @param[in] ctx
126 : : * Context returned from mlx5 open_device() glue function.
127 : : * @param[in] reg_id
128 : : * Register identifier according to the PRM.
129 : : * @param[in] arg
130 : : * Register access auxiliary parameter according to the PRM.
131 : : * @param[out] data
132 : : * Pointer to the buffer containing data to write.
133 : : * @param[in] dw_cnt
134 : : * Buffer size in double words (32bit units).
135 : : *
136 : : * @return
137 : : * 0 on success, a negative value otherwise.
138 : : */
139 : : int
140 : 0 : mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, uint32_t arg,
141 : : uint32_t *data, uint32_t dw_cnt)
142 : : {
143 : 0 : uint32_t in[MLX5_ST_SZ_DW(access_register_in) +
144 : : MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0};
145 : 0 : uint32_t out[MLX5_ST_SZ_DW(access_register_out)] = {0};
146 : : int rc;
147 : : void *ptr;
148 : :
149 : : MLX5_ASSERT(data && dw_cnt);
150 : : MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX);
151 [ # # ]: 0 : if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) {
152 : 0 : DRV_LOG(ERR, "Data to write exceeds max size");
153 : 0 : return -1;
154 : : }
155 : 0 : MLX5_SET(access_register_in, in, opcode,
156 : : MLX5_CMD_OP_ACCESS_REGISTER_USER);
157 : 0 : MLX5_SET(access_register_in, in, op_mod,
158 : : MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE);
159 : 0 : MLX5_SET(access_register_in, in, register_id, reg_id);
160 : 0 : MLX5_SET(access_register_in, in, argument, arg);
161 : : ptr = MLX5_ADDR_OF(access_register_in, in, register_data);
162 : 0 : memcpy(ptr, data, dw_cnt * sizeof(uint32_t));
163 : 0 : rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
164 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
165 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "write access", "NIC register", reg_id);
166 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
167 : : }
168 : 0 : rc = mlx5_glue->devx_general_cmd(ctx, in,
169 : 0 : MLX5_ST_SZ_BYTES(access_register_in) +
170 : : dw_cnt * sizeof(uint32_t),
171 : : out, sizeof(out));
172 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
173 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "write access", "NIC register", reg_id);
174 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
175 : : }
176 : : return 0;
177 : : }
178 : :
179 : : struct mlx5_devx_obj *
180 : 0 : mlx5_devx_cmd_flow_counter_alloc_general(void *ctx,
181 : : struct mlx5_devx_counter_attr *attr)
182 : : {
183 : 0 : struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs),
184 : : 0, SOCKET_ID_ANY);
185 : 0 : uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0};
186 : 0 : uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0};
187 : :
188 [ # # ]: 0 : if (!dcs) {
189 : 0 : rte_errno = ENOMEM;
190 : 0 : return NULL;
191 : : }
192 : 0 : MLX5_SET(alloc_flow_counter_in, in, opcode,
193 : : MLX5_CMD_OP_ALLOC_FLOW_COUNTER);
194 [ # # ]: 0 : if (attr->bulk_log_max_alloc)
195 : 0 : MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk_log_size,
196 : : attr->flow_counter_bulk_log_size);
197 : : else
198 : 0 : MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk,
199 : : attr->bulk_n_128);
200 [ # # ]: 0 : if (attr->pd_valid)
201 : 0 : MLX5_SET(alloc_flow_counter_in, in, pd, attr->pd);
202 : 0 : dcs->obj = mlx5_glue->devx_obj_create(ctx, in,
203 : : sizeof(in), out, sizeof(out));
204 [ # # ]: 0 : if (!dcs->obj) {
205 : 0 : DRV_LOG(ERR, "Can't allocate counters - error %d", errno);
206 : 0 : rte_errno = errno;
207 : 0 : mlx5_free(dcs);
208 : 0 : return NULL;
209 : : }
210 [ # # ]: 0 : dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id);
211 : 0 : return dcs;
212 : : }
213 : :
214 : : /**
215 : : * Allocate flow counters via devx interface.
216 : : *
217 : : * @param[in] ctx
218 : : * Context returned from mlx5 open_device() glue function.
219 : : * @param dcs
220 : : * Pointer to counters properties structure to be filled by the routine.
221 : : * @param bulk_n_128
222 : : * Bulk counter numbers in 128 counters units.
223 : : *
224 : : * @return
225 : : * Pointer to counter object on success, a negative value otherwise and
226 : : * rte_errno is set.
227 : : */
228 : : struct mlx5_devx_obj *
229 : 0 : mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128)
230 : : {
231 : 0 : struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs),
232 : : 0, SOCKET_ID_ANY);
233 : 0 : uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0};
234 : 0 : uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0};
235 : :
236 [ # # ]: 0 : if (!dcs) {
237 : 0 : rte_errno = ENOMEM;
238 : 0 : return NULL;
239 : : }
240 : 0 : MLX5_SET(alloc_flow_counter_in, in, opcode,
241 : : MLX5_CMD_OP_ALLOC_FLOW_COUNTER);
242 : 0 : MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128);
243 : 0 : dcs->obj = mlx5_glue->devx_obj_create(ctx, in,
244 : : sizeof(in), out, sizeof(out));
245 [ # # ]: 0 : if (!dcs->obj) {
246 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "allocate counters", NULL, 0);
247 : 0 : mlx5_free(dcs);
248 : 0 : return NULL;
249 : : }
250 [ # # ]: 0 : dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id);
251 : 0 : return dcs;
252 : : }
253 : :
254 : : /**
255 : : * Query flow counters values.
256 : : *
257 : : * @param[in] dcs
258 : : * devx object that was obtained from mlx5_devx_cmd_fc_alloc.
259 : : * @param[in] clear
260 : : * Whether hardware should clear the counters after the query or not.
261 : : * @param[in] n_counters
262 : : * 0 in case of 1 counter to read, otherwise the counter number to read.
263 : : * @param pkts
264 : : * The number of packets that matched the flow.
265 : : * @param bytes
266 : : * The number of bytes that matched the flow.
267 : : * @param mkey
268 : : * The mkey key for batch query.
269 : : * @param addr
270 : : * The address in the mkey range for batch query.
271 : : * @param cmd_comp
272 : : * The completion object for asynchronous batch query.
273 : : * @param async_id
274 : : * The ID to be returned in the asynchronous batch query response.
275 : : *
276 : : * @return
277 : : * 0 on success, a negative value otherwise.
278 : : */
279 : : int
280 : 0 : mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
281 : : int clear, uint32_t n_counters,
282 : : uint64_t *pkts, uint64_t *bytes,
283 : : uint32_t mkey, void *addr,
284 : : void *cmd_comp,
285 : : uint64_t async_id)
286 : : {
287 : : uint32_t out[MLX5_ST_SZ_BYTES(query_flow_counter_out) + MLX5_ST_SZ_BYTES(traffic_counter)];
288 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0};
289 : : const int out_len = RTE_DIM(out);
290 : : void *stats;
291 : : int rc;
292 : :
293 : 0 : MLX5_SET(query_flow_counter_in, in, opcode,
294 : : MLX5_CMD_OP_QUERY_FLOW_COUNTER);
295 : 0 : MLX5_SET(query_flow_counter_in, in, op_mod, 0);
296 : 0 : MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id);
297 : 0 : MLX5_SET(query_flow_counter_in, in, clear, !!clear);
298 : :
299 [ # # ]: 0 : if (n_counters) {
300 [ # # ]: 0 : MLX5_SET(query_flow_counter_in, in, num_of_counters,
301 : : n_counters);
302 [ # # ]: 0 : MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1);
303 : 0 : MLX5_SET(query_flow_counter_in, in, mkey, mkey);
304 : 0 : MLX5_SET64(query_flow_counter_in, in, address,
305 : : (uint64_t)(uintptr_t)addr);
306 : : }
307 [ # # ]: 0 : if (!cmd_comp)
308 : 0 : rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
309 : : out_len);
310 : : else
311 : 0 : rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in),
312 : : out_len, async_id,
313 : : cmd_comp);
314 [ # # ]: 0 : if (rc) {
315 : 0 : DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc);
316 : 0 : rte_errno = rc;
317 : 0 : return -rc;
318 : : }
319 [ # # ]: 0 : if (!n_counters) {
320 : : stats = MLX5_ADDR_OF(query_flow_counter_out,
321 : : out, flow_statistics);
322 [ # # ]: 0 : *pkts = MLX5_GET64(traffic_counter, stats, packets);
323 [ # # ]: 0 : *bytes = MLX5_GET64(traffic_counter, stats, octets);
324 : : }
325 : : return 0;
326 : : }
327 : :
328 : : /**
329 : : * Create a new mkey.
330 : : *
331 : : * @param[in] ctx
332 : : * Context returned from mlx5 open_device() glue function.
333 : : * @param[in] attr
334 : : * Attributes of the requested mkey.
335 : : *
336 : : * @return
337 : : * Pointer to Devx mkey on success, a negative value otherwise and rte_errno
338 : : * is set.
339 : : */
340 : : struct mlx5_devx_obj *
341 : 0 : mlx5_devx_cmd_mkey_create(void *ctx,
342 : : struct mlx5_devx_mkey_attr *attr)
343 : : {
344 : 0 : struct mlx5_klm *klm_array = attr->klm_array;
345 : 0 : int klm_num = attr->klm_num;
346 [ # # ]: 0 : int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) +
347 : 0 : (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm);
348 : 0 : uint32_t *in = alloca(sizeof(uint32_t) * in_size_dw);
349 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0};
350 : : void *mkc;
351 : 0 : struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey),
352 : : 0, SOCKET_ID_ANY);
353 : : size_t pgsize;
354 : : uint32_t translation_size;
355 : :
356 [ # # ]: 0 : if (!mkey) {
357 : 0 : rte_errno = ENOMEM;
358 : 0 : return NULL;
359 : : }
360 : : memset(in, 0, in_size_dw * 4);
361 : 0 : pgsize = rte_mem_page_size();
362 [ # # ]: 0 : if (pgsize == (size_t)-1) {
363 : 0 : mlx5_free(mkey);
364 : 0 : DRV_LOG(ERR, "Failed to get page size");
365 : 0 : rte_errno = ENOMEM;
366 : 0 : return NULL;
367 : : }
368 [ # # ]: 0 : MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY);
369 : : mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
370 [ # # ]: 0 : if (klm_num > 0) {
371 : : int i;
372 : 0 : uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in,
373 : : klm_pas_mtt);
374 : 0 : translation_size = RTE_ALIGN(klm_num, 4);
375 [ # # ]: 0 : for (i = 0; i < klm_num; i++) {
376 [ # # ]: 0 : MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count);
377 [ # # ]: 0 : MLX5_SET(klm, klm, mkey, klm_array[i].mkey);
378 [ # # ]: 0 : MLX5_SET64(klm, klm, address, klm_array[i].address);
379 : 0 : klm += MLX5_ST_SZ_BYTES(klm);
380 : : }
381 [ # # ]: 0 : for (; i < (int)translation_size; i++) {
382 [ # # ]: 0 : MLX5_SET(klm, klm, mkey, 0x0);
383 : 0 : MLX5_SET64(klm, klm, address, 0x0);
384 : 0 : klm += MLX5_ST_SZ_BYTES(klm);
385 : : }
386 [ # # # # ]: 0 : MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ?
387 : : MLX5_MKC_ACCESS_MODE_KLM_FBS :
388 : : MLX5_MKC_ACCESS_MODE_KLM);
389 [ # # ]: 0 : MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size);
390 : : } else {
391 : 0 : translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16;
392 [ # # ]: 0 : MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
393 [ # # # # ]: 0 : MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize));
394 : : }
395 [ # # ]: 0 : MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
396 : : translation_size);
397 [ # # ]: 0 : MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id);
398 [ # # ]: 0 : MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access);
399 [ # # ]: 0 : MLX5_SET(mkc, mkc, lw, 0x1);
400 [ # # ]: 0 : MLX5_SET(mkc, mkc, lr, 0x1);
401 [ # # ]: 0 : if (attr->set_remote_rw) {
402 [ # # ]: 0 : MLX5_SET(mkc, mkc, rw, 0x1);
403 [ # # ]: 0 : MLX5_SET(mkc, mkc, rr, 0x1);
404 : : }
405 [ # # ]: 0 : MLX5_SET(mkc, mkc, qpn, 0xffffff);
406 [ # # ]: 0 : MLX5_SET(mkc, mkc, pd, attr->pd);
407 [ # # ]: 0 : MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF);
408 [ # # ]: 0 : MLX5_SET(mkc, mkc, umr_en, attr->umr_en);
409 [ # # ]: 0 : MLX5_SET(mkc, mkc, translations_octword_size, translation_size);
410 [ # # ]: 0 : MLX5_SET(mkc, mkc, relaxed_ordering_write,
411 : : attr->relaxed_ordering_write);
412 [ # # ]: 0 : MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read);
413 [ # # ]: 0 : MLX5_SET64(mkc, mkc, start_addr, attr->addr);
414 [ # # ]: 0 : MLX5_SET64(mkc, mkc, len, attr->size);
415 [ # # ]: 0 : MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en);
416 [ # # ]: 0 : if (attr->crypto_en) {
417 [ # # ]: 0 : MLX5_SET(mkc, mkc, bsf_en, attr->crypto_en);
418 [ # # ]: 0 : MLX5_SET(mkc, mkc, bsf_octword_size, 4);
419 : : }
420 : 0 : mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out,
421 : : sizeof(out));
422 [ # # ]: 0 : if (!mkey->obj) {
423 [ # # # # : 0 : DEVX_DRV_LOG(ERR, out, klm_num ? "create indirect mkey"
# # ]
424 : : : "create direct key", NULL, 0);
425 : 0 : mlx5_free(mkey);
426 : 0 : return NULL;
427 : : }
428 [ # # ]: 0 : mkey->id = MLX5_GET(create_mkey_out, out, mkey_index);
429 : 0 : mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF);
430 : 0 : return mkey;
431 : : }
432 : :
433 : : /**
434 : : * Get status of devx command response.
435 : : * Mainly used for asynchronous commands.
436 : : *
437 : : * @param[in] out
438 : : * The out response buffer.
439 : : *
440 : : * @return
441 : : * 0 on success, non-zero value otherwise.
442 : : */
443 : : int
444 : 0 : mlx5_devx_get_out_command_status(void *out)
445 : : {
446 : : int status;
447 : :
448 [ # # ]: 0 : if (!out)
449 : : return -EINVAL;
450 [ # # ]: 0 : status = MLX5_GET(query_flow_counter_out, out, status);
451 [ # # ]: 0 : if (status) {
452 [ # # ]: 0 : int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome);
453 : :
454 : 0 : DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status,
455 : : syndrome);
456 : : }
457 : : return status;
458 : : }
459 : :
460 : : /**
461 : : * Destroy any object allocated by a Devx API.
462 : : *
463 : : * @param[in] obj
464 : : * Pointer to a general object.
465 : : *
466 : : * @return
467 : : * 0 on success, a negative value otherwise.
468 : : */
469 : : int
470 : 0 : mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj)
471 : : {
472 : : int ret;
473 : :
474 [ # # ]: 0 : if (!obj)
475 : : return 0;
476 : 0 : ret = mlx5_glue->devx_obj_destroy(obj->obj);
477 : 0 : mlx5_free(obj);
478 : 0 : return ret;
479 : : }
480 : :
481 : : /**
482 : : * Query NIC vport context.
483 : : * Fills minimal inline attribute.
484 : : *
485 : : * @param[in] ctx
486 : : * ibv contexts returned from mlx5dv_open_device.
487 : : * @param[in] vport
488 : : * vport index
489 : : * @param[out] attr
490 : : * Attributes device values.
491 : : *
492 : : * @return
493 : : * 0 on success, a negative value otherwise.
494 : : */
495 : : static int
496 : 0 : mlx5_devx_cmd_query_nic_vport_context(void *ctx,
497 : : unsigned int vport,
498 : : struct mlx5_hca_attr *attr)
499 : : {
500 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0};
501 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0};
502 : : void *vctx;
503 : : int rc;
504 : :
505 : : /* Query NIC vport context to determine inline mode. */
506 : 0 : MLX5_SET(query_nic_vport_context_in, in, opcode,
507 : : MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT);
508 : 0 : MLX5_SET(query_nic_vport_context_in, in, vport_number, vport);
509 [ # # ]: 0 : if (vport)
510 [ # # ]: 0 : MLX5_SET(query_nic_vport_context_in, in, other_vport, 1);
511 : 0 : rc = mlx5_glue->devx_general_cmd(ctx,
512 : : in, sizeof(in),
513 : : out, sizeof(out));
514 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
515 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "query NIC vport context", NULL, 0);
516 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
517 : : }
518 : : vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out,
519 : : nic_vport_context);
520 [ # # ]: 0 : if (attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
521 [ # # ]: 0 : attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx,
522 : : min_wqe_inline_mode);
523 [ # # ]: 0 : attr->system_image_guid = MLX5_GET64(nic_vport_context, vctx,
524 : : system_image_guid);
525 : 0 : return 0;
526 : : }
527 : :
528 : : /**
529 : : * Query NIC vDPA attributes.
530 : : *
531 : : * @param[in] ctx
532 : : * Context returned from mlx5 open_device() glue function.
533 : : * @param[out] vdpa_attr
534 : : * vDPA Attributes structure to fill.
535 : : */
536 : : static void
537 : 0 : mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx,
538 : : struct mlx5_hca_vdpa_attr *vdpa_attr)
539 : : {
540 : : uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)];
541 : : uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)];
542 : : void *hcattr;
543 : :
544 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, NULL,
545 : : MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION |
546 : : MLX5_HCA_CAP_OPMOD_GET_CUR);
547 [ # # ]: 0 : if (!hcattr) {
548 : 0 : DRV_LOG(DEBUG, "Failed to query devx VDPA capabilities");
549 : 0 : vdpa_attr->valid = 0;
550 : : } else {
551 : 0 : vdpa_attr->valid = 1;
552 : 0 : vdpa_attr->desc_tunnel_offload_type =
553 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
554 : : desc_tunnel_offload_type);
555 : 0 : vdpa_attr->eth_frame_offload_type =
556 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
557 : : eth_frame_offload_type);
558 : 0 : vdpa_attr->virtio_version_1_0 =
559 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
560 : : virtio_version_1_0);
561 [ # # ]: 0 : vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr,
562 : : tso_ipv4);
563 [ # # ]: 0 : vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr,
564 : : tso_ipv6);
565 [ # # ]: 0 : vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
566 : : tx_csum);
567 [ # # ]: 0 : vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
568 : : rx_csum);
569 [ # # ]: 0 : vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr,
570 : : event_mode);
571 : 0 : vdpa_attr->virtio_queue_type =
572 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
573 : : virtio_queue_type);
574 : 0 : vdpa_attr->log_doorbell_stride =
575 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
576 : : log_doorbell_stride);
577 : 0 : vdpa_attr->vnet_modify_ext =
578 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
579 : : vnet_modify_ext);
580 : 0 : vdpa_attr->virtio_net_q_addr_modify =
581 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
582 : : virtio_net_q_addr_modify);
583 : 0 : vdpa_attr->virtio_q_index_modify =
584 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
585 : : virtio_q_index_modify);
586 : 0 : vdpa_attr->log_doorbell_bar_size =
587 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
588 : : log_doorbell_bar_size);
589 : 0 : vdpa_attr->doorbell_bar_offset =
590 [ # # ]: 0 : MLX5_GET64(virtio_emulation_cap, hcattr,
591 : : doorbell_bar_offset);
592 : 0 : vdpa_attr->max_num_virtio_queues =
593 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
594 : : max_num_virtio_queues);
595 [ # # ]: 0 : vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr,
596 : : umem_1_buffer_param_a);
597 [ # # ]: 0 : vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr,
598 : : umem_1_buffer_param_b);
599 [ # # ]: 0 : vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr,
600 : : umem_2_buffer_param_a);
601 [ # # ]: 0 : vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr,
602 : : umem_2_buffer_param_b);
603 [ # # ]: 0 : vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr,
604 : : umem_3_buffer_param_a);
605 [ # # ]: 0 : vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr,
606 : : umem_3_buffer_param_b);
607 : : }
608 : 0 : }
609 : :
610 : : /**
611 : : * Query match sample handle parameters.
612 : : *
613 : : * This command allows translating a field sample handle returned by either
614 : : * PARSE_GRAPH_FLOW_MATCH_SAMPLE or by GENEVE TLV OPTION object into values
615 : : * used for header modification or header matching/hashing.
616 : : *
617 : : * @param[in] ctx
618 : : * Context used to create either GENEVE TLV option or FLEX PARSE GRAPH object.
619 : : * @param[in] sample_field_id
620 : : * Field sample handle returned by either PARSE_GRAPH_FLOW_MATCH_SAMPLE
621 : : * or by GENEVE TLV OPTION object.
622 : : * @param[out] attr
623 : : * Pointer to match sample info attributes structure.
624 : : *
625 : : * @return
626 : : * 0 on success, a negative errno otherwise and rte_errno is set.
627 : : */
628 : : int
629 : 0 : mlx5_devx_cmd_match_sample_info_query(void *ctx, uint32_t sample_field_id,
630 : : struct mlx5_devx_match_sample_info_query_attr *attr)
631 : : {
632 : : #ifdef HAVE_IBV_FLOW_DV_SUPPORT
633 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_match_sample_info_out)] = {0};
634 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_match_sample_info_in)] = {0};
635 : : int rc;
636 : :
637 : 0 : MLX5_SET(query_match_sample_info_in, in, opcode,
638 : : MLX5_CMD_OP_QUERY_MATCH_SAMPLE_INFO);
639 : 0 : MLX5_SET(query_match_sample_info_in, in, op_mod, 0);
640 : 0 : MLX5_SET(query_match_sample_info_in, in, sample_field_id,
641 : : sample_field_id);
642 : 0 : rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
643 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
644 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "query match sample info",
645 : : "sample_field_id", sample_field_id);
646 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
647 : : }
648 [ # # ]: 0 : attr->modify_field_id = MLX5_GET(query_match_sample_info_out, out,
649 : : modify_field_id);
650 [ # # ]: 0 : attr->sample_dw_data = MLX5_GET(query_match_sample_info_out, out,
651 : : field_format_select_dw);
652 [ # # ]: 0 : attr->sample_dw_ok_bit = MLX5_GET(query_match_sample_info_out, out,
653 : : ok_bit_format_select_dw);
654 [ # # ]: 0 : attr->sample_dw_ok_bit_offset = MLX5_GET(query_match_sample_info_out,
655 : : out, ok_bit_offset);
656 : 0 : return 0;
657 : : #else
658 : : (void)ctx;
659 : : (void)sample_field_id;
660 : : (void)attr;
661 : : return -ENOTSUP;
662 : : #endif
663 : : }
664 : :
665 : : int
666 : 0 : mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,
667 : : uint32_t *ids,
668 : : uint32_t num, uint8_t *anchor)
669 : : {
670 : 0 : uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
671 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0};
672 : : void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr);
673 : : void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex);
674 : : void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
675 : : int ret;
676 : : uint32_t idx = 0;
677 : : uint32_t i;
678 : :
679 [ # # ]: 0 : if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) {
680 : 0 : rte_errno = EINVAL;
681 : 0 : DRV_LOG(ERR, "Too many sample IDs to be fetched.");
682 : 0 : return -rte_errno;
683 : : }
684 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
685 : : MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
686 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
687 : : MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
688 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id);
689 : 0 : ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in),
690 : : out, sizeof(out));
691 [ # # ]: 0 : if (ret) {
692 : 0 : rte_errno = ret;
693 : 0 : DRV_LOG(ERR, "Failed to query sample IDs with object %p.",
694 : : (void *)flex_obj);
695 : 0 : return -rte_errno;
696 : : }
697 [ # # ]: 0 : if (anchor)
698 [ # # ]: 0 : *anchor = MLX5_GET(parse_graph_flex, flex, head_anchor_id);
699 [ # # ]: 0 : for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM && idx < num; i++) {
700 : 0 : void *s_off = (void *)((char *)sample + i *
701 : : MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
702 : : uint32_t en;
703 : :
704 [ # # ]: 0 : en = MLX5_GET(parse_graph_flow_match_sample, s_off,
705 : : flow_match_sample_en);
706 [ # # ]: 0 : if (!en)
707 : 0 : continue;
708 [ # # ]: 0 : ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off,
709 : : flow_match_sample_field_id);
710 : : }
711 [ # # ]: 0 : if (num != idx) {
712 : 0 : rte_errno = EINVAL;
713 : 0 : DRV_LOG(ERR, "Number of sample IDs are not as expected.");
714 : 0 : return -rte_errno;
715 : : }
716 : : return ret;
717 : : }
718 : :
719 : : struct mlx5_devx_obj *
720 : 0 : mlx5_devx_cmd_create_flex_parser(void *ctx,
721 : : struct mlx5_devx_graph_node_attr *data)
722 : : {
723 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0};
724 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
725 : : void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr);
726 : : void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex);
727 : : void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
728 : : void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc);
729 : : void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc);
730 : 0 : struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc
731 : : (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY);
732 : : uint32_t i;
733 : :
734 [ # # ]: 0 : if (!parse_flex_obj) {
735 : 0 : DRV_LOG(ERR, "Failed to allocate flex parser data.");
736 : 0 : rte_errno = ENOMEM;
737 : 0 : return NULL;
738 : : }
739 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
740 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
741 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
742 : : MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
743 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, header_length_mode,
744 : : data->header_length_mode);
745 [ # # ]: 0 : MLX5_SET64(parse_graph_flex, flex, modify_field_select,
746 : : data->modify_field_select);
747 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, header_length_base_value,
748 : : data->header_length_base_value);
749 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, header_length_field_offset,
750 : : data->header_length_field_offset);
751 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, header_length_field_shift,
752 : : data->header_length_field_shift);
753 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, next_header_field_offset,
754 : : data->next_header_field_offset);
755 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, next_header_field_size,
756 : : data->next_header_field_size);
757 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, header_length_field_mask,
758 : : data->header_length_field_mask);
759 [ # # ]: 0 : for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {
760 : : struct mlx5_devx_match_sample_attr *s = &data->sample[i];
761 : 0 : void *s_off = (void *)((char *)sample + i *
762 : : MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
763 : :
764 [ # # ]: 0 : if (!s->flow_match_sample_en)
765 : 0 : continue;
766 [ # # ]: 0 : MLX5_SET(parse_graph_flow_match_sample, s_off,
767 : : flow_match_sample_en, !!s->flow_match_sample_en);
768 [ # # ]: 0 : MLX5_SET(parse_graph_flow_match_sample, s_off,
769 : : flow_match_sample_field_offset,
770 : : s->flow_match_sample_field_offset);
771 [ # # ]: 0 : MLX5_SET(parse_graph_flow_match_sample, s_off,
772 : : flow_match_sample_offset_mode,
773 : : s->flow_match_sample_offset_mode);
774 [ # # ]: 0 : MLX5_SET(parse_graph_flow_match_sample, s_off,
775 : : flow_match_sample_field_offset_mask,
776 : : s->flow_match_sample_field_offset_mask);
777 [ # # ]: 0 : MLX5_SET(parse_graph_flow_match_sample, s_off,
778 : : flow_match_sample_field_offset_shift,
779 : : s->flow_match_sample_field_offset_shift);
780 [ # # ]: 0 : MLX5_SET(parse_graph_flow_match_sample, s_off,
781 : : flow_match_sample_field_base_offset,
782 : : s->flow_match_sample_field_base_offset);
783 [ # # ]: 0 : MLX5_SET(parse_graph_flow_match_sample, s_off,
784 : : flow_match_sample_tunnel_mode,
785 : : s->flow_match_sample_tunnel_mode);
786 : : }
787 [ # # ]: 0 : for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) {
788 : : struct mlx5_devx_graph_arc_attr *ia = &data->in[i];
789 : : struct mlx5_devx_graph_arc_attr *oa = &data->out[i];
790 : 0 : void *in_off = (void *)((char *)in_arc + i *
791 : : MLX5_ST_SZ_BYTES(parse_graph_arc));
792 : 0 : void *out_off = (void *)((char *)out_arc + i *
793 : : MLX5_ST_SZ_BYTES(parse_graph_arc));
794 : :
795 [ # # ]: 0 : if (ia->arc_parse_graph_node != 0) {
796 [ # # ]: 0 : MLX5_SET(parse_graph_arc, in_off,
797 : : compare_condition_value,
798 : : ia->compare_condition_value);
799 [ # # ]: 0 : MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel,
800 : : ia->start_inner_tunnel);
801 [ # # ]: 0 : MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node,
802 : : ia->arc_parse_graph_node);
803 [ # # ]: 0 : MLX5_SET(parse_graph_arc, in_off,
804 : : parse_graph_node_handle,
805 : : ia->parse_graph_node_handle);
806 : : }
807 [ # # ]: 0 : if (oa->arc_parse_graph_node != 0) {
808 [ # # ]: 0 : MLX5_SET(parse_graph_arc, out_off,
809 : : compare_condition_value,
810 : : oa->compare_condition_value);
811 [ # # ]: 0 : MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel,
812 : : oa->start_inner_tunnel);
813 [ # # ]: 0 : MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node,
814 : : oa->arc_parse_graph_node);
815 [ # # ]: 0 : MLX5_SET(parse_graph_arc, out_off,
816 : : parse_graph_node_handle,
817 : : oa->parse_graph_node_handle);
818 : : }
819 : : }
820 : 0 : parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
821 : : out, sizeof(out));
822 [ # # ]: 0 : if (!parse_flex_obj->obj) {
823 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create FLEX PARSE GRAPH", NULL, 0);
824 : 0 : mlx5_free(parse_flex_obj);
825 : 0 : return NULL;
826 : : }
827 [ # # ]: 0 : parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
828 : 0 : return parse_flex_obj;
829 : : }
830 : :
831 : : static int
832 : 0 : mlx5_devx_cmd_query_hca_parse_graph_node_cap
833 : : (void *ctx, struct mlx5_hca_flex_attr *attr)
834 : : {
835 : : uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)];
836 : : uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)];
837 : : void *hcattr;
838 : : int rc;
839 : :
840 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
841 : : MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP |
842 : : MLX5_HCA_CAP_OPMOD_GET_CUR);
843 [ # # ]: 0 : if (!hcattr)
844 : 0 : return rc;
845 [ # # ]: 0 : attr->node_in = MLX5_GET(parse_graph_node_cap, hcattr, node_in);
846 [ # # ]: 0 : attr->node_out = MLX5_GET(parse_graph_node_cap, hcattr, node_out);
847 [ # # ]: 0 : attr->header_length_mode = MLX5_GET(parse_graph_node_cap, hcattr,
848 : : header_length_mode);
849 [ # # ]: 0 : attr->sample_offset_mode = MLX5_GET(parse_graph_node_cap, hcattr,
850 : : sample_offset_mode);
851 [ # # ]: 0 : attr->max_num_arc_in = MLX5_GET(parse_graph_node_cap, hcattr,
852 : : max_num_arc_in);
853 [ # # ]: 0 : attr->max_num_arc_out = MLX5_GET(parse_graph_node_cap, hcattr,
854 : : max_num_arc_out);
855 [ # # ]: 0 : attr->max_num_sample = MLX5_GET(parse_graph_node_cap, hcattr,
856 : : max_num_sample);
857 [ # # ]: 0 : attr->parse_graph_anchor = MLX5_GET(parse_graph_node_cap, hcattr, parse_graph_anchor);
858 [ # # ]: 0 : attr->sample_tunnel_inner2 = MLX5_GET(parse_graph_node_cap, hcattr,
859 : : sample_tunnel_inner2);
860 [ # # ]: 0 : attr->zero_size_supported = MLX5_GET(parse_graph_node_cap, hcattr,
861 : : zero_size_supported);
862 [ # # ]: 0 : attr->sample_id_in_out = MLX5_GET(parse_graph_node_cap, hcattr,
863 : : sample_id_in_out);
864 [ # # ]: 0 : attr->max_base_header_length = MLX5_GET(parse_graph_node_cap, hcattr,
865 : : max_base_header_length);
866 [ # # ]: 0 : attr->max_sample_base_offset = MLX5_GET(parse_graph_node_cap, hcattr,
867 : : max_sample_base_offset);
868 [ # # ]: 0 : attr->max_next_header_offset = MLX5_GET(parse_graph_node_cap, hcattr,
869 : : max_next_header_offset);
870 [ # # ]: 0 : attr->header_length_mask_width = MLX5_GET(parse_graph_node_cap, hcattr,
871 : : header_length_mask_width);
872 : : /* Get the max supported samples from HCA CAP 2 */
873 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
874 : : MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 |
875 : : MLX5_HCA_CAP_OPMOD_GET_CUR);
876 [ # # ]: 0 : if (!hcattr)
877 : 0 : return rc;
878 : 0 : attr->max_num_prog_sample =
879 [ # # ]: 0 : MLX5_GET(cmd_hca_cap_2, hcattr, max_num_prog_sample_field);
880 : 0 : return 0;
881 : : }
882 : :
883 : : static int
884 : 0 : mlx5_devx_query_pkt_integrity_match(void *hcattr)
885 : : {
886 [ # # ]: 0 : return MLX5_GET(flow_table_nic_cap, hcattr,
887 [ # # # # ]: 0 : ft_field_support_2_nic_receive.inner_l3_ok) &&
888 : : MLX5_GET(flow_table_nic_cap, hcattr,
889 [ # # # # ]: 0 : ft_field_support_2_nic_receive.inner_l4_ok) &&
890 : : MLX5_GET(flow_table_nic_cap, hcattr,
891 [ # # # # ]: 0 : ft_field_support_2_nic_receive.outer_l3_ok) &&
892 : : MLX5_GET(flow_table_nic_cap, hcattr,
893 [ # # # # ]: 0 : ft_field_support_2_nic_receive.outer_l4_ok) &&
894 : : MLX5_GET(flow_table_nic_cap, hcattr,
895 : : ft_field_support_2_nic_receive
896 [ # # # # ]: 0 : .inner_ipv4_checksum_ok) &&
897 : : MLX5_GET(flow_table_nic_cap, hcattr,
898 [ # # # # ]: 0 : ft_field_support_2_nic_receive.inner_l4_checksum_ok) &&
899 : : MLX5_GET(flow_table_nic_cap, hcattr,
900 : : ft_field_support_2_nic_receive
901 [ # # # # : 0 : .outer_ipv4_checksum_ok) &&
# # # # #
# # # # #
# # # # ]
902 [ # # # # ]: 0 : MLX5_GET(flow_table_nic_cap, hcattr,
903 : : ft_field_support_2_nic_receive.outer_l4_checksum_ok);
904 : : }
905 : :
906 : : /**
907 : : * Query HCA attributes.
908 : : * Using those attributes we can check on run time if the device
909 : : * is having the required capabilities.
910 : : *
911 : : * @param[in] ctx
912 : : * Context returned from mlx5 open_device() glue function.
913 : : * @param[out] attr
914 : : * Attributes device values.
915 : : *
916 : : * @return
917 : : * 0 on success, a negative value otherwise.
918 : : */
919 : : int
920 : 0 : mlx5_devx_cmd_query_hca_attr(void *ctx,
921 : : struct mlx5_hca_attr *attr)
922 : : {
923 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
924 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
925 : : bool hca_cap_2_sup;
926 : : uint64_t general_obj_types_supported = 0;
927 : : uint64_t stc_action_type_127_64;
928 : : void *hcattr;
929 : : int rc, i;
930 : :
931 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
932 : : MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE |
933 : : MLX5_HCA_CAP_OPMOD_GET_CUR);
934 [ # # ]: 0 : if (!hcattr)
935 : 0 : return rc;
936 [ # # ]: 0 : hca_cap_2_sup = MLX5_GET(cmd_hca_cap, hcattr, hca_cap_2);
937 [ # # ]: 0 : attr->max_wqe_sz_sq = MLX5_GET(cmd_hca_cap, hcattr, max_wqe_sz_sq);
938 : 0 : attr->flow_counter_bulk_alloc_bitmap =
939 [ # # ]: 0 : MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc);
940 [ # # ]: 0 : attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr,
941 : : flow_counters_dump);
942 [ # # ]: 0 : attr->log_max_rmp = MLX5_GET(cmd_hca_cap, hcattr, log_max_rmp);
943 [ # # ]: 0 : attr->mem_rq_rmp = MLX5_GET(cmd_hca_cap, hcattr, mem_rq_rmp);
944 [ # # ]: 0 : attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr,
945 : : log_max_rqt_size);
946 [ # # ]: 0 : attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager);
947 [ # # ]: 0 : attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin);
948 [ # # ]: 0 : attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr,
949 : : log_max_hairpin_queues);
950 [ # # ]: 0 : attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr,
951 : : log_max_hairpin_wq_data_sz);
952 [ # # ]: 0 : attr->log_max_hairpin_num_packets = MLX5_GET
953 : : (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz);
954 [ # # ]: 0 : attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id);
955 [ # # ]: 0 : attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr,
956 : : relaxed_ordering_write);
957 [ # # ]: 0 : attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr,
958 : : relaxed_ordering_read);
959 [ # # ]: 0 : attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr,
960 : : access_register_user);
961 [ # # ]: 0 : attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr,
962 : : eth_net_offloads);
963 [ # # ]: 0 : attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);
964 [ # # ]: 0 : attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr,
965 : : flex_parser_protocols);
966 [ # # ]: 0 : attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr,
967 : : max_geneve_tlv_options);
968 [ # # ]: 0 : attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr,
969 : : max_geneve_tlv_option_data_len);
970 [ # # ]: 0 : attr->geneve_tlv_option_offset = MLX5_GET(cmd_hca_cap, hcattr,
971 : : geneve_tlv_option_offset);
972 [ # # ]: 0 : attr->geneve_tlv_sample = MLX5_GET(cmd_hca_cap, hcattr,
973 : : geneve_tlv_sample);
974 [ # # ]: 0 : attr->query_match_sample_info = MLX5_GET(cmd_hca_cap, hcattr,
975 : : query_match_sample_info);
976 [ # # ]: 0 : attr->geneve_tlv_option_sample_id = MLX5_GET(cmd_hca_cap, hcattr,
977 : : flex_parser_id_geneve_opt_0);
978 [ # # ]: 0 : attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos);
979 [ # # ]: 0 : attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr,
980 : : wqe_index_ignore_cap);
981 [ # # ]: 0 : attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd);
982 [ # # ]: 0 : attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq);
983 [ # # ]: 0 : attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr,
984 : : log_max_static_sq_wq);
985 [ # # ]: 0 : attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports);
986 [ # # ]: 0 : attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr,
987 : : device_frequency_khz);
988 : 0 : attr->scatter_fcs_w_decap_disable =
989 [ # # ]: 0 : MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable);
990 [ # # ]: 0 : attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce);
991 [ # # ]: 0 : attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format);
992 [ # # ]: 0 : attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format);
993 : 0 : attr->steering_format_version =
994 [ # # ]: 0 : MLX5_GET(cmd_hca_cap, hcattr, steering_format_version);
995 [ # # ]: 0 : attr->regexp_params = MLX5_GET(cmd_hca_cap, hcattr, regexp_params);
996 [ # # ]: 0 : attr->regexp_version = MLX5_GET(cmd_hca_cap, hcattr, regexp_version);
997 [ # # ]: 0 : attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr,
998 : : regexp_num_of_engines);
999 : : /* Read the general_obj_types bitmap and extract the relevant bits. */
1000 [ # # ]: 0 : general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr,
1001 : : general_obj_types);
1002 : 0 : attr->qos.flow_meter_aso_sup =
1003 : 0 : !!(general_obj_types_supported &
1004 : : MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO);
1005 : 0 : attr->vdpa.valid = !!(general_obj_types_supported &
1006 : : MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q);
1007 : 0 : attr->vdpa.queue_counters_valid =
1008 : 0 : !!(general_obj_types_supported &
1009 : : MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS);
1010 : 0 : attr->parse_graph_flex_node =
1011 : 0 : !!(general_obj_types_supported &
1012 : : MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE);
1013 : 0 : attr->flow_hit_aso = !!(general_obj_types_supported &
1014 : : MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO);
1015 : 0 : attr->geneve_tlv_opt = !!(general_obj_types_supported &
1016 : : MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT);
1017 : 0 : attr->dek = !!(general_obj_types_supported &
1018 : : MLX5_GENERAL_OBJ_TYPES_CAP_DEK);
1019 : 0 : attr->import_kek = !!(general_obj_types_supported &
1020 : : MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK);
1021 : 0 : attr->credential = !!(general_obj_types_supported &
1022 : : MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL);
1023 : 0 : attr->crypto_login = !!(general_obj_types_supported &
1024 : : MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN);
1025 : : /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */
1026 [ # # ]: 0 : attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq);
1027 [ # # ]: 0 : attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp);
1028 [ # # ]: 0 : attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz);
1029 [ # # ]: 0 : attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz);
1030 [ # # ]: 0 : attr->log_max_wq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_wq_sz);
1031 [ # # ]: 0 : attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz);
1032 [ # # ]: 0 : attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd);
1033 [ # # ]: 0 : attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq);
1034 [ # # ]: 0 : attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz);
1035 : 0 : attr->reg_c_preserve =
1036 [ # # ]: 0 : MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve);
1037 [ # # ]: 0 : attr->mmo_regex_qp_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_qp);
1038 [ # # ]: 0 : attr->mmo_regex_sq_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_sq);
1039 [ # # ]: 0 : attr->mmo_dma_sq_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_sq);
1040 [ # # ]: 0 : attr->mmo_compress_sq_en = MLX5_GET(cmd_hca_cap, hcattr,
1041 : : compress_mmo_sq);
1042 [ # # ]: 0 : attr->mmo_decompress_sq_en = MLX5_GET(cmd_hca_cap, hcattr,
1043 : : decompress_mmo_sq);
1044 [ # # ]: 0 : attr->mmo_dma_qp_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_qp);
1045 [ # # ]: 0 : attr->mmo_compress_qp_en = MLX5_GET(cmd_hca_cap, hcattr,
1046 : : compress_mmo_qp);
1047 [ # # ]: 0 : attr->decomp_deflate_v1_en = MLX5_GET(cmd_hca_cap, hcattr,
1048 : : decompress_deflate_v1);
1049 [ # # ]: 0 : attr->decomp_deflate_v2_en = MLX5_GET(cmd_hca_cap, hcattr,
1050 : : decompress_deflate_v2);
1051 [ # # ]: 0 : attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr,
1052 : : compress_min_block_size);
1053 [ # # ]: 0 : attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size);
1054 [ # # ]: 0 : attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr,
1055 : : log_compress_mmo_size);
1056 [ # # ]: 0 : attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr,
1057 : : log_decompress_mmo_size);
1058 [ # # ]: 0 : attr->decomp_lz4_data_only_en = MLX5_GET(cmd_hca_cap, hcattr,
1059 : : decompress_lz4_data_only_v2);
1060 [ # # ]: 0 : attr->decomp_lz4_no_checksum_en = MLX5_GET(cmd_hca_cap, hcattr,
1061 : : decompress_lz4_no_checksum_v2);
1062 [ # # ]: 0 : attr->decomp_lz4_checksum_en = MLX5_GET(cmd_hca_cap, hcattr,
1063 : : decompress_lz4_checksum_v2);
1064 [ # # ]: 0 : attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression);
1065 [ # # ]: 0 : attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr,
1066 : : mini_cqe_resp_flow_tag);
1067 [ # # ]: 0 : attr->cqe_compression_128 = MLX5_GET(cmd_hca_cap, hcattr,
1068 : : cqe_compression_128);
1069 [ # # ]: 0 : attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr,
1070 : : mini_cqe_resp_l3_l4_tag);
1071 [ # # ]: 0 : attr->enhanced_cqe_compression = MLX5_GET(cmd_hca_cap, hcattr,
1072 : : enhanced_cqe_compression);
1073 : 0 : attr->umr_indirect_mkey_disabled =
1074 [ # # ]: 0 : MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled);
1075 : 0 : attr->umr_modify_entity_size_disabled =
1076 [ # # ]: 0 : MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled);
1077 [ # # ]: 0 : attr->wait_on_time = MLX5_GET(cmd_hca_cap, hcattr, wait_on_time);
1078 [ # # ]: 0 : attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto);
1079 : 0 : attr->ct_offload = !!(general_obj_types_supported &
1080 : : MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD);
1081 [ # # ]: 0 : attr->rq_delay_drop = MLX5_GET(cmd_hca_cap, hcattr, rq_delay_drop);
1082 [ # # ]: 0 : attr->nic_flow_table = MLX5_GET(cmd_hca_cap, hcattr, nic_flow_table);
1083 [ # # ]: 0 : attr->striding_rq = MLX5_GET(cmd_hca_cap, hcattr, striding_rq);
1084 : 0 : attr->ext_stride_num_range =
1085 [ # # ]: 0 : MLX5_GET(cmd_hca_cap, hcattr, ext_stride_num_range);
1086 [ # # ]: 0 : attr->nic_flow_table = MLX5_GET(cmd_hca_cap, hcattr, nic_flow_table);
1087 [ # # ]: 0 : attr->max_flow_counter_15_0 = MLX5_GET(cmd_hca_cap, hcattr,
1088 : : max_flow_counter_15_0);
1089 [ # # ]: 0 : attr->max_flow_counter_31_16 = MLX5_GET(cmd_hca_cap, hcattr,
1090 : : max_flow_counter_31_16);
1091 [ # # ]: 0 : attr->alloc_flow_counter_pd = MLX5_GET(cmd_hca_cap, hcattr,
1092 : : alloc_flow_counter_pd);
1093 [ # # ]: 0 : attr->flow_counter_access_aso = MLX5_GET(cmd_hca_cap, hcattr,
1094 : : flow_counter_access_aso);
1095 [ # # ]: 0 : attr->flow_access_aso_opc_mod = MLX5_GET(cmd_hca_cap, hcattr,
1096 : : flow_access_aso_opc_mod);
1097 [ # # ]: 0 : attr->wqe_based_flow_table_sup = MLX5_GET(cmd_hca_cap, hcattr,
1098 : : wqe_based_flow_table_update_cap);
1099 : : /*
1100 : : * Flex item support needs max_num_prog_sample_field
1101 : : * from the Capabilities 2 table for PARSE_GRAPH_NODE
1102 : : */
1103 [ # # ]: 0 : if (attr->parse_graph_flex_node) {
1104 : 0 : rc = mlx5_devx_cmd_query_hca_parse_graph_node_cap
1105 : : (ctx, &attr->flex);
1106 [ # # ]: 0 : if (rc)
1107 : : return -1;
1108 : 0 : attr->flex.query_match_sample_info =
1109 : 0 : attr->query_match_sample_info;
1110 : : }
1111 [ # # ]: 0 : if (attr->crypto) {
1112 [ # # # # : 0 : attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts) ||
# # ]
1113 [ # # # # : 0 : MLX5_GET(cmd_hca_cap, hcattr, aes_xts_multi_block_be_tweak) ||
# # # # #
# # # ]
1114 : : MLX5_GET(cmd_hca_cap, hcattr, aes_xts_single_block_le_tweak);
1115 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1116 : : MLX5_GET_HCA_CAP_OP_MOD_CRYPTO |
1117 : : MLX5_HCA_CAP_OPMOD_GET_CUR);
1118 [ # # ]: 0 : if (!hcattr)
1119 : : return -1;
1120 [ # # ]: 0 : attr->crypto_wrapped_import_method = !!(MLX5_GET(crypto_caps,
1121 : : hcattr, wrapped_import_method)
1122 : 0 : & 1 << 2);
1123 [ # # ]: 0 : attr->crypto_mmo.crypto_mmo_qp = MLX5_GET(crypto_caps, hcattr, crypto_mmo_qp);
1124 : 0 : attr->crypto_mmo.gcm_256_encrypt =
1125 [ # # ]: 0 : MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_256_encrypt);
1126 : 0 : attr->crypto_mmo.gcm_128_encrypt =
1127 [ # # ]: 0 : MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_128_encrypt);
1128 : 0 : attr->crypto_mmo.gcm_256_decrypt =
1129 [ # # ]: 0 : MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_256_decrypt);
1130 : 0 : attr->crypto_mmo.gcm_128_decrypt =
1131 [ # # ]: 0 : MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_128_decrypt);
1132 : 0 : attr->crypto_mmo.gcm_auth_tag_128 =
1133 [ # # ]: 0 : MLX5_GET(crypto_caps, hcattr, gcm_auth_tag_128);
1134 : 0 : attr->crypto_mmo.gcm_auth_tag_96 =
1135 [ # # ]: 0 : MLX5_GET(crypto_caps, hcattr, gcm_auth_tag_96);
1136 : 0 : attr->crypto_mmo.log_crypto_mmo_max_size =
1137 [ # # ]: 0 : MLX5_GET(crypto_caps, hcattr, log_crypto_mmo_max_size);
1138 : : }
1139 [ # # ]: 0 : if (hca_cap_2_sup) {
1140 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1141 : : MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 |
1142 : : MLX5_HCA_CAP_OPMOD_GET_CUR);
1143 [ # # ]: 0 : if (!hcattr) {
1144 : 0 : DRV_LOG(DEBUG,
1145 : : "Failed to query DevX HCA capabilities 2.");
1146 : 0 : return rc;
1147 : : }
1148 [ # # ]: 0 : attr->log_min_stride_wqe_sz = MLX5_GET(cmd_hca_cap_2, hcattr,
1149 : : log_min_stride_wqe_sz);
1150 [ # # ]: 0 : attr->hairpin_sq_wqe_bb_size = MLX5_GET(cmd_hca_cap_2, hcattr,
1151 : : hairpin_sq_wqe_bb_size);
1152 [ # # ]: 0 : attr->hairpin_sq_wq_in_host_mem = MLX5_GET(cmd_hca_cap_2, hcattr,
1153 : : hairpin_sq_wq_in_host_mem);
1154 [ # # ]: 0 : attr->hairpin_data_buffer_locked = MLX5_GET(cmd_hca_cap_2, hcattr,
1155 : : hairpin_data_buffer_locked);
1156 [ # # ]: 0 : attr->flow_counter_bulk_log_max_alloc = MLX5_GET(cmd_hca_cap_2,
1157 : : hcattr, flow_counter_bulk_log_max_alloc);
1158 : 0 : attr->flow_counter_bulk_log_granularity =
1159 [ # # ]: 0 : MLX5_GET(cmd_hca_cap_2, hcattr,
1160 : : flow_counter_bulk_log_granularity);
1161 [ # # ]: 0 : rc = MLX5_GET(cmd_hca_cap_2, hcattr,
1162 : : cross_vhca_object_to_object_supported);
1163 : 0 : attr->cross_vhca =
1164 : : (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_STC_TO_TIR) &&
1165 : : (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_STC_TO_FT) &&
1166 : 0 : (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_FT_TO_FT) &&
1167 : : (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_FT_TO_RTC);
1168 [ # # ]: 0 : rc = MLX5_GET(cmd_hca_cap_2, hcattr,
1169 : : allowed_object_for_other_vhca_access);
1170 : 0 : attr->cross_vhca = attr->cross_vhca &&
1171 : : (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_TIR) &&
1172 [ # # # # ]: 0 : (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_FT) &&
1173 : : (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_RTC);
1174 [ # # ]: 0 : if (attr->ct_offload)
1175 [ # # ]: 0 : attr->log_max_conn_track_offload = MLX5_GET(cmd_hca_cap_2, hcattr,
1176 : : log_max_conn_track_offload);
1177 : : }
1178 [ # # ]: 0 : if (attr->log_min_stride_wqe_sz == 0)
1179 : 0 : attr->log_min_stride_wqe_sz = MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE;
1180 [ # # ]: 0 : if (attr->qos.sup) {
1181 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1182 : : MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |
1183 : : MLX5_HCA_CAP_OPMOD_GET_CUR);
1184 [ # # ]: 0 : if (!hcattr) {
1185 : 0 : DRV_LOG(DEBUG, "Failed to query devx QOS capabilities");
1186 : 0 : return rc;
1187 : : }
1188 : 0 : attr->qos.flow_meter_old =
1189 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr, flow_meter_old);
1190 [ # # ]: 0 : attr->qos.log_max_flow_meter =
1191 : 0 : MLX5_GET(qos_cap, hcattr, log_max_flow_meter);
1192 [ # # ]: 0 : attr->qos.flow_meter_reg_c_ids =
1193 : : MLX5_GET(qos_cap, hcattr, flow_meter_reg_id);
1194 : 0 : attr->qos.flow_meter =
1195 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr, flow_meter);
1196 : 0 : attr->qos.packet_pacing =
1197 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr, packet_pacing);
1198 : 0 : attr->qos.wqe_rate_pp =
1199 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr, wqe_rate_pp);
1200 [ # # ]: 0 : if (attr->qos.flow_meter_aso_sup) {
1201 : 0 : attr->qos.log_meter_aso_granularity =
1202 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr,
1203 : : log_meter_aso_granularity);
1204 : 0 : attr->qos.log_meter_aso_max_alloc =
1205 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr,
1206 : : log_meter_aso_max_alloc);
1207 : 0 : attr->qos.log_max_num_meter_aso =
1208 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr,
1209 : : log_max_num_meter_aso);
1210 : : }
1211 : : }
1212 [ # # ]: 0 : if (attr->vdpa.valid)
1213 : 0 : mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa);
1214 [ # # ]: 0 : if (!attr->eth_net_offloads)
1215 : : return 0;
1216 : : /* Query Flow Sampler Capability From FLow Table Properties Layout. */
1217 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1218 : : MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE |
1219 : : MLX5_HCA_CAP_OPMOD_GET_CUR);
1220 [ # # ]: 0 : if (!hcattr) {
1221 : 0 : attr->log_max_ft_sampler_num = 0;
1222 : 0 : return rc;
1223 : : }
1224 [ # # ]: 0 : attr->log_max_ft_sampler_num = MLX5_GET
1225 : : (flow_table_nic_cap, hcattr,
1226 : : flow_table_properties_nic_receive.log_max_ft_sampler_num);
1227 [ # # ]: 0 : attr->flow.tunnel_header_0_1 = MLX5_GET
1228 : : (flow_table_nic_cap, hcattr,
1229 : : ft_field_support_2_nic_receive.tunnel_header_0_1);
1230 [ # # ]: 0 : attr->flow.tunnel_header_2_3 = MLX5_GET
1231 : : (flow_table_nic_cap, hcattr,
1232 : : ft_field_support_2_nic_receive.tunnel_header_2_3);
1233 [ # # ]: 0 : attr->modify_outer_ip_ecn = MLX5_GET
1234 : : (flow_table_nic_cap, hcattr,
1235 : : ft_header_modify_nic_receive.outer_ip_ecn);
1236 [ # # ]: 0 : attr->modify_outer_ipv6_traffic_class = MLX5_GET
1237 : : (flow_table_nic_cap, hcattr,
1238 : : ft_header_modify_nic_receive.outer_ipv6_traffic_class);
1239 : 0 : attr->set_reg_c = 0xffff;
1240 [ # # ]: 0 : if (attr->nic_flow_table) {
1241 : : #define GET_RX_REG_X_BITS \
1242 : : MLX5_GET(flow_table_nic_cap, hcattr, \
1243 : : ft_header_modify_nic_receive.metadata_reg_c_x)
1244 : : #define GET_TX_REG_X_BITS \
1245 : : MLX5_GET(flow_table_nic_cap, hcattr, \
1246 : : ft_header_modify_nic_transmit.metadata_reg_c_x)
1247 : :
1248 : : uint32_t tx_reg, rx_reg, reg_c_8_15;
1249 : :
1250 [ # # ]: 0 : tx_reg = GET_TX_REG_X_BITS;
1251 [ # # ]: 0 : reg_c_8_15 = MLX5_GET(flow_table_nic_cap, hcattr,
1252 : : ft_field_support_2_nic_transmit.metadata_reg_c_8_15);
1253 : 0 : tx_reg |= ((0xff & reg_c_8_15) << 8);
1254 [ # # ]: 0 : rx_reg = GET_RX_REG_X_BITS;
1255 [ # # ]: 0 : reg_c_8_15 = MLX5_GET(flow_table_nic_cap, hcattr,
1256 : : ft_field_support_2_nic_receive.metadata_reg_c_8_15);
1257 : 0 : rx_reg |= ((0xff & reg_c_8_15) << 8);
1258 : 0 : attr->set_reg_c &= (rx_reg & tx_reg);
1259 : :
1260 : : #undef GET_RX_REG_X_BITS
1261 : : #undef GET_TX_REG_X_BITS
1262 : : }
1263 : 0 : attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr);
1264 [ # # ]: 0 : attr->inner_ipv4_ihl = MLX5_GET
1265 : : (flow_table_nic_cap, hcattr,
1266 : : ft_field_support_2_nic_receive.inner_ipv4_ihl);
1267 [ # # ]: 0 : attr->outer_ipv4_ihl = MLX5_GET
1268 : : (flow_table_nic_cap, hcattr,
1269 : : ft_field_support_2_nic_receive.outer_ipv4_ihl);
1270 [ # # ]: 0 : attr->lag_rx_port_affinity = MLX5_GET
1271 : : (flow_table_nic_cap, hcattr,
1272 : : ft_field_support_2_nic_receive.lag_rx_port_affinity);
1273 : : /* Query HCA offloads for Ethernet protocol. */
1274 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1275 : : MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS |
1276 : : MLX5_HCA_CAP_OPMOD_GET_CUR);
1277 [ # # ]: 0 : if (!hcattr) {
1278 : 0 : attr->eth_net_offloads = 0;
1279 : 0 : return rc;
1280 : : }
1281 [ # # ]: 0 : attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps,
1282 : : hcattr, wqe_vlan_insert);
1283 [ # # ]: 0 : attr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps,
1284 : : hcattr, csum_cap);
1285 [ # # ]: 0 : attr->vlan_cap = MLX5_GET(per_protocol_networking_offload_caps,
1286 : : hcattr, vlan_cap);
1287 [ # # ]: 0 : attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr,
1288 : : lro_cap);
1289 [ # # ]: 0 : attr->max_lso_cap = MLX5_GET(per_protocol_networking_offload_caps,
1290 : : hcattr, max_lso_cap);
1291 [ # # ]: 0 : attr->scatter_fcs = MLX5_GET(per_protocol_networking_offload_caps,
1292 : : hcattr, scatter_fcs);
1293 [ # # ]: 0 : attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps,
1294 : : hcattr, tunnel_lro_gre);
1295 [ # # ]: 0 : attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps,
1296 : : hcattr, tunnel_lro_vxlan);
1297 [ # # ]: 0 : attr->swp = MLX5_GET(per_protocol_networking_offload_caps,
1298 : : hcattr, swp);
1299 : 0 : attr->tunnel_stateless_gre =
1300 [ # # ]: 0 : MLX5_GET(per_protocol_networking_offload_caps,
1301 : : hcattr, tunnel_stateless_gre);
1302 : 0 : attr->tunnel_stateless_vxlan =
1303 [ # # ]: 0 : MLX5_GET(per_protocol_networking_offload_caps,
1304 : : hcattr, tunnel_stateless_vxlan);
1305 [ # # ]: 0 : attr->swp_csum = MLX5_GET(per_protocol_networking_offload_caps,
1306 : : hcattr, swp_csum);
1307 [ # # ]: 0 : attr->swp_lso = MLX5_GET(per_protocol_networking_offload_caps,
1308 : : hcattr, swp_lso);
1309 [ # # ]: 0 : attr->lro_max_msg_sz_mode = MLX5_GET
1310 : : (per_protocol_networking_offload_caps,
1311 : : hcattr, lro_max_msg_sz_mode);
1312 [ # # ]: 0 : for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) {
1313 : 0 : attr->lro_timer_supported_periods[i] =
1314 [ # # ]: 0 : MLX5_GET(per_protocol_networking_offload_caps, hcattr,
1315 : : lro_timer_supported_periods[i]);
1316 : : }
1317 [ # # ]: 0 : attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps,
1318 : : hcattr, lro_min_mss_size);
1319 : 0 : attr->tunnel_stateless_geneve_rx =
1320 [ # # ]: 0 : MLX5_GET(per_protocol_networking_offload_caps,
1321 : : hcattr, tunnel_stateless_geneve_rx);
1322 : 0 : attr->geneve_max_opt_len =
1323 [ # # ]: 0 : MLX5_GET(per_protocol_networking_offload_caps,
1324 : : hcattr, max_geneve_opt_len);
1325 [ # # ]: 0 : attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps,
1326 : : hcattr, wqe_inline_mode);
1327 [ # # ]: 0 : attr->tunnel_stateless_gtp = MLX5_GET
1328 : : (per_protocol_networking_offload_caps,
1329 : : hcattr, tunnel_stateless_gtp);
1330 [ # # ]: 0 : attr->tunnel_stateless_vxlan_gpe_nsh = MLX5_GET
1331 : : (per_protocol_networking_offload_caps,
1332 : : hcattr, tunnel_stateless_vxlan_gpe_nsh);
1333 [ # # ]: 0 : attr->rss_ind_tbl_cap = MLX5_GET
1334 : : (per_protocol_networking_offload_caps,
1335 : : hcattr, rss_ind_tbl_cap);
1336 [ # # ]: 0 : attr->multi_pkt_send_wqe = MLX5_GET
1337 : : (per_protocol_networking_offload_caps,
1338 : : hcattr, multi_pkt_send_wqe);
1339 [ # # ]: 0 : attr->enhanced_multi_pkt_send_wqe = MLX5_GET
1340 : : (per_protocol_networking_offload_caps,
1341 : : hcattr, enhanced_multi_pkt_send_wqe);
1342 [ # # ]: 0 : if (attr->wqe_based_flow_table_sup) {
1343 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1344 : : MLX5_GET_HCA_CAP_OP_MOD_WQE_BASED_FLOW_TABLE |
1345 : : MLX5_HCA_CAP_OPMOD_GET_CUR);
1346 [ # # ]: 0 : if (!hcattr) {
1347 : 0 : DRV_LOG(DEBUG, "Failed to query WQE Based Flow table capabilities");
1348 : 0 : return rc;
1349 : : }
1350 [ # # ]: 0 : attr->max_header_modify_pattern_length = MLX5_GET(wqe_based_flow_table_cap,
1351 : : hcattr,
1352 : : max_header_modify_pattern_length);
1353 [ # # ]: 0 : attr->fdb_unified_en = MLX5_GET(wqe_based_flow_table_cap,
1354 : : hcattr,
1355 : : fdb_unified_en);
1356 [ # # ]: 0 : stc_action_type_127_64 = MLX5_GET64(wqe_based_flow_table_cap,
1357 : : hcattr,
1358 : : stc_action_type_127_64);
1359 [ # # ]: 0 : if (stc_action_type_127_64 &
1360 : : (1 << (MLX5_IFC_STC_ACTION_TYPE_JUMP_FLOW_TABLE_FDB_RX_BIT_INDEX -
1361 : : MLX5_IFC_STC_ACTION_TYPE_BIT_64_INDEX)))
1362 : 0 : attr->jump_fdb_rx_en = 1;
1363 : : }
1364 : : /* Query HCA attribute for ROCE. */
1365 [ # # ]: 0 : if (attr->roce) {
1366 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1367 : : MLX5_GET_HCA_CAP_OP_MOD_ROCE |
1368 : : MLX5_HCA_CAP_OPMOD_GET_CUR);
1369 [ # # ]: 0 : if (!hcattr) {
1370 : 0 : DRV_LOG(DEBUG,
1371 : : "Failed to query devx HCA ROCE capabilities");
1372 : 0 : return rc;
1373 : : }
1374 [ # # ]: 0 : attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format);
1375 : : }
1376 [ # # ]: 0 : if (attr->eth_virt) {
1377 : 0 : rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr);
1378 [ # # ]: 0 : if (rc) {
1379 : 0 : attr->eth_virt = 0;
1380 : 0 : goto error;
1381 : : }
1382 : : }
1383 [ # # ]: 0 : if (attr->eswitch_manager) {
1384 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1385 : : MLX5_SET_HCA_CAP_OP_MOD_ESW |
1386 : : MLX5_HCA_CAP_OPMOD_GET_CUR);
1387 [ # # ]: 0 : if (!hcattr)
1388 : 0 : return rc;
1389 : 0 : attr->esw_mgr_vport_id_valid =
1390 [ # # ]: 0 : MLX5_GET(esw_cap, hcattr,
1391 : : esw_manager_vport_number_valid);
1392 : 0 : attr->esw_mgr_vport_id =
1393 [ # # ]: 0 : MLX5_GET(esw_cap, hcattr, esw_manager_vport_number);
1394 : : }
1395 [ # # ]: 0 : if (attr->eswitch_manager) {
1396 : : uint32_t esw_reg, reg_c_8_15;
1397 : :
1398 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1399 : : MLX5_GET_HCA_CAP_OP_MOD_ESW_FLOW_TABLE |
1400 : : MLX5_HCA_CAP_OPMOD_GET_CUR);
1401 [ # # ]: 0 : if (!hcattr)
1402 : 0 : return rc;
1403 [ # # ]: 0 : esw_reg = MLX5_GET(flow_table_esw_cap, hcattr,
1404 : : ft_header_modify_esw_fdb.metadata_reg_c_x);
1405 [ # # ]: 0 : reg_c_8_15 = MLX5_GET(flow_table_esw_cap, hcattr,
1406 : : ft_field_support_2_esw_fdb.metadata_reg_c_8_15);
1407 : 0 : attr->set_reg_c &= ((0xff & reg_c_8_15) << 8) | esw_reg;
1408 : : }
1409 : : return 0;
1410 : : error:
1411 : 0 : rc = (rc > 0) ? -rc : rc;
1412 : 0 : return rc;
1413 : : }
1414 : :
1415 : : /**
1416 : : * Query TIS transport domain from QP verbs object using DevX API.
1417 : : *
1418 : : * @param[in] qp
1419 : : * Pointer to verbs QP returned by ibv_create_qp .
1420 : : * @param[in] tis_num
1421 : : * TIS number of TIS to query.
1422 : : * @param[out] tis_td
1423 : : * Pointer to TIS transport domain variable, to be set by the routine.
1424 : : *
1425 : : * @return
1426 : : * 0 on success, a negative value otherwise.
1427 : : */
1428 : : int
1429 : 0 : mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num,
1430 : : uint32_t *tis_td)
1431 : : {
1432 : : #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1433 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0};
1434 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0};
1435 : : int rc;
1436 : : void *tis_ctx;
1437 : :
1438 : 0 : MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS);
1439 : 0 : MLX5_SET(query_tis_in, in, tisn, tis_num);
1440 : 0 : rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out));
1441 [ # # ]: 0 : if (rc) {
1442 : 0 : DRV_LOG(ERR, "Failed to query QP using DevX");
1443 : 0 : return -rc;
1444 : : };
1445 : : tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context);
1446 [ # # ]: 0 : *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain);
1447 : 0 : return 0;
1448 : : #else
1449 : : (void)qp;
1450 : : (void)tis_num;
1451 : : (void)tis_td;
1452 : : return -ENOTSUP;
1453 : : #endif
1454 : : }
1455 : :
1456 : : /**
1457 : : * Fill WQ data for DevX API command.
1458 : : * Utility function for use when creating DevX objects containing a WQ.
1459 : : *
1460 : : * @param[in] wq_ctx
1461 : : * Pointer to WQ context to fill with data.
1462 : : * @param [in] wq_attr
1463 : : * Pointer to WQ attributes structure to fill in WQ context.
1464 : : */
1465 : : static void
1466 : 0 : devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr)
1467 : : {
1468 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type);
1469 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature);
1470 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode);
1471 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave);
1472 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge);
1473 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size);
1474 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset);
1475 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm);
1476 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, pd, wq_attr->pd);
1477 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page);
1478 [ # # ]: 0 : MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr);
1479 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter);
1480 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter);
1481 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride);
1482 [ # # ]: 0 : if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT)
1483 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, log_wq_pg_sz,
1484 : : wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT);
1485 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz);
1486 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid);
1487 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid);
1488 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, log_hairpin_num_packets,
1489 : : wq_attr->log_hairpin_num_packets);
1490 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz);
1491 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides,
1492 : : wq_attr->single_wqe_log_num_of_strides);
1493 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en);
1494 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes,
1495 : : wq_attr->single_stride_log_num_of_bytes);
1496 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id);
1497 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id);
1498 [ # # ]: 0 : MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset);
1499 : 0 : }
1500 : :
1501 : : /**
1502 : : * Create RQ using DevX API.
1503 : : *
1504 : : * @param[in] ctx
1505 : : * Context returned from mlx5 open_device() glue function.
1506 : : * @param [in] rq_attr
1507 : : * Pointer to create RQ attributes structure.
1508 : : * @param [in] socket
1509 : : * CPU socket ID for allocations.
1510 : : *
1511 : : * @return
1512 : : * The DevX object created, NULL otherwise and rte_errno is set.
1513 : : */
1514 : : struct mlx5_devx_obj *
1515 : 0 : mlx5_devx_cmd_create_rq(void *ctx,
1516 : : struct mlx5_devx_create_rq_attr *rq_attr,
1517 : : int socket)
1518 : : {
1519 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0};
1520 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0};
1521 : : void *rq_ctx, *wq_ctx;
1522 : : struct mlx5_devx_wq_attr *wq_attr;
1523 : : struct mlx5_devx_obj *rq = NULL;
1524 : :
1525 : 0 : rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket);
1526 [ # # ]: 0 : if (!rq) {
1527 : 0 : DRV_LOG(ERR, "Failed to allocate RQ data");
1528 : 0 : rte_errno = ENOMEM;
1529 : 0 : return NULL;
1530 : : }
1531 [ # # ]: 0 : MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ);
1532 : : rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx);
1533 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky);
1534 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en);
1535 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
1536 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
1537 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type);
1538 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
1539 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en);
1540 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin);
1541 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, hairpin_data_buffer_type, rq_attr->hairpin_data_buffer_type);
1542 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index);
1543 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn);
1544 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
1545 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn);
1546 [ # # ]: 0 : MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format);
1547 : : wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
1548 : 0 : wq_attr = &rq_attr->wq_attr;
1549 : 0 : devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1550 : 0 : rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1551 : : out, sizeof(out));
1552 [ # # ]: 0 : if (!rq->obj) {
1553 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create RQ", NULL, 0);
1554 : 0 : mlx5_free(rq);
1555 : 0 : return NULL;
1556 : : }
1557 [ # # ]: 0 : rq->id = MLX5_GET(create_rq_out, out, rqn);
1558 : 0 : return rq;
1559 : : }
1560 : :
1561 : : /**
1562 : : * Modify RQ using DevX API.
1563 : : *
1564 : : * @param[in] rq
1565 : : * Pointer to RQ object structure.
1566 : : * @param [in] rq_attr
1567 : : * Pointer to modify RQ attributes structure.
1568 : : *
1569 : : * @return
1570 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
1571 : : */
1572 : : int
1573 : 0 : mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
1574 : : struct mlx5_devx_modify_rq_attr *rq_attr)
1575 : : {
1576 : 0 : uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0};
1577 : 0 : uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0};
1578 : : void *rq_ctx, *wq_ctx;
1579 : : int ret;
1580 : :
1581 : 0 : MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ);
1582 : 0 : MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state);
1583 [ # # ]: 0 : MLX5_SET(modify_rq_in, in, rqn, rq->id);
1584 [ # # ]: 0 : MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask);
1585 : : rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1586 : 0 : MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
1587 [ # # ]: 0 : if (rq_attr->modify_bitmask &
1588 : : MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS)
1589 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
1590 [ # # ]: 0 : if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD)
1591 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
1592 [ # # ]: 0 : if (rq_attr->modify_bitmask &
1593 : : MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID)
1594 : 0 : MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
1595 : 0 : MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq);
1596 : 0 : MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca);
1597 [ # # ]: 0 : if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) {
1598 : : wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
1599 : 0 : MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm);
1600 : : }
1601 : 0 : ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in),
1602 : : out, sizeof(out));
1603 : :
1604 [ # # ]: 0 : if (ret) {
1605 : 0 : DRV_LOG(ERR, "Failed to modify RQ using DevX");
1606 : 0 : rte_errno = errno;
1607 : 0 : return -errno;
1608 : : }
1609 : : return ret;
1610 : : }
1611 : :
1612 : : /*
1613 : : * Query RQ using DevX API.
1614 : : *
1615 : : * @param[in] rq_obj
1616 : : * RQ Devx Object
1617 : : * @param[out] out
1618 : : * RQ Query Output
1619 : : * @param[in] outlen
1620 : : * RQ Query Output Length
1621 : : *
1622 : : * @return
1623 : : * 0 if Query successful, else non-zero return value from devx_obj_query API
1624 : : */
1625 : : int
1626 : 0 : mlx5_devx_cmd_query_rq(struct mlx5_devx_obj *rq_obj, void *out, size_t outlen)
1627 : : {
1628 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0};
1629 : : int rc;
1630 : :
1631 : 0 : MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ);
1632 : 0 : MLX5_SET(query_rq_in, in, rqn, rq_obj->id);
1633 : 0 : rc = mlx5_glue->devx_obj_query(rq_obj->obj, in, sizeof(in), out, outlen);
1634 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
1635 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "RQ query", "rq_id", rq_obj->id);
1636 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
1637 : : }
1638 : : return 0;
1639 : : }
1640 : :
1641 : : /**
1642 : : * Create RMP using DevX API.
1643 : : *
1644 : : * @param[in] ctx
1645 : : * Context returned from mlx5 open_device() glue function.
1646 : : * @param [in] rmp_attr
1647 : : * Pointer to create RMP attributes structure.
1648 : : * @param [in] socket
1649 : : * CPU socket ID for allocations.
1650 : : *
1651 : : * @return
1652 : : * The DevX object created, NULL otherwise and rte_errno is set.
1653 : : */
1654 : : struct mlx5_devx_obj *
1655 : 0 : mlx5_devx_cmd_create_rmp(void *ctx,
1656 : : struct mlx5_devx_create_rmp_attr *rmp_attr,
1657 : : int socket)
1658 : : {
1659 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_rmp_in)] = {0};
1660 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_rmp_out)] = {0};
1661 : : void *rmp_ctx, *wq_ctx;
1662 : : struct mlx5_devx_wq_attr *wq_attr;
1663 : : struct mlx5_devx_obj *rmp = NULL;
1664 : :
1665 : 0 : rmp = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rmp), 0, socket);
1666 [ # # ]: 0 : if (!rmp) {
1667 : 0 : DRV_LOG(ERR, "Failed to allocate RMP data");
1668 : 0 : rte_errno = ENOMEM;
1669 : 0 : return NULL;
1670 : : }
1671 [ # # ]: 0 : MLX5_SET(create_rmp_in, in, opcode, MLX5_CMD_OP_CREATE_RMP);
1672 : : rmp_ctx = MLX5_ADDR_OF(create_rmp_in, in, ctx);
1673 [ # # ]: 0 : MLX5_SET(rmpc, rmp_ctx, state, rmp_attr->state);
1674 [ # # ]: 0 : MLX5_SET(rmpc, rmp_ctx, basic_cyclic_rcv_wqe,
1675 : : rmp_attr->basic_cyclic_rcv_wqe);
1676 : : wq_ctx = MLX5_ADDR_OF(rmpc, rmp_ctx, wq);
1677 : 0 : wq_attr = &rmp_attr->wq_attr;
1678 : 0 : devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1679 : 0 : rmp->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1680 : : sizeof(out));
1681 [ # # ]: 0 : if (!rmp->obj) {
1682 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create RMP", NULL, 0);
1683 : 0 : mlx5_free(rmp);
1684 : 0 : return NULL;
1685 : : }
1686 [ # # ]: 0 : rmp->id = MLX5_GET(create_rmp_out, out, rmpn);
1687 : 0 : return rmp;
1688 : : }
1689 : :
1690 : : /*
1691 : : * Create TIR using DevX API.
1692 : : *
1693 : : * @param[in] ctx
1694 : : * Context returned from mlx5 open_device() glue function.
1695 : : * @param [in] tir_attr
1696 : : * Pointer to TIR attributes structure.
1697 : : *
1698 : : * @return
1699 : : * The DevX object created, NULL otherwise and rte_errno is set.
1700 : : */
1701 : : struct mlx5_devx_obj *
1702 : 0 : mlx5_devx_cmd_create_tir(void *ctx,
1703 : : struct mlx5_devx_tir_attr *tir_attr)
1704 : : {
1705 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
1706 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0};
1707 : : void *tir_ctx, *outer, *inner, *rss_key;
1708 : : struct mlx5_devx_obj *tir = NULL;
1709 : :
1710 : 0 : tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY);
1711 [ # # ]: 0 : if (!tir) {
1712 : 0 : DRV_LOG(ERR, "Failed to allocate TIR data");
1713 : 0 : rte_errno = ENOMEM;
1714 : 0 : return NULL;
1715 : : }
1716 [ # # ]: 0 : MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1717 : : tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx);
1718 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type);
1719 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1720 : : tir_attr->lro_timeout_period_usecs);
1721 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask);
1722 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz);
1723 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn);
1724 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric);
1725 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, tunneled_offload_en,
1726 : : tir_attr->tunneled_offload_en);
1727 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table);
1728 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1729 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1730 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain);
1731 : : rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key);
1732 [ # # ]: 0 : memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN);
1733 : : outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer);
1734 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1735 : : tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1736 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1737 : : tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1738 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, outer, selected_fields,
1739 : : tir_attr->rx_hash_field_selector_outer.selected_fields);
1740 : : inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner);
1741 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1742 : : tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1743 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1744 : : tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1745 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, inner, selected_fields,
1746 : : tir_attr->rx_hash_field_selector_inner.selected_fields);
1747 : 0 : tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1748 : : out, sizeof(out));
1749 [ # # ]: 0 : if (!tir->obj) {
1750 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create TIR", NULL, 0);
1751 : 0 : mlx5_free(tir);
1752 : 0 : return NULL;
1753 : : }
1754 [ # # ]: 0 : tir->id = MLX5_GET(create_tir_out, out, tirn);
1755 : 0 : return tir;
1756 : : }
1757 : :
1758 : : /**
1759 : : * Modify TIR using DevX API.
1760 : : *
1761 : : * @param[in] tir
1762 : : * Pointer to TIR DevX object structure.
1763 : : * @param [in] modify_tir_attr
1764 : : * Pointer to TIR modification attributes structure.
1765 : : *
1766 : : * @return
1767 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
1768 : : */
1769 : : int
1770 : 0 : mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir,
1771 : : struct mlx5_devx_modify_tir_attr *modify_tir_attr)
1772 : : {
1773 : : struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir;
1774 : 0 : uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0};
1775 : 0 : uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0};
1776 : : void *tir_ctx;
1777 : : int ret;
1778 : :
1779 : 0 : MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR);
1780 : 0 : MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn);
1781 [ # # ]: 0 : MLX5_SET64(modify_tir_in, in, modify_bitmask,
1782 : : modify_tir_attr->modify_bitmask);
1783 : : tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1784 [ # # ]: 0 : if (modify_tir_attr->modify_bitmask &
1785 : : MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) {
1786 : 0 : MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1787 : : tir_attr->lro_timeout_period_usecs);
1788 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, lro_enable_mask,
1789 : : tir_attr->lro_enable_mask);
1790 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, lro_max_msg_sz,
1791 : : tir_attr->lro_max_msg_sz);
1792 : : }
1793 [ # # ]: 0 : if (modify_tir_attr->modify_bitmask &
1794 : : MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE)
1795 : 0 : MLX5_SET(tirc, tir_ctx, indirect_table,
1796 : : tir_attr->indirect_table);
1797 [ # # ]: 0 : if (modify_tir_attr->modify_bitmask &
1798 : : MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) {
1799 : : int i;
1800 : : void *outer, *inner;
1801 : :
1802 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, rx_hash_symmetric,
1803 : : tir_attr->rx_hash_symmetric);
1804 : 0 : MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1805 [ # # ]: 0 : for (i = 0; i < 10; i++) {
1806 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i],
1807 : : tir_attr->rx_hash_toeplitz_key[i]);
1808 : : }
1809 : : outer = MLX5_ADDR_OF(tirc, tir_ctx,
1810 : : rx_hash_field_selector_outer);
1811 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1812 : : tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1813 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1814 : : tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1815 [ # # ]: 0 : MLX5_SET
1816 : : (rx_hash_field_select, outer, selected_fields,
1817 : : tir_attr->rx_hash_field_selector_outer.selected_fields);
1818 : : inner = MLX5_ADDR_OF(tirc, tir_ctx,
1819 : : rx_hash_field_selector_inner);
1820 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1821 : : tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1822 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1823 : : tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1824 [ # # ]: 0 : MLX5_SET
1825 : : (rx_hash_field_select, inner, selected_fields,
1826 : : tir_attr->rx_hash_field_selector_inner.selected_fields);
1827 : : }
1828 [ # # ]: 0 : if (modify_tir_attr->modify_bitmask &
1829 : : MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) {
1830 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1831 : : }
1832 : 0 : ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in),
1833 : : out, sizeof(out));
1834 [ # # ]: 0 : if (ret) {
1835 : 0 : DRV_LOG(ERR, "Failed to modify TIR using DevX");
1836 : 0 : rte_errno = errno;
1837 : 0 : return -errno;
1838 : : }
1839 : : return ret;
1840 : : }
1841 : :
1842 : : /**
1843 : : * Create RQT using DevX API.
1844 : : *
1845 : : * @param[in] ctx
1846 : : * Context returned from mlx5 open_device() glue function.
1847 : : * @param [in] rqt_attr
1848 : : * Pointer to RQT attributes structure.
1849 : : *
1850 : : * @return
1851 : : * The DevX object created, NULL otherwise and rte_errno is set.
1852 : : */
1853 : : struct mlx5_devx_obj *
1854 : 0 : mlx5_devx_cmd_create_rqt(void *ctx,
1855 : : struct mlx5_devx_rqt_attr *rqt_attr)
1856 : : {
1857 : : uint32_t *in = NULL;
1858 : 0 : uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) +
1859 : 0 : rqt_attr->rqt_actual_size * sizeof(uint32_t);
1860 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
1861 : : void *rqt_ctx;
1862 : : struct mlx5_devx_obj *rqt = NULL;
1863 : : unsigned int i;
1864 : :
1865 : 0 : in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1866 [ # # ]: 0 : if (!in) {
1867 : 0 : DRV_LOG(ERR, "Failed to allocate RQT IN data");
1868 : 0 : rte_errno = ENOMEM;
1869 : 0 : return NULL;
1870 : : }
1871 : 0 : rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY);
1872 [ # # ]: 0 : if (!rqt) {
1873 : 0 : DRV_LOG(ERR, "Failed to allocate RQT data");
1874 : 0 : rte_errno = ENOMEM;
1875 : 0 : mlx5_free(in);
1876 : 0 : return NULL;
1877 : : }
1878 [ # # ]: 0 : MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
1879 : 0 : rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1880 [ # # ]: 0 : MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1881 [ # # ]: 0 : MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
1882 [ # # ]: 0 : MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1883 [ # # ]: 0 : for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1884 [ # # ]: 0 : MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1885 : 0 : rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out));
1886 : 0 : mlx5_free(in);
1887 [ # # ]: 0 : if (!rqt->obj) {
1888 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create RQT", NULL, 0);
1889 : 0 : mlx5_free(rqt);
1890 : 0 : return NULL;
1891 : : }
1892 [ # # ]: 0 : rqt->id = MLX5_GET(create_rqt_out, out, rqtn);
1893 : 0 : return rqt;
1894 : : }
1895 : :
1896 : : /**
1897 : : * Modify RQT using DevX API.
1898 : : *
1899 : : * @param[in] rqt
1900 : : * Pointer to RQT DevX object structure.
1901 : : * @param [in] rqt_attr
1902 : : * Pointer to RQT attributes structure.
1903 : : *
1904 : : * @return
1905 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
1906 : : */
1907 : : int
1908 : 0 : mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
1909 : : struct mlx5_devx_rqt_attr *rqt_attr)
1910 : : {
1911 : 0 : uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) +
1912 : 0 : rqt_attr->rqt_actual_size * sizeof(uint32_t);
1913 : 0 : uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0};
1914 : 0 : uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1915 : : void *rqt_ctx;
1916 : : unsigned int i;
1917 : : int ret;
1918 : :
1919 [ # # ]: 0 : if (!in) {
1920 : 0 : DRV_LOG(ERR, "Failed to allocate RQT modify IN data.");
1921 : 0 : rte_errno = ENOMEM;
1922 : 0 : return -ENOMEM;
1923 : : }
1924 [ # # ]: 0 : MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT);
1925 [ # # ]: 0 : MLX5_SET(modify_rqt_in, in, rqtn, rqt->id);
1926 : 0 : MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1);
1927 : 0 : rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context);
1928 [ # # ]: 0 : MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1929 [ # # ]: 0 : MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1930 [ # # ]: 0 : for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1931 [ # # ]: 0 : MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1932 : 0 : ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out));
1933 : 0 : mlx5_free(in);
1934 [ # # ]: 0 : if (ret) {
1935 : 0 : DRV_LOG(ERR, "Failed to modify RQT using DevX.");
1936 : 0 : rte_errno = errno;
1937 : 0 : return -rte_errno;
1938 : : }
1939 : : return ret;
1940 : : }
1941 : :
1942 : : /**
1943 : : * Create SQ using DevX API.
1944 : : *
1945 : : * @param[in] ctx
1946 : : * Context returned from mlx5 open_device() glue function.
1947 : : * @param [in] sq_attr
1948 : : * Pointer to SQ attributes structure.
1949 : : * @param [in] socket
1950 : : * CPU socket ID for allocations.
1951 : : *
1952 : : * @return
1953 : : * The DevX object created, NULL otherwise and rte_errno is set.
1954 : : **/
1955 : : struct mlx5_devx_obj *
1956 : 0 : mlx5_devx_cmd_create_sq(void *ctx,
1957 : : struct mlx5_devx_create_sq_attr *sq_attr)
1958 : : {
1959 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0};
1960 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0};
1961 : : void *sq_ctx;
1962 : : void *wq_ctx;
1963 : : struct mlx5_devx_wq_attr *wq_attr;
1964 : : struct mlx5_devx_obj *sq = NULL;
1965 : :
1966 : 0 : sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY);
1967 [ # # ]: 0 : if (!sq) {
1968 : 0 : DRV_LOG(ERR, "Failed to allocate SQ data");
1969 : 0 : rte_errno = ENOMEM;
1970 : 0 : return NULL;
1971 : : }
1972 [ # # ]: 0 : MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ);
1973 : : sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx);
1974 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky);
1975 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master);
1976 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre);
1977 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en);
1978 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe,
1979 : : sq_attr->allow_multi_pkt_send_wqe);
1980 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode,
1981 : : sq_attr->min_wqe_inline_mode);
1982 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
1983 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr);
1984 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp);
1985 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin);
1986 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire);
1987 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq);
1988 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, hairpin_wq_buffer_type, sq_attr->hairpin_wq_buffer_type);
1989 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index);
1990 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn);
1991 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index,
1992 : : sq_attr->packet_pacing_rate_limit_index);
1993 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz);
1994 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num);
1995 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format);
1996 : : wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq);
1997 : 0 : wq_attr = &sq_attr->wq_attr;
1998 : 0 : devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1999 : 0 : sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2000 : : out, sizeof(out));
2001 [ # # ]: 0 : if (!sq->obj) {
2002 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create SQ", NULL, 0);
2003 : 0 : mlx5_free(sq);
2004 : 0 : return NULL;
2005 : : }
2006 [ # # ]: 0 : sq->id = MLX5_GET(create_sq_out, out, sqn);
2007 : 0 : return sq;
2008 : : }
2009 : :
2010 : : /**
2011 : : * Modify SQ using DevX API.
2012 : : *
2013 : : * @param[in] sq
2014 : : * Pointer to SQ object structure.
2015 : : * @param [in] sq_attr
2016 : : * Pointer to SQ attributes structure.
2017 : : *
2018 : : * @return
2019 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
2020 : : */
2021 : : int
2022 : 0 : mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
2023 : : struct mlx5_devx_modify_sq_attr *sq_attr)
2024 : : {
2025 : 0 : uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0};
2026 : 0 : uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0};
2027 : : void *sq_ctx;
2028 : : int ret;
2029 : :
2030 : 0 : MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ);
2031 : 0 : MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state);
2032 [ # # ]: 0 : MLX5_SET(modify_sq_in, in, sqn, sq->id);
2033 : : sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2034 : 0 : MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
2035 : 0 : MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq);
2036 : 0 : MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca);
2037 : 0 : ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in),
2038 : : out, sizeof(out));
2039 [ # # ]: 0 : if (ret) {
2040 : 0 : DRV_LOG(ERR, "Failed to modify SQ using DevX");
2041 : 0 : rte_errno = errno;
2042 : 0 : return -rte_errno;
2043 : : }
2044 : : return ret;
2045 : : }
2046 : :
2047 : : /*
2048 : : * Query SQ using DevX API.
2049 : : *
2050 : : * @param[in] sq_obj
2051 : : * SQ Devx Object
2052 : : * @param[out] out
2053 : : * SQ Query Output
2054 : : * @param[in] outlen
2055 : : * SQ Query Output Length
2056 : : *
2057 : : * @return
2058 : : * 0 if Query successful, else non-zero return value from devx_obj_query API
2059 : : */
2060 : : int
2061 : 0 : mlx5_devx_cmd_query_sq(struct mlx5_devx_obj *sq_obj, void *out, size_t outlen)
2062 : : {
2063 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_sq_in)] = {0};
2064 : : int rc;
2065 : :
2066 : 0 : MLX5_SET(query_sq_in, in, opcode, MLX5_CMD_OP_QUERY_SQ);
2067 : 0 : MLX5_SET(query_sq_in, in, sqn, sq_obj->id);
2068 : 0 : rc = mlx5_glue->devx_obj_query(sq_obj->obj, in, sizeof(in), out, outlen);
2069 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
2070 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "SQ query", "sq_id", sq_obj->id);
2071 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
2072 : : }
2073 : : return 0;
2074 : : }
2075 : :
2076 : : /**
2077 : : * Create TIS using DevX API.
2078 : : *
2079 : : * @param[in] ctx
2080 : : * Context returned from mlx5 open_device() glue function.
2081 : : * @param [in] tis_attr
2082 : : * Pointer to TIS attributes structure.
2083 : : *
2084 : : * @return
2085 : : * The DevX object created, NULL otherwise and rte_errno is set.
2086 : : */
2087 : : struct mlx5_devx_obj *
2088 : 0 : mlx5_devx_cmd_create_tis(void *ctx,
2089 : : struct mlx5_devx_tis_attr *tis_attr)
2090 : : {
2091 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2092 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0};
2093 : : struct mlx5_devx_obj *tis = NULL;
2094 : : void *tis_ctx;
2095 : :
2096 : 0 : tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY);
2097 [ # # ]: 0 : if (!tis) {
2098 : 0 : DRV_LOG(ERR, "Failed to allocate TIS object");
2099 : 0 : rte_errno = ENOMEM;
2100 : 0 : return NULL;
2101 : : }
2102 [ # # ]: 0 : MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS);
2103 : : tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx);
2104 [ # # ]: 0 : MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,
2105 : : tis_attr->strict_lag_tx_port_affinity);
2106 [ # # ]: 0 : MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity,
2107 : : tis_attr->lag_tx_port_affinity);
2108 [ # # ]: 0 : MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio);
2109 [ # # ]: 0 : MLX5_SET(tisc, tis_ctx, transport_domain,
2110 : : tis_attr->transport_domain);
2111 : 0 : tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2112 : : out, sizeof(out));
2113 [ # # ]: 0 : if (!tis->obj) {
2114 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create TIS", NULL, 0);
2115 : 0 : mlx5_free(tis);
2116 : 0 : return NULL;
2117 : : }
2118 [ # # ]: 0 : tis->id = MLX5_GET(create_tis_out, out, tisn);
2119 : 0 : return tis;
2120 : : }
2121 : :
2122 : : /**
2123 : : * Create transport domain using DevX API.
2124 : : *
2125 : : * @param[in] ctx
2126 : : * Context returned from mlx5 open_device() glue function.
2127 : : * @return
2128 : : * The DevX object created, NULL otherwise and rte_errno is set.
2129 : : */
2130 : : struct mlx5_devx_obj *
2131 : 0 : mlx5_devx_cmd_create_td(void *ctx)
2132 : : {
2133 : 0 : uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0};
2134 : 0 : uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0};
2135 : : struct mlx5_devx_obj *td = NULL;
2136 : :
2137 : 0 : td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY);
2138 [ # # ]: 0 : if (!td) {
2139 : 0 : DRV_LOG(ERR, "Failed to allocate TD object");
2140 : 0 : rte_errno = ENOMEM;
2141 : 0 : return NULL;
2142 : : }
2143 [ # # ]: 0 : MLX5_SET(alloc_transport_domain_in, in, opcode,
2144 : : MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN);
2145 : 0 : td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2146 : : out, sizeof(out));
2147 [ # # ]: 0 : if (!td->obj) {
2148 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create TIS", NULL, 0);
2149 : 0 : mlx5_free(td);
2150 : 0 : return NULL;
2151 : : }
2152 [ # # ]: 0 : td->id = MLX5_GET(alloc_transport_domain_out, out,
2153 : : transport_domain);
2154 : 0 : return td;
2155 : : }
2156 : :
2157 : : /**
2158 : : * Dump all flows to file.
2159 : : *
2160 : : * @param[in] fdb_domain
2161 : : * FDB domain.
2162 : : * @param[in] rx_domain
2163 : : * RX domain.
2164 : : * @param[in] tx_domain
2165 : : * TX domain.
2166 : : * @param[out] file
2167 : : * Pointer to file stream.
2168 : : *
2169 : : * @return
2170 : : * 0 on success, a negative value otherwise.
2171 : : */
2172 : : int
2173 : 0 : mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused,
2174 : : void *rx_domain __rte_unused,
2175 : : void *tx_domain __rte_unused, FILE *file __rte_unused)
2176 : : {
2177 : : int ret = 0;
2178 : :
2179 : : #ifdef HAVE_MLX5_DR_FLOW_DUMP
2180 [ # # ]: 0 : if (fdb_domain) {
2181 : 0 : ret = mlx5_glue->dr_dump_domain(file, fdb_domain);
2182 [ # # ]: 0 : if (ret)
2183 : : return ret;
2184 : : }
2185 : : MLX5_ASSERT(rx_domain);
2186 : 0 : ret = mlx5_glue->dr_dump_domain(file, rx_domain);
2187 [ # # ]: 0 : if (ret)
2188 : : return ret;
2189 : : MLX5_ASSERT(tx_domain);
2190 : 0 : ret = mlx5_glue->dr_dump_domain(file, tx_domain);
2191 : : #else
2192 : : ret = ENOTSUP;
2193 : : #endif
2194 : 0 : return -ret;
2195 : : }
2196 : :
2197 : : int
2198 : 0 : mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused,
2199 : : FILE *file __rte_unused)
2200 : : {
2201 : : int ret = 0;
2202 : : #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE
2203 [ # # ]: 0 : if (rule_info)
2204 : 0 : ret = mlx5_glue->dr_dump_rule(file, rule_info);
2205 : : #else
2206 : : ret = ENOTSUP;
2207 : : #endif
2208 : 0 : return -ret;
2209 : : }
2210 : :
2211 : : /*
2212 : : * Create CQ using DevX API.
2213 : : *
2214 : : * @param[in] ctx
2215 : : * Context returned from mlx5 open_device() glue function.
2216 : : * @param [in] attr
2217 : : * Pointer to CQ attributes structure.
2218 : : *
2219 : : * @return
2220 : : * The DevX object created, NULL otherwise and rte_errno is set.
2221 : : */
2222 : : struct mlx5_devx_obj *
2223 : 0 : mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr)
2224 : : {
2225 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0};
2226 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0};
2227 : 0 : struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO,
2228 : : sizeof(*cq_obj),
2229 : : 0, SOCKET_ID_ANY);
2230 : : void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context);
2231 : :
2232 [ # # ]: 0 : if (!cq_obj) {
2233 : 0 : DRV_LOG(ERR, "Failed to allocate CQ object memory.");
2234 : 0 : rte_errno = ENOMEM;
2235 : 0 : return NULL;
2236 : : }
2237 [ # # ]: 0 : MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ);
2238 [ # # ]: 0 : if (attr->db_umem_valid) {
2239 [ # # ]: 0 : MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid);
2240 [ # # ]: 0 : MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id);
2241 [ # # ]: 0 : MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset);
2242 : : } else {
2243 [ # # ]: 0 : MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr);
2244 : : }
2245 [ # # ]: 0 : MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ?
2246 : : MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B);
2247 [ # # ]: 0 : MLX5_SET(cqc, cqctx, cc, attr->use_first_only);
2248 [ # # ]: 0 : MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore);
2249 [ # # ]: 0 : MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size);
2250 [ # # ]: 0 : if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)
2251 [ # # ]: 0 : MLX5_SET(cqc, cqctx, log_page_size,
2252 : : attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT);
2253 [ # # ]: 0 : MLX5_SET(cqc, cqctx, c_eqn, attr->eqn);
2254 [ # # ]: 0 : MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id);
2255 [ # # ]: 0 : MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en);
2256 [ # # ]: 0 : MLX5_SET(cqc, cqctx, cqe_comp_layout, !!attr->cqe_comp_layout);
2257 [ # # ]: 0 : MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format);
2258 [ # # ]: 0 : MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext,
2259 : : attr->mini_cqe_res_format_ext);
2260 [ # # ]: 0 : if (attr->q_umem_valid) {
2261 [ # # ]: 0 : MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid);
2262 [ # # ]: 0 : MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id);
2263 [ # # ]: 0 : MLX5_SET64(create_cq_in, in, cq_umem_offset,
2264 : : attr->q_umem_offset);
2265 : : }
2266 : 0 : cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2267 : : sizeof(out));
2268 [ # # ]: 0 : if (!cq_obj->obj) {
2269 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create CQ", NULL, 0);
2270 : 0 : mlx5_free(cq_obj);
2271 : 0 : return NULL;
2272 : : }
2273 [ # # ]: 0 : cq_obj->id = MLX5_GET(create_cq_out, out, cqn);
2274 : 0 : return cq_obj;
2275 : : }
2276 : :
2277 : : /*
2278 : : * Query CQ using DevX API.
2279 : : *
2280 : : * @param[in] cq_obj
2281 : : * CQ Devx Object
2282 : : * @param[out] out
2283 : : * CQ Query Output
2284 : : * @param[in] outlen
2285 : : * CQ Query Output Length
2286 : : *
2287 : : * @return
2288 : : * 0 if Query successful, else non-zero return value from devx_obj_query API
2289 : : */
2290 : : int
2291 : 0 : mlx5_devx_cmd_query_cq(struct mlx5_devx_obj *cq_obj, void *out, size_t outlen)
2292 : : {
2293 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_cq_in)] = {0};
2294 : : int rc;
2295 : :
2296 : 0 : MLX5_SET(query_cq_in, in, opcode, MLX5_CMD_OP_QUERY_CQ);
2297 : 0 : MLX5_SET(query_cq_in, in, cqn, cq_obj->id);
2298 : 0 : rc = mlx5_glue->devx_obj_query(cq_obj->obj, in, sizeof(in), out, outlen);
2299 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
2300 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "CQ query", "cq_id", cq_obj->id);
2301 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
2302 : : }
2303 : : return 0;
2304 : : }
2305 : :
2306 : : /**
2307 : : * Create VIRTQ using DevX API.
2308 : : *
2309 : : * @param[in] ctx
2310 : : * Context returned from mlx5 open_device() glue function.
2311 : : * @param [in] attr
2312 : : * Pointer to VIRTQ attributes structure.
2313 : : *
2314 : : * @return
2315 : : * The DevX object created, NULL otherwise and rte_errno is set.
2316 : : */
2317 : : struct mlx5_devx_obj *
2318 : 0 : mlx5_devx_cmd_create_virtq(void *ctx,
2319 : : struct mlx5_devx_virtq_attr *attr)
2320 : : {
2321 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
2322 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2323 : 0 : struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO,
2324 : : sizeof(*virtq_obj),
2325 : : 0, SOCKET_ID_ANY);
2326 : : void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
2327 : : void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
2328 : : void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
2329 : :
2330 [ # # ]: 0 : if (!virtq_obj) {
2331 : 0 : DRV_LOG(ERR, "Failed to allocate virtq data.");
2332 : 0 : rte_errno = ENOMEM;
2333 : 0 : return NULL;
2334 : : }
2335 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2336 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2337 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2338 : : MLX5_GENERAL_OBJ_TYPE_VIRTQ);
2339 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, hw_available_index,
2340 : : attr->hw_available_index);
2341 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index);
2342 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4);
2343 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6);
2344 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum);
2345 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum);
2346 [ # # ]: 0 : MLX5_SET16(virtio_q, virtctx, virtio_version_1_0,
2347 : : attr->virtio_version_1_0);
2348 [ # # ]: 0 : MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode);
2349 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id);
2350 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr);
2351 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr);
2352 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr);
2353 [ # # ]: 0 : MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
2354 [ # # ]: 0 : MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size);
2355 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey);
2356 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id);
2357 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size);
2358 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset);
2359 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id);
2360 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size);
2361 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset);
2362 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id);
2363 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size);
2364 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset);
2365 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id);
2366 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, pd, attr->pd);
2367 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode);
2368 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us);
2369 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp);
2370 [ # # ]: 0 : MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id);
2371 : 0 : virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2372 : : sizeof(out));
2373 [ # # ]: 0 : if (!virtq_obj->obj) {
2374 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create VIRTQ", NULL, 0);
2375 : 0 : mlx5_free(virtq_obj);
2376 : 0 : return NULL;
2377 : : }
2378 [ # # ]: 0 : virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2379 : 0 : return virtq_obj;
2380 : : }
2381 : :
2382 : : /**
2383 : : * Modify VIRTQ using DevX API.
2384 : : *
2385 : : * @param[in] virtq_obj
2386 : : * Pointer to virtq object structure.
2387 : : * @param [in] attr
2388 : : * Pointer to modify virtq attributes structure.
2389 : : *
2390 : : * @return
2391 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
2392 : : */
2393 : : int
2394 : 0 : mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,
2395 : : struct mlx5_devx_virtq_attr *attr)
2396 : : {
2397 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
2398 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2399 : : void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
2400 : : void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
2401 : : void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
2402 : : int ret;
2403 : :
2404 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2405 : : MLX5_CMD_OP_MODIFY_GENERAL_OBJECT);
2406 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2407 : : MLX5_GENERAL_OBJ_TYPE_VIRTQ);
2408 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
2409 [ # # ]: 0 : MLX5_SET64(virtio_net_q, virtq, modify_field_select,
2410 : : attr->mod_fields_bitmap);
2411 : 0 : MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
2412 [ # # ]: 0 : if (!attr->mod_fields_bitmap) {
2413 : 0 : DRV_LOG(ERR, "Failed to modify VIRTQ for no type set.");
2414 : 0 : rte_errno = EINVAL;
2415 : 0 : return -rte_errno;
2416 : : }
2417 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_STATE)
2418 : 0 : MLX5_SET16(virtio_net_q, virtq, state, attr->state);
2419 [ # # ]: 0 : if (attr->mod_fields_bitmap &
2420 : : MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS) {
2421 : 0 : MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey,
2422 : : attr->dirty_bitmap_mkey);
2423 [ # # ]: 0 : MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr,
2424 : : attr->dirty_bitmap_addr);
2425 : 0 : MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size,
2426 : : attr->dirty_bitmap_size);
2427 : : }
2428 [ # # ]: 0 : if (attr->mod_fields_bitmap &
2429 : : MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE)
2430 [ # # ]: 0 : MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable,
2431 : : attr->dirty_bitmap_dump_enable);
2432 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_QUEUE_PERIOD) {
2433 : 0 : MLX5_SET(virtio_q, virtctx, queue_period_mode,
2434 : : attr->hw_latency_mode);
2435 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, queue_period_us,
2436 : : attr->hw_max_latency_us);
2437 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, queue_max_count,
2438 : : attr->hw_max_pending_comp);
2439 : : }
2440 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_ADDR) {
2441 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr);
2442 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr);
2443 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, available_addr,
2444 : : attr->available_addr);
2445 : : }
2446 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_AVAILABLE_INDEX)
2447 : 0 : MLX5_SET16(virtio_net_q, virtq, hw_available_index,
2448 : : attr->hw_available_index);
2449 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_USED_INDEX)
2450 : 0 : MLX5_SET16(virtio_net_q, virtq, hw_used_index,
2451 : : attr->hw_used_index);
2452 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_TYPE)
2453 : 0 : MLX5_SET16(virtio_q, virtctx, virtio_q_type, attr->q_type);
2454 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_VERSION_1_0)
2455 : 0 : MLX5_SET16(virtio_q, virtctx, virtio_version_1_0,
2456 : : attr->virtio_version_1_0);
2457 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_MKEY)
2458 : 0 : MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey);
2459 [ # # ]: 0 : if (attr->mod_fields_bitmap &
2460 : : MLX5_VIRTQ_MODIFY_TYPE_QUEUE_FEATURE_BIT_MASK) {
2461 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4);
2462 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6);
2463 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum);
2464 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum);
2465 : : }
2466 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_EVENT_MODE) {
2467 [ # # ]: 0 : MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode);
2468 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id);
2469 : : }
2470 : 0 : ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in),
2471 : : out, sizeof(out));
2472 [ # # ]: 0 : if (ret) {
2473 : 0 : DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
2474 : 0 : rte_errno = errno;
2475 : 0 : return -rte_errno;
2476 : : }
2477 : : return ret;
2478 : : }
2479 : :
2480 : : /**
2481 : : * Query VIRTQ using DevX API.
2482 : : *
2483 : : * @param[in] virtq_obj
2484 : : * Pointer to virtq object structure.
2485 : : * @param [in/out] attr
2486 : : * Pointer to virtq attributes structure.
2487 : : *
2488 : : * @return
2489 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
2490 : : */
2491 : : int
2492 : 0 : mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,
2493 : : struct mlx5_devx_virtq_attr *attr)
2494 : : {
2495 : 0 : uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
2496 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0};
2497 : : void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr);
2498 : : void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq);
2499 : : int ret;
2500 : :
2501 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2502 : : MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
2503 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2504 : : MLX5_GENERAL_OBJ_TYPE_VIRTQ);
2505 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
2506 : 0 : ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in),
2507 : : out, sizeof(out));
2508 [ # # ]: 0 : if (ret) {
2509 : 0 : DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
2510 : 0 : rte_errno = errno;
2511 : 0 : return -errno;
2512 : : }
2513 [ # # ]: 0 : attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq,
2514 : : hw_available_index);
2515 [ # # ]: 0 : attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index);
2516 [ # # ]: 0 : attr->state = MLX5_GET16(virtio_net_q, virtq, state);
2517 [ # # ]: 0 : attr->error_type = MLX5_GET16(virtio_net_q, virtq,
2518 : : virtio_q_context.error_type);
2519 : 0 : return ret;
2520 : : }
2521 : :
2522 : : /**
2523 : : * Create QP using DevX API.
2524 : : *
2525 : : * @param[in] ctx
2526 : : * Context returned from mlx5 open_device() glue function.
2527 : : * @param [in] attr
2528 : : * Pointer to QP attributes structure.
2529 : : *
2530 : : * @return
2531 : : * The DevX object created, NULL otherwise and rte_errno is set.
2532 : : */
2533 : : struct mlx5_devx_obj *
2534 : 0 : mlx5_devx_cmd_create_qp(void *ctx,
2535 : : struct mlx5_devx_qp_attr *attr)
2536 : : {
2537 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0};
2538 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0};
2539 : 0 : struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO,
2540 : : sizeof(*qp_obj),
2541 : : 0, SOCKET_ID_ANY);
2542 : : void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
2543 : :
2544 [ # # ]: 0 : if (!qp_obj) {
2545 : 0 : DRV_LOG(ERR, "Failed to allocate QP data.");
2546 : 0 : rte_errno = ENOMEM;
2547 : 0 : return NULL;
2548 : : }
2549 [ # # ]: 0 : MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP);
2550 [ # # ]: 0 : MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC);
2551 [ # # ]: 0 : MLX5_SET(qpc, qpc, pd, attr->pd);
2552 [ # # ]: 0 : MLX5_SET(qpc, qpc, ts_format, attr->ts_format);
2553 [ # # ]: 0 : MLX5_SET(qpc, qpc, user_index, attr->user_index);
2554 [ # # ]: 0 : if (attr->uar_index) {
2555 [ # # ]: 0 : if (attr->mmo) {
2556 : : void *qpc_ext_and_pas_list = MLX5_ADDR_OF(create_qp_in,
2557 : : in, qpc_extension_and_pas_list);
2558 : : void *qpc_ext = MLX5_ADDR_OF(qpc_extension_and_pas_list,
2559 : : qpc_ext_and_pas_list, qpc_data_extension);
2560 : :
2561 [ # # ]: 0 : MLX5_SET(create_qp_in, in, qpc_ext, 1);
2562 [ # # ]: 0 : MLX5_SET(qpc_extension, qpc_ext, mmo, 1);
2563 : : }
2564 [ # # ]: 0 : MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2565 [ # # ]: 0 : MLX5_SET(qpc, qpc, uar_page, attr->uar_index);
2566 [ # # ]: 0 : if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)
2567 [ # # ]: 0 : MLX5_SET(qpc, qpc, log_page_size,
2568 : : attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT);
2569 [ # # ]: 0 : if (attr->num_of_send_wqbbs) {
2570 : : MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->num_of_send_wqbbs));
2571 [ # # ]: 0 : MLX5_SET(qpc, qpc, cqn_snd, attr->cqn);
2572 [ # # ]: 0 : MLX5_SET(qpc, qpc, log_sq_size,
2573 : : rte_log2_u32(attr->num_of_send_wqbbs));
2574 : : } else {
2575 [ # # ]: 0 : MLX5_SET(qpc, qpc, no_sq, 1);
2576 : : }
2577 [ # # ]: 0 : if (attr->num_of_receive_wqes) {
2578 : : MLX5_ASSERT(RTE_IS_POWER_OF_2(
2579 : : attr->num_of_receive_wqes));
2580 [ # # ]: 0 : MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn);
2581 [ # # ]: 0 : MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride -
2582 : : MLX5_LOG_RQ_STRIDE_SHIFT);
2583 [ # # # # ]: 0 : MLX5_SET(qpc, qpc, log_rq_size,
2584 : : rte_log2_u32(attr->num_of_receive_wqes));
2585 [ # # ]: 0 : MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ);
2586 : : } else {
2587 [ # # ]: 0 : MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
2588 : : }
2589 [ # # ]: 0 : if (attr->dbr_umem_valid) {
2590 [ # # ]: 0 : MLX5_SET(qpc, qpc, dbr_umem_valid,
2591 : : attr->dbr_umem_valid);
2592 [ # # ]: 0 : MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id);
2593 : : }
2594 [ # # ]: 0 : if (attr->cd_master)
2595 [ # # ]: 0 : MLX5_SET(qpc, qpc, cd_master, attr->cd_master);
2596 [ # # ]: 0 : if (attr->cd_slave_send)
2597 [ # # ]: 0 : MLX5_SET(qpc, qpc, cd_slave_send, attr->cd_slave_send);
2598 [ # # ]: 0 : if (attr->cd_slave_recv)
2599 [ # # ]: 0 : MLX5_SET(qpc, qpc, cd_slave_receive, attr->cd_slave_recv);
2600 [ # # ]: 0 : MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address);
2601 [ # # ]: 0 : MLX5_SET64(create_qp_in, in, wq_umem_offset,
2602 : : attr->wq_umem_offset);
2603 [ # # ]: 0 : MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id);
2604 [ # # ]: 0 : MLX5_SET(create_qp_in, in, wq_umem_valid, 1);
2605 : : } else {
2606 : : /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */
2607 [ # # ]: 0 : MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
2608 [ # # ]: 0 : MLX5_SET(qpc, qpc, no_sq, 1);
2609 : : }
2610 : 0 : qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2611 : : sizeof(out));
2612 [ # # ]: 0 : if (!qp_obj->obj) {
2613 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create QP", NULL, 0);
2614 : 0 : mlx5_free(qp_obj);
2615 : 0 : return NULL;
2616 : : }
2617 [ # # ]: 0 : qp_obj->id = MLX5_GET(create_qp_out, out, qpn);
2618 : 0 : return qp_obj;
2619 : : }
2620 : :
2621 : : /**
2622 : : * Modify QP using DevX API.
2623 : : * Currently supports only force loop-back QP.
2624 : : *
2625 : : * @param[in] qp
2626 : : * Pointer to QP object structure.
2627 : : * @param [in] qp_st_mod_op
2628 : : * The QP state modification operation.
2629 : : * @param [in] remote_qp_id
2630 : : * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation.
2631 : : *
2632 : : * @return
2633 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
2634 : : */
2635 : : int
2636 : 0 : mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op,
2637 : : uint32_t remote_qp_id)
2638 : : {
2639 : : union {
2640 : : uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)];
2641 : : uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)];
2642 : : uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)];
2643 : : uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_in)];
2644 : : } in;
2645 : : union {
2646 : : uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)];
2647 : : uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)];
2648 : : uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)];
2649 : : uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_out)];
2650 : : } out;
2651 : : void *qpc;
2652 : : int ret;
2653 : : unsigned int inlen;
2654 : : unsigned int outlen;
2655 : :
2656 : : memset(&in, 0, sizeof(in));
2657 : : memset(&out, 0, sizeof(out));
2658 : 0 : MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op);
2659 [ # # # # : 0 : switch (qp_st_mod_op) {
# ]
2660 : 0 : case MLX5_CMD_OP_RST2INIT_QP:
2661 : 0 : MLX5_SET(rst2init_qp_in, &in, qpn, qp->id);
2662 : : qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc);
2663 : 0 : MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
2664 : : MLX5_SET(qpc, qpc, rre, 1);
2665 [ # # ]: 0 : MLX5_SET(qpc, qpc, rwe, 1);
2666 : 0 : MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2667 : : inlen = sizeof(in.rst2init);
2668 : : outlen = sizeof(out.rst2init);
2669 : 0 : break;
2670 : 0 : case MLX5_CMD_OP_INIT2RTR_QP:
2671 : 0 : MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id);
2672 : : qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc);
2673 : 0 : MLX5_SET(qpc, qpc, primary_address_path.fl, 1);
2674 : 0 : MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
2675 : : MLX5_SET(qpc, qpc, mtu, 1);
2676 [ # # ]: 0 : MLX5_SET(qpc, qpc, log_msg_max, 30);
2677 : 0 : MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id);
2678 : 0 : MLX5_SET(qpc, qpc, min_rnr_nak, 0);
2679 : : inlen = sizeof(in.init2rtr);
2680 : : outlen = sizeof(out.init2rtr);
2681 : 0 : break;
2682 : 0 : case MLX5_CMD_OP_RTR2RTS_QP:
2683 : : qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc);
2684 : 0 : MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id);
2685 : 0 : MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 16);
2686 : : MLX5_SET(qpc, qpc, log_ack_req_freq, 0);
2687 [ # # ]: 0 : MLX5_SET(qpc, qpc, retry_count, 7);
2688 [ # # ]: 0 : MLX5_SET(qpc, qpc, rnr_retry, 7);
2689 : : inlen = sizeof(in.rtr2rts);
2690 : : outlen = sizeof(out.rtr2rts);
2691 : 0 : break;
2692 : 0 : case MLX5_CMD_OP_QP_2RST:
2693 : 0 : MLX5_SET(2rst_qp_in, &in, qpn, qp->id);
2694 : : inlen = sizeof(in.qp2rst);
2695 : : outlen = sizeof(out.qp2rst);
2696 : 0 : break;
2697 : 0 : default:
2698 : 0 : DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.",
2699 : : qp_st_mod_op);
2700 : 0 : rte_errno = EINVAL;
2701 : 0 : return -rte_errno;
2702 : : }
2703 : 0 : ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen);
2704 [ # # ]: 0 : if (ret) {
2705 : 0 : DRV_LOG(ERR, "Failed to modify QP using DevX.");
2706 : 0 : rte_errno = errno;
2707 : 0 : return -rte_errno;
2708 : : }
2709 : : return ret;
2710 : : }
2711 : :
2712 : : struct mlx5_devx_obj *
2713 : 0 : mlx5_devx_cmd_create_virtio_q_counters(void *ctx)
2714 : : {
2715 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0};
2716 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2717 : 0 : struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO,
2718 : : sizeof(*couners_obj), 0,
2719 : : SOCKET_ID_ANY);
2720 : : void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr);
2721 : :
2722 [ # # ]: 0 : if (!couners_obj) {
2723 : 0 : DRV_LOG(ERR, "Failed to allocate virtio queue counters data.");
2724 : 0 : rte_errno = ENOMEM;
2725 : 0 : return NULL;
2726 : : }
2727 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2728 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2729 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2730 : : MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
2731 : 0 : couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2732 : : sizeof(out));
2733 [ # # ]: 0 : if (!couners_obj->obj) {
2734 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create virtio queue counters Obj", NULL,
2735 : : 0);
2736 : 0 : mlx5_free(couners_obj);
2737 : 0 : return NULL;
2738 : : }
2739 [ # # ]: 0 : couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2740 : 0 : return couners_obj;
2741 : : }
2742 : :
2743 : : int
2744 : 0 : mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,
2745 : : struct mlx5_devx_virtio_q_couners_attr *attr)
2746 : : {
2747 : 0 : uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
2748 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0};
2749 : : void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr);
2750 : : void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out,
2751 : : virtio_q_counters);
2752 : : int ret;
2753 : :
2754 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2755 : : MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
2756 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2757 : : MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
2758 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id);
2759 : 0 : ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out,
2760 : : sizeof(out));
2761 [ # # ]: 0 : if (ret) {
2762 : 0 : DRV_LOG(ERR, "Failed to query virtio q counters using DevX.");
2763 : 0 : rte_errno = errno;
2764 : 0 : return -errno;
2765 : : }
2766 [ # # ]: 0 : attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
2767 : : received_desc);
2768 [ # # ]: 0 : attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
2769 : : completed_desc);
2770 [ # # ]: 0 : attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters,
2771 : : error_cqes);
2772 [ # # ]: 0 : attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters,
2773 : : bad_desc_errors);
2774 [ # # ]: 0 : attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters,
2775 : : exceed_max_chain);
2776 [ # # ]: 0 : attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters,
2777 : : invalid_buffer);
2778 : 0 : return ret;
2779 : : }
2780 : :
2781 : : /**
2782 : : * Create general object of type FLOW_HIT_ASO using DevX API.
2783 : : *
2784 : : * @param[in] ctx
2785 : : * Context returned from mlx5 open_device() glue function.
2786 : : * @param [in] pd
2787 : : * PD value to associate the FLOW_HIT_ASO object with.
2788 : : *
2789 : : * @return
2790 : : * The DevX object created, NULL otherwise and rte_errno is set.
2791 : : */
2792 : : struct mlx5_devx_obj *
2793 : 0 : mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd)
2794 : : {
2795 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0};
2796 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2797 : : struct mlx5_devx_obj *flow_hit_aso_obj = NULL;
2798 : : void *ptr = NULL;
2799 : :
2800 : 0 : flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj),
2801 : : 0, SOCKET_ID_ANY);
2802 [ # # ]: 0 : if (!flow_hit_aso_obj) {
2803 : 0 : DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data");
2804 : 0 : rte_errno = ENOMEM;
2805 : 0 : return NULL;
2806 : : }
2807 : : ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr);
2808 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2809 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2810 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2811 : : MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO);
2812 : : ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso);
2813 [ # # ]: 0 : MLX5_SET(flow_hit_aso, ptr, access_pd, pd);
2814 : 0 : flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2815 : : out, sizeof(out));
2816 [ # # ]: 0 : if (!flow_hit_aso_obj->obj) {
2817 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create FLOW_HIT_ASO", NULL, 0);
2818 : 0 : mlx5_free(flow_hit_aso_obj);
2819 : 0 : return NULL;
2820 : : }
2821 [ # # ]: 0 : flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2822 : 0 : return flow_hit_aso_obj;
2823 : : }
2824 : :
2825 : : /*
2826 : : * Create PD using DevX API.
2827 : : *
2828 : : * @param[in] ctx
2829 : : * Context returned from mlx5 open_device() glue function.
2830 : : *
2831 : : * @return
2832 : : * The DevX object created, NULL otherwise and rte_errno is set.
2833 : : */
2834 : : struct mlx5_devx_obj *
2835 : 0 : mlx5_devx_cmd_alloc_pd(void *ctx)
2836 : : {
2837 : : struct mlx5_devx_obj *ppd =
2838 : 0 : mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY);
2839 : 0 : u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0};
2840 : 0 : u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0};
2841 : :
2842 [ # # ]: 0 : if (!ppd) {
2843 : 0 : DRV_LOG(ERR, "Failed to allocate PD data.");
2844 : 0 : rte_errno = ENOMEM;
2845 : 0 : return NULL;
2846 : : }
2847 : 0 : MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2848 : 0 : ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2849 : : out, sizeof(out));
2850 [ # # ]: 0 : if (!ppd->obj) {
2851 : 0 : mlx5_free(ppd);
2852 : 0 : DRV_LOG(ERR, "Failed to allocate PD Obj using DevX.");
2853 : 0 : rte_errno = errno;
2854 : 0 : return NULL;
2855 : : }
2856 [ # # ]: 0 : ppd->id = MLX5_GET(alloc_pd_out, out, pd);
2857 : 0 : return ppd;
2858 : : }
2859 : :
2860 : : /**
2861 : : * Create general object of type FLOW_METER_ASO using DevX API.
2862 : : *
2863 : : * @param[in] ctx
2864 : : * Context returned from mlx5 open_device() glue function.
2865 : : * @param [in] pd
2866 : : * PD value to associate the FLOW_METER_ASO object with.
2867 : : * @param [in] log_obj_size
2868 : : * log_obj_size define to allocate number of 2 * meters
2869 : : * in one FLOW_METER_ASO object.
2870 : : *
2871 : : * @return
2872 : : * The DevX object created, NULL otherwise and rte_errno is set.
2873 : : */
2874 : : struct mlx5_devx_obj *
2875 : 0 : mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd,
2876 : : uint32_t log_obj_size)
2877 : : {
2878 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0};
2879 : : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
2880 : : struct mlx5_devx_obj *flow_meter_aso_obj;
2881 : : void *ptr;
2882 : :
2883 : 0 : flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO,
2884 : : sizeof(*flow_meter_aso_obj),
2885 : : 0, SOCKET_ID_ANY);
2886 [ # # ]: 0 : if (!flow_meter_aso_obj) {
2887 : 0 : DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data");
2888 : 0 : rte_errno = ENOMEM;
2889 : 0 : return NULL;
2890 : : }
2891 : : ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr);
2892 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2893 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2894 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2895 : : MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO);
2896 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range,
2897 : : log_obj_size);
2898 : : ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso);
2899 [ # # ]: 0 : MLX5_SET(flow_meter_aso, ptr, access_pd, pd);
2900 : 0 : flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create(
2901 : : ctx, in, sizeof(in),
2902 : : out, sizeof(out));
2903 [ # # ]: 0 : if (!flow_meter_aso_obj->obj) {
2904 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create FLOW_METTER_ASO", NULL, 0);
2905 : 0 : mlx5_free(flow_meter_aso_obj);
2906 : 0 : return NULL;
2907 : : }
2908 [ # # ]: 0 : flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr,
2909 : : out, obj_id);
2910 : 0 : return flow_meter_aso_obj;
2911 : : }
2912 : :
2913 : : /*
2914 : : * Create general object of type CONN_TRACK_OFFLOAD using DevX API.
2915 : : *
2916 : : * @param[in] ctx
2917 : : * Context returned from mlx5 open_device() glue function.
2918 : : * @param [in] pd
2919 : : * PD value to associate the CONN_TRACK_OFFLOAD ASO object with.
2920 : : * @param [in] log_obj_size
2921 : : * log_obj_size to allocate its power of 2 * objects
2922 : : * in one CONN_TRACK_OFFLOAD bulk allocation.
2923 : : *
2924 : : * @return
2925 : : * The DevX object created, NULL otherwise and rte_errno is set.
2926 : : */
2927 : : struct mlx5_devx_obj *
2928 : 0 : mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, uint32_t pd,
2929 : : uint32_t log_obj_size)
2930 : : {
2931 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_conn_track_aso_in)] = {0};
2932 : : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
2933 : : struct mlx5_devx_obj *ct_aso_obj;
2934 : : void *ptr;
2935 : :
2936 : 0 : ct_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ct_aso_obj),
2937 : : 0, SOCKET_ID_ANY);
2938 [ # # ]: 0 : if (!ct_aso_obj) {
2939 : 0 : DRV_LOG(ERR, "Failed to allocate CONN_TRACK_OFFLOAD object.");
2940 : 0 : rte_errno = ENOMEM;
2941 : 0 : return NULL;
2942 : : }
2943 : : ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, hdr);
2944 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2945 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2946 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2947 : : MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD);
2948 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, log_obj_size);
2949 : : ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, conn_track_offload);
2950 [ # # ]: 0 : MLX5_SET(conn_track_offload, ptr, conn_track_aso_access_pd, pd);
2951 : 0 : ct_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2952 : : out, sizeof(out));
2953 [ # # ]: 0 : if (!ct_aso_obj->obj) {
2954 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create CONN_TRACK_OFFLOAD", NULL, 0);
2955 : 0 : mlx5_free(ct_aso_obj);
2956 : 0 : return NULL;
2957 : : }
2958 [ # # ]: 0 : ct_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2959 : 0 : return ct_aso_obj;
2960 : : }
2961 : :
2962 : : /**
2963 : : * Create general object of type GENEVE TLV option using DevX API.
2964 : : *
2965 : : * @param[in] ctx
2966 : : * Context returned from mlx5 open_device() glue function.
2967 : : * @param[in] attr
2968 : : * Pointer to GENEVE TLV option attributes structure.
2969 : : *
2970 : : * @return
2971 : : * The DevX object created, NULL otherwise and rte_errno is set.
2972 : : */
2973 : : struct mlx5_devx_obj *
2974 : 0 : mlx5_devx_cmd_create_geneve_tlv_option(void *ctx,
2975 : : struct mlx5_devx_geneve_tlv_option_attr *attr)
2976 : : {
2977 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0};
2978 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2979 : 0 : struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO,
2980 : : sizeof(*geneve_tlv_opt_obj),
2981 : : 0, SOCKET_ID_ANY);
2982 : :
2983 [ # # ]: 0 : if (!geneve_tlv_opt_obj) {
2984 : 0 : DRV_LOG(ERR, "Failed to allocate GENEVE TLV option object.");
2985 : 0 : rte_errno = ENOMEM;
2986 : 0 : return NULL;
2987 : : }
2988 : : void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr);
2989 : : void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in,
2990 : : geneve_tlv_opt);
2991 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2992 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2993 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2994 : : MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT);
2995 [ # # ]: 0 : MLX5_SET(geneve_tlv_option, opt, option_type, attr->option_type);
2996 [ # # ]: 0 : MLX5_SET(geneve_tlv_option, opt, option_data_length,
2997 : : attr->option_data_len);
2998 [ # # ]: 0 : if (attr->option_class_ignore)
2999 [ # # ]: 0 : MLX5_SET(geneve_tlv_option, opt, option_class_ignore,
3000 : : attr->option_class_ignore);
3001 : : else
3002 [ # # # # ]: 0 : MLX5_SET(geneve_tlv_option, opt, option_class,
3003 : : rte_be_to_cpu_16(attr->option_class));
3004 [ # # ]: 0 : if (attr->offset_valid) {
3005 [ # # ]: 0 : MLX5_SET(geneve_tlv_option, opt, sample_offset_valid,
3006 : : attr->offset_valid);
3007 [ # # ]: 0 : MLX5_SET(geneve_tlv_option, opt, sample_offset,
3008 : : attr->sample_offset);
3009 : : }
3010 : 0 : geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in,
3011 : : sizeof(in), out,
3012 : : sizeof(out));
3013 [ # # ]: 0 : if (!geneve_tlv_opt_obj->obj) {
3014 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create GENEVE TLV option", NULL, 0);
3015 : 0 : mlx5_free(geneve_tlv_opt_obj);
3016 : 0 : return NULL;
3017 : : }
3018 [ # # ]: 0 : geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
3019 : 0 : return geneve_tlv_opt_obj;
3020 : : }
3021 : :
3022 : : /**
3023 : : * Query GENEVE TLV option using DevX API.
3024 : : *
3025 : : * @param[in] ctx
3026 : : * Context used to create GENEVE TLV option object.
3027 : : * @param[in] geneve_tlv_opt_obj
3028 : : * DevX object of the GENEVE TLV option.
3029 : : * @param[out] attr
3030 : : * Pointer to match sample info attributes structure.
3031 : : *
3032 : : * @return
3033 : : * 0 on success, a negative errno otherwise and rte_errno is set.
3034 : : */
3035 : : int
3036 : 0 : mlx5_devx_cmd_query_geneve_tlv_option(void *ctx,
3037 : : struct mlx5_devx_obj *geneve_tlv_opt_obj,
3038 : : struct mlx5_devx_match_sample_info_query_attr *attr)
3039 : : {
3040 : 0 : uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
3041 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_geneve_tlv_option_out)] = {0};
3042 : : void *hdr = MLX5_ADDR_OF(query_geneve_tlv_option_out, in, hdr);
3043 : : void *opt = MLX5_ADDR_OF(query_geneve_tlv_option_out, out,
3044 : : geneve_tlv_opt);
3045 : : int ret;
3046 : :
3047 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
3048 : : MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
3049 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
3050 : : MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT);
3051 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, geneve_tlv_opt_obj->id);
3052 : : /* Call first query to get sample handle. */
3053 : 0 : ret = mlx5_glue->devx_obj_query(geneve_tlv_opt_obj->obj, in, sizeof(in),
3054 : : out, sizeof(out));
3055 [ # # ]: 0 : if (ret) {
3056 : 0 : DRV_LOG(ERR, "Failed to query GENEVE TLV option using DevX.");
3057 : 0 : rte_errno = errno;
3058 : 0 : return -errno;
3059 : : }
3060 : : /* Call second query to get sample information. */
3061 [ # # # # ]: 0 : if (MLX5_GET(geneve_tlv_option, opt, sample_id_valid)) {
3062 [ # # ]: 0 : uint32_t sample_id = MLX5_GET(geneve_tlv_option, opt,
3063 : : geneve_sample_field_id);
3064 : :
3065 : 0 : return mlx5_devx_cmd_match_sample_info_query(ctx, sample_id,
3066 : : attr);
3067 : : }
3068 : 0 : DRV_LOG(DEBUG, "GENEVE TLV option sample isn't valid.");
3069 : 0 : return 0;
3070 : : }
3071 : :
3072 : : int
3073 : 0 : mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id)
3074 : : {
3075 : : #ifdef HAVE_IBV_FLOW_DV_SUPPORT
3076 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0};
3077 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0};
3078 : : int rc;
3079 : : void *rq_ctx;
3080 : :
3081 : 0 : MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ);
3082 : 0 : MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num);
3083 : 0 : rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out));
3084 [ # # ]: 0 : if (rc) {
3085 : 0 : rte_errno = errno;
3086 : 0 : DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - "
3087 : : "rc = %d, errno = %d.", rc, errno);
3088 : 0 : return -rc;
3089 : : };
3090 : : rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context);
3091 [ # # ]: 0 : *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id);
3092 : 0 : return 0;
3093 : : #else
3094 : : (void)wq;
3095 : : (void)counter_set_id;
3096 : : return -ENOTSUP;
3097 : : #endif
3098 : : }
3099 : :
3100 : : /*
3101 : : * Allocate queue counters via devx interface.
3102 : : *
3103 : : * @param[in] ctx
3104 : : * Context returned from mlx5 open_device() glue function.
3105 : : * @param[out] syndrome
3106 : : * Get syndrome of devx command response.
3107 : : *
3108 : : * @return
3109 : : * Pointer to counter object on success, a NULL value otherwise and
3110 : : * rte_errno is set.
3111 : : */
3112 : : struct mlx5_devx_obj *
3113 : 0 : mlx5_devx_cmd_queue_counter_alloc(void *ctx, int *syndrome)
3114 : : {
3115 : : int status;
3116 : 0 : struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0,
3117 : : SOCKET_ID_ANY);
3118 : 0 : uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {0};
3119 : 0 : uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0};
3120 : :
3121 [ # # ]: 0 : if (!dcs) {
3122 : 0 : rte_errno = ENOMEM;
3123 : 0 : return NULL;
3124 : : }
3125 : 0 : MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
3126 : 0 : dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
3127 : : sizeof(out));
3128 [ # # ]: 0 : if (!dcs->obj) {
3129 [ # # # # ]: 0 : DEVX_DRV_LOG(DEBUG, out, "create q counter set", NULL, 0);
3130 [ # # ]: 0 : status = MLX5_GET(alloc_q_counter_out, out, status);
3131 [ # # ]: 0 : if (status && syndrome)
3132 [ # # ]: 0 : *syndrome = MLX5_GET(alloc_q_counter_out, out, syndrome);
3133 : 0 : mlx5_free(dcs);
3134 : 0 : return NULL;
3135 : : }
3136 [ # # ]: 0 : dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id);
3137 : 0 : return dcs;
3138 : : }
3139 : :
3140 : : /**
3141 : : * Query queue counters values.
3142 : : *
3143 : : * @param[in] dcs
3144 : : * devx object of the queue counter set.
3145 : : * @param[in] clear
3146 : : * Whether hardware should clear the counters after the query or not.
3147 : : * @param[out] out_of_buffers
3148 : : * Number of dropped occurred due to lack of WQE for the associated QPs/RQs.
3149 : : *
3150 : : * @return
3151 : : * 0 on success, a negative value otherwise.
3152 : : */
3153 : : int
3154 : 0 : mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear,
3155 : : uint32_t *out_of_buffers)
3156 : : {
3157 : 0 : uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0};
3158 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0};
3159 : : int rc;
3160 : :
3161 : 0 : MLX5_SET(query_q_counter_in, in, opcode,
3162 : : MLX5_CMD_OP_QUERY_Q_COUNTER);
3163 : 0 : MLX5_SET(query_q_counter_in, in, op_mod, 0);
3164 : 0 : MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id);
3165 : 0 : MLX5_SET(query_q_counter_in, in, clear, !!clear);
3166 : 0 : rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
3167 : : sizeof(out));
3168 [ # # ]: 0 : if (rc) {
3169 : 0 : DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc);
3170 : 0 : rte_errno = rc;
3171 : 0 : return -rc;
3172 : : }
3173 [ # # ]: 0 : *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer);
3174 : 0 : return 0;
3175 : : }
3176 : :
3177 : : /**
3178 : : * Create general object of type DEK using DevX API.
3179 : : *
3180 : : * @param[in] ctx
3181 : : * Context returned from mlx5 open_device() glue function.
3182 : : * @param [in] attr
3183 : : * Pointer to DEK attributes structure.
3184 : : *
3185 : : * @return
3186 : : * The DevX object created, NULL otherwise and rte_errno is set.
3187 : : */
3188 : : struct mlx5_devx_obj *
3189 : 0 : mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr)
3190 : : {
3191 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0};
3192 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
3193 : : struct mlx5_devx_obj *dek_obj = NULL;
3194 : : void *ptr = NULL, *key_addr = NULL;
3195 : :
3196 : 0 : dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj),
3197 : : 0, SOCKET_ID_ANY);
3198 [ # # ]: 0 : if (dek_obj == NULL) {
3199 : 0 : DRV_LOG(ERR, "Failed to allocate DEK object data");
3200 : 0 : rte_errno = ENOMEM;
3201 : 0 : return NULL;
3202 : : }
3203 : : ptr = MLX5_ADDR_OF(create_dek_in, in, hdr);
3204 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
3205 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
3206 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
3207 : : MLX5_GENERAL_OBJ_TYPE_DEK);
3208 : : ptr = MLX5_ADDR_OF(create_dek_in, in, dek);
3209 [ # # ]: 0 : MLX5_SET(dek, ptr, key_size, attr->key_size);
3210 [ # # ]: 0 : MLX5_SET(dek, ptr, has_keytag, attr->has_keytag);
3211 [ # # ]: 0 : MLX5_SET(dek, ptr, key_purpose, attr->key_purpose);
3212 [ # # ]: 0 : MLX5_SET(dek, ptr, pd, attr->pd);
3213 [ # # ]: 0 : MLX5_SET64(dek, ptr, opaque, attr->opaque);
3214 : : key_addr = MLX5_ADDR_OF(dek, ptr, key);
3215 : 0 : memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE);
3216 : 0 : dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
3217 : : out, sizeof(out));
3218 [ # # ]: 0 : if (dek_obj->obj == NULL) {
3219 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create DEK", NULL, 0);
3220 : 0 : mlx5_free(dek_obj);
3221 : 0 : return NULL;
3222 : : }
3223 [ # # ]: 0 : dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
3224 : 0 : return dek_obj;
3225 : : }
3226 : :
3227 : : /**
3228 : : * Create general object of type IMPORT_KEK using DevX API.
3229 : : *
3230 : : * @param[in] ctx
3231 : : * Context returned from mlx5 open_device() glue function.
3232 : : * @param [in] attr
3233 : : * Pointer to IMPORT_KEK attributes structure.
3234 : : *
3235 : : * @return
3236 : : * The DevX object created, NULL otherwise and rte_errno is set.
3237 : : */
3238 : : struct mlx5_devx_obj *
3239 : 0 : mlx5_devx_cmd_create_import_kek_obj(void *ctx,
3240 : : struct mlx5_devx_import_kek_attr *attr)
3241 : : {
3242 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_import_kek_in)] = {0};
3243 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
3244 : : struct mlx5_devx_obj *import_kek_obj = NULL;
3245 : : void *ptr = NULL, *key_addr = NULL;
3246 : :
3247 : 0 : import_kek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*import_kek_obj),
3248 : : 0, SOCKET_ID_ANY);
3249 [ # # ]: 0 : if (import_kek_obj == NULL) {
3250 : 0 : DRV_LOG(ERR, "Failed to allocate IMPORT_KEK object data");
3251 : 0 : rte_errno = ENOMEM;
3252 : 0 : return NULL;
3253 : : }
3254 : : ptr = MLX5_ADDR_OF(create_import_kek_in, in, hdr);
3255 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
3256 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
3257 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
3258 : : MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK);
3259 : : ptr = MLX5_ADDR_OF(create_import_kek_in, in, import_kek);
3260 [ # # ]: 0 : MLX5_SET(import_kek, ptr, key_size, attr->key_size);
3261 : : key_addr = MLX5_ADDR_OF(import_kek, ptr, key);
3262 : 0 : memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE);
3263 : 0 : import_kek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
3264 : : out, sizeof(out));
3265 [ # # ]: 0 : if (import_kek_obj->obj == NULL) {
3266 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create IMPORT_KEK", NULL, 0);
3267 : 0 : mlx5_free(import_kek_obj);
3268 : 0 : return NULL;
3269 : : }
3270 [ # # ]: 0 : import_kek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
3271 : 0 : return import_kek_obj;
3272 : : }
3273 : :
3274 : : /**
3275 : : * Create general object of type CREDENTIAL using DevX API.
3276 : : *
3277 : : * @param[in] ctx
3278 : : * Context returned from mlx5 open_device() glue function.
3279 : : * @param [in] attr
3280 : : * Pointer to CREDENTIAL attributes structure.
3281 : : *
3282 : : * @return
3283 : : * The DevX object created, NULL otherwise and rte_errno is set.
3284 : : */
3285 : : struct mlx5_devx_obj *
3286 : 0 : mlx5_devx_cmd_create_credential_obj(void *ctx,
3287 : : struct mlx5_devx_credential_attr *attr)
3288 : : {
3289 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_credential_in)] = {0};
3290 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
3291 : : struct mlx5_devx_obj *credential_obj = NULL;
3292 : : void *ptr = NULL, *credential_addr = NULL;
3293 : :
3294 : 0 : credential_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*credential_obj),
3295 : : 0, SOCKET_ID_ANY);
3296 [ # # ]: 0 : if (credential_obj == NULL) {
3297 : 0 : DRV_LOG(ERR, "Failed to allocate CREDENTIAL object data");
3298 : 0 : rte_errno = ENOMEM;
3299 : 0 : return NULL;
3300 : : }
3301 : : ptr = MLX5_ADDR_OF(create_credential_in, in, hdr);
3302 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
3303 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
3304 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
3305 : : MLX5_GENERAL_OBJ_TYPE_CREDENTIAL);
3306 : : ptr = MLX5_ADDR_OF(create_credential_in, in, credential);
3307 [ # # ]: 0 : MLX5_SET(credential, ptr, credential_role, attr->credential_role);
3308 : : credential_addr = MLX5_ADDR_OF(credential, ptr, credential);
3309 : 0 : memcpy(credential_addr, (void *)(attr->credential),
3310 : : MLX5_CRYPTO_CREDENTIAL_SIZE);
3311 : 0 : credential_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
3312 : : out, sizeof(out));
3313 [ # # ]: 0 : if (credential_obj->obj == NULL) {
3314 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create CREDENTIAL", NULL, 0);
3315 : 0 : mlx5_free(credential_obj);
3316 : 0 : return NULL;
3317 : : }
3318 [ # # ]: 0 : credential_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
3319 : 0 : return credential_obj;
3320 : : }
3321 : :
3322 : : /**
3323 : : * Create general object of type CRYPTO_LOGIN using DevX API.
3324 : : *
3325 : : * @param[in] ctx
3326 : : * Context returned from mlx5 open_device() glue function.
3327 : : * @param [in] attr
3328 : : * Pointer to CRYPTO_LOGIN attributes structure.
3329 : : *
3330 : : * @return
3331 : : * The DevX object created, NULL otherwise and rte_errno is set.
3332 : : */
3333 : : struct mlx5_devx_obj *
3334 : 0 : mlx5_devx_cmd_create_crypto_login_obj(void *ctx,
3335 : : struct mlx5_devx_crypto_login_attr *attr)
3336 : : {
3337 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_crypto_login_in)] = {0};
3338 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
3339 : : struct mlx5_devx_obj *crypto_login_obj = NULL;
3340 : : void *ptr = NULL, *credential_addr = NULL;
3341 : :
3342 : 0 : crypto_login_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*crypto_login_obj),
3343 : : 0, SOCKET_ID_ANY);
3344 [ # # ]: 0 : if (crypto_login_obj == NULL) {
3345 : 0 : DRV_LOG(ERR, "Failed to allocate CRYPTO_LOGIN object data");
3346 : 0 : rte_errno = ENOMEM;
3347 : 0 : return NULL;
3348 : : }
3349 : : ptr = MLX5_ADDR_OF(create_crypto_login_in, in, hdr);
3350 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
3351 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
3352 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
3353 : : MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN);
3354 : : ptr = MLX5_ADDR_OF(create_crypto_login_in, in, crypto_login);
3355 [ # # ]: 0 : MLX5_SET(crypto_login, ptr, credential_pointer,
3356 : : attr->credential_pointer);
3357 [ # # ]: 0 : MLX5_SET(crypto_login, ptr, session_import_kek_ptr,
3358 : : attr->session_import_kek_ptr);
3359 : : credential_addr = MLX5_ADDR_OF(crypto_login, ptr, credential);
3360 : 0 : memcpy(credential_addr, (void *)(attr->credential),
3361 : : MLX5_CRYPTO_CREDENTIAL_SIZE);
3362 : 0 : crypto_login_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
3363 : : out, sizeof(out));
3364 [ # # ]: 0 : if (crypto_login_obj->obj == NULL) {
3365 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create CRYPTO_LOGIN", NULL, 0);
3366 : 0 : mlx5_free(crypto_login_obj);
3367 : 0 : return NULL;
3368 : : }
3369 [ # # ]: 0 : crypto_login_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
3370 : 0 : return crypto_login_obj;
3371 : : }
3372 : :
3373 : : /**
3374 : : * Query LAG context.
3375 : : *
3376 : : * @param[in] ctx
3377 : : * Pointer to ibv_context, returned from mlx5dv_open_device.
3378 : : * @param[out] lag_ctx
3379 : : * Pointer to struct mlx5_devx_lag_context, to be set by the routine.
3380 : : *
3381 : : * @return
3382 : : * 0 on success, a negative value otherwise.
3383 : : */
3384 : : int
3385 : 0 : mlx5_devx_cmd_query_lag(void *ctx,
3386 : : struct mlx5_devx_lag_context *lag_ctx)
3387 : : {
3388 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_lag_in)] = {0};
3389 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_lag_out)] = {0};
3390 : : void *lctx;
3391 : : int rc;
3392 : :
3393 : 0 : MLX5_SET(query_lag_in, in, opcode, MLX5_CMD_OP_QUERY_LAG);
3394 : 0 : rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
3395 [ # # ]: 0 : if (rc)
3396 : 0 : goto error;
3397 : : lctx = MLX5_ADDR_OF(query_lag_out, out, context);
3398 [ # # ]: 0 : lag_ctx->fdb_selection_mode = MLX5_GET(lag_context, lctx,
3399 : : fdb_selection_mode);
3400 [ # # ]: 0 : lag_ctx->port_select_mode = MLX5_GET(lag_context, lctx,
3401 : : port_select_mode);
3402 [ # # ]: 0 : lag_ctx->lag_state = MLX5_GET(lag_context, lctx, lag_state);
3403 [ # # ]: 0 : lag_ctx->tx_remap_affinity_2 = MLX5_GET(lag_context, lctx,
3404 : : tx_remap_affinity_2);
3405 [ # # ]: 0 : lag_ctx->tx_remap_affinity_1 = MLX5_GET(lag_context, lctx,
3406 : : tx_remap_affinity_1);
3407 : 0 : return 0;
3408 : : error:
3409 : 0 : rc = (rc > 0) ? -rc : rc;
3410 : 0 : return rc;
3411 : : }
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