Branch data Line data Source code
1 : : /* SPDX-License-Identifier: BSD-3-Clause
2 : : * Copyright(c) 2024 Realtek Corporation. All rights reserved
3 : : */
4 : :
5 : : #include "../r8169_ethdev.h"
6 : : #include "../r8169_hw.h"
7 : : #include "../r8169_phy.h"
8 : : #include "rtl8125d_mcu.h"
9 : :
10 : : /* For RTL8125D, CFG_METHOD_56,57 */
11 : :
12 : : static void
13 : 0 : hw_init_rxcfg_8125d(struct rtl_hw *hw)
14 : : {
15 : 0 : RTL_W32(hw, RxConfig, Rx_Fetch_Number_8 | Rx_Close_Multiple |
16 : : RxCfg_pause_slot_en | (RX_DMA_BURST_256 << RxCfgDMAShift));
17 : 0 : }
18 : :
19 : : static void
20 : 0 : hw_ephy_config_8125d(struct rtl_hw *hw)
21 : : {
22 : : switch (hw->mcfg) {
23 : : case CFG_METHOD_56:
24 : : case CFG_METHOD_57:
25 : : /* Nothing to do */
26 : : break;
27 : : }
28 : 0 : }
29 : :
30 : : static void
31 : 0 : rtl_hw_phy_config_8125d_1(struct rtl_hw *hw)
32 : : {
33 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA442, BIT_11);
34 : :
35 : 0 : rtl_set_phy_mcu_patch_request(hw);
36 : :
37 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xBF96, BIT_15);
38 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBF94, 0x0007, 0x0005);
39 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBF8E, 0x3C00, 0x2800);
40 : :
41 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBCD8, 0xC000, 0x4000);
42 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xBCD8, (BIT_15 | BIT_14));
43 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBCD8, 0xC000, 0x4000);
44 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBC80, 0x001F, 0x0004);
45 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xBC82, (BIT_15 | BIT_14 | BIT_13));
46 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xBC82, (BIT_12 | BIT_11 | BIT_10));
47 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBC80, 0x001F, 0x0005);
48 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBC82, 0x00E0, 0x0040);
49 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xBC82, (BIT_4 | BIT_3 | BIT_2));
50 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xBCD8, (BIT_15 | BIT_14));
51 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBCD8, 0xC000, 0x8000);
52 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xBCD8, (BIT_15 | BIT_14));
53 : :
54 : 0 : rtl_clear_phy_mcu_patch_request(hw);
55 : :
56 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x832C);
57 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0500);
58 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB106, 0x0700, 0x0100);
59 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB206, 0x0700, 0x0200);
60 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB306, 0x0700, 0x0300);
61 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x80CB);
62 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0300);
63 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xBCF4, 0x0000);
64 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xBCF6, 0x0000);
65 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xBC12, 0x0000);
66 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x844d);
67 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0200);
68 [ # # ]: 0 : if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(hw)) {
69 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8feb);
70 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
71 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8fe9);
72 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0600);
73 : : }
74 : :
75 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xAD40, (BIT_5 | BIT_4));
76 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAD66, 0x000F, 0x0007);
77 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAD68, 0xF000, 0x8000);
78 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAD68, 0x0F00, 0x0500);
79 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAD68, 0x000F, 0x0002);
80 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAD6A, 0xF000, 0x7000);
81 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xAC50, 0x01E8);
82 : :
83 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x81FA);
84 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x5400);
85 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA864, 0x00F0, 0x00C0);
86 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA42C, 0x00FF, 0x0002);
87 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80E1);
88 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x0F00);
89 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80DE);
90 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xF000, 0x0700);
91 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA846, BIT_7);
92 : :
93 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80BA);
94 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8A04);
95 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80BD);
96 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xCA00);
97 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80B7);
98 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xB300);
99 : :
100 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80CE);
101 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8A04);
102 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80D1);
103 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xCA00);
104 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80CB);
105 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xBB00);
106 : :
107 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80A6);
108 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x4909);
109 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80A8);
110 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x05B8);
111 : :
112 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8200);
113 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x5800);
114 : :
115 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8FF1);
116 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x7078);
117 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8FF3);
118 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x5D78);
119 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8FF5);
120 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x7862);
121 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8FF7);
122 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x1400);
123 : :
124 [ # # ]: 0 : if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(hw)) {
125 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x814C);
126 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8455);
127 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x814E);
128 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x84A6);
129 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8163);
130 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x0600);
131 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x816A);
132 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x0500);
133 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8171);
134 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x1f00);
135 : : }
136 : :
137 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBC3A, 0x000F, 0x0006);
138 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8064);
139 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA438, (BIT_10 | BIT_9 | BIT_8));
140 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8067);
141 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA438, (BIT_10 | BIT_9 | BIT_8));
142 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x806A);
143 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA438, (BIT_10 | BIT_9 | BIT_8));
144 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x806D);
145 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA438, (BIT_10 | BIT_9 | BIT_8));
146 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8070);
147 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA438, (BIT_10 | BIT_9 | BIT_8));
148 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8073);
149 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA438, (BIT_10 | BIT_9 | BIT_8));
150 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8076);
151 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA438, (BIT_10 | BIT_9 | BIT_8));
152 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8079);
153 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA438, (BIT_10 | BIT_9 | BIT_8));
154 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x807C);
155 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA438, (BIT_10 | BIT_9 | BIT_8));
156 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x807F);
157 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA438, (BIT_10 | BIT_9 | BIT_8));
158 : :
159 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBFA0, 0xFF70, 0x5500);
160 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xBFA2, 0x9D00);
161 : :
162 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8165);
163 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0x0700, 0x0200);
164 : :
165 [ # # ]: 0 : if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(hw)) {
166 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8019);
167 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA438, BIT_8);
168 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8FE3);
169 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0005);
170 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
171 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00ED);
172 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0502);
173 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0B00);
174 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xD401);
175 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x2900);
176 : : }
177 : :
178 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8018);
179 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x1700);
180 : :
181 [ # # ]: 0 : if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(hw)) {
182 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x815B);
183 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x1700);
184 : : }
185 : :
186 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA430, BIT_12 | BIT_0);
187 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA442, BIT_7);
188 : 0 : }
189 : :
190 : : static void
191 : : rtl_hw_phy_config_8125d_2(struct rtl_hw *hw)
192 : : {
193 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA442, BIT_11);
194 : 0 : }
195 : :
196 : : static void
197 : 0 : hw_phy_config_8125d(struct rtl_hw *hw)
198 : : {
199 [ # # # ]: 0 : switch (hw->mcfg) {
200 : 0 : case CFG_METHOD_56:
201 : 0 : rtl_hw_phy_config_8125d_1(hw);
202 : 0 : break;
203 : : case CFG_METHOD_57:
204 : : rtl_hw_phy_config_8125d_2(hw);
205 : : break;
206 : : }
207 : 0 : }
208 : :
209 : : static void
210 : 0 : hw_mac_mcu_config_8125d(struct rtl_hw *hw)
211 : : {
212 [ # # ]: 0 : if (hw->NotWrMcuPatchCode)
213 : : return;
214 : :
215 [ # # # ]: 0 : switch (hw->mcfg) {
216 : 0 : case CFG_METHOD_56:
217 : 0 : rtl_set_mac_mcu_8125d_1(hw);
218 : 0 : break;
219 : 0 : case CFG_METHOD_57:
220 : 0 : rtl_set_mac_mcu_8125d_2(hw);
221 : 0 : break;
222 : : }
223 : : }
224 : :
225 : : static void
226 : 0 : hw_phy_mcu_config_8125d(struct rtl_hw *hw)
227 : : {
228 [ # # ]: 0 : switch (hw->mcfg) {
229 : 0 : case CFG_METHOD_56:
230 : 0 : rtl_set_phy_mcu_8125d_1(hw);
231 : 0 : break;
232 : : case CFG_METHOD_57:
233 : : /* Nothing to do */
234 : : break;
235 : : }
236 : 0 : }
237 : :
238 : : const struct rtl_hw_ops rtl8125d_ops = {
239 : : .hw_init_rxcfg = hw_init_rxcfg_8125d,
240 : : .hw_ephy_config = hw_ephy_config_8125d,
241 : : .hw_phy_config = hw_phy_config_8125d,
242 : : .hw_mac_mcu_config = hw_mac_mcu_config_8125d,
243 : : .hw_phy_mcu_config = hw_phy_mcu_config_8125d,
244 : : };
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