Branch data Line data Source code
1 : : /* SPDX-License-Identifier: BSD-3-Clause
2 : : * Copyright(c) 2024 Realtek Corporation. All rights reserved
3 : : */
4 : :
5 : : #include "../r8169_ethdev.h"
6 : : #include "../r8169_hw.h"
7 : : #include "../r8169_phy.h"
8 : : #include "rtl8125b.h"
9 : :
10 : : /* For RTL8125B, CFG_METHOD_50,51 */
11 : :
12 : : static void
13 : 0 : hw_init_rxcfg_8125b(struct rtl_hw *hw)
14 : : {
15 : 0 : RTL_W32(hw, RxConfig, Rx_Fetch_Number_8 | RxCfg_pause_slot_en |
16 : : (RX_DMA_BURST_256 << RxCfgDMAShift));
17 : 0 : }
18 : :
19 : : static void
20 : 0 : hw_ephy_config_8125b(struct rtl_hw *hw)
21 : : {
22 [ # # # ]: 0 : switch (hw->mcfg) {
23 : 0 : case CFG_METHOD_50:
24 : 0 : rtl_ephy_write(hw, 0x06, 0x001F);
25 : 0 : rtl_ephy_write(hw, 0x0A, 0xB66B);
26 : 0 : rtl_ephy_write(hw, 0x01, 0xA852);
27 : 0 : rtl_ephy_write(hw, 0x24, 0x0008);
28 : 0 : rtl_ephy_write(hw, 0x2F, 0x6052);
29 : 0 : rtl_ephy_write(hw, 0x0D, 0xF716);
30 : 0 : rtl_ephy_write(hw, 0x20, 0xD477);
31 : 0 : rtl_ephy_write(hw, 0x21, 0x4477);
32 : 0 : rtl_ephy_write(hw, 0x22, 0x0013);
33 : 0 : rtl_ephy_write(hw, 0x23, 0xBB66);
34 : 0 : rtl_ephy_write(hw, 0x0B, 0xA909);
35 : 0 : rtl_ephy_write(hw, 0x29, 0xFF04);
36 : 0 : rtl_ephy_write(hw, 0x1B, 0x1EA0);
37 : :
38 : 0 : rtl_ephy_write(hw, 0x46, 0x001F);
39 : 0 : rtl_ephy_write(hw, 0x4A, 0xB66B);
40 : 0 : rtl_ephy_write(hw, 0x41, 0xA84A);
41 : 0 : rtl_ephy_write(hw, 0x64, 0x000C);
42 : 0 : rtl_ephy_write(hw, 0x6F, 0x604A);
43 : 0 : rtl_ephy_write(hw, 0x4D, 0xF716);
44 : 0 : rtl_ephy_write(hw, 0x60, 0xD477);
45 : 0 : rtl_ephy_write(hw, 0x61, 0x4477);
46 : 0 : rtl_ephy_write(hw, 0x62, 0x0013);
47 : 0 : rtl_ephy_write(hw, 0x63, 0xBB66);
48 : 0 : rtl_ephy_write(hw, 0x4B, 0xA909);
49 : 0 : rtl_ephy_write(hw, 0x69, 0xFF04);
50 : 0 : rtl_ephy_write(hw, 0x5B, 0x1EA0);
51 : 0 : break;
52 : 0 : case CFG_METHOD_51:
53 : 0 : rtl_ephy_write(hw, 0x0B, 0xA908);
54 : 0 : rtl_ephy_write(hw, 0x1E, 0x20EB);
55 : 0 : rtl_ephy_write(hw, 0x22, 0x0023);
56 : 0 : rtl_ephy_write(hw, 0x02, 0x60C2);
57 : 0 : rtl_ephy_write(hw, 0x29, 0xFF00);
58 : :
59 : 0 : rtl_ephy_write(hw, 0x4B, 0xA908);
60 : 0 : rtl_ephy_write(hw, 0x5E, 0x28EB);
61 : 0 : rtl_ephy_write(hw, 0x62, 0x0023);
62 : 0 : rtl_ephy_write(hw, 0x42, 0x60C2);
63 : 0 : rtl_ephy_write(hw, 0x69, 0xFF00);
64 : 0 : break;
65 : : }
66 : 0 : }
67 : :
68 : : static void
69 : 0 : rtl_hw_phy_config_8125b_1(struct rtl_hw *hw)
70 : : {
71 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA442, BIT_11);
72 : :
73 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xBC08, (BIT_3 | BIT_2));
74 : :
75 [ # # ]: 0 : if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(hw)) {
76 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8FFF);
77 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x0400);
78 : : }
79 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8560);
80 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x19CC);
81 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8562);
82 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x19CC);
83 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8564);
84 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x19CC);
85 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8566);
86 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x147D);
87 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8568);
88 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x147D);
89 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x856A);
90 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x147D);
91 [ # # ]: 0 : if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(hw)) {
92 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FFE);
93 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0907);
94 : : }
95 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xACDA, 0xFF00, 0xFF00);
96 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xACDE, 0xF000, 0xF000);
97 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x80D6);
98 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x2801);
99 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x80F2);
100 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x2801);
101 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x80F4);
102 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x6077);
103 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB506, 0x01E7);
104 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xAC8C, 0x0FFC);
105 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xAC46, 0xB7B4);
106 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xAC50, 0x0FBC);
107 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xAC3C, 0x9240);
108 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xAC4E, 0x0DB4);
109 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xACC6, 0x0707);
110 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xACC8, 0xA0D3);
111 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xAD08, 0x0007);
112 : :
113 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8013);
114 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0700);
115 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FB9);
116 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x2801);
117 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FBA);
118 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0100);
119 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FBC);
120 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x1900);
121 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FBE);
122 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0xE100);
123 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FC0);
124 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0800);
125 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FC2);
126 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0xE500);
127 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FC4);
128 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0F00);
129 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FC6);
130 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0xF100);
131 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FC8);
132 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0400);
133 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FCa);
134 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0xF300);
135 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FCc);
136 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0xFD00);
137 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FCe);
138 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0xFF00);
139 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FD0);
140 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0xFB00);
141 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FD2);
142 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0100);
143 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FD4);
144 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0xF400);
145 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FD6);
146 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0xFF00);
147 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FD8);
148 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0xF600);
149 : :
150 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x813D);
151 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x390E);
152 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x814F);
153 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x790E);
154 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x80B0);
155 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0F31);
156 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xBF4C, BIT_1);
157 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xBCCA, (BIT_9 | BIT_8));
158 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8141);
159 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x320E);
160 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8153);
161 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x720E);
162 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA432, BIT_6);
163 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8529);
164 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x050E);
165 : :
166 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x816C);
167 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xC4A0);
168 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8170);
169 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xC4A0);
170 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8174);
171 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x04A0);
172 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8178);
173 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x04A0);
174 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x817C);
175 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0719);
176 [ # # ]: 0 : if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(hw)) {
177 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8FF4);
178 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0400);
179 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8FF1);
180 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0404);
181 : : }
182 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xBF4A, 0x001B);
183 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8033);
184 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x7C13);
185 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8037);
186 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x7C13);
187 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x803B);
188 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0xFC32);
189 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x803F);
190 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x7C13);
191 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8043);
192 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x7C13);
193 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8047);
194 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x7C13);
195 : :
196 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8145);
197 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x370E);
198 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8157);
199 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x770E);
200 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8169);
201 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0D0A);
202 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x817B);
203 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x1D0A);
204 : :
205 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8217);
206 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x5000);
207 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x821A);
208 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x5000);
209 : :
210 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80DA);
211 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0403);
212 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80DC);
213 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x1000);
214 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80B3);
215 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0384);
216 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80B7);
217 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x2007);
218 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80BA);
219 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x6C00);
220 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80B5);
221 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xF009);
222 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80BD);
223 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x9F00);
224 : :
225 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80C7);
226 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xf083);
227 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80DD);
228 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x03f0);
229 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80DF);
230 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x1000);
231 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80CB);
232 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x2007);
233 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80CE);
234 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x6C00);
235 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80C9);
236 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x8009);
237 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80D1);
238 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x8000);
239 : :
240 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80A3);
241 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x200A);
242 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80A5);
243 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xF0AD);
244 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x809F);
245 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x6073);
246 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80A1);
247 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x000B);
248 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80A9);
249 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xC000);
250 : :
251 : 0 : rtl_set_phy_mcu_patch_request(hw);
252 : :
253 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xB896, BIT_0);
254 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xB892, 0xFF00);
255 : :
256 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC23E);
257 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x0000);
258 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC240);
259 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x0103);
260 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC242);
261 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x0507);
262 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC244);
263 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x090B);
264 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC246);
265 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x0C0E);
266 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC248);
267 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x1012);
268 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC24A);
269 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x1416);
270 : :
271 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xB896, BIT_0);
272 : :
273 : 0 : rtl_clear_phy_mcu_patch_request(hw);
274 : :
275 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA86A, BIT_0);
276 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA6F0, BIT_0);
277 : :
278 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xBFA0, 0xD70D);
279 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xBFA2, 0x4100);
280 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xBFA4, 0xE868);
281 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xBFA6, 0xDC59);
282 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB54C, 0x3C18);
283 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xBFA4, BIT_5);
284 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x817D);
285 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA438, BIT_12);
286 : 0 : }
287 : :
288 : : void
289 : 0 : rtl_hw_phy_config_8125b_2(struct rtl_hw *hw)
290 : : {
291 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA442, BIT_11);
292 : :
293 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAC46, 0x00F0, 0x0090);
294 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAD30, 0x0003, 0x0001);
295 : :
296 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x80F5);
297 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x760E);
298 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8107);
299 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x360E);
300 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8551);
301 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E,
302 : : (BIT_15 | BIT_14 | BIT_13 | BIT_12 |
303 : : BIT_11 | BIT_10 | BIT_9 | BIT_8),
304 : : BIT_11);
305 : :
306 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xbf00, 0xE000, 0xA000);
307 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xbf46, 0x0F00, 0x0300);
308 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xa436, 0x8044);
309 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xa438, 0x2417);
310 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xa436, 0x804A);
311 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xa438, 0x2417);
312 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xa436, 0x8050);
313 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xa438, 0x2417);
314 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xa436, 0x8056);
315 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xa438, 0x2417);
316 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xa436, 0x805C);
317 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xa438, 0x2417);
318 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xa436, 0x8062);
319 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xa438, 0x2417);
320 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xa436, 0x8068);
321 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xa438, 0x2417);
322 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xa436, 0x806E);
323 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xa438, 0x2417);
324 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xa436, 0x8074);
325 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xa438, 0x2417);
326 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xa436, 0x807A);
327 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xa438, 0x2417);
328 : :
329 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA4CA, BIT_6);
330 : :
331 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBF84, (BIT_15 | BIT_14 | BIT_13),
332 : : (BIT_15 | BIT_13));
333 : :
334 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8170);
335 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438,
336 : : (BIT_13 | BIT_10 | BIT_9 | BIT_8),
337 : : (BIT_15 | BIT_14 | BIT_12 | BIT_11));
338 : :
339 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA424, BIT_3);
340 : 0 : }
341 : :
342 : : static void
343 : 0 : hw_phy_config_8125b(struct rtl_hw *hw)
344 : : {
345 [ # # # ]: 0 : switch (hw->mcfg) {
346 : 0 : case CFG_METHOD_50:
347 : 0 : rtl_hw_phy_config_8125b_1(hw);
348 : 0 : break;
349 : 0 : case CFG_METHOD_51:
350 : 0 : rtl_hw_phy_config_8125b_2(hw);
351 : 0 : break;
352 : : }
353 : 0 : }
354 : :
355 : : static void
356 : 0 : hw_mac_mcu_config_8125b(struct rtl_hw *hw)
357 : : {
358 [ # # ]: 0 : if (hw->NotWrMcuPatchCode)
359 : : return;
360 : :
361 [ # # # ]: 0 : switch (hw->mcfg) {
362 : 0 : case CFG_METHOD_50:
363 : 0 : rtl_set_mac_mcu_8125b_1(hw);
364 : 0 : break;
365 : 0 : case CFG_METHOD_51:
366 : 0 : rtl_set_mac_mcu_8125b_2(hw);
367 : 0 : break;
368 : : }
369 : : }
370 : :
371 : : static void
372 : 0 : hw_phy_mcu_config_8125b(struct rtl_hw *hw)
373 : : {
374 [ # # # ]: 0 : switch (hw->mcfg) {
375 : 0 : case CFG_METHOD_50:
376 : 0 : rtl_set_phy_mcu_8125b_1(hw);
377 : 0 : break;
378 : 0 : case CFG_METHOD_51:
379 : 0 : rtl_set_phy_mcu_8125b_2(hw);
380 : 0 : break;
381 : : }
382 : 0 : }
383 : :
384 : : const struct rtl_hw_ops rtl8125b_ops = {
385 : : .hw_init_rxcfg = hw_init_rxcfg_8125b,
386 : : .hw_ephy_config = hw_ephy_config_8125b,
387 : : .hw_phy_config = hw_phy_config_8125b,
388 : : .hw_mac_mcu_config = hw_mac_mcu_config_8125b,
389 : : .hw_phy_mcu_config = hw_phy_mcu_config_8125b,
390 : : };
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