Branch data Line data Source code
1 : : /* SPDX-License-Identifier: BSD-3-Clause
2 : : * Copyright(c) 2024 Realtek Corporation. All rights reserved
3 : : */
4 : :
5 : : #include "../r8169_ethdev.h"
6 : : #include "../r8169_hw.h"
7 : : #include "../r8169_phy.h"
8 : : #include "rtl8125a.h"
9 : :
10 : : /* For RTL8125A, CFG_METHOD_48,49 */
11 : :
12 : : static void
13 : 0 : hw_init_rxcfg_8125a(struct rtl_hw *hw)
14 : : {
15 : 0 : RTL_W32(hw, RxConfig, Rx_Fetch_Number_8 | (RX_DMA_BURST_256 << RxCfgDMAShift));
16 : 0 : }
17 : :
18 : : static void
19 : 0 : hw_ephy_config_8125a(struct rtl_hw *hw)
20 : : {
21 [ # # # ]: 0 : switch (hw->mcfg) {
22 : 0 : case CFG_METHOD_48:
23 : 0 : rtl_ephy_write(hw, 0x01, 0xA812);
24 : 0 : rtl_ephy_write(hw, 0x09, 0x520C);
25 : 0 : rtl_ephy_write(hw, 0x04, 0xD000);
26 : 0 : rtl_ephy_write(hw, 0x0D, 0xF702);
27 : 0 : rtl_ephy_write(hw, 0x0A, 0x8653);
28 : 0 : rtl_ephy_write(hw, 0x06, 0x001E);
29 : 0 : rtl_ephy_write(hw, 0x08, 0x3595);
30 : 0 : rtl_ephy_write(hw, 0x20, 0x9455);
31 : 0 : rtl_ephy_write(hw, 0x21, 0x99FF);
32 : 0 : rtl_ephy_write(hw, 0x02, 0x6046);
33 : 0 : rtl_ephy_write(hw, 0x29, 0xFE00);
34 : 0 : rtl_ephy_write(hw, 0x23, 0xAB62);
35 : :
36 : 0 : rtl_ephy_write(hw, 0x41, 0xA80C);
37 : 0 : rtl_ephy_write(hw, 0x49, 0x520C);
38 : 0 : rtl_ephy_write(hw, 0x44, 0xD000);
39 : 0 : rtl_ephy_write(hw, 0x4D, 0xF702);
40 : 0 : rtl_ephy_write(hw, 0x4A, 0x8653);
41 : 0 : rtl_ephy_write(hw, 0x46, 0x001E);
42 : 0 : rtl_ephy_write(hw, 0x48, 0x3595);
43 : 0 : rtl_ephy_write(hw, 0x60, 0x9455);
44 : 0 : rtl_ephy_write(hw, 0x61, 0x99FF);
45 : 0 : rtl_ephy_write(hw, 0x42, 0x6046);
46 : 0 : rtl_ephy_write(hw, 0x69, 0xFE00);
47 : 0 : rtl_ephy_write(hw, 0x63, 0xAB62);
48 : 0 : break;
49 : 0 : case CFG_METHOD_49:
50 : 0 : rtl_ephy_write(hw, 0x04, 0xD000);
51 : 0 : rtl_ephy_write(hw, 0x0A, 0x8653);
52 : 0 : rtl_ephy_write(hw, 0x23, 0xAB66);
53 : 0 : rtl_ephy_write(hw, 0x20, 0x9455);
54 : 0 : rtl_ephy_write(hw, 0x21, 0x99FF);
55 : 0 : rtl_ephy_write(hw, 0x29, 0xFE04);
56 : :
57 : 0 : rtl_ephy_write(hw, 0x44, 0xD000);
58 : 0 : rtl_ephy_write(hw, 0x4A, 0x8653);
59 : 0 : rtl_ephy_write(hw, 0x63, 0xAB66);
60 : 0 : rtl_ephy_write(hw, 0x60, 0x9455);
61 : 0 : rtl_ephy_write(hw, 0x61, 0x99FF);
62 : 0 : rtl_ephy_write(hw, 0x69, 0xFE04);
63 : :
64 : 0 : rtl_clear_and_set_pcie_phy_bit(hw, 0x2A, (BIT_14 | BIT_13 | BIT_12),
65 : : (BIT_13 | BIT_12));
66 : 0 : rtl_clear_pcie_phy_bit(hw, 0x19, BIT_6);
67 : 0 : rtl_set_pcie_phy_bit(hw, 0x1B, (BIT_11 | BIT_10 | BIT_9));
68 : 0 : rtl_clear_pcie_phy_bit(hw, 0x1B, (BIT_14 | BIT_13 | BIT_12));
69 : 0 : rtl_ephy_write(hw, 0x02, 0x6042);
70 : 0 : rtl_ephy_write(hw, 0x06, 0x0014);
71 : :
72 : 0 : rtl_clear_and_set_pcie_phy_bit(hw, 0x6A, (BIT_14 | BIT_13 | BIT_12),
73 : : (BIT_13 | BIT_12));
74 : 0 : rtl_clear_pcie_phy_bit(hw, 0x59, BIT_6);
75 : 0 : rtl_set_pcie_phy_bit(hw, 0x5B, (BIT_11 | BIT_10 | BIT_9));
76 : 0 : rtl_clear_pcie_phy_bit(hw, 0x5B, (BIT_14 | BIT_13 | BIT_12));
77 : 0 : rtl_ephy_write(hw, 0x42, 0x6042);
78 : 0 : rtl_ephy_write(hw, 0x46, 0x0014);
79 : 0 : break;
80 : : }
81 : 0 : }
82 : :
83 : : static void
84 : 0 : rtl_hw_phy_config_8125a_1(struct rtl_hw *hw)
85 : : {
86 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAD40, 0x03FF, 0x84);
87 : :
88 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xAD4E, BIT_4);
89 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAD16, 0x03FF, 0x0006);
90 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAD32, 0x003F, 0x0006);
91 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xAC08, BIT_12);
92 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xAC08, BIT_8);
93 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAC8A,
94 : : (BIT_15 | BIT_14 | BIT_13 | BIT_12),
95 : : (BIT_14 | BIT_13 | BIT_12));
96 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xAD18, BIT_10);
97 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xAD1A, 0x3FF);
98 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xAD1C, 0x3FF);
99 : :
100 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80EA);
101 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xC400);
102 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80EB);
103 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0x0700, 0x0300);
104 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80F8);
105 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x1C00);
106 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80F1);
107 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x3000);
108 : :
109 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80FE);
110 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xA500);
111 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8102);
112 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x5000);
113 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8105);
114 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x3300);
115 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8100);
116 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x7000);
117 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8104);
118 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xF000);
119 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8106);
120 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x6500);
121 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80DC);
122 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xED00);
123 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80DF);
124 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA438, BIT_8);
125 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80E1);
126 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA438, BIT_8);
127 : :
128 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBF06, 0x003F, 0x38);
129 : :
130 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x819F);
131 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xD0B6);
132 : :
133 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xBC34, 0x5555);
134 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBF0A, (BIT_11 | BIT_10 | BIT_9),
135 : : (BIT_11 | BIT_9));
136 : :
137 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA5C0, BIT_10);
138 : :
139 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA442, BIT_11);
140 : 0 : }
141 : :
142 : : void
143 : 0 : rtl_hw_phy_config_8125a_2(struct rtl_hw *hw)
144 : : {
145 : : u16 adccal_offset_p0;
146 : : u16 adccal_offset_p1;
147 : : u16 adccal_offset_p2;
148 : : u16 adccal_offset_p3;
149 : : u16 rg_lpf_cap_xg_p0;
150 : : u16 rg_lpf_cap_xg_p1;
151 : : u16 rg_lpf_cap_xg_p2;
152 : : u16 rg_lpf_cap_xg_p3;
153 : : u16 rg_lpf_cap_p0;
154 : : u16 rg_lpf_cap_p1;
155 : : u16 rg_lpf_cap_p2;
156 : : u16 rg_lpf_cap_p3;
157 : :
158 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xAD4E, BIT_4);
159 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAD16, 0x03FF, 0x03FF);
160 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAD32, 0x003F, 0x0006);
161 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xAC08, BIT_12);
162 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xAC08, BIT_8);
163 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xACC0, (BIT_1 | BIT_0), BIT_1);
164 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAD40, (BIT_7 | BIT_6 | BIT_5),
165 : : BIT_6);
166 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAD40, (BIT_2 | BIT_1 | BIT_0),
167 : : BIT_2);
168 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xAC14, BIT_7);
169 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xAC80, BIT_9 | BIT_8);
170 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAC5E, (BIT_2 | BIT_1 | BIT_0),
171 : : BIT_1);
172 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xAD4C, 0x00A8);
173 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xAC5C, 0x01FF);
174 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAC8A, (BIT_7 | BIT_6 | BIT_5 | BIT_4),
175 : : (BIT_5 | BIT_4));
176 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8157);
177 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0500);
178 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8159);
179 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0700);
180 : :
181 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x80A2);
182 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0153);
183 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x809C);
184 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0153);
185 : :
186 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x81B3);
187 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0043);
188 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00A7);
189 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00D6);
190 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00EC);
191 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00F6);
192 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00FB);
193 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00FD);
194 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00FF);
195 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00BB);
196 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0058);
197 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0029);
198 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0013);
199 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0009);
200 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0004);
201 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0002);
202 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
203 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
204 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
205 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
206 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
207 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
208 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
209 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
210 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
211 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
212 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
213 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
214 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
215 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
216 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
217 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
218 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
219 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
220 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
221 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
222 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
223 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
224 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
225 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
226 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
227 : :
228 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8257);
229 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x020F);
230 : :
231 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80EA);
232 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x7843);
233 : :
234 : 0 : rtl_set_phy_mcu_patch_request(hw);
235 : :
236 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xB896, BIT_0);
237 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xB892, 0xFF00);
238 : :
239 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC091);
240 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x6E12);
241 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC092);
242 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x1214);
243 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC094);
244 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x1516);
245 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC096);
246 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x171B);
247 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC098);
248 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x1B1C);
249 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC09A);
250 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x1F1F);
251 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC09C);
252 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x2021);
253 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC09E);
254 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x2224);
255 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC0A0);
256 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x2424);
257 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC0A2);
258 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x2424);
259 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC0A4);
260 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x2424);
261 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC018);
262 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x0AF2);
263 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC01A);
264 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x0D4A);
265 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC01C);
266 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x0F26);
267 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC01E);
268 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x118D);
269 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC020);
270 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x14F3);
271 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC022);
272 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x175A);
273 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC024);
274 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x19C0);
275 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC026);
276 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x1C26);
277 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC089);
278 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x6050);
279 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC08A);
280 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x5F6E);
281 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC08C);
282 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x6E6E);
283 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC08E);
284 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x6E6E);
285 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB88E, 0xC090);
286 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB890, 0x6E12);
287 : :
288 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xB896, BIT_0);
289 : :
290 : 0 : rtl_clear_phy_mcu_patch_request(hw);
291 : :
292 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xD068, BIT_13);
293 : :
294 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x81A2);
295 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA438, BIT_8);
296 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB54C, 0xFF00, 0xDB00);
297 : :
298 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA454, BIT_0);
299 : :
300 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA5D4, BIT_5);
301 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xAD4E, BIT_4);
302 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA86A, BIT_0);
303 : :
304 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA442, BIT_11);
305 : :
306 [ # # ]: 0 : if (hw->RequirePhyMdiSwapPatch) {
307 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xD068, 0x0007, 0x0001);
308 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xD068, 0x0018, 0x0000);
309 : 0 : adccal_offset_p0 = rtl_mdio_direct_read_phy_ocp(hw, 0xD06A);
310 : 0 : adccal_offset_p0 &= 0x07FF;
311 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xD068, 0x0018, 0x0008);
312 : 0 : adccal_offset_p1 = rtl_mdio_direct_read_phy_ocp(hw, 0xD06A);
313 : 0 : adccal_offset_p1 &= 0x07FF;
314 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xD068, 0x0018, 0x0010);
315 : 0 : adccal_offset_p2 = rtl_mdio_direct_read_phy_ocp(hw, 0xD06A);
316 : 0 : adccal_offset_p2 &= 0x07FF;
317 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xD068, 0x0018, 0x0018);
318 : 0 : adccal_offset_p3 = rtl_mdio_direct_read_phy_ocp(hw, 0xD06A);
319 : 0 : adccal_offset_p3 &= 0x07FF;
320 : :
321 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xD068, 0x0018, 0x0000);
322 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xD06A, 0x07FF, adccal_offset_p3);
323 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xD068, 0x0018, 0x0008);
324 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xD06A, 0x07FF, adccal_offset_p2);
325 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xD068, 0x0018, 0x0010);
326 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xD06A, 0x07FF, adccal_offset_p1);
327 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xD068, 0x0018, 0x0018);
328 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xD06A, 0x07FF, adccal_offset_p0);
329 : :
330 : 0 : rg_lpf_cap_xg_p0 = rtl_mdio_direct_read_phy_ocp(hw, 0xBD5A);
331 : : rg_lpf_cap_xg_p0 &= 0x001F;
332 : 0 : rg_lpf_cap_xg_p1 = rtl_mdio_direct_read_phy_ocp(hw, 0xBD5A);
333 : : rg_lpf_cap_xg_p1 &= 0x1F00;
334 : 0 : rg_lpf_cap_xg_p2 = rtl_mdio_direct_read_phy_ocp(hw, 0xBD5C);
335 : : rg_lpf_cap_xg_p2 &= 0x001F;
336 : 0 : rg_lpf_cap_xg_p3 = rtl_mdio_direct_read_phy_ocp(hw, 0xBD5C);
337 : : rg_lpf_cap_xg_p3 &= 0x1F00;
338 : 0 : rg_lpf_cap_p0 = rtl_mdio_direct_read_phy_ocp(hw, 0xBC18);
339 : : rg_lpf_cap_p0 &= 0x001F;
340 : 0 : rg_lpf_cap_p1 = rtl_mdio_direct_read_phy_ocp(hw, 0xBC18);
341 : : rg_lpf_cap_p1 &= 0x1F00;
342 : 0 : rg_lpf_cap_p2 = rtl_mdio_direct_read_phy_ocp(hw, 0xBC1A);
343 : : rg_lpf_cap_p2 &= 0x001F;
344 : 0 : rg_lpf_cap_p3 = rtl_mdio_direct_read_phy_ocp(hw, 0xBC1A);
345 : : rg_lpf_cap_p3 &= 0x1F00;
346 : :
347 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBD5A, 0x001F,
348 : : rg_lpf_cap_xg_p3 >> 8);
349 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBD5A, 0x1F00,
350 : 0 : rg_lpf_cap_xg_p2 << 8);
351 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBD5C, 0x001F,
352 : : rg_lpf_cap_xg_p1 >> 8);
353 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBD5C, 0x1F00,
354 : 0 : rg_lpf_cap_xg_p0 << 8);
355 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBC18, 0x001F, rg_lpf_cap_p3 >> 8);
356 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBC18, 0x1F00, rg_lpf_cap_p2 << 8);
357 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBC1A, 0x001F, rg_lpf_cap_p1 >> 8);
358 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBC1A, 0x1F00, rg_lpf_cap_p0 << 8);
359 : : }
360 : :
361 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA424, BIT_3);
362 : 0 : }
363 : :
364 : : static void
365 : 0 : hw_phy_config_8125a(struct rtl_hw *hw)
366 : : {
367 [ # # # ]: 0 : switch (hw->mcfg) {
368 : 0 : case CFG_METHOD_48:
369 : 0 : rtl_hw_phy_config_8125a_1(hw);
370 : 0 : break;
371 : 0 : case CFG_METHOD_49:
372 : 0 : rtl_hw_phy_config_8125a_2(hw);
373 : 0 : break;
374 : : }
375 : 0 : }
376 : :
377 : : static void
378 : 0 : hw_mac_mcu_config_8125a(struct rtl_hw *hw)
379 : : {
380 [ # # ]: 0 : if (hw->NotWrMcuPatchCode)
381 : : return;
382 : :
383 [ # # # ]: 0 : switch (hw->mcfg) {
384 : 0 : case CFG_METHOD_48:
385 : 0 : rtl_set_mac_mcu_8125a_1(hw);
386 : 0 : break;
387 : 0 : case CFG_METHOD_49:
388 : 0 : rtl_set_mac_mcu_8125a_2(hw);
389 : 0 : break;
390 : : }
391 : : }
392 : :
393 : : static void
394 : 0 : hw_phy_mcu_config_8125a(struct rtl_hw *hw)
395 : : {
396 [ # # # ]: 0 : switch (hw->mcfg) {
397 : 0 : case CFG_METHOD_48:
398 : 0 : rtl_set_phy_mcu_8125a_1(hw);
399 : 0 : break;
400 : 0 : case CFG_METHOD_49:
401 : 0 : rtl_set_phy_mcu_8125a_2(hw);
402 : 0 : break;
403 : : }
404 : 0 : }
405 : :
406 : : const struct rtl_hw_ops rtl8125a_ops = {
407 : : .hw_init_rxcfg = hw_init_rxcfg_8125a,
408 : : .hw_ephy_config = hw_ephy_config_8125a,
409 : : .hw_phy_config = hw_phy_config_8125a,
410 : : .hw_mac_mcu_config = hw_mac_mcu_config_8125a,
411 : : .hw_phy_mcu_config = hw_phy_mcu_config_8125a,
412 : : };
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