Branch data Line data Source code
1 : : /* SPDX-License-Identifier: BSD-3-Clause
2 : : * Copyright (c) 2022 NVIDIA Corporation & Affiliates
3 : : */
4 : :
5 : : #include <rte_flow.h>
6 : : #include <rte_flow_driver.h>
7 : : #include <rte_stdatomic.h>
8 : :
9 : : #include <mlx5_malloc.h>
10 : :
11 : : #include "mlx5.h"
12 : : #include "mlx5_common.h"
13 : : #include "mlx5_defs.h"
14 : : #include "mlx5_flow.h"
15 : : #include "mlx5_flow_os.h"
16 : : #include "mlx5_rx.h"
17 : :
18 : : #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
19 : : #include "mlx5_hws_cnt.h"
20 : :
21 : : /** Fast path async flow API functions. */
22 : : static struct rte_flow_fp_ops mlx5_flow_hw_fp_ops;
23 : :
24 : : /*
25 : : * The default ipool threshold value indicates which per_core_cache
26 : : * value to set.
27 : : */
28 : : #define MLX5_HW_IPOOL_SIZE_THRESHOLD (1 << 19)
29 : : /* The default min local cache size. */
30 : : #define MLX5_HW_IPOOL_CACHE_MIN (1 << 9)
31 : :
32 : : /* Default push burst threshold. */
33 : : #define BURST_THR 32u
34 : :
35 : : /* Default queue to flush the flows. */
36 : : #define MLX5_DEFAULT_FLUSH_QUEUE 0
37 : :
38 : : /* Maximum number of rules in control flow tables. */
39 : : #define MLX5_HW_CTRL_FLOW_NB_RULES (4096)
40 : :
41 : : /* Lowest flow group usable by an application if group translation is done. */
42 : : #define MLX5_HW_LOWEST_USABLE_GROUP (1)
43 : :
44 : : /* Maximum group index usable by user applications for transfer flows. */
45 : : #define MLX5_HW_MAX_TRANSFER_GROUP (UINT32_MAX - 1)
46 : :
47 : : /* Maximum group index usable by user applications for egress flows. */
48 : : #define MLX5_HW_MAX_EGRESS_GROUP (UINT32_MAX - 1)
49 : :
50 : : /* Lowest priority for HW root table. */
51 : : #define MLX5_HW_LOWEST_PRIO_ROOT 15
52 : :
53 : : /* Lowest priority for HW non-root table. */
54 : : #define MLX5_HW_LOWEST_PRIO_NON_ROOT (UINT32_MAX)
55 : :
56 : : /* Priorities for Rx control flow rules. */
57 : : #define MLX5_HW_CTRL_RX_PRIO_L2 (MLX5_HW_LOWEST_PRIO_ROOT)
58 : : #define MLX5_HW_CTRL_RX_PRIO_L3 (MLX5_HW_LOWEST_PRIO_ROOT - 1)
59 : : #define MLX5_HW_CTRL_RX_PRIO_L4 (MLX5_HW_LOWEST_PRIO_ROOT - 2)
60 : :
61 : : #define MLX5_HW_VLAN_PUSH_TYPE_IDX 0
62 : : #define MLX5_HW_VLAN_PUSH_VID_IDX 1
63 : : #define MLX5_HW_VLAN_PUSH_PCP_IDX 2
64 : :
65 : : #define MLX5_MIRROR_MAX_CLONES_NUM 3
66 : : #define MLX5_MIRROR_MAX_SAMPLE_ACTIONS_LEN 4
67 : :
68 : : #define MLX5_HW_PORT_IS_PROXY(priv) \
69 : : (!!((priv)->sh->esw_mode && (priv)->master))
70 : :
71 : :
72 : : struct mlx5_indlst_legacy {
73 : : struct mlx5_indirect_list indirect;
74 : : struct rte_flow_action_handle *handle;
75 : : enum rte_flow_action_type legacy_type;
76 : : };
77 : :
78 : : #define MLX5_CONST_ENCAP_ITEM(encap_type, ptr) \
79 : : (((const struct encap_type *)(ptr))->definition)
80 : :
81 : : /**
82 : : * Returns the size of a struct with a following layout:
83 : : *
84 : : * @code{.c}
85 : : * struct rte_flow_hw {
86 : : * // rte_flow_hw fields
87 : : * uint8_t rule[mlx5dr_rule_get_handle_size()];
88 : : * };
89 : : * @endcode
90 : : *
91 : : * Such struct is used as a basic container for HW Steering flow rule.
92 : : */
93 : : static size_t
94 : : mlx5_flow_hw_entry_size(void)
95 : : {
96 : 0 : return sizeof(struct rte_flow_hw) + mlx5dr_rule_get_handle_size();
97 : : }
98 : :
99 : : /**
100 : : * Returns the size of "auxed" rte_flow_hw structure which is assumed to be laid out as follows:
101 : : *
102 : : * @code{.c}
103 : : * struct {
104 : : * struct rte_flow_hw {
105 : : * // rte_flow_hw fields
106 : : * uint8_t rule[mlx5dr_rule_get_handle_size()];
107 : : * } flow;
108 : : * struct rte_flow_hw_aux aux;
109 : : * };
110 : : * @endcode
111 : : *
112 : : * Such struct is used whenever rte_flow_hw_aux cannot be allocated separately from the rte_flow_hw
113 : : * e.g., when table is resizable.
114 : : */
115 : : static size_t
116 : : mlx5_flow_hw_auxed_entry_size(void)
117 : : {
118 : 0 : size_t rule_size = mlx5dr_rule_get_handle_size();
119 : :
120 : 0 : return sizeof(struct rte_flow_hw) + rule_size + sizeof(struct rte_flow_hw_aux);
121 : : }
122 : :
123 : : /**
124 : : * Returns a valid pointer to rte_flow_hw_aux associated with given rte_flow_hw
125 : : * depending on template table configuration.
126 : : */
127 : : static __rte_always_inline struct rte_flow_hw_aux *
128 : : mlx5_flow_hw_aux(uint16_t port_id, struct rte_flow_hw *flow)
129 : : {
130 : 0 : struct rte_flow_template_table *table = flow->table;
131 : :
132 [ # # # # : 0 : if (rte_flow_template_table_resizable(port_id, &table->cfg.attr)) {
# # # # #
# # # # #
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# # # # #
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# # # # #
# # # # #
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# # # # #
# # # #
# ]
133 : 0 : size_t offset = sizeof(struct rte_flow_hw) + mlx5dr_rule_get_handle_size();
134 : :
135 : 0 : return RTE_PTR_ADD(flow, offset);
136 : : } else {
137 [ # # # # : 0 : return ((flow->nt_rule) ? flow->nt2hws->flow_aux : &table->flow_aux[flow->idx - 1]);
# # # # #
# # # # #
# # # # #
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# # # # #
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# ]
138 : : }
139 : : }
140 : :
141 : : static __rte_always_inline void
142 : : mlx5_flow_hw_aux_set_age_idx(struct rte_flow_hw *flow,
143 : : struct rte_flow_hw_aux *aux,
144 : : uint32_t age_idx)
145 : : {
146 : : /*
147 : : * Only when creating a flow rule, the type will be set explicitly.
148 : : * Or else, it should be none in the rule update case.
149 : : */
150 [ # # # # : 0 : if (unlikely(flow->operation_type == MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE))
# # # # #
# # # # #
# # # # #
# ]
151 : 0 : aux->upd.age_idx = age_idx;
152 : : else
153 : 0 : aux->orig.age_idx = age_idx;
154 : : }
155 : :
156 : : static __rte_always_inline uint32_t
157 : : mlx5_flow_hw_aux_get_age_idx(struct rte_flow_hw *flow, struct rte_flow_hw_aux *aux)
158 : : {
159 [ # # # # : 0 : if (unlikely(flow->operation_type == MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE))
# # # # #
# # # ]
160 : 0 : return aux->upd.age_idx;
161 : : else
162 : 0 : return aux->orig.age_idx;
163 : : }
164 : :
165 : : static __rte_always_inline void
166 : : mlx5_flow_hw_aux_set_mtr_id(struct rte_flow_hw *flow,
167 : : struct rte_flow_hw_aux *aux,
168 : : uint32_t mtr_id)
169 : : {
170 [ # # # # : 0 : if (unlikely(flow->operation_type == MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE))
# # # # #
# ]
171 : 0 : aux->upd.mtr_id = mtr_id;
172 : : else
173 : 0 : aux->orig.mtr_id = mtr_id;
174 : : }
175 : :
176 : : static __rte_always_inline uint32_t
177 : : mlx5_flow_hw_aux_get_mtr_id(struct rte_flow_hw *flow, struct rte_flow_hw_aux *aux)
178 : : {
179 [ # # ]: 0 : if (unlikely(flow->operation_type == MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE))
180 : 0 : return aux->upd.mtr_id;
181 : : else
182 : 0 : return aux->orig.mtr_id;
183 : : }
184 : :
185 : : static __rte_always_inline struct mlx5_hw_q_job *
186 : : flow_hw_action_job_init(struct mlx5_priv *priv, uint32_t queue,
187 : : const struct rte_flow_action_handle *handle,
188 : : void *user_data, void *query_data,
189 : : enum mlx5_hw_job_type type,
190 : : enum mlx5_hw_indirect_type indirect_type,
191 : : struct rte_flow_error *error);
192 : : static void
193 : : flow_hw_age_count_release(struct mlx5_priv *priv, uint32_t queue, struct rte_flow_hw *flow,
194 : : struct rte_flow_error *error);
195 : :
196 : : static int
197 : : mlx5_tbl_multi_pattern_process(struct rte_eth_dev *dev,
198 : : struct rte_flow_template_table *tbl,
199 : : struct mlx5_multi_pattern_segment *segment,
200 : : uint32_t bulk_size,
201 : : struct rte_flow_error *error);
202 : : static void
203 : : mlx5_destroy_multi_pattern_segment(struct mlx5_multi_pattern_segment *segment);
204 : :
205 : : static __rte_always_inline enum mlx5_indirect_list_type
206 : : flow_hw_inlist_type_get(const struct rte_flow_action *actions);
207 : :
208 : : static int
209 : : flow_hw_allocate_actions(struct rte_eth_dev *dev,
210 : : uint64_t action_flags,
211 : : struct rte_flow_error *error);
212 : :
213 : : bool
214 : 0 : mlx5_hw_ctx_validate(const struct rte_eth_dev *dev, struct rte_flow_error *error)
215 : : {
216 : 0 : const struct mlx5_priv *priv = dev->data->dev_private;
217 : :
218 [ # # ]: 0 : if (!priv->dr_ctx) {
219 : 0 : rte_flow_error_set(error, EINVAL,
220 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
221 : : "non-template flow engine was not configured");
222 : 0 : return false;
223 : : }
224 : : return true;
225 : : }
226 : :
227 : : static int
228 : : flow_hw_allocate_actions(struct rte_eth_dev *dev,
229 : : uint64_t action_flags,
230 : : struct rte_flow_error *error);
231 : :
232 : : static __rte_always_inline int
233 : : mlx5_multi_pattern_reformat_to_index(enum mlx5dr_action_type type)
234 : : {
235 : : switch (type) {
236 : : case MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2:
237 : : return 0;
238 : : case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2:
239 : : return 1;
240 : : case MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2:
241 : : return 2;
242 : : case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3:
243 : : return 3;
244 : : default:
245 : : break;
246 : : }
247 : : return -1;
248 : : }
249 : :
250 : : /* Include only supported reformat actions for BWC non template API. */
251 : : static __rte_always_inline int
252 : : mlx5_bwc_multi_pattern_reformat_to_index(enum mlx5dr_action_type type)
253 : : {
254 : 0 : switch (type) {
255 : : case MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2:
256 : : case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2:
257 : : case MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2:
258 : : case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3:
259 : : return mlx5_multi_pattern_reformat_to_index(type);
260 : : default:
261 : : break;
262 : : }
263 : : return -1;
264 : : }
265 : :
266 : : static __rte_always_inline enum mlx5dr_action_type
267 : : mlx5_multi_pattern_reformat_index_to_type(uint32_t ix)
268 : : {
269 : : switch (ix) {
270 : : case 0:
271 : : return MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2;
272 : : case 1:
273 : : return MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;
274 : : case 2:
275 : : return MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2;
276 : : case 3:
277 : : return MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3;
278 : : default:
279 : : break;
280 : : }
281 : : return MLX5DR_ACTION_TYP_MAX;
282 : : }
283 : :
284 : : static inline enum mlx5dr_table_type
285 : : get_mlx5dr_table_type(const struct rte_flow_attr *attr)
286 : : {
287 : : enum mlx5dr_table_type type;
288 : :
289 [ # # ]: 0 : if (attr->transfer)
290 : : type = MLX5DR_TABLE_TYPE_FDB;
291 [ # # # # : 0 : else if (attr->egress)
# # # # #
# # # # #
# # ]
292 : : type = MLX5DR_TABLE_TYPE_NIC_TX;
293 : : else
294 : : type = MLX5DR_TABLE_TYPE_NIC_RX;
295 : : return type;
296 : : }
297 : :
298 : : /* Non template default queue size used for inner ctrl queue. */
299 : : #define MLX5_NT_DEFAULT_QUEUE_SIZE 32
300 : :
301 : : struct mlx5_mirror_clone {
302 : : enum rte_flow_action_type type;
303 : : void *action_ctx;
304 : : };
305 : :
306 : : struct mlx5_mirror {
307 : : struct mlx5_indirect_list indirect;
308 : : uint32_t clones_num;
309 : : struct mlx5dr_action *mirror_action;
310 : : struct mlx5_mirror_clone clone[MLX5_MIRROR_MAX_CLONES_NUM];
311 : : };
312 : :
313 : : static int flow_hw_flush_all_ctrl_flows(struct rte_eth_dev *dev);
314 : : static int flow_hw_translate_group(struct rte_eth_dev *dev,
315 : : const struct mlx5_flow_template_table_cfg *cfg,
316 : : uint32_t group,
317 : : uint32_t *table_group,
318 : : struct rte_flow_error *error);
319 : : static __rte_always_inline int
320 : : flow_hw_set_vlan_vid_construct(struct rte_eth_dev *dev,
321 : : struct mlx5_modification_cmd *mhdr_cmd,
322 : : struct mlx5_action_construct_data *act_data,
323 : : const struct mlx5_hw_actions *hw_acts,
324 : : const struct rte_flow_action *action);
325 : : static void
326 : : flow_hw_construct_quota(struct mlx5_priv *priv,
327 : : struct mlx5dr_rule_action *rule_act, uint32_t qid);
328 : :
329 : : static int
330 : : mlx5_flow_ct_init(struct rte_eth_dev *dev,
331 : : uint32_t nb_conn_tracks,
332 : : uint16_t nb_queue);
333 : :
334 : : static __rte_always_inline uint32_t flow_hw_tx_tag_regc_mask(struct rte_eth_dev *dev);
335 : : static __rte_always_inline uint32_t flow_hw_tx_tag_regc_value(struct rte_eth_dev *dev);
336 : :
337 : : static int flow_hw_async_create_validate(struct rte_eth_dev *dev,
338 : : const uint32_t queue,
339 : : const struct rte_flow_template_table *table,
340 : : enum rte_flow_table_insertion_type insertion_type,
341 : : const uint32_t rule_index,
342 : : const struct rte_flow_item items[],
343 : : const uint8_t pattern_template_index,
344 : : const struct rte_flow_action actions[],
345 : : const uint8_t action_template_index,
346 : : struct rte_flow_error *error);
347 : : static int flow_hw_async_update_validate(struct rte_eth_dev *dev,
348 : : const uint32_t queue,
349 : : const struct rte_flow_hw *flow,
350 : : const struct rte_flow_action actions[],
351 : : const uint8_t action_template_index,
352 : : struct rte_flow_error *error);
353 : : static int flow_hw_async_destroy_validate(struct rte_eth_dev *dev,
354 : : const uint32_t queue,
355 : : const struct rte_flow_hw *flow,
356 : : struct rte_flow_error *error);
357 : :
358 : : const struct mlx5_flow_driver_ops mlx5_flow_hw_drv_ops;
359 : :
360 : : /* DR action flags with different table. */
361 : : static uint32_t mlx5_hw_act_flag[MLX5_HW_ACTION_FLAG_MAX]
362 : : [MLX5DR_TABLE_TYPE_MAX] = {
363 : : {
364 : : MLX5DR_ACTION_FLAG_ROOT_RX,
365 : : MLX5DR_ACTION_FLAG_ROOT_TX,
366 : : MLX5DR_ACTION_FLAG_ROOT_FDB,
367 : : },
368 : : {
369 : : MLX5DR_ACTION_FLAG_HWS_RX,
370 : : MLX5DR_ACTION_FLAG_HWS_TX,
371 : : MLX5DR_ACTION_FLAG_HWS_FDB,
372 : : },
373 : : };
374 : :
375 : : /* Ethernet item spec for promiscuous mode. */
376 : : static const struct rte_flow_item_eth ctrl_rx_eth_promisc_spec = {
377 : : .hdr.dst_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
378 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
379 : : .hdr.ether_type = 0,
380 : : };
381 : : /* Ethernet item mask for promiscuous mode. */
382 : : static const struct rte_flow_item_eth ctrl_rx_eth_promisc_mask = {
383 : : .hdr.dst_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
384 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
385 : : .hdr.ether_type = 0,
386 : : };
387 : :
388 : : /* Ethernet item spec for all multicast mode. */
389 : : static const struct rte_flow_item_eth ctrl_rx_eth_mcast_spec = {
390 : : .hdr.dst_addr.addr_bytes = { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 },
391 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
392 : : .hdr.ether_type = 0,
393 : : };
394 : : /* Ethernet item mask for all multicast mode. */
395 : : static const struct rte_flow_item_eth ctrl_rx_eth_mcast_mask = {
396 : : .hdr.dst_addr.addr_bytes = { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 },
397 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
398 : : .hdr.ether_type = 0,
399 : : };
400 : :
401 : : /* Ethernet item spec for IPv4 multicast traffic. */
402 : : static const struct rte_flow_item_eth ctrl_rx_eth_ipv4_mcast_spec = {
403 : : .hdr.dst_addr.addr_bytes = { 0x01, 0x00, 0x5e, 0x00, 0x00, 0x00 },
404 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
405 : : .hdr.ether_type = 0,
406 : : };
407 : : /* Ethernet item mask for IPv4 multicast traffic. */
408 : : static const struct rte_flow_item_eth ctrl_rx_eth_ipv4_mcast_mask = {
409 : : .hdr.dst_addr.addr_bytes = { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 },
410 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
411 : : .hdr.ether_type = 0,
412 : : };
413 : :
414 : : /* Ethernet item spec for IPv6 multicast traffic. */
415 : : static const struct rte_flow_item_eth ctrl_rx_eth_ipv6_mcast_spec = {
416 : : .hdr.dst_addr.addr_bytes = { 0x33, 0x33, 0x00, 0x00, 0x00, 0x00 },
417 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
418 : : .hdr.ether_type = 0,
419 : : };
420 : : /* Ethernet item mask for IPv6 multicast traffic. */
421 : : static const struct rte_flow_item_eth ctrl_rx_eth_ipv6_mcast_mask = {
422 : : .hdr.dst_addr.addr_bytes = { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 },
423 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
424 : : .hdr.ether_type = 0,
425 : : };
426 : :
427 : : /* Ethernet item mask for unicast traffic. */
428 : : static const struct rte_flow_item_eth ctrl_rx_eth_dmac_mask = {
429 : : .hdr.dst_addr.addr_bytes = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
430 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
431 : : .hdr.ether_type = 0,
432 : : };
433 : :
434 : : /* Ethernet item spec for broadcast. */
435 : : static const struct rte_flow_item_eth ctrl_rx_eth_bcast_spec = {
436 : : .hdr.dst_addr.addr_bytes = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
437 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
438 : : .hdr.ether_type = 0,
439 : : };
440 : :
441 : : static inline uint32_t
442 : : flow_hw_q_pending(struct mlx5_priv *priv, uint32_t queue)
443 : : {
444 : 0 : struct mlx5_hw_q *q = &priv->hw_q[queue];
445 : :
446 : : MLX5_ASSERT(q->size >= q->job_idx);
447 : 0 : return (q->size - q->job_idx) + q->ongoing_flow_ops;
448 : : }
449 : :
450 : : static inline void
451 : 0 : flow_hw_q_inc_flow_ops(struct mlx5_priv *priv, uint32_t queue)
452 : : {
453 : 0 : struct mlx5_hw_q *q = &priv->hw_q[queue];
454 : :
455 : 0 : q->ongoing_flow_ops++;
456 : 0 : }
457 : :
458 : : static inline void
459 : : flow_hw_q_dec_flow_ops(struct mlx5_priv *priv, uint32_t queue)
460 : : {
461 : 0 : struct mlx5_hw_q *q = &priv->hw_q[queue];
462 : :
463 : 0 : q->ongoing_flow_ops--;
464 : : }
465 : :
466 : : static inline enum mlx5dr_matcher_insert_mode
467 : : flow_hw_matcher_insert_mode_get(enum rte_flow_table_insertion_type insert_type)
468 : : {
469 : 0 : if (insert_type == RTE_FLOW_TABLE_INSERTION_TYPE_PATTERN)
470 : : return MLX5DR_MATCHER_INSERT_BY_HASH;
471 : : else
472 : 0 : return MLX5DR_MATCHER_INSERT_BY_INDEX;
473 : : }
474 : :
475 : : static inline enum mlx5dr_matcher_distribute_mode
476 : : flow_hw_matcher_distribute_mode_get(enum rte_flow_table_hash_func hash_func)
477 : : {
478 [ # # ]: 0 : if (hash_func == RTE_FLOW_TABLE_HASH_FUNC_LINEAR)
479 : : return MLX5DR_MATCHER_DISTRIBUTE_BY_LINEAR;
480 : : else
481 : 0 : return MLX5DR_MATCHER_DISTRIBUTE_BY_HASH;
482 : : }
483 : :
484 : : /**
485 : : * Set the hash fields according to the @p rss_desc information.
486 : : *
487 : : * @param[in] rss_desc
488 : : * Pointer to the mlx5_flow_rss_desc.
489 : : * @param[out] hash_fields
490 : : * Pointer to the RSS hash fields.
491 : : */
492 : : static void
493 : 0 : flow_hw_hashfields_set(struct mlx5_flow_rss_desc *rss_desc,
494 : : uint64_t *hash_fields)
495 : : {
496 : : uint64_t fields = 0;
497 : : int rss_inner = 0;
498 [ # # ]: 0 : uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
499 : :
500 : : #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
501 [ # # ]: 0 : if (rss_desc->level >= 2)
502 : : rss_inner = 1;
503 : : #endif
504 [ # # ]: 0 : if (rss_types & MLX5_IPV4_LAYER_TYPES) {
505 [ # # ]: 0 : if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
506 : : fields |= IBV_RX_HASH_SRC_IPV4;
507 [ # # ]: 0 : else if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
508 : : fields |= IBV_RX_HASH_DST_IPV4;
509 : : else
510 : : fields |= MLX5_IPV4_IBV_RX_HASH;
511 [ # # ]: 0 : } else if (rss_types & MLX5_IPV6_LAYER_TYPES) {
512 [ # # ]: 0 : if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
513 : : fields |= IBV_RX_HASH_SRC_IPV6;
514 [ # # ]: 0 : else if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
515 : : fields |= IBV_RX_HASH_DST_IPV6;
516 : : else
517 : : fields |= MLX5_IPV6_IBV_RX_HASH;
518 : : }
519 [ # # ]: 0 : if (rss_types & RTE_ETH_RSS_UDP) {
520 [ # # ]: 0 : if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
521 : 0 : fields |= IBV_RX_HASH_SRC_PORT_UDP;
522 [ # # ]: 0 : else if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
523 : 0 : fields |= IBV_RX_HASH_DST_PORT_UDP;
524 : : else
525 : 0 : fields |= MLX5_UDP_IBV_RX_HASH;
526 [ # # ]: 0 : } else if (rss_types & RTE_ETH_RSS_TCP) {
527 [ # # ]: 0 : if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
528 : 0 : fields |= IBV_RX_HASH_SRC_PORT_TCP;
529 [ # # ]: 0 : else if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
530 : 0 : fields |= IBV_RX_HASH_DST_PORT_TCP;
531 : : else
532 : 0 : fields |= MLX5_TCP_IBV_RX_HASH;
533 : : }
534 [ # # ]: 0 : if (rss_types & RTE_ETH_RSS_ESP)
535 : 0 : fields |= IBV_RX_HASH_IPSEC_SPI;
536 [ # # ]: 0 : if (rss_inner)
537 : 0 : fields |= IBV_RX_HASH_INNER;
538 : 0 : *hash_fields |= fields;
539 : 0 : }
540 : :
541 : : /**
542 : : * Generate the matching pattern item flags.
543 : : *
544 : : * @param[in] items
545 : : * Pointer to the list of items.
546 : : *
547 : : * @return
548 : : * Matching item flags. RSS hash field function
549 : : * silently ignores the flags which are unsupported.
550 : : */
551 : : static uint64_t
552 : 0 : flow_hw_matching_item_flags_get(const struct rte_flow_item items[])
553 : : {
554 : : uint64_t item_flags = 0;
555 : : uint64_t last_item = 0;
556 : :
557 [ # # ]: 0 : for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
558 : 0 : enum rte_flow_item_flex_tunnel_mode tunnel_mode = FLEX_TUNNEL_MODE_SINGLE;
559 : 0 : int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
560 : : int item_type = items->type;
561 : :
562 [ # # # # : 0 : switch (item_type) {
# # # # #
# # # # #
# ]
563 : 0 : case RTE_FLOW_ITEM_TYPE_IPV4:
564 [ # # ]: 0 : last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
565 : : MLX5_FLOW_LAYER_OUTER_L3_IPV4;
566 : : break;
567 : 0 : case RTE_FLOW_ITEM_TYPE_IPV6:
568 [ # # ]: 0 : last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
569 : : MLX5_FLOW_LAYER_OUTER_L3_IPV6;
570 : : break;
571 : 0 : case RTE_FLOW_ITEM_TYPE_TCP:
572 [ # # ]: 0 : last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
573 : : MLX5_FLOW_LAYER_OUTER_L4_TCP;
574 : : break;
575 : 0 : case RTE_FLOW_ITEM_TYPE_UDP:
576 [ # # ]: 0 : last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
577 : : MLX5_FLOW_LAYER_OUTER_L4_UDP;
578 : : break;
579 : 0 : case RTE_FLOW_ITEM_TYPE_IPV6_ROUTING_EXT:
580 [ # # ]: 0 : last_item = tunnel ? MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT :
581 : : MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT;
582 : : break;
583 : 0 : case RTE_FLOW_ITEM_TYPE_GRE:
584 : : last_item = MLX5_FLOW_LAYER_GRE;
585 : 0 : break;
586 : 0 : case RTE_FLOW_ITEM_TYPE_NVGRE:
587 : : last_item = MLX5_FLOW_LAYER_GRE;
588 : 0 : break;
589 : 0 : case RTE_FLOW_ITEM_TYPE_VXLAN:
590 : : last_item = MLX5_FLOW_LAYER_VXLAN;
591 : 0 : break;
592 : 0 : case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
593 : : last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
594 : 0 : break;
595 : 0 : case RTE_FLOW_ITEM_TYPE_GENEVE:
596 : : last_item = MLX5_FLOW_LAYER_GENEVE;
597 : 0 : break;
598 : 0 : case RTE_FLOW_ITEM_TYPE_MPLS:
599 : : last_item = MLX5_FLOW_LAYER_MPLS;
600 : 0 : break;
601 : 0 : case RTE_FLOW_ITEM_TYPE_GTP:
602 : : last_item = MLX5_FLOW_LAYER_GTP;
603 : 0 : break;
604 : 0 : case RTE_FLOW_ITEM_TYPE_COMPARE:
605 : : last_item = MLX5_FLOW_ITEM_COMPARE;
606 : 0 : break;
607 : 0 : case RTE_FLOW_ITEM_TYPE_FLEX:
608 : 0 : mlx5_flex_get_tunnel_mode(items, &tunnel_mode);
609 : 0 : last_item = tunnel_mode == FLEX_TUNNEL_MODE_TUNNEL ?
610 [ # # ]: 0 : MLX5_FLOW_ITEM_FLEX_TUNNEL :
611 [ # # ]: 0 : tunnel ? MLX5_FLOW_ITEM_INNER_FLEX :
612 : : MLX5_FLOW_ITEM_OUTER_FLEX;
613 : : break;
614 : : default:
615 : : break;
616 : : }
617 : 0 : item_flags |= last_item;
618 : : }
619 : 0 : return item_flags;
620 : : }
621 : :
622 : : static uint64_t
623 : 0 : flow_hw_action_flags_get(const struct rte_flow_action actions[],
624 : : const struct rte_flow_action **qrss,
625 : : const struct rte_flow_action **mark,
626 : : int *encap_idx,
627 : : int *act_cnt,
628 : : struct rte_flow_error *error)
629 : : {
630 : : uint64_t action_flags = 0;
631 : : const struct rte_flow_action *action;
632 : : const struct rte_flow_action_raw_encap *raw_encap;
633 : : int raw_decap_idx = -1;
634 : : int action_idx;
635 : :
636 : 0 : *encap_idx = -1;
637 : : action_idx = 0;
638 [ # # ]: 0 : for (action = actions; action->type != RTE_FLOW_ACTION_TYPE_END; action++) {
639 : 0 : int type = (int)action->type;
640 [ # # # # : 0 : switch (type) {
# # # # #
# # # # #
# # # # #
# # # #
# ]
641 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT:
642 [ # # # # : 0 : switch (MLX5_INDIRECT_ACTION_TYPE_GET(action->conf)) {
# # ]
643 : 0 : case MLX5_INDIRECT_ACTION_TYPE_RSS:
644 : 0 : goto rss;
645 : 0 : case MLX5_INDIRECT_ACTION_TYPE_AGE:
646 : 0 : goto age;
647 : 0 : case MLX5_INDIRECT_ACTION_TYPE_COUNT:
648 : 0 : goto count;
649 : 0 : case MLX5_INDIRECT_ACTION_TYPE_CT:
650 : 0 : goto ct;
651 : 0 : case MLX5_INDIRECT_ACTION_TYPE_METER_MARK:
652 : 0 : goto meter;
653 : 0 : default:
654 : 0 : goto error;
655 : : }
656 : : break;
657 : 0 : case RTE_FLOW_ACTION_TYPE_DROP:
658 : 0 : action_flags |= MLX5_FLOW_ACTION_DROP;
659 : 0 : break;
660 : 0 : case RTE_FLOW_ACTION_TYPE_FLAG:
661 : 0 : action_flags |= MLX5_FLOW_ACTION_FLAG;
662 : 0 : break;
663 : 0 : case RTE_FLOW_ACTION_TYPE_MARK:
664 : 0 : action_flags |= MLX5_FLOW_ACTION_MARK;
665 : 0 : *mark = action;
666 : 0 : break;
667 : 0 : case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
668 : 0 : action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
669 : 0 : break;
670 : 0 : case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
671 : 0 : action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
672 : 0 : break;
673 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP:
674 : 0 : action_flags |= MLX5_FLOW_ACTION_JUMP;
675 : 0 : break;
676 : 0 : case RTE_FLOW_ACTION_TYPE_QUEUE:
677 : 0 : action_flags |= MLX5_FLOW_ACTION_QUEUE;
678 : 0 : *qrss = action;
679 : 0 : break;
680 : : case RTE_FLOW_ACTION_TYPE_RSS:
681 : 0 : rss:
682 : 0 : action_flags |= MLX5_FLOW_ACTION_RSS;
683 : 0 : *qrss = action;
684 : 0 : break;
685 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
686 : : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
687 : 0 : action_flags |= MLX5_FLOW_ACTION_ENCAP;
688 : 0 : *encap_idx = action_idx;
689 : 0 : break;
690 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
691 : 0 : action_flags |= MLX5_FLOW_ACTION_ENCAP;
692 : 0 : raw_encap = action->conf;
693 [ # # ]: 0 : if (raw_encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
694 : 0 : *encap_idx = raw_decap_idx != -1 ?
695 [ # # ]: 0 : raw_decap_idx : action_idx;
696 : : break;
697 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
698 : : case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
699 : 0 : action_flags |= MLX5_FLOW_ACTION_DECAP;
700 : 0 : break;
701 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
702 : 0 : action_flags |= MLX5_FLOW_ACTION_DECAP;
703 : : raw_decap_idx = action_idx;
704 : 0 : break;
705 : 0 : case RTE_FLOW_ACTION_TYPE_SEND_TO_KERNEL:
706 : 0 : action_flags |= MLX5_FLOW_ACTION_SEND_TO_KERNEL;
707 : 0 : break;
708 : 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
709 : 0 : action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
710 : 0 : break;
711 : 0 : case RTE_FLOW_ACTION_TYPE_PORT_ID:
712 : : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
713 : 0 : action_flags |= MLX5_FLOW_ACTION_PORT_ID;
714 : 0 : break;
715 : : case RTE_FLOW_ACTION_TYPE_AGE:
716 : 0 : age:
717 : 0 : action_flags |= MLX5_FLOW_ACTION_AGE;
718 : 0 : break;
719 : : case RTE_FLOW_ACTION_TYPE_COUNT:
720 : 0 : count:
721 : 0 : action_flags |= MLX5_FLOW_ACTION_COUNT;
722 : 0 : break;
723 : : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
724 : 0 : ct:
725 : 0 : action_flags |= MLX5_FLOW_ACTION_CT;
726 : 0 : break;
727 : : case RTE_FLOW_ACTION_TYPE_METER_MARK:
728 : 0 : meter:
729 : 0 : action_flags |= MLX5_FLOW_ACTION_METER;
730 : 0 : break;
731 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
732 : 0 : action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
733 : 0 : break;
734 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
735 : 0 : action_flags |= MLX5_FLOW_ACTION_JUMP_TO_TABLE_INDEX;
736 : 0 : break;
737 : : case RTE_FLOW_ACTION_TYPE_VOID:
738 : : case RTE_FLOW_ACTION_TYPE_END:
739 : : break;
740 : 0 : default:
741 : 0 : goto error;
742 : : }
743 : 0 : action_idx++;
744 : : }
745 [ # # ]: 0 : if (*encap_idx == -1)
746 : 0 : *encap_idx = action_idx;
747 : 0 : action_idx++; /* The END action. */
748 : 0 : *act_cnt = action_idx;
749 : 0 : return action_flags;
750 : 0 : error:
751 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
752 : : action, "invalid flow action");
753 : 0 : return 0;
754 : : }
755 : :
756 : : /**
757 : : * Register destination table DR jump action.
758 : : *
759 : : * @param[in] dev
760 : : * Pointer to the rte_eth_dev structure.
761 : : * @param[in] table_attr
762 : : * Pointer to the flow attributes.
763 : : * @param[in] dest_group
764 : : * The destination group ID.
765 : : * @param[out] error
766 : : * Pointer to error structure.
767 : : *
768 : : * @return
769 : : * Table on success, NULL otherwise and rte_errno is set.
770 : : */
771 : : static struct mlx5_hw_jump_action *
772 : 0 : flow_hw_jump_action_register(struct rte_eth_dev *dev,
773 : : const struct mlx5_flow_template_table_cfg *cfg,
774 : : uint32_t dest_group,
775 : : struct rte_flow_error *error)
776 : : {
777 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
778 : 0 : struct rte_flow_attr jattr = cfg->attr.flow_attr;
779 : : struct mlx5_flow_group *grp;
780 : 0 : struct mlx5_flow_cb_ctx ctx = {
781 : : .dev = dev,
782 : : .error = error,
783 : : .data = &jattr,
784 : : };
785 : : struct mlx5_list_entry *ge;
786 : : uint32_t target_group;
787 : :
788 : 0 : target_group = dest_group;
789 [ # # ]: 0 : if (flow_hw_translate_group(dev, cfg, dest_group, &target_group, error))
790 : : return NULL;
791 : 0 : jattr.group = target_group;
792 : 0 : ge = mlx5_hlist_register(priv->sh->flow_tbls, target_group, &ctx);
793 [ # # ]: 0 : if (!ge)
794 : : return NULL;
795 : : grp = container_of(ge, struct mlx5_flow_group, entry);
796 : 0 : return &grp->jump;
797 : : }
798 : :
799 : : /**
800 : : * Release jump action.
801 : : *
802 : : * @param[in] dev
803 : : * Pointer to the rte_eth_dev structure.
804 : : * @param[in] jump
805 : : * Pointer to the jump action.
806 : : */
807 : :
808 : : static void
809 : : flow_hw_jump_release(struct rte_eth_dev *dev, struct mlx5_hw_jump_action *jump)
810 : : {
811 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
812 : : struct mlx5_flow_group *grp;
813 : :
814 : 0 : grp = container_of(jump, struct mlx5_flow_group, jump);
815 : 0 : mlx5_hlist_unregister(priv->sh->flow_tbls, &grp->entry);
816 : 0 : }
817 : :
818 : : /**
819 : : * Register queue/RSS action.
820 : : *
821 : : * @param[in] dev
822 : : * Pointer to the rte_eth_dev structure.
823 : : * @param[in] hws_flags
824 : : * DR action flags.
825 : : * @param[in] action
826 : : * rte flow action.
827 : : * @param[in] item_flags
828 : : * Item flags for non template rule.
829 : : * @param[in] is_template
830 : : * True if it is a template rule.
831 : : *
832 : : * @return
833 : : * Table on success, NULL otherwise and rte_errno is set.
834 : : */
835 : : static inline struct mlx5_hrxq*
836 : 0 : flow_hw_tir_action_register(struct rte_eth_dev *dev,
837 : : uint32_t hws_flags,
838 : : const struct rte_flow_action *action)
839 : : {
840 : 0 : struct mlx5_flow_rss_desc rss_desc = {
841 : : .hws_flags = hws_flags,
842 : : };
843 : : struct mlx5_hrxq *hrxq;
844 : :
845 [ # # ]: 0 : if (action->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
846 : 0 : const struct rte_flow_action_queue *queue = action->conf;
847 : :
848 : 0 : rss_desc.const_q = &queue->index;
849 : 0 : rss_desc.queue_num = 1;
850 : : } else {
851 : 0 : const struct rte_flow_action_rss *rss = action->conf;
852 : :
853 : 0 : rss_desc.queue_num = rss->queue_num;
854 : 0 : rss_desc.const_q = rss->queue;
855 : 0 : memcpy(rss_desc.key,
856 [ # # ]: 0 : !rss->key ? rss_hash_default_key : rss->key,
857 : : MLX5_RSS_HASH_KEY_LEN);
858 : 0 : rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
859 [ # # ]: 0 : rss_desc.types = !rss->types ? RTE_ETH_RSS_IP : rss->types;
860 : 0 : rss_desc.symmetric_hash_function = MLX5_RSS_IS_SYMM(rss->func);
861 : 0 : flow_hw_hashfields_set(&rss_desc, &rss_desc.hash_fields);
862 : 0 : flow_dv_action_rss_l34_hash_adjust(rss->types,
863 : : &rss_desc.hash_fields);
864 [ # # ]: 0 : if (rss->level > 1) {
865 : 0 : rss_desc.hash_fields |= IBV_RX_HASH_INNER;
866 : 0 : rss_desc.tunnel = 1;
867 : : }
868 : : }
869 : 0 : hrxq = mlx5_hrxq_get(dev, &rss_desc);
870 : 0 : return hrxq;
871 : : }
872 : :
873 : : static __rte_always_inline int
874 : : flow_hw_ct_compile(struct rte_eth_dev *dev,
875 : : uint32_t queue, uint32_t idx,
876 : : struct mlx5dr_rule_action *rule_act)
877 : : {
878 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
879 : : struct mlx5_aso_ct_action *ct;
880 : :
881 : 0 : ct = mlx5_ipool_get(priv->hws_ctpool->cts, idx);
882 [ # # # # : 0 : if (!ct || (!priv->shared_host && mlx5_aso_ct_available(priv->sh, queue, ct)))
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # ]
883 : : return -1;
884 : 0 : rule_act->action = priv->hws_ctpool->dr_action;
885 : 0 : rule_act->aso_ct.offset = ct->offset;
886 : 0 : rule_act->aso_ct.direction = ct->is_original ?
887 : 0 : MLX5DR_ACTION_ASO_CT_DIRECTION_INITIATOR :
888 : : MLX5DR_ACTION_ASO_CT_DIRECTION_RESPONDER;
889 : : return 0;
890 : : }
891 : :
892 : : static void
893 : : flow_hw_template_destroy_reformat_action(struct mlx5_hw_encap_decap_action *encap_decap)
894 : : {
895 [ # # # # ]: 0 : if (encap_decap->action && !encap_decap->multi_pattern)
896 : 0 : mlx5dr_action_destroy(encap_decap->action);
897 : : }
898 : :
899 : : static void
900 : : flow_hw_template_destroy_mhdr_action(struct mlx5_hw_modify_header_action *mhdr)
901 : : {
902 [ # # # # ]: 0 : if (mhdr->action && !mhdr->multi_pattern)
903 : 0 : mlx5dr_action_destroy(mhdr->action);
904 : : }
905 : :
906 : : /**
907 : : * Destroy DR actions created by action template.
908 : : *
909 : : * For DR actions created during table creation's action translate.
910 : : * Need to destroy the DR action when destroying the table.
911 : : *
912 : : * @param[in] dev
913 : : * Pointer to the rte_eth_dev structure.
914 : : * @param[in] acts
915 : : * Pointer to the template HW steering DR actions.
916 : : */
917 : : static void
918 : 0 : __flow_hw_actions_release(struct rte_eth_dev *dev, struct mlx5_hw_actions *acts)
919 : : {
920 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
921 : :
922 [ # # ]: 0 : if (acts->mark)
923 [ # # ]: 0 : if (!(rte_atomic_fetch_sub_explicit(&priv->hws_mark_refcnt, 1,
924 : : rte_memory_order_relaxed) - 1))
925 : 0 : flow_hw_rxq_flag_set(dev, false);
926 : :
927 [ # # ]: 0 : if (acts->jump) {
928 : : struct mlx5_flow_group *grp;
929 : :
930 : 0 : grp = container_of
931 : : (acts->jump, struct mlx5_flow_group, jump);
932 : 0 : mlx5_hlist_unregister(priv->sh->flow_tbls, &grp->entry);
933 : 0 : acts->jump = NULL;
934 : : }
935 [ # # ]: 0 : if (acts->tir) {
936 : 0 : mlx5_hrxq_release(dev, acts->tir->idx);
937 : 0 : acts->tir = NULL;
938 : : }
939 [ # # ]: 0 : if (acts->encap_decap) {
940 : : flow_hw_template_destroy_reformat_action(acts->encap_decap);
941 : 0 : mlx5_free(acts->encap_decap);
942 : 0 : acts->encap_decap = NULL;
943 : : }
944 [ # # ]: 0 : if (acts->push_remove) {
945 [ # # ]: 0 : if (acts->push_remove->action)
946 : 0 : mlx5dr_action_destroy(acts->push_remove->action);
947 : 0 : mlx5_free(acts->push_remove);
948 : 0 : acts->push_remove = NULL;
949 : : }
950 [ # # ]: 0 : if (acts->mhdr) {
951 : : flow_hw_template_destroy_mhdr_action(acts->mhdr);
952 : 0 : mlx5_free(acts->mhdr);
953 : 0 : acts->mhdr = NULL;
954 : : }
955 [ # # ]: 0 : if (mlx5_hws_cnt_id_valid(acts->cnt_id)) {
956 [ # # ]: 0 : mlx5_hws_cnt_shared_put(priv->hws_cpool, &acts->cnt_id);
957 : 0 : acts->cnt_id = 0;
958 : : }
959 [ # # ]: 0 : if (acts->mtr_id) {
960 : 0 : mlx5_ipool_free(priv->hws_mpool->idx_pool, acts->mtr_id);
961 : 0 : acts->mtr_id = 0;
962 : : }
963 : 0 : }
964 : :
965 : : /**
966 : : * Release the action data back into the pool without destroy any action.
967 : : *
968 : : * @param[in] dev
969 : : * Pointer to the rte_eth_dev structure.
970 : : * @param[in] acts
971 : : * Pointer to the template HW steering DR actions.
972 : : */
973 : : static inline void
974 : 0 : __flow_hw_act_data_flush(struct rte_eth_dev *dev, struct mlx5_hw_actions *acts)
975 : : {
976 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
977 : : struct mlx5_action_construct_data *data;
978 : :
979 [ # # ]: 0 : while (!LIST_EMPTY(&acts->act_list)) {
980 : : data = LIST_FIRST(&acts->act_list);
981 [ # # ]: 0 : LIST_REMOVE(data, next);
982 : 0 : mlx5_ipool_free(priv->acts_ipool, data->idx);
983 : : }
984 : 0 : }
985 : :
986 : : /*
987 : : * Destroy DR actions created by action template.
988 : : *
989 : : * For DR actions created during table creation's action translate.
990 : : * Need to destroy the DR action when destroying the table.
991 : : *
992 : : * @param[in] dev
993 : : * Pointer to the rte_eth_dev structure.
994 : : * @param[in] acts
995 : : * Pointer to the template HW steering DR actions.
996 : : */
997 : : static void
998 : 0 : __flow_hw_action_template_destroy(struct rte_eth_dev *dev, struct mlx5_hw_actions *acts)
999 : : {
1000 : 0 : __flow_hw_act_data_flush(dev, acts);
1001 : 0 : __flow_hw_actions_release(dev, acts);
1002 : 0 : }
1003 : :
1004 : : /**
1005 : : * Append dynamic action to the dynamic action list.
1006 : : *
1007 : : * @param[in] priv
1008 : : * Pointer to the port private data structure.
1009 : : * @param[in] acts
1010 : : * Pointer to the template HW steering DR actions.
1011 : : * @param[in] type
1012 : : * Action type.
1013 : : * @param[in] action_src
1014 : : * Offset of source rte flow action.
1015 : : * @param[in] action_dst
1016 : : * Offset of destination DR action.
1017 : : *
1018 : : * @return
1019 : : * 0 on success, negative value otherwise and rte_errno is set.
1020 : : */
1021 : : static __rte_always_inline struct mlx5_action_construct_data *
1022 : : __flow_hw_act_data_alloc(struct mlx5_priv *priv,
1023 : : enum rte_flow_action_type type,
1024 : : uint16_t action_src,
1025 : : uint16_t action_dst)
1026 : : {
1027 : : struct mlx5_action_construct_data *act_data;
1028 : 0 : uint32_t idx = 0;
1029 : :
1030 : 0 : act_data = mlx5_ipool_zmalloc(priv->acts_ipool, &idx);
1031 [ # # # # : 0 : if (!act_data)
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
1032 : : return NULL;
1033 : 0 : act_data->idx = idx;
1034 : 0 : act_data->type = type;
1035 : 0 : act_data->action_src = action_src;
1036 : 0 : act_data->action_dst = action_dst;
1037 : : return act_data;
1038 : : }
1039 : :
1040 : : /**
1041 : : * Append dynamic action to the dynamic action list.
1042 : : *
1043 : : * @param[in] priv
1044 : : * Pointer to the port private data structure.
1045 : : * @param[in] acts
1046 : : * Pointer to the template HW steering DR actions.
1047 : : * @param[in] type
1048 : : * Action type.
1049 : : * @param[in] action_src
1050 : : * Offset of source rte flow action.
1051 : : * @param[in] action_dst
1052 : : * Offset of destination DR action.
1053 : : *
1054 : : * @return
1055 : : * 0 on success, negative value otherwise and rte_errno is set.
1056 : : */
1057 : : static __rte_always_inline int
1058 : : __flow_hw_act_data_general_append(struct mlx5_priv *priv,
1059 : : struct mlx5_hw_actions *acts,
1060 : : enum rte_flow_action_type type,
1061 : : uint16_t action_src,
1062 : : uint16_t action_dst)
1063 : : {
1064 : : struct mlx5_action_construct_data *act_data;
1065 : :
1066 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1067 : : if (!act_data)
1068 : : return -1;
1069 [ # # # # : 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
1070 : : return 0;
1071 : : }
1072 : :
1073 : : static __rte_always_inline int
1074 : : __flow_hw_act_data_indirect_append(struct mlx5_priv *priv,
1075 : : struct mlx5_hw_actions *acts,
1076 : : enum rte_flow_action_type type,
1077 : : enum rte_flow_action_type mask_type,
1078 : : uint16_t action_src,
1079 : : uint16_t action_dst)
1080 : : {
1081 : : struct mlx5_action_construct_data *act_data;
1082 : :
1083 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1084 : : if (!act_data)
1085 : : return -1;
1086 : 0 : act_data->indirect.expected_type = mask_type;
1087 [ # # ]: 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
1088 : : return 0;
1089 : : }
1090 : :
1091 : : static __rte_always_inline int
1092 : : flow_hw_act_data_indirect_list_append(struct mlx5_priv *priv,
1093 : : struct mlx5_hw_actions *acts,
1094 : : enum rte_flow_action_type type,
1095 : : uint16_t action_src, uint16_t action_dst,
1096 : : indirect_list_callback_t cb)
1097 : : {
1098 : : struct mlx5_action_construct_data *act_data;
1099 : :
1100 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1101 : : if (!act_data)
1102 : 0 : return -1;
1103 : 0 : act_data->indirect_list_cb = cb;
1104 [ # # # # : 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
# # ]
1105 : 0 : return 0;
1106 : : }
1107 : : /**
1108 : : * Append dynamic encap action to the dynamic action list.
1109 : : *
1110 : : * @param[in] priv
1111 : : * Pointer to the port private data structure.
1112 : : * @param[in] acts
1113 : : * Pointer to the template HW steering DR actions.
1114 : : * @param[in] type
1115 : : * Action type.
1116 : : * @param[in] action_src
1117 : : * Offset of source rte flow action.
1118 : : * @param[in] action_dst
1119 : : * Offset of destination DR action.
1120 : : * @param[in] len
1121 : : * Length of the data to be updated.
1122 : : *
1123 : : * @return
1124 : : * 0 on success, negative value otherwise and rte_errno is set.
1125 : : */
1126 : : static __rte_always_inline int
1127 : : __flow_hw_act_data_encap_append(struct mlx5_priv *priv,
1128 : : struct mlx5_hw_actions *acts,
1129 : : enum rte_flow_action_type type,
1130 : : uint16_t action_src,
1131 : : uint16_t action_dst,
1132 : : uint16_t len)
1133 : : {
1134 : : struct mlx5_action_construct_data *act_data;
1135 : :
1136 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1137 : : if (!act_data)
1138 : : return -1;
1139 : 0 : act_data->encap.len = len;
1140 [ # # ]: 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
1141 : : return 0;
1142 : : }
1143 : :
1144 : : /**
1145 : : * Append dynamic push action to the dynamic action list.
1146 : : *
1147 : : * @param[in] dev
1148 : : * Pointer to the port.
1149 : : * @param[in] acts
1150 : : * Pointer to the template HW steering DR actions.
1151 : : * @param[in] type
1152 : : * Action type.
1153 : : * @param[in] action_src
1154 : : * Offset of source rte flow action.
1155 : : * @param[in] action_dst
1156 : : * Offset of destination DR action.
1157 : : * @param[in] len
1158 : : * Length of the data to be updated.
1159 : : *
1160 : : * @return
1161 : : * Data pointer on success, NULL otherwise and rte_errno is set.
1162 : : */
1163 : : static __rte_always_inline void *
1164 : : __flow_hw_act_data_push_append(struct rte_eth_dev *dev,
1165 : : struct mlx5_hw_actions *acts,
1166 : : enum rte_flow_action_type type,
1167 : : uint16_t action_src,
1168 : : uint16_t action_dst,
1169 : : uint16_t len)
1170 : : {
1171 : : struct mlx5_action_construct_data *act_data;
1172 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1173 : :
1174 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1175 : : if (!act_data)
1176 : : return NULL;
1177 : 0 : act_data->ipv6_ext.len = len;
1178 [ # # ]: 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
1179 : : return act_data;
1180 : : }
1181 : :
1182 : : static __rte_always_inline int
1183 : : __flow_hw_act_data_hdr_modify_append(struct mlx5_priv *priv,
1184 : : struct mlx5_hw_actions *acts,
1185 : : enum rte_flow_action_type type,
1186 : : uint16_t action_src,
1187 : : uint16_t action_dst,
1188 : : const struct rte_flow_action_modify_field *mf,
1189 : : uint16_t mhdr_cmds_off,
1190 : : uint16_t mhdr_cmds_end,
1191 : : bool shared,
1192 : : struct field_modify_info *field,
1193 : : struct field_modify_info *dcopy,
1194 : : uint32_t *mask)
1195 : : {
1196 : : struct mlx5_action_construct_data *act_data;
1197 : :
1198 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1199 : : if (!act_data)
1200 : : return -1;
1201 : 0 : act_data->modify_header.action = *mf;
1202 : 0 : act_data->modify_header.mhdr_cmds_off = mhdr_cmds_off;
1203 : 0 : act_data->modify_header.mhdr_cmds_end = mhdr_cmds_end;
1204 : 0 : act_data->modify_header.shared = shared;
1205 [ # # ]: 0 : rte_memcpy(act_data->modify_header.field, field,
1206 : : sizeof(*field) * MLX5_ACT_MAX_MOD_FIELDS);
1207 [ # # ]: 0 : rte_memcpy(act_data->modify_header.dcopy, dcopy,
1208 : : sizeof(*dcopy) * MLX5_ACT_MAX_MOD_FIELDS);
1209 [ # # ]: 0 : rte_memcpy(act_data->modify_header.mask, mask,
1210 : : sizeof(*mask) * MLX5_ACT_MAX_MOD_FIELDS);
1211 [ # # ]: 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
1212 : : return 0;
1213 : : }
1214 : :
1215 : : /**
1216 : : * Append shared RSS action to the dynamic action list.
1217 : : *
1218 : : * @param[in] priv
1219 : : * Pointer to the port private data structure.
1220 : : * @param[in] acts
1221 : : * Pointer to the template HW steering DR actions.
1222 : : * @param[in] type
1223 : : * Action type.
1224 : : * @param[in] action_src
1225 : : * Offset of source rte flow action.
1226 : : * @param[in] action_dst
1227 : : * Offset of destination DR action.
1228 : : * @param[in] idx
1229 : : * Shared RSS index.
1230 : : * @param[in] rss
1231 : : * Pointer to the shared RSS info.
1232 : : *
1233 : : * @return
1234 : : * 0 on success, negative value otherwise and rte_errno is set.
1235 : : */
1236 : : static __rte_always_inline int
1237 : : __flow_hw_act_data_shared_rss_append(struct mlx5_priv *priv,
1238 : : struct mlx5_hw_actions *acts,
1239 : : enum rte_flow_action_type type,
1240 : : uint16_t action_src,
1241 : : uint16_t action_dst,
1242 : : uint32_t idx,
1243 : : struct mlx5_shared_action_rss *rss)
1244 : : {
1245 : : struct mlx5_action_construct_data *act_data;
1246 : :
1247 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1248 : : if (!act_data)
1249 : : return -1;
1250 : 0 : act_data->shared_rss.level = rss->origin.level;
1251 [ # # ]: 0 : act_data->shared_rss.types = !rss->origin.types ? RTE_ETH_RSS_IP :
1252 : : rss->origin.types;
1253 : 0 : act_data->shared_rss.idx = idx;
1254 : 0 : act_data->shared_rss.symmetric_hash_function =
1255 : 0 : MLX5_RSS_IS_SYMM(rss->origin.func);
1256 [ # # ]: 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
1257 : : return 0;
1258 : : }
1259 : :
1260 : : /**
1261 : : * Append shared counter action to the dynamic action list.
1262 : : *
1263 : : * @param[in] priv
1264 : : * Pointer to the port private data structure.
1265 : : * @param[in] acts
1266 : : * Pointer to the template HW steering DR actions.
1267 : : * @param[in] type
1268 : : * Action type.
1269 : : * @param[in] action_src
1270 : : * Offset of source rte flow action.
1271 : : * @param[in] action_dst
1272 : : * Offset of destination DR action.
1273 : : * @param[in] cnt_id
1274 : : * Shared counter id.
1275 : : *
1276 : : * @return
1277 : : * 0 on success, negative value otherwise and rte_errno is set.
1278 : : */
1279 : : static __rte_always_inline int
1280 : : __flow_hw_act_data_shared_cnt_append(struct mlx5_priv *priv,
1281 : : struct mlx5_hw_actions *acts,
1282 : : enum rte_flow_action_type type,
1283 : : uint16_t action_src,
1284 : : uint16_t action_dst,
1285 : : cnt_id_t cnt_id)
1286 : : {
1287 : : struct mlx5_action_construct_data *act_data;
1288 : :
1289 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1290 : : if (!act_data)
1291 : : return -1;
1292 : : act_data->type = type;
1293 : 0 : act_data->shared_counter.id = cnt_id;
1294 [ # # ]: 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
1295 : : return 0;
1296 : : }
1297 : :
1298 : : /**
1299 : : * Append shared meter_mark action to the dynamic action list.
1300 : : *
1301 : : * @param[in] priv
1302 : : * Pointer to the port private data structure.
1303 : : * @param[in] acts
1304 : : * Pointer to the template HW steering DR actions.
1305 : : * @param[in] type
1306 : : * Action type.
1307 : : * @param[in] action_src
1308 : : * Offset of source rte flow action.
1309 : : * @param[in] action_dst
1310 : : * Offset of destination DR action.
1311 : : * @param[in] mtr_id
1312 : : * Shared meter id.
1313 : : *
1314 : : * @return
1315 : : * 0 on success, negative value otherwise and rte_errno is set.
1316 : : */
1317 : : static __rte_always_inline int
1318 : : __flow_hw_act_data_shared_mtr_append(struct mlx5_priv *priv,
1319 : : struct mlx5_hw_actions *acts,
1320 : : enum rte_flow_action_type type,
1321 : : uint16_t action_src,
1322 : : uint16_t action_dst,
1323 : : cnt_id_t mtr_id)
1324 : : { struct mlx5_action_construct_data *act_data;
1325 : :
1326 : : act_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);
1327 : : if (!act_data)
1328 : : return -1;
1329 : : act_data->type = type;
1330 : 0 : act_data->shared_meter.id = mtr_id;
1331 [ # # ]: 0 : LIST_INSERT_HEAD(&acts->act_list, act_data, next);
1332 : : return 0;
1333 : : }
1334 : :
1335 : : /**
1336 : : * Translate shared indirect action.
1337 : : *
1338 : : * @param[in] dev
1339 : : * Pointer to the rte_eth_dev data structure.
1340 : : * @param[in] action
1341 : : * Pointer to the shared indirect rte_flow action.
1342 : : * @param[in] acts
1343 : : * Pointer to the template HW steering DR actions.
1344 : : * @param[in] action_src
1345 : : * Offset of source rte flow action.
1346 : : * @param[in] action_dst
1347 : : * Offset of destination DR action.
1348 : : *
1349 : : * @return
1350 : : * 0 on success, negative value otherwise and rte_errno is set.
1351 : : */
1352 : : static __rte_always_inline int
1353 : : flow_hw_shared_action_translate(struct rte_eth_dev *dev,
1354 : : const struct rte_flow_action *action,
1355 : : struct mlx5_hw_actions *acts,
1356 : : uint16_t action_src,
1357 : : uint16_t action_dst)
1358 : : {
1359 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1360 : : struct mlx5_shared_action_rss *shared_rss;
1361 : 0 : uint32_t act_idx = (uint32_t)(uintptr_t)action->conf;
1362 : 0 : uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
1363 : 0 : uint32_t idx = act_idx &
1364 : : ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
1365 : :
1366 : 0 : switch (type) {
1367 : 0 : case MLX5_INDIRECT_ACTION_TYPE_RSS:
1368 : 0 : shared_rss = mlx5_ipool_get
1369 : 0 : (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
1370 [ # # ]: 0 : if (!shared_rss || __flow_hw_act_data_shared_rss_append
1371 : : (priv, acts,
1372 : : (enum rte_flow_action_type)MLX5_RTE_FLOW_ACTION_TYPE_RSS,
1373 : : action_src, action_dst, idx, shared_rss)) {
1374 : 0 : DRV_LOG(WARNING, "Indirect RSS action index %d translate failed", act_idx);
1375 : : return -1;
1376 : : }
1377 : : break;
1378 : 0 : case MLX5_INDIRECT_ACTION_TYPE_COUNT:
1379 : : if (__flow_hw_act_data_shared_cnt_append(priv, acts,
1380 : : (enum rte_flow_action_type)
1381 : : MLX5_RTE_FLOW_ACTION_TYPE_COUNT,
1382 : : action_src, action_dst, act_idx)) {
1383 : 0 : DRV_LOG(WARNING, "Indirect count action translate failed");
1384 : : return -1;
1385 : : }
1386 : : break;
1387 : : case MLX5_INDIRECT_ACTION_TYPE_AGE:
1388 : : /* Not supported, prevent by validate function. */
1389 : : MLX5_ASSERT(0);
1390 : : break;
1391 : 0 : case MLX5_INDIRECT_ACTION_TYPE_CT:
1392 : : if (flow_hw_ct_compile(dev, MLX5_HW_INV_QUEUE,
1393 : : idx, &acts->rule_acts[action_dst])) {
1394 : 0 : DRV_LOG(WARNING, "Indirect CT action translate failed");
1395 : : return -1;
1396 : : }
1397 : : break;
1398 : 0 : case MLX5_INDIRECT_ACTION_TYPE_METER_MARK:
1399 : : if (__flow_hw_act_data_shared_mtr_append(priv, acts,
1400 : : (enum rte_flow_action_type)
1401 : : MLX5_RTE_FLOW_ACTION_TYPE_METER_MARK,
1402 : : action_src, action_dst, idx)) {
1403 : 0 : DRV_LOG(WARNING, "Indirect meter mark action translate failed");
1404 : : return -1;
1405 : : }
1406 : : break;
1407 : 0 : case MLX5_INDIRECT_ACTION_TYPE_QUOTA:
1408 : : flow_hw_construct_quota(priv, &acts->rule_acts[action_dst], idx);
1409 : : break;
1410 : 0 : default:
1411 : 0 : DRV_LOG(WARNING, "Unsupported shared action type:%d", type);
1412 : : break;
1413 : : }
1414 : : return 0;
1415 : : }
1416 : :
1417 : : static __rte_always_inline bool
1418 : : flow_hw_action_modify_field_is_shared(const struct rte_flow_action *action,
1419 : : const struct rte_flow_action *mask)
1420 : : {
1421 : : const struct rte_flow_action_modify_field *v = action->conf;
1422 : 0 : const struct rte_flow_action_modify_field *m = mask->conf;
1423 : :
1424 : 0 : if (v->src.field == RTE_FLOW_FIELD_VALUE) {
1425 : : uint32_t j;
1426 : :
1427 [ # # ]: 0 : for (j = 0; j < RTE_DIM(m->src.value); ++j) {
1428 : : /*
1429 : : * Immediate value is considered to be masked
1430 : : * (and thus shared by all flow rules), if mask
1431 : : * is non-zero. Partial mask over immediate value
1432 : : * is not allowed.
1433 : : */
1434 [ # # ]: 0 : if (m->src.value[j])
1435 : : return true;
1436 : : }
1437 : : return false;
1438 : : }
1439 [ # # ]: 0 : if (v->src.field == RTE_FLOW_FIELD_POINTER)
1440 : 0 : return m->src.pvalue != NULL;
1441 : : /*
1442 : : * Source field types other than VALUE and
1443 : : * POINTER are always shared.
1444 : : */
1445 : : return true;
1446 : : }
1447 : :
1448 : : static __rte_always_inline bool
1449 : : flow_hw_should_insert_nop(const struct mlx5_hw_modify_header_action *mhdr,
1450 : : const struct mlx5_modification_cmd *cmd)
1451 : : {
1452 : : struct mlx5_modification_cmd last_cmd = { { 0 } };
1453 : : struct mlx5_modification_cmd new_cmd = { { 0 } };
1454 : 0 : const uint32_t cmds_num = mhdr->mhdr_cmds_num;
1455 : : unsigned int last_type;
1456 : : bool should_insert = false;
1457 : :
1458 [ # # # # ]: 0 : if (cmds_num == 0)
1459 : : return false;
1460 : 0 : last_cmd = *(&mhdr->mhdr_cmds[cmds_num - 1]);
1461 [ # # # # ]: 0 : last_cmd.data0 = rte_be_to_cpu_32(last_cmd.data0);
1462 [ # # # # ]: 0 : last_cmd.data1 = rte_be_to_cpu_32(last_cmd.data1);
1463 : 0 : last_type = last_cmd.action_type;
1464 : 0 : new_cmd = *cmd;
1465 [ # # # # ]: 0 : new_cmd.data0 = rte_be_to_cpu_32(new_cmd.data0);
1466 [ # # # # ]: 0 : new_cmd.data1 = rte_be_to_cpu_32(new_cmd.data1);
1467 [ # # # # : 0 : switch (new_cmd.action_type) {
# # ]
1468 : 0 : case MLX5_MODIFICATION_TYPE_SET:
1469 : : case MLX5_MODIFICATION_TYPE_ADD:
1470 [ # # # # ]: 0 : if (last_type == MLX5_MODIFICATION_TYPE_SET ||
1471 : : last_type == MLX5_MODIFICATION_TYPE_ADD)
1472 : 0 : should_insert = new_cmd.field == last_cmd.field;
1473 : 0 : else if (last_type == MLX5_MODIFICATION_TYPE_COPY ||
1474 [ # # # # ]: 0 : last_type == MLX5_MODIFICATION_TYPE_ADD_FIELD)
1475 : 0 : should_insert = new_cmd.field == last_cmd.dst_field;
1476 : : else if (last_type == MLX5_MODIFICATION_TYPE_NOP)
1477 : : should_insert = false;
1478 : : else
1479 : : MLX5_ASSERT(false); /* Other types are not supported. */
1480 : : break;
1481 : 0 : case MLX5_MODIFICATION_TYPE_COPY:
1482 : : case MLX5_MODIFICATION_TYPE_ADD_FIELD:
1483 [ # # # # ]: 0 : if (last_type == MLX5_MODIFICATION_TYPE_SET ||
1484 : : last_type == MLX5_MODIFICATION_TYPE_ADD)
1485 [ # # # # ]: 0 : should_insert = (new_cmd.field == last_cmd.field ||
1486 [ # # # # ]: 0 : new_cmd.dst_field == last_cmd.field);
1487 : 0 : else if (last_type == MLX5_MODIFICATION_TYPE_COPY ||
1488 [ # # # # ]: 0 : last_type == MLX5_MODIFICATION_TYPE_ADD_FIELD)
1489 [ # # # # ]: 0 : should_insert = (new_cmd.field == last_cmd.dst_field ||
1490 [ # # # # ]: 0 : new_cmd.dst_field == last_cmd.dst_field);
1491 : : else if (last_type == MLX5_MODIFICATION_TYPE_NOP)
1492 : : should_insert = false;
1493 : : else
1494 : : MLX5_ASSERT(false); /* Other types are not supported. */
1495 : : break;
1496 : : default:
1497 : : /* Other action types should be rejected on AT validation. */
1498 : : MLX5_ASSERT(false);
1499 : : break;
1500 : : }
1501 : : return should_insert;
1502 : : }
1503 : :
1504 : : static __rte_always_inline int
1505 : : flow_hw_mhdr_cmd_nop_append(struct mlx5_hw_modify_header_action *mhdr)
1506 : : {
1507 : : struct mlx5_modification_cmd *nop;
1508 : : uint32_t num = mhdr->mhdr_cmds_num;
1509 : :
1510 [ # # # # ]: 0 : if (num + 1 >= MLX5_MHDR_MAX_CMD)
1511 : : return -ENOMEM;
1512 : 0 : nop = mhdr->mhdr_cmds + num;
1513 : : nop->data0 = 0;
1514 : : nop->action_type = MLX5_MODIFICATION_TYPE_NOP;
1515 : 0 : nop->data0 = rte_cpu_to_be_32(nop->data0);
1516 : 0 : nop->data1 = 0;
1517 : 0 : mhdr->mhdr_cmds_num = num + 1;
1518 : : return 0;
1519 : : }
1520 : :
1521 : : static __rte_always_inline int
1522 : : flow_hw_mhdr_cmd_append(struct mlx5_hw_modify_header_action *mhdr,
1523 : : struct mlx5_modification_cmd *cmd)
1524 : : {
1525 : 0 : uint32_t num = mhdr->mhdr_cmds_num;
1526 : :
1527 [ # # ]: 0 : if (num + 1 >= MLX5_MHDR_MAX_CMD)
1528 : : return -ENOMEM;
1529 : 0 : mhdr->mhdr_cmds[num] = *cmd;
1530 : 0 : mhdr->mhdr_cmds_num = num + 1;
1531 : : return 0;
1532 : : }
1533 : :
1534 : : static __rte_always_inline int
1535 : : flow_hw_converted_mhdr_cmds_append(struct mlx5_hw_modify_header_action *mhdr,
1536 : : struct mlx5_flow_dv_modify_hdr_resource *resource)
1537 : : {
1538 : : uint32_t idx;
1539 : : int ret;
1540 : :
1541 [ # # ]: 0 : for (idx = 0; idx < resource->actions_num; ++idx) {
1542 : : struct mlx5_modification_cmd *src = &resource->actions[idx];
1543 : :
1544 [ # # ]: 0 : if (flow_hw_should_insert_nop(mhdr, src)) {
1545 : : ret = flow_hw_mhdr_cmd_nop_append(mhdr);
1546 : : if (ret)
1547 : : return ret;
1548 : : }
1549 : : ret = flow_hw_mhdr_cmd_append(mhdr, src);
1550 : : if (ret)
1551 : : return ret;
1552 : : }
1553 : : return 0;
1554 : : }
1555 : :
1556 : : static __rte_always_inline void
1557 : : flow_hw_modify_field_init(struct mlx5_hw_modify_header_action *mhdr,
1558 : : struct rte_flow_actions_template *at)
1559 : : {
1560 : : memset(mhdr, 0, sizeof(*mhdr));
1561 : : /* Modify header action without any commands is shared by default. */
1562 : 0 : mhdr->shared = true;
1563 : 0 : mhdr->pos = at->mhdr_off;
1564 : : }
1565 : :
1566 : : static __rte_always_inline int
1567 : : flow_hw_modify_field_compile(struct rte_eth_dev *dev,
1568 : : const struct rte_flow_attr *attr,
1569 : : const struct rte_flow_action *action, /* Current action from AT. */
1570 : : const struct rte_flow_action *action_mask, /* Current mask from AT. */
1571 : : struct mlx5_hw_actions *acts,
1572 : : struct mlx5_hw_modify_header_action *mhdr,
1573 : : uint16_t src_pos,
1574 : : struct rte_flow_error *error)
1575 : : {
1576 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1577 : 0 : const struct rte_flow_action_modify_field *conf = action->conf;
1578 : : union {
1579 : : struct mlx5_flow_dv_modify_hdr_resource resource;
1580 : : uint8_t data[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
1581 : : sizeof(struct mlx5_modification_cmd) * MLX5_MHDR_MAX_CMD];
1582 : : } dummy;
1583 : : struct mlx5_flow_dv_modify_hdr_resource *resource;
1584 : 0 : struct rte_flow_item item = {
1585 : : .spec = NULL,
1586 : : .mask = NULL
1587 : : };
1588 : 0 : struct field_modify_info field[MLX5_ACT_MAX_MOD_FIELDS] = {
1589 : : {0, 0, MLX5_MODI_OUT_NONE} };
1590 : 0 : struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {
1591 : : {0, 0, MLX5_MODI_OUT_NONE} };
1592 : 0 : uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = { 0 };
1593 : 0 : uint32_t type, value = 0;
1594 : : uint16_t cmds_start, cmds_end;
1595 : : bool shared;
1596 : : int ret;
1597 : :
1598 : : /*
1599 : : * Modify header action is shared if previous modify_field actions
1600 : : * are shared and currently compiled action is shared.
1601 : : */
1602 : : shared = flow_hw_action_modify_field_is_shared(action, action_mask);
1603 : 0 : mhdr->shared &= shared;
1604 [ # # ]: 0 : if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
1605 : : conf->src.field == RTE_FLOW_FIELD_VALUE) {
1606 [ # # ]: 0 : type = conf->operation == RTE_FLOW_MODIFY_SET ? MLX5_MODIFICATION_TYPE_SET :
1607 : : MLX5_MODIFICATION_TYPE_ADD;
1608 : : /* For SET/ADD fill the destination field (field) first. */
1609 : 0 : mlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,
1610 : 0 : conf->width, dev,
1611 : : attr, error);
1612 : 0 : item.spec = conf->src.field == RTE_FLOW_FIELD_POINTER ?
1613 [ # # ]: 0 : (void *)(uintptr_t)conf->src.pvalue :
1614 : : (void *)(uintptr_t)&conf->src.value;
1615 [ # # ]: 0 : if (conf->dst.field == RTE_FLOW_FIELD_META ||
1616 [ # # ]: 0 : conf->dst.field == RTE_FLOW_FIELD_TAG ||
1617 [ # # ]: 0 : conf->dst.field == RTE_FLOW_FIELD_METER_COLOR ||
1618 : 0 : conf->dst.field == (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG) {
1619 : : uint8_t tag_index = flow_tag_index_get(&conf->dst);
1620 : :
1621 : 0 : value = *(const unaligned_uint32_t *)item.spec;
1622 [ # # # # ]: 0 : if (conf->dst.field == RTE_FLOW_FIELD_TAG &&
1623 : : tag_index == RTE_PMD_MLX5_LINEAR_HASH_TAG_INDEX)
1624 [ # # ]: 0 : value = rte_cpu_to_be_32(value << 16);
1625 : : else
1626 [ # # ]: 0 : value = rte_cpu_to_be_32(value);
1627 : 0 : item.spec = &value;
1628 [ # # ]: 0 : } else if (conf->dst.field == RTE_FLOW_FIELD_GTP_PSC_QFI ||
1629 : : conf->dst.field == RTE_FLOW_FIELD_GENEVE_OPT_TYPE) {
1630 : : /*
1631 : : * Both QFI and Geneve option type are passed as an uint8_t integer,
1632 : : * but it is accessed through a 2nd least significant byte of a 32-bit
1633 : : * field in modify header command.
1634 : : */
1635 : 0 : value = *(const uint8_t *)item.spec;
1636 [ # # ]: 0 : value = rte_cpu_to_be_32(value << 8);
1637 : 0 : item.spec = &value;
1638 [ # # ]: 0 : } else if (conf->dst.field == RTE_FLOW_FIELD_VXLAN_LAST_RSVD) {
1639 : 0 : value = *(const uint8_t *)item.spec << 24;
1640 [ # # ]: 0 : value = rte_cpu_to_be_32(value);
1641 : 0 : item.spec = &value;
1642 : : }
1643 : : } else {
1644 : 0 : type = conf->operation == RTE_FLOW_MODIFY_SET ?
1645 [ # # ]: 0 : MLX5_MODIFICATION_TYPE_COPY : MLX5_MODIFICATION_TYPE_ADD_FIELD;
1646 : : /* For COPY fill the destination field (dcopy) without mask. */
1647 : 0 : mlx5_flow_field_id_to_modify_info(&conf->dst, dcopy, NULL,
1648 : 0 : conf->width, dev,
1649 : : attr, error);
1650 : : /* Then construct the source field (field) with mask. */
1651 : 0 : mlx5_flow_field_id_to_modify_info(&conf->src, field, mask,
1652 : 0 : conf->width, dev,
1653 : : attr, error);
1654 : : }
1655 : 0 : item.mask = &mask;
1656 : : memset(&dummy, 0, sizeof(dummy));
1657 : : resource = &dummy.resource;
1658 : 0 : ret = flow_dv_convert_modify_action(&item, field, dcopy, resource, type, error);
1659 [ # # ]: 0 : if (ret)
1660 : : return ret;
1661 : : MLX5_ASSERT(resource->actions_num > 0);
1662 : : /*
1663 : : * If previous modify field action collide with this one, then insert NOP command.
1664 : : * This NOP command will not be a part of action's command range used to update commands
1665 : : * on rule creation.
1666 : : */
1667 [ # # ]: 0 : if (flow_hw_should_insert_nop(mhdr, &resource->actions[0])) {
1668 : : ret = flow_hw_mhdr_cmd_nop_append(mhdr);
1669 : : if (ret)
1670 : 0 : return rte_flow_error_set(error, ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1671 : : NULL, "too many modify field operations specified");
1672 : : }
1673 : 0 : cmds_start = mhdr->mhdr_cmds_num;
1674 : : ret = flow_hw_converted_mhdr_cmds_append(mhdr, resource);
1675 [ # # ]: 0 : if (ret)
1676 : 0 : return rte_flow_error_set(error, ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1677 : : NULL, "too many modify field operations specified");
1678 : :
1679 : 0 : cmds_end = mhdr->mhdr_cmds_num;
1680 [ # # ]: 0 : if (shared)
1681 : : return 0;
1682 : : ret = __flow_hw_act_data_hdr_modify_append(priv, acts, RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
1683 : 0 : src_pos, mhdr->pos, conf,
1684 : : cmds_start, cmds_end, shared,
1685 : : field, dcopy, mask);
1686 : : if (ret)
1687 : 0 : return rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1688 : : NULL, "not enough memory to store modify field metadata");
1689 : : return 0;
1690 : : }
1691 : :
1692 : : static uint32_t
1693 : 0 : flow_hw_count_nop_modify_field(struct mlx5_hw_modify_header_action *mhdr)
1694 : : {
1695 : : uint32_t i;
1696 : : uint32_t nops = 0;
1697 : :
1698 [ # # ]: 0 : for (i = 0; i < mhdr->mhdr_cmds_num; ++i) {
1699 : 0 : struct mlx5_modification_cmd cmd = mhdr->mhdr_cmds[i];
1700 : :
1701 [ # # ]: 0 : cmd.data0 = rte_be_to_cpu_32(cmd.data0);
1702 [ # # ]: 0 : if (cmd.action_type == MLX5_MODIFICATION_TYPE_NOP)
1703 : 0 : ++nops;
1704 : : }
1705 : 0 : return nops;
1706 : : }
1707 : :
1708 : : static int
1709 : 0 : flow_hw_validate_compiled_modify_field(struct rte_eth_dev *dev,
1710 : : const struct mlx5_flow_template_table_cfg *cfg,
1711 : : struct mlx5_hw_modify_header_action *mhdr,
1712 : : struct rte_flow_error *error)
1713 : : {
1714 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1715 : 0 : struct mlx5_hca_attr *hca_attr = &priv->sh->cdev->config.hca_attr;
1716 : :
1717 : : /*
1718 : : * Header modify pattern length limitation is only valid for HWS groups, i.e. groups > 0.
1719 : : * In group 0, MODIFY_FIELD actions are handled with header modify actions
1720 : : * managed by rdma-core.
1721 : : */
1722 [ # # ]: 0 : if (cfg->attr.flow_attr.group != 0 &&
1723 [ # # ]: 0 : mhdr->mhdr_cmds_num > hca_attr->max_header_modify_pattern_length) {
1724 : 0 : uint32_t nops = flow_hw_count_nop_modify_field(mhdr);
1725 : :
1726 : 0 : DRV_LOG(ERR, "Too many modify header commands generated from "
1727 : : "MODIFY_FIELD actions. "
1728 : : "Generated HW commands = %u (amount of NOP commands = %u). "
1729 : : "Maximum supported = %u.",
1730 : : mhdr->mhdr_cmds_num, nops,
1731 : : hca_attr->max_header_modify_pattern_length);
1732 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1733 : : "Number of MODIFY_FIELD actions exceeds maximum "
1734 : : "supported limit of actions");
1735 : : }
1736 : : return 0;
1737 : : }
1738 : :
1739 : : static int
1740 : 0 : flow_hw_represented_port_compile(struct rte_eth_dev *dev,
1741 : : const struct rte_flow_attr *attr,
1742 : : const struct rte_flow_action *action,
1743 : : const struct rte_flow_action *action_mask,
1744 : : struct mlx5_hw_actions *acts,
1745 : : uint16_t action_src, uint16_t action_dst,
1746 : : struct rte_flow_error *error)
1747 : : {
1748 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1749 : 0 : const struct rte_flow_action_ethdev *v = action->conf;
1750 : 0 : const struct rte_flow_action_ethdev *m = action_mask->conf;
1751 : : int ret;
1752 : :
1753 [ # # ]: 0 : if (!attr->group)
1754 : 0 : return rte_flow_error_set(error, EINVAL,
1755 : : RTE_FLOW_ERROR_TYPE_ATTR, NULL,
1756 : : "represented_port action cannot"
1757 : : " be used on group 0");
1758 [ # # ]: 0 : if (!attr->transfer)
1759 : 0 : return rte_flow_error_set(error, EINVAL,
1760 : : RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER,
1761 : : NULL,
1762 : : "represented_port action requires"
1763 : : " transfer attribute");
1764 [ # # ]: 0 : if (attr->ingress || attr->egress)
1765 : 0 : return rte_flow_error_set(error, EINVAL,
1766 : : RTE_FLOW_ERROR_TYPE_ATTR, NULL,
1767 : : "represented_port action cannot"
1768 : : " be used with direction attributes");
1769 [ # # ]: 0 : if (!priv->master)
1770 : 0 : return rte_flow_error_set(error, EINVAL,
1771 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1772 : : "represented_port action must"
1773 : : " be used on proxy port");
1774 [ # # # # ]: 0 : if (m && !!m->port_id) {
1775 : : struct mlx5_priv *port_priv;
1776 : :
1777 [ # # ]: 0 : if (!v)
1778 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
1779 : : action, "port index was not provided");
1780 : 0 : port_priv = mlx5_port_to_eswitch_info(v->port_id, false);
1781 [ # # ]: 0 : if (port_priv == NULL)
1782 : 0 : return rte_flow_error_set
1783 : : (error, EINVAL,
1784 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1785 : : "port does not exist or unable to"
1786 : : " obtain E-Switch info for port");
1787 : : MLX5_ASSERT(priv->hw_vport != NULL);
1788 [ # # ]: 0 : if (priv->hw_vport[v->port_id]) {
1789 : 0 : acts->rule_acts[action_dst].action =
1790 : : priv->hw_vport[v->port_id];
1791 : : } else {
1792 : 0 : return rte_flow_error_set
1793 : : (error, EINVAL,
1794 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1795 : : "cannot use represented_port action"
1796 : : " with this port");
1797 : : }
1798 : : } else {
1799 : : ret = __flow_hw_act_data_general_append
1800 : 0 : (priv, acts, action->type,
1801 : : action_src, action_dst);
1802 : : if (ret)
1803 : 0 : return rte_flow_error_set
1804 : : (error, ENOMEM,
1805 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1806 : : "not enough memory to store"
1807 : : " vport action");
1808 : : }
1809 : : return 0;
1810 : : }
1811 : :
1812 : : static __rte_always_inline int
1813 : : flow_hw_meter_compile(struct rte_eth_dev *dev,
1814 : : const struct mlx5_flow_template_table_cfg *cfg,
1815 : : uint16_t aso_mtr_pos,
1816 : : uint16_t jump_pos,
1817 : : const struct rte_flow_action *action,
1818 : : struct mlx5_hw_actions *acts,
1819 : : struct rte_flow_error *error)
1820 : : {
1821 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1822 : : struct mlx5_aso_mtr *aso_mtr;
1823 : : const struct rte_flow_action_meter *meter = action->conf;
1824 : 0 : uint32_t group = cfg->attr.flow_attr.group;
1825 : :
1826 : 0 : aso_mtr = mlx5_aso_meter_by_idx(priv, meter->mtr_id);
1827 : 0 : acts->rule_acts[aso_mtr_pos].action = priv->mtr_bulk.action;
1828 : 0 : acts->rule_acts[aso_mtr_pos].aso_meter.offset = aso_mtr->offset;
1829 : 0 : acts->jump = flow_hw_jump_action_register
1830 : 0 : (dev, cfg, aso_mtr->fm.group, error);
1831 [ # # ]: 0 : if (!acts->jump)
1832 : : return -ENOMEM;
1833 : 0 : acts->rule_acts[jump_pos].action = (!!group) ?
1834 [ # # ]: 0 : acts->jump->hws_action :
1835 : : acts->jump->root_action;
1836 [ # # ]: 0 : if (mlx5_aso_mtr_wait(priv, aso_mtr, true))
1837 : : return -ENOMEM;
1838 : : return 0;
1839 : : }
1840 : :
1841 : : static __rte_always_inline int
1842 : : flow_hw_cnt_compile(struct rte_eth_dev *dev, uint32_t start_pos,
1843 : : struct mlx5_hw_actions *acts)
1844 : : {
1845 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1846 : : uint32_t pos = start_pos;
1847 : : cnt_id_t cnt_id;
1848 : : int ret;
1849 : :
1850 : 0 : ret = mlx5_hws_cnt_shared_get(priv->hws_cpool, &cnt_id, 0);
1851 : : if (ret != 0)
1852 : : return ret;
1853 : 0 : ret = mlx5_hws_cnt_pool_get_action_offset
1854 : : (priv->hws_cpool,
1855 : : cnt_id,
1856 : : &acts->rule_acts[pos].action,
1857 : : &acts->rule_acts[pos].counter.offset);
1858 : : if (ret != 0)
1859 : : return ret;
1860 : 0 : acts->cnt_id = cnt_id;
1861 : : return 0;
1862 : : }
1863 : :
1864 : : static __rte_always_inline bool
1865 : : is_of_vlan_pcp_present(const struct rte_flow_action *actions)
1866 : : {
1867 : : /*
1868 : : * Order of RTE VLAN push actions is
1869 : : * OF_PUSH_VLAN / OF_SET_VLAN_VID [ / OF_SET_VLAN_PCP ]
1870 : : */
1871 : 0 : return actions[MLX5_HW_VLAN_PUSH_PCP_IDX].type ==
1872 : : RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP;
1873 : : }
1874 : :
1875 : : static __rte_always_inline bool
1876 : : is_template_masked_push_vlan(const struct rte_flow_action_of_push_vlan *mask)
1877 : : {
1878 : : /*
1879 : : * In masked push VLAN template all RTE push actions are masked.
1880 : : */
1881 [ # # ]: 0 : return mask && mask->ethertype != 0;
1882 : : }
1883 : :
1884 : 0 : static rte_be32_t vlan_hdr_to_be32(const struct rte_flow_action *actions)
1885 : : {
1886 : : /*
1887 : : * OpenFlow Switch Specification defines 801.1q VID as 12+1 bits.
1888 : : */
1889 : : rte_be32_t type, vid, pcp;
1890 : : #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
1891 : : rte_be32_t vid_lo, vid_hi;
1892 : : #endif
1893 : :
1894 : 0 : type = ((const struct rte_flow_action_of_push_vlan *)
1895 : 0 : actions[MLX5_HW_VLAN_PUSH_TYPE_IDX].conf)->ethertype;
1896 : 0 : vid = ((const struct rte_flow_action_of_set_vlan_vid *)
1897 : 0 : actions[MLX5_HW_VLAN_PUSH_VID_IDX].conf)->vlan_vid;
1898 : : pcp = is_of_vlan_pcp_present(actions) ?
1899 : : ((const struct rte_flow_action_of_set_vlan_pcp *)
1900 [ # # # # ]: 0 : actions[MLX5_HW_VLAN_PUSH_PCP_IDX].conf)->vlan_pcp : 0;
1901 : : #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
1902 : 0 : vid_hi = vid & 0xff;
1903 : : vid_lo = vid >> 8;
1904 : 0 : return (((vid_lo << 8) | (pcp << 5) | vid_hi) << 16) | type;
1905 : : #else
1906 : : return (type << 16) | (pcp << 13) | vid;
1907 : : #endif
1908 : : }
1909 : :
1910 : : static __rte_always_inline struct mlx5_aso_mtr *
1911 : : flow_hw_meter_mark_alloc(struct rte_eth_dev *dev, uint32_t queue,
1912 : : const struct rte_flow_action *action,
1913 : : struct mlx5_hw_q_job *job, bool push,
1914 : : struct rte_flow_error *error)
1915 : : {
1916 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1917 : 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
1918 : 0 : const struct rte_flow_action_meter_mark *meter_mark = action->conf;
1919 : : struct mlx5_aso_mtr *aso_mtr;
1920 : : struct mlx5_flow_meter_info *fm;
1921 : 0 : uint32_t mtr_id = 0;
1922 : : uintptr_t handle = (uintptr_t)MLX5_INDIRECT_ACTION_TYPE_METER_MARK <<
1923 : : MLX5_INDIRECT_ACTION_TYPE_OFFSET;
1924 : :
1925 : 0 : if (priv->shared_host) {
1926 : 0 : rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1927 : : "Meter mark actions can only be created on the host port");
1928 : : return NULL;
1929 : : }
1930 [ # # # # : 0 : if (meter_mark->profile == NULL)
# # # # #
# # # #
# ]
1931 : : return NULL;
1932 : 0 : aso_mtr = mlx5_ipool_malloc(pool->idx_pool, &mtr_id);
1933 [ # # # # : 0 : if (!aso_mtr) {
# # # # #
# # # #
# ]
1934 : 0 : rte_flow_error_set(error, ENOMEM,
1935 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1936 : : NULL,
1937 : : "failed to allocate aso meter entry");
1938 [ # # # # : 0 : if (mtr_id)
# # # # #
# # # #
# ]
1939 : 0 : mlx5_ipool_free(pool->idx_pool, mtr_id);
1940 : : return NULL;
1941 : : }
1942 : : /* Fill the flow meter parameters. */
1943 : 0 : aso_mtr->type = ASO_METER_INDIRECT;
1944 : : fm = &aso_mtr->fm;
1945 : 0 : fm->meter_id = mtr_id;
1946 : 0 : fm->profile = (struct mlx5_flow_meter_profile *)(meter_mark->profile);
1947 : 0 : fm->is_enable = meter_mark->state;
1948 : 0 : fm->color_aware = meter_mark->color_mode;
1949 : 0 : aso_mtr->pool = pool;
1950 [ # # ]: 0 : aso_mtr->state = (queue == MLX5_HW_INV_QUEUE) ?
1951 : : ASO_METER_WAIT : ASO_METER_WAIT_ASYNC;
1952 : 0 : aso_mtr->offset = mtr_id - 1;
1953 [ # # # # : 0 : aso_mtr->init_color = fm->color_aware ? RTE_COLORS : RTE_COLOR_GREEN;
# # # # #
# # # #
# ]
1954 : 0 : job->action = (void *)(handle | mtr_id);
1955 : : /* Update ASO flow meter by wqe. */
1956 [ # # # # : 0 : if (mlx5_aso_meter_update_by_wqe(priv, queue, aso_mtr,
# # # # #
# # # #
# ]
1957 : : &priv->mtr_bulk, job, push)) {
1958 : 0 : mlx5_ipool_free(pool->idx_pool, mtr_id);
1959 : : return NULL;
1960 : : }
1961 : : /* Wait for ASO object completion. */
1962 [ # # # # : 0 : if (queue == MLX5_HW_INV_QUEUE &&
# # # # #
# # # # #
# # ]
1963 : 0 : mlx5_aso_mtr_wait(priv, aso_mtr, true)) {
1964 : 0 : mlx5_ipool_free(pool->idx_pool, mtr_id);
1965 : : return NULL;
1966 : : }
1967 : : return aso_mtr;
1968 : : }
1969 : :
1970 : : static __rte_always_inline int
1971 : : flow_hw_meter_mark_compile(struct rte_eth_dev *dev,
1972 : : uint16_t aso_mtr_pos,
1973 : : const struct rte_flow_action *action,
1974 : : struct mlx5dr_rule_action *acts,
1975 : : uint32_t *index,
1976 : : uint32_t queue,
1977 : : struct rte_flow_error *error)
1978 : : {
1979 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
1980 : 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
1981 : : struct mlx5_aso_mtr *aso_mtr;
1982 : : struct mlx5_hw_q_job *job =
1983 : : flow_hw_action_job_init(priv, queue, NULL, NULL, NULL,
1984 : : MLX5_HW_Q_JOB_TYPE_CREATE,
1985 : : MLX5_HW_INDIRECT_TYPE_LEGACY, NULL);
1986 : :
1987 : : if (!job)
1988 : : return -1;
1989 : : aso_mtr = flow_hw_meter_mark_alloc(dev, queue, action, job,
1990 : : true, error);
1991 : : if (!aso_mtr) {
1992 : : flow_hw_job_put(priv, job, queue);
1993 : : return -1;
1994 : : }
1995 : :
1996 : : /* Compile METER_MARK action */
1997 : 0 : acts[aso_mtr_pos].action = pool->action;
1998 : 0 : acts[aso_mtr_pos].aso_meter.offset = aso_mtr->offset;
1999 : 0 : *index = aso_mtr->fm.meter_id;
2000 : : return 0;
2001 : : }
2002 : :
2003 : : static int
2004 : 0 : flow_hw_translate_indirect_mirror(__rte_unused struct rte_eth_dev *dev,
2005 : : __rte_unused const struct mlx5_action_construct_data *act_data,
2006 : : const struct rte_flow_action *action,
2007 : : struct mlx5dr_rule_action *dr_rule)
2008 : : {
2009 : 0 : const struct rte_flow_action_indirect_list *list_conf = action->conf;
2010 : 0 : const struct mlx5_mirror *mirror = (typeof(mirror))list_conf->handle;
2011 : :
2012 : 0 : dr_rule->action = mirror->mirror_action;
2013 : 0 : return 0;
2014 : : }
2015 : :
2016 : : /**
2017 : : * HWS mirror implemented as FW island.
2018 : : * The action does not support indirect list flow configuration.
2019 : : * If template handle was masked, use handle mirror action in flow rules.
2020 : : * Otherwise let flow rule specify mirror handle.
2021 : : */
2022 : : static int
2023 : 0 : hws_table_tmpl_translate_indirect_mirror(struct rte_eth_dev *dev,
2024 : : const struct rte_flow_action *action,
2025 : : const struct rte_flow_action *mask,
2026 : : struct mlx5_hw_actions *acts,
2027 : : uint16_t action_src, uint16_t action_dst)
2028 : : {
2029 : : int ret = 0;
2030 : 0 : const struct rte_flow_action_indirect_list *mask_conf = mask->conf;
2031 : :
2032 [ # # # # ]: 0 : if (mask_conf && mask_conf->handle) {
2033 : : /**
2034 : : * If mirror handle was masked, assign fixed DR5 mirror action.
2035 : : */
2036 : : flow_hw_translate_indirect_mirror(dev, NULL, action,
2037 : 0 : &acts->rule_acts[action_dst]);
2038 : : } else {
2039 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
2040 : : ret = flow_hw_act_data_indirect_list_append
2041 : : (priv, acts, RTE_FLOW_ACTION_TYPE_INDIRECT_LIST,
2042 : : action_src, action_dst,
2043 : : flow_hw_translate_indirect_mirror);
2044 : : }
2045 : 0 : return ret;
2046 : : }
2047 : :
2048 : : static int
2049 : 0 : flow_hw_reformat_action(__rte_unused struct rte_eth_dev *dev,
2050 : : __rte_unused const struct mlx5_action_construct_data *data,
2051 : : const struct rte_flow_action *action,
2052 : : struct mlx5dr_rule_action *dr_rule)
2053 : : {
2054 : 0 : const struct rte_flow_action_indirect_list *indlst_conf = action->conf;
2055 : :
2056 : 0 : dr_rule->action = ((struct mlx5_hw_encap_decap_action *)
2057 : 0 : (indlst_conf->handle))->action;
2058 [ # # ]: 0 : if (!dr_rule->action)
2059 : 0 : return -EINVAL;
2060 : : return 0;
2061 : : }
2062 : :
2063 : : /**
2064 : : * Template conf must not be masked. If handle is masked, use the one in template,
2065 : : * otherwise update per flow rule.
2066 : : */
2067 : : static int
2068 : 0 : hws_table_tmpl_translate_indirect_reformat(struct rte_eth_dev *dev,
2069 : : const struct rte_flow_action *action,
2070 : : const struct rte_flow_action *mask,
2071 : : struct mlx5_hw_actions *acts,
2072 : : uint16_t action_src, uint16_t action_dst)
2073 : : {
2074 : : int ret = -1;
2075 : 0 : const struct rte_flow_action_indirect_list *mask_conf = mask->conf;
2076 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
2077 : :
2078 [ # # # # : 0 : if (mask_conf && mask_conf->handle && !mask_conf->conf)
# # ]
2079 : : /**
2080 : : * If handle was masked, assign fixed DR action.
2081 : : */
2082 : : ret = flow_hw_reformat_action(dev, NULL, action,
2083 [ # # ]: 0 : &acts->rule_acts[action_dst]);
2084 [ # # # # : 0 : else if (mask_conf && !mask_conf->handle && !mask_conf->conf)
# # ]
2085 : : ret = flow_hw_act_data_indirect_list_append
2086 : : (priv, acts, RTE_FLOW_ACTION_TYPE_INDIRECT_LIST,
2087 : : action_src, action_dst, flow_hw_reformat_action);
2088 : 0 : return ret;
2089 : : }
2090 : :
2091 : : static int
2092 : 0 : flow_dr_set_meter(struct mlx5_priv *priv,
2093 : : struct mlx5dr_rule_action *dr_rule,
2094 : : const struct rte_flow_action_indirect_list *action_conf)
2095 : : {
2096 : 0 : const struct mlx5_indlst_legacy *legacy_obj =
2097 : : (typeof(legacy_obj))action_conf->handle;
2098 : 0 : struct mlx5_aso_mtr_pool *mtr_pool = priv->hws_mpool;
2099 : 0 : uint32_t act_idx = (uint32_t)(uintptr_t)legacy_obj->handle;
2100 : 0 : uint32_t mtr_id = act_idx & (RTE_BIT32(MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
2101 : 0 : struct mlx5_aso_mtr *aso_mtr = mlx5_ipool_get(mtr_pool->idx_pool, mtr_id);
2102 : :
2103 [ # # ]: 0 : if (!aso_mtr)
2104 : : return -EINVAL;
2105 : 0 : dr_rule->action = mtr_pool->action;
2106 : 0 : dr_rule->aso_meter.offset = aso_mtr->offset;
2107 : 0 : return 0;
2108 : : }
2109 : :
2110 : : __rte_always_inline static void
2111 : : flow_dr_mtr_flow_color(struct mlx5dr_rule_action *dr_rule, enum rte_color init_color)
2112 : : {
2113 : 0 : dr_rule->aso_meter.init_color =
2114 : 0 : (enum mlx5dr_action_aso_meter_color)rte_col_2_mlx5_col(init_color);
2115 : 0 : }
2116 : :
2117 : : static int
2118 : 0 : flow_hw_translate_indirect_meter(struct rte_eth_dev *dev,
2119 : : const struct mlx5_action_construct_data *act_data,
2120 : : const struct rte_flow_action *action,
2121 : : struct mlx5dr_rule_action *dr_rule)
2122 : : {
2123 : : int ret;
2124 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
2125 : 0 : const struct rte_flow_action_indirect_list *action_conf = action->conf;
2126 : 0 : const struct rte_flow_indirect_update_flow_meter_mark **flow_conf =
2127 : : (typeof(flow_conf))action_conf->conf;
2128 : :
2129 : 0 : ret = flow_dr_set_meter(priv, dr_rule, action_conf);
2130 [ # # ]: 0 : if (ret)
2131 : : return ret;
2132 [ # # ]: 0 : if (!act_data->shared_meter.conf_masked) {
2133 [ # # # # : 0 : if (flow_conf && flow_conf[0] && flow_conf[0]->init_color < RTE_COLORS)
# # ]
2134 : : flow_dr_mtr_flow_color(dr_rule, flow_conf[0]->init_color);
2135 : : }
2136 : : return 0;
2137 : : }
2138 : :
2139 : : static int
2140 : 0 : hws_table_tmpl_translate_indirect_meter(struct rte_eth_dev *dev,
2141 : : const struct rte_flow_action *action,
2142 : : const struct rte_flow_action *mask,
2143 : : struct mlx5_hw_actions *acts,
2144 : : uint16_t action_src, uint16_t action_dst)
2145 : : {
2146 : : int ret;
2147 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
2148 : 0 : const struct rte_flow_action_indirect_list *action_conf = action->conf;
2149 : 0 : const struct rte_flow_action_indirect_list *mask_conf = mask->conf;
2150 [ # # # # ]: 0 : bool is_handle_masked = mask_conf && mask_conf->handle;
2151 [ # # # # : 0 : bool is_conf_masked = mask_conf && mask_conf->conf && mask_conf->conf[0];
# # ]
2152 : 0 : struct mlx5dr_rule_action *dr_rule = &acts->rule_acts[action_dst];
2153 : :
2154 [ # # ]: 0 : if (is_handle_masked) {
2155 : 0 : ret = flow_dr_set_meter(priv, dr_rule, action->conf);
2156 [ # # ]: 0 : if (ret)
2157 : : return ret;
2158 : : }
2159 [ # # ]: 0 : if (is_conf_masked) {
2160 : : const struct
2161 : 0 : rte_flow_indirect_update_flow_meter_mark **flow_conf =
2162 : : (typeof(flow_conf))action_conf->conf;
2163 : : flow_dr_mtr_flow_color(dr_rule,
2164 [ # # ]: 0 : flow_conf[0]->init_color);
2165 : : }
2166 [ # # ]: 0 : if (!is_handle_masked || !is_conf_masked) {
2167 : : struct mlx5_action_construct_data *act_data;
2168 : :
2169 : : ret = flow_hw_act_data_indirect_list_append
2170 : : (priv, acts, RTE_FLOW_ACTION_TYPE_INDIRECT_LIST,
2171 : : action_src, action_dst, flow_hw_translate_indirect_meter);
2172 : : if (ret)
2173 : 0 : return ret;
2174 : : act_data = LIST_FIRST(&acts->act_list);
2175 : 0 : act_data->shared_meter.conf_masked = is_conf_masked;
2176 : : }
2177 : : return 0;
2178 : : }
2179 : :
2180 : : static int
2181 : : hws_table_tmpl_translate_indirect_legacy(struct rte_eth_dev *dev,
2182 : : const struct rte_flow_action *action,
2183 : : const struct rte_flow_action *mask,
2184 : : struct mlx5_hw_actions *acts,
2185 : : uint16_t action_src, uint16_t action_dst)
2186 : : {
2187 : : int ret;
2188 : : const struct rte_flow_action_indirect_list *indlst_conf = action->conf;
2189 : : struct mlx5_indlst_legacy *indlst_obj = (typeof(indlst_obj))indlst_conf->handle;
2190 : 0 : uint32_t act_idx = (uint32_t)(uintptr_t)indlst_obj->handle;
2191 : 0 : uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
2192 : :
2193 : 0 : switch (type) {
2194 : 0 : case MLX5_INDIRECT_ACTION_TYPE_METER_MARK:
2195 : 0 : ret = hws_table_tmpl_translate_indirect_meter(dev, action, mask,
2196 : : acts, action_src,
2197 : : action_dst);
2198 : 0 : break;
2199 : : default:
2200 : : ret = -EINVAL;
2201 : : break;
2202 : : }
2203 : : return ret;
2204 : : }
2205 : :
2206 : : /*
2207 : : * template .. indirect_list handle Ht conf Ct ..
2208 : : * mask .. indirect_list handle Hm conf Cm ..
2209 : : *
2210 : : * PMD requires Ht != 0 to resolve handle type.
2211 : : * If Ht was masked (Hm != 0) DR5 action will be set according to Ht and will
2212 : : * not change. Otherwise, DR5 action will be resolved during flow rule build.
2213 : : * If Ct was masked (Cm != 0), table template processing updates base
2214 : : * indirect action configuration with Ct parameters.
2215 : : */
2216 : : static int
2217 : 0 : table_template_translate_indirect_list(struct rte_eth_dev *dev,
2218 : : const struct rte_flow_action *action,
2219 : : const struct rte_flow_action *mask,
2220 : : struct mlx5_hw_actions *acts,
2221 : : uint16_t action_src, uint16_t action_dst)
2222 : : {
2223 : : int ret = 0;
2224 : : enum mlx5_indirect_list_type type;
2225 : 0 : const struct rte_flow_action_indirect_list *list_conf = action->conf;
2226 : :
2227 [ # # # # ]: 0 : if (!list_conf || !list_conf->handle)
2228 : : return -EINVAL;
2229 : : type = mlx5_get_indirect_list_type(list_conf->handle);
2230 [ # # # # ]: 0 : switch (type) {
2231 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY:
2232 [ # # ]: 0 : ret = hws_table_tmpl_translate_indirect_legacy(dev, action, mask,
2233 : : acts, action_src,
2234 : : action_dst);
2235 : : break;
2236 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR:
2237 : 0 : ret = hws_table_tmpl_translate_indirect_mirror(dev, action, mask,
2238 : : acts, action_src,
2239 : : action_dst);
2240 : 0 : break;
2241 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT:
2242 [ # # ]: 0 : if (list_conf->conf)
2243 : : return -EINVAL;
2244 : 0 : ret = hws_table_tmpl_translate_indirect_reformat(dev, action, mask,
2245 : : acts, action_src,
2246 : : action_dst);
2247 : 0 : break;
2248 : : default:
2249 : : return -EINVAL;
2250 : : }
2251 : : return ret;
2252 : : }
2253 : :
2254 : : static void
2255 : : mlx5_set_reformat_header(struct mlx5dr_action_reformat_header *hdr,
2256 : : uint8_t *encap_data,
2257 : : size_t data_size)
2258 : : {
2259 : 0 : hdr->sz = data_size;
2260 : 0 : hdr->data = encap_data;
2261 : : }
2262 : :
2263 : : static int
2264 [ # # ]: 0 : mlx5_tbl_translate_reformat(struct mlx5_priv *priv,
2265 : : struct mlx5_hw_actions *acts,
2266 : : struct rte_flow_actions_template *at,
2267 : : const struct rte_flow_item *enc_item,
2268 : : const struct rte_flow_item *enc_item_m,
2269 : : uint8_t *encap_data, uint8_t *encap_data_m,
2270 : : struct mlx5_tbl_multi_pattern_ctx *mp_ctx,
2271 : : size_t data_size, uint16_t reformat_src,
2272 : : enum mlx5dr_action_type refmt_type,
2273 : : struct rte_flow_error *error)
2274 : : {
2275 : : int mp_reformat_ix = mlx5_multi_pattern_reformat_to_index(refmt_type);
2276 : : struct mlx5dr_action_reformat_header hdr;
2277 : : uint8_t buf[MLX5_ENCAP_MAX_LEN];
2278 : : bool shared_rfmt = false;
2279 : : int ret;
2280 : :
2281 : : MLX5_ASSERT(at->reformat_off != UINT16_MAX);
2282 [ # # ]: 0 : if (enc_item) {
2283 : : MLX5_ASSERT(!encap_data);
2284 : 0 : ret = flow_dv_convert_encap_data(enc_item, buf, &data_size, error);
2285 [ # # ]: 0 : if (ret)
2286 : : return ret;
2287 : : encap_data = buf;
2288 [ # # ]: 0 : if (enc_item_m)
2289 : : shared_rfmt = true;
2290 [ # # ]: 0 : } else if (encap_data && encap_data_m) {
2291 : : shared_rfmt = true;
2292 : : }
2293 : 0 : acts->encap_decap = mlx5_malloc(MLX5_MEM_ZERO,
2294 : : sizeof(*acts->encap_decap) + data_size,
2295 : : 0, SOCKET_ID_ANY);
2296 [ # # ]: 0 : if (!acts->encap_decap)
2297 : 0 : return rte_flow_error_set(error, ENOMEM,
2298 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2299 : : NULL, "no memory for reformat context");
2300 : 0 : acts->encap_decap_pos = at->reformat_off;
2301 : 0 : acts->encap_decap->data_size = data_size;
2302 : 0 : acts->encap_decap->action_type = refmt_type;
2303 [ # # ]: 0 : if (shared_rfmt || mp_reformat_ix < 0) {
2304 : : uint16_t reformat_ix = at->reformat_off;
2305 : : /*
2306 : : * This copy is only needed in non template mode.
2307 : : * In order to create the action later.
2308 : : */
2309 : 0 : memcpy(acts->encap_decap->data, encap_data, data_size);
2310 : 0 : acts->rule_acts[reformat_ix].reformat.data = acts->encap_decap->data;
2311 : 0 : acts->rule_acts[reformat_ix].reformat.offset = 0;
2312 : 0 : acts->encap_decap->shared = true;
2313 : : } else {
2314 : : uint32_t ix;
2315 : 0 : typeof(mp_ctx->reformat[0]) *reformat = mp_ctx->reformat +
2316 : : mp_reformat_ix;
2317 : : mlx5_set_reformat_header(&hdr, encap_data, data_size);
2318 : 0 : ix = reformat->elements_num++;
2319 : 0 : reformat->reformat_hdr[ix] = hdr;
2320 : 0 : acts->rule_acts[at->reformat_off].reformat.hdr_idx = ix;
2321 : 0 : acts->encap_decap->multi_pattern = 1;
2322 : 0 : ret = __flow_hw_act_data_encap_append
2323 : 0 : (priv, acts, (at->actions + reformat_src)->type,
2324 : : reformat_src, at->reformat_off, data_size);
2325 : : if (ret)
2326 : 0 : return -rte_errno;
2327 : : mlx5_multi_pattern_activate(mp_ctx);
2328 : : }
2329 : : return 0;
2330 : : }
2331 : :
2332 : : static int
2333 [ # # ]: 0 : mlx5_tbl_create_reformat_action(struct mlx5_priv *priv,
2334 : : const struct rte_flow_template_table_attr *table_attr,
2335 : : struct mlx5_hw_actions *acts,
2336 : : struct rte_flow_actions_template *at,
2337 : : uint8_t *encap_data,
2338 : : size_t data_size,
2339 : : enum mlx5dr_action_type refmt_type)
2340 : : {
2341 : : const struct rte_flow_attr *attr = &table_attr->flow_attr;
2342 : : enum mlx5dr_table_type tbl_type = get_mlx5dr_table_type(attr);
2343 : : struct mlx5dr_action_reformat_header hdr;
2344 : :
2345 : : mlx5_set_reformat_header(&hdr, encap_data, data_size);
2346 : 0 : uint16_t reformat_ix = at->reformat_off;
2347 : 0 : uint32_t flags = mlx5_hw_act_flag[!!attr->group][tbl_type] |
2348 : : MLX5DR_ACTION_FLAG_SHARED;
2349 : :
2350 : 0 : acts->encap_decap->action = mlx5dr_action_create_reformat(priv->dr_ctx, refmt_type,
2351 : : 1, &hdr, 0, flags);
2352 [ # # ]: 0 : if (!acts->encap_decap->action)
2353 : 0 : return -rte_errno;
2354 : 0 : acts->rule_acts[reformat_ix].action = acts->encap_decap->action;
2355 : 0 : return 0;
2356 : : }
2357 : :
2358 : : static int
2359 : 0 : mlx5_tbl_translate_modify_header(struct rte_eth_dev *dev,
2360 : : const struct mlx5_flow_template_table_cfg *cfg,
2361 : : struct mlx5_hw_actions *acts,
2362 : : struct mlx5_tbl_multi_pattern_ctx *mp_ctx,
2363 : : struct mlx5_hw_modify_header_action *mhdr,
2364 : : struct rte_flow_error *error)
2365 : : {
2366 : 0 : uint16_t mhdr_ix = mhdr->pos;
2367 : : struct mlx5dr_action_mh_pattern pattern = {
2368 : 0 : .sz = sizeof(struct mlx5_modification_cmd) * mhdr->mhdr_cmds_num
2369 : : };
2370 : :
2371 [ # # ]: 0 : if (flow_hw_validate_compiled_modify_field(dev, cfg, mhdr, error)) {
2372 : : __flow_hw_action_template_destroy(dev, acts);
2373 : 0 : return -rte_errno;
2374 : : }
2375 : 0 : acts->mhdr = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*acts->mhdr),
2376 : : 0, SOCKET_ID_ANY);
2377 [ # # ]: 0 : if (!acts->mhdr)
2378 : 0 : return rte_flow_error_set(error, ENOMEM,
2379 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2380 : : NULL, "translate modify_header: no memory for modify header context");
2381 : : rte_memcpy(acts->mhdr, mhdr, sizeof(*mhdr));
2382 [ # # ]: 0 : if (!mhdr->shared) {
2383 : 0 : pattern.data = (__be64 *)acts->mhdr->mhdr_cmds;
2384 : : typeof(mp_ctx->mh) *mh = &mp_ctx->mh;
2385 : 0 : uint32_t idx = mh->elements_num;
2386 : 0 : mh->pattern[mh->elements_num++] = pattern;
2387 : 0 : acts->mhdr->multi_pattern = 1;
2388 : 0 : acts->rule_acts[mhdr_ix].modify_header.pattern_idx = idx;
2389 : : mlx5_multi_pattern_activate(mp_ctx);
2390 : : }
2391 : : return 0;
2392 : : }
2393 : :
2394 : : static int
2395 : 0 : mlx5_tbl_ensure_shared_modify_header(struct rte_eth_dev *dev,
2396 : : const struct mlx5_flow_template_table_cfg *cfg,
2397 : : struct mlx5_hw_actions *acts,
2398 : : struct rte_flow_error *error)
2399 : : {
2400 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
2401 : : const struct rte_flow_template_table_attr *table_attr = &cfg->attr;
2402 : : const struct rte_flow_attr *attr = &table_attr->flow_attr;
2403 : : enum mlx5dr_table_type tbl_type = get_mlx5dr_table_type(attr);
2404 : 0 : struct mlx5dr_action_mh_pattern pattern = {
2405 : 0 : .sz = sizeof(struct mlx5_modification_cmd) * acts->mhdr->mhdr_cmds_num
2406 : : };
2407 : 0 : uint16_t mhdr_ix = acts->mhdr->pos;
2408 : 0 : uint32_t flags = mlx5_hw_act_flag[!!attr->group][tbl_type] | MLX5DR_ACTION_FLAG_SHARED;
2409 : :
2410 : 0 : pattern.data = (__be64 *)acts->mhdr->mhdr_cmds;
2411 : 0 : acts->mhdr->action = mlx5dr_action_create_modify_header(priv->dr_ctx, 1,
2412 : : &pattern, 0, flags);
2413 [ # # ]: 0 : if (!acts->mhdr->action)
2414 : 0 : return rte_flow_error_set(error, rte_errno,
2415 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2416 : : "translate modify_header: failed to create DR action");
2417 : 0 : acts->rule_acts[mhdr_ix].action = acts->mhdr->action;
2418 : 0 : return 0;
2419 : : }
2420 : :
2421 : : static int
2422 : 0 : mlx5_create_ipv6_ext_reformat(struct rte_eth_dev *dev,
2423 : : const struct mlx5_flow_template_table_cfg *cfg,
2424 : : struct mlx5_hw_actions *acts,
2425 : : struct rte_flow_actions_template *at,
2426 : : uint8_t *push_data, uint8_t *push_data_m,
2427 : : size_t push_size, uint16_t recom_src,
2428 : : enum mlx5dr_action_type recom_type)
2429 : : {
2430 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
2431 : : const struct rte_flow_template_table_attr *table_attr = &cfg->attr;
2432 : : const struct rte_flow_attr *attr = &table_attr->flow_attr;
2433 : : enum mlx5dr_table_type type = get_mlx5dr_table_type(attr);
2434 : : struct mlx5_action_construct_data *act_data;
2435 : 0 : struct mlx5dr_action_reformat_header hdr = {0};
2436 : : uint32_t flag, bulk = 0;
2437 : :
2438 : 0 : flag = mlx5_hw_act_flag[!!attr->group][type];
2439 : 0 : acts->push_remove = mlx5_malloc(MLX5_MEM_ZERO,
2440 : : sizeof(*acts->push_remove) + push_size,
2441 : : 0, SOCKET_ID_ANY);
2442 [ # # ]: 0 : if (!acts->push_remove)
2443 : : return -ENOMEM;
2444 : :
2445 [ # # # ]: 0 : switch (recom_type) {
2446 : 0 : case MLX5DR_ACTION_TYP_PUSH_IPV6_ROUTE_EXT:
2447 [ # # ]: 0 : if (!push_data || !push_size)
2448 : 0 : goto err1;
2449 [ # # ]: 0 : if (!push_data_m) {
2450 [ # # ]: 0 : bulk = rte_log2_u32(table_attr->nb_flows);
2451 : : } else {
2452 : 0 : flag |= MLX5DR_ACTION_FLAG_SHARED;
2453 : 0 : acts->push_remove->shared = 1;
2454 : : }
2455 : 0 : acts->push_remove->data_size = push_size;
2456 : 0 : memcpy(acts->push_remove->data, push_data, push_size);
2457 : 0 : hdr.data = push_data;
2458 : 0 : hdr.sz = push_size;
2459 : 0 : break;
2460 : 0 : case MLX5DR_ACTION_TYP_POP_IPV6_ROUTE_EXT:
2461 : 0 : flag |= MLX5DR_ACTION_FLAG_SHARED;
2462 : 0 : acts->push_remove->shared = 1;
2463 : 0 : break;
2464 : : default:
2465 : : break;
2466 : : }
2467 : :
2468 : 0 : acts->push_remove->action =
2469 : 0 : mlx5dr_action_create_reformat_ipv6_ext(priv->dr_ctx,
2470 : : recom_type, &hdr, bulk, flag);
2471 [ # # ]: 0 : if (!acts->push_remove->action)
2472 : 0 : goto err1;
2473 : 0 : acts->rule_acts[at->recom_off].action = acts->push_remove->action;
2474 : 0 : acts->rule_acts[at->recom_off].ipv6_ext.header = acts->push_remove->data;
2475 : 0 : acts->rule_acts[at->recom_off].ipv6_ext.offset = 0;
2476 : 0 : acts->push_remove_pos = at->recom_off;
2477 [ # # ]: 0 : if (!acts->push_remove->shared) {
2478 : 0 : act_data = __flow_hw_act_data_push_append(dev, acts,
2479 : : RTE_FLOW_ACTION_TYPE_IPV6_EXT_PUSH,
2480 : : recom_src, at->recom_off, push_size);
2481 : : if (!act_data)
2482 : 0 : goto err;
2483 : : }
2484 : : return 0;
2485 : : err:
2486 [ # # ]: 0 : if (acts->push_remove->action)
2487 : 0 : mlx5dr_action_destroy(acts->push_remove->action);
2488 : 0 : err1:
2489 [ # # ]: 0 : if (acts->push_remove) {
2490 : 0 : mlx5_free(acts->push_remove);
2491 : 0 : acts->push_remove = NULL;
2492 : : }
2493 : : return -EINVAL;
2494 : : }
2495 : :
2496 : : /**
2497 : : * Translate rte_flow actions to DR action.
2498 : : *
2499 : : * As the action template has already indicated the actions. Translate
2500 : : * the rte_flow actions to DR action if possbile. So in flow create
2501 : : * stage we will save cycles from handing the actions' organizing.
2502 : : * For the actions with limited information, need to add these to a
2503 : : * list.
2504 : : *
2505 : : * @param[in] dev
2506 : : * Pointer to the rte_eth_dev structure.
2507 : : * @param[in] cfg
2508 : : * Pointer to the table configuration.
2509 : : * @param[in/out] acts
2510 : : * Pointer to the template HW steering DR actions.
2511 : : * @param[in] at
2512 : : * Action template.
2513 : : * @param[in] nt_mode
2514 : : * Non template rule translate.
2515 : : * @param[out] error
2516 : : * Pointer to error structure.
2517 : : *
2518 : : * @return
2519 : : * 0 on success, a negative errno otherwise and rte_errno is set.
2520 : : */
2521 : : static int
2522 : 0 : __flow_hw_translate_actions_template(struct rte_eth_dev *dev,
2523 : : const struct mlx5_flow_template_table_cfg *cfg,
2524 : : struct mlx5_hw_actions *acts,
2525 : : struct rte_flow_actions_template *at,
2526 : : struct mlx5_tbl_multi_pattern_ctx *mp_ctx,
2527 : : bool nt_mode,
2528 : : struct rte_flow_error *error)
2529 : : {
2530 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
2531 : 0 : const struct rte_flow_template_table_attr *table_attr = &cfg->attr;
2532 : 0 : struct mlx5_hca_flex_attr *hca_attr = &priv->sh->cdev->config.hca_attr.flex;
2533 : 0 : const struct rte_flow_attr *attr = &table_attr->flow_attr;
2534 : 0 : struct rte_flow_action *actions = at->actions;
2535 : 0 : struct rte_flow_action *masks = at->masks;
2536 : : enum mlx5dr_action_type refmt_type = MLX5DR_ACTION_TYP_LAST;
2537 : : enum mlx5dr_action_type recom_type = MLX5DR_ACTION_TYP_LAST;
2538 : : const struct rte_flow_action_raw_encap *raw_encap_data;
2539 : : const struct rte_flow_action_ipv6_ext_push *ipv6_ext_data;
2540 : : const struct rte_flow_item *enc_item = NULL, *enc_item_m = NULL;
2541 : : uint16_t reformat_src = 0, recom_src = 0;
2542 : : uint8_t *encap_data = NULL, *encap_data_m = NULL;
2543 : : uint8_t *push_data = NULL, *push_data_m = NULL;
2544 : : size_t data_size = 0, push_size = 0;
2545 : : struct mlx5_hw_modify_header_action mhdr = { 0 };
2546 : : bool actions_end = false;
2547 : : uint32_t type;
2548 : : bool reformat_used = false;
2549 : : bool recom_used = false;
2550 : : unsigned int of_vlan_offset;
2551 : : uint16_t jump_pos;
2552 : : uint32_t ct_idx;
2553 : : int ret, err;
2554 [ # # ]: 0 : uint32_t target_grp = 0;
2555 : : int table_type;
2556 : :
2557 : : flow_hw_modify_field_init(&mhdr, at);
2558 [ # # ]: 0 : if (attr->transfer)
2559 : : type = MLX5DR_TABLE_TYPE_FDB;
2560 [ # # ]: 0 : else if (attr->egress)
2561 : : type = MLX5DR_TABLE_TYPE_NIC_TX;
2562 : : else
2563 : : type = MLX5DR_TABLE_TYPE_NIC_RX;
2564 [ # # ]: 0 : for (; !actions_end; actions++, masks++) {
2565 : 0 : uint64_t pos = actions - at->actions;
2566 : 0 : uint16_t src_pos = pos - at->src_off[pos];
2567 : 0 : uint16_t dr_pos = at->dr_off[pos];
2568 : :
2569 [ # # # # : 0 : switch ((int)actions->type) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
2570 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT_LIST:
2571 [ # # ]: 0 : if (!attr->group) {
2572 : 0 : DRV_LOG(ERR, "Indirect action is not supported in root table.");
2573 : 0 : goto err;
2574 : : }
2575 : 0 : ret = table_template_translate_indirect_list
2576 : : (dev, actions, masks, acts, src_pos, dr_pos);
2577 [ # # ]: 0 : if (ret)
2578 : 0 : goto err;
2579 : : break;
2580 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT:
2581 [ # # ]: 0 : if (!attr->group) {
2582 : 0 : DRV_LOG(ERR, "Indirect action is not supported in root table.");
2583 : 0 : goto err;
2584 : : }
2585 [ # # # # ]: 0 : if (actions->conf && masks->conf) {
2586 [ # # # # : 0 : if (flow_hw_shared_action_translate
# # # ]
2587 : : (dev, actions, acts, src_pos, dr_pos))
2588 : 0 : goto err;
2589 : 0 : } else if (__flow_hw_act_data_indirect_append
2590 : : (priv, acts, RTE_FLOW_ACTION_TYPE_INDIRECT,
2591 : : masks->type, src_pos, dr_pos)){
2592 : 0 : goto err;
2593 : : }
2594 : : break;
2595 : : case RTE_FLOW_ACTION_TYPE_VOID:
2596 : : break;
2597 : 0 : case RTE_FLOW_ACTION_TYPE_DROP:
2598 : 0 : acts->rule_acts[dr_pos].action =
2599 : 0 : priv->hw_drop[!!attr->group];
2600 : 0 : break;
2601 : 0 : case RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:
2602 [ # # ]: 0 : if (!attr->group) {
2603 : 0 : DRV_LOG(ERR, "Port representor is not supported in root table.");
2604 : 0 : goto err;
2605 : : }
2606 : 0 : acts->rule_acts[dr_pos].action = priv->hw_def_miss;
2607 : 0 : break;
2608 : 0 : case RTE_FLOW_ACTION_TYPE_FLAG:
2609 : 0 : acts->mark = true;
2610 : 0 : acts->rule_acts[dr_pos].tag.value =
2611 : : mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
2612 : 0 : acts->rule_acts[dr_pos].action =
2613 : 0 : priv->hw_tag[!!attr->group];
2614 : 0 : rte_atomic_fetch_add_explicit(&priv->hws_mark_refcnt, 1,
2615 : : rte_memory_order_relaxed);
2616 : 0 : flow_hw_rxq_flag_set(dev, true);
2617 : 0 : break;
2618 : 0 : case RTE_FLOW_ACTION_TYPE_MARK:
2619 : 0 : acts->mark = true;
2620 [ # # ]: 0 : if (masks->conf &&
2621 : : ((const struct rte_flow_action_mark *)
2622 [ # # ]: 0 : masks->conf)->id)
2623 : 0 : acts->rule_acts[dr_pos].tag.value =
2624 : : mlx5_flow_mark_set
2625 : : (((const struct rte_flow_action_mark *)
2626 [ # # ]: 0 : (actions->conf))->id);
2627 : : else if (__flow_hw_act_data_general_append(priv, acts,
2628 : : actions->type,
2629 : : src_pos, dr_pos))
2630 : 0 : goto err;
2631 : 0 : acts->rule_acts[dr_pos].action =
2632 : 0 : priv->hw_tag[!!attr->group];
2633 : 0 : rte_atomic_fetch_add_explicit(&priv->hws_mark_refcnt, 1,
2634 : : rte_memory_order_relaxed);
2635 : 0 : flow_hw_rxq_flag_set(dev, true);
2636 : 0 : break;
2637 : 0 : case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
2638 : 0 : acts->rule_acts[dr_pos].action =
2639 : 0 : priv->hw_push_vlan[type];
2640 [ # # # # ]: 0 : if (is_template_masked_push_vlan(masks->conf))
2641 : 0 : acts->rule_acts[dr_pos].push_vlan.vlan_hdr =
2642 : : vlan_hdr_to_be32(actions);
2643 : : else if (__flow_hw_act_data_general_append
2644 : : (priv, acts, actions->type,
2645 : : src_pos, dr_pos))
2646 : 0 : goto err;
2647 : : of_vlan_offset = is_of_vlan_pcp_present(actions) ?
2648 [ # # ]: 0 : MLX5_HW_VLAN_PUSH_PCP_IDX :
2649 : : MLX5_HW_VLAN_PUSH_VID_IDX;
2650 : 0 : actions += of_vlan_offset;
2651 : 0 : masks += of_vlan_offset;
2652 : 0 : break;
2653 : 0 : case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
2654 : 0 : acts->rule_acts[dr_pos].action =
2655 : 0 : priv->hw_pop_vlan[type];
2656 : 0 : break;
2657 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP:
2658 [ # # ]: 0 : if (masks->conf &&
2659 : : ((const struct rte_flow_action_jump *)
2660 [ # # ]: 0 : masks->conf)->group) {
2661 : 0 : uint32_t jump_group =
2662 : : ((const struct rte_flow_action_jump *)
2663 : 0 : actions->conf)->group;
2664 : 0 : acts->jump = flow_hw_jump_action_register
2665 : : (dev, cfg, jump_group, error);
2666 [ # # ]: 0 : if (!acts->jump)
2667 : 0 : goto err;
2668 : 0 : acts->rule_acts[dr_pos].action = (!!attr->group) ?
2669 [ # # ]: 0 : acts->jump->hws_action :
2670 : : acts->jump->root_action;
2671 : : } else if (__flow_hw_act_data_general_append
2672 : : (priv, acts, actions->type,
2673 : : src_pos, dr_pos)){
2674 : 0 : goto err;
2675 : : }
2676 : : break;
2677 : 0 : case RTE_FLOW_ACTION_TYPE_QUEUE:
2678 [ # # ]: 0 : if (masks->conf &&
2679 : : ((const struct rte_flow_action_queue *)
2680 [ # # ]: 0 : masks->conf)->index) {
2681 : 0 : acts->tir = flow_hw_tir_action_register
2682 : 0 : (dev, mlx5_hw_act_flag[!!attr->group][type],
2683 : : actions);
2684 [ # # ]: 0 : if (!acts->tir)
2685 : 0 : goto err;
2686 : 0 : acts->rule_acts[dr_pos].action =
2687 : 0 : acts->tir->action;
2688 : : } else if (__flow_hw_act_data_general_append
2689 : : (priv, acts, actions->type,
2690 : : src_pos, dr_pos)) {
2691 : 0 : goto err;
2692 : : }
2693 : : break;
2694 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
2695 [ # # # # ]: 0 : if (actions->conf && masks->conf) {
2696 : 0 : acts->tir = flow_hw_tir_action_register
2697 : 0 : (dev, mlx5_hw_act_flag[!!attr->group][type],
2698 : : actions);
2699 [ # # ]: 0 : if (!acts->tir)
2700 : 0 : goto err;
2701 : 0 : acts->rule_acts[dr_pos].action =
2702 : 0 : acts->tir->action;
2703 : : } else if (__flow_hw_act_data_general_append
2704 : : (priv, acts, actions->type,
2705 : : src_pos, dr_pos)) {
2706 : 0 : goto err;
2707 : : }
2708 : : break;
2709 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
2710 : : MLX5_ASSERT(!reformat_used);
2711 : 0 : enc_item = MLX5_CONST_ENCAP_ITEM(rte_flow_action_vxlan_encap,
2712 : : actions->conf);
2713 [ # # ]: 0 : if (masks->conf)
2714 : 0 : enc_item_m = MLX5_CONST_ENCAP_ITEM(rte_flow_action_vxlan_encap,
2715 : : masks->conf);
2716 : : reformat_used = true;
2717 : : reformat_src = src_pos;
2718 : : refmt_type = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;
2719 : : break;
2720 : 0 : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
2721 : : MLX5_ASSERT(!reformat_used);
2722 : 0 : enc_item = MLX5_CONST_ENCAP_ITEM(rte_flow_action_nvgre_encap,
2723 : : actions->conf);
2724 [ # # ]: 0 : if (masks->conf)
2725 : 0 : enc_item_m = MLX5_CONST_ENCAP_ITEM(rte_flow_action_nvgre_encap,
2726 : : masks->conf);
2727 : : reformat_used = true;
2728 : : reformat_src = src_pos;
2729 : : refmt_type = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;
2730 : : break;
2731 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
2732 : 0 : raw_encap_data =
2733 : : (const struct rte_flow_action_raw_encap *)
2734 : : masks->conf;
2735 [ # # ]: 0 : if (raw_encap_data)
2736 : 0 : encap_data_m = raw_encap_data->data;
2737 : 0 : raw_encap_data =
2738 : : (const struct rte_flow_action_raw_encap *)
2739 : : actions->conf;
2740 : 0 : encap_data = raw_encap_data->data;
2741 : 0 : data_size = raw_encap_data->size;
2742 [ # # ]: 0 : if (reformat_used) {
2743 : : refmt_type = data_size <
2744 : : MLX5_ENCAPSULATION_DECISION_SIZE ?
2745 [ # # ]: 0 : MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2 :
2746 : : MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3;
2747 : : } else {
2748 : : reformat_used = true;
2749 : : refmt_type =
2750 : : MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;
2751 : : }
2752 : : reformat_src = src_pos;
2753 : : break;
2754 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
2755 : : case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
2756 : : MLX5_ASSERT(!reformat_used);
2757 : : reformat_used = true;
2758 : : refmt_type = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2;
2759 : 0 : break;
2760 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
2761 : : reformat_used = true;
2762 : : refmt_type = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2;
2763 : 0 : break;
2764 : 0 : case RTE_FLOW_ACTION_TYPE_IPV6_EXT_PUSH:
2765 [ # # ]: 0 : if (!hca_attr->query_match_sample_info || !hca_attr->parse_graph_anchor ||
2766 [ # # ]: 0 : !priv->sh->srh_flex_parser.flex.mapnum) {
2767 : 0 : DRV_LOG(ERR, "SRv6 anchor is not supported.");
2768 : 0 : goto err;
2769 : : }
2770 : : MLX5_ASSERT(!recom_used && !recom_type);
2771 : : recom_used = true;
2772 : : recom_type = MLX5DR_ACTION_TYP_PUSH_IPV6_ROUTE_EXT;
2773 : 0 : ipv6_ext_data =
2774 : : (const struct rte_flow_action_ipv6_ext_push *)masks->conf;
2775 [ # # ]: 0 : if (ipv6_ext_data)
2776 : 0 : push_data_m = ipv6_ext_data->data;
2777 : 0 : ipv6_ext_data =
2778 : : (const struct rte_flow_action_ipv6_ext_push *)actions->conf;
2779 [ # # ]: 0 : if (ipv6_ext_data) {
2780 : 0 : push_data = ipv6_ext_data->data;
2781 : 0 : push_size = ipv6_ext_data->size;
2782 : : }
2783 : : recom_src = src_pos;
2784 : : break;
2785 : 0 : case RTE_FLOW_ACTION_TYPE_IPV6_EXT_REMOVE:
2786 [ # # ]: 0 : if (!hca_attr->query_match_sample_info || !hca_attr->parse_graph_anchor ||
2787 [ # # ]: 0 : !priv->sh->srh_flex_parser.flex.mapnum) {
2788 : 0 : DRV_LOG(ERR, "SRv6 anchor is not supported.");
2789 : 0 : goto err;
2790 : : }
2791 : : recom_used = true;
2792 : : recom_type = MLX5DR_ACTION_TYP_POP_IPV6_ROUTE_EXT;
2793 : : break;
2794 : 0 : case RTE_FLOW_ACTION_TYPE_SEND_TO_KERNEL:
2795 : 0 : ret = flow_hw_translate_group(dev, cfg, attr->group,
2796 : : &target_grp, error);
2797 [ # # ]: 0 : if (ret)
2798 : 0 : return ret;
2799 [ # # ]: 0 : if (target_grp == 0) {
2800 : : __flow_hw_action_template_destroy(dev, acts);
2801 : 0 : return rte_flow_error_set(error, ENOTSUP,
2802 : : RTE_FLOW_ERROR_TYPE_ACTION,
2803 : : NULL,
2804 : : "Send to kernel action on root table is not supported in HW steering mode");
2805 : : }
2806 [ # # ]: 0 : table_type = attr->ingress ? MLX5DR_TABLE_TYPE_NIC_RX :
2807 [ # # ]: 0 : ((attr->egress) ? MLX5DR_TABLE_TYPE_NIC_TX :
2808 : : MLX5DR_TABLE_TYPE_FDB);
2809 : 0 : acts->rule_acts[dr_pos].action = priv->hw_send_to_kernel[table_type];
2810 : 0 : break;
2811 [ # # ]: 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
2812 : : err = flow_hw_modify_field_compile(dev, attr, actions,
2813 : : masks, acts, &mhdr,
2814 : : src_pos, error);
2815 [ # # ]: 0 : if (err)
2816 : 0 : goto err;
2817 : : break;
2818 : 0 : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
2819 [ # # ]: 0 : if (flow_hw_represented_port_compile
2820 : : (dev, attr, actions,
2821 : : masks, acts, src_pos, dr_pos, error))
2822 : 0 : goto err;
2823 : : break;
2824 : 0 : case RTE_FLOW_ACTION_TYPE_METER:
2825 : : /*
2826 : : * METER action is compiled to 2 DR actions - ASO_METER and FT.
2827 : : * Calculated DR offset is stored only for ASO_METER and FT
2828 : : * is assumed to be the next action.
2829 : : */
2830 : 0 : jump_pos = dr_pos + 1;
2831 [ # # # # ]: 0 : if (actions->conf && masks->conf &&
2832 : : ((const struct rte_flow_action_meter *)
2833 [ # # ]: 0 : masks->conf)->mtr_id) {
2834 : 0 : err = flow_hw_meter_compile(dev, cfg,
2835 : : dr_pos, jump_pos, actions, acts, error);
2836 : : if (err)
2837 : 0 : goto err;
2838 : : } else if (__flow_hw_act_data_general_append(priv, acts,
2839 : : actions->type,
2840 : : src_pos,
2841 : : dr_pos))
2842 : 0 : goto err;
2843 : : break;
2844 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
2845 : 0 : ret = flow_hw_translate_group(dev, cfg, attr->group,
2846 : : &target_grp, error);
2847 [ # # ]: 0 : if (ret)
2848 : 0 : return ret;
2849 [ # # ]: 0 : if (target_grp == 0) {
2850 : : __flow_hw_action_template_destroy(dev, acts);
2851 : 0 : return rte_flow_error_set(error, ENOTSUP,
2852 : : RTE_FLOW_ERROR_TYPE_ACTION,
2853 : : NULL,
2854 : : "Age action on root table is not supported in HW steering mode");
2855 : : }
2856 : 0 : if (__flow_hw_act_data_general_append(priv, acts,
2857 : : actions->type,
2858 : : src_pos,
2859 : : dr_pos))
2860 : 0 : goto err;
2861 : : break;
2862 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
2863 : 0 : ret = flow_hw_translate_group(dev, cfg, attr->group,
2864 : : &target_grp, error);
2865 [ # # ]: 0 : if (ret)
2866 : 0 : return ret;
2867 [ # # ]: 0 : if (target_grp == 0) {
2868 : : __flow_hw_action_template_destroy(dev, acts);
2869 : 0 : return rte_flow_error_set(error, ENOTSUP,
2870 : : RTE_FLOW_ERROR_TYPE_ACTION,
2871 : : NULL,
2872 : : "Counter action on root table is not supported in HW steering mode");
2873 : : }
2874 [ # # ]: 0 : if ((at->action_flags & MLX5_FLOW_ACTION_AGE) ||
2875 : : (at->action_flags & MLX5_FLOW_ACTION_INDIRECT_AGE))
2876 : : /*
2877 : : * When both COUNT and AGE are requested, it is
2878 : : * saved as AGE action which creates also the
2879 : : * counter.
2880 : : */
2881 : : break;
2882 [ # # ]: 0 : if (masks->conf &&
2883 : : ((const struct rte_flow_action_count *)
2884 [ # # ]: 0 : masks->conf)->id) {
2885 [ # # ]: 0 : err = flow_hw_cnt_compile(dev, dr_pos, acts);
2886 : : if (err)
2887 : 0 : goto err;
2888 : 0 : } else if (__flow_hw_act_data_general_append
2889 : : (priv, acts, actions->type,
2890 : : src_pos, dr_pos)) {
2891 : 0 : goto err;
2892 : : }
2893 : : break;
2894 : 0 : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
2895 [ # # ]: 0 : if (masks->conf) {
2896 : 0 : ct_idx = MLX5_INDIRECT_ACTION_IDX_GET(actions->conf);
2897 : : if (flow_hw_ct_compile(dev, MLX5_HW_INV_QUEUE, ct_idx,
2898 : 0 : &acts->rule_acts[dr_pos]))
2899 : 0 : goto err;
2900 : : } else if (__flow_hw_act_data_general_append
2901 : : (priv, acts, actions->type,
2902 : : src_pos, dr_pos)) {
2903 : 0 : goto err;
2904 : : }
2905 : : break;
2906 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
2907 [ # # # # ]: 0 : if (actions->conf && masks->conf &&
2908 : : ((const struct rte_flow_action_meter_mark *)
2909 [ # # ]: 0 : masks->conf)->profile) {
2910 : : err = flow_hw_meter_mark_compile(dev,
2911 : : dr_pos, actions,
2912 : 0 : acts->rule_acts,
2913 : : &acts->mtr_id,
2914 : : MLX5_HW_INV_QUEUE,
2915 : : error);
2916 : : if (err)
2917 : 0 : goto err;
2918 : : } else if (__flow_hw_act_data_general_append(priv, acts,
2919 : : actions->type,
2920 : : src_pos,
2921 : : dr_pos))
2922 : 0 : goto err;
2923 : : break;
2924 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
2925 : : /* Internal, can be skipped. */
2926 [ # # ]: 0 : if (!!attr->group) {
2927 : 0 : DRV_LOG(ERR, "DEFAULT MISS action is only"
2928 : : " supported in root table.");
2929 : 0 : goto err;
2930 : : }
2931 : 0 : acts->rule_acts[dr_pos].action = priv->hw_def_miss;
2932 : 0 : break;
2933 : 0 : case RTE_FLOW_ACTION_TYPE_NAT64:
2934 [ # # ]: 0 : if (masks->conf &&
2935 [ # # ]: 0 : ((const struct rte_flow_action_nat64 *)masks->conf)->type) {
2936 : 0 : const struct rte_flow_action_nat64 *nat64_c =
2937 : : (const struct rte_flow_action_nat64 *)actions->conf;
2938 : :
2939 : 0 : acts->rule_acts[dr_pos].action =
2940 : 0 : priv->action_nat64[type][nat64_c->type];
2941 : : } else if (__flow_hw_act_data_general_append(priv, acts,
2942 : : actions->type,
2943 : : src_pos, dr_pos))
2944 : 0 : goto err;
2945 : : break;
2946 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
2947 [ # # ]: 0 : if (masks->conf &&
2948 : : ((const struct rte_flow_action_jump_to_table_index *)
2949 [ # # ]: 0 : masks->conf)->table) {
2950 : 0 : struct rte_flow_template_table *jump_table =
2951 : : ((const struct rte_flow_action_jump_to_table_index *)
2952 : 0 : actions->conf)->table;
2953 : 0 : acts->rule_acts[dr_pos].jump_to_matcher.offset =
2954 : : ((const struct rte_flow_action_jump_to_table_index *)
2955 : 0 : actions->conf)->index;
2956 [ # # ]: 0 : if (likely(!rte_flow_template_table_resizable(dev->data->port_id,
2957 : : &jump_table->cfg.attr))) {
2958 : 0 : acts->rule_acts[dr_pos].action =
2959 : 0 : jump_table->matcher_info[0].jump;
2960 : : } else {
2961 : : uint32_t selector;
2962 : 0 : rte_rwlock_read_lock(&jump_table->matcher_replace_rwlk);
2963 : 0 : selector = jump_table->matcher_selector;
2964 : 0 : acts->rule_acts[dr_pos].action =
2965 : 0 : jump_table->matcher_info[selector].jump;
2966 : : rte_rwlock_read_unlock(&jump_table->matcher_replace_rwlk);
2967 : : }
2968 : : } else if (__flow_hw_act_data_general_append
2969 : : (priv, acts, actions->type,
2970 : : src_pos, dr_pos)){
2971 : 0 : goto err;
2972 : : }
2973 : : break;
2974 : 0 : case RTE_FLOW_ACTION_TYPE_END:
2975 : : actions_end = true;
2976 : 0 : break;
2977 : : default:
2978 : : break;
2979 : : }
2980 : : }
2981 [ # # ]: 0 : if (mhdr.pos != UINT16_MAX) {
2982 : 0 : ret = mlx5_tbl_translate_modify_header(dev, cfg, acts, mp_ctx, &mhdr, error);
2983 [ # # ]: 0 : if (ret)
2984 : 0 : goto err;
2985 [ # # # # ]: 0 : if (!nt_mode && mhdr.shared) {
2986 : 0 : ret = mlx5_tbl_ensure_shared_modify_header(dev, cfg, acts, error);
2987 [ # # ]: 0 : if (ret)
2988 : 0 : goto err;
2989 : : }
2990 : : }
2991 [ # # ]: 0 : if (reformat_used) {
2992 : 0 : ret = mlx5_tbl_translate_reformat(priv, acts, at,
2993 : : enc_item, enc_item_m,
2994 : : encap_data, encap_data_m,
2995 : : mp_ctx, data_size,
2996 : : reformat_src,
2997 : : refmt_type, error);
2998 [ # # ]: 0 : if (ret)
2999 : 0 : goto err;
3000 [ # # # # ]: 0 : if (!nt_mode && acts->encap_decap->shared) {
3001 : 0 : ret = mlx5_tbl_create_reformat_action(priv, table_attr, acts, at,
3002 : : encap_data, data_size,
3003 : : refmt_type);
3004 [ # # ]: 0 : if (ret)
3005 : 0 : goto err;
3006 : : }
3007 : : }
3008 [ # # ]: 0 : if (recom_used) {
3009 : : MLX5_ASSERT(at->recom_off != UINT16_MAX);
3010 : 0 : ret = mlx5_create_ipv6_ext_reformat(dev, cfg, acts, at, push_data,
3011 : : push_data_m, push_size, recom_src,
3012 : : recom_type);
3013 [ # # ]: 0 : if (ret)
3014 : 0 : goto err;
3015 : : }
3016 : : return 0;
3017 : 0 : err:
3018 : : /* If rte_errno was not initialized and reached error state. */
3019 [ # # ]: 0 : if (!rte_errno)
3020 : 0 : rte_errno = EINVAL;
3021 : 0 : err = rte_errno;
3022 : : __flow_hw_action_template_destroy(dev, acts);
3023 : 0 : return rte_flow_error_set(error, err,
3024 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3025 : : "fail to create rte table");
3026 : : }
3027 : :
3028 : : /**
3029 : : * Translate rte_flow actions to DR action.
3030 : : *
3031 : : * As the action template has already indicated the actions. Translate
3032 : : * the rte_flow actions to DR action if possible. So in flow create
3033 : : * stage we will save cycles from handing the actions' organizing.
3034 : : * For the actions with limited information, need to add these to a
3035 : : * list.
3036 : : *
3037 : : * @param[in] dev
3038 : : * Pointer to the rte_eth_dev structure.
3039 : : * @param[in] cfg
3040 : : * Pointer to the table configuration.
3041 : : * @param[in/out] acts
3042 : : * Pointer to the template HW steering DR actions.
3043 : : * @param[in] at
3044 : : * Action template.
3045 : : * @param[out] error
3046 : : * Pointer to error structure.
3047 : : *
3048 : : * @return
3049 : : * 0 on success, a negative errno otherwise and rte_errno is set.
3050 : : */
3051 : : static int
3052 : : flow_hw_translate_actions_template(struct rte_eth_dev *dev,
3053 : : const struct mlx5_flow_template_table_cfg *cfg,
3054 : : struct mlx5_hw_actions *acts,
3055 : : struct rte_flow_actions_template *at,
3056 : : struct mlx5_tbl_multi_pattern_ctx *mp_ctx,
3057 : : struct rte_flow_error *error)
3058 : : {
3059 : 0 : return __flow_hw_translate_actions_template(dev, cfg, acts, at, mp_ctx, false, error);
3060 : : }
3061 : :
3062 : : static __rte_always_inline struct mlx5dr_rule_action *
3063 : : flow_hw_get_dr_action_buffer(struct mlx5_priv *priv,
3064 : : struct rte_flow_template_table *table,
3065 : : uint8_t action_template_index,
3066 : : uint32_t queue)
3067 : : {
3068 : 0 : uint32_t offset = action_template_index * priv->nb_queue + queue;
3069 : :
3070 : 0 : return &table->rule_acts[offset].acts[0];
3071 : : }
3072 : :
3073 : : static void
3074 : 0 : flow_hw_populate_rule_acts_caches(struct rte_eth_dev *dev,
3075 : : struct rte_flow_template_table *table,
3076 : : uint8_t at_idx)
3077 : : {
3078 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
3079 : : uint32_t q;
3080 : :
3081 [ # # ]: 0 : for (q = 0; q < priv->nb_queue; ++q) {
3082 : : struct mlx5dr_rule_action *rule_acts =
3083 : 0 : flow_hw_get_dr_action_buffer(priv, table, at_idx, q);
3084 : :
3085 [ # # ]: 0 : rte_memcpy(rule_acts, table->ats[at_idx].acts.rule_acts,
3086 : : sizeof(table->ats[at_idx].acts.rule_acts));
3087 : : }
3088 : 0 : }
3089 : :
3090 : : /**
3091 : : * Translate rte_flow actions to DR action.
3092 : : *
3093 : : * @param[in] dev
3094 : : * Pointer to the rte_eth_dev structure.
3095 : : * @param[in] tbl
3096 : : * Pointer to the flow template table.
3097 : : * @param[out] error
3098 : : * Pointer to error structure.
3099 : : *
3100 : : * @return
3101 : : * 0 on success, negative value otherwise and rte_errno is set.
3102 : : */
3103 : : static int
3104 : 0 : flow_hw_translate_all_actions_templates(struct rte_eth_dev *dev,
3105 : : struct rte_flow_template_table *tbl,
3106 : : struct rte_flow_error *error)
3107 : : {
3108 : : int ret;
3109 : : uint32_t i;
3110 : :
3111 [ # # ]: 0 : for (i = 0; i < tbl->nb_action_templates; i++) {
3112 [ # # ]: 0 : if (flow_hw_translate_actions_template(dev, &tbl->cfg,
3113 : : &tbl->ats[i].acts,
3114 : : tbl->ats[i].action_template,
3115 : : &tbl->mpctx, error))
3116 : 0 : goto err;
3117 : 0 : flow_hw_populate_rule_acts_caches(dev, tbl, i);
3118 : : }
3119 [ # # ]: 0 : ret = mlx5_tbl_multi_pattern_process(dev, tbl, &tbl->mpctx.segments[0],
3120 : : rte_log2_u32(tbl->cfg.attr.nb_flows),
3121 : : error);
3122 [ # # ]: 0 : if (ret)
3123 : 0 : goto err;
3124 : : return 0;
3125 : : err:
3126 [ # # ]: 0 : while (i--)
3127 : 0 : __flow_hw_action_template_destroy(dev, &tbl->ats[i].acts);
3128 : : return -1;
3129 : : }
3130 : :
3131 : : /**
3132 : : * Get shared indirect action.
3133 : : *
3134 : : * @param[in] dev
3135 : : * Pointer to the rte_eth_dev data structure.
3136 : : * @param[in] act_data
3137 : : * Pointer to the recorded action construct data.
3138 : : * @param[in] item_flags
3139 : : * The matcher itme_flags used for RSS lookup.
3140 : : * @param[in] rule_act
3141 : : * Pointer to the shared action's destination rule DR action.
3142 : : *
3143 : : * @return
3144 : : * 0 on success, negative value otherwise and rte_errno is set.
3145 : : */
3146 : : static __rte_always_inline int
3147 : : flow_hw_shared_action_get(struct rte_eth_dev *dev,
3148 : : struct mlx5_action_construct_data *act_data,
3149 : : const uint64_t item_flags,
3150 : : struct mlx5dr_rule_action *rule_act)
3151 : : {
3152 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
3153 : 0 : struct mlx5_flow_rss_desc rss_desc = { 0 };
3154 : 0 : uint64_t hash_fields = 0;
3155 : : uint32_t hrxq_idx = 0;
3156 : : struct mlx5_hrxq *hrxq = NULL;
3157 : : int act_type = act_data->type;
3158 : :
3159 : : switch (act_type) {
3160 : : case MLX5_RTE_FLOW_ACTION_TYPE_RSS:
3161 : 0 : rss_desc.level = act_data->shared_rss.level;
3162 : 0 : rss_desc.types = act_data->shared_rss.types;
3163 : 0 : rss_desc.symmetric_hash_function = act_data->shared_rss.symmetric_hash_function;
3164 : 0 : flow_dv_hashfields_set(item_flags, &rss_desc, &hash_fields);
3165 : 0 : hrxq_idx = flow_dv_action_rss_hrxq_lookup
3166 : : (dev, act_data->shared_rss.idx, hash_fields);
3167 [ # # # # : 0 : if (hrxq_idx)
# # # # #
# # # # #
# # # # #
# ]
3168 : 0 : hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
3169 : : hrxq_idx);
3170 [ # # # # : 0 : if (hrxq) {
# # # # #
# # # # #
# # # # #
# ]
3171 : 0 : rule_act->action = hrxq->action;
3172 : : return 0;
3173 : : }
3174 : : break;
3175 : : default:
3176 : : DRV_LOG(WARNING, "Unsupported shared action type:%d",
3177 : : act_data->type);
3178 : : break;
3179 : : }
3180 : : return -1;
3181 : : }
3182 : :
3183 : : static void
3184 : 0 : flow_hw_construct_quota(struct mlx5_priv *priv,
3185 : : struct mlx5dr_rule_action *rule_act, uint32_t qid)
3186 : : {
3187 : 0 : rule_act->action = priv->quota_ctx.dr_action;
3188 : 0 : rule_act->aso_meter.offset = qid - 1;
3189 : 0 : rule_act->aso_meter.init_color =
3190 : : MLX5DR_ACTION_ASO_METER_COLOR_GREEN;
3191 : 0 : }
3192 : :
3193 : : /**
3194 : : * Construct shared indirect action.
3195 : : *
3196 : : * @param[in] dev
3197 : : * Pointer to the rte_eth_dev data structure.
3198 : : * @param[in] queue
3199 : : * The flow creation queue index.
3200 : : * @param[in] action
3201 : : * Pointer to the shared indirect rte_flow action.
3202 : : * @param[in] table
3203 : : * Pointer to the flow table.
3204 : : * @param[in] item_flags
3205 : : * Item flags.
3206 : : * @param[in] action_flags
3207 : : * Actions bit-map detected in this template.
3208 : : * @param[in, out] flow
3209 : : * Pointer to the flow containing the counter.
3210 : : * @param[in] rule_act
3211 : : * Pointer to the shared action's destination rule DR action.
3212 : : *
3213 : : * @return
3214 : : * 0 on success, negative value otherwise and rte_errno is set.
3215 : : */
3216 : : static __rte_always_inline int
3217 : : flow_hw_shared_action_construct(struct rte_eth_dev *dev, uint32_t queue,
3218 : : const struct rte_flow_action *action,
3219 : : struct rte_flow_template_table *table __rte_unused,
3220 : : const uint64_t item_flags, uint64_t action_flags,
3221 : : struct rte_flow_hw *flow,
3222 : : struct mlx5dr_rule_action *rule_act)
3223 : : {
3224 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
3225 : 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
3226 : : struct mlx5_action_construct_data act_data;
3227 : : struct mlx5_shared_action_rss *shared_rss;
3228 : : struct mlx5_aso_mtr *aso_mtr;
3229 : : struct mlx5_age_info *age_info;
3230 : : struct mlx5_hws_age_param *param;
3231 : : struct rte_flow_hw_aux *aux;
3232 : 0 : uint32_t act_idx = (uint32_t)(uintptr_t)action->conf;
3233 : 0 : uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
3234 : 0 : uint32_t idx = act_idx &
3235 : : ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
3236 : : cnt_id_t age_cnt;
3237 : :
3238 : : memset(&act_data, 0, sizeof(act_data));
3239 [ # # # # : 0 : switch (type) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3240 : 0 : case MLX5_INDIRECT_ACTION_TYPE_RSS:
3241 : 0 : act_data.type = MLX5_RTE_FLOW_ACTION_TYPE_RSS;
3242 : 0 : shared_rss = mlx5_ipool_get
3243 : 0 : (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
3244 [ # # # # : 0 : if (!shared_rss)
# # # # #
# ]
3245 : : return -1;
3246 : 0 : act_data.shared_rss.idx = idx;
3247 : 0 : act_data.shared_rss.level = shared_rss->origin.level;
3248 : 0 : act_data.shared_rss.types = !shared_rss->origin.types ?
3249 [ # # # # : 0 : RTE_ETH_RSS_IP :
# # # # #
# ]
3250 : : shared_rss->origin.types;
3251 : 0 : act_data.shared_rss.symmetric_hash_function =
3252 : 0 : MLX5_RSS_IS_SYMM(shared_rss->origin.func);
3253 : :
3254 : : if (flow_hw_shared_action_get
3255 : : (dev, &act_data, item_flags, rule_act))
3256 : : return -1;
3257 : : break;
3258 : 0 : case MLX5_INDIRECT_ACTION_TYPE_COUNT:
3259 : 0 : if (mlx5_hws_cnt_pool_get_action_offset(priv->hws_cpool,
3260 : : act_idx,
3261 : : &rule_act->action,
3262 : : &rule_act->counter.offset))
3263 : : return -1;
3264 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_CNT_ID;
3265 : 0 : flow->cnt_id = act_idx;
3266 : : break;
3267 : 0 : case MLX5_INDIRECT_ACTION_TYPE_AGE:
3268 : 0 : aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
3269 : : /*
3270 : : * Save the index with the indirect type, to recognize
3271 : : * it in flow destroy.
3272 : : */
3273 : : mlx5_flow_hw_aux_set_age_idx(flow, aux, act_idx);
3274 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_AGE_IDX;
3275 [ # # # # : 0 : if (action_flags & MLX5_FLOW_ACTION_INDIRECT_COUNT)
# # # # #
# ]
3276 : : /*
3277 : : * The mutual update for idirect AGE & COUNT will be
3278 : : * performed later after we have ID for both of them.
3279 : : */
3280 : : break;
3281 : 0 : age_info = GET_PORT_AGE_INFO(priv);
3282 : 0 : param = mlx5_ipool_get(age_info->ages_ipool, idx);
3283 [ # # # # : 0 : if (param == NULL)
# # # # #
# ]
3284 : : return -1;
3285 [ # # # # : 0 : if (action_flags & MLX5_FLOW_ACTION_COUNT) {
# # # # #
# ]
3286 [ # # # # : 0 : if (mlx5_hws_cnt_pool_get(priv->hws_cpool,
# # # # #
# # # # #
# # # # #
# ]
3287 : : ¶m->queue_id, &age_cnt,
3288 : : idx) < 0)
3289 : : return -1;
3290 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_CNT_ID;
3291 : 0 : flow->cnt_id = age_cnt;
3292 : 0 : param->nb_cnts++;
3293 : : } else {
3294 : : /*
3295 : : * Get the counter of this indirect AGE or create one
3296 : : * if doesn't exist.
3297 : : */
3298 : : age_cnt = mlx5_hws_age_cnt_get(priv, param, idx);
3299 [ # # # # : 0 : if (age_cnt == 0)
# # # # #
# ]
3300 : : return -1;
3301 : : }
3302 : 0 : if (mlx5_hws_cnt_pool_get_action_offset(priv->hws_cpool,
3303 : : age_cnt, &rule_act->action,
3304 : : &rule_act->counter.offset))
3305 : : return -1;
3306 : : break;
3307 : : case MLX5_INDIRECT_ACTION_TYPE_CT:
3308 : : if (flow_hw_ct_compile(dev, queue, idx, rule_act))
3309 : : return -1;
3310 : : break;
3311 : 0 : case MLX5_INDIRECT_ACTION_TYPE_METER_MARK:
3312 : : /* Find ASO object. */
3313 : 0 : aso_mtr = mlx5_ipool_get(pool->idx_pool, idx);
3314 [ # # # # : 0 : if (!aso_mtr)
# # # # #
# ]
3315 : : return -1;
3316 : 0 : rule_act->action = pool->action;
3317 : 0 : rule_act->aso_meter.offset = aso_mtr->offset;
3318 : : break;
3319 : 0 : case MLX5_INDIRECT_ACTION_TYPE_QUOTA:
3320 : 0 : flow_hw_construct_quota(priv, rule_act, idx);
3321 : : break;
3322 : 0 : default:
3323 : 0 : DRV_LOG(WARNING, "Unsupported shared action type:%d", type);
3324 : : break;
3325 : : }
3326 : : return 0;
3327 : : }
3328 : :
3329 : : static __rte_always_inline int
3330 : : flow_hw_mhdr_cmd_is_nop(const struct mlx5_modification_cmd *cmd)
3331 : : {
3332 : : struct mlx5_modification_cmd cmd_he = {
3333 : 0 : .data0 = rte_be_to_cpu_32(cmd->data0),
3334 : : .data1 = 0,
3335 : : };
3336 : :
3337 : 0 : return cmd_he.action_type == MLX5_MODIFICATION_TYPE_NOP;
3338 : : }
3339 : :
3340 : : /**
3341 : : * Construct flow action array.
3342 : : *
3343 : : * For action template contains dynamic actions, these actions need to
3344 : : * be updated according to the rte_flow action during flow creation.
3345 : : *
3346 : : * @param[in] dev
3347 : : * Pointer to the rte_eth_dev structure.
3348 : : * @param[in] job
3349 : : * Pointer to job descriptor.
3350 : : * @param[in] hw_acts
3351 : : * Pointer to translated actions from template.
3352 : : * @param[in] it_idx
3353 : : * Item template index the action template refer to.
3354 : : * @param[in] actions
3355 : : * Array of rte_flow action need to be checked.
3356 : : * @param[in] rule_acts
3357 : : * Array of DR rule actions to be used during flow creation..
3358 : : * @param[in] acts_num
3359 : : * Pointer to the real acts_num flow has.
3360 : : *
3361 : : * @return
3362 : : * 0 on success, negative value otherwise and rte_errno is set.
3363 : : */
3364 : : static __rte_always_inline int
3365 : : flow_hw_modify_field_construct(struct mlx5_modification_cmd *mhdr_cmd,
3366 : : struct mlx5_action_construct_data *act_data,
3367 : : const struct mlx5_hw_actions *hw_acts,
3368 : : const struct rte_flow_action *action)
3369 : : {
3370 : 0 : const struct rte_flow_action_modify_field *mhdr_action = action->conf;
3371 : 0 : uint8_t values[16] = { 0 };
3372 : : unaligned_uint32_t *value_p;
3373 : : uint32_t i;
3374 : : struct field_modify_info *field;
3375 : :
3376 [ # # # # : 0 : if (!hw_acts->mhdr)
# # # # #
# ]
3377 : : return -1;
3378 [ # # # # : 0 : if (hw_acts->mhdr->shared || act_data->modify_header.shared)
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3379 : : return 0;
3380 : : MLX5_ASSERT(mhdr_action->operation == RTE_FLOW_MODIFY_SET ||
3381 : : mhdr_action->operation == RTE_FLOW_MODIFY_ADD);
3382 [ # # # # : 0 : if (mhdr_action->src.field != RTE_FLOW_FIELD_VALUE &&
# # # # #
# ]
3383 : : mhdr_action->src.field != RTE_FLOW_FIELD_POINTER)
3384 : : return 0;
3385 [ # # # # : 0 : if (mhdr_action->src.field == RTE_FLOW_FIELD_VALUE)
# # # # #
# ]
3386 [ # # # # : 0 : rte_memcpy(values, &mhdr_action->src.value, sizeof(values));
# # # # #
# ]
3387 : : else
3388 [ # # # # : 0 : rte_memcpy(values, mhdr_action->src.pvalue, sizeof(values));
# # # # #
# ]
3389 [ # # # # : 0 : if (mhdr_action->dst.field == RTE_FLOW_FIELD_META ||
# # # # #
# ]
3390 [ # # # # : 0 : mhdr_action->dst.field == RTE_FLOW_FIELD_TAG ||
# # # # #
# ]
3391 [ # # # # : 0 : mhdr_action->dst.field == RTE_FLOW_FIELD_METER_COLOR ||
# # # # #
# ]
3392 : : mhdr_action->dst.field == (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG) {
3393 : 0 : uint8_t tag_index = flow_tag_index_get(&mhdr_action->dst);
3394 : :
3395 : : value_p = (unaligned_uint32_t *)values;
3396 [ # # # # : 0 : if (mhdr_action->dst.field == RTE_FLOW_FIELD_TAG &&
# # # # #
# # # # #
# # # # #
# ]
3397 : : tag_index == RTE_PMD_MLX5_LINEAR_HASH_TAG_INDEX)
3398 [ # # # # : 0 : *value_p = rte_cpu_to_be_32(*value_p << 16);
# # # # #
# ]
3399 : : else
3400 [ # # # # : 0 : *value_p = rte_cpu_to_be_32(*value_p);
# # # # #
# ]
3401 [ # # # # : 0 : } else if (mhdr_action->dst.field == RTE_FLOW_FIELD_GTP_PSC_QFI ||
# # # # #
# ]
3402 : : mhdr_action->dst.field == RTE_FLOW_FIELD_GENEVE_OPT_TYPE) {
3403 : : uint32_t tmp;
3404 : :
3405 : : /*
3406 : : * Both QFI and Geneve option type are passed as an uint8_t integer,
3407 : : * but it is accessed through a 2nd least significant byte of a 32-bit
3408 : : * field in modify header command.
3409 : : */
3410 : 0 : tmp = values[0];
3411 : : value_p = (unaligned_uint32_t *)values;
3412 [ # # # # : 0 : *value_p = rte_cpu_to_be_32(tmp << 8);
# # # # #
# ]
3413 : : }
3414 : 0 : i = act_data->modify_header.mhdr_cmds_off;
3415 : 0 : field = act_data->modify_header.field;
3416 : : do {
3417 : : uint32_t off_b;
3418 : : uint32_t mask;
3419 : : uint32_t data;
3420 : : const uint8_t *mask_src;
3421 : :
3422 [ # # # # : 0 : if (i >= act_data->modify_header.mhdr_cmds_end)
# # # # #
# # # # #
# # # # #
# ]
3423 : : return -1;
3424 [ # # # # : 0 : if (flow_hw_mhdr_cmd_is_nop(&mhdr_cmd[i])) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3425 : 0 : ++i;
3426 : 0 : continue;
3427 : : }
3428 : 0 : mask_src = (const uint8_t *)act_data->modify_header.mask;
3429 : 0 : mask = flow_dv_fetch_field(mask_src + field->offset, field->size);
3430 [ # # # # : 0 : if (!mask) {
# # # # #
# # # # #
# # # # #
# ]
3431 : 0 : ++field;
3432 : 0 : continue;
3433 : : }
3434 : 0 : off_b = rte_bsf32(mask);
3435 : 0 : data = flow_dv_fetch_field(values + field->offset, field->size);
3436 : : /*
3437 : : * IPv6 DSCP uses OUT_IPV6_TRAFFIC_CLASS as ID but it starts from 2
3438 : : * bits left. Shift the data left for IPv6 DSCP
3439 : : */
3440 [ # # # # : 0 : if (field->id == MLX5_MODI_OUT_IPV6_TRAFFIC_CLASS &&
# # # # #
# # # #
# ]
3441 [ # # # # : 0 : mhdr_action->dst.field == RTE_FLOW_FIELD_IPV6_DSCP)
# # ]
3442 : 0 : data <<= MLX5_IPV6_HDR_DSCP_SHIFT;
3443 : 0 : data = (data & mask) >> off_b;
3444 [ # # # # : 0 : mhdr_cmd[i++].data1 = rte_cpu_to_be_32(data);
# # # # #
# # # # #
# # # # #
# ]
3445 : 0 : ++field;
3446 [ # # # # : 0 : } while (field->size);
# # # # #
# # # # #
# # # # #
# ]
3447 : : return 0;
3448 : : }
3449 : :
3450 : : /**
3451 : : * Release any actions allocated for the flow rule during actions construction.
3452 : : *
3453 : : * @param[in] flow
3454 : : * Pointer to flow structure.
3455 : : */
3456 : : static void
3457 : 0 : flow_hw_release_actions(struct rte_eth_dev *dev,
3458 : : uint32_t queue,
3459 : : struct rte_flow_hw *flow)
3460 : : {
3461 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
3462 : 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
3463 : 0 : struct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
3464 : :
3465 [ # # ]: 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_FATE_JUMP)
3466 : 0 : flow_hw_jump_release(dev, flow->jump);
3467 [ # # ]: 0 : else if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_FATE_HRXQ)
3468 : 0 : mlx5_hrxq_obj_release(dev, flow->hrxq);
3469 [ # # ]: 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_CNT_ID)
3470 : 0 : flow_hw_age_count_release(priv, queue, flow, NULL);
3471 [ # # ]: 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_MTR_ID)
3472 : 0 : mlx5_ipool_free(pool->idx_pool, mlx5_flow_hw_aux_get_mtr_id(flow, aux));
3473 : 0 : }
3474 : :
3475 : : /**
3476 : : * Construct flow action array.
3477 : : *
3478 : : * For action template contains dynamic actions, these actions need to
3479 : : * be updated according to the rte_flow action during flow creation.
3480 : : *
3481 : : * @param[in] dev
3482 : : * Pointer to the rte_eth_dev structure.
3483 : : * @param[in] flow
3484 : : * Pointer to flow structure.
3485 : : * @param[in] ap
3486 : : * Pointer to container for temporarily constructed actions' parameters.
3487 : : * @param[in] hw_acts
3488 : : * Pointer to translated actions from template.
3489 : : * @param[in] items_flags
3490 : : * Item flags.
3491 : : * @param[in] table
3492 : : * Pointer to the template table.
3493 : : * @param[in] actions
3494 : : * Array of rte_flow action need to be checked.
3495 : : * @param[in] rule_acts
3496 : : * Array of DR rule actions to be used during flow creation..
3497 : : * @param[in] acts_num
3498 : : * Pointer to the real acts_num flow has.
3499 : : *
3500 : : * @return
3501 : : * 0 on success, negative value otherwise and rte_errno is set.
3502 : : */
3503 : : static __rte_always_inline int
3504 : : flow_hw_actions_construct(struct rte_eth_dev *dev,
3505 : : struct rte_flow_hw *flow,
3506 : : struct mlx5_flow_hw_action_params *ap,
3507 : : const struct mlx5_hw_action_template *hw_at,
3508 : : uint64_t item_flags,
3509 : : struct rte_flow_template_table *table,
3510 : : const struct rte_flow_action actions[],
3511 : : struct mlx5dr_rule_action *rule_acts,
3512 : : uint32_t queue,
3513 : : struct rte_flow_error *error)
3514 : : {
3515 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
3516 : 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
3517 : : struct mlx5_action_construct_data *act_data;
3518 : 0 : const struct rte_flow_actions_template *at = hw_at->action_template;
3519 : : const struct mlx5_hw_actions *hw_acts = &hw_at->acts;
3520 : : const struct rte_flow_action *action;
3521 : : const struct rte_flow_action_raw_encap *raw_encap_data;
3522 : : const struct rte_flow_action_ipv6_ext_push *ipv6_push;
3523 : : const struct rte_flow_item *enc_item = NULL;
3524 : : const struct rte_flow_action_ethdev *port_action = NULL;
3525 : : const struct rte_flow_action_meter *meter = NULL;
3526 : : const struct rte_flow_action_age *age = NULL;
3527 : : const struct rte_flow_action_nat64 *nat64_c = NULL;
3528 : 0 : struct rte_flow_attr attr = {
3529 : : .ingress = 1,
3530 : : };
3531 : : uint32_t ft_flag;
3532 : : int ret;
3533 : 0 : size_t encap_len = 0;
3534 : : uint32_t age_idx = 0;
3535 : : uint32_t mtr_idx = 0;
3536 : : struct mlx5_aso_mtr *aso_mtr;
3537 : : struct mlx5_multi_pattern_segment *mp_segment = NULL;
3538 : : struct rte_flow_hw_aux *aux;
3539 : :
3540 : 0 : attr.group = table->grp->group_id;
3541 : 0 : ft_flag = mlx5_hw_act_flag[!!table->grp->group_id][table->type];
3542 : 0 : if (table->type == MLX5DR_TABLE_TYPE_FDB) {
3543 : 0 : attr.transfer = 1;
3544 : : attr.ingress = 1;
3545 [ # # # # : 0 : } else if (table->type == MLX5DR_TABLE_TYPE_NIC_TX) {
# # # # #
# ]
3546 : 0 : attr.egress = 1;
3547 : 0 : attr.ingress = 0;
3548 : : } else {
3549 : : attr.ingress = 1;
3550 : : }
3551 [ # # # # : 0 : if (hw_acts->mhdr && hw_acts->mhdr->mhdr_cmds_num > 0 && !hw_acts->mhdr->shared) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3552 : 0 : uint16_t pos = hw_acts->mhdr->pos;
3553 : :
3554 : 0 : mp_segment = mlx5_multi_pattern_segment_find(table, flow->res_idx);
3555 [ # # # # : 0 : if (!mp_segment || !mp_segment->mhdr_action)
# # # # #
# # # # #
# # # # #
# ]
3556 : : return -1;
3557 : 0 : rule_acts[pos].action = mp_segment->mhdr_action;
3558 : : /* offset is relative to DR action */
3559 : 0 : rule_acts[pos].modify_header.offset =
3560 : 0 : flow->res_idx - mp_segment->head_index;
3561 : 0 : rule_acts[pos].modify_header.data =
3562 : 0 : (uint8_t *)ap->mhdr_cmd;
3563 : : MLX5_ASSERT(hw_acts->mhdr->mhdr_cmds_num <= MLX5_MHDR_MAX_CMD);
3564 : 0 : rte_memcpy(ap->mhdr_cmd, hw_acts->mhdr->mhdr_cmds,
3565 [ # # # # : 0 : sizeof(*ap->mhdr_cmd) * hw_acts->mhdr->mhdr_cmds_num);
# # # # #
# ]
3566 : : }
3567 [ # # # # : 0 : LIST_FOREACH(act_data, &hw_acts->act_list, next) {
# # # # #
# ]
3568 : : uint32_t jump_group;
3569 : : uint32_t tag;
3570 : : struct mlx5_hw_jump_action *jump;
3571 : : struct mlx5_hrxq *hrxq;
3572 : : uint32_t ct_idx;
3573 : : cnt_id_t cnt_id;
3574 : : uint32_t *cnt_queue;
3575 : : uint32_t mtr_id;
3576 : : struct rte_flow_template_table *jump_table;
3577 : :
3578 : 0 : action = &actions[act_data->action_src];
3579 : : /*
3580 : : * action template construction replaces
3581 : : * OF_SET_VLAN_VID with MODIFY_FIELD
3582 : : */
3583 : 0 : if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)
3584 : : MLX5_ASSERT(act_data->type ==
3585 : : RTE_FLOW_ACTION_TYPE_MODIFY_FIELD);
3586 : : else
3587 : : MLX5_ASSERT(action->type ==
3588 : : RTE_FLOW_ACTION_TYPE_INDIRECT ||
3589 : : (int)action->type == act_data->type);
3590 [ # # # # : 0 : switch ((int)act_data->type) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3591 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT_LIST:
3592 : 0 : act_data->indirect_list_cb(dev, act_data, action,
3593 : 0 : &rule_acts[act_data->action_dst]);
3594 : 0 : break;
3595 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT:
3596 : 0 : if (flow_hw_shared_action_construct
3597 : : (dev, queue, action, table,
3598 : 0 : item_flags, at->action_flags, flow,
3599 [ # # # # : 0 : &rule_acts[act_data->action_dst]))
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3600 : 0 : goto error;
3601 : : break;
3602 : : case RTE_FLOW_ACTION_TYPE_VOID:
3603 : : break;
3604 : 0 : case RTE_FLOW_ACTION_TYPE_MARK:
3605 : 0 : tag = mlx5_flow_mark_set
3606 : : (((const struct rte_flow_action_mark *)
3607 : 0 : (action->conf))->id);
3608 : 0 : rule_acts[act_data->action_dst].tag.value = tag;
3609 : 0 : break;
3610 : 0 : case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
3611 : 0 : rule_acts[act_data->action_dst].push_vlan.vlan_hdr =
3612 : 0 : vlan_hdr_to_be32(action);
3613 : 0 : break;
3614 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP:
3615 : 0 : jump_group = ((const struct rte_flow_action_jump *)
3616 : 0 : action->conf)->group;
3617 : 0 : jump = flow_hw_jump_action_register
3618 : 0 : (dev, &table->cfg, jump_group, NULL);
3619 [ # # # # : 0 : if (!jump)
# # # # #
# ]
3620 : 0 : goto error;
3621 : 0 : rule_acts[act_data->action_dst].action =
3622 [ # # # # : 0 : (!!attr.group) ? jump->hws_action : jump->root_action;
# # # # #
# ]
3623 : 0 : flow->jump = jump;
3624 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_FATE_JUMP;
3625 : 0 : break;
3626 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
3627 : : case RTE_FLOW_ACTION_TYPE_QUEUE:
3628 : 0 : hrxq = flow_hw_tir_action_register(dev, ft_flag, action);
3629 [ # # # # : 0 : if (!hrxq)
# # # # #
# ]
3630 : 0 : goto error;
3631 : 0 : rule_acts[act_data->action_dst].action = hrxq->action;
3632 : 0 : flow->hrxq = hrxq;
3633 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_FATE_HRXQ;
3634 : 0 : break;
3635 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_RSS:
3636 : 0 : if (flow_hw_shared_action_get
3637 : : (dev, act_data, item_flags,
3638 : 0 : &rule_acts[act_data->action_dst]))
3639 : 0 : goto error;
3640 : : break;
3641 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
3642 : 0 : enc_item = ((const struct rte_flow_action_vxlan_encap *)
3643 : 0 : action->conf)->definition;
3644 [ # # # # : 0 : if (flow_dv_convert_encap_data(enc_item, ap->encap_data, &encap_len, NULL))
# # # # #
# ]
3645 : 0 : goto error;
3646 : : break;
3647 : 0 : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
3648 : 0 : enc_item = ((const struct rte_flow_action_nvgre_encap *)
3649 : 0 : action->conf)->definition;
3650 [ # # # # : 0 : if (flow_dv_convert_encap_data(enc_item, ap->encap_data, &encap_len, NULL))
# # # # #
# ]
3651 : 0 : goto error;
3652 : : break;
3653 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
3654 : 0 : raw_encap_data =
3655 : : (const struct rte_flow_action_raw_encap *)
3656 : : action->conf;
3657 : : MLX5_ASSERT(raw_encap_data->size == act_data->encap.len);
3658 [ # # # # : 0 : if (unlikely(act_data->encap.len > MLX5_ENCAP_MAX_LEN))
# # # # #
# ]
3659 : : return -1;
3660 [ # # # # : 0 : rte_memcpy(ap->encap_data, raw_encap_data->data, act_data->encap.len);
# # # # #
# ]
3661 : : break;
3662 : 0 : case RTE_FLOW_ACTION_TYPE_IPV6_EXT_PUSH:
3663 : 0 : ipv6_push =
3664 : : (const struct rte_flow_action_ipv6_ext_push *)action->conf;
3665 : : MLX5_ASSERT(ipv6_push->size == act_data->ipv6_ext.len);
3666 [ # # # # : 0 : if (unlikely(act_data->ipv6_ext.len > MLX5_PUSH_MAX_LEN))
# # # # #
# ]
3667 : : return -1;
3668 [ # # # # : 0 : rte_memcpy(ap->ipv6_push_data, ipv6_push->data,
# # # # #
# ]
3669 : : act_data->ipv6_ext.len);
3670 : : break;
3671 : 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
3672 [ # # # # : 0 : if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)
# # # # #
# ]
3673 : 0 : ret = flow_hw_set_vlan_vid_construct(dev, ap->mhdr_cmd,
3674 : : act_data,
3675 : : hw_acts,
3676 : : action);
3677 : : else
3678 [ # # # # : 0 : ret = flow_hw_modify_field_construct(ap->mhdr_cmd,
# # # # #
# ]
3679 : : act_data,
3680 : : hw_acts,
3681 : : action);
3682 [ # # # # : 0 : if (ret)
# # # # #
# ]
3683 : 0 : goto error;
3684 : : break;
3685 : 0 : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
3686 : 0 : port_action = action->conf;
3687 [ # # # # : 0 : if (!priv->hw_vport[port_action->port_id])
# # # # #
# ]
3688 : 0 : goto error;
3689 : 0 : rule_acts[act_data->action_dst].action =
3690 : : priv->hw_vport[port_action->port_id];
3691 : 0 : break;
3692 : 0 : case RTE_FLOW_ACTION_TYPE_QUOTA:
3693 : 0 : flow_hw_construct_quota(priv,
3694 : 0 : rule_acts + act_data->action_dst,
3695 : : act_data->shared_meter.id);
3696 : 0 : break;
3697 : 0 : case RTE_FLOW_ACTION_TYPE_METER:
3698 : 0 : meter = action->conf;
3699 : 0 : mtr_id = meter->mtr_id;
3700 : 0 : aso_mtr = mlx5_aso_meter_by_idx(priv, mtr_id);
3701 : 0 : rule_acts[act_data->action_dst].action =
3702 : 0 : priv->mtr_bulk.action;
3703 : 0 : rule_acts[act_data->action_dst].aso_meter.offset =
3704 : 0 : aso_mtr->offset;
3705 : 0 : jump = flow_hw_jump_action_register
3706 : 0 : (dev, &table->cfg, aso_mtr->fm.group, NULL);
3707 [ # # # # : 0 : if (!jump)
# # # # #
# ]
3708 : 0 : goto error;
3709 : : MLX5_ASSERT
3710 : : (!rule_acts[act_data->action_dst + 1].action);
3711 : 0 : rule_acts[act_data->action_dst + 1].action =
3712 [ # # # # : 0 : (!!attr.group) ? jump->hws_action :
# # # # #
# ]
3713 : : jump->root_action;
3714 : 0 : flow->jump = jump;
3715 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_FATE_JUMP;
3716 [ # # # # : 0 : if (mlx5_aso_mtr_wait(priv, aso_mtr, true))
# # # # #
# ]
3717 : 0 : goto error;
3718 : : break;
3719 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
3720 : 0 : aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
3721 : 0 : age = action->conf;
3722 : : /*
3723 : : * First, create the AGE parameter, then create its
3724 : : * counter later:
3725 : : * Regular counter - in next case.
3726 : : * Indirect counter - update it after the loop.
3727 : : */
3728 : 0 : age_idx = mlx5_hws_age_action_create(priv, queue, 0,
3729 : : age,
3730 : : flow->res_idx,
3731 : : error);
3732 [ # # # # : 0 : if (age_idx == 0)
# # # # #
# ]
3733 : 0 : goto error;
3734 : : mlx5_flow_hw_aux_set_age_idx(flow, aux, age_idx);
3735 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_AGE_IDX;
3736 [ # # # # : 0 : if (at->action_flags & MLX5_FLOW_ACTION_INDIRECT_COUNT)
# # # # #
# ]
3737 : : /*
3738 : : * When AGE uses indirect counter, no need to
3739 : : * create counter but need to update it with the
3740 : : * AGE parameter, will be done after the loop.
3741 : : */
3742 : : break;
3743 : : /* Fall-through. */
3744 : : case RTE_FLOW_ACTION_TYPE_COUNT:
3745 : : cnt_queue = mlx5_hws_cnt_get_queue(priv, &queue);
3746 : : ret = mlx5_hws_cnt_pool_get(priv->hws_cpool, cnt_queue, &cnt_id, age_idx);
3747 [ # # # # : 0 : if (ret != 0) {
# # # # #
# ]
3748 : 0 : rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_ACTION,
3749 : : action, "Failed to allocate flow counter");
3750 : 0 : goto error;
3751 : : }
3752 : 0 : ret = mlx5_hws_cnt_pool_get_action_offset
3753 : : (priv->hws_cpool,
3754 : : cnt_id,
3755 : : &rule_acts[act_data->action_dst].action,
3756 : 0 : &rule_acts[act_data->action_dst].counter.offset
3757 : : );
3758 : : if (ret != 0)
3759 : : goto error;
3760 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_CNT_ID;
3761 : 0 : flow->cnt_id = cnt_id;
3762 : 0 : break;
3763 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
3764 : 0 : ret = mlx5_hws_cnt_pool_get_action_offset
3765 : : (priv->hws_cpool,
3766 : : act_data->shared_counter.id,
3767 : : &rule_acts[act_data->action_dst].action,
3768 : 0 : &rule_acts[act_data->action_dst].counter.offset
3769 : : );
3770 : : if (ret != 0)
3771 : : goto error;
3772 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_CNT_ID;
3773 : 0 : flow->cnt_id = act_data->shared_counter.id;
3774 : 0 : break;
3775 : 0 : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
3776 : 0 : ct_idx = MLX5_INDIRECT_ACTION_IDX_GET(action->conf);
3777 : 0 : if (flow_hw_ct_compile(dev, queue, ct_idx,
3778 : 0 : &rule_acts[act_data->action_dst]))
3779 : 0 : goto error;
3780 : : break;
3781 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_METER_MARK:
3782 : 0 : mtr_id = act_data->shared_meter.id &
3783 : : ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
3784 : : /* Find ASO object. */
3785 : 0 : aso_mtr = mlx5_ipool_get(pool->idx_pool, mtr_id);
3786 [ # # # # : 0 : if (!aso_mtr)
# # # # #
# ]
3787 : 0 : goto error;
3788 : 0 : rule_acts[act_data->action_dst].action =
3789 : 0 : pool->action;
3790 : 0 : rule_acts[act_data->action_dst].aso_meter.offset =
3791 : 0 : aso_mtr->offset;
3792 : 0 : break;
3793 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
3794 : : /*
3795 : : * Allocate meter directly will slow down flow
3796 : : * insertion rate.
3797 : : */
3798 : : ret = flow_hw_meter_mark_compile(dev,
3799 : 0 : act_data->action_dst, action,
3800 : : rule_acts, &mtr_idx, MLX5_HW_INV_QUEUE, error);
3801 : : if (ret != 0)
3802 : 0 : goto error;
3803 : 0 : aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
3804 : : mlx5_flow_hw_aux_set_mtr_id(flow, aux, mtr_idx);
3805 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_MTR_ID;
3806 : 0 : break;
3807 : 0 : case RTE_FLOW_ACTION_TYPE_NAT64:
3808 : 0 : nat64_c = action->conf;
3809 : 0 : rule_acts[act_data->action_dst].action =
3810 : 0 : priv->action_nat64[table->type][nat64_c->type];
3811 : 0 : break;
3812 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
3813 : 0 : jump_table = ((const struct rte_flow_action_jump_to_table_index *)
3814 : 0 : action->conf)->table;
3815 [ # # # # : 0 : if (likely(!rte_flow_template_table_resizable(dev->data->port_id,
# # # # #
# ]
3816 : : &table->cfg.attr))) {
3817 : 0 : rule_acts[act_data->action_dst].action =
3818 : 0 : jump_table->matcher_info[0].jump;
3819 : : } else {
3820 : : uint32_t selector;
3821 : 0 : rte_rwlock_read_lock(&table->matcher_replace_rwlk);
3822 : 0 : selector = table->matcher_selector;
3823 : 0 : rule_acts[act_data->action_dst].action =
3824 : 0 : jump_table->matcher_info[selector].jump;
3825 : 0 : rte_rwlock_read_unlock(&table->matcher_replace_rwlk);
3826 : : }
3827 : 0 : rule_acts[act_data->action_dst].jump_to_matcher.offset =
3828 : : ((const struct rte_flow_action_jump_to_table_index *)
3829 : 0 : action->conf)->index;
3830 : 0 : break;
3831 : : default:
3832 : : break;
3833 : : }
3834 : : }
3835 [ # # # # : 0 : if (at->action_flags & MLX5_FLOW_ACTION_INDIRECT_COUNT) {
# # # # #
# ]
3836 : : /* If indirect count is used, then CNT_ID flag should be set. */
3837 : : MLX5_ASSERT(flow->flags & MLX5_FLOW_HW_FLOW_FLAG_CNT_ID);
3838 [ # # # # : 0 : if (at->action_flags & MLX5_FLOW_ACTION_INDIRECT_AGE) {
# # # # #
# ]
3839 : : /* If indirect AGE is used, then AGE_IDX flag should be set. */
3840 : : MLX5_ASSERT(flow->flags & MLX5_FLOW_HW_FLOW_FLAG_AGE_IDX);
3841 : 0 : aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
3842 : 0 : age_idx = mlx5_flow_hw_aux_get_age_idx(flow, aux) &
3843 : : MLX5_HWS_AGE_IDX_MASK;
3844 [ # # # # : 0 : if (mlx5_hws_cnt_age_get(priv->hws_cpool, flow->cnt_id) != age_idx)
# # # # #
# # # # #
# # # # #
# ]
3845 : : /*
3846 : : * This is first use of this indirect counter
3847 : : * for this indirect AGE, need to increase the
3848 : : * number of counters.
3849 : : */
3850 : : mlx5_hws_age_nb_cnt_increase(priv, age_idx);
3851 : : }
3852 : : /*
3853 : : * Update this indirect counter the indirect/direct AGE in which
3854 : : * using it.
3855 : : */
3856 [ # # # # : 0 : mlx5_hws_cnt_age_set(priv->hws_cpool, flow->cnt_id, age_idx);
# # # # #
# ]
3857 : : }
3858 [ # # # # : 0 : if (hw_acts->encap_decap && !hw_acts->encap_decap->shared) {
# # # # #
# # # # #
# # # # #
# ]
3859 [ # # # # : 0 : int ix = mlx5_multi_pattern_reformat_to_index(hw_acts->encap_decap->action_type);
# # # # #
# ]
3860 : 0 : struct mlx5dr_rule_action *ra = &rule_acts[hw_acts->encap_decap_pos];
3861 : :
3862 [ # # # # : 0 : if (ix < 0)
# # # # #
# ]
3863 : 0 : goto error;
3864 [ # # # # : 0 : if (!mp_segment)
# # # # #
# ]
3865 : 0 : mp_segment = mlx5_multi_pattern_segment_find(table, flow->res_idx);
3866 [ # # # # : 0 : if (!mp_segment || !mp_segment->reformat_action[ix])
# # # # #
# # # # #
# # # # #
# ]
3867 : 0 : goto error;
3868 : 0 : ra->action = mp_segment->reformat_action[ix];
3869 : : /* reformat offset is relative to selected DR action */
3870 : 0 : ra->reformat.offset = flow->res_idx - mp_segment->head_index;
3871 : 0 : ra->reformat.data = ap->encap_data;
3872 : : }
3873 [ # # # # : 0 : if (hw_acts->push_remove && !hw_acts->push_remove->shared) {
# # # # #
# # # # #
# # # # #
# ]
3874 : 0 : rule_acts[hw_acts->push_remove_pos].ipv6_ext.offset =
3875 : 0 : flow->res_idx - 1;
3876 : 0 : rule_acts[hw_acts->push_remove_pos].ipv6_ext.header = ap->ipv6_push_data;
3877 : : }
3878 [ # # # # : 0 : if (mlx5_hws_cnt_id_valid(hw_acts->cnt_id)) {
# # # # #
# ]
3879 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_CNT_ID;
3880 : 0 : flow->cnt_id = hw_acts->cnt_id;
3881 : : }
3882 : : return 0;
3883 : :
3884 : 0 : error:
3885 : 0 : flow_hw_release_actions(dev, queue, flow);
3886 : 0 : rte_errno = EINVAL;
3887 : : return -rte_errno;
3888 : : }
3889 : :
3890 : : static const struct rte_flow_item *
3891 : 0 : flow_hw_get_rule_items(struct rte_eth_dev *dev,
3892 : : const struct rte_flow_template_table *table,
3893 : : const struct rte_flow_item items[],
3894 : : uint8_t pattern_template_index,
3895 : : struct mlx5_flow_hw_pattern_params *pp)
3896 : : {
3897 : 0 : struct rte_flow_pattern_template *pt = table->its[pattern_template_index];
3898 : :
3899 : : /* Only one implicit item can be added to flow rule pattern. */
3900 : : MLX5_ASSERT(!pt->implicit_port || !pt->implicit_tag);
3901 : : /* At least one item was allocated in pattern params for items. */
3902 : : MLX5_ASSERT(MLX5_HW_MAX_ITEMS >= 1);
3903 [ # # ]: 0 : if (pt->implicit_port) {
3904 [ # # ]: 0 : if (pt->orig_item_nb + 1 > MLX5_HW_MAX_ITEMS) {
3905 : 0 : rte_errno = ENOMEM;
3906 : 0 : return NULL;
3907 : : }
3908 : : /* Set up represented port item in pattern params. */
3909 : 0 : pp->port_spec = (struct rte_flow_item_ethdev){
3910 : 0 : .port_id = dev->data->port_id,
3911 : : };
3912 : 0 : pp->items[0] = (struct rte_flow_item){
3913 : : .type = RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT,
3914 : 0 : .spec = &pp->port_spec,
3915 : : };
3916 [ # # ]: 0 : rte_memcpy(&pp->items[1], items, sizeof(*items) * pt->orig_item_nb);
3917 : 0 : return pp->items;
3918 [ # # ]: 0 : } else if (pt->implicit_tag) {
3919 [ # # ]: 0 : if (pt->orig_item_nb + 1 > MLX5_HW_MAX_ITEMS) {
3920 : 0 : rte_errno = ENOMEM;
3921 : 0 : return NULL;
3922 : : }
3923 : : /* Set up tag item in pattern params. */
3924 : 0 : pp->tag_spec = (struct rte_flow_item_tag){
3925 : : .data = flow_hw_tx_tag_regc_value(dev),
3926 : : };
3927 : 0 : pp->items[0] = (struct rte_flow_item){
3928 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_TAG,
3929 : 0 : .spec = &pp->tag_spec,
3930 : : };
3931 : 0 : rte_memcpy(&pp->items[1], items, sizeof(*items) * pt->orig_item_nb);
3932 : 0 : return pp->items;
3933 : : } else {
3934 : : return items;
3935 : : }
3936 : : }
3937 : :
3938 : : /**
3939 : : * Enqueue HW steering flow creation.
3940 : : *
3941 : : * The flow will be applied to the HW only if the postpone bit is not set or
3942 : : * the extra push function is called.
3943 : : * The flow creation status should be checked from dequeue result.
3944 : : *
3945 : : * @param[in] dev
3946 : : * Pointer to the rte_eth_dev structure.
3947 : : * @param[in] queue
3948 : : * The queue to create the flow.
3949 : : * @param[in] attr
3950 : : * Pointer to the flow operation attributes.
3951 : : * @param[in] table
3952 : : * Pointer to the template table.
3953 : : * @param[in] insertion_type
3954 : : * Insertion type for flow rules.
3955 : : * @param[in] rule_index
3956 : : * The item pattern flow follows from the table.
3957 : : * @param[in] items
3958 : : * Items with flow spec value.
3959 : : * @param[in] pattern_template_index
3960 : : * The item pattern flow follows from the table.
3961 : : * @param[in] actions
3962 : : * Action with flow spec value.
3963 : : * @param[in] action_template_index
3964 : : * The action pattern flow follows from the table.
3965 : : * @param[in] user_data
3966 : : * Pointer to the user_data.
3967 : : * @param[out] error
3968 : : * Pointer to error structure.
3969 : : *
3970 : : * @return
3971 : : * Flow pointer on success, NULL otherwise and rte_errno is set.
3972 : : */
3973 : : static __rte_always_inline struct rte_flow *
3974 : : flow_hw_async_flow_create_generic(struct rte_eth_dev *dev,
3975 : : uint32_t queue,
3976 : : const struct rte_flow_op_attr *attr,
3977 : : struct rte_flow_template_table *table,
3978 : : enum rte_flow_table_insertion_type insertion_type,
3979 : : uint32_t rule_index,
3980 : : const struct rte_flow_item items[],
3981 : : uint8_t pattern_template_index,
3982 : : const struct rte_flow_action actions[],
3983 : : uint8_t action_template_index,
3984 : : void *user_data,
3985 : : struct rte_flow_error *error)
3986 : : {
3987 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
3988 : 0 : struct mlx5dr_rule_attr rule_attr = {
3989 : : .queue_id = queue,
3990 : : .user_data = user_data,
3991 : 0 : .burst = attr->postpone,
3992 : : };
3993 : : struct mlx5dr_rule_action *rule_acts;
3994 : : struct rte_flow_hw *flow = NULL;
3995 : : const struct rte_flow_item *rule_items;
3996 : 0 : struct rte_flow_error sub_error = { 0 };
3997 : 0 : uint32_t flow_idx = 0;
3998 : 0 : uint32_t res_idx = 0;
3999 : : int ret;
4000 : :
4001 : 0 : if (mlx5_fp_debug_enabled()) {
4002 [ # # # # : 0 : if (flow_hw_async_create_validate(dev, queue, table, insertion_type, rule_index,
# # ]
4003 : : items, pattern_template_index, actions, action_template_index, error))
4004 : : return NULL;
4005 : : }
4006 : 0 : flow = mlx5_ipool_malloc(table->flow, &flow_idx);
4007 [ # # # # : 0 : if (!flow) {
# # ]
4008 : 0 : rte_errno = ENOMEM;
4009 : 0 : goto error;
4010 : : }
4011 : : rule_acts = flow_hw_get_dr_action_buffer(priv, table, action_template_index, queue);
4012 : : /*
4013 : : * Set the table here in order to know the destination table
4014 : : * when free the flow afterward.
4015 : : */
4016 : 0 : flow->table = table;
4017 : 0 : flow->mt_idx = pattern_template_index;
4018 : 0 : flow->idx = flow_idx;
4019 [ # # # # : 0 : if (table->resource) {
# # ]
4020 : 0 : mlx5_ipool_malloc(table->resource, &res_idx);
4021 [ # # # # : 0 : if (!res_idx) {
# # ]
4022 : 0 : rte_errno = ENOMEM;
4023 : 0 : goto error;
4024 : : }
4025 : 0 : flow->res_idx = res_idx;
4026 : : } else {
4027 : 0 : flow->res_idx = flow_idx;
4028 : : }
4029 : 0 : flow->flags = 0;
4030 : : /*
4031 : : * Set the flow operation type here in order to know if the flow memory
4032 : : * should be freed or not when get the result from dequeue.
4033 : : */
4034 : 0 : flow->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_CREATE;
4035 : 0 : flow->user_data = user_data;
4036 : 0 : rule_attr.user_data = flow;
4037 : : /*
4038 : : * Indexed pool returns 1-based indices, but mlx5dr expects 0-based indices
4039 : : * for rule insertion hints.
4040 : : */
4041 [ # # # # ]: 0 : flow->rule_idx = (rule_index == UINT32_MAX) ? flow->res_idx - 1 : rule_index;
4042 : 0 : rule_attr.rule_idx = flow->rule_idx;
4043 : : /*
4044 : : * Construct the flow actions based on the input actions.
4045 : : * The implicitly appended action is always fixed, like metadata
4046 : : * copy action from FDB to NIC Rx.
4047 : : * No need to copy and contrust a new "actions" list based on the
4048 : : * user's input, in order to save the cost.
4049 : : */
4050 : 0 : if (flow_hw_actions_construct(dev, flow, &priv->hw_q[queue].ap,
4051 : 0 : &table->ats[action_template_index],
4052 [ # # # # : 0 : table->its[pattern_template_index]->item_flags,
# # ]
4053 : : flow->table, actions,
4054 : : rule_acts, queue, &sub_error))
4055 : 0 : goto error;
4056 : 0 : rule_items = flow_hw_get_rule_items(dev, table, items,
4057 : 0 : pattern_template_index, &priv->hw_q[queue].pp);
4058 [ # # # # : 0 : if (!rule_items)
# # ]
4059 : 0 : goto error;
4060 [ # # # # : 0 : if (likely(!rte_flow_template_table_resizable(dev->data->port_id, &table->cfg.attr))) {
# # ]
4061 : 0 : ret = mlx5dr_rule_create(table->matcher_info[0].matcher,
4062 : : pattern_template_index, rule_items,
4063 : : action_template_index, rule_acts,
4064 : : &rule_attr,
4065 : 0 : (struct mlx5dr_rule *)flow->rule);
4066 : : } else {
4067 : 0 : struct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
4068 : : uint32_t selector;
4069 : :
4070 : 0 : flow->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_CREATE;
4071 : 0 : rte_rwlock_read_lock(&table->matcher_replace_rwlk);
4072 : 0 : selector = table->matcher_selector;
4073 : 0 : ret = mlx5dr_rule_create(table->matcher_info[selector].matcher,
4074 : : pattern_template_index, rule_items,
4075 : : action_template_index, rule_acts,
4076 : : &rule_attr,
4077 : 0 : (struct mlx5dr_rule *)flow->rule);
4078 : 0 : rte_rwlock_read_unlock(&table->matcher_replace_rwlk);
4079 : 0 : aux->matcher_selector = selector;
4080 : 0 : flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_MATCHER_SELECTOR;
4081 : : }
4082 [ # # # # : 0 : if (likely(!ret)) {
# # ]
4083 : 0 : flow_hw_q_inc_flow_ops(priv, queue);
4084 : 0 : return (struct rte_flow *)flow;
4085 : : }
4086 : 0 : error:
4087 [ # # # # : 0 : if (table->resource && res_idx)
# # # # #
# # # ]
4088 : 0 : mlx5_ipool_free(table->resource, res_idx);
4089 [ # # # # : 0 : if (flow_idx)
# # ]
4090 : 0 : mlx5_ipool_free(table->flow, flow_idx);
4091 [ # # # # : 0 : if (sub_error.cause != RTE_FLOW_ERROR_TYPE_NONE && error != NULL)
# # # # #
# # # ]
4092 : 0 : *error = sub_error;
4093 : : else
4094 : 0 : rte_flow_error_set(error, rte_errno,
4095 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4096 : : "fail to create rte flow");
4097 : : return NULL;
4098 : : }
4099 : :
4100 : : static struct rte_flow *
4101 : 0 : flow_hw_async_flow_create(struct rte_eth_dev *dev,
4102 : : uint32_t queue,
4103 : : const struct rte_flow_op_attr *attr,
4104 : : struct rte_flow_template_table *table,
4105 : : const struct rte_flow_item items[],
4106 : : uint8_t pattern_template_index,
4107 : : const struct rte_flow_action actions[],
4108 : : uint8_t action_template_index,
4109 : : void *user_data,
4110 : : struct rte_flow_error *error)
4111 : : {
4112 : : uint32_t rule_index = UINT32_MAX;
4113 : :
4114 [ # # ]: 0 : return flow_hw_async_flow_create_generic(dev, queue, attr, table,
4115 : : RTE_FLOW_TABLE_INSERTION_TYPE_PATTERN, rule_index,
4116 : : items, pattern_template_index, actions, action_template_index,
4117 : : user_data, error);
4118 : : }
4119 : :
4120 : : static struct rte_flow *
4121 : 0 : flow_hw_async_flow_create_by_index(struct rte_eth_dev *dev,
4122 : : uint32_t queue,
4123 : : const struct rte_flow_op_attr *attr,
4124 : : struct rte_flow_template_table *table,
4125 : : uint32_t rule_index,
4126 : : const struct rte_flow_action actions[],
4127 : : uint8_t action_template_index,
4128 : : void *user_data,
4129 : : struct rte_flow_error *error)
4130 : : {
4131 : 0 : struct rte_flow_item items[] = {{.type = RTE_FLOW_ITEM_TYPE_END,}};
4132 : : uint8_t pattern_template_index = 0;
4133 : :
4134 [ # # ]: 0 : return flow_hw_async_flow_create_generic(dev, queue, attr, table,
4135 : : RTE_FLOW_TABLE_INSERTION_TYPE_INDEX, rule_index,
4136 : : items, pattern_template_index, actions, action_template_index,
4137 : : user_data, error);
4138 : : }
4139 : :
4140 : : static struct rte_flow *
4141 : 0 : flow_hw_async_flow_create_by_index_with_pattern(struct rte_eth_dev *dev,
4142 : : uint32_t queue,
4143 : : const struct rte_flow_op_attr *attr,
4144 : : struct rte_flow_template_table *table,
4145 : : uint32_t rule_index,
4146 : : const struct rte_flow_item items[],
4147 : : uint8_t pattern_template_index,
4148 : : const struct rte_flow_action actions[],
4149 : : uint8_t action_template_index,
4150 : : void *user_data,
4151 : : struct rte_flow_error *error)
4152 : : {
4153 [ # # ]: 0 : return flow_hw_async_flow_create_generic(dev, queue, attr, table,
4154 : : RTE_FLOW_TABLE_INSERTION_TYPE_INDEX_WITH_PATTERN, rule_index,
4155 : : items, pattern_template_index, actions, action_template_index,
4156 : : user_data, error);
4157 : : }
4158 : :
4159 : : /**
4160 : : * Enqueue HW steering flow update.
4161 : : *
4162 : : * The flow will be applied to the HW only if the postpone bit is not set or
4163 : : * the extra push function is called.
4164 : : * The flow destruction status should be checked from dequeue result.
4165 : : *
4166 : : * @param[in] dev
4167 : : * Pointer to the rte_eth_dev structure.
4168 : : * @param[in] queue
4169 : : * The queue to destroy the flow.
4170 : : * @param[in] attr
4171 : : * Pointer to the flow operation attributes.
4172 : : * @param[in] flow
4173 : : * Pointer to the flow to be destroyed.
4174 : : * @param[in] actions
4175 : : * Action with flow spec value.
4176 : : * @param[in] action_template_index
4177 : : * The action pattern flow follows from the table.
4178 : : * @param[in] user_data
4179 : : * Pointer to the user_data.
4180 : : * @param[out] error
4181 : : * Pointer to error structure.
4182 : : *
4183 : : * @return
4184 : : * 0 on success, negative value otherwise and rte_errno is set.
4185 : : */
4186 : : static int
4187 : 0 : flow_hw_async_flow_update(struct rte_eth_dev *dev,
4188 : : uint32_t queue,
4189 : : const struct rte_flow_op_attr *attr,
4190 : : struct rte_flow *flow,
4191 : : const struct rte_flow_action actions[],
4192 : : uint8_t action_template_index,
4193 : : void *user_data,
4194 : : struct rte_flow_error *error)
4195 : : {
4196 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4197 : 0 : struct mlx5dr_rule_attr rule_attr = {
4198 : : .queue_id = queue,
4199 : : .user_data = user_data,
4200 : 0 : .burst = attr->postpone,
4201 : : };
4202 : : struct mlx5dr_rule_action *rule_acts;
4203 : : struct rte_flow_hw *of = (struct rte_flow_hw *)flow;
4204 : : struct rte_flow_hw *nf;
4205 : : struct rte_flow_hw_aux *aux;
4206 : 0 : struct rte_flow_template_table *table = of->table;
4207 : 0 : uint32_t res_idx = 0;
4208 : : int ret;
4209 : :
4210 [ # # ]: 0 : if (mlx5_fp_debug_enabled()) {
4211 [ # # ]: 0 : if (flow_hw_async_update_validate(dev, queue, of, actions, action_template_index,
4212 : : error))
4213 : 0 : return -rte_errno;
4214 : : }
4215 : 0 : aux = mlx5_flow_hw_aux(dev->data->port_id, of);
4216 [ # # ]: 0 : nf = &aux->upd_flow;
4217 : : memset(nf, 0, sizeof(struct rte_flow_hw));
4218 : 0 : rule_acts = flow_hw_get_dr_action_buffer(priv, table, action_template_index, queue);
4219 : : /*
4220 : : * Set the table here in order to know the destination table
4221 : : * when free the flow afterwards.
4222 : : */
4223 : 0 : nf->table = table;
4224 : 0 : nf->mt_idx = of->mt_idx;
4225 : 0 : nf->idx = of->idx;
4226 [ # # ]: 0 : if (table->resource) {
4227 : 0 : mlx5_ipool_malloc(table->resource, &res_idx);
4228 [ # # ]: 0 : if (!res_idx) {
4229 : 0 : rte_errno = ENOMEM;
4230 : 0 : goto error;
4231 : : }
4232 : 0 : nf->res_idx = res_idx;
4233 : : } else {
4234 : 0 : nf->res_idx = of->res_idx;
4235 : : }
4236 : 0 : nf->flags = 0;
4237 : : /* Indicate the construction function to set the proper fields. */
4238 : 0 : nf->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE;
4239 : : /*
4240 : : * Indexed pool returns 1-based indices, but mlx5dr expects 0-based indices
4241 : : * for rule insertion hints.
4242 : : * If there is only one STE, the update will be atomic by nature.
4243 : : */
4244 : 0 : nf->rule_idx = nf->res_idx - 1;
4245 : 0 : rule_attr.rule_idx = nf->rule_idx;
4246 : : /*
4247 : : * Construct the flow actions based on the input actions.
4248 : : * The implicitly appended action is always fixed, like metadata
4249 : : * copy action from FDB to NIC Rx.
4250 : : * No need to copy and contrust a new "actions" list based on the
4251 : : * user's input, in order to save the cost.
4252 : : */
4253 : 0 : if (flow_hw_actions_construct(dev, nf, &priv->hw_q[queue].ap,
4254 : 0 : &table->ats[action_template_index],
4255 [ # # ]: 0 : table->its[nf->mt_idx]->item_flags,
4256 : : table, actions,
4257 : : rule_acts, queue, error)) {
4258 : 0 : rte_errno = EINVAL;
4259 : 0 : goto error;
4260 : : }
4261 : : /*
4262 : : * Set the flow operation type here in order to know if the flow memory
4263 : : * should be freed or not when get the result from dequeue.
4264 : : */
4265 : 0 : of->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE;
4266 : 0 : of->user_data = user_data;
4267 : 0 : of->flags |= MLX5_FLOW_HW_FLOW_FLAG_UPD_FLOW;
4268 : 0 : rule_attr.user_data = of;
4269 : 0 : ret = mlx5dr_rule_action_update((struct mlx5dr_rule *)of->rule,
4270 : : action_template_index, rule_acts, &rule_attr);
4271 [ # # ]: 0 : if (likely(!ret)) {
4272 : 0 : flow_hw_q_inc_flow_ops(priv, queue);
4273 : 0 : return 0;
4274 : : }
4275 : 0 : error:
4276 [ # # # # ]: 0 : if (table->resource && res_idx)
4277 : 0 : mlx5_ipool_free(table->resource, res_idx);
4278 : 0 : return rte_flow_error_set(error, rte_errno,
4279 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4280 : : "fail to update rte flow");
4281 : : }
4282 : :
4283 : : /**
4284 : : * Enqueue HW steering flow destruction.
4285 : : *
4286 : : * The flow will be applied to the HW only if the postpone bit is not set or
4287 : : * the extra push function is called.
4288 : : * The flow destruction status should be checked from dequeue result.
4289 : : *
4290 : : * @param[in] dev
4291 : : * Pointer to the rte_eth_dev structure.
4292 : : * @param[in] queue
4293 : : * The queue to destroy the flow.
4294 : : * @param[in] attr
4295 : : * Pointer to the flow operation attributes.
4296 : : * @param[in] flow
4297 : : * Pointer to the flow to be destroyed.
4298 : : * @param[in] user_data
4299 : : * Pointer to the user_data.
4300 : : * @param[out] error
4301 : : * Pointer to error structure.
4302 : : *
4303 : : * @return
4304 : : * 0 on success, negative value otherwise and rte_errno is set.
4305 : : */
4306 : : static int
4307 : 0 : flow_hw_async_flow_destroy(struct rte_eth_dev *dev,
4308 : : uint32_t queue,
4309 : : const struct rte_flow_op_attr *attr,
4310 : : struct rte_flow *flow,
4311 : : void *user_data,
4312 : : struct rte_flow_error *error)
4313 : : {
4314 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4315 : 0 : struct mlx5dr_rule_attr rule_attr = {
4316 : : .queue_id = queue,
4317 : : .user_data = user_data,
4318 : 0 : .burst = attr->postpone,
4319 : : };
4320 : : struct rte_flow_hw *fh = (struct rte_flow_hw *)flow;
4321 : 0 : bool resizable = rte_flow_template_table_resizable(dev->data->port_id,
4322 : 0 : &fh->table->cfg.attr);
4323 : : int ret;
4324 : :
4325 : : if (mlx5_fp_debug_enabled()) {
4326 : : if (flow_hw_async_destroy_validate(dev, queue, fh, error))
4327 : : return -rte_errno;
4328 : : }
4329 [ # # ]: 0 : fh->operation_type = !resizable ?
4330 : : MLX5_FLOW_HW_FLOW_OP_TYPE_DESTROY :
4331 : : MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_DESTROY;
4332 : 0 : fh->user_data = user_data;
4333 : 0 : rule_attr.user_data = fh;
4334 : 0 : rule_attr.rule_idx = fh->rule_idx;
4335 : 0 : ret = mlx5dr_rule_destroy((struct mlx5dr_rule *)fh->rule, &rule_attr);
4336 [ # # ]: 0 : if (ret) {
4337 : 0 : return rte_flow_error_set(error, rte_errno,
4338 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4339 : : "fail to destroy rte flow");
4340 : : }
4341 : : flow_hw_q_inc_flow_ops(priv, queue);
4342 : 0 : return 0;
4343 : : }
4344 : :
4345 : : /**
4346 : : * Release the AGE and counter for given flow.
4347 : : *
4348 : : * @param[in] priv
4349 : : * Pointer to the port private data structure.
4350 : : * @param[in] queue
4351 : : * The queue to release the counter.
4352 : : * @param[in, out] flow
4353 : : * Pointer to the flow containing the counter.
4354 : : * @param[out] error
4355 : : * Pointer to error structure.
4356 : : */
4357 : : static void
4358 : 0 : flow_hw_age_count_release(struct mlx5_priv *priv, uint32_t queue,
4359 : : struct rte_flow_hw *flow,
4360 : : struct rte_flow_error *error)
4361 : : {
4362 : 0 : struct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(priv->dev_data->port_id, flow);
4363 : : uint32_t *cnt_queue;
4364 : 0 : uint32_t age_idx = aux->orig.age_idx;
4365 : :
4366 : : MLX5_ASSERT(flow->flags & MLX5_FLOW_HW_FLOW_FLAG_CNT_ID);
4367 [ # # # # ]: 0 : if (mlx5_hws_cnt_is_shared(priv->hws_cpool, flow->cnt_id)) {
4368 [ # # # # ]: 0 : if ((flow->flags & MLX5_FLOW_HW_FLOW_FLAG_AGE_IDX) &&
4369 : : !mlx5_hws_age_is_indirect(age_idx)) {
4370 : : /* Remove this AGE parameter from indirect counter. */
4371 : : mlx5_hws_cnt_age_set(priv->hws_cpool, flow->cnt_id, 0);
4372 : : /* Release the AGE parameter. */
4373 : 0 : mlx5_hws_age_action_destroy(priv, age_idx, error);
4374 : : }
4375 : 0 : return;
4376 : : }
4377 : : cnt_queue = mlx5_hws_cnt_get_queue(priv, &queue);
4378 : : /* Put the counter first to reduce the race risk in BG thread. */
4379 [ # # ]: 0 : mlx5_hws_cnt_pool_put(priv->hws_cpool, cnt_queue, &flow->cnt_id);
4380 [ # # ]: 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_AGE_IDX) {
4381 [ # # ]: 0 : if (mlx5_hws_age_is_indirect(age_idx)) {
4382 : 0 : uint32_t idx = age_idx & MLX5_HWS_AGE_IDX_MASK;
4383 : :
4384 : : mlx5_hws_age_nb_cnt_decrease(priv, idx);
4385 : : } else {
4386 : : /* Release the AGE parameter. */
4387 : 0 : mlx5_hws_age_action_destroy(priv, age_idx, error);
4388 : : }
4389 : : }
4390 : : }
4391 : :
4392 : : static __rte_always_inline void
4393 : : flow_hw_pull_legacy_indirect_comp(struct rte_eth_dev *dev, struct mlx5_hw_q_job *job,
4394 : : uint32_t queue)
4395 : : {
4396 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4397 : : struct mlx5_aso_ct_action *aso_ct;
4398 : : struct mlx5_aso_mtr *aso_mtr;
4399 : : uint32_t type, idx;
4400 : :
4401 [ # # ]: 0 : if (MLX5_INDIRECT_ACTION_TYPE_GET(job->action) ==
4402 : : MLX5_INDIRECT_ACTION_TYPE_QUOTA) {
4403 : 0 : mlx5_quota_async_completion(dev, queue, job);
4404 [ # # ]: 0 : } else if (job->type == MLX5_HW_Q_JOB_TYPE_DESTROY) {
4405 : : type = MLX5_INDIRECT_ACTION_TYPE_GET(job->action);
4406 [ # # ]: 0 : if (type == MLX5_INDIRECT_ACTION_TYPE_METER_MARK) {
4407 : 0 : idx = MLX5_INDIRECT_ACTION_IDX_GET(job->action);
4408 : 0 : mlx5_ipool_free(priv->hws_mpool->idx_pool, idx);
4409 : : }
4410 [ # # ]: 0 : } else if (job->type == MLX5_HW_Q_JOB_TYPE_CREATE) {
4411 : : type = MLX5_INDIRECT_ACTION_TYPE_GET(job->action);
4412 [ # # ]: 0 : if (type == MLX5_INDIRECT_ACTION_TYPE_METER_MARK) {
4413 : 0 : idx = MLX5_INDIRECT_ACTION_IDX_GET(job->action);
4414 : 0 : aso_mtr = mlx5_ipool_get(priv->hws_mpool->idx_pool, idx);
4415 : 0 : aso_mtr->state = ASO_METER_READY;
4416 [ # # ]: 0 : } else if (type == MLX5_INDIRECT_ACTION_TYPE_CT) {
4417 : 0 : idx = MLX5_INDIRECT_ACTION_IDX_GET(job->action);
4418 : 0 : aso_ct = mlx5_ipool_get(priv->hws_ctpool->cts, idx);
4419 : 0 : aso_ct->state = ASO_CONNTRACK_READY;
4420 : : }
4421 [ # # ]: 0 : } else if (job->type == MLX5_HW_Q_JOB_TYPE_QUERY) {
4422 : : type = MLX5_INDIRECT_ACTION_TYPE_GET(job->action);
4423 [ # # ]: 0 : if (type == MLX5_INDIRECT_ACTION_TYPE_CT) {
4424 : 0 : idx = MLX5_INDIRECT_ACTION_IDX_GET(job->action);
4425 : 0 : aso_ct = mlx5_ipool_get(priv->hws_ctpool->cts, idx);
4426 : 0 : mlx5_aso_ct_obj_analyze(job->query.user,
4427 : 0 : job->query.hw);
4428 : 0 : aso_ct->state = ASO_CONNTRACK_READY;
4429 : : }
4430 : : }
4431 : : }
4432 : :
4433 : : static __rte_always_inline int
4434 : : mlx5_hw_pull_flow_transfer_comp(struct rte_eth_dev *dev,
4435 : : uint32_t queue, struct rte_flow_op_result res[],
4436 : : uint16_t n_res)
4437 : : {
4438 : : uint32_t size, i;
4439 : 0 : struct rte_flow_hw *flow = NULL;
4440 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4441 : 0 : struct rte_ring *ring = priv->hw_q[queue].flow_transfer_completed;
4442 : :
4443 : 0 : size = RTE_MIN(rte_ring_count(ring), n_res);
4444 [ # # ]: 0 : for (i = 0; i < size; i++) {
4445 [ # # # # : 0 : res[i].status = RTE_FLOW_OP_SUCCESS;
# ]
4446 : : rte_ring_dequeue(ring, (void **)&flow);
4447 : 0 : res[i].user_data = flow->user_data;
4448 : : flow_hw_q_dec_flow_ops(priv, queue);
4449 : : }
4450 : 0 : return (int)size;
4451 : : }
4452 : :
4453 : : static inline int
4454 : 0 : __flow_hw_pull_indir_action_comp(struct rte_eth_dev *dev,
4455 : : uint32_t queue,
4456 : : struct rte_flow_op_result res[],
4457 : : uint16_t n_res)
4458 : :
4459 : : {
4460 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4461 : 0 : struct rte_ring *r = priv->hw_q[queue].indir_cq;
4462 : 0 : void *user_data = NULL;
4463 : : int ret_comp, i;
4464 : :
4465 : 0 : ret_comp = (int)rte_ring_count(r);
4466 : 0 : if (ret_comp > n_res)
4467 : : ret_comp = n_res;
4468 [ # # ]: 0 : for (i = 0; i < ret_comp; i++) {
4469 : : rte_ring_dequeue(r, &user_data);
4470 : 0 : res[i].user_data = user_data;
4471 : 0 : res[i].status = RTE_FLOW_OP_SUCCESS;
4472 : : }
4473 [ # # ]: 0 : if (!priv->shared_host) {
4474 [ # # # # ]: 0 : if (ret_comp < n_res && priv->hws_mpool)
4475 : 0 : ret_comp += mlx5_aso_pull_completion(&priv->hws_mpool->sq[queue],
4476 : 0 : &res[ret_comp], n_res - ret_comp);
4477 [ # # # # ]: 0 : if (ret_comp < n_res && priv->hws_ctpool)
4478 : 0 : ret_comp += mlx5_aso_pull_completion(&priv->ct_mng->aso_sqs[queue],
4479 : 0 : &res[ret_comp], n_res - ret_comp);
4480 : : }
4481 [ # # # # ]: 0 : if (ret_comp < n_res && priv->quota_ctx.sq)
4482 : 0 : ret_comp += mlx5_aso_pull_completion(&priv->quota_ctx.sq[queue],
4483 : 0 : &res[ret_comp],
4484 : 0 : n_res - ret_comp);
4485 [ # # ]: 0 : for (i = 0; i < ret_comp; i++) {
4486 : 0 : struct mlx5_hw_q_job *job = (struct mlx5_hw_q_job *)res[i].user_data;
4487 : :
4488 : : /* Restore user data. */
4489 : 0 : res[i].user_data = job->user_data;
4490 [ # # ]: 0 : if (job->indirect_type == MLX5_HW_INDIRECT_TYPE_LEGACY)
4491 : : flow_hw_pull_legacy_indirect_comp(dev, job, queue);
4492 : : /*
4493 : : * Current PMD supports 2 indirect action list types - MIRROR and REFORMAT.
4494 : : * These indirect list types do not post WQE to create action.
4495 : : * Future indirect list types that do post WQE will add
4496 : : * completion handlers here.
4497 : : */
4498 : : flow_hw_job_put(priv, job, queue);
4499 : : }
4500 : 0 : return ret_comp;
4501 : : }
4502 : :
4503 : : static __rte_always_inline void
4504 : : hw_cmpl_flow_update_or_destroy(struct rte_eth_dev *dev,
4505 : : struct rte_flow_hw *flow,
4506 : : uint32_t queue, struct rte_flow_error *error)
4507 : : {
4508 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4509 : 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
4510 : 0 : struct rte_flow_template_table *table = flow->table;
4511 : : /* Release the original resource index in case of update. */
4512 : 0 : uint32_t res_idx = flow->res_idx;
4513 : :
4514 [ # # ]: 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAGS_ALL) {
4515 : 0 : struct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
4516 : :
4517 [ # # # # : 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_FATE_JUMP)
# # ]
4518 : 0 : flow_hw_jump_release(dev, flow->jump);
4519 [ # # # # : 0 : else if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_FATE_HRXQ)
# # ]
4520 : 0 : mlx5_hrxq_obj_release(dev, flow->hrxq);
4521 [ # # # # : 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_CNT_ID)
# # ]
4522 : 0 : flow_hw_age_count_release(priv, queue, flow, error);
4523 [ # # # # : 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_MTR_ID)
# # ]
4524 : 0 : mlx5_ipool_free(pool->idx_pool, aux->orig.mtr_id);
4525 [ # # # # : 0 : if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_UPD_FLOW) {
# # ]
4526 [ # # # # : 0 : struct rte_flow_hw *upd_flow = &aux->upd_flow;
# # ]
4527 : :
4528 : : rte_memcpy(flow, upd_flow, offsetof(struct rte_flow_hw, rule));
4529 : 0 : aux->orig = aux->upd;
4530 : 0 : flow->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_CREATE;
4531 [ # # # # : 0 : if (!flow->nt_rule && table->resource)
# # # # #
# # # ]
4532 : 0 : mlx5_ipool_free(table->resource, res_idx);
4533 : : }
4534 : : }
4535 [ # # # # : 0 : if (flow->operation_type == MLX5_FLOW_HW_FLOW_OP_TYPE_DESTROY ||
# # ]
4536 : : flow->operation_type == MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_DESTROY) {
4537 [ # # # # : 0 : if (!flow->nt_rule) {
# # ]
4538 [ # # # # : 0 : if (table->resource)
# # ]
4539 : 0 : mlx5_ipool_free(table->resource, res_idx);
4540 : 0 : mlx5_ipool_free(table->flow, flow->idx);
4541 : : }
4542 : : }
4543 : : }
4544 : :
4545 : : static __rte_always_inline void
4546 : : hw_cmpl_resizable_tbl(struct rte_eth_dev *dev,
4547 : : struct rte_flow_hw *flow,
4548 : : uint32_t queue, enum rte_flow_op_status status,
4549 : : struct rte_flow_error *error)
4550 : : {
4551 : 0 : struct rte_flow_template_table *table = flow->table;
4552 : 0 : struct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(dev->data->port_id, flow);
4553 : 0 : uint32_t selector = aux->matcher_selector;
4554 : 0 : uint32_t other_selector = (selector + 1) & 1;
4555 : :
4556 : : MLX5_ASSERT(flow->flags & MLX5_FLOW_HW_FLOW_FLAG_MATCHER_SELECTOR);
4557 [ # # # # ]: 0 : switch (flow->operation_type) {
4558 : 0 : case MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_CREATE:
4559 : 0 : rte_atomic_fetch_add_explicit
4560 : : (&table->matcher_info[selector].refcnt, 1,
4561 : : rte_memory_order_relaxed);
4562 : 0 : break;
4563 : 0 : case MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_DESTROY:
4564 [ # # ]: 0 : rte_atomic_fetch_sub_explicit
4565 : : (&table->matcher_info[selector].refcnt, 1,
4566 : : rte_memory_order_relaxed);
4567 : : hw_cmpl_flow_update_or_destroy(dev, flow, queue, error);
4568 : : break;
4569 : 0 : case MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_MOVE:
4570 [ # # ]: 0 : if (status == RTE_FLOW_OP_SUCCESS) {
4571 : 0 : rte_atomic_fetch_sub_explicit
4572 : : (&table->matcher_info[selector].refcnt, 1,
4573 : : rte_memory_order_relaxed);
4574 : 0 : rte_atomic_fetch_add_explicit
4575 : : (&table->matcher_info[other_selector].refcnt, 1,
4576 : : rte_memory_order_relaxed);
4577 : 0 : aux->matcher_selector = other_selector;
4578 : : }
4579 : : break;
4580 : : default:
4581 : : break;
4582 : : }
4583 : : }
4584 : :
4585 : : /**
4586 : : * Pull the enqueued flows.
4587 : : *
4588 : : * For flows enqueued from creation/destruction, the status should be
4589 : : * checked from the dequeue result.
4590 : : *
4591 : : * @param[in] dev
4592 : : * Pointer to the rte_eth_dev structure.
4593 : : * @param[in] queue
4594 : : * The queue to pull the result.
4595 : : * @param[in/out] res
4596 : : * Array to save the results.
4597 : : * @param[in] n_res
4598 : : * Available result with the array.
4599 : : * @param[out] error
4600 : : * Pointer to error structure.
4601 : : *
4602 : : * @return
4603 : : * Result number on success, negative value otherwise and rte_errno is set.
4604 : : */
4605 : : static int
4606 : 0 : flow_hw_pull(struct rte_eth_dev *dev,
4607 : : uint32_t queue,
4608 : : struct rte_flow_op_result res[],
4609 : : uint16_t n_res,
4610 : : struct rte_flow_error *error)
4611 : : {
4612 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4613 : : int ret, i;
4614 : :
4615 : : /* 1. Pull the flow completion. */
4616 : 0 : ret = mlx5dr_send_queue_poll(priv->dr_ctx, queue, res, n_res);
4617 [ # # ]: 0 : if (ret < 0)
4618 : 0 : return rte_flow_error_set(error, rte_errno,
4619 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4620 : : "fail to query flow queue");
4621 [ # # ]: 0 : for (i = 0; i < ret; i++) {
4622 : 0 : struct rte_flow_hw *flow = res[i].user_data;
4623 : :
4624 : : /* Restore user data. */
4625 : 0 : res[i].user_data = flow->user_data;
4626 [ # # # ]: 0 : switch (flow->operation_type) {
4627 : : case MLX5_FLOW_HW_FLOW_OP_TYPE_DESTROY:
4628 : : case MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE:
4629 : : hw_cmpl_flow_update_or_destroy(dev, flow, queue, error);
4630 : : break;
4631 : 0 : case MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_CREATE:
4632 : : case MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_DESTROY:
4633 : : case MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_MOVE:
4634 : 0 : hw_cmpl_resizable_tbl(dev, flow, queue, res[i].status, error);
4635 : : break;
4636 : : default:
4637 : : break;
4638 : : }
4639 : : flow_hw_q_dec_flow_ops(priv, queue);
4640 : : }
4641 : : /* 2. Pull indirect action comp. */
4642 [ # # ]: 0 : if (ret < n_res)
4643 : 0 : ret += __flow_hw_pull_indir_action_comp(dev, queue, &res[ret],
4644 : 0 : n_res - ret);
4645 [ # # ]: 0 : if (ret < n_res)
4646 : 0 : ret += mlx5_hw_pull_flow_transfer_comp(dev, queue, &res[ret],
4647 : 0 : n_res - ret);
4648 : :
4649 : : return ret;
4650 : : }
4651 : :
4652 : : static uint32_t
4653 : 0 : mlx5_hw_push_queue(struct rte_ring *pending_q, struct rte_ring *cmpl_q)
4654 : : {
4655 : 0 : void *job = NULL;
4656 : : uint32_t i, size = rte_ring_count(pending_q);
4657 : :
4658 [ # # ]: 0 : for (i = 0; i < size; i++) {
4659 : : rte_ring_dequeue(pending_q, &job);
4660 [ # # # # : 0 : rte_ring_enqueue(cmpl_q, job);
# ]
4661 : : }
4662 : 0 : return size;
4663 : : }
4664 : :
4665 : : static inline uint32_t
4666 : 0 : __flow_hw_push_action(struct rte_eth_dev *dev,
4667 : : uint32_t queue)
4668 : : {
4669 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4670 : 0 : struct mlx5_hw_q *hw_q = &priv->hw_q[queue];
4671 : :
4672 : 0 : mlx5_hw_push_queue(hw_q->indir_iq, hw_q->indir_cq);
4673 : 0 : mlx5_hw_push_queue(hw_q->flow_transfer_pending,
4674 : : hw_q->flow_transfer_completed);
4675 [ # # ]: 0 : if (!priv->shared_host) {
4676 [ # # ]: 0 : if (priv->hws_ctpool)
4677 : 0 : mlx5_aso_push_wqe(priv->sh,
4678 : 0 : &priv->ct_mng->aso_sqs[queue]);
4679 [ # # ]: 0 : if (priv->hws_mpool)
4680 : 0 : mlx5_aso_push_wqe(priv->sh,
4681 : 0 : &priv->hws_mpool->sq[queue]);
4682 : : }
4683 : 0 : return flow_hw_q_pending(priv, queue);
4684 : : }
4685 : :
4686 : : static int
4687 : 0 : __flow_hw_push(struct rte_eth_dev *dev,
4688 : : uint32_t queue,
4689 : : struct rte_flow_error *error)
4690 : : {
4691 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4692 : : int ret, num;
4693 : :
4694 : 0 : num = __flow_hw_push_action(dev, queue);
4695 : 0 : ret = mlx5dr_send_queue_action(priv->dr_ctx, queue,
4696 : : MLX5DR_SEND_QUEUE_ACTION_DRAIN_ASYNC);
4697 [ # # ]: 0 : if (ret) {
4698 : 0 : rte_flow_error_set(error, rte_errno,
4699 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4700 : : "fail to push flows");
4701 : 0 : return ret;
4702 : : }
4703 : : return num;
4704 : : }
4705 : :
4706 : : /**
4707 : : * Push the enqueued flows to HW.
4708 : : *
4709 : : * Force apply all the enqueued flows to the HW.
4710 : : *
4711 : : * @param[in] dev
4712 : : * Pointer to the rte_eth_dev structure.
4713 : : * @param[in] queue
4714 : : * The queue to push the flow.
4715 : : * @param[out] error
4716 : : * Pointer to error structure.
4717 : : *
4718 : : * @return
4719 : : * 0 on success, negative value otherwise and rte_errno is set.
4720 : : */
4721 : : static int
4722 : 0 : flow_hw_push(struct rte_eth_dev *dev,
4723 : : uint32_t queue, struct rte_flow_error *error)
4724 : : {
4725 : 0 : int ret = __flow_hw_push(dev, queue, error);
4726 : :
4727 : 0 : return ret >= 0 ? 0 : ret;
4728 : : }
4729 : :
4730 : : /**
4731 : : * Drain the enqueued flows' completion.
4732 : : *
4733 : : * @param[in] dev
4734 : : * Pointer to the rte_eth_dev structure.
4735 : : * @param[in] queue
4736 : : * The queue to pull the flow.
4737 : : * @param[out] error
4738 : : * Pointer to error structure.
4739 : : *
4740 : : * @return
4741 : : * 0 on success, negative value otherwise and rte_errno is set.
4742 : : */
4743 : : static int
4744 : 0 : __flow_hw_pull_comp(struct rte_eth_dev *dev,
4745 : : uint32_t queue, struct rte_flow_error *error)
4746 : : {
4747 : : struct rte_flow_op_result comp[BURST_THR];
4748 : : int ret, i, empty_loop = 0;
4749 : : uint32_t pending_rules;
4750 : :
4751 : 0 : ret = __flow_hw_push(dev, queue, error);
4752 [ # # ]: 0 : if (ret < 0)
4753 : : return ret;
4754 : 0 : pending_rules = ret;
4755 [ # # ]: 0 : while (pending_rules) {
4756 : 0 : ret = flow_hw_pull(dev, queue, comp, BURST_THR, error);
4757 [ # # ]: 0 : if (ret < 0)
4758 : : return -1;
4759 [ # # ]: 0 : if (!ret) {
4760 : 0 : rte_delay_us_sleep(MLX5_ASO_WQE_CQE_RESPONSE_DELAY);
4761 [ # # ]: 0 : if (++empty_loop > 5) {
4762 : 0 : DRV_LOG(WARNING, "No available dequeue %u, quit.", pending_rules);
4763 : 0 : break;
4764 : : }
4765 : 0 : continue;
4766 : : }
4767 [ # # ]: 0 : for (i = 0; i < ret; i++) {
4768 [ # # ]: 0 : if (comp[i].status == RTE_FLOW_OP_ERROR)
4769 : 0 : DRV_LOG(WARNING, "Flow flush get error CQE.");
4770 : : }
4771 : : /*
4772 : : * Indirect **SYNC** METER_MARK and CT actions do not
4773 : : * remove completion after WQE post.
4774 : : * That implementation avoids HW timeout.
4775 : : * The completion is removed before the following WQE post.
4776 : : * However, HWS queue updates do not reflect that behaviour.
4777 : : * Therefore, during port destruction sync queue may have
4778 : : * pending completions.
4779 : : */
4780 : 0 : pending_rules -= RTE_MIN(pending_rules, (uint32_t)ret);
4781 : : empty_loop = 0;
4782 : : }
4783 : : return 0;
4784 : : }
4785 : :
4786 : : /**
4787 : : * Flush created flows.
4788 : : *
4789 : : * @param[in] dev
4790 : : * Pointer to the rte_eth_dev structure.
4791 : : * @param[out] error
4792 : : * Pointer to error structure.
4793 : : *
4794 : : * @return
4795 : : * 0 on success, negative value otherwise and rte_errno is set.
4796 : : */
4797 : : int
4798 : 0 : flow_hw_q_flow_flush(struct rte_eth_dev *dev,
4799 : : struct rte_flow_error *error)
4800 : : {
4801 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
4802 : 0 : struct mlx5_hw_q *hw_q = &priv->hw_q[MLX5_DEFAULT_FLUSH_QUEUE];
4803 : : struct rte_flow_template_table *tbl;
4804 : : struct rte_flow_hw *flow;
4805 : 0 : struct rte_flow_op_attr attr = {
4806 : : .postpone = 0,
4807 : : };
4808 : : uint32_t pending_rules = 0;
4809 : : uint32_t queue;
4810 : : uint32_t fidx;
4811 : :
4812 : : /*
4813 : : * Ensure to push and dequeue all the enqueued flow
4814 : : * creation/destruction jobs in case user forgot to
4815 : : * dequeue. Or the enqueued created flows will be
4816 : : * leaked. The forgotten dequeues would also cause
4817 : : * flow flush get extra CQEs as expected and pending_rules
4818 : : * be minus value.
4819 : : */
4820 [ # # ]: 0 : for (queue = 0; queue < priv->nb_queue; queue++) {
4821 [ # # ]: 0 : if (__flow_hw_pull_comp(dev, queue, error))
4822 : : return -1;
4823 : : }
4824 : : /* Flush flow per-table from MLX5_DEFAULT_FLUSH_QUEUE. */
4825 [ # # ]: 0 : LIST_FOREACH(tbl, &priv->flow_hw_tbl, next) {
4826 [ # # ]: 0 : if (!tbl->cfg.external)
4827 : 0 : continue;
4828 [ # # ]: 0 : MLX5_IPOOL_FOREACH(tbl->flow, fidx, flow) {
4829 [ # # ]: 0 : if (flow_hw_async_flow_destroy(dev,
4830 : : MLX5_DEFAULT_FLUSH_QUEUE,
4831 : : &attr,
4832 : : (struct rte_flow *)flow,
4833 : : NULL,
4834 : : error))
4835 : : return -1;
4836 : 0 : pending_rules++;
4837 : : /* Drain completion with queue size. */
4838 [ # # ]: 0 : if (pending_rules >= hw_q->size) {
4839 [ # # ]: 0 : if (__flow_hw_pull_comp(dev,
4840 : : MLX5_DEFAULT_FLUSH_QUEUE,
4841 : : error))
4842 : : return -1;
4843 : : pending_rules = 0;
4844 : : }
4845 : : }
4846 : : }
4847 : : /* Drain left completion. */
4848 [ # # # # ]: 0 : if (pending_rules &&
4849 : 0 : __flow_hw_pull_comp(dev, MLX5_DEFAULT_FLUSH_QUEUE, error))
4850 : 0 : return -1;
4851 : : return 0;
4852 : : }
4853 : :
4854 : : static int
4855 : 0 : mlx5_tbl_multi_pattern_process(struct rte_eth_dev *dev,
4856 : : struct rte_flow_template_table *tbl,
4857 : : struct mlx5_multi_pattern_segment *segment,
4858 : : uint32_t bulk_size,
4859 : : struct rte_flow_error *error)
4860 : : {
4861 : : int ret = 0;
4862 : : uint32_t i;
4863 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
4864 : : struct mlx5_tbl_multi_pattern_ctx *mpctx = &tbl->mpctx;
4865 : : const struct rte_flow_template_table_attr *table_attr = &tbl->cfg.attr;
4866 : : const struct rte_flow_attr *attr = &table_attr->flow_attr;
4867 : : enum mlx5dr_table_type type = get_mlx5dr_table_type(attr);
4868 : 0 : uint32_t flags = mlx5_hw_act_flag[!!attr->group][type];
4869 : : struct mlx5dr_action *dr_action = NULL;
4870 : :
4871 [ # # ]: 0 : for (i = 0; i < MLX5_MULTIPATTERN_ENCAP_NUM; i++) {
4872 [ # # ]: 0 : typeof(mpctx->reformat[0]) *reformat = mpctx->reformat + i;
4873 : : enum mlx5dr_action_type reformat_type =
4874 : : mlx5_multi_pattern_reformat_index_to_type(i);
4875 : :
4876 [ # # ]: 0 : if (!reformat->elements_num)
4877 : 0 : continue;
4878 : : dr_action = reformat_type == MLX5DR_ACTION_TYP_INSERT_HEADER ?
4879 : : mlx5dr_action_create_insert_header
4880 : : (priv->dr_ctx, reformat->elements_num,
4881 : : reformat->insert_hdr, bulk_size, flags) :
4882 : 0 : mlx5dr_action_create_reformat
4883 : : (priv->dr_ctx, reformat_type, reformat->elements_num,
4884 : 0 : reformat->reformat_hdr, bulk_size, flags);
4885 [ # # ]: 0 : if (!dr_action) {
4886 : 0 : ret = rte_flow_error_set(error, rte_errno,
4887 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4888 : : NULL,
4889 : : "failed to create multi-pattern encap action");
4890 : 0 : goto error;
4891 : : }
4892 : 0 : segment->reformat_action[i] = dr_action;
4893 : : }
4894 [ # # ]: 0 : if (mpctx->mh.elements_num) {
4895 : : typeof(mpctx->mh) *mh = &mpctx->mh;
4896 : 0 : dr_action = mlx5dr_action_create_modify_header
4897 : 0 : (priv->dr_ctx, mpctx->mh.elements_num, mh->pattern,
4898 : : bulk_size, flags);
4899 [ # # ]: 0 : if (!dr_action) {
4900 : 0 : ret = rte_flow_error_set(error, rte_errno,
4901 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4902 : : NULL, "failed to create multi-pattern header modify action");
4903 : 0 : goto error;
4904 : : }
4905 : 0 : segment->mhdr_action = dr_action;
4906 : : }
4907 [ # # ]: 0 : if (dr_action) {
4908 : 0 : segment->capacity = RTE_BIT32(bulk_size);
4909 [ # # ]: 0 : if (segment != &mpctx->segments[MLX5_MAX_TABLE_RESIZE_NUM - 1])
4910 : 0 : segment[1].head_index = segment->head_index + segment->capacity;
4911 : : }
4912 : : return 0;
4913 : 0 : error:
4914 : 0 : mlx5_destroy_multi_pattern_segment(segment);
4915 : 0 : return ret;
4916 : : }
4917 : :
4918 : : static int
4919 : 0 : mlx5_hw_build_template_table(struct rte_eth_dev *dev,
4920 : : uint8_t nb_action_templates,
4921 : : struct rte_flow_actions_template *action_templates[],
4922 : : struct mlx5dr_action_template *at[],
4923 : : struct rte_flow_template_table *tbl,
4924 : : struct rte_flow_error *error)
4925 : : {
4926 : : int ret;
4927 : : uint8_t i;
4928 : :
4929 [ # # ]: 0 : for (i = 0; i < nb_action_templates; i++) {
4930 : 0 : uint32_t refcnt = rte_atomic_fetch_add_explicit(&action_templates[i]->refcnt, 1,
4931 : : rte_memory_order_relaxed) + 1;
4932 : :
4933 [ # # ]: 0 : if (refcnt <= 1) {
4934 : 0 : rte_flow_error_set(error, EINVAL,
4935 : : RTE_FLOW_ERROR_TYPE_ACTION,
4936 : : &action_templates[i], "invalid AT refcount");
4937 : 0 : goto at_error;
4938 : : }
4939 : 0 : at[i] = action_templates[i]->tmpl;
4940 : 0 : tbl->ats[i].action_template = action_templates[i];
4941 : 0 : LIST_INIT(&tbl->ats[i].acts.act_list);
4942 : : /* do NOT translate table action if `dev` was not started */
4943 [ # # ]: 0 : if (!dev->data->dev_started)
4944 : 0 : continue;
4945 : 0 : ret = flow_hw_translate_actions_template(dev, &tbl->cfg,
4946 : : &tbl->ats[i].acts,
4947 : : action_templates[i],
4948 : : &tbl->mpctx, error);
4949 [ # # ]: 0 : if (ret) {
4950 : 0 : i++;
4951 : 0 : goto at_error;
4952 : : }
4953 : 0 : flow_hw_populate_rule_acts_caches(dev, tbl, i);
4954 : : }
4955 [ # # ]: 0 : tbl->nb_action_templates = nb_action_templates;
4956 [ # # ]: 0 : if (mlx5_is_multi_pattern_active(&tbl->mpctx)) {
4957 [ # # ]: 0 : ret = mlx5_tbl_multi_pattern_process(dev, tbl,
4958 : : &tbl->mpctx.segments[0],
4959 : : rte_log2_u32(tbl->cfg.attr.nb_flows),
4960 : : error);
4961 [ # # ]: 0 : if (ret)
4962 : 0 : goto at_error;
4963 : : }
4964 : : return 0;
4965 : :
4966 : : at_error:
4967 [ # # ]: 0 : while (i--) {
4968 : 0 : __flow_hw_action_template_destroy(dev, &tbl->ats[i].acts);
4969 : 0 : rte_atomic_fetch_sub_explicit(&action_templates[i]->refcnt,
4970 : : 1, rte_memory_order_relaxed);
4971 : : }
4972 : 0 : return rte_errno;
4973 : : }
4974 : :
4975 : : static bool
4976 : : flow_hw_validate_template_domain(const struct rte_flow_attr *table_attr,
4977 : : uint32_t ingress, uint32_t egress, uint32_t transfer)
4978 : : {
4979 : 0 : if (table_attr->ingress)
4980 : : return ingress != 0;
4981 [ # # # # ]: 0 : else if (table_attr->egress)
4982 : : return egress != 0;
4983 : : else
4984 : 0 : return transfer;
4985 : : }
4986 : :
4987 : : static bool
4988 : : flow_hw_validate_table_domain(const struct rte_flow_attr *table_attr)
4989 : : {
4990 : 0 : return table_attr->ingress + table_attr->egress + table_attr->transfer
4991 : : == 1;
4992 : : }
4993 : :
4994 : : /**
4995 : : * Create flow table.
4996 : : *
4997 : : * The input item and action templates will be binded to the table.
4998 : : * Flow memory will also be allocated. Matcher will be created based
4999 : : * on the item template. Action will be translated to the dedicated
5000 : : * DR action if possible.
5001 : : *
5002 : : * @param[in] dev
5003 : : * Pointer to the rte_eth_dev structure.
5004 : : * @param[in] table_cfg
5005 : : * Pointer to the table configuration.
5006 : : * @param[in] item_templates
5007 : : * Item template array to be binded to the table.
5008 : : * @param[in] nb_item_templates
5009 : : * Number of item template.
5010 : : * @param[in] action_templates
5011 : : * Action template array to be binded to the table.
5012 : : * @param[in] nb_action_templates
5013 : : * Number of action template.
5014 : : * @param[out] error
5015 : : * Pointer to error structure.
5016 : : *
5017 : : * @return
5018 : : * Table on success, NULL otherwise and rte_errno is set.
5019 : : */
5020 : : static struct rte_flow_template_table *
5021 : 0 : flow_hw_table_create(struct rte_eth_dev *dev,
5022 : : const struct mlx5_flow_template_table_cfg *table_cfg,
5023 : : struct rte_flow_pattern_template *item_templates[],
5024 : : uint8_t nb_item_templates,
5025 : : struct rte_flow_actions_template *action_templates[],
5026 : : uint8_t nb_action_templates,
5027 : : struct rte_flow_error *error)
5028 : : {
5029 : 0 : struct rte_flow_error sub_error = {
5030 : : .type = RTE_FLOW_ERROR_TYPE_NONE,
5031 : : .cause = NULL,
5032 : : .message = NULL,
5033 : : };
5034 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
5035 : 0 : struct mlx5dr_matcher_attr matcher_attr = {0};
5036 : 0 : struct mlx5dr_action_jump_to_matcher_attr jump_attr = {
5037 : : .type = MLX5DR_ACTION_JUMP_TO_MATCHER_BY_INDEX,
5038 : : .matcher = NULL,
5039 : : };
5040 : : struct rte_flow_template_table *tbl = NULL;
5041 : : struct mlx5_flow_group *grp;
5042 : : struct mlx5dr_match_template *mt[MLX5_HW_TBL_MAX_ITEM_TEMPLATE];
5043 : : struct mlx5dr_action_template *at[MLX5_HW_TBL_MAX_ACTION_TEMPLATE];
5044 : 0 : const struct rte_flow_template_table_attr *attr = &table_cfg->attr;
5045 : 0 : struct rte_flow_attr flow_attr = attr->flow_attr;
5046 : 0 : struct mlx5_flow_cb_ctx ctx = {
5047 : : .dev = dev,
5048 : : .error = &sub_error,
5049 : : .data = &flow_attr,
5050 : : };
5051 : 0 : struct mlx5_indexed_pool_config cfg = {
5052 : : .trunk_size = 1 << 12,
5053 : : .per_core_cache = 1 << 13,
5054 : : .need_lock = 1,
5055 : 0 : .release_mem_en = !!priv->sh->config.reclaim_mode,
5056 : : .malloc = mlx5_malloc,
5057 : : .free = mlx5_free,
5058 : : .type = "mlx5_hw_table_flow",
5059 : : };
5060 : : struct mlx5_list_entry *ge;
5061 : : uint32_t i = 0, max_tpl = MLX5_HW_TBL_MAX_ITEM_TEMPLATE;
5062 [ # # ]: 0 : uint32_t nb_flows = rte_align32pow2(attr->nb_flows);
5063 : 0 : bool port_started = !!dev->data->dev_started;
5064 : : bool rpool_needed;
5065 : : size_t tbl_mem_size;
5066 : : int err;
5067 : :
5068 [ # # ]: 0 : if (!flow_hw_validate_table_domain(&attr->flow_attr)) {
5069 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ATTR,
5070 : : NULL, "invalid table domain attributes");
5071 : 0 : return NULL;
5072 : : }
5073 [ # # ]: 0 : for (i = 0; i < nb_item_templates; i++) {
5074 : : const struct rte_flow_pattern_template_attr *pt_attr =
5075 : 0 : &item_templates[i]->attr;
5076 : : bool match = flow_hw_validate_template_domain(&attr->flow_attr,
5077 : 0 : pt_attr->ingress,
5078 : 0 : pt_attr->egress,
5079 [ # # ]: 0 : pt_attr->transfer);
5080 [ # # ]: 0 : if (!match) {
5081 : 0 : rte_flow_error_set(error, EINVAL,
5082 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5083 : : NULL, "pattern template domain does not match table");
5084 : 0 : return NULL;
5085 : : }
5086 : : }
5087 [ # # ]: 0 : for (i = 0; i < nb_action_templates; i++) {
5088 : 0 : const struct rte_flow_actions_template *at = action_templates[i];
5089 : : bool match = flow_hw_validate_template_domain(&attr->flow_attr,
5090 : 0 : at->attr.ingress,
5091 : 0 : at->attr.egress,
5092 [ # # ]: 0 : at->attr.transfer);
5093 [ # # ]: 0 : if (!match) {
5094 : 0 : rte_flow_error_set(error, EINVAL,
5095 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5096 : : NULL, "action template domain does not match table");
5097 : 0 : return NULL;
5098 : : }
5099 : : }
5100 : : /* HWS layer accepts only 1 item template with root table. */
5101 [ # # ]: 0 : if (!attr->flow_attr.group)
5102 : : max_tpl = 1;
5103 : 0 : cfg.max_idx = nb_flows;
5104 [ # # ]: 0 : cfg.size = !rte_flow_template_table_resizable(dev->data->port_id, attr) ?
5105 : : mlx5_flow_hw_entry_size() :
5106 : : mlx5_flow_hw_auxed_entry_size();
5107 : : /* For table has very limited flows, disable cache. */
5108 [ # # ]: 0 : if (nb_flows < cfg.trunk_size) {
5109 : 0 : cfg.per_core_cache = 0;
5110 : 0 : cfg.trunk_size = nb_flows;
5111 [ # # ]: 0 : } else if (nb_flows <= MLX5_HW_IPOOL_SIZE_THRESHOLD) {
5112 : 0 : cfg.per_core_cache = MLX5_HW_IPOOL_CACHE_MIN;
5113 : : }
5114 : : /* Check if we requires too many templates. */
5115 [ # # # # ]: 0 : if (nb_item_templates > max_tpl ||
5116 : : nb_action_templates > MLX5_HW_TBL_MAX_ACTION_TEMPLATE) {
5117 : 0 : rte_errno = EINVAL;
5118 : 0 : goto error;
5119 : : }
5120 : : /*
5121 : : * Amount of memory required for rte_flow_template_table struct:
5122 : : * - Size of the struct itself.
5123 : : * - VLA of DR rule action containers at the end =
5124 : : * number of actions templates * number of queues * size of DR rule actions container.
5125 : : */
5126 : : tbl_mem_size = sizeof(*tbl);
5127 : 0 : tbl_mem_size += nb_action_templates * priv->nb_queue * sizeof(tbl->rule_acts[0]);
5128 : : /* Allocate the table memory. */
5129 : 0 : tbl = mlx5_malloc(MLX5_MEM_ZERO, tbl_mem_size, RTE_CACHE_LINE_SIZE, rte_socket_id());
5130 [ # # ]: 0 : if (!tbl)
5131 : 0 : goto error;
5132 : 0 : tbl->cfg = *table_cfg;
5133 : : /* Allocate flow indexed pool. */
5134 : 0 : tbl->flow = mlx5_ipool_create(&cfg);
5135 [ # # ]: 0 : if (!tbl->flow)
5136 : 0 : goto error;
5137 : : /* Allocate table of auxiliary flow rule structs. */
5138 : 0 : tbl->flow_aux = mlx5_malloc(MLX5_MEM_ZERO, sizeof(struct rte_flow_hw_aux) * nb_flows,
5139 : 0 : RTE_CACHE_LINE_SIZE, rte_dev_numa_node(dev->device));
5140 [ # # ]: 0 : if (!tbl->flow_aux)
5141 : 0 : goto error;
5142 : : /* Register the flow group. */
5143 : 0 : ge = mlx5_hlist_register(priv->sh->groups, attr->flow_attr.group, &ctx);
5144 [ # # ]: 0 : if (!ge)
5145 : 0 : goto error;
5146 : : grp = container_of(ge, struct mlx5_flow_group, entry);
5147 : 0 : tbl->grp = grp;
5148 : : /* Prepare matcher information. */
5149 : 0 : matcher_attr.resizable = !!rte_flow_template_table_resizable
5150 : 0 : (dev->data->port_id, &table_cfg->attr);
5151 : 0 : matcher_attr.optimize_flow_src = MLX5DR_MATCHER_FLOW_SRC_ANY;
5152 : 0 : matcher_attr.priority = attr->flow_attr.priority;
5153 : 0 : matcher_attr.optimize_using_rule_idx = true;
5154 : 0 : matcher_attr.mode = MLX5DR_MATCHER_RESOURCE_MODE_RULE;
5155 [ # # ]: 0 : matcher_attr.insert_mode = flow_hw_matcher_insert_mode_get(attr->insertion_type);
5156 [ # # ]: 0 : if (matcher_attr.insert_mode == MLX5DR_MATCHER_INSERT_BY_INDEX) {
5157 [ # # ]: 0 : if (attr->insertion_type == RTE_FLOW_TABLE_INSERTION_TYPE_INDEX_WITH_PATTERN) {
5158 : 0 : matcher_attr.isolated = true;
5159 : 0 : matcher_attr.match_mode = MLX5DR_MATCHER_MATCH_MODE_DEFAULT;
5160 : : } else {
5161 : 0 : matcher_attr.isolated = false;
5162 : 0 : matcher_attr.match_mode = MLX5DR_MATCHER_MATCH_MODE_ALWAYS_HIT;
5163 : : }
5164 : : }
5165 [ # # ]: 0 : if (attr->hash_func == RTE_FLOW_TABLE_HASH_FUNC_CRC16) {
5166 : 0 : DRV_LOG(ERR, "16-bit checksum hash type is not supported");
5167 : 0 : rte_errno = ENOTSUP;
5168 : 0 : goto it_error;
5169 : : }
5170 [ # # ]: 0 : matcher_attr.distribute_mode = flow_hw_matcher_distribute_mode_get(attr->hash_func);
5171 : 0 : matcher_attr.rule.num_log = rte_log2_u32(nb_flows);
5172 : : /* Parse hints information. */
5173 [ # # ]: 0 : if (attr->specialize) {
5174 : : uint32_t val = RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_WIRE_ORIG |
5175 : : RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_VPORT_ORIG;
5176 : :
5177 [ # # ]: 0 : if ((attr->specialize & val) == val) {
5178 : 0 : DRV_LOG(ERR, "Invalid hint value %x",
5179 : : attr->specialize);
5180 : 0 : rte_errno = EINVAL;
5181 : 0 : goto it_error;
5182 : : }
5183 [ # # ]: 0 : if (attr->specialize &
5184 : : RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_WIRE_ORIG)
5185 : 0 : matcher_attr.optimize_flow_src =
5186 : : MLX5DR_MATCHER_FLOW_SRC_WIRE;
5187 [ # # ]: 0 : else if (attr->specialize &
5188 : : RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_VPORT_ORIG)
5189 : 0 : matcher_attr.optimize_flow_src =
5190 : : MLX5DR_MATCHER_FLOW_SRC_VPORT;
5191 : : }
5192 : : /* Build the item template. */
5193 [ # # ]: 0 : for (i = 0; i < nb_item_templates; i++) {
5194 : : uint32_t ret;
5195 : :
5196 [ # # # # ]: 0 : if ((flow_attr.ingress && !item_templates[i]->attr.ingress) ||
5197 [ # # # # ]: 0 : (flow_attr.egress && !item_templates[i]->attr.egress) ||
5198 [ # # # # ]: 0 : (flow_attr.transfer && !item_templates[i]->attr.transfer)) {
5199 : 0 : DRV_LOG(ERR, "pattern template and template table attribute mismatch");
5200 : 0 : rte_errno = EINVAL;
5201 : 0 : goto it_error;
5202 : : }
5203 [ # # ]: 0 : if (item_templates[i]->item_flags & MLX5_FLOW_ITEM_COMPARE)
5204 : 0 : matcher_attr.mode = MLX5DR_MATCHER_RESOURCE_MODE_HTABLE;
5205 : 0 : ret = rte_atomic_fetch_add_explicit(&item_templates[i]->refcnt, 1,
5206 : : rte_memory_order_relaxed) + 1;
5207 [ # # ]: 0 : if (ret <= 1) {
5208 : 0 : rte_errno = EINVAL;
5209 : 0 : goto it_error;
5210 : : }
5211 : 0 : mt[i] = item_templates[i]->mt;
5212 : 0 : tbl->its[i] = item_templates[i];
5213 : : }
5214 : 0 : tbl->nb_item_templates = nb_item_templates;
5215 : : /* Build the action template. */
5216 : 0 : err = mlx5_hw_build_template_table(dev, nb_action_templates,
5217 : : action_templates, at, tbl, &sub_error);
5218 [ # # ]: 0 : if (err) {
5219 : : i = nb_item_templates;
5220 : 0 : goto it_error;
5221 : : }
5222 : 0 : tbl->matcher_info[0].matcher = mlx5dr_matcher_create
5223 : 0 : (tbl->grp->tbl, mt, nb_item_templates, at, nb_action_templates, &matcher_attr);
5224 [ # # ]: 0 : if (!tbl->matcher_info[0].matcher)
5225 : 0 : goto at_error;
5226 : 0 : tbl->matcher_attr = matcher_attr;
5227 [ # # ]: 0 : tbl->type = attr->flow_attr.transfer ? MLX5DR_TABLE_TYPE_FDB :
5228 : 0 : (attr->flow_attr.egress ? MLX5DR_TABLE_TYPE_NIC_TX :
5229 : : MLX5DR_TABLE_TYPE_NIC_RX);
5230 [ # # ]: 0 : if (matcher_attr.isolated) {
5231 : 0 : jump_attr.matcher = tbl->matcher_info[0].matcher;
5232 : 0 : tbl->matcher_info[0].jump = mlx5dr_action_create_jump_to_matcher(priv->dr_ctx,
5233 : 0 : &jump_attr, mlx5_hw_act_flag[!!attr->flow_attr.group][tbl->type]);
5234 [ # # ]: 0 : if (!tbl->matcher_info[0].jump)
5235 : 0 : goto jtm_error;
5236 : : }
5237 : : /*
5238 : : * Only the matcher supports update and needs more than 1 WQE, an additional
5239 : : * index is needed. Or else the flow index can be reused.
5240 : : */
5241 [ # # # # ]: 0 : rpool_needed = mlx5dr_matcher_is_updatable(tbl->matcher_info[0].matcher) &&
5242 : 0 : mlx5dr_matcher_is_dependent(tbl->matcher_info[0].matcher);
5243 [ # # ]: 0 : if (rpool_needed) {
5244 : : /* Allocate rule indexed pool. */
5245 : 0 : cfg.size = 0;
5246 : 0 : cfg.type = "mlx5_hw_table_rule";
5247 : 0 : cfg.max_idx += priv->hw_q[0].size;
5248 : 0 : tbl->resource = mlx5_ipool_create(&cfg);
5249 [ # # ]: 0 : if (!tbl->resource)
5250 : 0 : goto res_error;
5251 : : }
5252 [ # # ]: 0 : if (port_started)
5253 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->flow_hw_tbl, tbl, next);
5254 : : else
5255 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->flow_hw_tbl_ongo, tbl, next);
5256 : : rte_rwlock_init(&tbl->matcher_replace_rwlk);
5257 : 0 : return tbl;
5258 : : res_error:
5259 [ # # ]: 0 : if (tbl->matcher_info[0].jump)
5260 : 0 : mlx5dr_action_destroy(tbl->matcher_info[0].jump);
5261 : 0 : jtm_error:
5262 [ # # ]: 0 : if (tbl->matcher_info[0].matcher)
5263 : 0 : (void)mlx5dr_matcher_destroy(tbl->matcher_info[0].matcher);
5264 : 0 : at_error:
5265 [ # # ]: 0 : for (i = 0; i < nb_action_templates; i++) {
5266 : 0 : __flow_hw_action_template_destroy(dev, &tbl->ats[i].acts);
5267 : 0 : rte_atomic_fetch_sub_explicit(&action_templates[i]->refcnt,
5268 : : 1, rte_memory_order_relaxed);
5269 : : }
5270 : : i = nb_item_templates;
5271 : : it_error:
5272 [ # # ]: 0 : while (i--)
5273 : 0 : rte_atomic_fetch_sub_explicit(&item_templates[i]->refcnt,
5274 : : 1, rte_memory_order_relaxed);
5275 : 0 : error:
5276 : 0 : err = rte_errno;
5277 [ # # ]: 0 : if (tbl) {
5278 [ # # ]: 0 : if (tbl->grp)
5279 : 0 : mlx5_hlist_unregister(priv->sh->groups,
5280 : : &tbl->grp->entry);
5281 [ # # ]: 0 : if (tbl->flow_aux)
5282 : 0 : mlx5_free(tbl->flow_aux);
5283 [ # # ]: 0 : if (tbl->flow)
5284 : 0 : mlx5_ipool_destroy(tbl->flow);
5285 : 0 : mlx5_free(tbl);
5286 : : }
5287 [ # # ]: 0 : if (error != NULL) {
5288 [ # # ]: 0 : if (sub_error.type == RTE_FLOW_ERROR_TYPE_NONE)
5289 : 0 : rte_flow_error_set(error, err, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5290 : : "Failed to create template table");
5291 : : else
5292 : : rte_memcpy(error, &sub_error, sizeof(sub_error));
5293 : : }
5294 : : return NULL;
5295 : : }
5296 : :
5297 : : /**
5298 : : * Update flow template table.
5299 : : *
5300 : : * @param[in] dev
5301 : : * Pointer to the rte_eth_dev structure.
5302 : : * @param[out] error
5303 : : * Pointer to error structure.
5304 : : *
5305 : : * @return
5306 : : * 0 on success, negative value otherwise and rte_errno is set.
5307 : : */
5308 : : int
5309 : 0 : flow_hw_table_update(struct rte_eth_dev *dev,
5310 : : struct rte_flow_error *error)
5311 : : {
5312 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
5313 : : struct rte_flow_template_table *tbl;
5314 : :
5315 [ # # ]: 0 : while ((tbl = LIST_FIRST(&priv->flow_hw_tbl_ongo)) != NULL) {
5316 [ # # ]: 0 : if (flow_hw_translate_all_actions_templates(dev, tbl, error))
5317 : : return -1;
5318 [ # # ]: 0 : LIST_REMOVE(tbl, next);
5319 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->flow_hw_tbl, tbl, next);
5320 : : }
5321 : : return 0;
5322 : : }
5323 : :
5324 : : static inline int
5325 : 0 : __translate_group(struct rte_eth_dev *dev,
5326 : : const struct rte_flow_attr *flow_attr,
5327 : : bool external,
5328 : : uint32_t group,
5329 : : uint32_t *table_group,
5330 : : struct rte_flow_error *error)
5331 : : {
5332 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
5333 : 0 : struct mlx5_sh_config *config = &priv->sh->config;
5334 : :
5335 [ # # ]: 0 : if (config->dv_esw_en &&
5336 [ # # # # ]: 0 : priv->fdb_def_rule &&
5337 [ # # ]: 0 : external &&
5338 : : flow_attr->transfer) {
5339 [ # # ]: 0 : if (group > MLX5_HW_MAX_TRANSFER_GROUP)
5340 : 0 : return rte_flow_error_set(error, EINVAL,
5341 : : RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5342 : : NULL,
5343 : : "group index not supported");
5344 : 0 : *table_group = group + 1;
5345 [ # # ]: 0 : } else if (config->dv_esw_en &&
5346 [ # # # # : 0 : (config->repr_matching || config->dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS) &&
# # ]
5347 [ # # ]: 0 : external &&
5348 : : flow_attr->egress) {
5349 : : /*
5350 : : * On E-Switch setups, default egress flow rules are inserted to allow
5351 : : * representor matching and/or preserving metadata across steering domains.
5352 : : * These flow rules are inserted in group 0 and this group is reserved by PMD
5353 : : * for these purposes.
5354 : : *
5355 : : * As a result, if representor matching or extended metadata mode is enabled,
5356 : : * group provided by the user must be incremented to avoid inserting flow rules
5357 : : * in group 0.
5358 : : */
5359 [ # # ]: 0 : if (group > MLX5_HW_MAX_EGRESS_GROUP)
5360 : 0 : return rte_flow_error_set(error, EINVAL,
5361 : : RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5362 : : NULL,
5363 : : "group index not supported");
5364 : 0 : *table_group = group + 1;
5365 : : } else {
5366 : 0 : *table_group = group;
5367 : : }
5368 : : return 0;
5369 : : }
5370 : :
5371 : : /**
5372 : : * Translates group index specified by the user in @p attr to internal
5373 : : * group index.
5374 : : *
5375 : : * Translation is done by incrementing group index, so group n becomes n + 1.
5376 : : *
5377 : : * @param[in] dev
5378 : : * Pointer to Ethernet device.
5379 : : * @param[in] cfg
5380 : : * Pointer to the template table configuration.
5381 : : * @param[in] group
5382 : : * Currently used group index (table group or jump destination).
5383 : : * @param[out] table_group
5384 : : * Pointer to output group index.
5385 : : * @param[out] error
5386 : : * Pointer to error structure.
5387 : : *
5388 : : * @return
5389 : : * 0 on success. Otherwise, returns negative error code, rte_errno is set
5390 : : * and error structure is filled.
5391 : : */
5392 : : static int
5393 : : flow_hw_translate_group(struct rte_eth_dev *dev,
5394 : : const struct mlx5_flow_template_table_cfg *cfg,
5395 : : uint32_t group,
5396 : : uint32_t *table_group,
5397 : : struct rte_flow_error *error)
5398 : : {
5399 : 0 : const struct rte_flow_attr *flow_attr = &cfg->attr.flow_attr;
5400 : :
5401 : 0 : return __translate_group(dev, flow_attr, cfg->external, group, table_group, error);
5402 : : }
5403 : :
5404 : : /**
5405 : : * Create flow table.
5406 : : *
5407 : : * This function is a wrapper over @ref flow_hw_table_create(), which translates parameters
5408 : : * provided by user to proper internal values.
5409 : : *
5410 : : * @param[in] dev
5411 : : * Pointer to Ethernet device.
5412 : : * @param[in] attr
5413 : : * Pointer to the table attributes.
5414 : : * @param[in] item_templates
5415 : : * Item template array to be binded to the table.
5416 : : * @param[in] nb_item_templates
5417 : : * Number of item templates.
5418 : : * @param[in] action_templates
5419 : : * Action template array to be binded to the table.
5420 : : * @param[in] nb_action_templates
5421 : : * Number of action templates.
5422 : : * @param[out] error
5423 : : * Pointer to error structure.
5424 : : *
5425 : : * @return
5426 : : * Table on success, Otherwise, returns negative error code, rte_errno is set
5427 : : * and error structure is filled.
5428 : : */
5429 : : static struct rte_flow_template_table *
5430 : 0 : flow_hw_template_table_create(struct rte_eth_dev *dev,
5431 : : const struct rte_flow_template_table_attr *attr,
5432 : : struct rte_flow_pattern_template *item_templates[],
5433 : : uint8_t nb_item_templates,
5434 : : struct rte_flow_actions_template *action_templates[],
5435 : : uint8_t nb_action_templates,
5436 : : struct rte_flow_error *error)
5437 : : {
5438 : 0 : struct mlx5_flow_template_table_cfg cfg = {
5439 : : .attr = *attr,
5440 : : .external = true,
5441 : : };
5442 : 0 : uint32_t group = attr->flow_attr.group;
5443 : :
5444 [ # # ]: 0 : if (flow_hw_translate_group(dev, &cfg, group, &cfg.attr.flow_attr.group, error))
5445 : : return NULL;
5446 [ # # # # ]: 0 : if (!cfg.attr.flow_attr.group &&
5447 : 0 : rte_flow_template_table_resizable(dev->data->port_id, attr)) {
5448 : 0 : rte_flow_error_set(error, EINVAL,
5449 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5450 : : "table cannot be resized: invalid group");
5451 : 0 : return NULL;
5452 : : }
5453 : 0 : return flow_hw_table_create(dev, &cfg, item_templates, nb_item_templates,
5454 : : action_templates, nb_action_templates, error);
5455 : : }
5456 : :
5457 : : static void
5458 : 0 : mlx5_destroy_multi_pattern_segment(struct mlx5_multi_pattern_segment *segment)
5459 : : {
5460 : : int i;
5461 : :
5462 [ # # ]: 0 : if (segment->mhdr_action)
5463 : 0 : mlx5dr_action_destroy(segment->mhdr_action);
5464 [ # # ]: 0 : for (i = 0; i < MLX5_MULTIPATTERN_ENCAP_NUM; i++) {
5465 [ # # ]: 0 : if (segment->reformat_action[i])
5466 : 0 : mlx5dr_action_destroy(segment->reformat_action[i]);
5467 : : }
5468 : 0 : segment->capacity = 0;
5469 : 0 : }
5470 : :
5471 : : static void
5472 : : flow_hw_destroy_table_multi_pattern_ctx(struct rte_flow_template_table *table)
5473 : : {
5474 : : int sx;
5475 : :
5476 [ # # ]: 0 : for (sx = 0; sx < MLX5_MAX_TABLE_RESIZE_NUM; sx++)
5477 : 0 : mlx5_destroy_multi_pattern_segment(table->mpctx.segments + sx);
5478 : : }
5479 : : /**
5480 : : * Destroy flow table.
5481 : : *
5482 : : * @param[in] dev
5483 : : * Pointer to the rte_eth_dev structure.
5484 : : * @param[in] table
5485 : : * Pointer to the table to be destroyed.
5486 : : * @param[out] error
5487 : : * Pointer to error structure.
5488 : : *
5489 : : * @return
5490 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
5491 : : */
5492 : : static int
5493 : 0 : flow_hw_table_destroy(struct rte_eth_dev *dev,
5494 : : struct rte_flow_template_table *table,
5495 : : struct rte_flow_error *error)
5496 : : {
5497 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
5498 : : int i;
5499 : 0 : uint32_t fidx = 1;
5500 : 0 : uint32_t ridx = 1;
5501 : :
5502 : : /* Build ipool allocated object bitmap. */
5503 [ # # ]: 0 : if (table->resource)
5504 : 0 : mlx5_ipool_flush_cache(table->resource);
5505 : 0 : mlx5_ipool_flush_cache(table->flow);
5506 : : /* Check if ipool has allocated objects. */
5507 [ # # # # ]: 0 : if (table->refcnt ||
5508 : 0 : mlx5_ipool_get_next(table->flow, &fidx) ||
5509 [ # # # # ]: 0 : (table->resource && mlx5_ipool_get_next(table->resource, &ridx))) {
5510 : 0 : DRV_LOG(WARNING, "Table %p is still in use.", (void *)table);
5511 : 0 : return rte_flow_error_set(error, EBUSY,
5512 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5513 : : NULL,
5514 : : "table is in use");
5515 : : }
5516 [ # # ]: 0 : LIST_REMOVE(table, next);
5517 [ # # ]: 0 : for (i = 0; i < table->nb_item_templates; i++)
5518 : 0 : rte_atomic_fetch_sub_explicit(&table->its[i]->refcnt,
5519 : : 1, rte_memory_order_relaxed);
5520 [ # # ]: 0 : for (i = 0; i < table->nb_action_templates; i++) {
5521 : 0 : __flow_hw_action_template_destroy(dev, &table->ats[i].acts);
5522 : 0 : rte_atomic_fetch_sub_explicit(&table->ats[i].action_template->refcnt,
5523 : : 1, rte_memory_order_relaxed);
5524 : : }
5525 : : flow_hw_destroy_table_multi_pattern_ctx(table);
5526 [ # # ]: 0 : if (table->matcher_info[0].jump)
5527 : 0 : mlx5dr_action_destroy(table->matcher_info[0].jump);
5528 [ # # ]: 0 : if (table->matcher_info[0].matcher)
5529 : 0 : mlx5dr_matcher_destroy(table->matcher_info[0].matcher);
5530 [ # # ]: 0 : if (table->matcher_info[1].jump)
5531 : 0 : mlx5dr_action_destroy(table->matcher_info[1].jump);
5532 [ # # ]: 0 : if (table->matcher_info[1].matcher)
5533 : 0 : mlx5dr_matcher_destroy(table->matcher_info[1].matcher);
5534 : 0 : mlx5_hlist_unregister(priv->sh->groups, &table->grp->entry);
5535 [ # # ]: 0 : if (table->resource)
5536 : 0 : mlx5_ipool_destroy(table->resource);
5537 : 0 : mlx5_free(table->flow_aux);
5538 : 0 : mlx5_ipool_destroy(table->flow);
5539 : 0 : mlx5_free(table);
5540 : 0 : return 0;
5541 : : }
5542 : :
5543 : : /**
5544 : : * Parse group's miss actions.
5545 : : *
5546 : : * @param[in] dev
5547 : : * Pointer to the rte_eth_dev structure.
5548 : : * @param[in] cfg
5549 : : * Pointer to the table_cfg structure.
5550 : : * @param[in] actions
5551 : : * Array of actions to perform on group miss. Supported types:
5552 : : * RTE_FLOW_ACTION_TYPE_JUMP, RTE_FLOW_ACTION_TYPE_VOID, RTE_FLOW_ACTION_TYPE_END.
5553 : : * @param[out] dst_group_id
5554 : : * Pointer to destination group id output. will be set to 0 if actions is END,
5555 : : * otherwise will be set to destination group id.
5556 : : * @param[out] error
5557 : : * Pointer to error structure.
5558 : : *
5559 : : * @return
5560 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
5561 : : */
5562 : :
5563 : : static int
5564 : 0 : flow_hw_group_parse_miss_actions(struct rte_eth_dev *dev,
5565 : : struct mlx5_flow_template_table_cfg *cfg,
5566 : : const struct rte_flow_action actions[],
5567 : : uint32_t *dst_group_id,
5568 : : struct rte_flow_error *error)
5569 : : {
5570 : : const struct rte_flow_action_jump *jump_conf;
5571 : 0 : uint32_t temp = 0;
5572 : : uint32_t i;
5573 : :
5574 [ # # ]: 0 : for (i = 0; actions[i].type != RTE_FLOW_ACTION_TYPE_END; i++) {
5575 [ # # # ]: 0 : switch (actions[i].type) {
5576 : 0 : case RTE_FLOW_ACTION_TYPE_VOID:
5577 : 0 : continue;
5578 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP:
5579 [ # # ]: 0 : if (temp)
5580 : 0 : return rte_flow_error_set(error, ENOTSUP,
5581 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, actions,
5582 : : "Miss actions can contain only a single JUMP");
5583 : :
5584 : 0 : jump_conf = (const struct rte_flow_action_jump *)actions[i].conf;
5585 [ # # ]: 0 : if (!jump_conf)
5586 : 0 : return rte_flow_error_set(error, EINVAL,
5587 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5588 : : jump_conf, "Jump conf must not be NULL");
5589 : :
5590 [ # # ]: 0 : if (flow_hw_translate_group(dev, cfg, jump_conf->group, &temp, error))
5591 : 0 : return -rte_errno;
5592 : :
5593 [ # # ]: 0 : if (!temp)
5594 : 0 : return rte_flow_error_set(error, EINVAL,
5595 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5596 : : "Failed to set group miss actions - Invalid target group");
5597 : : break;
5598 : 0 : default:
5599 : 0 : return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
5600 : : &actions[i], "Unsupported default miss action type");
5601 : : }
5602 : : }
5603 : :
5604 : 0 : *dst_group_id = temp;
5605 : 0 : return 0;
5606 : : }
5607 : :
5608 : : /**
5609 : : * Set group's miss group.
5610 : : *
5611 : : * @param[in] dev
5612 : : * Pointer to the rte_eth_dev structure.
5613 : : * @param[in] cfg
5614 : : * Pointer to the table_cfg structure.
5615 : : * @param[in] src_grp
5616 : : * Pointer to source group structure.
5617 : : * if NULL, a new group will be created based on group id from cfg->attr.flow_attr.group.
5618 : : * @param[in] dst_grp
5619 : : * Pointer to destination group structure.
5620 : : * @param[out] error
5621 : : * Pointer to error structure.
5622 : : *
5623 : : * @return
5624 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
5625 : : */
5626 : :
5627 : : static int
5628 : 0 : flow_hw_group_set_miss_group(struct rte_eth_dev *dev,
5629 : : struct mlx5_flow_template_table_cfg *cfg,
5630 : : struct mlx5_flow_group *src_grp,
5631 : : struct mlx5_flow_group *dst_grp,
5632 : : struct rte_flow_error *error)
5633 : : {
5634 : 0 : struct rte_flow_error sub_error = {
5635 : : .type = RTE_FLOW_ERROR_TYPE_NONE,
5636 : : .cause = NULL,
5637 : : .message = NULL,
5638 : : };
5639 : 0 : struct mlx5_flow_cb_ctx ctx = {
5640 : : .dev = dev,
5641 : : .error = &sub_error,
5642 : 0 : .data = &cfg->attr.flow_attr,
5643 : : };
5644 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
5645 : : struct mlx5_list_entry *ge;
5646 : : bool ref = false;
5647 : : int ret;
5648 : :
5649 [ # # ]: 0 : if (!dst_grp)
5650 : : return -EINVAL;
5651 : :
5652 : : /* If group doesn't exist - needs to be created. */
5653 [ # # ]: 0 : if (!src_grp) {
5654 : 0 : ge = mlx5_hlist_register(priv->sh->groups, cfg->attr.flow_attr.group, &ctx);
5655 [ # # ]: 0 : if (!ge)
5656 : 0 : return -rte_errno;
5657 : :
5658 : : src_grp = container_of(ge, struct mlx5_flow_group, entry);
5659 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->flow_hw_grp, src_grp, next);
5660 : : ref = true;
5661 [ # # ]: 0 : } else if (!src_grp->miss_group) {
5662 : : /* If group exists, but has no miss actions - need to increase ref_cnt. */
5663 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->flow_hw_grp, src_grp, next);
5664 : 0 : src_grp->entry.ref_cnt++;
5665 : : ref = true;
5666 : : }
5667 : :
5668 : 0 : ret = mlx5dr_table_set_default_miss(src_grp->tbl, dst_grp->tbl);
5669 [ # # ]: 0 : if (ret)
5670 : 0 : goto mlx5dr_error;
5671 : :
5672 : : /* If group existed and had old miss actions - ref_cnt is already correct.
5673 : : * However, need to reduce ref counter for old miss group.
5674 : : */
5675 [ # # ]: 0 : if (src_grp->miss_group)
5676 : 0 : mlx5_hlist_unregister(priv->sh->groups, &src_grp->miss_group->entry);
5677 : :
5678 : 0 : src_grp->miss_group = dst_grp;
5679 : 0 : return 0;
5680 : :
5681 : : mlx5dr_error:
5682 : : /* Reduce src_grp ref_cnt back & remove from grp list in case of mlx5dr error */
5683 [ # # ]: 0 : if (ref) {
5684 : 0 : mlx5_hlist_unregister(priv->sh->groups, &src_grp->entry);
5685 [ # # ]: 0 : LIST_REMOVE(src_grp, next);
5686 : : }
5687 : :
5688 : 0 : return rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5689 : : "Failed to set group miss actions");
5690 : : }
5691 : :
5692 : : /**
5693 : : * Unset group's miss group.
5694 : : *
5695 : : * @param[in] dev
5696 : : * Pointer to the rte_eth_dev structure.
5697 : : * @param[in] grp
5698 : : * Pointer to group structure.
5699 : : * @param[out] error
5700 : : * Pointer to error structure.
5701 : : *
5702 : : * @return
5703 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
5704 : : */
5705 : :
5706 : : static int
5707 : 0 : flow_hw_group_unset_miss_group(struct rte_eth_dev *dev,
5708 : : struct mlx5_flow_group *grp,
5709 : : struct rte_flow_error *error)
5710 : : {
5711 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
5712 : : int ret;
5713 : :
5714 : : /* If group doesn't exist - no need to change anything. */
5715 [ # # ]: 0 : if (!grp)
5716 : : return 0;
5717 : :
5718 : : /* If group exists, but miss actions is already default behavior -
5719 : : * no need to change anything.
5720 : : */
5721 [ # # ]: 0 : if (!grp->miss_group)
5722 : : return 0;
5723 : :
5724 : 0 : ret = mlx5dr_table_set_default_miss(grp->tbl, NULL);
5725 [ # # ]: 0 : if (ret)
5726 : 0 : return rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5727 : : "Failed to unset group miss actions");
5728 : :
5729 : 0 : mlx5_hlist_unregister(priv->sh->groups, &grp->miss_group->entry);
5730 : 0 : grp->miss_group = NULL;
5731 : :
5732 [ # # ]: 0 : LIST_REMOVE(grp, next);
5733 : 0 : mlx5_hlist_unregister(priv->sh->groups, &grp->entry);
5734 : :
5735 : 0 : return 0;
5736 : : }
5737 : :
5738 : : /**
5739 : : * Set group miss actions.
5740 : : *
5741 : : * @param[in] dev
5742 : : * Pointer to the rte_eth_dev structure.
5743 : : * @param[in] group_id
5744 : : * Group id.
5745 : : * @param[in] attr
5746 : : * Pointer to group attributes structure.
5747 : : * @param[in] actions
5748 : : * Array of actions to perform on group miss. Supported types:
5749 : : * RTE_FLOW_ACTION_TYPE_JUMP, RTE_FLOW_ACTION_TYPE_VOID, RTE_FLOW_ACTION_TYPE_END.
5750 : : * @param[out] error
5751 : : * Pointer to error structure.
5752 : : *
5753 : : * @return
5754 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
5755 : : */
5756 : :
5757 : : static int
5758 : 0 : flow_hw_group_set_miss_actions(struct rte_eth_dev *dev,
5759 : : uint32_t group_id,
5760 : : const struct rte_flow_group_attr *attr,
5761 : : const struct rte_flow_action actions[],
5762 : : struct rte_flow_error *error)
5763 : : {
5764 : 0 : struct rte_flow_error sub_error = {
5765 : : .type = RTE_FLOW_ERROR_TYPE_NONE,
5766 : : .cause = NULL,
5767 : : .message = NULL,
5768 : : };
5769 : 0 : struct mlx5_flow_template_table_cfg cfg = {
5770 : : .external = true,
5771 : : .attr = {
5772 : : .flow_attr = {
5773 : : .group = group_id,
5774 : 0 : .ingress = attr->ingress,
5775 : 0 : .egress = attr->egress,
5776 : 0 : .transfer = attr->transfer,
5777 : : },
5778 : : },
5779 : : };
5780 : 0 : struct mlx5_flow_cb_ctx ctx = {
5781 : : .dev = dev,
5782 : : .error = &sub_error,
5783 : : .data = &cfg.attr.flow_attr,
5784 : : };
5785 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
5786 : : struct mlx5_flow_group *src_grp = NULL;
5787 : : struct mlx5_flow_group *dst_grp = NULL;
5788 : : struct mlx5_list_entry *ge;
5789 : 0 : uint32_t dst_group_id = 0;
5790 : : int ret;
5791 : :
5792 [ # # ]: 0 : if (flow_hw_translate_group(dev, &cfg, group_id, &group_id, error))
5793 : 0 : return -rte_errno;
5794 : :
5795 [ # # ]: 0 : if (!group_id)
5796 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5797 : : NULL, "Failed to set group miss actions - invalid group id");
5798 : :
5799 : 0 : ret = flow_hw_group_parse_miss_actions(dev, &cfg, actions, &dst_group_id, error);
5800 [ # # ]: 0 : if (ret)
5801 : 0 : return -rte_errno;
5802 : :
5803 [ # # ]: 0 : if (dst_group_id == group_id) {
5804 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5805 : : NULL, "Failed to set group miss actions - target group id must differ from group_id");
5806 : : }
5807 : :
5808 : 0 : cfg.attr.flow_attr.group = group_id;
5809 : 0 : ge = mlx5_hlist_lookup(priv->sh->groups, group_id, &ctx);
5810 [ # # ]: 0 : if (ge)
5811 : : src_grp = container_of(ge, struct mlx5_flow_group, entry);
5812 : :
5813 [ # # ]: 0 : if (dst_group_id) {
5814 : : /* Increase ref_cnt for new miss group. */
5815 : 0 : cfg.attr.flow_attr.group = dst_group_id;
5816 : 0 : ge = mlx5_hlist_register(priv->sh->groups, dst_group_id, &ctx);
5817 [ # # ]: 0 : if (!ge)
5818 : 0 : return -rte_errno;
5819 : :
5820 : : dst_grp = container_of(ge, struct mlx5_flow_group, entry);
5821 : :
5822 : 0 : cfg.attr.flow_attr.group = group_id;
5823 : 0 : ret = flow_hw_group_set_miss_group(dev, &cfg, src_grp, dst_grp, error);
5824 [ # # ]: 0 : if (ret)
5825 : 0 : goto error;
5826 : : } else {
5827 : 0 : return flow_hw_group_unset_miss_group(dev, src_grp, error);
5828 : : }
5829 : :
5830 : : return 0;
5831 : :
5832 : : error:
5833 : : if (dst_grp)
5834 : 0 : mlx5_hlist_unregister(priv->sh->groups, &dst_grp->entry);
5835 : 0 : return -rte_errno;
5836 : : }
5837 : :
5838 : : static bool
5839 : : flow_hw_modify_field_is_used(const struct rte_flow_action_modify_field *action,
5840 : : enum rte_flow_field_id field)
5841 : : {
5842 [ # # # # : 0 : return action->src.field == field || action->dst.field == field;
# # # # #
# # # # #
# # # # #
# # # # #
# # # # ]
5843 : : }
5844 : :
5845 : : static bool
5846 : : flow_hw_modify_field_is_geneve_opt(enum rte_flow_field_id field)
5847 : : {
5848 : : return field == RTE_FLOW_FIELD_GENEVE_OPT_TYPE ||
5849 : 0 : field == RTE_FLOW_FIELD_GENEVE_OPT_CLASS ||
5850 : : field == RTE_FLOW_FIELD_GENEVE_OPT_DATA;
5851 : : }
5852 : :
5853 : : static bool
5854 : 0 : flow_hw_modify_field_is_add_dst_valid(const struct rte_flow_action_modify_field *conf)
5855 : : {
5856 [ # # ]: 0 : if (conf->operation != RTE_FLOW_MODIFY_ADD)
5857 : : return true;
5858 [ # # ]: 0 : if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
5859 : : conf->src.field == RTE_FLOW_FIELD_VALUE)
5860 : : return true;
5861 [ # # ]: 0 : switch (conf->dst.field) {
5862 : : case RTE_FLOW_FIELD_IPV4_TTL:
5863 : : case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
5864 : : case RTE_FLOW_FIELD_TCP_SEQ_NUM:
5865 : : case RTE_FLOW_FIELD_TCP_ACK_NUM:
5866 : : case RTE_FLOW_FIELD_TAG:
5867 : : case RTE_FLOW_FIELD_META:
5868 : : case RTE_FLOW_FIELD_FLEX_ITEM:
5869 : : case RTE_FLOW_FIELD_TCP_DATA_OFFSET:
5870 : : case RTE_FLOW_FIELD_IPV4_IHL:
5871 : : case RTE_FLOW_FIELD_IPV4_TOTAL_LEN:
5872 : : case RTE_FLOW_FIELD_IPV6_PAYLOAD_LEN:
5873 : : return true;
5874 : : default:
5875 : : break;
5876 : : }
5877 : 0 : return false;
5878 : : }
5879 : :
5880 : : /**
5881 : : * Validate the level value for modify field action.
5882 : : *
5883 : : * @param[in] data
5884 : : * Pointer to the rte_flow_field_data structure either src or dst.
5885 : : * @param[in] inner_supported
5886 : : * Indicator whether inner should be supported.
5887 : : * @param[out] error
5888 : : * Pointer to error structure.
5889 : : *
5890 : : * @return
5891 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
5892 : : */
5893 : : static int
5894 : 0 : flow_hw_validate_modify_field_level(const struct rte_flow_field_data *data,
5895 : : bool inner_supported,
5896 : : struct rte_flow_error *error)
5897 : : {
5898 [ # # # # : 0 : switch ((int)data->field) {
# ]
5899 : : case RTE_FLOW_FIELD_START:
5900 : : case RTE_FLOW_FIELD_VLAN_TYPE:
5901 : : case RTE_FLOW_FIELD_RANDOM:
5902 : : case RTE_FLOW_FIELD_FLEX_ITEM:
5903 : : /*
5904 : : * Level shouldn't be valid since field isn't supported or
5905 : : * doesn't use 'level'.
5906 : : */
5907 : : break;
5908 : : case RTE_FLOW_FIELD_MARK:
5909 : : case RTE_FLOW_FIELD_META:
5910 : : case RTE_FLOW_FIELD_METER_COLOR:
5911 : : case RTE_FLOW_FIELD_HASH_RESULT:
5912 : : /* For meta data fields encapsulation level is don't-care. */
5913 : : break;
5914 : 0 : case RTE_FLOW_FIELD_TAG:
5915 : : case MLX5_RTE_FLOW_FIELD_META_REG:
5916 : : /*
5917 : : * The tag array for RTE_FLOW_FIELD_TAG type is provided using
5918 : : * 'tag_index' field. In old API, it was provided using 'level'
5919 : : * field and it is still supported for backwards compatibility.
5920 : : * Therefore, for meta tag field only, level is matter. It is
5921 : : * taken as tag index when 'tag_index' field isn't set, and
5922 : : * return error otherwise.
5923 : : */
5924 [ # # ]: 0 : if (data->level > 0) {
5925 [ # # ]: 0 : if (data->tag_index > 0)
5926 : 0 : return rte_flow_error_set(error, EINVAL,
5927 : : RTE_FLOW_ERROR_TYPE_ACTION,
5928 : : data,
5929 : : "tag array can be provided using 'level' or 'tag_index' fields, not both");
5930 : 0 : DRV_LOG(WARNING,
5931 : : "tag array provided in 'level' field instead of 'tag_index' field.");
5932 : : }
5933 : : break;
5934 : 0 : case RTE_FLOW_FIELD_MAC_DST:
5935 : : case RTE_FLOW_FIELD_MAC_SRC:
5936 : : case RTE_FLOW_FIELD_MAC_TYPE:
5937 : : case RTE_FLOW_FIELD_IPV4_IHL:
5938 : : case RTE_FLOW_FIELD_IPV4_TOTAL_LEN:
5939 : : case RTE_FLOW_FIELD_IPV4_DSCP:
5940 : : case RTE_FLOW_FIELD_IPV4_ECN:
5941 : : case RTE_FLOW_FIELD_IPV4_TTL:
5942 : : case RTE_FLOW_FIELD_IPV4_SRC:
5943 : : case RTE_FLOW_FIELD_IPV4_DST:
5944 : : case RTE_FLOW_FIELD_IPV6_TRAFFIC_CLASS:
5945 : : case RTE_FLOW_FIELD_IPV6_FLOW_LABEL:
5946 : : case RTE_FLOW_FIELD_IPV6_PAYLOAD_LEN:
5947 : : case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
5948 : : case RTE_FLOW_FIELD_IPV6_SRC:
5949 : : case RTE_FLOW_FIELD_IPV6_DST:
5950 : : case RTE_FLOW_FIELD_TCP_PORT_SRC:
5951 : : case RTE_FLOW_FIELD_TCP_PORT_DST:
5952 : : case RTE_FLOW_FIELD_TCP_FLAGS:
5953 : : case RTE_FLOW_FIELD_TCP_DATA_OFFSET:
5954 : : case RTE_FLOW_FIELD_UDP_PORT_SRC:
5955 : : case RTE_FLOW_FIELD_UDP_PORT_DST:
5956 [ # # ]: 0 : if (data->level > 2)
5957 : 0 : return rte_flow_error_set(error, ENOTSUP,
5958 : : RTE_FLOW_ERROR_TYPE_ACTION,
5959 : : data,
5960 : : "second inner header fields modification is not supported");
5961 [ # # ]: 0 : if (inner_supported)
5962 : : break;
5963 : : /* Fallthrough */
5964 : : case RTE_FLOW_FIELD_VLAN_ID:
5965 : : case RTE_FLOW_FIELD_IPV4_PROTO:
5966 : : case RTE_FLOW_FIELD_IPV6_PROTO:
5967 : : case RTE_FLOW_FIELD_IPV6_DSCP:
5968 : : case RTE_FLOW_FIELD_IPV6_ECN:
5969 : : case RTE_FLOW_FIELD_TCP_SEQ_NUM:
5970 : : case RTE_FLOW_FIELD_TCP_ACK_NUM:
5971 : : case RTE_FLOW_FIELD_ESP_PROTO:
5972 : : case RTE_FLOW_FIELD_ESP_SPI:
5973 : : case RTE_FLOW_FIELD_ESP_SEQ_NUM:
5974 : : case RTE_FLOW_FIELD_VXLAN_VNI:
5975 : : case RTE_FLOW_FIELD_VXLAN_LAST_RSVD:
5976 : : case RTE_FLOW_FIELD_GENEVE_VNI:
5977 : : case RTE_FLOW_FIELD_GENEVE_OPT_TYPE:
5978 : : case RTE_FLOW_FIELD_GENEVE_OPT_CLASS:
5979 : : case RTE_FLOW_FIELD_GENEVE_OPT_DATA:
5980 : : case RTE_FLOW_FIELD_GTP_TEID:
5981 : : case RTE_FLOW_FIELD_GTP_PSC_QFI:
5982 [ # # ]: 0 : if (data->level > 1)
5983 : 0 : return rte_flow_error_set(error, ENOTSUP,
5984 : : RTE_FLOW_ERROR_TYPE_ACTION,
5985 : : data,
5986 : : "inner header fields modification is not supported");
5987 : : break;
5988 : 0 : case RTE_FLOW_FIELD_MPLS:
5989 [ # # ]: 0 : if (data->level == 1)
5990 : 0 : return rte_flow_error_set(error, ENOTSUP,
5991 : : RTE_FLOW_ERROR_TYPE_ACTION,
5992 : : data,
5993 : : "outer MPLS header modification is not supported");
5994 [ # # ]: 0 : if (data->level > 2)
5995 : 0 : return rte_flow_error_set(error, ENOTSUP,
5996 : : RTE_FLOW_ERROR_TYPE_ACTION,
5997 : : data,
5998 : : "inner MPLS header modification is not supported");
5999 : : break;
6000 : 0 : case RTE_FLOW_FIELD_POINTER:
6001 : : case RTE_FLOW_FIELD_VALUE:
6002 : : default:
6003 : : MLX5_ASSERT(false);
6004 : : }
6005 : : return 0;
6006 : : }
6007 : :
6008 : : static int
6009 : 0 : flow_hw_validate_action_modify_field(struct rte_eth_dev *dev,
6010 : : const struct rte_flow_action *action,
6011 : : const struct rte_flow_action *mask,
6012 : : struct rte_flow_error *error)
6013 : : {
6014 : 0 : const struct rte_flow_action_modify_field *action_conf = action->conf;
6015 : 0 : const struct rte_flow_action_modify_field *mask_conf = mask->conf;
6016 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6017 : 0 : struct mlx5_hca_attr *attr = &priv->sh->cdev->config.hca_attr;
6018 : : int ret;
6019 : :
6020 [ # # ]: 0 : if (!mask_conf)
6021 : 0 : return rte_flow_error_set(error, EINVAL,
6022 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6023 : : "modify_field mask conf is missing");
6024 [ # # ]: 0 : if (action_conf->operation != mask_conf->operation)
6025 : 0 : return rte_flow_error_set(error, EINVAL,
6026 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6027 : : "modify_field operation mask and template are not equal");
6028 [ # # ]: 0 : if (action_conf->dst.field != mask_conf->dst.field)
6029 : 0 : return rte_flow_error_set(error, EINVAL,
6030 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6031 : : "destination field mask and template are not equal");
6032 : 0 : if (action_conf->dst.field == RTE_FLOW_FIELD_POINTER ||
6033 [ # # ]: 0 : action_conf->dst.field == RTE_FLOW_FIELD_VALUE ||
6034 : : action_conf->dst.field == RTE_FLOW_FIELD_HASH_RESULT)
6035 : 0 : return rte_flow_error_set(error, EINVAL,
6036 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6037 : : "immediate value, pointer and hash result cannot be used as destination");
6038 : 0 : ret = flow_hw_validate_modify_field_level(&action_conf->dst, false, error);
6039 [ # # ]: 0 : if (ret)
6040 : : return ret;
6041 [ # # # # ]: 0 : if (action_conf->dst.field != RTE_FLOW_FIELD_FLEX_ITEM &&
6042 : : !flow_hw_modify_field_is_geneve_opt(action_conf->dst.field)) {
6043 [ # # ]: 0 : if (action_conf->dst.tag_index &&
6044 : : !flow_modify_field_support_tag_array(action_conf->dst.field))
6045 : 0 : return rte_flow_error_set(error, EINVAL,
6046 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6047 : : "destination tag index is not supported");
6048 [ # # ]: 0 : if (action_conf->dst.class_id)
6049 : 0 : return rte_flow_error_set(error, EINVAL,
6050 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6051 : : "destination class id is not supported");
6052 : : }
6053 [ # # ]: 0 : if (mask_conf->dst.level != UINT8_MAX)
6054 : 0 : return rte_flow_error_set(error, EINVAL,
6055 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6056 : : "destination encapsulation level must be fully masked");
6057 [ # # ]: 0 : if (mask_conf->dst.offset != UINT32_MAX)
6058 : 0 : return rte_flow_error_set(error, EINVAL,
6059 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6060 : : "destination offset level must be fully masked");
6061 [ # # ]: 0 : if (action_conf->src.field != mask_conf->src.field)
6062 : 0 : return rte_flow_error_set(error, EINVAL,
6063 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6064 : : "destination field mask and template are not equal");
6065 [ # # ]: 0 : if (action_conf->src.field != RTE_FLOW_FIELD_POINTER &&
6066 : : action_conf->src.field != RTE_FLOW_FIELD_VALUE) {
6067 [ # # # # ]: 0 : if (action_conf->src.field != RTE_FLOW_FIELD_FLEX_ITEM &&
6068 : : !flow_hw_modify_field_is_geneve_opt(action_conf->src.field)) {
6069 [ # # ]: 0 : if (action_conf->src.tag_index &&
6070 : : !flow_modify_field_support_tag_array(action_conf->src.field))
6071 : 0 : return rte_flow_error_set(error, EINVAL,
6072 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6073 : : "source tag index is not supported");
6074 [ # # ]: 0 : if (action_conf->src.class_id)
6075 : 0 : return rte_flow_error_set(error, EINVAL,
6076 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6077 : : "source class id is not supported");
6078 : : }
6079 [ # # ]: 0 : if (mask_conf->src.level != UINT8_MAX)
6080 : 0 : return rte_flow_error_set(error, EINVAL,
6081 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6082 : : "source encapsulation level must be fully masked");
6083 [ # # ]: 0 : if (mask_conf->src.offset != UINT32_MAX)
6084 : 0 : return rte_flow_error_set(error, EINVAL,
6085 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6086 : : "source offset level must be fully masked");
6087 : 0 : ret = flow_hw_validate_modify_field_level(&action_conf->src, true, error);
6088 [ # # ]: 0 : if (ret)
6089 : : return ret;
6090 : : }
6091 [ # # ]: 0 : if ((action_conf->dst.field == RTE_FLOW_FIELD_TAG &&
6092 [ # # # # ]: 0 : action_conf->dst.tag_index >= MLX5_FLOW_HW_TAGS_MAX &&
6093 : 0 : action_conf->dst.tag_index != RTE_PMD_MLX5_LINEAR_HASH_TAG_INDEX) ||
6094 [ # # ]: 0 : (action_conf->src.field == RTE_FLOW_FIELD_TAG &&
6095 [ # # # # ]: 0 : action_conf->src.tag_index >= MLX5_FLOW_HW_TAGS_MAX &&
6096 : : action_conf->src.tag_index != RTE_PMD_MLX5_LINEAR_HASH_TAG_INDEX))
6097 : 0 : return rte_flow_error_set(error, EINVAL,
6098 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6099 : : "tag index is out of range");
6100 [ # # # # ]: 0 : if ((action_conf->dst.field == RTE_FLOW_FIELD_TAG &&
6101 [ # # # # ]: 0 : flow_hw_get_reg_id(dev, RTE_FLOW_ITEM_TYPE_TAG, action_conf->dst.tag_index) == REG_NON) ||
6102 [ # # ]: 0 : (action_conf->src.field == RTE_FLOW_FIELD_TAG &&
6103 [ # # ]: 0 : flow_hw_get_reg_id(dev, RTE_FLOW_ITEM_TYPE_TAG, action_conf->src.tag_index) == REG_NON))
6104 : 0 : return rte_flow_error_set(error, EINVAL,
6105 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6106 : : "tag index is out of range");
6107 [ # # ]: 0 : if (mask_conf->width != UINT32_MAX)
6108 : 0 : return rte_flow_error_set(error, EINVAL,
6109 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6110 : : "modify_field width field must be fully masked");
6111 [ # # ]: 0 : if (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_START))
6112 : 0 : return rte_flow_error_set(error, EINVAL,
6113 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6114 : : "modifying arbitrary place in a packet is not supported");
6115 [ # # ]: 0 : if (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_VLAN_TYPE))
6116 : 0 : return rte_flow_error_set(error, EINVAL,
6117 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6118 : : "modifying vlan_type is not supported");
6119 [ # # ]: 0 : if (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_RANDOM))
6120 : 0 : return rte_flow_error_set(error, EINVAL,
6121 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6122 : : "modifying random value is not supported");
6123 : : /**
6124 : : * Geneve VNI modification is supported only when Geneve header is
6125 : : * parsed natively. When GENEVE options are supported, they both Geneve
6126 : : * and options headers are parsed as a flex parser.
6127 : : */
6128 [ # # ]: 0 : if (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_GENEVE_VNI) &&
6129 [ # # ]: 0 : attr->geneve_tlv_opt)
6130 : 0 : return rte_flow_error_set(error, EINVAL,
6131 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6132 : : "modifying Geneve VNI is not supported when GENEVE opt is supported");
6133 [ # # # # ]: 0 : if (priv->tlv_options == NULL &&
6134 [ # # ]: 0 : (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_GENEVE_OPT_TYPE) ||
6135 [ # # ]: 0 : flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_GENEVE_OPT_CLASS) ||
6136 : : flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_GENEVE_OPT_DATA)))
6137 : 0 : return rte_flow_error_set(error, EINVAL,
6138 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6139 : : "modifying Geneve TLV option is supported only after parser configuration");
6140 : : /* Due to HW bug, tunnel MPLS header is read only. */
6141 [ # # ]: 0 : if (action_conf->dst.field == RTE_FLOW_FIELD_MPLS)
6142 : 0 : return rte_flow_error_set(error, EINVAL,
6143 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6144 : : "MPLS cannot be used as destination");
6145 : : /* ADD_FIELD is not supported for all the fields. */
6146 [ # # ]: 0 : if (!flow_hw_modify_field_is_add_dst_valid(action_conf))
6147 : 0 : return rte_flow_error_set(error, EINVAL,
6148 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6149 : : "invalid add_field destination");
6150 : : return 0;
6151 : : }
6152 : :
6153 : : static int
6154 : 0 : flow_hw_validate_action_port_representor(struct rte_eth_dev *dev __rte_unused,
6155 : : const struct rte_flow_actions_template_attr *attr,
6156 : : const struct rte_flow_action *action,
6157 : : const struct rte_flow_action *mask,
6158 : : struct rte_flow_error *error)
6159 : : {
6160 : : const struct rte_flow_action_ethdev *action_conf = NULL;
6161 : : const struct rte_flow_action_ethdev *mask_conf = NULL;
6162 : :
6163 : : /* If transfer is set, port has been validated as proxy port. */
6164 [ # # ]: 0 : if (!attr->transfer)
6165 : 0 : return rte_flow_error_set(error, EINVAL,
6166 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6167 : : "cannot use port_representor actions"
6168 : : " without an E-Switch");
6169 [ # # ]: 0 : if (!action || !mask)
6170 : 0 : return rte_flow_error_set(error, EINVAL,
6171 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6172 : : "actiona and mask configuration must be set");
6173 : 0 : action_conf = action->conf;
6174 : 0 : mask_conf = mask->conf;
6175 [ # # # # : 0 : if (!mask_conf || mask_conf->port_id != MLX5_REPRESENTED_PORT_ESW_MGR ||
# # ]
6176 [ # # ]: 0 : !action_conf || action_conf->port_id != MLX5_REPRESENTED_PORT_ESW_MGR)
6177 : 0 : return rte_flow_error_set(error, EINVAL,
6178 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6179 : : "only eswitch manager port 0xffff is"
6180 : : " supported");
6181 : : return 0;
6182 : : }
6183 : :
6184 : : static int
6185 : 0 : flow_hw_validate_target_port_id(struct rte_eth_dev *dev,
6186 : : uint16_t target_port_id)
6187 : : {
6188 : : struct mlx5_priv *port_priv;
6189 : : struct mlx5_priv *dev_priv;
6190 : :
6191 [ # # ]: 0 : if (target_port_id == MLX5_REPRESENTED_PORT_ESW_MGR)
6192 : : return 0;
6193 : :
6194 : 0 : port_priv = mlx5_port_to_eswitch_info(target_port_id, false);
6195 [ # # ]: 0 : if (!port_priv) {
6196 : 0 : rte_errno = EINVAL;
6197 : 0 : DRV_LOG(ERR, "Port %u Failed to obtain E-Switch info for port %u",
6198 : : dev->data->port_id, target_port_id);
6199 : 0 : return -rte_errno;
6200 : : }
6201 : :
6202 : 0 : dev_priv = mlx5_dev_to_eswitch_info(dev);
6203 [ # # ]: 0 : if (!dev_priv) {
6204 : 0 : rte_errno = EINVAL;
6205 : 0 : DRV_LOG(ERR, "Port %u Failed to obtain E-Switch info for transfer proxy",
6206 : : dev->data->port_id);
6207 : 0 : return -rte_errno;
6208 : : }
6209 : :
6210 [ # # ]: 0 : if (port_priv->domain_id != dev_priv->domain_id) {
6211 : 0 : rte_errno = EINVAL;
6212 : 0 : DRV_LOG(ERR, "Port %u Failed to obtain E-Switch info for transfer proxy",
6213 : : dev->data->port_id);
6214 : 0 : return -rte_errno;
6215 : : }
6216 : :
6217 : : return 0;
6218 : : }
6219 : :
6220 : : static int
6221 : 0 : flow_hw_validate_action_represented_port(struct rte_eth_dev *dev,
6222 : : const struct rte_flow_action *action,
6223 : : const struct rte_flow_action *mask,
6224 : : struct rte_flow_error *error)
6225 : : {
6226 : 0 : const struct rte_flow_action_ethdev *action_conf = action->conf;
6227 : 0 : const struct rte_flow_action_ethdev *mask_conf = mask->conf;
6228 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6229 : :
6230 [ # # ]: 0 : if (!priv->sh->config.dv_esw_en)
6231 : 0 : return rte_flow_error_set(error, EINVAL,
6232 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6233 : : "cannot use represented_port actions"
6234 : : " without an E-Switch");
6235 [ # # # # ]: 0 : if (mask_conf && mask_conf->port_id) {
6236 [ # # ]: 0 : if (!action_conf)
6237 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
6238 : : action, "port index was not provided");
6239 : :
6240 [ # # ]: 0 : if (flow_hw_validate_target_port_id(dev, action_conf->port_id))
6241 : 0 : return rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
6242 : : action, "port index is invalid");
6243 : : }
6244 : : return 0;
6245 : : }
6246 : :
6247 : : /**
6248 : : * Validate AGE action.
6249 : : *
6250 : : * @param[in] dev
6251 : : * Pointer to rte_eth_dev structure.
6252 : : * @param[in] action
6253 : : * Pointer to the indirect action.
6254 : : * @param[in] action_flags
6255 : : * Holds the actions detected until now.
6256 : : * @param[in] fixed_cnt
6257 : : * Indicator if this list has a fixed COUNT action.
6258 : : * @param[out] error
6259 : : * Pointer to error structure.
6260 : : *
6261 : : * @return
6262 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
6263 : : */
6264 : : static int
6265 : 0 : flow_hw_validate_action_age(struct rte_eth_dev *dev,
6266 : : const struct rte_flow_action *action,
6267 : : uint64_t action_flags, bool fixed_cnt,
6268 : : struct rte_flow_error *error)
6269 : : {
6270 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6271 : 0 : struct mlx5_age_info *age_info = GET_PORT_AGE_INFO(priv);
6272 : :
6273 [ # # ]: 0 : if (!priv->sh->cdev->config.devx)
6274 : 0 : return rte_flow_error_set(error, ENOTSUP,
6275 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6276 : : NULL, "AGE action not supported");
6277 [ # # ]: 0 : if (age_info->ages_ipool == NULL)
6278 : 0 : return rte_flow_error_set(error, EINVAL,
6279 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6280 : : "aging pool not initialized");
6281 [ # # ]: 0 : if ((action_flags & MLX5_FLOW_ACTION_AGE) ||
6282 : : (action_flags & MLX5_FLOW_ACTION_INDIRECT_AGE))
6283 : 0 : return rte_flow_error_set(error, EINVAL,
6284 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6285 : : "duplicate AGE actions set");
6286 [ # # ]: 0 : if (fixed_cnt)
6287 : 0 : return rte_flow_error_set(error, EINVAL,
6288 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6289 : : "AGE and fixed COUNT combination is not supported");
6290 : : return 0;
6291 : : }
6292 : :
6293 : : /**
6294 : : * Validate count action.
6295 : : *
6296 : : * @param[in] dev
6297 : : * Pointer to rte_eth_dev structure.
6298 : : * @param[in] action
6299 : : * Pointer to the indirect action.
6300 : : * @param[in] mask
6301 : : * Pointer to the indirect action mask.
6302 : : * @param[in] action_flags
6303 : : * Holds the actions detected until now.
6304 : : * @param[out] error
6305 : : * Pointer to error structure.
6306 : : *
6307 : : * @return
6308 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
6309 : : */
6310 : : static int
6311 : 0 : flow_hw_validate_action_count(struct rte_eth_dev *dev,
6312 : : const struct rte_flow_action *action,
6313 : : const struct rte_flow_action *mask,
6314 : : uint64_t action_flags,
6315 : : struct rte_flow_error *error)
6316 : : {
6317 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6318 : 0 : const struct rte_flow_action_count *count = mask->conf;
6319 : :
6320 [ # # ]: 0 : if (!priv->sh->cdev->config.devx)
6321 : 0 : return rte_flow_error_set(error, ENOTSUP,
6322 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6323 : : "count action not supported");
6324 [ # # ]: 0 : if (!priv->hws_cpool)
6325 : 0 : return rte_flow_error_set(error, EINVAL,
6326 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6327 : : "counters pool not initialized");
6328 [ # # ]: 0 : if ((action_flags & MLX5_FLOW_ACTION_COUNT) ||
6329 : : (action_flags & MLX5_FLOW_ACTION_INDIRECT_COUNT))
6330 : 0 : return rte_flow_error_set(error, EINVAL,
6331 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6332 : : "duplicate count actions set");
6333 [ # # # # : 0 : if (count && count->id && (action_flags & MLX5_FLOW_ACTION_AGE))
# # ]
6334 : 0 : return rte_flow_error_set(error, EINVAL,
6335 : : RTE_FLOW_ERROR_TYPE_ACTION, mask,
6336 : : "AGE and COUNT action shared by mask combination is not supported");
6337 : : return 0;
6338 : : }
6339 : :
6340 : : /**
6341 : : * Validate meter_mark action.
6342 : : *
6343 : : * @param[in] dev
6344 : : * Pointer to rte_eth_dev structure.
6345 : : * @param[in] action
6346 : : * Pointer to the indirect action.
6347 : : * @param[in] indirect
6348 : : * If true, then provided action was passed using an indirect action.
6349 : : * @param[out] error
6350 : : * Pointer to error structure.
6351 : : *
6352 : : * @return
6353 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
6354 : : */
6355 : : static int
6356 : 0 : flow_hw_validate_action_meter_mark(struct rte_eth_dev *dev,
6357 : : const struct rte_flow_action *action,
6358 : : bool indirect,
6359 : : struct rte_flow_error *error)
6360 : : {
6361 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6362 : :
6363 : : RTE_SET_USED(action);
6364 : :
6365 [ # # ]: 0 : if (!priv->sh->cdev->config.devx)
6366 : 0 : return rte_flow_error_set(error, ENOTSUP,
6367 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6368 : : "meter_mark action not supported");
6369 [ # # # # ]: 0 : if (!indirect && priv->shared_host)
6370 : 0 : return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, action,
6371 : : "meter_mark action can only be used on host port");
6372 [ # # ]: 0 : if (!priv->hws_mpool)
6373 : 0 : return rte_flow_error_set(error, EINVAL,
6374 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6375 : : "meter_mark pool not initialized");
6376 : : return 0;
6377 : : }
6378 : :
6379 : : /**
6380 : : * Validate indirect action.
6381 : : *
6382 : : * @param[in] dev
6383 : : * Pointer to rte_eth_dev structure.
6384 : : * @param[in] action
6385 : : * Pointer to the indirect action.
6386 : : * @param[in] mask
6387 : : * Pointer to the indirect action mask.
6388 : : * @param[in, out] action_flags
6389 : : * Holds the actions detected until now.
6390 : : * @param[in, out] fixed_cnt
6391 : : * Pointer to indicator if this list has a fixed COUNT action.
6392 : : * @param[out] error
6393 : : * Pointer to error structure.
6394 : : *
6395 : : * @return
6396 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
6397 : : */
6398 : : static int
6399 : 0 : flow_hw_validate_action_indirect(struct rte_eth_dev *dev,
6400 : : const struct rte_flow_action *action,
6401 : : const struct rte_flow_action *mask,
6402 : : uint64_t *action_flags, bool *fixed_cnt,
6403 : : struct rte_flow_error *error)
6404 : : {
6405 : : uint32_t type;
6406 : : int ret;
6407 : :
6408 [ # # ]: 0 : if (!mask)
6409 : 0 : return rte_flow_error_set(error, EINVAL,
6410 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6411 : : "Unable to determine indirect action type without a mask specified");
6412 : 0 : type = mask->type;
6413 [ # # # # : 0 : switch (type) {
# # # ]
6414 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
6415 : 0 : ret = flow_hw_validate_action_meter_mark(dev, mask, true, error);
6416 [ # # ]: 0 : if (ret < 0)
6417 : : return ret;
6418 : 0 : *action_flags |= MLX5_FLOW_ACTION_METER;
6419 : 0 : break;
6420 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
6421 : : /* TODO: Validation logic (same as flow_hw_actions_validate) */
6422 : 0 : *action_flags |= MLX5_FLOW_ACTION_RSS;
6423 : 0 : break;
6424 : 0 : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
6425 : : /* TODO: Validation logic (same as flow_hw_actions_validate) */
6426 : 0 : *action_flags |= MLX5_FLOW_ACTION_CT;
6427 : 0 : break;
6428 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
6429 [ # # # # ]: 0 : if (action->conf && mask->conf) {
6430 [ # # ]: 0 : if ((*action_flags & MLX5_FLOW_ACTION_AGE) ||
6431 : : (*action_flags & MLX5_FLOW_ACTION_INDIRECT_AGE))
6432 : : /*
6433 : : * AGE cannot use indirect counter which is
6434 : : * shared with enother flow rules.
6435 : : */
6436 : 0 : return rte_flow_error_set(error, EINVAL,
6437 : : RTE_FLOW_ERROR_TYPE_ACTION,
6438 : : NULL,
6439 : : "AGE and fixed COUNT combination is not supported");
6440 : 0 : *fixed_cnt = true;
6441 : : }
6442 : 0 : ret = flow_hw_validate_action_count(dev, action, mask,
6443 : : *action_flags, error);
6444 [ # # ]: 0 : if (ret < 0)
6445 : : return ret;
6446 : 0 : *action_flags |= MLX5_FLOW_ACTION_INDIRECT_COUNT;
6447 : 0 : break;
6448 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
6449 : 0 : ret = flow_hw_validate_action_age(dev, action, *action_flags,
6450 : 0 : *fixed_cnt, error);
6451 [ # # ]: 0 : if (ret < 0)
6452 : : return ret;
6453 : 0 : *action_flags |= MLX5_FLOW_ACTION_INDIRECT_AGE;
6454 : 0 : break;
6455 : 0 : case RTE_FLOW_ACTION_TYPE_QUOTA:
6456 : : /* TODO: add proper quota verification */
6457 : 0 : *action_flags |= MLX5_FLOW_ACTION_QUOTA;
6458 : 0 : break;
6459 : 0 : default:
6460 : 0 : DRV_LOG(WARNING, "Unsupported shared action type: %d", type);
6461 : 0 : return rte_flow_error_set(error, ENOTSUP,
6462 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, mask,
6463 : : "Unsupported indirect action type");
6464 : : }
6465 : : return 0;
6466 : : }
6467 : :
6468 : : /**
6469 : : * Validate ipv6_ext_push action.
6470 : : *
6471 : : * @param[in] dev
6472 : : * Pointer to rte_eth_dev structure.
6473 : : * @param[in] action
6474 : : * Pointer to the indirect action.
6475 : : * @param[out] error
6476 : : * Pointer to error structure.
6477 : : *
6478 : : * @return
6479 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
6480 : : */
6481 : : static int
6482 : 0 : flow_hw_validate_action_ipv6_ext_push(struct rte_eth_dev *dev __rte_unused,
6483 : : const struct rte_flow_action *action,
6484 : : struct rte_flow_error *error)
6485 : : {
6486 : 0 : const struct rte_flow_action_ipv6_ext_push *raw_push_data = action->conf;
6487 : :
6488 [ # # # # : 0 : if (!raw_push_data || !raw_push_data->size || !raw_push_data->data)
# # ]
6489 : 0 : return rte_flow_error_set(error, EINVAL,
6490 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6491 : : "invalid ipv6_ext_push data");
6492 [ # # # # ]: 0 : if (raw_push_data->type != IPPROTO_ROUTING ||
6493 : : raw_push_data->size > MLX5_PUSH_MAX_LEN)
6494 : 0 : return rte_flow_error_set(error, EINVAL,
6495 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6496 : : "Unsupported ipv6_ext_push type or length");
6497 : : return 0;
6498 : : }
6499 : :
6500 : : /**
6501 : : * Process `... / raw_decap / raw_encap / ...` actions sequence.
6502 : : * The PMD handles the sequence as a single encap or decap reformat action,
6503 : : * depending on the raw_encap configuration.
6504 : : *
6505 : : * The function assumes that the raw_decap / raw_encap location
6506 : : * in actions template list complies with relative HWS actions order:
6507 : : * for the required reformat configuration:
6508 : : * ENCAP configuration must appear before [JUMP|DROP|PORT]
6509 : : * DECAP configuration must appear at the template head.
6510 : : */
6511 : : static uint64_t
6512 : : mlx5_decap_encap_reformat_type(const struct rte_flow_action *actions,
6513 : : uint32_t encap_ind, uint64_t flags)
6514 : : {
6515 : 0 : const struct rte_flow_action_raw_encap *encap = actions[encap_ind].conf;
6516 : :
6517 [ # # ]: 0 : if ((flags & MLX5_FLOW_ACTION_DECAP) == 0)
6518 : : return MLX5_FLOW_ACTION_ENCAP;
6519 [ # # ]: 0 : if (actions[encap_ind - 1].type != RTE_FLOW_ACTION_TYPE_RAW_DECAP)
6520 : : return MLX5_FLOW_ACTION_ENCAP;
6521 : 0 : return encap->size >= MLX5_ENCAPSULATION_DECISION_SIZE ?
6522 [ # # ]: 0 : MLX5_FLOW_ACTION_ENCAP : MLX5_FLOW_ACTION_DECAP;
6523 : : }
6524 : :
6525 : : enum mlx5_hw_indirect_list_relative_position {
6526 : : MLX5_INDIRECT_LIST_POSITION_UNKNOWN = -1,
6527 : : MLX5_INDIRECT_LIST_POSITION_BEFORE_MH = 0,
6528 : : MLX5_INDIRECT_LIST_POSITION_AFTER_MH,
6529 : : };
6530 : :
6531 : : static enum mlx5_hw_indirect_list_relative_position
6532 : 0 : mlx5_hw_indirect_list_mh_position(const struct rte_flow_action *action)
6533 : : {
6534 : 0 : const struct rte_flow_action_indirect_list *conf = action->conf;
6535 [ # # # # ]: 0 : enum mlx5_indirect_list_type list_type = mlx5_get_indirect_list_type(conf->handle);
6536 : : enum mlx5_hw_indirect_list_relative_position pos = MLX5_INDIRECT_LIST_POSITION_UNKNOWN;
6537 : : const union {
6538 : : struct mlx5_indlst_legacy *legacy;
6539 : : struct mlx5_hw_encap_decap_action *reformat;
6540 : : struct rte_flow_action_list_handle *handle;
6541 : : } h = { .handle = conf->handle};
6542 : :
6543 [ # # # # ]: 0 : switch (list_type) {
6544 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY:
6545 [ # # # ]: 0 : switch (h.legacy->legacy_type) {
6546 : : case RTE_FLOW_ACTION_TYPE_AGE:
6547 : : case RTE_FLOW_ACTION_TYPE_COUNT:
6548 : : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
6549 : : case RTE_FLOW_ACTION_TYPE_METER_MARK:
6550 : : case RTE_FLOW_ACTION_TYPE_QUOTA:
6551 : : pos = MLX5_INDIRECT_LIST_POSITION_BEFORE_MH;
6552 : : break;
6553 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
6554 : : pos = MLX5_INDIRECT_LIST_POSITION_AFTER_MH;
6555 : 0 : break;
6556 : 0 : default:
6557 : : pos = MLX5_INDIRECT_LIST_POSITION_UNKNOWN;
6558 : 0 : break;
6559 : : }
6560 : : break;
6561 : : case MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR:
6562 : : pos = MLX5_INDIRECT_LIST_POSITION_AFTER_MH;
6563 : : break;
6564 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT:
6565 [ # # # ]: 0 : switch (h.reformat->action_type) {
6566 : : case MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2:
6567 : : case MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2:
6568 : : pos = MLX5_INDIRECT_LIST_POSITION_BEFORE_MH;
6569 : : break;
6570 : 0 : case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2:
6571 : : case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3:
6572 : : pos = MLX5_INDIRECT_LIST_POSITION_AFTER_MH;
6573 : 0 : break;
6574 : 0 : default:
6575 : : pos = MLX5_INDIRECT_LIST_POSITION_UNKNOWN;
6576 : 0 : break;
6577 : : }
6578 : : break;
6579 : 0 : default:
6580 : : pos = MLX5_INDIRECT_LIST_POSITION_UNKNOWN;
6581 : 0 : break;
6582 : : }
6583 : 0 : return pos;
6584 : : }
6585 : :
6586 : : #define MLX5_HW_EXPAND_MH_FAILED 0xffff
6587 : :
6588 : : static inline uint16_t
6589 : 0 : flow_hw_template_expand_modify_field(struct rte_flow_action actions[],
6590 : : struct rte_flow_action masks[],
6591 : : const struct rte_flow_action *mf_actions,
6592 : : const struct rte_flow_action *mf_masks,
6593 : : uint64_t flags, uint32_t act_num,
6594 : : uint32_t mf_num)
6595 : : {
6596 : : uint32_t i, tail;
6597 : :
6598 : : MLX5_ASSERT(actions && masks);
6599 : : MLX5_ASSERT(mf_num > 0);
6600 [ # # ]: 0 : if (flags & MLX5_FLOW_ACTION_MODIFY_FIELD) {
6601 : : /*
6602 : : * Application action template already has Modify Field.
6603 : : * It's location will be used in DR.
6604 : : * Expanded MF action can be added before the END.
6605 : : */
6606 : 0 : i = act_num - 1;
6607 : 0 : goto insert;
6608 : : }
6609 : : /**
6610 : : * Locate the first action positioned BEFORE the new MF.
6611 : : *
6612 : : * Search for a place to insert modify header
6613 : : * from the END action backwards:
6614 : : * 1. END is always present in actions array
6615 : : * 2. END location is always at action[act_num - 1]
6616 : : * 3. END always positioned AFTER modify field location
6617 : : *
6618 : : * Relative actions order is the same for RX, TX and FDB.
6619 : : *
6620 : : * Current actions order (draft-3)
6621 : : * @see action_order_arr[]
6622 : : */
6623 [ # # ]: 0 : for (i = act_num - 2; (int)i >= 0; i--) {
6624 : : enum mlx5_hw_indirect_list_relative_position pos;
6625 : 0 : enum rte_flow_action_type type = actions[i].type;
6626 : : uint64_t reformat_type;
6627 : :
6628 [ # # ]: 0 : if (type == RTE_FLOW_ACTION_TYPE_INDIRECT)
6629 : 0 : type = masks[i].type;
6630 [ # # # # ]: 0 : switch (type) {
6631 : : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
6632 : : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
6633 : : case RTE_FLOW_ACTION_TYPE_DROP:
6634 : : case RTE_FLOW_ACTION_TYPE_SEND_TO_KERNEL:
6635 : : case RTE_FLOW_ACTION_TYPE_JUMP:
6636 : : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
6637 : : case RTE_FLOW_ACTION_TYPE_QUEUE:
6638 : : case RTE_FLOW_ACTION_TYPE_RSS:
6639 : : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
6640 : : case RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:
6641 : : case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
6642 : : case RTE_FLOW_ACTION_TYPE_VOID:
6643 : : case RTE_FLOW_ACTION_TYPE_END:
6644 : : break;
6645 : : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
6646 : : reformat_type =
6647 : : mlx5_decap_encap_reformat_type(actions, i,
6648 : : flags);
6649 : : if (reformat_type == MLX5_FLOW_ACTION_DECAP) {
6650 : 0 : i++;
6651 : 0 : goto insert;
6652 : : }
6653 [ # # ]: 0 : if (actions[i - 1].type == RTE_FLOW_ACTION_TYPE_RAW_DECAP)
6654 : : i--;
6655 : : break;
6656 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT_LIST:
6657 : 0 : pos = mlx5_hw_indirect_list_mh_position(&actions[i]);
6658 [ # # ]: 0 : if (pos == MLX5_INDIRECT_LIST_POSITION_UNKNOWN)
6659 : : return MLX5_HW_EXPAND_MH_FAILED;
6660 [ # # ]: 0 : if (pos == MLX5_INDIRECT_LIST_POSITION_BEFORE_MH)
6661 : 0 : goto insert;
6662 : : break;
6663 : 0 : default:
6664 : 0 : i++; /* new MF inserted AFTER actions[i] */
6665 : 0 : goto insert;
6666 : : }
6667 : : }
6668 : : i = 0;
6669 : 0 : insert:
6670 : 0 : tail = act_num - i; /* num action to move */
6671 : 0 : memmove(actions + i + mf_num, actions + i, sizeof(actions[0]) * tail);
6672 : 0 : memcpy(actions + i, mf_actions, sizeof(actions[0]) * mf_num);
6673 : 0 : memmove(masks + i + mf_num, masks + i, sizeof(masks[0]) * tail);
6674 : : memcpy(masks + i, mf_masks, sizeof(masks[0]) * mf_num);
6675 : 0 : return i;
6676 : : }
6677 : :
6678 : : static int
6679 : 0 : flow_hw_validate_action_push_vlan(struct rte_eth_dev *dev,
6680 : : const
6681 : : struct rte_flow_actions_template_attr *attr,
6682 : : const struct rte_flow_action *action,
6683 : : const struct rte_flow_action *mask,
6684 : : struct rte_flow_error *error)
6685 : : {
6686 : : #define X_FIELD(ptr, t, f) (((ptr)->conf) && ((t *)((ptr)->conf))->f)
6687 : :
6688 : 0 : const bool masked_push =
6689 [ # # # # ]: 0 : X_FIELD(mask + MLX5_HW_VLAN_PUSH_TYPE_IDX,
6690 : : const struct rte_flow_action_of_push_vlan, ethertype);
6691 : : bool masked_param;
6692 : :
6693 : : /*
6694 : : * Mandatory actions order:
6695 : : * OF_PUSH_VLAN / OF_SET_VLAN_VID [ / OF_SET_VLAN_PCP ]
6696 : : */
6697 : : RTE_SET_USED(dev);
6698 : : RTE_SET_USED(attr);
6699 : : /* Check that mark matches OF_PUSH_VLAN */
6700 [ # # ]: 0 : if (mask[MLX5_HW_VLAN_PUSH_TYPE_IDX].type !=
6701 : : RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN)
6702 : 0 : return rte_flow_error_set(error, EINVAL,
6703 : : RTE_FLOW_ERROR_TYPE_ACTION,
6704 : : action, "OF_PUSH_VLAN: mask does not match");
6705 : : /* Check that the second template and mask items are SET_VLAN_VID */
6706 [ # # ]: 0 : if (action[MLX5_HW_VLAN_PUSH_VID_IDX].type !=
6707 : 0 : RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID ||
6708 [ # # ]: 0 : mask[MLX5_HW_VLAN_PUSH_VID_IDX].type !=
6709 : : RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)
6710 : 0 : return rte_flow_error_set(error, EINVAL,
6711 : : RTE_FLOW_ERROR_TYPE_ACTION,
6712 : : action, "OF_PUSH_VLAN: invalid actions order");
6713 [ # # # # ]: 0 : masked_param = X_FIELD(mask + MLX5_HW_VLAN_PUSH_VID_IDX,
6714 : : const struct rte_flow_action_of_set_vlan_vid,
6715 : : vlan_vid);
6716 : : /*
6717 : : * PMD requires OF_SET_VLAN_VID mask to must match OF_PUSH_VLAN
6718 : : */
6719 [ # # ]: 0 : if (masked_push ^ masked_param)
6720 : 0 : return rte_flow_error_set(error, EINVAL,
6721 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6722 : : "OF_SET_VLAN_VID: mask does not match OF_PUSH_VLAN");
6723 [ # # ]: 0 : if (is_of_vlan_pcp_present(action)) {
6724 [ # # ]: 0 : if (mask[MLX5_HW_VLAN_PUSH_PCP_IDX].type !=
6725 : : RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)
6726 : 0 : return rte_flow_error_set(error, EINVAL,
6727 : : RTE_FLOW_ERROR_TYPE_ACTION,
6728 : : action, "OF_SET_VLAN_PCP: missing mask configuration");
6729 [ # # # # ]: 0 : masked_param = X_FIELD(mask + MLX5_HW_VLAN_PUSH_PCP_IDX,
6730 : : const struct
6731 : : rte_flow_action_of_set_vlan_pcp,
6732 : : vlan_pcp);
6733 : : /*
6734 : : * PMD requires OF_SET_VLAN_PCP mask to must match OF_PUSH_VLAN
6735 : : */
6736 [ # # ]: 0 : if (masked_push ^ masked_param)
6737 : 0 : return rte_flow_error_set(error, EINVAL,
6738 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6739 : : "OF_SET_VLAN_PCP: mask does not match OF_PUSH_VLAN");
6740 : : }
6741 : : return 0;
6742 : : #undef X_FIELD
6743 : : }
6744 : :
6745 : : static int
6746 : 0 : flow_hw_validate_action_default_miss(struct rte_eth_dev *dev,
6747 : : const struct rte_flow_actions_template_attr *attr,
6748 : : uint64_t action_flags,
6749 : : struct rte_flow_error *error)
6750 : : {
6751 : : /*
6752 : : * The private DEFAULT_MISS action is used internally for LACP in control
6753 : : * flows. So this validation can be ignored. It can be kept right now since
6754 : : * the validation will be done only once.
6755 : : */
6756 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6757 : :
6758 [ # # ]: 0 : if (!attr->ingress || attr->egress || attr->transfer)
6759 : 0 : return rte_flow_error_set(error, EINVAL,
6760 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6761 : : "DEFAULT MISS is only supported in ingress.");
6762 [ # # ]: 0 : if (!priv->hw_def_miss)
6763 : 0 : return rte_flow_error_set(error, EINVAL,
6764 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6765 : : "DEFAULT MISS action does not exist.");
6766 [ # # ]: 0 : if (action_flags & MLX5_FLOW_FATE_ACTIONS)
6767 : 0 : return rte_flow_error_set(error, EINVAL,
6768 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6769 : : "DEFAULT MISS should be the only termination.");
6770 : : return 0;
6771 : : }
6772 : :
6773 : : static int
6774 : 0 : flow_hw_validate_action_nat64(struct rte_eth_dev *dev,
6775 : : const struct rte_flow_actions_template_attr *attr,
6776 : : const struct rte_flow_action *action,
6777 : : const struct rte_flow_action *mask,
6778 : : uint64_t action_flags,
6779 : : struct rte_flow_error *error)
6780 : : {
6781 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
6782 : : const struct rte_flow_action_nat64 *nat64_c;
6783 : : enum rte_flow_nat64_type cov_type;
6784 : :
6785 : : RTE_SET_USED(action_flags);
6786 [ # # # # ]: 0 : if (mask->conf && ((const struct rte_flow_action_nat64 *)mask->conf)->type) {
6787 : 0 : nat64_c = (const struct rte_flow_action_nat64 *)action->conf;
6788 : 0 : cov_type = nat64_c->type;
6789 [ # # # # ]: 0 : if ((attr->ingress && !priv->action_nat64[MLX5DR_TABLE_TYPE_NIC_RX][cov_type]) ||
6790 [ # # # # ]: 0 : (attr->egress && !priv->action_nat64[MLX5DR_TABLE_TYPE_NIC_TX][cov_type]) ||
6791 [ # # # # ]: 0 : (attr->transfer && !priv->action_nat64[MLX5DR_TABLE_TYPE_FDB][cov_type]))
6792 : 0 : goto err_out;
6793 : : } else {
6794 : : /*
6795 : : * Usually, the actions will be used on both directions. For non-masked actions,
6796 : : * both directions' actions will be checked.
6797 : : */
6798 [ # # ]: 0 : if (attr->ingress)
6799 [ # # ]: 0 : if (!priv->action_nat64[MLX5DR_TABLE_TYPE_NIC_RX][RTE_FLOW_NAT64_6TO4] ||
6800 [ # # ]: 0 : !priv->action_nat64[MLX5DR_TABLE_TYPE_NIC_RX][RTE_FLOW_NAT64_4TO6])
6801 : 0 : goto err_out;
6802 [ # # ]: 0 : if (attr->egress)
6803 [ # # ]: 0 : if (!priv->action_nat64[MLX5DR_TABLE_TYPE_NIC_TX][RTE_FLOW_NAT64_6TO4] ||
6804 [ # # ]: 0 : !priv->action_nat64[MLX5DR_TABLE_TYPE_NIC_TX][RTE_FLOW_NAT64_4TO6])
6805 : 0 : goto err_out;
6806 [ # # ]: 0 : if (attr->transfer)
6807 [ # # ]: 0 : if (!priv->action_nat64[MLX5DR_TABLE_TYPE_FDB][RTE_FLOW_NAT64_6TO4] ||
6808 [ # # ]: 0 : !priv->action_nat64[MLX5DR_TABLE_TYPE_FDB][RTE_FLOW_NAT64_4TO6])
6809 : 0 : goto err_out;
6810 : : }
6811 : : return 0;
6812 : 0 : err_out:
6813 : 0 : return rte_flow_error_set(error, EOPNOTSUPP, RTE_FLOW_ERROR_TYPE_ACTION,
6814 : : NULL, "NAT64 action is not supported.");
6815 : : }
6816 : :
6817 : : static int
6818 : 0 : flow_hw_validate_action_jump(struct rte_eth_dev *dev,
6819 : : const struct rte_flow_actions_template_attr *attr,
6820 : : const struct rte_flow_action *action,
6821 : : const struct rte_flow_action *mask,
6822 : : struct rte_flow_error *error)
6823 : : {
6824 : 0 : const struct rte_flow_action_jump *m = mask->conf;
6825 : 0 : const struct rte_flow_action_jump *v = action->conf;
6826 : 0 : struct mlx5_flow_template_table_cfg cfg = {
6827 : : .external = true,
6828 : : .attr = {
6829 : : .flow_attr = {
6830 : 0 : .ingress = attr->ingress,
6831 : 0 : .egress = attr->egress,
6832 : 0 : .transfer = attr->transfer,
6833 : : },
6834 : : },
6835 : : };
6836 : 0 : uint32_t t_group = 0;
6837 : :
6838 [ # # # # ]: 0 : if (!m || !m->group)
6839 : : return 0;
6840 [ # # ]: 0 : if (!v)
6841 : 0 : return rte_flow_error_set(error, EINVAL,
6842 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6843 : : "Invalid jump action configuration");
6844 [ # # ]: 0 : if (flow_hw_translate_group(dev, &cfg, v->group, &t_group, error))
6845 : 0 : return -rte_errno;
6846 [ # # ]: 0 : if (t_group == 0)
6847 : 0 : return rte_flow_error_set(error, EINVAL,
6848 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6849 : : "Unsupported action - jump to root table");
6850 : : return 0;
6851 : : }
6852 : :
6853 : : static int
6854 : 0 : mlx5_flow_validate_action_jump_to_table_index(const struct rte_flow_action *action,
6855 : : const struct rte_flow_action *mask,
6856 : : struct rte_flow_error *error)
6857 : : {
6858 : 0 : const struct rte_flow_action_jump_to_table_index *m = mask->conf;
6859 : 0 : const struct rte_flow_action_jump_to_table_index *v = action->conf;
6860 : : struct mlx5dr_action *jump_action;
6861 : : uint32_t t_group = 0;
6862 : :
6863 [ # # # # ]: 0 : if (!m || !m->table)
6864 : : return 0;
6865 [ # # ]: 0 : if (!v)
6866 : 0 : return rte_flow_error_set(error, EINVAL,
6867 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6868 : : "Invalid jump to matcher action configuration");
6869 : 0 : t_group = v->table->grp->group_id;
6870 [ # # ]: 0 : if (t_group == 0)
6871 : 0 : return rte_flow_error_set(error, EINVAL,
6872 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6873 : : "Unsupported action - jump to root table");
6874 [ # # ]: 0 : if (likely(!rte_flow_template_table_resizable(0, &v->table->cfg.attr))) {
6875 : 0 : jump_action = v->table->matcher_info[0].jump;
6876 : : } else {
6877 : : uint32_t selector;
6878 : 0 : rte_rwlock_read_lock(&v->table->matcher_replace_rwlk);
6879 : 0 : selector = v->table->matcher_selector;
6880 : 0 : jump_action = v->table->matcher_info[selector].jump;
6881 : : rte_rwlock_read_unlock(&v->table->matcher_replace_rwlk);
6882 : : }
6883 [ # # ]: 0 : if (jump_action == NULL)
6884 : 0 : return rte_flow_error_set(error, EINVAL,
6885 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
6886 : : "Unsupported action - table is not an rule array");
6887 : : return 0;
6888 : : }
6889 : :
6890 : : static int
6891 : 0 : mlx5_hw_validate_action_mark(struct rte_eth_dev *dev,
6892 : : const struct rte_flow_action *template_action,
6893 : : const struct rte_flow_action *template_mask,
6894 : : uint64_t action_flags,
6895 : : const struct rte_flow_actions_template_attr *template_attr,
6896 : : struct rte_flow_error *error)
6897 : : {
6898 : 0 : const struct rte_flow_action_mark *mark_mask = template_mask->conf;
6899 : : const struct rte_flow_action *action =
6900 [ # # # # ]: 0 : mark_mask && mark_mask->id ? template_action :
6901 : 0 : &(const struct rte_flow_action) {
6902 : : .type = RTE_FLOW_ACTION_TYPE_MARK,
6903 : 0 : .conf = &(const struct rte_flow_action_mark) {
6904 : : .id = MLX5_FLOW_MARK_MAX - 1
6905 : : }
6906 : : };
6907 : 0 : const struct rte_flow_attr attr = {
6908 : 0 : .ingress = template_attr->ingress,
6909 : 0 : .egress = template_attr->egress,
6910 : 0 : .transfer = template_attr->transfer
6911 : : };
6912 : :
6913 : 0 : return mlx5_flow_validate_action_mark(dev, action, action_flags,
6914 : : &attr, error);
6915 : : }
6916 : :
6917 : : static int
6918 : 0 : mlx5_hw_validate_action_queue(struct rte_eth_dev *dev,
6919 : : const struct rte_flow_action *template_action,
6920 : : const struct rte_flow_action *template_mask,
6921 : : const struct rte_flow_actions_template_attr *template_attr,
6922 : : uint64_t action_flags,
6923 : : struct rte_flow_error *error)
6924 : : {
6925 : 0 : const struct rte_flow_action_queue *queue_mask = template_mask->conf;
6926 : 0 : const struct rte_flow_attr attr = {
6927 : 0 : .ingress = template_attr->ingress,
6928 : 0 : .egress = template_attr->egress,
6929 : 0 : .transfer = template_attr->transfer
6930 : : };
6931 [ # # # # ]: 0 : bool masked = queue_mask != NULL && queue_mask->index;
6932 : :
6933 [ # # ]: 0 : if (template_attr->egress || template_attr->transfer)
6934 : 0 : return rte_flow_error_set(error, EINVAL,
6935 : : RTE_FLOW_ERROR_TYPE_ATTR, NULL,
6936 : : "QUEUE action supported for ingress only");
6937 [ # # ]: 0 : if (masked)
6938 : 0 : return mlx5_flow_validate_action_queue(template_action, action_flags, dev,
6939 : : &attr, error);
6940 : : else
6941 : : return 0;
6942 : : }
6943 : :
6944 : : static int
6945 : 0 : mlx5_hw_validate_action_rss(struct rte_eth_dev *dev,
6946 : : const struct rte_flow_action *template_action,
6947 : : const struct rte_flow_action *template_mask,
6948 : : const struct rte_flow_actions_template_attr *template_attr,
6949 : : __rte_unused uint64_t action_flags,
6950 : : struct rte_flow_error *error)
6951 : : {
6952 : 0 : const struct rte_flow_action_rss *mask = template_mask->conf;
6953 : :
6954 [ # # ]: 0 : if (template_attr->egress || template_attr->transfer)
6955 : 0 : return rte_flow_error_set(error, EINVAL,
6956 : : RTE_FLOW_ERROR_TYPE_ATTR, NULL,
6957 : : "RSS action supported for ingress only");
6958 [ # # ]: 0 : if (mask != NULL)
6959 : 0 : return mlx5_validate_action_rss(dev, template_action, error);
6960 : : else
6961 : : return 0;
6962 : : }
6963 : :
6964 : : static int
6965 : 0 : mlx5_hw_validate_action_l2_encap(struct rte_eth_dev *dev,
6966 : : const struct rte_flow_action *template_action,
6967 : : const struct rte_flow_action *template_mask,
6968 : : const struct rte_flow_actions_template_attr *template_attr,
6969 : : uint64_t action_flags,
6970 : : struct rte_flow_error *error)
6971 : : {
6972 : 0 : const struct rte_flow_action_vxlan_encap default_action_conf = {
6973 : : .definition = (struct rte_flow_item *)
6974 : 0 : (struct rte_flow_item [1]) {
6975 : : [0] = { .type = RTE_FLOW_ITEM_TYPE_END }
6976 : : }
6977 : : };
6978 : 0 : const struct rte_flow_action *action = template_mask->conf ?
6979 [ # # ]: 0 : template_action : &(const struct rte_flow_action) {
6980 : 0 : .type = template_mask->type,
6981 : : .conf = &default_action_conf
6982 : : };
6983 : 0 : const struct rte_flow_attr attr = {
6984 : 0 : .ingress = template_attr->ingress,
6985 : 0 : .egress = template_attr->egress,
6986 : 0 : .transfer = template_attr->transfer
6987 : : };
6988 : :
6989 : 0 : return mlx5_flow_dv_validate_action_l2_encap(dev, action_flags, action,
6990 : : &attr, error);
6991 : : }
6992 : :
6993 : : static int
6994 : 0 : mlx5_hw_validate_action_l2_decap(struct rte_eth_dev *dev,
6995 : : const struct rte_flow_action *template_action,
6996 : : const struct rte_flow_action *template_mask,
6997 : : const struct rte_flow_actions_template_attr *template_attr,
6998 : : uint64_t action_flags,
6999 : : struct rte_flow_error *error)
7000 : : {
7001 : 0 : const struct rte_flow_action_vxlan_encap default_action_conf = {
7002 : : .definition = (struct rte_flow_item *)
7003 : 0 : (struct rte_flow_item [1]) {
7004 : : [0] = { .type = RTE_FLOW_ITEM_TYPE_END }
7005 : : }
7006 : : };
7007 : 0 : const struct rte_flow_action *action = template_mask->conf ?
7008 [ # # ]: 0 : template_action : &(const struct rte_flow_action) {
7009 : 0 : .type = template_mask->type,
7010 : : .conf = &default_action_conf
7011 : : };
7012 : 0 : const struct rte_flow_attr attr = {
7013 : 0 : .ingress = template_attr->ingress,
7014 : 0 : .egress = template_attr->egress,
7015 : 0 : .transfer = template_attr->transfer
7016 : : };
7017 : : uint64_t item_flags =
7018 : 0 : action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
7019 [ # # ]: 0 : MLX5_FLOW_LAYER_VXLAN : 0;
7020 : :
7021 : 0 : return mlx5_flow_dv_validate_action_decap(dev, action_flags, action,
7022 : : item_flags, &attr, error);
7023 : : }
7024 : :
7025 : : static int
7026 : : mlx5_hw_validate_action_conntrack(struct rte_eth_dev *dev,
7027 : : const struct rte_flow_action *template_action,
7028 : : const struct rte_flow_action *template_mask,
7029 : : const struct rte_flow_actions_template_attr *template_attr,
7030 : : uint64_t action_flags,
7031 : : struct rte_flow_error *error)
7032 : : {
7033 : : RTE_SET_USED(template_action);
7034 : : RTE_SET_USED(template_mask);
7035 : : RTE_SET_USED(template_attr);
7036 : 0 : return mlx5_flow_dv_validate_action_aso_ct(dev, action_flags,
7037 : : MLX5_FLOW_LAYER_OUTER_L4_TCP,
7038 : : false, error);
7039 : : }
7040 : :
7041 : : static int
7042 : 0 : flow_hw_validate_action_raw_encap(const struct rte_flow_action *action,
7043 : : const struct rte_flow_action *mask,
7044 : : struct rte_flow_error *error)
7045 : : {
7046 : 0 : const struct rte_flow_action_raw_encap *mask_conf = mask->conf;
7047 : 0 : const struct rte_flow_action_raw_encap *action_conf = action->conf;
7048 : :
7049 [ # # # # ]: 0 : if (!mask_conf || !mask_conf->size)
7050 : 0 : return rte_flow_error_set(error, EINVAL,
7051 : : RTE_FLOW_ERROR_TYPE_ACTION, mask,
7052 : : "raw_encap: size must be masked");
7053 [ # # # # ]: 0 : if (!action_conf || !action_conf->size)
7054 : 0 : return rte_flow_error_set(error, EINVAL,
7055 : : RTE_FLOW_ERROR_TYPE_ACTION, action,
7056 : : "raw_encap: invalid action configuration");
7057 [ # # # # ]: 0 : if (mask_conf->data && !action_conf->data)
7058 : 0 : return rte_flow_error_set(error, EINVAL,
7059 : : RTE_FLOW_ERROR_TYPE_ACTION,
7060 : : action, "raw_encap: masked data is missing");
7061 : : return 0;
7062 : : }
7063 : :
7064 : :
7065 : : static int
7066 : 0 : flow_hw_validate_action_raw_reformat(struct rte_eth_dev *dev,
7067 : : const struct rte_flow_action *template_action,
7068 : : const struct rte_flow_action *template_mask,
7069 : : const struct
7070 : : rte_flow_actions_template_attr *template_attr,
7071 : : uint64_t *action_flags,
7072 : : struct rte_flow_error *error)
7073 : : {
7074 : : const struct rte_flow_action *encap_action = NULL;
7075 : : const struct rte_flow_action *encap_mask = NULL;
7076 : : const struct rte_flow_action_raw_decap *raw_decap = NULL;
7077 : : const struct rte_flow_action_raw_encap *raw_encap = NULL;
7078 : 0 : const struct rte_flow_attr attr = {
7079 : 0 : .ingress = template_attr->ingress,
7080 : 0 : .egress = template_attr->egress,
7081 : 0 : .transfer = template_attr->transfer
7082 : : };
7083 : : uint64_t item_flags = 0;
7084 : 0 : int ret, actions_n = 0;
7085 : :
7086 [ # # ]: 0 : if (template_action->type == RTE_FLOW_ACTION_TYPE_RAW_DECAP) {
7087 : 0 : raw_decap = template_mask->conf ?
7088 [ # # ]: 0 : template_action->conf : &empty_decap;
7089 [ # # ]: 0 : if ((template_action + 1)->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7090 [ # # ]: 0 : if ((template_mask + 1)->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP)
7091 : 0 : return rte_flow_error_set(error, EINVAL,
7092 : : RTE_FLOW_ERROR_TYPE_ACTION,
7093 : 0 : template_mask + 1, "invalid mask type");
7094 : 0 : encap_action = template_action + 1;
7095 : 0 : encap_mask = template_mask + 1;
7096 : : }
7097 : : } else {
7098 : : encap_action = template_action;
7099 : : encap_mask = template_mask;
7100 : : }
7101 [ # # ]: 0 : if (encap_action) {
7102 : 0 : raw_encap = encap_action->conf;
7103 : 0 : ret = flow_hw_validate_action_raw_encap(encap_action,
7104 : : encap_mask, error);
7105 [ # # ]: 0 : if (ret)
7106 : : return ret;
7107 : : }
7108 : 0 : return mlx5_flow_dv_validate_action_raw_encap_decap(dev, raw_decap,
7109 : : raw_encap, &attr,
7110 : : action_flags,
7111 : : &actions_n,
7112 : : template_action,
7113 : : item_flags, error);
7114 : : }
7115 : :
7116 : :
7117 : :
7118 : : static int
7119 : 0 : mlx5_flow_hw_actions_validate(struct rte_eth_dev *dev,
7120 : : const struct rte_flow_actions_template_attr *attr,
7121 : : const struct rte_flow_action actions[],
7122 : : const struct rte_flow_action masks[],
7123 : : uint64_t *act_flags,
7124 : : struct rte_flow_error *error)
7125 : : {
7126 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
7127 : : const struct rte_flow_action_count *count_mask = NULL;
7128 : 0 : bool fixed_cnt = false;
7129 : 0 : uint64_t action_flags = 0;
7130 : : bool actions_end = false;
7131 : : #ifdef HAVE_MLX5DV_DR_ACTION_CREATE_DEST_ROOT_TABLE
7132 : : int table_type;
7133 : : #endif
7134 : : uint16_t i;
7135 : : int ret;
7136 : : const struct rte_flow_action_ipv6_ext_remove *remove_data;
7137 : :
7138 [ # # ]: 0 : if (!mlx5_hw_ctx_validate(dev, error))
7139 : 0 : return -rte_errno;
7140 : : /* FDB actions are only valid to proxy port. */
7141 [ # # # # : 0 : if (attr->transfer && (!priv->sh->config.dv_esw_en || !priv->master))
# # ]
7142 : 0 : return rte_flow_error_set(error, EINVAL,
7143 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7144 : : NULL,
7145 : : "transfer actions are only valid to proxy port");
7146 [ # # ]: 0 : for (i = 0; !actions_end; ++i) {
7147 : 0 : const struct rte_flow_action *action = &actions[i];
7148 : 0 : const struct rte_flow_action *mask = &masks[i];
7149 : :
7150 : : MLX5_ASSERT(i < MLX5_HW_MAX_ACTS);
7151 [ # # ]: 0 : if (action->type != RTE_FLOW_ACTION_TYPE_INDIRECT &&
7152 [ # # ]: 0 : action->type != mask->type)
7153 : 0 : return rte_flow_error_set(error, ENOTSUP,
7154 : : RTE_FLOW_ERROR_TYPE_ACTION,
7155 : : action,
7156 : : "mask type does not match action type");
7157 [ # # # # : 0 : switch ((int)action->type) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # #
# ]
7158 : : case RTE_FLOW_ACTION_TYPE_VOID:
7159 : 0 : break;
7160 : : case RTE_FLOW_ACTION_TYPE_INDIRECT_LIST:
7161 : : break;
7162 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT:
7163 : 0 : ret = flow_hw_validate_action_indirect(dev, action,
7164 : : mask,
7165 : : &action_flags,
7166 : : &fixed_cnt,
7167 : : error);
7168 [ # # ]: 0 : if (ret < 0)
7169 : 0 : return ret;
7170 : : break;
7171 : 0 : case RTE_FLOW_ACTION_TYPE_FLAG:
7172 : : /* TODO: Validation logic */
7173 : 0 : action_flags |= MLX5_FLOW_ACTION_FLAG;
7174 : 0 : break;
7175 : 0 : case RTE_FLOW_ACTION_TYPE_MARK:
7176 : 0 : ret = mlx5_hw_validate_action_mark(dev, action, mask,
7177 : : action_flags,
7178 : : attr, error);
7179 [ # # ]: 0 : if (ret)
7180 : 0 : return ret;
7181 : 0 : action_flags |= MLX5_FLOW_ACTION_MARK;
7182 : 0 : break;
7183 : 0 : case RTE_FLOW_ACTION_TYPE_DROP:
7184 : 0 : ret = mlx5_flow_validate_action_drop
7185 : : (dev, action_flags,
7186 : 0 : &(struct rte_flow_attr){.egress = attr->egress},
7187 : : error);
7188 [ # # ]: 0 : if (ret)
7189 : 0 : return ret;
7190 : 0 : action_flags |= MLX5_FLOW_ACTION_DROP;
7191 : 0 : break;
7192 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP:
7193 : : /* Only validate the jump to root table in template stage. */
7194 : 0 : ret = flow_hw_validate_action_jump(dev, attr, action, mask, error);
7195 [ # # ]: 0 : if (ret)
7196 : 0 : return ret;
7197 : 0 : action_flags |= MLX5_FLOW_ACTION_JUMP;
7198 : 0 : break;
7199 : : #ifdef HAVE_MLX5DV_DR_ACTION_CREATE_DEST_ROOT_TABLE
7200 : : case RTE_FLOW_ACTION_TYPE_SEND_TO_KERNEL:
7201 : : if (priv->shared_host)
7202 : : return rte_flow_error_set(error, ENOTSUP,
7203 : : RTE_FLOW_ERROR_TYPE_ACTION,
7204 : : action,
7205 : : "action not supported in guest port");
7206 : : table_type = attr->ingress ? MLX5DR_TABLE_TYPE_NIC_RX :
7207 : : ((attr->egress) ? MLX5DR_TABLE_TYPE_NIC_TX :
7208 : : MLX5DR_TABLE_TYPE_FDB);
7209 : : if (!priv->hw_send_to_kernel[table_type])
7210 : : return rte_flow_error_set(error, ENOTSUP,
7211 : : RTE_FLOW_ERROR_TYPE_ACTION,
7212 : : action,
7213 : : "action is not available");
7214 : : action_flags |= MLX5_FLOW_ACTION_SEND_TO_KERNEL;
7215 : : break;
7216 : : #endif
7217 : 0 : case RTE_FLOW_ACTION_TYPE_QUEUE:
7218 : 0 : ret = mlx5_hw_validate_action_queue(dev, action, mask,
7219 : : attr, action_flags,
7220 : : error);
7221 [ # # ]: 0 : if (ret)
7222 : 0 : return ret;
7223 : 0 : action_flags |= MLX5_FLOW_ACTION_QUEUE;
7224 : 0 : break;
7225 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
7226 : 0 : ret = mlx5_hw_validate_action_rss(dev, action, mask,
7227 : : attr, action_flags,
7228 : : error);
7229 [ # # ]: 0 : if (ret)
7230 : 0 : return ret;
7231 : 0 : action_flags |= MLX5_FLOW_ACTION_RSS;
7232 : 0 : break;
7233 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7234 : : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7235 : 0 : ret = mlx5_hw_validate_action_l2_encap(dev, action, mask,
7236 : : attr, action_flags,
7237 : : error);
7238 [ # # ]: 0 : if (ret)
7239 : 0 : return ret;
7240 : 0 : action_flags |= MLX5_FLOW_ACTION_ENCAP;
7241 : 0 : break;
7242 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7243 : : case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7244 : 0 : ret = mlx5_hw_validate_action_l2_decap(dev, action, mask,
7245 : : attr, action_flags,
7246 : : error);
7247 [ # # ]: 0 : if (ret)
7248 : 0 : return ret;
7249 : 0 : action_flags |= MLX5_FLOW_ACTION_DECAP;
7250 : 0 : break;
7251 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7252 : : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7253 : 0 : ret = flow_hw_validate_action_raw_reformat(dev, action,
7254 : : mask, attr,
7255 : : &action_flags,
7256 : : error);
7257 [ # # ]: 0 : if (ret)
7258 : 0 : return ret;
7259 [ # # ]: 0 : if (action->type == RTE_FLOW_ACTION_TYPE_RAW_DECAP &&
7260 [ # # ]: 0 : (action + 1)->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7261 : 0 : action_flags |= MLX5_FLOW_XCAP_ACTIONS;
7262 : 0 : i++;
7263 : : }
7264 : : break;
7265 : 0 : case RTE_FLOW_ACTION_TYPE_IPV6_EXT_PUSH:
7266 : 0 : ret = flow_hw_validate_action_ipv6_ext_push(dev, action, error);
7267 [ # # ]: 0 : if (ret < 0)
7268 : 0 : return ret;
7269 : 0 : action_flags |= MLX5_FLOW_ACTION_IPV6_ROUTING_PUSH;
7270 : 0 : break;
7271 : 0 : case RTE_FLOW_ACTION_TYPE_IPV6_EXT_REMOVE:
7272 : 0 : remove_data = action->conf;
7273 : : /* Remove action must be shared. */
7274 [ # # # # ]: 0 : if (remove_data->type != IPPROTO_ROUTING || !mask) {
7275 : 0 : DRV_LOG(ERR, "Only supports shared IPv6 routing remove");
7276 : 0 : return -EINVAL;
7277 : : }
7278 : 0 : action_flags |= MLX5_FLOW_ACTION_IPV6_ROUTING_REMOVE;
7279 : 0 : break;
7280 : 0 : case RTE_FLOW_ACTION_TYPE_METER:
7281 : : /* TODO: Validation logic */
7282 : 0 : action_flags |= MLX5_FLOW_ACTION_METER;
7283 : 0 : break;
7284 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
7285 : 0 : ret = flow_hw_validate_action_meter_mark(dev, action, false, error);
7286 [ # # ]: 0 : if (ret < 0)
7287 : 0 : return ret;
7288 : 0 : action_flags |= MLX5_FLOW_ACTION_METER;
7289 : 0 : break;
7290 : 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
7291 : 0 : ret = flow_hw_validate_action_modify_field(dev, action, mask,
7292 : : error);
7293 [ # # ]: 0 : if (ret < 0)
7294 : 0 : return ret;
7295 : 0 : action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
7296 : 0 : break;
7297 : 0 : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
7298 : 0 : ret = flow_hw_validate_action_represented_port
7299 : : (dev, action, mask, error);
7300 [ # # ]: 0 : if (ret < 0)
7301 : 0 : return ret;
7302 : 0 : action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7303 : 0 : break;
7304 : 0 : case RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:
7305 : 0 : ret = flow_hw_validate_action_port_representor
7306 : : (dev, attr, action, mask, error);
7307 [ # # ]: 0 : if (ret < 0)
7308 : 0 : return ret;
7309 : 0 : action_flags |= MLX5_FLOW_ACTION_PORT_REPRESENTOR;
7310 : 0 : break;
7311 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
7312 [ # # # # ]: 0 : if (count_mask && count_mask->id)
7313 : 0 : fixed_cnt = true;
7314 : 0 : ret = flow_hw_validate_action_age(dev, action,
7315 : : action_flags,
7316 : : fixed_cnt, error);
7317 [ # # ]: 0 : if (ret < 0)
7318 : 0 : return ret;
7319 : 0 : action_flags |= MLX5_FLOW_ACTION_AGE;
7320 : 0 : break;
7321 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
7322 : 0 : ret = flow_hw_validate_action_count(dev, action, mask,
7323 : : action_flags,
7324 : : error);
7325 [ # # ]: 0 : if (ret < 0)
7326 : 0 : return ret;
7327 : 0 : count_mask = mask->conf;
7328 : 0 : action_flags |= MLX5_FLOW_ACTION_COUNT;
7329 : 0 : break;
7330 : 0 : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
7331 : 0 : ret = mlx5_hw_validate_action_conntrack(dev, action, mask,
7332 : : attr, action_flags,
7333 : : error);
7334 [ # # ]: 0 : if (ret)
7335 : 0 : return ret;
7336 : 0 : action_flags |= MLX5_FLOW_ACTION_CT;
7337 : 0 : break;
7338 : 0 : case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7339 : 0 : action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7340 : 0 : break;
7341 : 0 : case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7342 : 0 : action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7343 : 0 : break;
7344 : 0 : case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7345 : 0 : ret = flow_hw_validate_action_push_vlan
7346 : : (dev, attr, action, mask, error);
7347 [ # # ]: 0 : if (ret != 0)
7348 : 0 : return ret;
7349 : 0 : i += is_of_vlan_pcp_present(action) ?
7350 [ # # ]: 0 : MLX5_HW_VLAN_PUSH_PCP_IDX :
7351 : : MLX5_HW_VLAN_PUSH_VID_IDX;
7352 : 0 : action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7353 : 0 : break;
7354 : 0 : case RTE_FLOW_ACTION_TYPE_NAT64:
7355 : 0 : ret = flow_hw_validate_action_nat64(dev, attr, action, mask,
7356 : : action_flags, error);
7357 [ # # ]: 0 : if (ret != 0)
7358 : 0 : return ret;
7359 : 0 : action_flags |= MLX5_FLOW_ACTION_NAT64;
7360 : 0 : break;
7361 : 0 : case RTE_FLOW_ACTION_TYPE_END:
7362 : : actions_end = true;
7363 : 0 : break;
7364 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
7365 : 0 : ret = flow_hw_validate_action_default_miss(dev, attr,
7366 : : action_flags, error);
7367 [ # # ]: 0 : if (ret < 0)
7368 : 0 : return ret;
7369 : 0 : action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
7370 : 0 : break;
7371 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
7372 : 0 : ret = mlx5_flow_validate_action_jump_to_table_index(action, mask, error);
7373 [ # # ]: 0 : if (ret < 0)
7374 : 0 : return ret;
7375 : 0 : action_flags |= MLX5_FLOW_ACTION_JUMP_TO_TABLE_INDEX;
7376 : 0 : break;
7377 : 0 : default:
7378 : 0 : return rte_flow_error_set(error, ENOTSUP,
7379 : : RTE_FLOW_ERROR_TYPE_ACTION,
7380 : : action,
7381 : : "action not supported in template API");
7382 : : }
7383 : : }
7384 [ # # ]: 0 : if (act_flags != NULL)
7385 : 0 : *act_flags = action_flags;
7386 : : return 0;
7387 : : }
7388 : :
7389 : : static int
7390 : 0 : flow_hw_actions_validate(struct rte_eth_dev *dev,
7391 : : const struct rte_flow_actions_template_attr *attr,
7392 : : const struct rte_flow_action actions[],
7393 : : const struct rte_flow_action masks[],
7394 : : struct rte_flow_error *error)
7395 : : {
7396 : 0 : return mlx5_flow_hw_actions_validate(dev, attr, actions, masks, NULL, error);
7397 : : }
7398 : :
7399 : :
7400 : : static enum mlx5dr_action_type mlx5_hw_dr_action_types[] = {
7401 : : [RTE_FLOW_ACTION_TYPE_MARK] = MLX5DR_ACTION_TYP_TAG,
7402 : : [RTE_FLOW_ACTION_TYPE_FLAG] = MLX5DR_ACTION_TYP_TAG,
7403 : : [RTE_FLOW_ACTION_TYPE_DROP] = MLX5DR_ACTION_TYP_DROP,
7404 : : [RTE_FLOW_ACTION_TYPE_JUMP] = MLX5DR_ACTION_TYP_TBL,
7405 : : [RTE_FLOW_ACTION_TYPE_QUEUE] = MLX5DR_ACTION_TYP_TIR,
7406 : : [RTE_FLOW_ACTION_TYPE_RSS] = MLX5DR_ACTION_TYP_TIR,
7407 : : [RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP] = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2,
7408 : : [RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP] = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2,
7409 : : [RTE_FLOW_ACTION_TYPE_VXLAN_DECAP] = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2,
7410 : : [RTE_FLOW_ACTION_TYPE_NVGRE_DECAP] = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2,
7411 : : [RTE_FLOW_ACTION_TYPE_MODIFY_FIELD] = MLX5DR_ACTION_TYP_MODIFY_HDR,
7412 : : [RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT] = MLX5DR_ACTION_TYP_VPORT,
7413 : : [RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR] = MLX5DR_ACTION_TYP_MISS,
7414 : : [RTE_FLOW_ACTION_TYPE_CONNTRACK] = MLX5DR_ACTION_TYP_ASO_CT,
7415 : : [RTE_FLOW_ACTION_TYPE_OF_POP_VLAN] = MLX5DR_ACTION_TYP_POP_VLAN,
7416 : : [RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN] = MLX5DR_ACTION_TYP_PUSH_VLAN,
7417 : : [RTE_FLOW_ACTION_TYPE_SEND_TO_KERNEL] = MLX5DR_ACTION_TYP_DEST_ROOT,
7418 : : [RTE_FLOW_ACTION_TYPE_IPV6_EXT_PUSH] = MLX5DR_ACTION_TYP_PUSH_IPV6_ROUTE_EXT,
7419 : : [RTE_FLOW_ACTION_TYPE_IPV6_EXT_REMOVE] = MLX5DR_ACTION_TYP_POP_IPV6_ROUTE_EXT,
7420 : : [RTE_FLOW_ACTION_TYPE_NAT64] = MLX5DR_ACTION_TYP_NAT64,
7421 : : [RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX] = MLX5DR_ACTION_TYP_JUMP_TO_MATCHER,
7422 : : };
7423 : :
7424 : : static inline void
7425 : : action_template_set_type(struct rte_flow_actions_template *at,
7426 : : enum mlx5dr_action_type *action_types,
7427 : : unsigned int action_src, uint16_t *curr_off,
7428 : : enum mlx5dr_action_type type)
7429 : : {
7430 : 0 : at->dr_off[action_src] = *curr_off;
7431 : 0 : action_types[*curr_off] = type;
7432 : 0 : *curr_off = *curr_off + 1;
7433 : 0 : }
7434 : :
7435 : : static int
7436 : 0 : flow_hw_dr_actions_template_handle_shared(int type, uint32_t action_src,
7437 : : enum mlx5dr_action_type *action_types,
7438 : : uint16_t *curr_off, uint16_t *cnt_off,
7439 : : struct rte_flow_actions_template *at)
7440 : : {
7441 [ # # # # : 0 : switch (type) {
# ]
7442 : : case RTE_FLOW_ACTION_TYPE_RSS:
7443 : : action_template_set_type(at, action_types, action_src, curr_off,
7444 : : MLX5DR_ACTION_TYP_TIR);
7445 : : break;
7446 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
7447 : : case RTE_FLOW_ACTION_TYPE_COUNT:
7448 : : /*
7449 : : * Both AGE and COUNT action need counter, the first one fills
7450 : : * the action_types array, and the second only saves the offset.
7451 : : */
7452 [ # # ]: 0 : if (*cnt_off == UINT16_MAX) {
7453 : 0 : *cnt_off = *curr_off;
7454 : : action_template_set_type(at, action_types,
7455 : : action_src, curr_off,
7456 : : MLX5DR_ACTION_TYP_CTR);
7457 : : }
7458 : 0 : at->dr_off[action_src] = *cnt_off;
7459 : 0 : break;
7460 : : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
7461 : : action_template_set_type(at, action_types, action_src, curr_off,
7462 : : MLX5DR_ACTION_TYP_ASO_CT);
7463 : : break;
7464 : : case RTE_FLOW_ACTION_TYPE_QUOTA:
7465 : : case RTE_FLOW_ACTION_TYPE_METER_MARK:
7466 : : action_template_set_type(at, action_types, action_src, curr_off,
7467 : : MLX5DR_ACTION_TYP_ASO_METER);
7468 : : break;
7469 : 0 : default:
7470 : 0 : DRV_LOG(WARNING, "Unsupported shared action type: %d", type);
7471 : 0 : return -EINVAL;
7472 : : }
7473 : : return 0;
7474 : : }
7475 : :
7476 : :
7477 : : static int
7478 : 0 : flow_hw_template_actions_list(struct rte_flow_actions_template *at,
7479 : : unsigned int action_src,
7480 : : enum mlx5dr_action_type *action_types,
7481 : : uint16_t *curr_off, uint16_t *cnt_off)
7482 : : {
7483 : : int ret;
7484 : 0 : const struct rte_flow_action_indirect_list *indlst_conf = at->actions[action_src].conf;
7485 [ # # # # ]: 0 : enum mlx5_indirect_list_type list_type = mlx5_get_indirect_list_type(indlst_conf->handle);
7486 : : const union {
7487 : : struct mlx5_indlst_legacy *legacy;
7488 : : struct rte_flow_action_list_handle *handle;
7489 : : } indlst_obj = { .handle = indlst_conf->handle };
7490 : : enum mlx5dr_action_type type;
7491 : :
7492 [ # # # # ]: 0 : switch (list_type) {
7493 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY:
7494 : 0 : ret = flow_hw_dr_actions_template_handle_shared
7495 : 0 : (indlst_obj.legacy->legacy_type, action_src,
7496 : : action_types, curr_off, cnt_off, at);
7497 [ # # ]: 0 : if (ret)
7498 : 0 : return ret;
7499 : : break;
7500 : : case MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR:
7501 : : action_template_set_type(at, action_types, action_src, curr_off,
7502 : : MLX5DR_ACTION_TYP_DEST_ARRAY);
7503 : : break;
7504 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT:
7505 : 0 : type = ((struct mlx5_hw_encap_decap_action *)
7506 : : (indlst_conf->handle))->action_type;
7507 : : action_template_set_type(at, action_types, action_src, curr_off, type);
7508 : : break;
7509 : 0 : default:
7510 : 0 : DRV_LOG(ERR, "Unsupported indirect list type");
7511 : 0 : return -EINVAL;
7512 : : }
7513 : : return 0;
7514 : : }
7515 : :
7516 : : /**
7517 : : * Create DR action template based on a provided sequence of flow actions.
7518 : : *
7519 : : * @param[in] dev
7520 : : * Pointer to the rte_eth_dev structure.
7521 : : * @param[in] at
7522 : : * Pointer to flow actions template to be updated.
7523 : : * @param[out] action_types
7524 : : * Action types array to be filled.
7525 : : * @param[out] tmpl_flags
7526 : : * Template DR flags to be filled.
7527 : : *
7528 : : * @return
7529 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
7530 : : */
7531 : : static int
7532 : 0 : flow_hw_parse_flow_actions_to_dr_actions(struct rte_eth_dev *dev,
7533 : : struct rte_flow_actions_template *at,
7534 : : enum mlx5dr_action_type action_types[MLX5_HW_MAX_ACTS],
7535 : : uint32_t *tmpl_flags __rte_unused)
7536 : : {
7537 : : unsigned int i;
7538 : : uint16_t curr_off;
7539 : : enum mlx5dr_action_type reformat_act_type = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2;
7540 : : uint16_t reformat_off = UINT16_MAX;
7541 : : uint16_t mhdr_off = UINT16_MAX;
7542 : : uint16_t recom_off = UINT16_MAX;
7543 : 0 : uint16_t cnt_off = UINT16_MAX;
7544 : : enum mlx5dr_action_type recom_type = MLX5DR_ACTION_TYP_LAST;
7545 : : int ret;
7546 : :
7547 [ # # ]: 0 : for (i = 0, curr_off = 0; at->actions[i].type != RTE_FLOW_ACTION_TYPE_END; ++i) {
7548 : : const struct rte_flow_action_raw_encap *raw_encap_data;
7549 : : size_t data_size;
7550 : : enum mlx5dr_action_type type;
7551 : :
7552 [ # # ]: 0 : if (curr_off >= MLX5_HW_MAX_ACTS)
7553 : 0 : goto err_actions_num;
7554 [ # # # # : 0 : switch ((int)at->actions[i].type) {
# # # # #
# # # # #
# # ]
7555 : : case RTE_FLOW_ACTION_TYPE_VOID:
7556 : : break;
7557 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT_LIST:
7558 : 0 : ret = flow_hw_template_actions_list(at, i, action_types,
7559 : : &curr_off, &cnt_off);
7560 [ # # ]: 0 : if (ret)
7561 : 0 : return ret;
7562 : : break;
7563 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT:
7564 : 0 : ret = flow_hw_dr_actions_template_handle_shared
7565 : 0 : (at->masks[i].type, i, action_types,
7566 : : &curr_off, &cnt_off, at);
7567 [ # # ]: 0 : if (ret)
7568 : 0 : return ret;
7569 : : break;
7570 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7571 : : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7572 : : case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7573 : : case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7574 : : MLX5_ASSERT(reformat_off == UINT16_MAX);
7575 : 0 : reformat_off = curr_off++;
7576 : 0 : reformat_act_type = mlx5_hw_dr_action_types[at->actions[i].type];
7577 : 0 : break;
7578 : 0 : case RTE_FLOW_ACTION_TYPE_IPV6_EXT_PUSH:
7579 : : MLX5_ASSERT(recom_off == UINT16_MAX);
7580 : : recom_type = MLX5DR_ACTION_TYP_PUSH_IPV6_ROUTE_EXT;
7581 : 0 : recom_off = curr_off++;
7582 : 0 : break;
7583 : 0 : case RTE_FLOW_ACTION_TYPE_IPV6_EXT_REMOVE:
7584 : : MLX5_ASSERT(recom_off == UINT16_MAX);
7585 : : recom_type = MLX5DR_ACTION_TYP_POP_IPV6_ROUTE_EXT;
7586 : 0 : recom_off = curr_off++;
7587 : 0 : break;
7588 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7589 : 0 : raw_encap_data = at->actions[i].conf;
7590 : 0 : data_size = raw_encap_data->size;
7591 [ # # ]: 0 : if (reformat_off != UINT16_MAX) {
7592 : : reformat_act_type = data_size < MLX5_ENCAPSULATION_DECISION_SIZE ?
7593 [ # # ]: 0 : MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2 :
7594 : : MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3;
7595 : : } else {
7596 : 0 : reformat_off = curr_off++;
7597 : : reformat_act_type = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;
7598 : : }
7599 : : break;
7600 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7601 : 0 : reformat_off = curr_off++;
7602 : : reformat_act_type = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2;
7603 : 0 : break;
7604 : 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
7605 [ # # ]: 0 : if (mhdr_off == UINT16_MAX) {
7606 : 0 : mhdr_off = curr_off++;
7607 : 0 : type = mlx5_hw_dr_action_types[at->actions[i].type];
7608 : 0 : action_types[mhdr_off] = type;
7609 : : }
7610 : : break;
7611 : 0 : case RTE_FLOW_ACTION_TYPE_METER:
7612 : 0 : at->dr_off[i] = curr_off;
7613 : 0 : action_types[curr_off++] = MLX5DR_ACTION_TYP_ASO_METER;
7614 [ # # ]: 0 : if (curr_off >= MLX5_HW_MAX_ACTS)
7615 : 0 : goto err_actions_num;
7616 : 0 : action_types[curr_off++] = MLX5DR_ACTION_TYP_TBL;
7617 : 0 : break;
7618 : 0 : case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7619 : 0 : type = mlx5_hw_dr_action_types[at->actions[i].type];
7620 : 0 : at->dr_off[i] = curr_off;
7621 : 0 : action_types[curr_off++] = type;
7622 : 0 : i += is_of_vlan_pcp_present(at->actions + i) ?
7623 [ # # ]: 0 : MLX5_HW_VLAN_PUSH_PCP_IDX :
7624 : : MLX5_HW_VLAN_PUSH_VID_IDX;
7625 : 0 : break;
7626 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
7627 : 0 : at->dr_off[i] = curr_off;
7628 : 0 : action_types[curr_off++] = MLX5DR_ACTION_TYP_ASO_METER;
7629 [ # # ]: 0 : if (curr_off >= MLX5_HW_MAX_ACTS)
7630 : 0 : goto err_actions_num;
7631 : : break;
7632 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
7633 : : case RTE_FLOW_ACTION_TYPE_COUNT:
7634 : : /*
7635 : : * Both AGE and COUNT action need counter, the first
7636 : : * one fills the action_types array, and the second only
7637 : : * saves the offset.
7638 : : */
7639 [ # # ]: 0 : if (cnt_off == UINT16_MAX) {
7640 : 0 : cnt_off = curr_off++;
7641 : 0 : action_types[cnt_off] = MLX5DR_ACTION_TYP_CTR;
7642 : : }
7643 : 0 : at->dr_off[i] = cnt_off;
7644 : 0 : break;
7645 : 0 : case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
7646 : 0 : at->dr_off[i] = curr_off;
7647 : 0 : action_types[curr_off++] = MLX5DR_ACTION_TYP_MISS;
7648 : 0 : break;
7649 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
7650 : 0 : *tmpl_flags |= MLX5DR_ACTION_TEMPLATE_FLAG_RELAXED_ORDER;
7651 : 0 : at->dr_off[i] = curr_off;
7652 : 0 : action_types[curr_off++] = MLX5DR_ACTION_TYP_JUMP_TO_MATCHER;
7653 : 0 : break;
7654 : 0 : default:
7655 : 0 : type = mlx5_hw_dr_action_types[at->actions[i].type];
7656 : 0 : at->dr_off[i] = curr_off;
7657 : 0 : action_types[curr_off++] = type;
7658 : 0 : break;
7659 : : }
7660 : : }
7661 [ # # ]: 0 : if (curr_off >= MLX5_HW_MAX_ACTS)
7662 : 0 : goto err_actions_num;
7663 [ # # ]: 0 : if (mhdr_off != UINT16_MAX)
7664 : 0 : at->mhdr_off = mhdr_off;
7665 [ # # ]: 0 : if (reformat_off != UINT16_MAX) {
7666 : 0 : at->reformat_off = reformat_off;
7667 : 0 : action_types[reformat_off] = reformat_act_type;
7668 : : }
7669 [ # # ]: 0 : if (recom_off != UINT16_MAX) {
7670 : 0 : at->recom_off = recom_off;
7671 : 0 : action_types[recom_off] = recom_type;
7672 : : }
7673 : 0 : at->dr_actions_num = curr_off;
7674 : :
7675 : : /* Create srh flex parser for remove anchor. */
7676 [ # # ]: 0 : if ((recom_type == MLX5DR_ACTION_TYP_POP_IPV6_ROUTE_EXT ||
7677 [ # # ]: 0 : recom_type == MLX5DR_ACTION_TYP_PUSH_IPV6_ROUTE_EXT) &&
7678 : 0 : (ret = mlx5_alloc_srh_flex_parser(dev))) {
7679 : 0 : DRV_LOG(ERR, "Failed to create srv6 flex parser");
7680 : 0 : return ret;
7681 : : }
7682 : : return 0;
7683 : 0 : err_actions_num:
7684 : 0 : DRV_LOG(ERR, "Number of HW actions (%u) exceeded maximum (%u) allowed in template",
7685 : : curr_off, MLX5_HW_MAX_ACTS);
7686 : 0 : return -EINVAL;
7687 : : }
7688 : :
7689 : : static void
7690 : 0 : flow_hw_set_vlan_vid(struct rte_eth_dev *dev,
7691 : : struct rte_flow_action *ra,
7692 : : struct rte_flow_action *rm,
7693 : : struct rte_flow_action_modify_field *spec,
7694 : : struct rte_flow_action_modify_field *mask,
7695 : : int set_vlan_vid_ix)
7696 : : {
7697 : : struct rte_flow_error error;
7698 [ # # ]: 0 : const bool masked = rm[set_vlan_vid_ix].conf &&
7699 : : (((const struct rte_flow_action_of_set_vlan_vid *)
7700 [ # # ]: 0 : rm[set_vlan_vid_ix].conf)->vlan_vid != 0);
7701 : 0 : const struct rte_flow_action_of_set_vlan_vid *conf =
7702 : 0 : ra[set_vlan_vid_ix].conf;
7703 : 0 : int width = mlx5_flow_item_field_width(dev, RTE_FLOW_FIELD_VLAN_ID, 0,
7704 : : NULL, &error);
7705 : 0 : *spec = (typeof(*spec)) {
7706 : : .operation = RTE_FLOW_MODIFY_SET,
7707 : : .dst = {
7708 : : .field = RTE_FLOW_FIELD_VLAN_ID,
7709 : : .level = 0, .offset = 0,
7710 : : },
7711 : : .src = {
7712 : : .field = RTE_FLOW_FIELD_VALUE,
7713 : : },
7714 : : .width = width,
7715 : : };
7716 : 0 : *mask = (typeof(*mask)) {
7717 : : .operation = RTE_FLOW_MODIFY_SET,
7718 : : .dst = {
7719 : : .field = RTE_FLOW_FIELD_VLAN_ID,
7720 : : .level = 0xff, .offset = 0xffffffff,
7721 : : },
7722 : : .src = {
7723 : : .field = RTE_FLOW_FIELD_VALUE,
7724 : : },
7725 : : .width = 0xffffffff,
7726 : : };
7727 [ # # ]: 0 : if (masked) {
7728 : 0 : uint32_t mask_val = 0xffffffff;
7729 : :
7730 [ # # ]: 0 : rte_memcpy(spec->src.value, &conf->vlan_vid, sizeof(conf->vlan_vid));
7731 [ # # ]: 0 : rte_memcpy(mask->src.value, &mask_val, sizeof(mask_val));
7732 : : }
7733 : 0 : ra[set_vlan_vid_ix].type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD;
7734 : 0 : ra[set_vlan_vid_ix].conf = spec;
7735 : 0 : rm[set_vlan_vid_ix].type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD;
7736 : 0 : rm[set_vlan_vid_ix].conf = mask;
7737 : 0 : }
7738 : :
7739 : : static __rte_always_inline int
7740 : : flow_hw_set_vlan_vid_construct(struct rte_eth_dev *dev,
7741 : : struct mlx5_modification_cmd *mhdr_cmd,
7742 : : struct mlx5_action_construct_data *act_data,
7743 : : const struct mlx5_hw_actions *hw_acts,
7744 : : const struct rte_flow_action *action)
7745 : : {
7746 : : struct rte_flow_error error;
7747 : 0 : rte_be16_t vid = ((const struct rte_flow_action_of_set_vlan_vid *)
7748 : 0 : action->conf)->vlan_vid;
7749 : 0 : int width = mlx5_flow_item_field_width(dev, RTE_FLOW_FIELD_VLAN_ID, 0,
7750 : : NULL, &error);
7751 [ # # # # : 0 : struct rte_flow_action_modify_field conf = {
# # # # #
# ]
7752 : : .operation = RTE_FLOW_MODIFY_SET,
7753 : : .dst = {
7754 : : .field = RTE_FLOW_FIELD_VLAN_ID,
7755 : : .level = 0, .offset = 0,
7756 : : },
7757 : : .src = {
7758 : : .field = RTE_FLOW_FIELD_VALUE,
7759 : : },
7760 : : .width = width,
7761 : : };
7762 : : struct rte_flow_action modify_action = {
7763 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
7764 : : .conf = &conf
7765 : : };
7766 : :
7767 : : rte_memcpy(conf.src.value, &vid, sizeof(vid));
7768 : : return flow_hw_modify_field_construct(mhdr_cmd, act_data, hw_acts, &modify_action);
7769 : : }
7770 : :
7771 : : static int
7772 : 0 : flow_hw_flex_item_acquire(struct rte_eth_dev *dev,
7773 : : struct rte_flow_item_flex_handle *handle,
7774 : : uint8_t *flex_item)
7775 : : {
7776 : 0 : int index = mlx5_flex_acquire_index(dev, handle, false);
7777 : :
7778 : : MLX5_ASSERT(index >= 0 && index < (int)(sizeof(uint32_t) * CHAR_BIT));
7779 [ # # ]: 0 : if (index < 0)
7780 : : return -1;
7781 [ # # ]: 0 : if (!(*flex_item & RTE_BIT32(index))) {
7782 : : /* Don't count same flex item again. */
7783 : 0 : if (mlx5_flex_acquire_index(dev, handle, true) != index)
7784 : : MLX5_ASSERT(false);
7785 : 0 : *flex_item |= (uint8_t)RTE_BIT32(index);
7786 : : }
7787 : : return 0;
7788 : : }
7789 : :
7790 : : static void
7791 : 0 : flow_hw_flex_item_release(struct rte_eth_dev *dev, uint8_t *flex_item)
7792 : : {
7793 [ # # ]: 0 : while (*flex_item) {
7794 : 0 : int index = rte_bsf32(*flex_item);
7795 : :
7796 : 0 : mlx5_flex_release_index(dev, index);
7797 : 0 : *flex_item &= ~(uint8_t)RTE_BIT32(index);
7798 : : }
7799 : 0 : }
7800 : : static __rte_always_inline void
7801 : : flow_hw_actions_template_replace_container(const
7802 : : struct rte_flow_action *actions,
7803 : : const
7804 : : struct rte_flow_action *masks,
7805 : : struct rte_flow_action *new_actions,
7806 : : struct rte_flow_action *new_masks,
7807 : : struct rte_flow_action **ra,
7808 : : struct rte_flow_action **rm,
7809 : : uint32_t act_num)
7810 : : {
7811 : 0 : memcpy(new_actions, actions, sizeof(actions[0]) * act_num);
7812 : : memcpy(new_masks, masks, sizeof(masks[0]) * act_num);
7813 : : *ra = (void *)(uintptr_t)new_actions;
7814 : : *rm = (void *)(uintptr_t)new_masks;
7815 : 0 : }
7816 : :
7817 : : /* Action template copies these actions in rte_flow_conv() */
7818 : :
7819 : : static const struct rte_flow_action rx_meta_copy_action = {
7820 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
7821 : : .conf = &(struct rte_flow_action_modify_field){
7822 : : .operation = RTE_FLOW_MODIFY_SET,
7823 : : .dst = {
7824 : : .field = (enum rte_flow_field_id)
7825 : : MLX5_RTE_FLOW_FIELD_META_REG,
7826 : : .tag_index = REG_B,
7827 : : },
7828 : : .src = {
7829 : : .field = (enum rte_flow_field_id)
7830 : : MLX5_RTE_FLOW_FIELD_META_REG,
7831 : : .tag_index = REG_C_1,
7832 : : },
7833 : : .width = 32,
7834 : : }
7835 : : };
7836 : :
7837 : : static const struct rte_flow_action rx_meta_copy_mask = {
7838 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
7839 : : .conf = &(struct rte_flow_action_modify_field){
7840 : : .operation = RTE_FLOW_MODIFY_SET,
7841 : : .dst = {
7842 : : .field = (enum rte_flow_field_id)
7843 : : MLX5_RTE_FLOW_FIELD_META_REG,
7844 : : .level = UINT8_MAX,
7845 : : .tag_index = UINT8_MAX,
7846 : : .offset = UINT32_MAX,
7847 : : },
7848 : : .src = {
7849 : : .field = (enum rte_flow_field_id)
7850 : : MLX5_RTE_FLOW_FIELD_META_REG,
7851 : : .level = UINT8_MAX,
7852 : : .tag_index = UINT8_MAX,
7853 : : .offset = UINT32_MAX,
7854 : : },
7855 : : .width = UINT32_MAX,
7856 : : }
7857 : : };
7858 : :
7859 : : static const struct rte_flow_action quota_color_inc_action = {
7860 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
7861 : : .conf = &(struct rte_flow_action_modify_field) {
7862 : : .operation = RTE_FLOW_MODIFY_ADD,
7863 : : .dst = {
7864 : : .field = RTE_FLOW_FIELD_METER_COLOR,
7865 : : .level = 0, .offset = 0
7866 : : },
7867 : : .src = {
7868 : : .field = RTE_FLOW_FIELD_VALUE,
7869 : : .level = 1,
7870 : : .offset = 0,
7871 : : },
7872 : : .width = 2
7873 : : }
7874 : : };
7875 : :
7876 : : static const struct rte_flow_action quota_color_inc_mask = {
7877 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
7878 : : .conf = &(struct rte_flow_action_modify_field) {
7879 : : .operation = RTE_FLOW_MODIFY_ADD,
7880 : : .dst = {
7881 : : .field = RTE_FLOW_FIELD_METER_COLOR,
7882 : : .level = UINT8_MAX,
7883 : : .tag_index = UINT8_MAX,
7884 : : .offset = UINT32_MAX,
7885 : : },
7886 : : .src = {
7887 : : .field = RTE_FLOW_FIELD_VALUE,
7888 : : .level = 3,
7889 : : .offset = 0
7890 : : },
7891 : : .width = UINT32_MAX
7892 : : }
7893 : : };
7894 : :
7895 : : /**
7896 : : * Create flow action template.
7897 : : *
7898 : : * @param[in] dev
7899 : : * Pointer to the rte_eth_dev structure.
7900 : : * @param[in] attr
7901 : : * Pointer to the action template attributes.
7902 : : * @param[in] actions
7903 : : * Associated actions (list terminated by the END action).
7904 : : * @param[in] masks
7905 : : * List of actions that marks which of the action's member is constant.
7906 : : * @param[in] nt_mode
7907 : : * Non template mode.
7908 : : * @param[out] error
7909 : : * Pointer to error structure.
7910 : : *
7911 : : * @return
7912 : : * Action template pointer on success, NULL otherwise and rte_errno is set.
7913 : : */
7914 : : static struct rte_flow_actions_template *
7915 : 0 : __flow_hw_actions_template_create(struct rte_eth_dev *dev,
7916 : : const struct rte_flow_actions_template_attr *attr,
7917 : : const struct rte_flow_action actions[],
7918 : : const struct rte_flow_action masks[],
7919 : : bool nt_mode,
7920 : : struct rte_flow_error *error)
7921 : : {
7922 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
7923 : : int len, act_len, mask_len;
7924 : : int orig_act_len;
7925 : : unsigned int act_num;
7926 : : unsigned int i;
7927 : : struct rte_flow_actions_template *at = NULL;
7928 : : uint16_t pos;
7929 : 0 : uint64_t action_flags = 0;
7930 : : struct rte_flow_action tmp_action[MLX5_HW_MAX_ACTS];
7931 : : struct rte_flow_action tmp_mask[MLX5_HW_MAX_ACTS];
7932 : : struct rte_flow_action *ra = (void *)(uintptr_t)actions;
7933 : : struct rte_flow_action *rm = (void *)(uintptr_t)masks;
7934 : : int set_vlan_vid_ix = -1;
7935 : 0 : struct rte_flow_action_modify_field set_vlan_vid_spec = {0, };
7936 : 0 : struct rte_flow_action_modify_field set_vlan_vid_mask = {0, };
7937 : : struct rte_flow_action mf_actions[MLX5_HW_MAX_ACTS];
7938 : : struct rte_flow_action mf_masks[MLX5_HW_MAX_ACTS];
7939 : : uint32_t expand_mf_num = 0;
7940 : 0 : uint16_t src_off[MLX5_HW_MAX_ACTS] = {0, };
7941 : 0 : enum mlx5dr_action_type action_types[MLX5_HW_MAX_ACTS] = { MLX5DR_ACTION_TYP_LAST };
7942 : 0 : uint32_t tmpl_flags = 0;
7943 : : int ret;
7944 : :
7945 [ # # # # ]: 0 : if (!nt_mode && mlx5_flow_hw_actions_validate(dev, attr, actions, masks,
7946 : : &action_flags, error))
7947 : : return NULL;
7948 [ # # ]: 0 : for (i = 0; ra[i].type != RTE_FLOW_ACTION_TYPE_END; ++i) {
7949 [ # # # ]: 0 : switch (ra[i].type) {
7950 : : /* OF_PUSH_VLAN *MUST* come before OF_SET_VLAN_VID */
7951 : 0 : case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7952 : 0 : i += is_of_vlan_pcp_present(ra + i) ?
7953 [ # # ]: 0 : MLX5_HW_VLAN_PUSH_PCP_IDX :
7954 : : MLX5_HW_VLAN_PUSH_VID_IDX;
7955 : 0 : break;
7956 : 0 : case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7957 : 0 : set_vlan_vid_ix = i;
7958 : 0 : break;
7959 : : default:
7960 : : break;
7961 : : }
7962 : : }
7963 : : /*
7964 : : * Count flow actions to allocate required space for storing DR offsets and to check
7965 : : * if temporary buffer would not be overrun.
7966 : : */
7967 : 0 : act_num = i + 1;
7968 [ # # ]: 0 : if (act_num >= MLX5_HW_MAX_ACTS) {
7969 : 0 : rte_flow_error_set(error, EINVAL,
7970 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL, "Too many actions");
7971 : 0 : return NULL;
7972 : : }
7973 [ # # ]: 0 : if (set_vlan_vid_ix != -1) {
7974 : : /* If temporary action buffer was not used, copy template actions to it */
7975 : : if (ra == actions)
7976 : : flow_hw_actions_template_replace_container(actions,
7977 : : masks,
7978 : : tmp_action,
7979 : : tmp_mask,
7980 : : &ra, &rm,
7981 : : act_num);
7982 : 0 : flow_hw_set_vlan_vid(dev, ra, rm,
7983 : : &set_vlan_vid_spec, &set_vlan_vid_mask,
7984 : : set_vlan_vid_ix);
7985 : 0 : action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
7986 : : }
7987 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_QUOTA) {
7988 : 0 : mf_actions[expand_mf_num] = quota_color_inc_action;
7989 : 0 : mf_masks[expand_mf_num] = quota_color_inc_mask;
7990 : : expand_mf_num++;
7991 : : }
7992 [ # # ]: 0 : if (priv->sh->config.dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS &&
7993 : 0 : priv->sh->config.dv_esw_en &&
7994 [ # # ]: 0 : (action_flags & (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS))) {
7995 : : /* Insert META copy */
7996 : 0 : mf_actions[expand_mf_num] = rx_meta_copy_action;
7997 : 0 : mf_masks[expand_mf_num] = rx_meta_copy_mask;
7998 : 0 : expand_mf_num++;
7999 : : }
8000 [ # # ]: 0 : if (expand_mf_num) {
8001 [ # # ]: 0 : if (act_num + expand_mf_num > MLX5_HW_MAX_ACTS) {
8002 : 0 : rte_flow_error_set(error, E2BIG,
8003 : : RTE_FLOW_ERROR_TYPE_ACTION,
8004 : : NULL, "cannot expand: too many actions");
8005 : 0 : return NULL;
8006 : : }
8007 [ # # ]: 0 : if (ra == actions)
8008 : : flow_hw_actions_template_replace_container(actions,
8009 : : masks,
8010 : : tmp_action,
8011 : : tmp_mask,
8012 : : &ra, &rm,
8013 : : act_num);
8014 : : /* Application should make sure only one Q/RSS exist in one rule. */
8015 : 0 : pos = flow_hw_template_expand_modify_field(ra, rm,
8016 : : mf_actions,
8017 : : mf_masks,
8018 : : action_flags,
8019 : : act_num,
8020 : : expand_mf_num);
8021 [ # # ]: 0 : if (pos == MLX5_HW_EXPAND_MH_FAILED) {
8022 : 0 : rte_flow_error_set(error, ENOMEM,
8023 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8024 : : NULL, "modify header expansion failed");
8025 : 0 : return NULL;
8026 : : }
8027 : : act_num += expand_mf_num;
8028 [ # # ]: 0 : for (i = pos + expand_mf_num; i < act_num; i++)
8029 : 0 : src_off[i] += expand_mf_num;
8030 : 0 : action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
8031 : : }
8032 : 0 : act_len = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, NULL, 0, ra, error);
8033 [ # # ]: 0 : if (act_len <= 0)
8034 : : return NULL;
8035 : 0 : len = RTE_ALIGN(act_len, 16);
8036 : 0 : mask_len = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, NULL, 0, rm, error);
8037 [ # # ]: 0 : if (mask_len <= 0)
8038 : : return NULL;
8039 : 0 : len += RTE_ALIGN(mask_len, 16);
8040 : 0 : len += RTE_ALIGN(act_num * sizeof(*at->dr_off), 16);
8041 : 0 : len += RTE_ALIGN(act_num * sizeof(*at->src_off), 16);
8042 : 0 : orig_act_len = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, NULL, 0, actions, error);
8043 [ # # ]: 0 : if (orig_act_len <= 0)
8044 : : return NULL;
8045 : 0 : len += RTE_ALIGN(orig_act_len, 16);
8046 : 0 : at = mlx5_malloc(MLX5_MEM_ZERO, len + sizeof(*at),
8047 : 0 : RTE_CACHE_LINE_SIZE, rte_socket_id());
8048 [ # # ]: 0 : if (!at) {
8049 : 0 : rte_flow_error_set(error, ENOMEM,
8050 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8051 : : NULL,
8052 : : "cannot allocate action template");
8053 : 0 : return NULL;
8054 : : }
8055 : : /* Actions part is in the first part. */
8056 : 0 : at->attr = *attr;
8057 : 0 : at->actions = (struct rte_flow_action *)(at + 1);
8058 : 0 : act_len = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, at->actions,
8059 : : len, ra, error);
8060 [ # # ]: 0 : if (act_len <= 0)
8061 : 0 : goto error;
8062 : : /* Masks part is in the second part. */
8063 : 0 : at->masks = (struct rte_flow_action *)(((uint8_t *)at->actions) + act_len);
8064 : 0 : mask_len = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, at->masks,
8065 : 0 : len - act_len, rm, error);
8066 [ # # ]: 0 : if (mask_len <= 0)
8067 : 0 : goto error;
8068 : : /* DR actions offsets in the third part. */
8069 : 0 : at->dr_off = (uint16_t *)((uint8_t *)at->masks + mask_len);
8070 : 0 : at->src_off = RTE_PTR_ADD(at->dr_off,
8071 : : RTE_ALIGN(act_num * sizeof(*at->dr_off), 16));
8072 : : memcpy(at->src_off, src_off, act_num * sizeof(at->src_off[0]));
8073 : 0 : at->orig_actions = RTE_PTR_ADD(at->src_off,
8074 : : RTE_ALIGN(act_num * sizeof(*at->src_off), 16));
8075 : 0 : orig_act_len = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, at->orig_actions, orig_act_len,
8076 : : actions, error);
8077 [ # # ]: 0 : if (orig_act_len <= 0)
8078 : 0 : goto error;
8079 : 0 : at->actions_num = act_num;
8080 [ # # ]: 0 : for (i = 0; i < at->actions_num; ++i)
8081 : 0 : at->dr_off[i] = UINT16_MAX;
8082 : 0 : at->reformat_off = UINT16_MAX;
8083 : 0 : at->mhdr_off = UINT16_MAX;
8084 : 0 : at->recom_off = UINT16_MAX;
8085 [ # # ]: 0 : for (i = 0; actions->type != RTE_FLOW_ACTION_TYPE_END;
8086 : 0 : actions++, masks++, i++) {
8087 : : const struct rte_flow_action_modify_field *info;
8088 : :
8089 [ # # # ]: 0 : switch (actions->type) {
8090 : : /*
8091 : : * mlx5 PMD hacks indirect action index directly to the action conf.
8092 : : * The rte_flow_conv() function copies the content from conf pointer.
8093 : : * Need to restore the indirect action index from action conf here.
8094 : : */
8095 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT:
8096 : 0 : at->actions[i].conf = ra[i].conf;
8097 : 0 : at->masks[i].conf = rm[i].conf;
8098 : 0 : break;
8099 : 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
8100 : 0 : info = actions->conf;
8101 [ # # # # ]: 0 : if ((info->dst.field == RTE_FLOW_FIELD_FLEX_ITEM &&
8102 : 0 : flow_hw_flex_item_acquire(dev, info->dst.flex_handle,
8103 : 0 : &at->flex_item)) ||
8104 [ # # # # ]: 0 : (info->src.field == RTE_FLOW_FIELD_FLEX_ITEM &&
8105 : 0 : flow_hw_flex_item_acquire(dev, info->src.flex_handle,
8106 : : &at->flex_item)))
8107 : 0 : goto error;
8108 : : break;
8109 : : default:
8110 : : break;
8111 : : }
8112 : : }
8113 : 0 : ret = flow_hw_parse_flow_actions_to_dr_actions(dev, at, action_types, &tmpl_flags);
8114 [ # # ]: 0 : if (ret)
8115 : 0 : goto error;
8116 : 0 : at->action_flags = action_flags;
8117 : : /* In non template mode there is no need to create the dr template. */
8118 [ # # ]: 0 : if (nt_mode)
8119 : : return at;
8120 : 0 : at->tmpl = mlx5dr_action_template_create(action_types, tmpl_flags);
8121 [ # # ]: 0 : if (!at->tmpl) {
8122 : 0 : DRV_LOG(ERR, "Failed to create DR action template: %d", rte_errno);
8123 : 0 : goto error;
8124 : : }
8125 : 0 : rte_atomic_fetch_add_explicit(&at->refcnt, 1, rte_memory_order_relaxed);
8126 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->flow_hw_at, at, next);
8127 : 0 : return at;
8128 : 0 : error:
8129 : : if (at) {
8130 : 0 : mlx5_free(at);
8131 : : }
8132 : 0 : rte_flow_error_set(error, rte_errno,
8133 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8134 : : "Failed to create action template");
8135 : 0 : return NULL;
8136 : : }
8137 : :
8138 : : /**
8139 : : * Create flow action template.
8140 : : *
8141 : : * @param[in] dev
8142 : : * Pointer to the rte_eth_dev structure.
8143 : : * @param[in] attr
8144 : : * Pointer to the action template attributes.
8145 : : * @param[in] actions
8146 : : * Associated actions (list terminated by the END action).
8147 : : * @param[in] masks
8148 : : * List of actions that marks which of the action's member is constant.
8149 : : * @param[out] error
8150 : : * Pointer to error structure.
8151 : : *
8152 : : * @return
8153 : : * Action template pointer on success, NULL otherwise and rte_errno is set.
8154 : : */
8155 : : static struct rte_flow_actions_template *
8156 : 0 : flow_hw_actions_template_create(struct rte_eth_dev *dev,
8157 : : const struct rte_flow_actions_template_attr *attr,
8158 : : const struct rte_flow_action actions[],
8159 : : const struct rte_flow_action masks[],
8160 : : struct rte_flow_error *error)
8161 : : {
8162 : 0 : return __flow_hw_actions_template_create(dev, attr, actions, masks, false, error);
8163 : : }
8164 : :
8165 : : /**
8166 : : * Destroy flow action template.
8167 : : *
8168 : : * @param[in] dev
8169 : : * Pointer to the rte_eth_dev structure.
8170 : : * @param[in] template
8171 : : * Pointer to the action template to be destroyed.
8172 : : * @param[out] error
8173 : : * Pointer to error structure.
8174 : : *
8175 : : * @return
8176 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
8177 : : */
8178 : : static int
8179 : 0 : flow_hw_actions_template_destroy(struct rte_eth_dev *dev,
8180 : : struct rte_flow_actions_template *template,
8181 : : struct rte_flow_error *error __rte_unused)
8182 : : {
8183 : : uint64_t flag = MLX5_FLOW_ACTION_IPV6_ROUTING_REMOVE |
8184 : : MLX5_FLOW_ACTION_IPV6_ROUTING_PUSH;
8185 : :
8186 [ # # ]: 0 : if (rte_atomic_load_explicit(&template->refcnt, rte_memory_order_relaxed) > 1) {
8187 : 0 : DRV_LOG(WARNING, "Action template %p is still in use.",
8188 : : (void *)template);
8189 : 0 : return rte_flow_error_set(error, EBUSY,
8190 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8191 : : NULL,
8192 : : "action template is in use");
8193 : : }
8194 [ # # ]: 0 : if (template->action_flags & flag)
8195 : 0 : mlx5_free_srh_flex_parser(dev);
8196 [ # # ]: 0 : LIST_REMOVE(template, next);
8197 : 0 : flow_hw_flex_item_release(dev, &template->flex_item);
8198 [ # # ]: 0 : if (template->tmpl)
8199 : 0 : mlx5dr_action_template_destroy(template->tmpl);
8200 : 0 : mlx5_free(template);
8201 : 0 : return 0;
8202 : : }
8203 : :
8204 : : static struct rte_flow_item *
8205 : 0 : flow_hw_prepend_item(const struct rte_flow_item *items,
8206 : : const uint32_t nb_items,
8207 : : const struct rte_flow_item *new_item,
8208 : : struct rte_flow_error *error)
8209 : : {
8210 : : struct rte_flow_item *copied_items;
8211 : : size_t size;
8212 : :
8213 : : /* Allocate new array of items. */
8214 : 0 : size = sizeof(*copied_items) * (nb_items + 1);
8215 : 0 : copied_items = mlx5_malloc(MLX5_MEM_ZERO, size, 0, rte_socket_id());
8216 [ # # ]: 0 : if (!copied_items) {
8217 : 0 : rte_flow_error_set(error, ENOMEM,
8218 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8219 : : NULL,
8220 : : "cannot allocate item template");
8221 : 0 : return NULL;
8222 : : }
8223 : : /* Put new item at the beginning and copy the rest. */
8224 : 0 : copied_items[0] = *new_item;
8225 [ # # ]: 0 : rte_memcpy(&copied_items[1], items, sizeof(*items) * nb_items);
8226 : : return copied_items;
8227 : : }
8228 : :
8229 : : static int
8230 : 0 : flow_hw_item_compare_field_validate(enum rte_flow_field_id arg_field,
8231 : : enum rte_flow_field_id base_field,
8232 : : struct rte_flow_error *error)
8233 : : {
8234 [ # # # ]: 0 : switch (arg_field) {
8235 : : case RTE_FLOW_FIELD_TAG:
8236 : : case RTE_FLOW_FIELD_META:
8237 : : case RTE_FLOW_FIELD_ESP_SEQ_NUM:
8238 : : break;
8239 : 0 : case RTE_FLOW_FIELD_RANDOM:
8240 [ # # ]: 0 : if (base_field == RTE_FLOW_FIELD_VALUE)
8241 : : return 0;
8242 : 0 : return rte_flow_error_set(error, EINVAL,
8243 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8244 : : NULL,
8245 : : "compare random is supported only with immediate value");
8246 : 0 : default:
8247 : 0 : return rte_flow_error_set(error, ENOTSUP,
8248 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8249 : : NULL,
8250 : : "compare item argument field is not supported");
8251 : : }
8252 [ # # ]: 0 : switch (base_field) {
8253 : : case RTE_FLOW_FIELD_TAG:
8254 : : case RTE_FLOW_FIELD_META:
8255 : : case RTE_FLOW_FIELD_VALUE:
8256 : : case RTE_FLOW_FIELD_ESP_SEQ_NUM:
8257 : : break;
8258 : 0 : default:
8259 : 0 : return rte_flow_error_set(error, ENOTSUP,
8260 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8261 : : NULL,
8262 : : "compare item base field is not supported");
8263 : : }
8264 : : return 0;
8265 : : }
8266 : :
8267 : : static inline uint32_t
8268 : : flow_hw_item_compare_width_supported(enum rte_flow_field_id field)
8269 : : {
8270 [ # # # ]: 0 : switch (field) {
8271 : : case RTE_FLOW_FIELD_TAG:
8272 : : case RTE_FLOW_FIELD_META:
8273 : : case RTE_FLOW_FIELD_ESP_SEQ_NUM:
8274 : : return 32;
8275 : 0 : case RTE_FLOW_FIELD_RANDOM:
8276 : 0 : return 16;
8277 : : default:
8278 : : break;
8279 : : }
8280 : 0 : return 0;
8281 : : }
8282 : :
8283 : : static int
8284 : 0 : flow_hw_validate_item_compare(const struct rte_flow_item *item,
8285 : : struct rte_flow_error *error)
8286 : : {
8287 : 0 : const struct rte_flow_item_compare *comp_m = item->mask;
8288 : 0 : const struct rte_flow_item_compare *comp_v = item->spec;
8289 : : int ret;
8290 : :
8291 [ # # ]: 0 : if (unlikely(!comp_m))
8292 : 0 : return rte_flow_error_set(error, EINVAL,
8293 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8294 : : NULL,
8295 : : "compare item mask is missing");
8296 [ # # ]: 0 : if (comp_m->width != UINT32_MAX)
8297 : 0 : return rte_flow_error_set(error, EINVAL,
8298 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8299 : : NULL,
8300 : : "compare item only support full mask");
8301 : 0 : ret = flow_hw_item_compare_field_validate(comp_m->a.field,
8302 : 0 : comp_m->b.field, error);
8303 [ # # ]: 0 : if (ret < 0)
8304 : : return ret;
8305 [ # # ]: 0 : if (comp_v) {
8306 : : uint32_t width;
8307 : :
8308 [ # # ]: 0 : if (comp_v->operation != comp_m->operation ||
8309 [ # # ]: 0 : comp_v->a.field != comp_m->a.field ||
8310 [ # # ]: 0 : comp_v->b.field != comp_m->b.field)
8311 : 0 : return rte_flow_error_set(error, EINVAL,
8312 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8313 : : NULL,
8314 : : "compare item spec/mask not matching");
8315 : : width = flow_hw_item_compare_width_supported(comp_v->a.field);
8316 : : MLX5_ASSERT(width > 0);
8317 [ # # ]: 0 : if ((comp_v->width & comp_m->width) != width)
8318 : 0 : return rte_flow_error_set(error, EINVAL,
8319 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8320 : : NULL,
8321 : : "compare item only support full mask");
8322 : : }
8323 : : return 0;
8324 : : }
8325 : :
8326 : : static inline int
8327 : : mlx5_hw_validate_item_nsh(struct rte_eth_dev *dev,
8328 : : const struct rte_flow_item *item,
8329 : : struct rte_flow_error *error)
8330 : : {
8331 : 0 : return mlx5_flow_validate_item_nsh(dev, item, error);
8332 : : }
8333 : :
8334 : : static bool
8335 : : mlx5_hw_flow_tunnel_ip_check(uint64_t last_item, uint64_t *item_flags)
8336 : : {
8337 : : bool tunnel;
8338 : :
8339 [ # # # # ]: 0 : if (last_item == MLX5_FLOW_LAYER_OUTER_L3_IPV4) {
8340 : : tunnel = true;
8341 : 0 : *item_flags |= MLX5_FLOW_LAYER_IPIP;
8342 : 0 : } else if (last_item == MLX5_FLOW_LAYER_OUTER_L3_IPV6 ||
8343 [ # # # # ]: 0 : last_item == MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT) {
8344 : : tunnel = true;
8345 : 0 : *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
8346 : : } else {
8347 : : tunnel = false;
8348 : : }
8349 : : return tunnel;
8350 : : }
8351 : :
8352 : : const struct rte_flow_item_ipv4 hws_nic_ipv4_mask = {
8353 : : .hdr = {
8354 : : .version = 0xf,
8355 : : .ihl = 0xf,
8356 : : .type_of_service = 0xff,
8357 : : .total_length = RTE_BE16(0xffff),
8358 : : .packet_id = RTE_BE16(0xffff),
8359 : : .fragment_offset = RTE_BE16(0xffff),
8360 : : .time_to_live = 0xff,
8361 : : .next_proto_id = 0xff,
8362 : : .src_addr = RTE_BE32(0xffffffff),
8363 : : .dst_addr = RTE_BE32(0xffffffff),
8364 : : },
8365 : : };
8366 : :
8367 : : const struct rte_flow_item_ipv6 hws_nic_ipv6_mask = {
8368 : : .hdr = {
8369 : : .vtc_flow = RTE_BE32(0xffffffff),
8370 : : .payload_len = RTE_BE16(0xffff),
8371 : : .proto = 0xff,
8372 : : .hop_limits = 0xff,
8373 : : .src_addr = RTE_IPV6_MASK_FULL,
8374 : : .dst_addr = RTE_IPV6_MASK_FULL,
8375 : : },
8376 : : .has_frag_ext = 1,
8377 : : };
8378 : :
8379 : : static int
8380 : 0 : flow_hw_validate_item_ptype(const struct rte_flow_item *item,
8381 : : struct rte_flow_error *error)
8382 : : {
8383 : 0 : const struct rte_flow_item_ptype *ptype = item->mask;
8384 : :
8385 : : /* HWS does not allow empty PTYPE mask */
8386 [ # # ]: 0 : if (!ptype)
8387 : 0 : return rte_flow_error_set(error, EINVAL,
8388 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8389 : : NULL, "empty ptype mask");
8390 [ # # ]: 0 : if (!(ptype->packet_type &
8391 : : (RTE_PTYPE_L2_MASK | RTE_PTYPE_L3_MASK | RTE_PTYPE_L4_MASK |
8392 : : RTE_PTYPE_INNER_L2_MASK | RTE_PTYPE_INNER_L3_MASK |
8393 : : RTE_PTYPE_INNER_L4_MASK)))
8394 : 0 : return rte_flow_error_set(error, ENOTSUP,
8395 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8396 : : NULL, "ptype mask not supported");
8397 : : return 0;
8398 : : }
8399 : :
8400 : : struct mlx5_hw_pattern_validation_ctx {
8401 : : const struct rte_flow_item *geneve_item;
8402 : : const struct rte_flow_item *flex_item;
8403 : : };
8404 : :
8405 : : static int
8406 : 0 : flow_hw_pattern_validate(struct rte_eth_dev *dev,
8407 : : const struct rte_flow_pattern_template_attr *attr,
8408 : : const struct rte_flow_item items[],
8409 : : uint64_t *item_flags,
8410 : : struct rte_flow_error *error)
8411 : : {
8412 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
8413 : : const struct rte_flow_item *item;
8414 : : const struct rte_flow_item *gtp_item = NULL;
8415 : : const struct rte_flow_item *gre_item = NULL;
8416 : 0 : const struct rte_flow_attr flow_attr = {
8417 : 0 : .ingress = attr->ingress,
8418 : 0 : .egress = attr->egress,
8419 : 0 : .transfer = attr->transfer
8420 : : };
8421 : : int ret, tag_idx;
8422 : : uint32_t tag_bitmap = 0;
8423 : : uint64_t last_item = 0;
8424 : :
8425 [ # # ]: 0 : if (!mlx5_hw_ctx_validate(dev, error))
8426 : 0 : return -rte_errno;
8427 [ # # ]: 0 : if (!attr->ingress && !attr->egress && !attr->transfer)
8428 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ATTR, NULL,
8429 : : "at least one of the direction attributes"
8430 : : " must be specified");
8431 [ # # ]: 0 : if (priv->sh->config.dv_esw_en) {
8432 : : MLX5_ASSERT(priv->master || priv->representor);
8433 [ # # ]: 0 : if (priv->master) {
8434 [ # # ]: 0 : if ((attr->ingress && attr->egress) ||
8435 [ # # ]: 0 : (attr->ingress && attr->transfer) ||
8436 [ # # ]: 0 : (attr->egress && attr->transfer))
8437 : 0 : return rte_flow_error_set(error, EINVAL,
8438 : : RTE_FLOW_ERROR_TYPE_ATTR, NULL,
8439 : : "only one direction attribute at once"
8440 : : " can be used on transfer proxy port");
8441 : : } else {
8442 [ # # ]: 0 : if (attr->transfer)
8443 : 0 : return rte_flow_error_set(error, EINVAL,
8444 : : RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER, NULL,
8445 : : "transfer attribute cannot be used with"
8446 : : " port representors");
8447 [ # # ]: 0 : if (attr->ingress && attr->egress)
8448 : 0 : return rte_flow_error_set(error, EINVAL,
8449 : : RTE_FLOW_ERROR_TYPE_ATTR, NULL,
8450 : : "ingress and egress direction attributes"
8451 : : " cannot be used at the same time on"
8452 : : " port representors");
8453 : : }
8454 : : } else {
8455 [ # # ]: 0 : if (attr->transfer)
8456 : 0 : return rte_flow_error_set(error, EINVAL,
8457 : : RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER, NULL,
8458 : : "transfer attribute cannot be used when"
8459 : : " E-Switch is disabled");
8460 : : }
8461 [ # # ]: 0 : for (item = items; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
8462 : 0 : bool tunnel = *item_flags & MLX5_FLOW_LAYER_TUNNEL;
8463 : :
8464 [ # # # # : 0 : switch ((int)item->type) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # ]
8465 : 0 : case RTE_FLOW_ITEM_TYPE_PTYPE:
8466 : 0 : ret = flow_hw_validate_item_ptype(item, error);
8467 [ # # ]: 0 : if (ret)
8468 : 0 : return ret;
8469 : : last_item = MLX5_FLOW_ITEM_PTYPE;
8470 : : break;
8471 : 0 : case RTE_FLOW_ITEM_TYPE_TAG:
8472 : : {
8473 : 0 : const struct rte_flow_item_tag *tag =
8474 : : (const struct rte_flow_item_tag *)item->spec;
8475 : :
8476 [ # # ]: 0 : if (tag == NULL)
8477 : 0 : return rte_flow_error_set(error, EINVAL,
8478 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8479 : : NULL,
8480 : : "Tag spec is NULL");
8481 [ # # ]: 0 : if (tag->index >= MLX5_FLOW_HW_TAGS_MAX &&
8482 : : tag->index != RTE_PMD_MLX5_LINEAR_HASH_TAG_INDEX)
8483 : 0 : return rte_flow_error_set(error, EINVAL,
8484 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8485 : : NULL,
8486 : : "Invalid tag index");
8487 [ # # ]: 0 : tag_idx = flow_hw_get_reg_id(dev, RTE_FLOW_ITEM_TYPE_TAG, tag->index);
8488 [ # # ]: 0 : if (tag_idx == REG_NON)
8489 : 0 : return rte_flow_error_set(error, EINVAL,
8490 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8491 : : NULL,
8492 : : "Unsupported tag index");
8493 [ # # ]: 0 : if (tag_bitmap & (1 << tag_idx))
8494 : 0 : return rte_flow_error_set(error, EINVAL,
8495 : : RTE_FLOW_ERROR_TYPE_ITEM,
8496 : : NULL,
8497 : : "Duplicated tag index");
8498 : 0 : tag_bitmap |= 1 << tag_idx;
8499 : : last_item = MLX5_FLOW_ITEM_TAG;
8500 : 0 : break;
8501 : : }
8502 : 0 : case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
8503 : : {
8504 : 0 : const struct rte_flow_item_tag *tag =
8505 : : (const struct rte_flow_item_tag *)item->spec;
8506 : 0 : uint16_t regcs = (uint8_t)priv->sh->cdev->config.hca_attr.set_reg_c;
8507 : :
8508 [ # # ]: 0 : if (!((1 << (tag->index - REG_C_0)) & regcs))
8509 : 0 : return rte_flow_error_set(error, EINVAL,
8510 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8511 : : NULL,
8512 : : "Unsupported internal tag index");
8513 [ # # ]: 0 : if (tag_bitmap & (1 << tag->index))
8514 : 0 : return rte_flow_error_set(error, EINVAL,
8515 : : RTE_FLOW_ERROR_TYPE_ITEM,
8516 : : NULL,
8517 : : "Duplicated tag index");
8518 : 0 : tag_bitmap |= 1 << tag->index;
8519 : 0 : break;
8520 : : }
8521 : 0 : case RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT:
8522 [ # # # # ]: 0 : if (attr->ingress && priv->sh->config.repr_matching)
8523 : 0 : return rte_flow_error_set(error, EINVAL,
8524 : : RTE_FLOW_ERROR_TYPE_ITEM, NULL,
8525 : : "represented port item cannot be used"
8526 : : " when ingress attribute is set");
8527 [ # # ]: 0 : if (attr->egress)
8528 : 0 : return rte_flow_error_set(error, EINVAL,
8529 : : RTE_FLOW_ERROR_TYPE_ITEM, NULL,
8530 : : "represented port item cannot be used"
8531 : : " when egress attribute is set");
8532 : : last_item = MLX5_FLOW_ITEM_REPRESENTED_PORT;
8533 : : break;
8534 : 0 : case RTE_FLOW_ITEM_TYPE_META:
8535 : : /* ingress + group 0 is not supported */
8536 : 0 : *item_flags |= MLX5_FLOW_ITEM_METADATA;
8537 : 0 : break;
8538 : : case RTE_FLOW_ITEM_TYPE_METER_COLOR:
8539 : : {
8540 : : int reg = flow_hw_get_reg_id(dev,
8541 : : RTE_FLOW_ITEM_TYPE_METER_COLOR,
8542 : : 0);
8543 [ # # ]: 0 : if (reg == REG_NON)
8544 : 0 : return rte_flow_error_set(error, EINVAL,
8545 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8546 : : NULL,
8547 : : "Unsupported meter color register");
8548 [ # # ]: 0 : if (*item_flags &
8549 : : (MLX5_FLOW_ITEM_QUOTA | MLX5_FLOW_LAYER_ASO_CT))
8550 : 0 : return rte_flow_error_set
8551 : : (error, EINVAL,
8552 : : RTE_FLOW_ERROR_TYPE_ITEM, NULL, "Only one ASO item is supported");
8553 : : last_item = MLX5_FLOW_ITEM_METER_COLOR;
8554 : : break;
8555 : : }
8556 : 0 : case RTE_FLOW_ITEM_TYPE_AGGR_AFFINITY:
8557 : : {
8558 [ # # ]: 0 : if (!priv->sh->lag_rx_port_affinity_en)
8559 : 0 : return rte_flow_error_set(error, EINVAL,
8560 : : RTE_FLOW_ERROR_TYPE_ITEM, NULL,
8561 : : "Unsupported aggregated affinity with Older FW");
8562 [ # # # # : 0 : if ((attr->transfer && priv->fdb_def_rule) || attr->egress)
# # ]
8563 : 0 : return rte_flow_error_set(error, EINVAL,
8564 : : RTE_FLOW_ERROR_TYPE_ITEM, NULL,
8565 : : "Aggregated affinity item not supported"
8566 : : " with egress or transfer"
8567 : : " attribute");
8568 : : last_item = MLX5_FLOW_ITEM_AGGR_AFFINITY;
8569 : : break;
8570 : : }
8571 : 0 : case RTE_FLOW_ITEM_TYPE_GENEVE:
8572 : : last_item = MLX5_FLOW_LAYER_GENEVE;
8573 : 0 : break;
8574 : 0 : case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
8575 : : {
8576 : : last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
8577 : 0 : ret = mlx5_flow_geneve_tlv_option_validate(priv, item,
8578 : : error);
8579 [ # # ]: 0 : if (ret < 0)
8580 : 0 : return ret;
8581 : : break;
8582 : : }
8583 : 0 : case RTE_FLOW_ITEM_TYPE_COMPARE:
8584 : : {
8585 : : last_item = MLX5_FLOW_ITEM_COMPARE;
8586 : 0 : ret = flow_hw_validate_item_compare(item, error);
8587 [ # # ]: 0 : if (ret)
8588 : 0 : return ret;
8589 : : break;
8590 : : }
8591 : 0 : case RTE_FLOW_ITEM_TYPE_ETH:
8592 : 0 : ret = mlx5_flow_validate_item_eth(dev, item,
8593 : : *item_flags,
8594 : : true, error);
8595 [ # # ]: 0 : if (ret < 0)
8596 : 0 : return ret;
8597 [ # # ]: 0 : last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
8598 : : MLX5_FLOW_LAYER_OUTER_L2;
8599 : : break;
8600 : 0 : case RTE_FLOW_ITEM_TYPE_VLAN:
8601 : 0 : ret = mlx5_flow_dv_validate_item_vlan(item, *item_flags,
8602 : : dev, error);
8603 [ # # ]: 0 : if (ret < 0)
8604 : 0 : return ret;
8605 [ # # ]: 0 : last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
8606 : : MLX5_FLOW_LAYER_OUTER_VLAN;
8607 : : break;
8608 : : case RTE_FLOW_ITEM_TYPE_IPV4:
8609 : 0 : tunnel |= mlx5_hw_flow_tunnel_ip_check(last_item,
8610 : : item_flags);
8611 : 0 : ret = mlx5_flow_dv_validate_item_ipv4(dev, item,
8612 : : *item_flags,
8613 : : last_item, 0,
8614 : : &hws_nic_ipv4_mask,
8615 : : error);
8616 [ # # ]: 0 : if (ret)
8617 : 0 : return ret;
8618 [ # # ]: 0 : last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
8619 : : MLX5_FLOW_LAYER_OUTER_L3_IPV4;
8620 : : break;
8621 : : case RTE_FLOW_ITEM_TYPE_IPV6:
8622 : 0 : tunnel |= mlx5_hw_flow_tunnel_ip_check(last_item,
8623 : : item_flags);
8624 : 0 : ret = mlx5_flow_validate_item_ipv6(dev, item,
8625 : : *item_flags,
8626 : : last_item, 0,
8627 : : &hws_nic_ipv6_mask,
8628 : : error);
8629 [ # # ]: 0 : if (ret < 0)
8630 : 0 : return ret;
8631 [ # # ]: 0 : last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
8632 : : MLX5_FLOW_LAYER_OUTER_L3_IPV6;
8633 : : break;
8634 : 0 : case RTE_FLOW_ITEM_TYPE_UDP:
8635 : 0 : ret = mlx5_flow_validate_item_udp(dev, item,
8636 : : *item_flags,
8637 : : 0xff, error);
8638 [ # # ]: 0 : if (ret)
8639 : 0 : return ret;
8640 [ # # ]: 0 : last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
8641 : : MLX5_FLOW_LAYER_OUTER_L4_UDP;
8642 : : break;
8643 : 0 : case RTE_FLOW_ITEM_TYPE_TCP:
8644 : 0 : ret = mlx5_flow_validate_item_tcp
8645 : : (dev, item, *item_flags,
8646 : : 0xff, &nic_tcp_mask, error);
8647 [ # # ]: 0 : if (ret < 0)
8648 : 0 : return ret;
8649 [ # # ]: 0 : last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
8650 : : MLX5_FLOW_LAYER_OUTER_L4_TCP;
8651 : : break;
8652 : 0 : case RTE_FLOW_ITEM_TYPE_GTP:
8653 : : gtp_item = item;
8654 : 0 : ret = mlx5_flow_dv_validate_item_gtp(dev, gtp_item,
8655 : : *item_flags, error);
8656 [ # # ]: 0 : if (ret < 0)
8657 : 0 : return ret;
8658 : : last_item = MLX5_FLOW_LAYER_GTP;
8659 : : break;
8660 : 0 : case RTE_FLOW_ITEM_TYPE_GTP_PSC:
8661 : 0 : ret = mlx5_flow_dv_validate_item_gtp_psc(dev, item,
8662 : : last_item,
8663 : : gtp_item,
8664 : : false, error);
8665 [ # # ]: 0 : if (ret < 0)
8666 : 0 : return ret;
8667 : : last_item = MLX5_FLOW_LAYER_GTP_PSC;
8668 : : break;
8669 : 0 : case RTE_FLOW_ITEM_TYPE_VXLAN:
8670 : 0 : ret = mlx5_flow_validate_item_vxlan(dev, 0, item,
8671 : : *item_flags,
8672 : : false, error);
8673 [ # # ]: 0 : if (ret < 0)
8674 : 0 : return ret;
8675 : : last_item = MLX5_FLOW_LAYER_VXLAN;
8676 : : break;
8677 : 0 : case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
8678 : 0 : ret = mlx5_flow_validate_item_vxlan_gpe(item,
8679 : : *item_flags,
8680 : : dev, error);
8681 [ # # ]: 0 : if (ret < 0)
8682 : 0 : return ret;
8683 : : last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
8684 : : break;
8685 : 0 : case RTE_FLOW_ITEM_TYPE_MPLS:
8686 : 0 : ret = mlx5_flow_validate_item_mpls(dev, item,
8687 : : *item_flags,
8688 : : last_item, error);
8689 [ # # ]: 0 : if (ret < 0)
8690 : 0 : return ret;
8691 : : last_item = MLX5_FLOW_LAYER_MPLS;
8692 : : break;
8693 : 0 : case MLX5_RTE_FLOW_ITEM_TYPE_SQ:
8694 : : case RTE_FLOW_ITEM_TYPE_TX_QUEUE:
8695 : : last_item = MLX5_FLOW_ITEM_SQ;
8696 : 0 : break;
8697 : 0 : case RTE_FLOW_ITEM_TYPE_GRE:
8698 : 0 : ret = mlx5_flow_validate_item_gre(dev, item,
8699 : : *item_flags,
8700 : : 0xff, error);
8701 [ # # ]: 0 : if (ret < 0)
8702 : 0 : return ret;
8703 : : gre_item = item;
8704 : : last_item = MLX5_FLOW_LAYER_GRE;
8705 : : break;
8706 : 0 : case RTE_FLOW_ITEM_TYPE_GRE_KEY:
8707 [ # # ]: 0 : if (!(*item_flags & MLX5_FLOW_LAYER_GRE))
8708 : 0 : return rte_flow_error_set
8709 : : (error, EINVAL,
8710 : : RTE_FLOW_ERROR_TYPE_ITEM, item, "GRE item is missing");
8711 : 0 : ret = mlx5_flow_validate_item_gre_key
8712 : : (dev, item, *item_flags, gre_item, error);
8713 [ # # ]: 0 : if (ret < 0)
8714 : 0 : return ret;
8715 : : last_item = MLX5_FLOW_LAYER_GRE_KEY;
8716 : : break;
8717 : 0 : case RTE_FLOW_ITEM_TYPE_GRE_OPTION:
8718 [ # # ]: 0 : if (!(*item_flags & MLX5_FLOW_LAYER_GRE))
8719 : 0 : return rte_flow_error_set
8720 : : (error, EINVAL,
8721 : : RTE_FLOW_ERROR_TYPE_ITEM, item, "GRE item is missing");
8722 : 0 : ret = mlx5_flow_validate_item_gre_option(dev, item,
8723 : : *item_flags,
8724 : : &flow_attr,
8725 : : gre_item,
8726 : : error);
8727 [ # # ]: 0 : if (ret < 0)
8728 : 0 : return ret;
8729 : : last_item = MLX5_FLOW_LAYER_GRE;
8730 : : break;
8731 : 0 : case RTE_FLOW_ITEM_TYPE_NVGRE:
8732 : 0 : ret = mlx5_flow_validate_item_nvgre(dev, item,
8733 : : *item_flags, 0xff,
8734 : : error);
8735 [ # # ]: 0 : if (ret)
8736 : 0 : return ret;
8737 : : last_item = MLX5_FLOW_LAYER_NVGRE;
8738 : : break;
8739 : 0 : case RTE_FLOW_ITEM_TYPE_ICMP:
8740 : 0 : ret = mlx5_flow_validate_item_icmp(dev, item,
8741 : : *item_flags, 0xff,
8742 : : error);
8743 [ # # ]: 0 : if (ret < 0)
8744 : 0 : return ret;
8745 : : last_item = MLX5_FLOW_LAYER_ICMP;
8746 : : break;
8747 : 0 : case RTE_FLOW_ITEM_TYPE_ICMP6:
8748 : 0 : ret = mlx5_flow_validate_item_icmp6(dev, item,
8749 : : *item_flags, 0xff,
8750 : : error);
8751 [ # # ]: 0 : if (ret < 0)
8752 : 0 : return ret;
8753 : : last_item = MLX5_FLOW_LAYER_ICMP6;
8754 : : break;
8755 : 0 : case RTE_FLOW_ITEM_TYPE_ICMP6_ECHO_REQUEST:
8756 : : case RTE_FLOW_ITEM_TYPE_ICMP6_ECHO_REPLY:
8757 : 0 : ret = mlx5_flow_validate_item_icmp6_echo(dev, item,
8758 : : *item_flags,
8759 : : 0xff, error);
8760 [ # # ]: 0 : if (ret < 0)
8761 : 0 : return ret;
8762 : : last_item = MLX5_FLOW_LAYER_ICMP6;
8763 : : break;
8764 : 0 : case RTE_FLOW_ITEM_TYPE_CONNTRACK:
8765 [ # # ]: 0 : if (*item_flags &
8766 : : (MLX5_FLOW_ITEM_QUOTA | MLX5_FLOW_LAYER_ASO_CT))
8767 : 0 : return rte_flow_error_set
8768 : : (error, EINVAL,
8769 : : RTE_FLOW_ERROR_TYPE_ITEM, NULL, "Only one ASO item is supported");
8770 : 0 : ret = mlx5_flow_dv_validate_item_aso_ct(dev, item,
8771 : : item_flags,
8772 : : error);
8773 [ # # ]: 0 : if (ret < 0)
8774 : 0 : return ret;
8775 : : break;
8776 : 0 : case RTE_FLOW_ITEM_TYPE_QUOTA:
8777 [ # # ]: 0 : if (*item_flags &
8778 : : (MLX5_FLOW_ITEM_METER_COLOR |
8779 : : MLX5_FLOW_LAYER_ASO_CT))
8780 : 0 : return rte_flow_error_set
8781 : : (error, EINVAL,
8782 : : RTE_FLOW_ERROR_TYPE_ITEM, NULL, "Only one ASO item is supported");
8783 : : last_item = MLX5_FLOW_ITEM_QUOTA;
8784 : : break;
8785 : 0 : case RTE_FLOW_ITEM_TYPE_ESP:
8786 : 0 : ret = mlx5_flow_os_validate_item_esp(dev, item,
8787 : : *item_flags, 0xff,
8788 : : error);
8789 [ # # ]: 0 : if (ret < 0)
8790 : 0 : return ret;
8791 : : last_item = MLX5_FLOW_ITEM_ESP;
8792 : : break;
8793 : 0 : case RTE_FLOW_ITEM_TYPE_IPV6_ROUTING_EXT:
8794 : : last_item = tunnel ?
8795 [ # # ]: 0 : MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT :
8796 : : MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT;
8797 : : break;
8798 : 0 : case RTE_FLOW_ITEM_TYPE_FLEX:
8799 : : /* match mlx5dr_definer_conv_items_to_hl() */
8800 : : last_item = tunnel ?
8801 [ # # ]: 0 : MLX5_FLOW_ITEM_INNER_FLEX :
8802 : : MLX5_FLOW_ITEM_OUTER_FLEX;
8803 : : break;
8804 : 0 : case RTE_FLOW_ITEM_TYPE_RANDOM:
8805 : : last_item = MLX5_FLOW_ITEM_RANDOM;
8806 : 0 : break;
8807 : 0 : case RTE_FLOW_ITEM_TYPE_NSH:
8808 : : last_item = MLX5_FLOW_ITEM_NSH;
8809 : : ret = mlx5_hw_validate_item_nsh(dev, item, error);
8810 [ # # ]: 0 : if (ret < 0)
8811 : 0 : return ret;
8812 : : break;
8813 : : case RTE_FLOW_ITEM_TYPE_INTEGRITY:
8814 : : /*
8815 : : * Integrity flow item validation require access to
8816 : : * both item mask and spec.
8817 : : * Current HWS model allows item mask in pattern
8818 : : * template and item spec in flow rule.
8819 : : */
8820 : : break;
8821 : : case RTE_FLOW_ITEM_TYPE_IB_BTH:
8822 : : case RTE_FLOW_ITEM_TYPE_VOID:
8823 : : case RTE_FLOW_ITEM_TYPE_END:
8824 : : break;
8825 : 0 : default:
8826 : 0 : return rte_flow_error_set(error, EINVAL,
8827 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8828 : : NULL,
8829 : : "Unsupported item type");
8830 : : }
8831 : 0 : *item_flags |= last_item;
8832 : : }
8833 : 0 : return 1 + RTE_PTR_DIFF(item, items) / sizeof(item[0]);
8834 : : }
8835 : :
8836 : : /*
8837 : : * Verify that the tested flow patterns fits STE size limit in HWS group.
8838 : : *
8839 : : *
8840 : : * Return values:
8841 : : * 0 : Tested patterns fit STE size limit
8842 : : * -EINVAL : Invalid parameters detected
8843 : : * -E2BIG : Tested patterns exceed STE size limit
8844 : : */
8845 : : static int
8846 : 0 : pattern_template_validate(struct rte_eth_dev *dev,
8847 : : struct rte_flow_pattern_template *pt[],
8848 : : uint32_t pt_num,
8849 : : struct rte_flow_error *error)
8850 : : {
8851 : 0 : struct mlx5_flow_template_table_cfg tbl_cfg = {
8852 : : .attr = {
8853 : : .nb_flows = 64,
8854 : : .insertion_type = RTE_FLOW_TABLE_INSERTION_TYPE_PATTERN,
8855 : : .hash_func = RTE_FLOW_TABLE_HASH_FUNC_DEFAULT,
8856 : : .flow_attr = {
8857 : : .group = 1,
8858 : 0 : .ingress = pt[0]->attr.ingress,
8859 : 0 : .egress = pt[0]->attr.egress,
8860 : 0 : .transfer = pt[0]->attr.transfer
8861 : : }
8862 : : }
8863 : : };
8864 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
8865 : : struct rte_flow_actions_template *action_template;
8866 : : struct rte_flow_template_table *tmpl_tbl;
8867 : : int ret;
8868 : :
8869 [ # # ]: 0 : if (pt[0]->attr.ingress) {
8870 : 0 : action_template =
8871 : 0 : priv->action_template_drop[MLX5DR_TABLE_TYPE_NIC_RX];
8872 [ # # ]: 0 : } else if (pt[0]->attr.egress) {
8873 : 0 : action_template =
8874 : 0 : priv->action_template_drop[MLX5DR_TABLE_TYPE_NIC_TX];
8875 [ # # ]: 0 : } else if (pt[0]->attr.transfer) {
8876 : 0 : action_template =
8877 : 0 : priv->action_template_drop[MLX5DR_TABLE_TYPE_FDB];
8878 : : } else {
8879 : : ret = EINVAL;
8880 : 0 : goto end;
8881 : : }
8882 : :
8883 [ # # ]: 0 : if (pt[0]->item_flags & MLX5_FLOW_ITEM_COMPARE)
8884 : 0 : tbl_cfg.attr.nb_flows = 1;
8885 : 0 : tmpl_tbl = flow_hw_table_create(dev, &tbl_cfg, pt, pt_num,
8886 : : &action_template, 1, error);
8887 [ # # ]: 0 : if (tmpl_tbl) {
8888 : : ret = 0;
8889 : 0 : flow_hw_table_destroy(dev, tmpl_tbl, error);
8890 : : } else {
8891 [ # # # ]: 0 : switch (rte_errno) {
8892 : : case E2BIG:
8893 : : ret = E2BIG;
8894 : : break;
8895 : : case ENOTSUP:
8896 : : ret = EINVAL;
8897 : : break;
8898 : : default:
8899 : : ret = 0;
8900 : : break;
8901 : : }
8902 : : }
8903 : : end:
8904 : : if (ret)
8905 : 0 : rte_flow_error_set(error, ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8906 : : NULL, "failed to validate pattern template");
8907 : 0 : return -ret;
8908 : : }
8909 : :
8910 : : /**
8911 : : * Create flow item template.
8912 : : *
8913 : : * @param[in] dev
8914 : : * Pointer to the rte_eth_dev structure.
8915 : : * @param[in] attr
8916 : : * Pointer to the item template attributes.
8917 : : * @param[in] items
8918 : : * The template item pattern.
8919 : : * @param[out] error
8920 : : * Pointer to error structure.
8921 : : *
8922 : : * @return
8923 : : * Item template pointer on success, NULL otherwise and rte_errno is set.
8924 : : */
8925 : : static struct rte_flow_pattern_template *
8926 : 0 : flow_hw_pattern_template_create(struct rte_eth_dev *dev,
8927 : : const struct rte_flow_pattern_template_attr *attr,
8928 : : const struct rte_flow_item items[],
8929 : : struct rte_flow_error *error)
8930 : : {
8931 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
8932 : : struct rte_flow_pattern_template *it;
8933 : : struct rte_flow_item *copied_items = NULL;
8934 : : const struct rte_flow_item *tmpl_items;
8935 : 0 : uint64_t orig_item_nb, item_flags = 0;
8936 : 0 : struct rte_flow_item port = {
8937 : : .type = RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT,
8938 : : .mask = &rte_flow_item_ethdev_mask,
8939 : : };
8940 : 0 : struct rte_flow_item_tag tag_v = {
8941 : : .data = 0,
8942 : : .index = REG_C_0,
8943 : : };
8944 : 0 : struct rte_flow_item_tag tag_m = {
8945 : : .data = flow_hw_tx_tag_regc_mask(dev),
8946 : : .index = 0xff,
8947 : : };
8948 : 0 : struct rte_flow_item tag = {
8949 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_TAG,
8950 : : .spec = &tag_v,
8951 : : .mask = &tag_m,
8952 : : .last = NULL
8953 : : };
8954 : : int it_items_size;
8955 : : unsigned int i = 0;
8956 : : int rc;
8957 : :
8958 : : /* Validate application items only */
8959 : 0 : rc = flow_hw_pattern_validate(dev, attr, items, &item_flags, error);
8960 [ # # ]: 0 : if (rc < 0)
8961 : : return NULL;
8962 : 0 : orig_item_nb = rc;
8963 [ # # # # ]: 0 : if (priv->sh->config.dv_esw_en &&
8964 : : priv->sh->config.repr_matching &&
8965 [ # # ]: 0 : attr->ingress && !attr->egress && !attr->transfer) {
8966 : 0 : copied_items = flow_hw_prepend_item(items, orig_item_nb, &port, error);
8967 [ # # ]: 0 : if (!copied_items)
8968 : : return NULL;
8969 : : tmpl_items = copied_items;
8970 [ # # # # ]: 0 : } else if (priv->sh->config.dv_esw_en &&
8971 : : priv->sh->config.repr_matching &&
8972 [ # # ]: 0 : !attr->ingress && attr->egress && !attr->transfer) {
8973 [ # # ]: 0 : if (item_flags & MLX5_FLOW_ITEM_SQ) {
8974 : 0 : DRV_LOG(DEBUG, "Port %u omitting implicit REG_C_0 match for egress "
8975 : : "pattern template", dev->data->port_id);
8976 : : tmpl_items = items;
8977 : 0 : goto setup_pattern_template;
8978 : : }
8979 : 0 : copied_items = flow_hw_prepend_item(items, orig_item_nb, &tag, error);
8980 [ # # ]: 0 : if (!copied_items)
8981 : : return NULL;
8982 : : tmpl_items = copied_items;
8983 : : } else {
8984 : : tmpl_items = items;
8985 : : }
8986 : 0 : setup_pattern_template:
8987 : 0 : it = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*it), 0, rte_socket_id());
8988 [ # # ]: 0 : if (!it) {
8989 : 0 : rte_flow_error_set(error, ENOMEM,
8990 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8991 : : NULL,
8992 : : "cannot allocate item template");
8993 : 0 : goto error;
8994 : : }
8995 : 0 : it->attr = *attr;
8996 : 0 : it->item_flags = item_flags;
8997 : 0 : it->orig_item_nb = orig_item_nb;
8998 : 0 : it_items_size = rte_flow_conv(RTE_FLOW_CONV_OP_PATTERN, NULL, 0, tmpl_items, error);
8999 [ # # ]: 0 : if (it_items_size <= 0) {
9000 : 0 : rte_flow_error_set(error, ENOMEM,
9001 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9002 : : NULL,
9003 : : "Failed to determine buffer size for pattern");
9004 : 0 : goto error;
9005 : : }
9006 : 0 : it_items_size = RTE_ALIGN(it_items_size, 16);
9007 : 0 : it->items = mlx5_malloc(MLX5_MEM_ZERO, it_items_size, 0, rte_dev_numa_node(dev->device));
9008 [ # # ]: 0 : if (it->items == NULL) {
9009 : 0 : rte_flow_error_set(error, ENOMEM,
9010 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9011 : : NULL,
9012 : : "Cannot allocate memory for pattern");
9013 : 0 : goto error;
9014 : : }
9015 : 0 : rc = rte_flow_conv(RTE_FLOW_CONV_OP_PATTERN, it->items, it_items_size, tmpl_items, error);
9016 [ # # ]: 0 : if (rc <= 0) {
9017 : 0 : rte_flow_error_set(error, ENOMEM,
9018 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9019 : : NULL,
9020 : : "Failed to store pattern");
9021 : 0 : goto error;
9022 : : }
9023 : 0 : it->mt = mlx5dr_match_template_create(tmpl_items, attr->relaxed_matching);
9024 [ # # ]: 0 : if (!it->mt) {
9025 : 0 : rte_flow_error_set(error, rte_errno,
9026 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9027 : : NULL,
9028 : : "cannot create match template");
9029 : 0 : goto error;
9030 : : }
9031 [ # # ]: 0 : if (copied_items) {
9032 [ # # ]: 0 : if (attr->ingress)
9033 : 0 : it->implicit_port = true;
9034 [ # # ]: 0 : else if (attr->egress)
9035 : 0 : it->implicit_tag = true;
9036 : 0 : mlx5_free(copied_items);
9037 : : copied_items = NULL;
9038 : : }
9039 : : /* Either inner or outer, can't both. */
9040 [ # # ]: 0 : if (it->item_flags & (MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT |
9041 : : MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT)) {
9042 [ # # ]: 0 : if (((it->item_flags & MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT) &&
9043 [ # # ]: 0 : (it->item_flags & MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT)) ||
9044 : 0 : (mlx5_alloc_srh_flex_parser(dev))) {
9045 : 0 : rte_flow_error_set(error, rte_errno,
9046 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9047 : : "cannot create IPv6 routing extension support");
9048 : 0 : goto error;
9049 : : }
9050 : : }
9051 [ # # ]: 0 : if (it->item_flags & MLX5_FLOW_ITEM_FLEX) {
9052 [ # # ]: 0 : for (i = 0; items[i].type != RTE_FLOW_ITEM_TYPE_END; i++) {
9053 : 0 : const struct rte_flow_item_flex *spec = items[i].spec;
9054 : : struct rte_flow_item_flex_handle *handle;
9055 : :
9056 [ # # ]: 0 : if (items[i].type != RTE_FLOW_ITEM_TYPE_FLEX)
9057 : 0 : continue;
9058 : 0 : handle = spec->handle;
9059 [ # # ]: 0 : if (flow_hw_flex_item_acquire(dev, handle,
9060 : 0 : &it->flex_item)) {
9061 : 0 : rte_flow_error_set(error, EINVAL,
9062 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9063 : : NULL, "cannot create hw FLEX item");
9064 : 0 : goto error;
9065 : : }
9066 : : }
9067 : : }
9068 [ # # ]: 0 : if (it->item_flags & MLX5_FLOW_LAYER_GENEVE_OPT) {
9069 [ # # ]: 0 : for (i = 0; items[i].type != RTE_FLOW_ITEM_TYPE_END; i++) {
9070 : 0 : const struct rte_flow_item_geneve_opt *spec =
9071 : : items[i].spec;
9072 : :
9073 [ # # ]: 0 : if (items[i].type != RTE_FLOW_ITEM_TYPE_GENEVE_OPT)
9074 : 0 : continue;
9075 [ # # ]: 0 : if (mlx5_geneve_tlv_option_register(priv, spec,
9076 : 0 : &it->geneve_opt_mng)) {
9077 : 0 : rte_flow_error_set(error, EINVAL,
9078 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9079 : : NULL, "cannot register GENEVE TLV option");
9080 : 0 : goto error;
9081 : : }
9082 : : }
9083 : : }
9084 : 0 : rte_atomic_fetch_add_explicit(&it->refcnt, 1, rte_memory_order_relaxed);
9085 : 0 : rc = pattern_template_validate(dev, &it, 1, error);
9086 [ # # ]: 0 : if (rc)
9087 : 0 : goto error;
9088 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->flow_hw_itt, it, next);
9089 : 0 : return it;
9090 : 0 : error:
9091 [ # # ]: 0 : if (it) {
9092 [ # # ]: 0 : if (it->flex_item)
9093 : 0 : flow_hw_flex_item_release(dev, &it->flex_item);
9094 [ # # ]: 0 : if (it->geneve_opt_mng.nb_options)
9095 : 0 : mlx5_geneve_tlv_options_unregister(priv, &it->geneve_opt_mng);
9096 [ # # ]: 0 : if (it->mt)
9097 : 0 : claim_zero(mlx5dr_match_template_destroy(it->mt));
9098 : 0 : mlx5_free(it->items);
9099 : 0 : mlx5_free(it);
9100 : : }
9101 [ # # ]: 0 : if (copied_items)
9102 : 0 : mlx5_free(copied_items);
9103 : : return NULL;
9104 : : }
9105 : :
9106 : : /**
9107 : : * Destroy flow item template.
9108 : : *
9109 : : * @param[in] dev
9110 : : * Pointer to the rte_eth_dev structure.
9111 : : * @param[in] template
9112 : : * Pointer to the item template to be destroyed.
9113 : : * @param[out] error
9114 : : * Pointer to error structure.
9115 : : *
9116 : : * @return
9117 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
9118 : : */
9119 : : static int
9120 : 0 : flow_hw_pattern_template_destroy(struct rte_eth_dev *dev,
9121 : : struct rte_flow_pattern_template *template,
9122 : : struct rte_flow_error *error __rte_unused)
9123 : : {
9124 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
9125 : :
9126 [ # # ]: 0 : if (rte_atomic_load_explicit(&template->refcnt, rte_memory_order_relaxed) > 1) {
9127 : 0 : DRV_LOG(WARNING, "Item template %p is still in use.",
9128 : : (void *)template);
9129 : 0 : return rte_flow_error_set(error, EBUSY,
9130 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9131 : : NULL,
9132 : : "item template is in use");
9133 : : }
9134 [ # # ]: 0 : if (template->item_flags & (MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT |
9135 : : MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT))
9136 : 0 : mlx5_free_srh_flex_parser(dev);
9137 [ # # ]: 0 : LIST_REMOVE(template, next);
9138 : 0 : flow_hw_flex_item_release(dev, &template->flex_item);
9139 : 0 : mlx5_geneve_tlv_options_unregister(priv, &template->geneve_opt_mng);
9140 : 0 : claim_zero(mlx5dr_match_template_destroy(template->mt));
9141 : 0 : mlx5_free(template->items);
9142 : 0 : mlx5_free(template);
9143 : 0 : return 0;
9144 : : }
9145 : :
9146 : : /*
9147 : : * Get information about HWS pre-configurable resources.
9148 : : *
9149 : : * @param[in] dev
9150 : : * Pointer to the rte_eth_dev structure.
9151 : : * @param[out] port_info
9152 : : * Pointer to port information.
9153 : : * @param[out] queue_info
9154 : : * Pointer to queue information.
9155 : : * @param[out] error
9156 : : * Pointer to error structure.
9157 : : *
9158 : : * @return
9159 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
9160 : : */
9161 : : static int
9162 : 0 : flow_hw_info_get(struct rte_eth_dev *dev,
9163 : : struct rte_flow_port_info *port_info,
9164 : : struct rte_flow_queue_info *queue_info,
9165 : : struct rte_flow_error *error __rte_unused)
9166 : : {
9167 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
9168 : 0 : uint16_t port_id = dev->data->port_id;
9169 : : struct rte_mtr_capabilities mtr_cap;
9170 : : int ret;
9171 : :
9172 : : memset(port_info, 0, sizeof(*port_info));
9173 : : /* Queue size is unlimited from low-level. */
9174 : 0 : port_info->max_nb_queues = UINT32_MAX;
9175 : 0 : queue_info->max_size = UINT32_MAX;
9176 : :
9177 : : memset(&mtr_cap, 0, sizeof(struct rte_mtr_capabilities));
9178 : 0 : ret = rte_mtr_capabilities_get(port_id, &mtr_cap, NULL);
9179 [ # # ]: 0 : if (!ret)
9180 : 0 : port_info->max_nb_meters = mtr_cap.n_max;
9181 : 0 : port_info->max_nb_counters = priv->sh->hws_max_nb_counters;
9182 : 0 : port_info->max_nb_aging_objects = port_info->max_nb_counters;
9183 : 0 : return 0;
9184 : : }
9185 : :
9186 : : /**
9187 : : * Create group callback.
9188 : : *
9189 : : * @param[in] tool_ctx
9190 : : * Pointer to the hash list related context.
9191 : : * @param[in] cb_ctx
9192 : : * Pointer to the group creation context.
9193 : : *
9194 : : * @return
9195 : : * Group entry on success, NULL otherwise and rte_errno is set.
9196 : : */
9197 : : struct mlx5_list_entry *
9198 : 0 : flow_hw_grp_create_cb(void *tool_ctx, void *cb_ctx)
9199 : : {
9200 : : struct mlx5_dev_ctx_shared *sh = tool_ctx;
9201 : : struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9202 : 0 : struct rte_eth_dev *dev = ctx->dev;
9203 : 0 : struct rte_flow_attr *attr = (struct rte_flow_attr *)ctx->data;
9204 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
9205 : 0 : struct mlx5dr_table_attr dr_tbl_attr = {0};
9206 : 0 : struct rte_flow_error *error = ctx->error;
9207 : : struct mlx5_flow_group *grp_data;
9208 : : struct mlx5dr_table *tbl = NULL;
9209 : : struct mlx5dr_action *jump;
9210 : 0 : uint32_t idx = 0;
9211 [ # # # # : 0 : MKSTR(matcher_name, "%s_%s_%u_%u_matcher_list",
# # # # ]
9212 : : attr->transfer ? "FDB" : "NIC", attr->egress ? "egress" : "ingress",
9213 : : attr->group, idx);
9214 : :
9215 : 0 : grp_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_HW_GRP], &idx);
9216 [ # # ]: 0 : if (!grp_data) {
9217 : 0 : rte_flow_error_set(error, ENOMEM,
9218 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9219 : : NULL,
9220 : : "cannot allocate flow table data entry");
9221 : 0 : return NULL;
9222 : : }
9223 : 0 : dr_tbl_attr.level = attr->group;
9224 [ # # ]: 0 : if (attr->transfer)
9225 : 0 : dr_tbl_attr.type = MLX5DR_TABLE_TYPE_FDB;
9226 [ # # ]: 0 : else if (attr->egress)
9227 : 0 : dr_tbl_attr.type = MLX5DR_TABLE_TYPE_NIC_TX;
9228 : : else
9229 : 0 : dr_tbl_attr.type = MLX5DR_TABLE_TYPE_NIC_RX;
9230 : 0 : tbl = mlx5dr_table_create(priv->dr_ctx, &dr_tbl_attr);
9231 [ # # ]: 0 : if (!tbl)
9232 : 0 : goto error;
9233 : 0 : grp_data->tbl = tbl;
9234 [ # # ]: 0 : if (attr->group) {
9235 : : /* Jump action be used by non-root table. */
9236 : 0 : jump = mlx5dr_action_create_dest_table
9237 : : (priv->dr_ctx, tbl,
9238 : 0 : mlx5_hw_act_flag[!!attr->group][dr_tbl_attr.type]);
9239 [ # # ]: 0 : if (!jump)
9240 : 0 : goto error;
9241 : 0 : grp_data->jump.hws_action = jump;
9242 : : /* Jump action be used by root table. */
9243 : 0 : jump = mlx5dr_action_create_dest_table
9244 : : (priv->dr_ctx, tbl,
9245 : : mlx5_hw_act_flag[MLX5_HW_ACTION_FLAG_ROOT]
9246 : 0 : [dr_tbl_attr.type]);
9247 [ # # ]: 0 : if (!jump)
9248 : 0 : goto error;
9249 : 0 : grp_data->jump.root_action = jump;
9250 : : }
9251 : :
9252 : 0 : grp_data->matchers = mlx5_list_create(matcher_name, sh, true,
9253 : : flow_matcher_create_cb,
9254 : : flow_matcher_match_cb,
9255 : : flow_matcher_remove_cb,
9256 : : flow_matcher_clone_cb,
9257 : : flow_matcher_clone_free_cb);
9258 : 0 : grp_data->dev = dev;
9259 : 0 : grp_data->idx = idx;
9260 : 0 : grp_data->group_id = attr->group;
9261 : 0 : grp_data->type = dr_tbl_attr.type;
9262 : 0 : return &grp_data->entry;
9263 : 0 : error:
9264 [ # # ]: 0 : if (grp_data->jump.root_action)
9265 : 0 : mlx5dr_action_destroy(grp_data->jump.root_action);
9266 [ # # ]: 0 : if (grp_data->jump.hws_action)
9267 : 0 : mlx5dr_action_destroy(grp_data->jump.hws_action);
9268 [ # # ]: 0 : if (tbl)
9269 : 0 : mlx5dr_table_destroy(tbl);
9270 [ # # ]: 0 : if (idx)
9271 : 0 : mlx5_ipool_free(sh->ipool[MLX5_IPOOL_HW_GRP], idx);
9272 : 0 : rte_flow_error_set(error, ENOMEM,
9273 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9274 : : NULL,
9275 : : "cannot allocate flow dr table");
9276 : 0 : return NULL;
9277 : : }
9278 : :
9279 : : /**
9280 : : * Remove group callback.
9281 : : *
9282 : : * @param[in] tool_ctx
9283 : : * Pointer to the hash list related context.
9284 : : * @param[in] entry
9285 : : * Pointer to the entry to be removed.
9286 : : */
9287 : : void
9288 : 0 : flow_hw_grp_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
9289 : : {
9290 : : struct mlx5_dev_ctx_shared *sh = tool_ctx;
9291 : : struct mlx5_flow_group *grp_data =
9292 : : container_of(entry, struct mlx5_flow_group, entry);
9293 : :
9294 : : MLX5_ASSERT(entry && sh);
9295 : : /* To use the wrapper glue functions instead. */
9296 [ # # ]: 0 : if (grp_data->jump.hws_action)
9297 : 0 : mlx5dr_action_destroy(grp_data->jump.hws_action);
9298 [ # # ]: 0 : if (grp_data->jump.root_action)
9299 : 0 : mlx5dr_action_destroy(grp_data->jump.root_action);
9300 : 0 : mlx5_list_destroy(grp_data->matchers);
9301 : 0 : mlx5dr_table_destroy(grp_data->tbl);
9302 : 0 : mlx5_ipool_free(sh->ipool[MLX5_IPOOL_HW_GRP], grp_data->idx);
9303 : 0 : }
9304 : :
9305 : : /**
9306 : : * Match group callback.
9307 : : *
9308 : : * @param[in] tool_ctx
9309 : : * Pointer to the hash list related context.
9310 : : * @param[in] entry
9311 : : * Pointer to the group to be matched.
9312 : : * @param[in] cb_ctx
9313 : : * Pointer to the group matching context.
9314 : : *
9315 : : * @return
9316 : : * 0 on matched, 1 on miss matched.
9317 : : */
9318 : : int
9319 : 0 : flow_hw_grp_match_cb(void *tool_ctx __rte_unused, struct mlx5_list_entry *entry,
9320 : : void *cb_ctx)
9321 : : {
9322 : : struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9323 : : struct mlx5_flow_group *grp_data =
9324 : : container_of(entry, struct mlx5_flow_group, entry);
9325 : 0 : struct rte_flow_attr *attr =
9326 : : (struct rte_flow_attr *)ctx->data;
9327 : :
9328 : 0 : return (grp_data->dev != ctx->dev) ||
9329 [ # # ]: 0 : (grp_data->group_id != attr->group) ||
9330 [ # # # # ]: 0 : ((grp_data->type != MLX5DR_TABLE_TYPE_FDB) &&
9331 [ # # ]: 0 : attr->transfer) ||
9332 [ # # ]: 0 : ((grp_data->type != MLX5DR_TABLE_TYPE_NIC_TX) &&
9333 [ # # # # ]: 0 : attr->egress) ||
9334 [ # # ]: 0 : ((grp_data->type != MLX5DR_TABLE_TYPE_NIC_RX) &&
9335 : : attr->ingress);
9336 : : }
9337 : :
9338 : : /**
9339 : : * Clone group entry callback.
9340 : : *
9341 : : * @param[in] tool_ctx
9342 : : * Pointer to the hash list related context.
9343 : : * @param[in] entry
9344 : : * Pointer to the group to be matched.
9345 : : * @param[in] cb_ctx
9346 : : * Pointer to the group matching context.
9347 : : *
9348 : : * @return
9349 : : * 0 on matched, 1 on miss matched.
9350 : : */
9351 : : struct mlx5_list_entry *
9352 : 0 : flow_hw_grp_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
9353 : : void *cb_ctx)
9354 : : {
9355 : : struct mlx5_dev_ctx_shared *sh = tool_ctx;
9356 : : struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9357 : : struct mlx5_flow_group *grp_data;
9358 : 0 : struct rte_flow_error *error = ctx->error;
9359 : 0 : uint32_t idx = 0;
9360 : :
9361 : 0 : grp_data = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_HW_GRP], &idx);
9362 [ # # ]: 0 : if (!grp_data) {
9363 : 0 : rte_flow_error_set(error, ENOMEM,
9364 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9365 : : NULL,
9366 : : "cannot allocate flow table data entry");
9367 : 0 : return NULL;
9368 : : }
9369 : : memcpy(grp_data, oentry, sizeof(*grp_data));
9370 : 0 : grp_data->idx = idx;
9371 : 0 : return &grp_data->entry;
9372 : : }
9373 : :
9374 : : /**
9375 : : * Free cloned group entry callback.
9376 : : *
9377 : : * @param[in] tool_ctx
9378 : : * Pointer to the hash list related context.
9379 : : * @param[in] entry
9380 : : * Pointer to the group to be freed.
9381 : : */
9382 : : void
9383 : 0 : flow_hw_grp_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
9384 : : {
9385 : : struct mlx5_dev_ctx_shared *sh = tool_ctx;
9386 : : struct mlx5_flow_group *grp_data =
9387 : : container_of(entry, struct mlx5_flow_group, entry);
9388 : :
9389 : 0 : mlx5_ipool_free(sh->ipool[MLX5_IPOOL_HW_GRP], grp_data->idx);
9390 : 0 : }
9391 : :
9392 : : /**
9393 : : * Create and cache a vport action for given @p dev port. vport actions
9394 : : * cache is used in HWS with FDB flows.
9395 : : *
9396 : : * This function does not create any function if proxy port for @p dev port
9397 : : * was not configured for HW Steering.
9398 : : *
9399 : : * This function assumes that E-Switch is enabled and PMD is running with
9400 : : * HW Steering configured.
9401 : : *
9402 : : * @param dev
9403 : : * Pointer to Ethernet device which will be the action destination.
9404 : : *
9405 : : * @return
9406 : : * 0 on success, positive value otherwise.
9407 : : */
9408 : : int
9409 : 0 : flow_hw_create_vport_action(struct rte_eth_dev *dev)
9410 : : {
9411 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
9412 : : struct rte_eth_dev *proxy_dev;
9413 : : struct mlx5_priv *proxy_priv;
9414 : 0 : uint16_t port_id = dev->data->port_id;
9415 : 0 : uint16_t proxy_port_id = port_id;
9416 : : int ret;
9417 : :
9418 : 0 : ret = mlx5_flow_pick_transfer_proxy(dev, &proxy_port_id, NULL);
9419 [ # # ]: 0 : if (ret)
9420 : : return ret;
9421 : 0 : proxy_dev = &rte_eth_devices[proxy_port_id];
9422 : 0 : proxy_priv = proxy_dev->data->dev_private;
9423 [ # # ]: 0 : if (!proxy_priv->hw_vport)
9424 : : return 0;
9425 [ # # ]: 0 : if (proxy_priv->hw_vport[port_id]) {
9426 : 0 : DRV_LOG(ERR, "port %u HWS vport action already created",
9427 : : port_id);
9428 : 0 : return -EINVAL;
9429 : : }
9430 : 0 : proxy_priv->hw_vport[port_id] = mlx5dr_action_create_dest_vport
9431 : : (proxy_priv->dr_ctx, priv->dev_port,
9432 : : MLX5DR_ACTION_FLAG_HWS_FDB);
9433 [ # # ]: 0 : if (!proxy_priv->hw_vport[port_id]) {
9434 : 0 : DRV_LOG(ERR, "port %u unable to create HWS vport action",
9435 : : port_id);
9436 : 0 : return -EINVAL;
9437 : : }
9438 : : return 0;
9439 : : }
9440 : :
9441 : : /**
9442 : : * Destroys the vport action associated with @p dev device
9443 : : * from actions' cache.
9444 : : *
9445 : : * This function does not destroy any action if there is no action cached
9446 : : * for @p dev or proxy port was not configured for HW Steering.
9447 : : *
9448 : : * This function assumes that E-Switch is enabled and PMD is running with
9449 : : * HW Steering configured.
9450 : : *
9451 : : * @param dev
9452 : : * Pointer to Ethernet device which will be the action destination.
9453 : : */
9454 : : void
9455 : 0 : flow_hw_destroy_vport_action(struct rte_eth_dev *dev)
9456 : : {
9457 : : struct rte_eth_dev *proxy_dev;
9458 : : struct mlx5_priv *proxy_priv;
9459 : 0 : uint16_t port_id = dev->data->port_id;
9460 : 0 : uint16_t proxy_port_id = port_id;
9461 : :
9462 [ # # ]: 0 : if (mlx5_flow_pick_transfer_proxy(dev, &proxy_port_id, NULL))
9463 : 0 : return;
9464 : 0 : proxy_dev = &rte_eth_devices[proxy_port_id];
9465 : 0 : proxy_priv = proxy_dev->data->dev_private;
9466 [ # # # # ]: 0 : if (!proxy_priv->hw_vport || !proxy_priv->hw_vport[port_id])
9467 : : return;
9468 : 0 : mlx5dr_action_destroy(proxy_priv->hw_vport[port_id]);
9469 : 0 : proxy_priv->hw_vport[port_id] = NULL;
9470 : : }
9471 : :
9472 : : static int
9473 : 0 : flow_hw_create_vport_actions(struct mlx5_priv *priv)
9474 : : {
9475 : : uint16_t port_id;
9476 : :
9477 : : MLX5_ASSERT(!priv->hw_vport);
9478 : 0 : priv->hw_vport = mlx5_malloc(MLX5_MEM_ZERO,
9479 : : sizeof(*priv->hw_vport) * RTE_MAX_ETHPORTS,
9480 : : 0, SOCKET_ID_ANY);
9481 [ # # ]: 0 : if (!priv->hw_vport)
9482 : : return -ENOMEM;
9483 : 0 : DRV_LOG(DEBUG, "port %u :: creating vport actions", priv->dev_data->port_id);
9484 : 0 : DRV_LOG(DEBUG, "port %u :: domain_id=%u", priv->dev_data->port_id, priv->domain_id);
9485 [ # # ]: 0 : MLX5_ETH_FOREACH_DEV(port_id, NULL) {
9486 : 0 : struct mlx5_priv *port_priv = rte_eth_devices[port_id].data->dev_private;
9487 : :
9488 [ # # ]: 0 : if (!port_priv ||
9489 [ # # ]: 0 : port_priv->domain_id != priv->domain_id)
9490 : 0 : continue;
9491 : 0 : DRV_LOG(DEBUG, "port %u :: for port_id=%u, calling mlx5dr_action_create_dest_vport() with ibport=%u",
9492 : : priv->dev_data->port_id, port_id, port_priv->dev_port);
9493 : 0 : priv->hw_vport[port_id] = mlx5dr_action_create_dest_vport
9494 : : (priv->dr_ctx, port_priv->dev_port,
9495 : : MLX5DR_ACTION_FLAG_HWS_FDB);
9496 : 0 : DRV_LOG(DEBUG, "port %u :: priv->hw_vport[%u]=%p",
9497 : : priv->dev_data->port_id, port_id, (void *)priv->hw_vport[port_id]);
9498 [ # # ]: 0 : if (!priv->hw_vport[port_id])
9499 : : return -EINVAL;
9500 : : }
9501 : : return 0;
9502 : : }
9503 : :
9504 : : static void
9505 : 0 : flow_hw_free_vport_actions(struct mlx5_priv *priv)
9506 : : {
9507 : : uint16_t port_id;
9508 : :
9509 [ # # ]: 0 : if (!priv->hw_vport)
9510 : : return;
9511 [ # # ]: 0 : for (port_id = 0; port_id < RTE_MAX_ETHPORTS; ++port_id)
9512 [ # # ]: 0 : if (priv->hw_vport[port_id])
9513 : 0 : mlx5dr_action_destroy(priv->hw_vport[port_id]);
9514 : 0 : mlx5_free(priv->hw_vport);
9515 : 0 : priv->hw_vport = NULL;
9516 : : }
9517 : :
9518 : : static void
9519 : : flow_hw_create_send_to_kernel_actions(struct mlx5_priv *priv __rte_unused)
9520 : : {
9521 : : #ifdef HAVE_MLX5DV_DR_ACTION_CREATE_DEST_ROOT_TABLE
9522 : : int action_flag;
9523 : : int i;
9524 : : bool is_vf_sf_dev = priv->sh->dev_cap.vf || priv->sh->dev_cap.sf;
9525 : :
9526 : : for (i = MLX5DR_TABLE_TYPE_NIC_RX; i < MLX5DR_TABLE_TYPE_MAX; i++) {
9527 : : if ((!priv->sh->config.dv_esw_en || is_vf_sf_dev) &&
9528 : : i == MLX5DR_TABLE_TYPE_FDB)
9529 : : continue;
9530 : : action_flag = mlx5_hw_act_flag[1][i];
9531 : : priv->hw_send_to_kernel[i] =
9532 : : mlx5dr_action_create_dest_root(priv->dr_ctx,
9533 : : MLX5_HW_LOWEST_PRIO_ROOT,
9534 : : action_flag);
9535 : : if (!priv->hw_send_to_kernel[i]) {
9536 : : DRV_LOG(WARNING, "Unable to create HWS send to kernel action");
9537 : : return;
9538 : : }
9539 : : }
9540 : : #endif
9541 : : }
9542 : :
9543 : : static void
9544 : 0 : flow_hw_destroy_send_to_kernel_action(struct mlx5_priv *priv)
9545 : : {
9546 : : int i;
9547 [ # # ]: 0 : for (i = MLX5DR_TABLE_TYPE_NIC_RX; i < MLX5DR_TABLE_TYPE_MAX; i++) {
9548 [ # # ]: 0 : if (priv->hw_send_to_kernel[i]) {
9549 : 0 : mlx5dr_action_destroy(priv->hw_send_to_kernel[i]);
9550 : 0 : priv->hw_send_to_kernel[i] = NULL;
9551 : : }
9552 : : }
9553 : 0 : }
9554 : :
9555 : : static void
9556 : 0 : flow_hw_destroy_nat64_actions(struct mlx5_priv *priv)
9557 : : {
9558 : : uint32_t i;
9559 : :
9560 [ # # ]: 0 : for (i = MLX5DR_TABLE_TYPE_NIC_RX; i < MLX5DR_TABLE_TYPE_MAX; i++) {
9561 [ # # ]: 0 : if (priv->action_nat64[i][RTE_FLOW_NAT64_6TO4]) {
9562 : 0 : (void)mlx5dr_action_destroy(priv->action_nat64[i][RTE_FLOW_NAT64_6TO4]);
9563 : 0 : priv->action_nat64[i][RTE_FLOW_NAT64_6TO4] = NULL;
9564 : : }
9565 [ # # ]: 0 : if (priv->action_nat64[i][RTE_FLOW_NAT64_4TO6]) {
9566 : 0 : (void)mlx5dr_action_destroy(priv->action_nat64[i][RTE_FLOW_NAT64_4TO6]);
9567 : 0 : priv->action_nat64[i][RTE_FLOW_NAT64_4TO6] = NULL;
9568 : : }
9569 : : }
9570 : 0 : }
9571 : :
9572 : : static int
9573 : 0 : flow_hw_create_nat64_actions(struct mlx5_priv *priv, struct rte_flow_error *error)
9574 : : {
9575 : : struct mlx5dr_action_nat64_attr attr;
9576 : : uint8_t regs[MLX5_FLOW_NAT64_REGS_MAX];
9577 : : uint32_t i;
9578 : 0 : const uint32_t flags[MLX5DR_TABLE_TYPE_MAX] = {
9579 : : MLX5DR_ACTION_FLAG_HWS_RX | MLX5DR_ACTION_FLAG_SHARED,
9580 : : MLX5DR_ACTION_FLAG_HWS_TX | MLX5DR_ACTION_FLAG_SHARED,
9581 : : MLX5DR_ACTION_FLAG_HWS_FDB | MLX5DR_ACTION_FLAG_SHARED,
9582 : : };
9583 : : struct mlx5dr_action *act;
9584 : :
9585 : 0 : attr.registers = regs;
9586 : : /* Try to use 3 registers by default. */
9587 : 0 : attr.num_of_registers = MLX5_FLOW_NAT64_REGS_MAX;
9588 [ # # ]: 0 : for (i = 0; i < MLX5_FLOW_NAT64_REGS_MAX; i++) {
9589 : : MLX5_ASSERT(priv->sh->registers.nat64_regs[i] != REG_NON);
9590 : 0 : regs[i] = mlx5_convert_reg_to_field(priv->sh->registers.nat64_regs[i]);
9591 : : }
9592 [ # # ]: 0 : for (i = MLX5DR_TABLE_TYPE_NIC_RX; i < MLX5DR_TABLE_TYPE_MAX; i++) {
9593 [ # # # # ]: 0 : if (i == MLX5DR_TABLE_TYPE_FDB && !priv->sh->config.dv_esw_en)
9594 : 0 : continue;
9595 : 0 : attr.flags = (enum mlx5dr_action_nat64_flags)
9596 : : (MLX5DR_ACTION_NAT64_V6_TO_V4 | MLX5DR_ACTION_NAT64_BACKUP_ADDR);
9597 : 0 : act = mlx5dr_action_create_nat64(priv->dr_ctx, &attr, flags[i]);
9598 [ # # ]: 0 : if (!act)
9599 : 0 : return rte_flow_error_set(error, rte_errno,
9600 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9601 : : "Failed to create v6 to v4 action.");
9602 : 0 : priv->action_nat64[i][RTE_FLOW_NAT64_6TO4] = act;
9603 : 0 : attr.flags = (enum mlx5dr_action_nat64_flags)
9604 : : (MLX5DR_ACTION_NAT64_V4_TO_V6 | MLX5DR_ACTION_NAT64_BACKUP_ADDR);
9605 : 0 : act = mlx5dr_action_create_nat64(priv->dr_ctx, &attr, flags[i]);
9606 [ # # ]: 0 : if (!act)
9607 : 0 : return rte_flow_error_set(error, rte_errno,
9608 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9609 : : "Failed to create v4 to v6 action.");
9610 : 0 : priv->action_nat64[i][RTE_FLOW_NAT64_4TO6] = act;
9611 : : }
9612 : : return 0;
9613 : : }
9614 : :
9615 : : /**
9616 : : * Create an egress pattern template matching on source SQ.
9617 : : *
9618 : : * @param dev
9619 : : * Pointer to Ethernet device.
9620 : : * @param[out] error
9621 : : * Pointer to error structure.
9622 : : *
9623 : : * @return
9624 : : * Pointer to pattern template on success. NULL otherwise, and rte_errno is set.
9625 : : */
9626 : : static struct rte_flow_pattern_template *
9627 : 0 : flow_hw_create_tx_repr_sq_pattern_tmpl(struct rte_eth_dev *dev, struct rte_flow_error *error)
9628 : : {
9629 : 0 : struct rte_flow_pattern_template_attr attr = {
9630 : : .relaxed_matching = 0,
9631 : : .egress = 1,
9632 : : };
9633 : 0 : struct mlx5_rte_flow_item_sq sq_mask = {
9634 : : .queue = UINT32_MAX,
9635 : : };
9636 : 0 : struct rte_flow_item items[] = {
9637 : : {
9638 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_SQ,
9639 : : .mask = &sq_mask,
9640 : : },
9641 : : {
9642 : : .type = RTE_FLOW_ITEM_TYPE_END,
9643 : : },
9644 : : };
9645 : :
9646 : 0 : return flow_hw_pattern_template_create(dev, &attr, items, error);
9647 : : }
9648 : :
9649 : : static __rte_always_inline uint32_t
9650 : : flow_hw_tx_tag_regc_mask(struct rte_eth_dev *dev)
9651 : : {
9652 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
9653 : 0 : uint32_t mask = priv->sh->dv_regc0_mask;
9654 : :
9655 : : /* Mask is verified during device initialization. Sanity checking here. */
9656 : : MLX5_ASSERT(mask != 0);
9657 : : /*
9658 : : * Availability of sufficient number of bits in REG_C_0 is verified on initialization.
9659 : : * Sanity checking here.
9660 : : */
9661 : : MLX5_ASSERT(rte_popcount32(mask) >= rte_popcount32(priv->vport_meta_mask));
9662 : : return mask;
9663 : : }
9664 : :
9665 : : static __rte_always_inline uint32_t
9666 : : flow_hw_tx_tag_regc_value(struct rte_eth_dev *dev)
9667 : : {
9668 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
9669 : : uint32_t tag;
9670 : :
9671 : : /* Mask is verified during device initialization. Sanity checking here. */
9672 : : MLX5_ASSERT(priv->vport_meta_mask != 0);
9673 [ # # ]: 0 : tag = priv->vport_meta_tag >> (rte_bsf32(priv->vport_meta_mask));
9674 : : /*
9675 : : * Availability of sufficient number of bits in REG_C_0 is verified on initialization.
9676 : : * Sanity checking here.
9677 : : */
9678 : : MLX5_ASSERT((tag & priv->sh->dv_regc0_mask) == tag);
9679 : : return tag;
9680 : : }
9681 : :
9682 : : static void
9683 : : flow_hw_update_action_mask(struct rte_flow_action *action,
9684 : : struct rte_flow_action *mask,
9685 : : enum rte_flow_action_type type,
9686 : : void *conf_v,
9687 : : void *conf_m)
9688 : : {
9689 : 0 : action->type = type;
9690 : 0 : action->conf = conf_v;
9691 : 0 : mask->type = type;
9692 : 0 : mask->conf = conf_m;
9693 : : }
9694 : :
9695 : : /**
9696 : : * Create an egress actions template with MODIFY_FIELD action for setting unused REG_C_0 bits
9697 : : * to vport tag and JUMP action to group 1.
9698 : : *
9699 : : * If extended metadata mode is enabled, then MODIFY_FIELD action for copying software metadata
9700 : : * to REG_C_1 is added as well.
9701 : : *
9702 : : * @param dev
9703 : : * Pointer to Ethernet device.
9704 : : * @param[out] error
9705 : : * Pointer to error structure.
9706 : : *
9707 : : * @return
9708 : : * Pointer to actions template on success. NULL otherwise, and rte_errno is set.
9709 : : */
9710 : : static struct rte_flow_actions_template *
9711 : 0 : flow_hw_create_tx_repr_tag_jump_acts_tmpl(struct rte_eth_dev *dev,
9712 : : struct rte_flow_error *error)
9713 : : {
9714 [ # # ]: 0 : uint32_t tag_mask = flow_hw_tx_tag_regc_mask(dev);
9715 : 0 : uint32_t tag_value = flow_hw_tx_tag_regc_value(dev);
9716 : 0 : struct rte_flow_actions_template_attr attr = {
9717 : : .egress = 1,
9718 : : };
9719 [ # # ]: 0 : struct rte_flow_action_modify_field set_tag_v = {
9720 : : .operation = RTE_FLOW_MODIFY_SET,
9721 : : .dst = {
9722 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
9723 : : .tag_index = REG_C_0,
9724 : : .offset = rte_bsf32(tag_mask),
9725 : : },
9726 : : .src = {
9727 : : .field = RTE_FLOW_FIELD_VALUE,
9728 : : },
9729 : : .width = rte_popcount32(tag_mask),
9730 : : };
9731 : 0 : struct rte_flow_action_modify_field set_tag_m = {
9732 : : .operation = RTE_FLOW_MODIFY_SET,
9733 : : .dst = {
9734 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
9735 : : .level = UINT8_MAX,
9736 : : .tag_index = UINT8_MAX,
9737 : : .offset = UINT32_MAX,
9738 : : },
9739 : : .src = {
9740 : : .field = RTE_FLOW_FIELD_VALUE,
9741 : : },
9742 : : .width = UINT32_MAX,
9743 : : };
9744 : 0 : struct rte_flow_action_modify_field copy_metadata_v = {
9745 : : .operation = RTE_FLOW_MODIFY_SET,
9746 : : .dst = {
9747 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
9748 : : .tag_index = REG_C_1,
9749 : : },
9750 : : .src = {
9751 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
9752 : : .tag_index = REG_A,
9753 : : },
9754 : : .width = 32,
9755 : : };
9756 : 0 : struct rte_flow_action_modify_field copy_metadata_m = {
9757 : : .operation = RTE_FLOW_MODIFY_SET,
9758 : : .dst = {
9759 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
9760 : : .level = UINT8_MAX,
9761 : : .tag_index = UINT8_MAX,
9762 : : .offset = UINT32_MAX,
9763 : : },
9764 : : .src = {
9765 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
9766 : : .level = UINT8_MAX,
9767 : : .tag_index = UINT8_MAX,
9768 : : .offset = UINT32_MAX,
9769 : : },
9770 : : .width = UINT32_MAX,
9771 : : };
9772 : 0 : struct rte_flow_action_jump jump_v = {
9773 : : .group = MLX5_HW_LOWEST_USABLE_GROUP,
9774 : : };
9775 : 0 : struct rte_flow_action_jump jump_m = {
9776 : : .group = UINT32_MAX,
9777 : : };
9778 : 0 : struct rte_flow_action actions_v[4] = { { 0 } };
9779 [ # # ]: 0 : struct rte_flow_action actions_m[4] = { { 0 } };
9780 : : unsigned int idx = 0;
9781 : :
9782 : : rte_memcpy(set_tag_v.src.value, &tag_value, sizeof(tag_value));
9783 : : rte_memcpy(set_tag_m.src.value, &tag_mask, sizeof(tag_mask));
9784 : : flow_hw_update_action_mask(&actions_v[idx], &actions_m[idx],
9785 : : RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
9786 : : &set_tag_v, &set_tag_m);
9787 : : idx++;
9788 [ # # ]: 0 : if (MLX5_SH(dev)->config.dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS) {
9789 : : flow_hw_update_action_mask(&actions_v[idx], &actions_m[idx],
9790 : : RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
9791 : : ©_metadata_v, ©_metadata_m);
9792 : : idx++;
9793 : : }
9794 : : flow_hw_update_action_mask(&actions_v[idx], &actions_m[idx], RTE_FLOW_ACTION_TYPE_JUMP,
9795 : : &jump_v, &jump_m);
9796 : 0 : idx++;
9797 : : flow_hw_update_action_mask(&actions_v[idx], &actions_m[idx], RTE_FLOW_ACTION_TYPE_END,
9798 : : NULL, NULL);
9799 : : idx++;
9800 : : MLX5_ASSERT(idx <= RTE_DIM(actions_v));
9801 : 0 : return flow_hw_actions_template_create(dev, &attr, actions_v, actions_m, error);
9802 : : }
9803 : :
9804 : : static void
9805 : 0 : flow_hw_cleanup_tx_repr_tagging(struct rte_eth_dev *dev)
9806 : : {
9807 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
9808 : :
9809 [ # # ]: 0 : if (priv->hw_tx_repr_tagging_tbl) {
9810 : 0 : flow_hw_table_destroy(dev, priv->hw_tx_repr_tagging_tbl, NULL);
9811 : 0 : priv->hw_tx_repr_tagging_tbl = NULL;
9812 : : }
9813 [ # # ]: 0 : if (priv->hw_tx_repr_tagging_at) {
9814 : 0 : flow_hw_actions_template_destroy(dev, priv->hw_tx_repr_tagging_at, NULL);
9815 : 0 : priv->hw_tx_repr_tagging_at = NULL;
9816 : : }
9817 [ # # ]: 0 : if (priv->hw_tx_repr_tagging_pt) {
9818 : 0 : flow_hw_pattern_template_destroy(dev, priv->hw_tx_repr_tagging_pt, NULL);
9819 : 0 : priv->hw_tx_repr_tagging_pt = NULL;
9820 : : }
9821 : 0 : }
9822 : :
9823 : : /**
9824 : : * Setup templates and table used to create default Tx flow rules. These default rules
9825 : : * allow for matching Tx representor traffic using a vport tag placed in unused bits of
9826 : : * REG_C_0 register.
9827 : : *
9828 : : * @param dev
9829 : : * Pointer to Ethernet device.
9830 : : * @param[out] error
9831 : : * Pointer to error structure.
9832 : : *
9833 : : * @return
9834 : : * 0 on success, negative errno value otherwise.
9835 : : */
9836 : : static int
9837 : 0 : flow_hw_setup_tx_repr_tagging(struct rte_eth_dev *dev, struct rte_flow_error *error)
9838 : : {
9839 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
9840 : 0 : struct rte_flow_template_table_attr attr = {
9841 : : .flow_attr = {
9842 : : .group = 0,
9843 : : .priority = MLX5_HW_LOWEST_PRIO_ROOT,
9844 : : .egress = 1,
9845 : : },
9846 : : .nb_flows = MLX5_HW_CTRL_FLOW_NB_RULES,
9847 : : };
9848 : 0 : struct mlx5_flow_template_table_cfg cfg = {
9849 : : .attr = attr,
9850 : : .external = false,
9851 : : };
9852 : :
9853 : : MLX5_ASSERT(priv->sh->config.dv_esw_en);
9854 : : MLX5_ASSERT(priv->sh->config.repr_matching);
9855 : 0 : priv->hw_tx_repr_tagging_pt =
9856 : 0 : flow_hw_create_tx_repr_sq_pattern_tmpl(dev, error);
9857 [ # # ]: 0 : if (!priv->hw_tx_repr_tagging_pt)
9858 : 0 : goto err;
9859 : 0 : priv->hw_tx_repr_tagging_at =
9860 : 0 : flow_hw_create_tx_repr_tag_jump_acts_tmpl(dev, error);
9861 [ # # ]: 0 : if (!priv->hw_tx_repr_tagging_at)
9862 : 0 : goto err;
9863 : 0 : priv->hw_tx_repr_tagging_tbl = flow_hw_table_create(dev, &cfg,
9864 : : &priv->hw_tx_repr_tagging_pt, 1,
9865 : : &priv->hw_tx_repr_tagging_at, 1,
9866 : : error);
9867 [ # # ]: 0 : if (!priv->hw_tx_repr_tagging_tbl)
9868 : 0 : goto err;
9869 : : return 0;
9870 : 0 : err:
9871 : 0 : flow_hw_cleanup_tx_repr_tagging(dev);
9872 : 0 : return -rte_errno;
9873 : : }
9874 : :
9875 : : static uint32_t
9876 : : flow_hw_esw_mgr_regc_marker_mask(struct rte_eth_dev *dev)
9877 : : {
9878 : 0 : uint32_t mask = MLX5_SH(dev)->dv_regc0_mask;
9879 : :
9880 : : /* Mask is verified during device initialization. */
9881 : : MLX5_ASSERT(mask != 0);
9882 : : return mask;
9883 : : }
9884 : :
9885 : : static uint32_t
9886 : : flow_hw_esw_mgr_regc_marker(struct rte_eth_dev *dev)
9887 : : {
9888 : 0 : uint32_t mask = MLX5_SH(dev)->dv_regc0_mask;
9889 : :
9890 : : /* Mask is verified during device initialization. */
9891 : : MLX5_ASSERT(mask != 0);
9892 : 0 : return RTE_BIT32(rte_bsf32(mask));
9893 : : }
9894 : :
9895 : : /**
9896 : : * Creates a flow pattern template used to match on E-Switch Manager.
9897 : : * This template is used to set up a table for SQ miss default flow.
9898 : : *
9899 : : * @param dev
9900 : : * Pointer to Ethernet device.
9901 : : * @param error
9902 : : * Pointer to error structure.
9903 : : *
9904 : : * @return
9905 : : * Pointer to flow pattern template on success, NULL otherwise.
9906 : : */
9907 : : static struct rte_flow_pattern_template *
9908 : 0 : flow_hw_create_ctrl_esw_mgr_pattern_template(struct rte_eth_dev *dev,
9909 : : struct rte_flow_error *error)
9910 : : {
9911 : 0 : struct rte_flow_pattern_template_attr attr = {
9912 : : .relaxed_matching = 0,
9913 : : .transfer = 1,
9914 : : };
9915 : 0 : struct rte_flow_item_ethdev port_spec = {
9916 : : .port_id = MLX5_REPRESENTED_PORT_ESW_MGR,
9917 : : };
9918 : 0 : struct rte_flow_item_ethdev port_mask = {
9919 : : .port_id = UINT16_MAX,
9920 : : };
9921 : 0 : struct mlx5_rte_flow_item_sq sq_mask = {
9922 : : .queue = UINT32_MAX,
9923 : : };
9924 : 0 : struct rte_flow_item items[] = {
9925 : : {
9926 : : .type = RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT,
9927 : : .spec = &port_spec,
9928 : : .mask = &port_mask,
9929 : : },
9930 : : {
9931 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_SQ,
9932 : : .mask = &sq_mask,
9933 : : },
9934 : : {
9935 : : .type = RTE_FLOW_ITEM_TYPE_END,
9936 : : },
9937 : : };
9938 : :
9939 : 0 : return flow_hw_pattern_template_create(dev, &attr, items, error);
9940 : : }
9941 : :
9942 : : /**
9943 : : * Creates a flow pattern template used to match REG_C_0 and a SQ.
9944 : : * Matching on REG_C_0 is set up to match on all bits usable by user-space.
9945 : : * If traffic was sent from E-Switch Manager, then all usable bits will be set to 0,
9946 : : * except the least significant bit, which will be set to 1.
9947 : : *
9948 : : * This template is used to set up a table for SQ miss default flow.
9949 : : *
9950 : : * @param dev
9951 : : * Pointer to Ethernet device.
9952 : : * @param error
9953 : : * Pointer to error structure.
9954 : : *
9955 : : * @return
9956 : : * Pointer to flow pattern template on success, NULL otherwise.
9957 : : */
9958 : : static struct rte_flow_pattern_template *
9959 : 0 : flow_hw_create_ctrl_regc_sq_pattern_template(struct rte_eth_dev *dev,
9960 : : struct rte_flow_error *error)
9961 : : {
9962 : 0 : struct rte_flow_pattern_template_attr attr = {
9963 : : .relaxed_matching = 0,
9964 : : .transfer = 1,
9965 : : };
9966 : 0 : struct rte_flow_item_tag reg_c0_spec = {
9967 : : .index = (uint8_t)REG_C_0,
9968 : : };
9969 : 0 : struct rte_flow_item_tag reg_c0_mask = {
9970 : : .index = 0xff,
9971 : : .data = flow_hw_esw_mgr_regc_marker_mask(dev),
9972 : : };
9973 : 0 : struct mlx5_rte_flow_item_sq queue_mask = {
9974 : : .queue = UINT32_MAX,
9975 : : };
9976 : 0 : struct rte_flow_item items[] = {
9977 : : {
9978 : : .type = (enum rte_flow_item_type)
9979 : : MLX5_RTE_FLOW_ITEM_TYPE_TAG,
9980 : : .spec = ®_c0_spec,
9981 : : .mask = ®_c0_mask,
9982 : : },
9983 : : {
9984 : : .type = (enum rte_flow_item_type)
9985 : : MLX5_RTE_FLOW_ITEM_TYPE_SQ,
9986 : : .mask = &queue_mask,
9987 : : },
9988 : : {
9989 : : .type = RTE_FLOW_ITEM_TYPE_END,
9990 : : },
9991 : : };
9992 : :
9993 : 0 : return flow_hw_pattern_template_create(dev, &attr, items, error);
9994 : : }
9995 : :
9996 : : /**
9997 : : * Creates a flow pattern template with unmasked represented port matching.
9998 : : * This template is used to set up a table for default transfer flows
9999 : : * directing packets to group 1.
10000 : : *
10001 : : * @param dev
10002 : : * Pointer to Ethernet device.
10003 : : * @param error
10004 : : * Pointer to error structure.
10005 : : *
10006 : : * @return
10007 : : * Pointer to flow pattern template on success, NULL otherwise.
10008 : : */
10009 : : static struct rte_flow_pattern_template *
10010 : 0 : flow_hw_create_ctrl_port_pattern_template(struct rte_eth_dev *dev,
10011 : : struct rte_flow_error *error)
10012 : : {
10013 : 0 : struct rte_flow_pattern_template_attr attr = {
10014 : : .relaxed_matching = 0,
10015 : : .transfer = 1,
10016 : : };
10017 : 0 : struct rte_flow_item_ethdev port_mask = {
10018 : : .port_id = UINT16_MAX,
10019 : : };
10020 : 0 : struct rte_flow_item items[] = {
10021 : : {
10022 : : .type = RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT,
10023 : : .mask = &port_mask,
10024 : : },
10025 : : {
10026 : : .type = RTE_FLOW_ITEM_TYPE_END,
10027 : : },
10028 : : };
10029 : :
10030 : 0 : return flow_hw_pattern_template_create(dev, &attr, items, error);
10031 : : }
10032 : :
10033 : : /*
10034 : : * Creating a flow pattern template with all ETH packets matching.
10035 : : * This template is used to set up a table for default Tx copy (Tx metadata
10036 : : * to REG_C_1) flow rule usage.
10037 : : *
10038 : : * @param dev
10039 : : * Pointer to Ethernet device.
10040 : : * @param error
10041 : : * Pointer to error structure.
10042 : : *
10043 : : * @return
10044 : : * Pointer to flow pattern template on success, NULL otherwise.
10045 : : */
10046 : : static struct rte_flow_pattern_template *
10047 : 0 : flow_hw_create_tx_default_mreg_copy_pattern_template(struct rte_eth_dev *dev,
10048 : : struct rte_flow_error *error)
10049 : : {
10050 : 0 : struct rte_flow_pattern_template_attr tx_pa_attr = {
10051 : : .relaxed_matching = 0,
10052 : : .egress = 1,
10053 : : };
10054 : 0 : struct rte_flow_item_eth promisc = {
10055 : : .hdr.dst_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
10056 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
10057 : : .hdr.ether_type = 0,
10058 : : };
10059 : 0 : struct rte_flow_item eth_all[] = {
10060 : : [0] = {
10061 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
10062 : : .spec = &promisc,
10063 : : .mask = &promisc,
10064 : : },
10065 : : [1] = {
10066 : : .type = RTE_FLOW_ITEM_TYPE_END,
10067 : : },
10068 : : };
10069 : :
10070 : 0 : return flow_hw_pattern_template_create(dev, &tx_pa_attr, eth_all, error);
10071 : : }
10072 : :
10073 : : /*
10074 : : * Creating a flow pattern template with all LACP packets matching, only for NIC
10075 : : * ingress domain.
10076 : : *
10077 : : * @param dev
10078 : : * Pointer to Ethernet device.
10079 : : * @param error
10080 : : * Pointer to error structure.
10081 : : *
10082 : : * @return
10083 : : * Pointer to flow pattern template on success, NULL otherwise.
10084 : : */
10085 : : static struct rte_flow_pattern_template *
10086 : 0 : flow_hw_create_lacp_rx_pattern_template(struct rte_eth_dev *dev, struct rte_flow_error *error)
10087 : : {
10088 : 0 : struct rte_flow_pattern_template_attr pa_attr = {
10089 : : .relaxed_matching = 0,
10090 : : .ingress = 1,
10091 : : };
10092 : 0 : struct rte_flow_item_eth lacp_mask = {
10093 : : .dst.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
10094 : : .src.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
10095 : : .type = 0xFFFF,
10096 : : };
10097 : 0 : struct rte_flow_item eth_all[] = {
10098 : : [0] = {
10099 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
10100 : : .mask = &lacp_mask,
10101 : : },
10102 : : [1] = {
10103 : : .type = RTE_FLOW_ITEM_TYPE_END,
10104 : : },
10105 : : };
10106 : 0 : return flow_hw_pattern_template_create(dev, &pa_attr, eth_all, error);
10107 : : }
10108 : :
10109 : : /**
10110 : : * Creates a flow actions template with modify field action and masked jump action.
10111 : : * Modify field action sets the least significant bit of REG_C_0 (usable by user-space)
10112 : : * to 1, meaning that packet was originated from E-Switch Manager. Jump action
10113 : : * transfers steering to group 1.
10114 : : *
10115 : : * @param dev
10116 : : * Pointer to Ethernet device.
10117 : : * @param error
10118 : : * Pointer to error structure.
10119 : : *
10120 : : * @return
10121 : : * Pointer to flow actions template on success, NULL otherwise.
10122 : : */
10123 : : static struct rte_flow_actions_template *
10124 : 0 : flow_hw_create_ctrl_regc_jump_actions_template(struct rte_eth_dev *dev,
10125 : : struct rte_flow_error *error)
10126 : : {
10127 [ # # ]: 0 : uint32_t marker_mask = flow_hw_esw_mgr_regc_marker_mask(dev);
10128 : 0 : uint32_t marker_bits = flow_hw_esw_mgr_regc_marker(dev);
10129 : 0 : struct rte_flow_actions_template_attr attr = {
10130 : : .transfer = 1,
10131 : : };
10132 [ # # ]: 0 : struct rte_flow_action_modify_field set_reg_v = {
10133 : : .operation = RTE_FLOW_MODIFY_SET,
10134 : : .dst = {
10135 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
10136 : : .tag_index = REG_C_0,
10137 : : },
10138 : : .src = {
10139 : : .field = RTE_FLOW_FIELD_VALUE,
10140 : : },
10141 : : .width = rte_popcount32(marker_mask),
10142 : : };
10143 : 0 : struct rte_flow_action_modify_field set_reg_m = {
10144 : : .operation = RTE_FLOW_MODIFY_SET,
10145 : : .dst = {
10146 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
10147 : : .level = UINT8_MAX,
10148 : : .tag_index = UINT8_MAX,
10149 : : .offset = UINT32_MAX,
10150 : : },
10151 : : .src = {
10152 : : .field = RTE_FLOW_FIELD_VALUE,
10153 : : },
10154 : : .width = UINT32_MAX,
10155 : : };
10156 : 0 : struct rte_flow_action_jump jump_v = {
10157 : : .group = MLX5_HW_LOWEST_USABLE_GROUP,
10158 : : };
10159 : 0 : struct rte_flow_action_jump jump_m = {
10160 : : .group = UINT32_MAX,
10161 : : };
10162 : 0 : struct rte_flow_action actions_v[] = {
10163 : : {
10164 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
10165 : : .conf = &set_reg_v,
10166 : : },
10167 : : {
10168 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
10169 : : .conf = &jump_v,
10170 : : },
10171 : : {
10172 : : .type = RTE_FLOW_ACTION_TYPE_END,
10173 : : }
10174 : : };
10175 : 0 : struct rte_flow_action actions_m[] = {
10176 : : {
10177 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
10178 : : .conf = &set_reg_m,
10179 : : },
10180 : : {
10181 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
10182 : : .conf = &jump_m,
10183 : : },
10184 : : {
10185 : : .type = RTE_FLOW_ACTION_TYPE_END,
10186 : : }
10187 : : };
10188 : :
10189 [ # # ]: 0 : set_reg_v.dst.offset = rte_bsf32(marker_mask);
10190 : : rte_memcpy(set_reg_v.src.value, &marker_bits, sizeof(marker_bits));
10191 : : rte_memcpy(set_reg_m.src.value, &marker_mask, sizeof(marker_mask));
10192 : 0 : return flow_hw_actions_template_create(dev, &attr, actions_v, actions_m, error);
10193 : : }
10194 : :
10195 : : /**
10196 : : * Creates a flow actions template with an unmasked JUMP action. Flows
10197 : : * based on this template will perform a jump to some group. This template
10198 : : * is used to set up tables for control flows.
10199 : : *
10200 : : * @param dev
10201 : : * Pointer to Ethernet device.
10202 : : * @param group
10203 : : * Destination group for this action template.
10204 : : * @param error
10205 : : * Pointer to error structure.
10206 : : *
10207 : : * @return
10208 : : * Pointer to flow actions template on success, NULL otherwise.
10209 : : */
10210 : : static struct rte_flow_actions_template *
10211 : 0 : flow_hw_create_ctrl_jump_actions_template(struct rte_eth_dev *dev,
10212 : : uint32_t group,
10213 : : struct rte_flow_error *error)
10214 : : {
10215 : 0 : struct rte_flow_actions_template_attr attr = {
10216 : : .transfer = 1,
10217 : : };
10218 : 0 : struct rte_flow_action_jump jump_v = {
10219 : : .group = group,
10220 : : };
10221 : 0 : struct rte_flow_action_jump jump_m = {
10222 : : .group = UINT32_MAX,
10223 : : };
10224 : 0 : struct rte_flow_action actions_v[] = {
10225 : : {
10226 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
10227 : : .conf = &jump_v,
10228 : : },
10229 : : {
10230 : : .type = RTE_FLOW_ACTION_TYPE_END,
10231 : : }
10232 : : };
10233 : 0 : struct rte_flow_action actions_m[] = {
10234 : : {
10235 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
10236 : : .conf = &jump_m,
10237 : : },
10238 : : {
10239 : : .type = RTE_FLOW_ACTION_TYPE_END,
10240 : : }
10241 : : };
10242 : :
10243 : 0 : return flow_hw_actions_template_create(dev, &attr, actions_v,
10244 : : actions_m, error);
10245 : : }
10246 : :
10247 : : /**
10248 : : * Creates a flow action template with a unmasked REPRESENTED_PORT action.
10249 : : * It is used to create control flow tables.
10250 : : *
10251 : : * @param dev
10252 : : * Pointer to Ethernet device.
10253 : : * @param error
10254 : : * Pointer to error structure.
10255 : : *
10256 : : * @return
10257 : : * Pointer to flow action template on success, NULL otherwise.
10258 : : */
10259 : : static struct rte_flow_actions_template *
10260 : 0 : flow_hw_create_ctrl_port_actions_template(struct rte_eth_dev *dev,
10261 : : struct rte_flow_error *error)
10262 : : {
10263 : 0 : struct rte_flow_actions_template_attr attr = {
10264 : : .transfer = 1,
10265 : : };
10266 : 0 : struct rte_flow_action_ethdev port_v = {
10267 : : .port_id = 0,
10268 : : };
10269 : 0 : struct rte_flow_action actions_v[] = {
10270 : : {
10271 : : .type = RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT,
10272 : : .conf = &port_v,
10273 : : },
10274 : : {
10275 : : .type = RTE_FLOW_ACTION_TYPE_END,
10276 : : }
10277 : : };
10278 : 0 : struct rte_flow_action_ethdev port_m = {
10279 : : .port_id = 0,
10280 : : };
10281 : 0 : struct rte_flow_action actions_m[] = {
10282 : : {
10283 : : .type = RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT,
10284 : : .conf = &port_m,
10285 : : },
10286 : : {
10287 : : .type = RTE_FLOW_ACTION_TYPE_END,
10288 : : }
10289 : : };
10290 : :
10291 : 0 : return flow_hw_actions_template_create(dev, &attr, actions_v, actions_m, error);
10292 : : }
10293 : :
10294 : : /*
10295 : : * Creating an actions template to use header modify action for register
10296 : : * copying. This template is used to set up a table for copy flow.
10297 : : *
10298 : : * @param dev
10299 : : * Pointer to Ethernet device.
10300 : : * @param error
10301 : : * Pointer to error structure.
10302 : : *
10303 : : * @return
10304 : : * Pointer to flow actions template on success, NULL otherwise.
10305 : : */
10306 : : static struct rte_flow_actions_template *
10307 : 0 : flow_hw_create_tx_default_mreg_copy_actions_template(struct rte_eth_dev *dev,
10308 : : struct rte_flow_error *error)
10309 : : {
10310 : 0 : struct rte_flow_actions_template_attr tx_act_attr = {
10311 : : .egress = 1,
10312 : : };
10313 : 0 : const struct rte_flow_action_modify_field mreg_action = {
10314 : : .operation = RTE_FLOW_MODIFY_SET,
10315 : : .dst = {
10316 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
10317 : : .tag_index = REG_C_1,
10318 : : },
10319 : : .src = {
10320 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
10321 : : .tag_index = REG_A,
10322 : : },
10323 : : .width = 32,
10324 : : };
10325 : 0 : const struct rte_flow_action_modify_field mreg_mask = {
10326 : : .operation = RTE_FLOW_MODIFY_SET,
10327 : : .dst = {
10328 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
10329 : : .level = UINT8_MAX,
10330 : : .tag_index = UINT8_MAX,
10331 : : .offset = UINT32_MAX,
10332 : : },
10333 : : .src = {
10334 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
10335 : : .level = UINT8_MAX,
10336 : : .tag_index = UINT8_MAX,
10337 : : .offset = UINT32_MAX,
10338 : : },
10339 : : .width = UINT32_MAX,
10340 : : };
10341 : 0 : const struct rte_flow_action_jump jump_action = {
10342 : : .group = 1,
10343 : : };
10344 : 0 : const struct rte_flow_action_jump jump_mask = {
10345 : : .group = UINT32_MAX,
10346 : : };
10347 : 0 : const struct rte_flow_action actions[] = {
10348 : : [0] = {
10349 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
10350 : : .conf = &mreg_action,
10351 : : },
10352 : : [1] = {
10353 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
10354 : : .conf = &jump_action,
10355 : : },
10356 : : [2] = {
10357 : : .type = RTE_FLOW_ACTION_TYPE_END,
10358 : : },
10359 : : };
10360 : 0 : const struct rte_flow_action masks[] = {
10361 : : [0] = {
10362 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
10363 : : .conf = &mreg_mask,
10364 : : },
10365 : : [1] = {
10366 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
10367 : : .conf = &jump_mask,
10368 : : },
10369 : : [2] = {
10370 : : .type = RTE_FLOW_ACTION_TYPE_END,
10371 : : },
10372 : : };
10373 : :
10374 : 0 : return flow_hw_actions_template_create(dev, &tx_act_attr, actions,
10375 : : masks, error);
10376 : : }
10377 : :
10378 : : /*
10379 : : * Creating an actions template to use default miss to re-route packets to the
10380 : : * kernel driver stack.
10381 : : * On root table, only DEFAULT_MISS action can be used.
10382 : : *
10383 : : * @param dev
10384 : : * Pointer to Ethernet device.
10385 : : * @param error
10386 : : * Pointer to error structure.
10387 : : *
10388 : : * @return
10389 : : * Pointer to flow actions template on success, NULL otherwise.
10390 : : */
10391 : : static struct rte_flow_actions_template *
10392 : 0 : flow_hw_create_lacp_rx_actions_template(struct rte_eth_dev *dev, struct rte_flow_error *error)
10393 : : {
10394 : 0 : struct rte_flow_actions_template_attr act_attr = {
10395 : : .ingress = 1,
10396 : : };
10397 : 0 : const struct rte_flow_action actions[] = {
10398 : : [0] = {
10399 : : .type = (enum rte_flow_action_type)
10400 : : MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS,
10401 : : },
10402 : : [1] = {
10403 : : .type = RTE_FLOW_ACTION_TYPE_END,
10404 : : },
10405 : : };
10406 : :
10407 : 0 : return flow_hw_actions_template_create(dev, &act_attr, actions, actions, error);
10408 : : }
10409 : :
10410 : : /**
10411 : : * Creates a control flow table used to transfer traffic from E-Switch Manager
10412 : : * and TX queues from group 0 to group 1.
10413 : : *
10414 : : * @param dev
10415 : : * Pointer to Ethernet device.
10416 : : * @param it
10417 : : * Pointer to flow pattern template.
10418 : : * @param at
10419 : : * Pointer to flow actions template.
10420 : : * @param error
10421 : : * Pointer to error structure.
10422 : : *
10423 : : * @return
10424 : : * Pointer to flow table on success, NULL otherwise.
10425 : : */
10426 : : static struct rte_flow_template_table*
10427 : 0 : flow_hw_create_ctrl_sq_miss_root_table(struct rte_eth_dev *dev,
10428 : : struct rte_flow_pattern_template *it,
10429 : : struct rte_flow_actions_template *at,
10430 : : struct rte_flow_error *error)
10431 : : {
10432 : 0 : struct rte_flow_template_table_attr attr = {
10433 : : .flow_attr = {
10434 : : .group = 0,
10435 : : .priority = MLX5_HW_LOWEST_PRIO_ROOT,
10436 : : .ingress = 0,
10437 : : .egress = 0,
10438 : : .transfer = 1,
10439 : : },
10440 : : .nb_flows = MLX5_HW_CTRL_FLOW_NB_RULES,
10441 : : };
10442 : 0 : struct mlx5_flow_template_table_cfg cfg = {
10443 : : .attr = attr,
10444 : : .external = false,
10445 : : };
10446 : :
10447 : 0 : return flow_hw_table_create(dev, &cfg, &it, 1, &at, 1, error);
10448 : : }
10449 : :
10450 : :
10451 : : /**
10452 : : * Creates a control flow table used to transfer traffic from E-Switch Manager
10453 : : * and TX queues from group 0 to group 1.
10454 : : *
10455 : : * @param dev
10456 : : * Pointer to Ethernet device.
10457 : : * @param it
10458 : : * Pointer to flow pattern template.
10459 : : * @param at
10460 : : * Pointer to flow actions template.
10461 : : * @param error
10462 : : * Pointer to error structure.
10463 : : *
10464 : : * @return
10465 : : * Pointer to flow table on success, NULL otherwise.
10466 : : */
10467 : : static struct rte_flow_template_table*
10468 : 0 : flow_hw_create_ctrl_sq_miss_table(struct rte_eth_dev *dev,
10469 : : struct rte_flow_pattern_template *it,
10470 : : struct rte_flow_actions_template *at,
10471 : : struct rte_flow_error *error)
10472 : : {
10473 : 0 : struct rte_flow_template_table_attr attr = {
10474 : : .flow_attr = {
10475 : : .group = 1,
10476 : : .priority = MLX5_HW_LOWEST_PRIO_NON_ROOT,
10477 : : .ingress = 0,
10478 : : .egress = 0,
10479 : : .transfer = 1,
10480 : : },
10481 : : .nb_flows = MLX5_HW_CTRL_FLOW_NB_RULES,
10482 : : };
10483 : 0 : struct mlx5_flow_template_table_cfg cfg = {
10484 : : .attr = attr,
10485 : : .external = false,
10486 : : };
10487 : :
10488 : 0 : return flow_hw_table_create(dev, &cfg, &it, 1, &at, 1, error);
10489 : : }
10490 : :
10491 : : /*
10492 : : * Creating the default Tx metadata copy table on NIC Tx group 0.
10493 : : *
10494 : : * @param dev
10495 : : * Pointer to Ethernet device.
10496 : : * @param pt
10497 : : * Pointer to flow pattern template.
10498 : : * @param at
10499 : : * Pointer to flow actions template.
10500 : : * @param error
10501 : : * Pointer to error structure.
10502 : : *
10503 : : * @return
10504 : : * Pointer to flow table on success, NULL otherwise.
10505 : : */
10506 : : static struct rte_flow_template_table*
10507 : 0 : flow_hw_create_tx_default_mreg_copy_table(struct rte_eth_dev *dev,
10508 : : struct rte_flow_pattern_template *pt,
10509 : : struct rte_flow_actions_template *at,
10510 : : struct rte_flow_error *error)
10511 : : {
10512 : 0 : struct rte_flow_template_table_attr tx_tbl_attr = {
10513 : : .flow_attr = {
10514 : : .group = 0, /* Root */
10515 : : .priority = MLX5_HW_LOWEST_PRIO_ROOT,
10516 : : .egress = 1,
10517 : : },
10518 : : .nb_flows = 1, /* One default flow rule for all. */
10519 : : };
10520 : 0 : struct mlx5_flow_template_table_cfg tx_tbl_cfg = {
10521 : : .attr = tx_tbl_attr,
10522 : : .external = false,
10523 : : };
10524 : :
10525 : 0 : return flow_hw_table_create(dev, &tx_tbl_cfg, &pt, 1, &at, 1, error);
10526 : : }
10527 : :
10528 : : /**
10529 : : * Creates a control flow table used to transfer traffic
10530 : : * from group 0 to group 1.
10531 : : *
10532 : : * @param dev
10533 : : * Pointer to Ethernet device.
10534 : : * @param it
10535 : : * Pointer to flow pattern template.
10536 : : * @param at
10537 : : * Pointer to flow actions template.
10538 : : * @param error
10539 : : * Pointer to error structure.
10540 : : *
10541 : : * @return
10542 : : * Pointer to flow table on success, NULL otherwise.
10543 : : */
10544 : : static struct rte_flow_template_table *
10545 : 0 : flow_hw_create_ctrl_jump_table(struct rte_eth_dev *dev,
10546 : : struct rte_flow_pattern_template *it,
10547 : : struct rte_flow_actions_template *at,
10548 : : struct rte_flow_error *error)
10549 : : {
10550 : 0 : struct rte_flow_template_table_attr attr = {
10551 : : .flow_attr = {
10552 : : .group = 0,
10553 : : .priority = 0,
10554 : : .ingress = 0,
10555 : : .egress = 0,
10556 : : .transfer = 1,
10557 : : },
10558 : : .nb_flows = MLX5_HW_CTRL_FLOW_NB_RULES,
10559 : : };
10560 : 0 : struct mlx5_flow_template_table_cfg cfg = {
10561 : : .attr = attr,
10562 : : .external = false,
10563 : : };
10564 : :
10565 : 0 : return flow_hw_table_create(dev, &cfg, &it, 1, &at, 1, error);
10566 : : }
10567 : :
10568 : : /**
10569 : : * Cleans up all template tables and pattern, and actions templates used for
10570 : : * FDB control flow rules.
10571 : : *
10572 : : * @param dev
10573 : : * Pointer to Ethernet device.
10574 : : */
10575 : : static void
10576 : 0 : flow_hw_cleanup_ctrl_fdb_tables(struct rte_eth_dev *dev)
10577 : : {
10578 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
10579 : : struct mlx5_flow_hw_ctrl_fdb *hw_ctrl_fdb;
10580 : :
10581 [ # # ]: 0 : if (!priv->hw_ctrl_fdb)
10582 : : return;
10583 : : hw_ctrl_fdb = priv->hw_ctrl_fdb;
10584 : : /* Clean up templates used for LACP default miss table. */
10585 [ # # ]: 0 : if (hw_ctrl_fdb->hw_lacp_rx_tbl)
10586 : 0 : claim_zero(flow_hw_table_destroy(dev, hw_ctrl_fdb->hw_lacp_rx_tbl, NULL));
10587 [ # # ]: 0 : if (hw_ctrl_fdb->lacp_rx_actions_tmpl)
10588 : 0 : claim_zero(flow_hw_actions_template_destroy(dev, hw_ctrl_fdb->lacp_rx_actions_tmpl,
10589 : : NULL));
10590 [ # # ]: 0 : if (hw_ctrl_fdb->lacp_rx_items_tmpl)
10591 : 0 : claim_zero(flow_hw_pattern_template_destroy(dev, hw_ctrl_fdb->lacp_rx_items_tmpl,
10592 : : NULL));
10593 : : /* Clean up templates used for default Tx metadata copy. */
10594 [ # # ]: 0 : if (hw_ctrl_fdb->hw_tx_meta_cpy_tbl)
10595 : 0 : claim_zero(flow_hw_table_destroy(dev, hw_ctrl_fdb->hw_tx_meta_cpy_tbl, NULL));
10596 [ # # ]: 0 : if (hw_ctrl_fdb->tx_meta_actions_tmpl)
10597 : 0 : claim_zero(flow_hw_actions_template_destroy(dev, hw_ctrl_fdb->tx_meta_actions_tmpl,
10598 : : NULL));
10599 [ # # ]: 0 : if (hw_ctrl_fdb->tx_meta_items_tmpl)
10600 : 0 : claim_zero(flow_hw_pattern_template_destroy(dev, hw_ctrl_fdb->tx_meta_items_tmpl,
10601 : : NULL));
10602 : : /* Clean up templates used for default FDB jump rule. */
10603 [ # # ]: 0 : if (hw_ctrl_fdb->hw_esw_zero_tbl)
10604 : 0 : claim_zero(flow_hw_table_destroy(dev, hw_ctrl_fdb->hw_esw_zero_tbl, NULL));
10605 [ # # ]: 0 : if (hw_ctrl_fdb->jump_one_actions_tmpl)
10606 : 0 : claim_zero(flow_hw_actions_template_destroy(dev, hw_ctrl_fdb->jump_one_actions_tmpl,
10607 : : NULL));
10608 [ # # ]: 0 : if (hw_ctrl_fdb->port_items_tmpl)
10609 : 0 : claim_zero(flow_hw_pattern_template_destroy(dev, hw_ctrl_fdb->port_items_tmpl,
10610 : : NULL));
10611 : : /* Clean up templates used for default SQ miss flow rules - non-root table. */
10612 [ # # ]: 0 : if (hw_ctrl_fdb->hw_esw_sq_miss_tbl)
10613 : 0 : claim_zero(flow_hw_table_destroy(dev, hw_ctrl_fdb->hw_esw_sq_miss_tbl, NULL));
10614 [ # # ]: 0 : if (hw_ctrl_fdb->regc_sq_items_tmpl)
10615 : 0 : claim_zero(flow_hw_pattern_template_destroy(dev, hw_ctrl_fdb->regc_sq_items_tmpl,
10616 : : NULL));
10617 [ # # ]: 0 : if (hw_ctrl_fdb->port_actions_tmpl)
10618 : 0 : claim_zero(flow_hw_actions_template_destroy(dev, hw_ctrl_fdb->port_actions_tmpl,
10619 : : NULL));
10620 : : /* Clean up templates used for default SQ miss flow rules - root table. */
10621 [ # # ]: 0 : if (hw_ctrl_fdb->hw_esw_sq_miss_root_tbl)
10622 : 0 : claim_zero(flow_hw_table_destroy(dev, hw_ctrl_fdb->hw_esw_sq_miss_root_tbl, NULL));
10623 [ # # ]: 0 : if (hw_ctrl_fdb->regc_jump_actions_tmpl)
10624 : 0 : claim_zero(flow_hw_actions_template_destroy(dev,
10625 : : hw_ctrl_fdb->regc_jump_actions_tmpl, NULL));
10626 [ # # ]: 0 : if (hw_ctrl_fdb->esw_mgr_items_tmpl)
10627 : 0 : claim_zero(flow_hw_pattern_template_destroy(dev, hw_ctrl_fdb->esw_mgr_items_tmpl,
10628 : : NULL));
10629 : : /* Clean up templates structure for FDB control flow rules. */
10630 : 0 : mlx5_free(hw_ctrl_fdb);
10631 : 0 : priv->hw_ctrl_fdb = NULL;
10632 : : }
10633 : :
10634 : : /*
10635 : : * Create a table on the root group to for the LACP traffic redirecting.
10636 : : *
10637 : : * @param dev
10638 : : * Pointer to Ethernet device.
10639 : : * @param it
10640 : : * Pointer to flow pattern template.
10641 : : * @param at
10642 : : * Pointer to flow actions template.
10643 : : *
10644 : : * @return
10645 : : * Pointer to flow table on success, NULL otherwise.
10646 : : */
10647 : : static struct rte_flow_template_table *
10648 : 0 : flow_hw_create_lacp_rx_table(struct rte_eth_dev *dev,
10649 : : struct rte_flow_pattern_template *it,
10650 : : struct rte_flow_actions_template *at,
10651 : : struct rte_flow_error *error)
10652 : : {
10653 : 0 : struct rte_flow_template_table_attr attr = {
10654 : : .flow_attr = {
10655 : : .group = 0,
10656 : : .priority = 0,
10657 : : .ingress = 1,
10658 : : .egress = 0,
10659 : : .transfer = 0,
10660 : : },
10661 : : .nb_flows = 1,
10662 : : };
10663 : 0 : struct mlx5_flow_template_table_cfg cfg = {
10664 : : .attr = attr,
10665 : : .external = false,
10666 : : };
10667 : :
10668 : 0 : return flow_hw_table_create(dev, &cfg, &it, 1, &at, 1, error);
10669 : : }
10670 : :
10671 : : /**
10672 : : * Creates a set of flow tables used to create control flows used
10673 : : * when E-Switch is engaged.
10674 : : *
10675 : : * @param dev
10676 : : * Pointer to Ethernet device.
10677 : : * @param error
10678 : : * Pointer to error structure.
10679 : : *
10680 : : * @return
10681 : : * 0 on success, negative values otherwise
10682 : : */
10683 : : static int
10684 : 0 : flow_hw_create_ctrl_tables(struct rte_eth_dev *dev, struct rte_flow_error *error)
10685 : : {
10686 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
10687 : : struct mlx5_flow_hw_ctrl_fdb *hw_ctrl_fdb;
10688 : 0 : uint32_t xmeta = priv->sh->config.dv_xmeta_en;
10689 : 0 : uint32_t repr_matching = priv->sh->config.repr_matching;
10690 : 0 : uint32_t fdb_def_rule = priv->sh->config.fdb_def_rule;
10691 : :
10692 : : MLX5_ASSERT(priv->hw_ctrl_fdb == NULL);
10693 : 0 : hw_ctrl_fdb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*hw_ctrl_fdb), 0, SOCKET_ID_ANY);
10694 [ # # ]: 0 : if (!hw_ctrl_fdb) {
10695 : 0 : DRV_LOG(ERR, "port %u failed to allocate memory for FDB control flow templates",
10696 : : dev->data->port_id);
10697 : 0 : rte_errno = ENOMEM;
10698 : 0 : goto err;
10699 : : }
10700 : 0 : priv->hw_ctrl_fdb = hw_ctrl_fdb;
10701 [ # # ]: 0 : if (fdb_def_rule) {
10702 : : /* Create templates and table for default SQ miss flow rules - root table. */
10703 : 0 : hw_ctrl_fdb->esw_mgr_items_tmpl =
10704 : 0 : flow_hw_create_ctrl_esw_mgr_pattern_template(dev, error);
10705 [ # # ]: 0 : if (!hw_ctrl_fdb->esw_mgr_items_tmpl) {
10706 : 0 : DRV_LOG(ERR, "port %u failed to create E-Switch Manager item"
10707 : : " template for control flows", dev->data->port_id);
10708 : 0 : goto err;
10709 : : }
10710 : 0 : hw_ctrl_fdb->regc_jump_actions_tmpl =
10711 : 0 : flow_hw_create_ctrl_regc_jump_actions_template(dev, error);
10712 [ # # ]: 0 : if (!hw_ctrl_fdb->regc_jump_actions_tmpl) {
10713 : 0 : DRV_LOG(ERR, "port %u failed to create REG_C set and jump action template"
10714 : : " for control flows", dev->data->port_id);
10715 : 0 : goto err;
10716 : : }
10717 : 0 : hw_ctrl_fdb->hw_esw_sq_miss_root_tbl =
10718 : 0 : flow_hw_create_ctrl_sq_miss_root_table
10719 : : (dev, hw_ctrl_fdb->esw_mgr_items_tmpl,
10720 : : hw_ctrl_fdb->regc_jump_actions_tmpl, error);
10721 [ # # ]: 0 : if (!hw_ctrl_fdb->hw_esw_sq_miss_root_tbl) {
10722 : 0 : DRV_LOG(ERR, "port %u failed to create table for default sq miss (root table)"
10723 : : " for control flows", dev->data->port_id);
10724 : 0 : goto err;
10725 : : }
10726 : : /* Create templates and table for default SQ miss flow rules - non-root table. */
10727 : 0 : hw_ctrl_fdb->regc_sq_items_tmpl =
10728 : 0 : flow_hw_create_ctrl_regc_sq_pattern_template(dev, error);
10729 [ # # ]: 0 : if (!hw_ctrl_fdb->regc_sq_items_tmpl) {
10730 : 0 : DRV_LOG(ERR, "port %u failed to create SQ item template for"
10731 : : " control flows", dev->data->port_id);
10732 : 0 : goto err;
10733 : : }
10734 : 0 : hw_ctrl_fdb->port_actions_tmpl =
10735 : 0 : flow_hw_create_ctrl_port_actions_template(dev, error);
10736 [ # # ]: 0 : if (!hw_ctrl_fdb->port_actions_tmpl) {
10737 : 0 : DRV_LOG(ERR, "port %u failed to create port action template"
10738 : : " for control flows", dev->data->port_id);
10739 : 0 : goto err;
10740 : : }
10741 : 0 : hw_ctrl_fdb->hw_esw_sq_miss_tbl =
10742 : 0 : flow_hw_create_ctrl_sq_miss_table
10743 : : (dev, hw_ctrl_fdb->regc_sq_items_tmpl,
10744 : : hw_ctrl_fdb->port_actions_tmpl, error);
10745 [ # # ]: 0 : if (!hw_ctrl_fdb->hw_esw_sq_miss_tbl) {
10746 : 0 : DRV_LOG(ERR, "port %u failed to create table for default sq miss (non-root table)"
10747 : : " for control flows", dev->data->port_id);
10748 : 0 : goto err;
10749 : : }
10750 : : /* Create templates and table for default FDB jump flow rules. */
10751 : 0 : hw_ctrl_fdb->port_items_tmpl =
10752 : 0 : flow_hw_create_ctrl_port_pattern_template(dev, error);
10753 [ # # ]: 0 : if (!hw_ctrl_fdb->port_items_tmpl) {
10754 : 0 : DRV_LOG(ERR, "port %u failed to create SQ item template for"
10755 : : " control flows", dev->data->port_id);
10756 : 0 : goto err;
10757 : : }
10758 : 0 : hw_ctrl_fdb->jump_one_actions_tmpl =
10759 : 0 : flow_hw_create_ctrl_jump_actions_template
10760 : : (dev, MLX5_HW_LOWEST_USABLE_GROUP, error);
10761 [ # # ]: 0 : if (!hw_ctrl_fdb->jump_one_actions_tmpl) {
10762 : 0 : DRV_LOG(ERR, "port %u failed to create jump action template"
10763 : : " for control flows", dev->data->port_id);
10764 : 0 : goto err;
10765 : : }
10766 : 0 : hw_ctrl_fdb->hw_esw_zero_tbl = flow_hw_create_ctrl_jump_table
10767 : : (dev, hw_ctrl_fdb->port_items_tmpl,
10768 : : hw_ctrl_fdb->jump_one_actions_tmpl, error);
10769 [ # # ]: 0 : if (!hw_ctrl_fdb->hw_esw_zero_tbl) {
10770 : 0 : DRV_LOG(ERR, "port %u failed to create table for default jump to group 1"
10771 : : " for control flows", dev->data->port_id);
10772 : 0 : goto err;
10773 : : }
10774 : : }
10775 : : /* Create templates and table for default Tx metadata copy flow rule. */
10776 [ # # ]: 0 : if (!repr_matching && xmeta == MLX5_XMETA_MODE_META32_HWS) {
10777 : 0 : hw_ctrl_fdb->tx_meta_items_tmpl =
10778 : 0 : flow_hw_create_tx_default_mreg_copy_pattern_template(dev, error);
10779 [ # # ]: 0 : if (!hw_ctrl_fdb->tx_meta_items_tmpl) {
10780 : 0 : DRV_LOG(ERR, "port %u failed to Tx metadata copy pattern"
10781 : : " template for control flows", dev->data->port_id);
10782 : 0 : goto err;
10783 : : }
10784 : 0 : hw_ctrl_fdb->tx_meta_actions_tmpl =
10785 : 0 : flow_hw_create_tx_default_mreg_copy_actions_template(dev, error);
10786 [ # # ]: 0 : if (!hw_ctrl_fdb->tx_meta_actions_tmpl) {
10787 : 0 : DRV_LOG(ERR, "port %u failed to Tx metadata copy actions"
10788 : : " template for control flows", dev->data->port_id);
10789 : 0 : goto err;
10790 : : }
10791 : 0 : hw_ctrl_fdb->hw_tx_meta_cpy_tbl =
10792 : 0 : flow_hw_create_tx_default_mreg_copy_table
10793 : : (dev, hw_ctrl_fdb->tx_meta_items_tmpl,
10794 : : hw_ctrl_fdb->tx_meta_actions_tmpl, error);
10795 [ # # ]: 0 : if (!hw_ctrl_fdb->hw_tx_meta_cpy_tbl) {
10796 : 0 : DRV_LOG(ERR, "port %u failed to create table for default"
10797 : : " Tx metadata copy flow rule", dev->data->port_id);
10798 : 0 : goto err;
10799 : : }
10800 : : }
10801 : : /* Create LACP default miss table. */
10802 [ # # # # : 0 : if (!priv->sh->config.lacp_by_user && priv->pf_bond >= 0 && priv->master) {
# # ]
10803 : 0 : hw_ctrl_fdb->lacp_rx_items_tmpl =
10804 : 0 : flow_hw_create_lacp_rx_pattern_template(dev, error);
10805 [ # # ]: 0 : if (!hw_ctrl_fdb->lacp_rx_items_tmpl) {
10806 : 0 : DRV_LOG(ERR, "port %u failed to create pattern template"
10807 : : " for LACP Rx traffic", dev->data->port_id);
10808 : 0 : goto err;
10809 : : }
10810 : 0 : hw_ctrl_fdb->lacp_rx_actions_tmpl =
10811 : 0 : flow_hw_create_lacp_rx_actions_template(dev, error);
10812 [ # # ]: 0 : if (!hw_ctrl_fdb->lacp_rx_actions_tmpl) {
10813 : 0 : DRV_LOG(ERR, "port %u failed to create actions template"
10814 : : " for LACP Rx traffic", dev->data->port_id);
10815 : 0 : goto err;
10816 : : }
10817 : 0 : hw_ctrl_fdb->hw_lacp_rx_tbl = flow_hw_create_lacp_rx_table
10818 : : (dev, hw_ctrl_fdb->lacp_rx_items_tmpl,
10819 : : hw_ctrl_fdb->lacp_rx_actions_tmpl, error);
10820 [ # # ]: 0 : if (!hw_ctrl_fdb->hw_lacp_rx_tbl) {
10821 : 0 : DRV_LOG(ERR, "port %u failed to create template table for"
10822 : : " for LACP Rx traffic", dev->data->port_id);
10823 : 0 : goto err;
10824 : : }
10825 : : }
10826 : : return 0;
10827 : :
10828 : 0 : err:
10829 : 0 : flow_hw_cleanup_ctrl_fdb_tables(dev);
10830 : 0 : return -EINVAL;
10831 : : }
10832 : :
10833 : : static void
10834 : 0 : flow_hw_ct_mng_destroy(struct rte_eth_dev *dev,
10835 : : struct mlx5_aso_ct_pools_mng *ct_mng)
10836 : : {
10837 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
10838 : :
10839 : 0 : mlx5_aso_ct_queue_uninit(priv->sh, ct_mng);
10840 : 0 : mlx5_free(ct_mng);
10841 : 0 : }
10842 : :
10843 : : static void
10844 : 0 : flow_hw_ct_pool_destroy(struct rte_eth_dev *dev,
10845 : : struct mlx5_aso_ct_pool *pool)
10846 : : {
10847 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
10848 : :
10849 [ # # ]: 0 : if (pool->dr_action)
10850 : 0 : mlx5dr_action_destroy(pool->dr_action);
10851 [ # # ]: 0 : if (!priv->shared_host) {
10852 [ # # ]: 0 : if (pool->devx_obj)
10853 : 0 : claim_zero(mlx5_devx_cmd_destroy(pool->devx_obj));
10854 [ # # ]: 0 : if (pool->cts)
10855 : 0 : mlx5_ipool_destroy(pool->cts);
10856 : : }
10857 : 0 : mlx5_free(pool);
10858 : 0 : }
10859 : :
10860 : : static struct mlx5_aso_ct_pool *
10861 : 0 : flow_hw_ct_pool_create(struct rte_eth_dev *dev,
10862 : : uint32_t nb_conn_tracks)
10863 : : {
10864 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
10865 : : struct mlx5_aso_ct_pool *pool;
10866 : : struct mlx5_devx_obj *obj;
10867 : : uint32_t nb_cts = rte_align32pow2(nb_conn_tracks);
10868 : : uint32_t log_obj_size = rte_log2_u32(nb_cts);
10869 : 0 : struct mlx5_indexed_pool_config cfg = {
10870 : : .size = sizeof(struct mlx5_aso_ct_action),
10871 : : .trunk_size = 1 << 12,
10872 : : .per_core_cache = 1 << 13,
10873 : : .need_lock = 1,
10874 : 0 : .release_mem_en = !!priv->sh->config.reclaim_mode,
10875 : : .malloc = mlx5_malloc,
10876 : : .free = mlx5_free,
10877 : : .type = "mlx5_hw_ct_action",
10878 : : };
10879 : : int reg_id;
10880 : : uint32_t flags = 0;
10881 : :
10882 : 0 : pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
10883 [ # # ]: 0 : if (!pool) {
10884 : 0 : rte_errno = ENOMEM;
10885 : 0 : return NULL;
10886 : : }
10887 [ # # ]: 0 : if (!priv->shared_host) {
10888 : : /*
10889 : : * No need for local cache if CT number is a small number. Since
10890 : : * flow insertion rate will be very limited in that case. Here let's
10891 : : * set the number to less than default trunk size 4K.
10892 : : */
10893 [ # # ]: 0 : if (nb_cts <= cfg.trunk_size) {
10894 : 0 : cfg.per_core_cache = 0;
10895 : 0 : cfg.trunk_size = nb_cts;
10896 [ # # ]: 0 : } else if (nb_cts <= MLX5_HW_IPOOL_SIZE_THRESHOLD) {
10897 : 0 : cfg.per_core_cache = MLX5_HW_IPOOL_CACHE_MIN;
10898 : : }
10899 : 0 : cfg.max_idx = nb_cts;
10900 : 0 : pool->cts = mlx5_ipool_create(&cfg);
10901 [ # # ]: 0 : if (!pool->cts)
10902 : 0 : goto err;
10903 : 0 : obj = mlx5_devx_cmd_create_conn_track_offload_obj(priv->sh->cdev->ctx,
10904 : 0 : priv->sh->cdev->pdn,
10905 : : log_obj_size);
10906 [ # # ]: 0 : if (!obj) {
10907 : 0 : rte_errno = ENODATA;
10908 : 0 : DRV_LOG(ERR, "Failed to create conn_track_offload_obj using DevX.");
10909 : 0 : goto err;
10910 : : }
10911 : 0 : pool->devx_obj = obj;
10912 : : } else {
10913 : : struct rte_eth_dev *host_dev = priv->shared_host;
10914 : 0 : struct mlx5_priv *host_priv = host_dev->data->dev_private;
10915 : :
10916 : 0 : pool->devx_obj = host_priv->hws_ctpool->devx_obj;
10917 : 0 : pool->cts = host_priv->hws_ctpool->cts;
10918 : : MLX5_ASSERT(pool->cts);
10919 : : MLX5_ASSERT(!nb_conn_tracks);
10920 : : }
10921 : 0 : reg_id = mlx5_flow_get_reg_id(dev, MLX5_ASO_CONNTRACK, 0, NULL);
10922 : : flags |= MLX5DR_ACTION_FLAG_HWS_RX | MLX5DR_ACTION_FLAG_HWS_TX;
10923 [ # # # # ]: 0 : if (priv->sh->config.dv_esw_en && priv->master)
10924 : : flags |= MLX5DR_ACTION_FLAG_HWS_FDB;
10925 : 0 : pool->dr_action = mlx5dr_action_create_aso_ct(priv->dr_ctx,
10926 : 0 : (struct mlx5dr_devx_obj *)pool->devx_obj,
10927 : 0 : reg_id - REG_C_0, flags);
10928 [ # # ]: 0 : if (!pool->dr_action)
10929 : 0 : goto err;
10930 : 0 : pool->sq = priv->ct_mng->aso_sqs;
10931 : : /* Assign the last extra ASO SQ as public SQ. */
10932 : 0 : pool->shared_sq = &priv->ct_mng->aso_sqs[priv->nb_queue - 1];
10933 : 0 : return pool;
10934 : 0 : err:
10935 : 0 : flow_hw_ct_pool_destroy(dev, pool);
10936 : 0 : return NULL;
10937 : : }
10938 : :
10939 : : static int
10940 : 0 : mlx5_flow_ct_init(struct rte_eth_dev *dev,
10941 : : uint32_t nb_conn_tracks,
10942 : : uint16_t nb_queue)
10943 : : {
10944 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
10945 : : uint32_t mem_size;
10946 : : int ret = -ENOMEM;
10947 : :
10948 [ # # ]: 0 : if (!priv->shared_host) {
10949 : 0 : mem_size = sizeof(struct mlx5_aso_sq) * nb_queue +
10950 : : sizeof(*priv->ct_mng);
10951 : 0 : priv->ct_mng = mlx5_malloc(MLX5_MEM_ZERO, mem_size,
10952 : : RTE_CACHE_LINE_SIZE,
10953 : : SOCKET_ID_ANY);
10954 [ # # ]: 0 : if (!priv->ct_mng)
10955 : 0 : goto err;
10956 : 0 : ret = mlx5_aso_ct_queue_init(priv->sh, priv->ct_mng,
10957 : : nb_queue);
10958 [ # # ]: 0 : if (ret)
10959 : 0 : goto err;
10960 : : }
10961 : 0 : priv->hws_ctpool = flow_hw_ct_pool_create(dev, nb_conn_tracks);
10962 [ # # ]: 0 : if (!priv->hws_ctpool)
10963 : 0 : goto err;
10964 : 0 : priv->sh->ct_aso_en = 1;
10965 : 0 : return 0;
10966 : :
10967 : 0 : err:
10968 [ # # ]: 0 : if (priv->hws_ctpool) {
10969 : 0 : flow_hw_ct_pool_destroy(dev, priv->hws_ctpool);
10970 : 0 : priv->hws_ctpool = NULL;
10971 : : }
10972 [ # # ]: 0 : if (priv->ct_mng) {
10973 : 0 : flow_hw_ct_mng_destroy(dev, priv->ct_mng);
10974 : 0 : priv->ct_mng = NULL;
10975 : : }
10976 : : return ret;
10977 : : }
10978 : :
10979 : : static void
10980 : 0 : flow_hw_destroy_vlan(struct rte_eth_dev *dev)
10981 : : {
10982 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
10983 : : enum mlx5dr_table_type i;
10984 : :
10985 [ # # ]: 0 : for (i = MLX5DR_TABLE_TYPE_NIC_RX; i < MLX5DR_TABLE_TYPE_MAX; i++) {
10986 [ # # ]: 0 : if (priv->hw_pop_vlan[i]) {
10987 : 0 : mlx5dr_action_destroy(priv->hw_pop_vlan[i]);
10988 : 0 : priv->hw_pop_vlan[i] = NULL;
10989 : : }
10990 [ # # ]: 0 : if (priv->hw_push_vlan[i]) {
10991 : 0 : mlx5dr_action_destroy(priv->hw_push_vlan[i]);
10992 : 0 : priv->hw_push_vlan[i] = NULL;
10993 : : }
10994 : : }
10995 : 0 : }
10996 : :
10997 : : static int
10998 : 0 : flow_hw_create_vlan(struct rte_eth_dev *dev)
10999 : : {
11000 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11001 : : enum mlx5dr_table_type i;
11002 : 0 : const enum mlx5dr_action_flags flags[MLX5DR_TABLE_TYPE_MAX] = {
11003 : : MLX5DR_ACTION_FLAG_HWS_RX,
11004 : : MLX5DR_ACTION_FLAG_HWS_TX,
11005 : : MLX5DR_ACTION_FLAG_HWS_FDB
11006 : : };
11007 : :
11008 : : /* rte_errno is set in the mlx5dr_action* functions. */
11009 [ # # ]: 0 : for (i = MLX5DR_TABLE_TYPE_NIC_RX; i <= MLX5DR_TABLE_TYPE_NIC_TX; i++) {
11010 : 0 : priv->hw_pop_vlan[i] =
11011 : 0 : mlx5dr_action_create_pop_vlan(priv->dr_ctx, flags[i]);
11012 [ # # ]: 0 : if (!priv->hw_pop_vlan[i])
11013 : 0 : return -rte_errno;
11014 : 0 : priv->hw_push_vlan[i] =
11015 : 0 : mlx5dr_action_create_push_vlan(priv->dr_ctx, flags[i]);
11016 [ # # ]: 0 : if (!priv->hw_pop_vlan[i])
11017 : 0 : return -rte_errno;
11018 : : }
11019 [ # # # # ]: 0 : if (priv->sh->config.dv_esw_en && priv->master) {
11020 : 0 : priv->hw_pop_vlan[MLX5DR_TABLE_TYPE_FDB] =
11021 : 0 : mlx5dr_action_create_pop_vlan
11022 : : (priv->dr_ctx, MLX5DR_ACTION_FLAG_HWS_FDB);
11023 [ # # ]: 0 : if (!priv->hw_pop_vlan[MLX5DR_TABLE_TYPE_FDB])
11024 : 0 : return -rte_errno;
11025 : 0 : priv->hw_push_vlan[MLX5DR_TABLE_TYPE_FDB] =
11026 : 0 : mlx5dr_action_create_push_vlan
11027 : : (priv->dr_ctx, MLX5DR_ACTION_FLAG_HWS_FDB);
11028 [ # # ]: 0 : if (!priv->hw_pop_vlan[MLX5DR_TABLE_TYPE_FDB])
11029 : 0 : return -rte_errno;
11030 : : }
11031 : : return 0;
11032 : : }
11033 : :
11034 : : static void
11035 : 0 : flow_hw_cleanup_ctrl_rx_tables(struct rte_eth_dev *dev)
11036 : : {
11037 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11038 : : unsigned int i;
11039 : : unsigned int j;
11040 : :
11041 [ # # ]: 0 : if (!priv->hw_ctrl_rx)
11042 : : return;
11043 [ # # ]: 0 : for (i = 0; i < MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_MAX; ++i) {
11044 [ # # ]: 0 : for (j = 0; j < MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX; ++j) {
11045 : 0 : struct rte_flow_template_table *tbl = priv->hw_ctrl_rx->tables[i][j].tbl;
11046 : 0 : struct rte_flow_pattern_template *pt = priv->hw_ctrl_rx->tables[i][j].pt;
11047 : :
11048 [ # # ]: 0 : if (tbl)
11049 : 0 : claim_zero(flow_hw_table_destroy(dev, tbl, NULL));
11050 [ # # ]: 0 : if (pt)
11051 : 0 : claim_zero(flow_hw_pattern_template_destroy(dev, pt, NULL));
11052 : : }
11053 : : }
11054 [ # # ]: 0 : for (i = 0; i < MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX; ++i) {
11055 : 0 : struct rte_flow_actions_template *at = priv->hw_ctrl_rx->rss[i];
11056 : :
11057 [ # # ]: 0 : if (at)
11058 : 0 : claim_zero(flow_hw_actions_template_destroy(dev, at, NULL));
11059 : : }
11060 : 0 : mlx5_free(priv->hw_ctrl_rx);
11061 : 0 : priv->hw_ctrl_rx = NULL;
11062 : : }
11063 : :
11064 : : static uint64_t
11065 : : flow_hw_ctrl_rx_rss_type_hash_types(const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
11066 : : {
11067 : : switch (rss_type) {
11068 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_NON_IP:
11069 : : return 0;
11070 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4:
11071 : : return RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_FRAG_IPV4 | RTE_ETH_RSS_NONFRAG_IPV4_OTHER;
11072 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_UDP:
11073 : : return RTE_ETH_RSS_NONFRAG_IPV4_UDP;
11074 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_TCP:
11075 : : return RTE_ETH_RSS_NONFRAG_IPV4_TCP;
11076 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6:
11077 : : return RTE_ETH_RSS_IPV6 | RTE_ETH_RSS_FRAG_IPV6 | RTE_ETH_RSS_NONFRAG_IPV6_OTHER;
11078 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_UDP:
11079 : : return RTE_ETH_RSS_NONFRAG_IPV6_UDP | RTE_ETH_RSS_IPV6_UDP_EX;
11080 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_TCP:
11081 : : return RTE_ETH_RSS_NONFRAG_IPV6_TCP | RTE_ETH_RSS_IPV6_TCP_EX;
11082 : : default:
11083 : : /* Should not reach here. */
11084 : : MLX5_ASSERT(false);
11085 : : return 0;
11086 : : }
11087 : : }
11088 : :
11089 : : static struct rte_flow_actions_template *
11090 : 0 : flow_hw_create_ctrl_rx_rss_template(struct rte_eth_dev *dev,
11091 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
11092 : : {
11093 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11094 : 0 : struct rte_flow_actions_template_attr attr = {
11095 : : .ingress = 1,
11096 : : };
11097 : : uint16_t queue[RTE_MAX_QUEUES_PER_PORT];
11098 : 0 : struct rte_flow_action_rss rss_conf = {
11099 : : .func = RTE_ETH_HASH_FUNCTION_DEFAULT,
11100 : : .level = 0,
11101 : : .types = 0,
11102 : 0 : .key_len = priv->rss_conf.rss_key_len,
11103 : 0 : .key = priv->rss_conf.rss_key,
11104 : 0 : .queue_num = priv->reta_idx_n,
11105 : : .queue = queue,
11106 : : };
11107 : 0 : struct rte_flow_action actions[] = {
11108 : : {
11109 : : .type = RTE_FLOW_ACTION_TYPE_RSS,
11110 : : .conf = &rss_conf,
11111 : : },
11112 : : {
11113 : : .type = RTE_FLOW_ACTION_TYPE_END,
11114 : : }
11115 : : };
11116 [ # # ]: 0 : struct rte_flow_action masks[] = {
11117 : : {
11118 : : .type = RTE_FLOW_ACTION_TYPE_RSS,
11119 : : .conf = &rss_conf,
11120 : : },
11121 : : {
11122 : : .type = RTE_FLOW_ACTION_TYPE_END,
11123 : : }
11124 : : };
11125 : : struct rte_flow_actions_template *at;
11126 : : struct rte_flow_error error;
11127 : : unsigned int i;
11128 : :
11129 : : MLX5_ASSERT(priv->reta_idx_n > 0 && priv->reta_idx);
11130 : : /* Select proper RSS hash types and based on that configure the actions template. */
11131 : 0 : rss_conf.types = flow_hw_ctrl_rx_rss_type_hash_types(rss_type);
11132 [ # # ]: 0 : if (rss_conf.types) {
11133 [ # # ]: 0 : for (i = 0; i < priv->reta_idx_n; ++i)
11134 : 0 : queue[i] = (*priv->reta_idx)[i];
11135 : : } else {
11136 : 0 : rss_conf.queue_num = 1;
11137 : 0 : queue[0] = (*priv->reta_idx)[0];
11138 : : }
11139 : : at = flow_hw_actions_template_create(dev, &attr, actions, masks, &error);
11140 [ # # ]: 0 : if (!at)
11141 [ # # ]: 0 : DRV_LOG(ERR,
11142 : : "Failed to create ctrl flow actions template: rte_errno(%d), type(%d): %s",
11143 : : rte_errno, error.type,
11144 : : error.message ? error.message : "(no stated reason)");
11145 : 0 : return at;
11146 : : }
11147 : :
11148 : : static uint32_t ctrl_rx_rss_priority_map[MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX] = {
11149 : : [MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_NON_IP] = MLX5_HW_CTRL_RX_PRIO_L2,
11150 : : [MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4] = MLX5_HW_CTRL_RX_PRIO_L3,
11151 : : [MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_UDP] = MLX5_HW_CTRL_RX_PRIO_L4,
11152 : : [MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_TCP] = MLX5_HW_CTRL_RX_PRIO_L4,
11153 : : [MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6] = MLX5_HW_CTRL_RX_PRIO_L3,
11154 : : [MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_UDP] = MLX5_HW_CTRL_RX_PRIO_L4,
11155 : : [MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_TCP] = MLX5_HW_CTRL_RX_PRIO_L4,
11156 : : };
11157 : :
11158 : : static uint32_t ctrl_rx_nb_flows_map[MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_MAX] = {
11159 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL] = 1,
11160 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL_MCAST] = 1,
11161 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST] = 1,
11162 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST_VLAN] = MLX5_MAX_VLAN_IDS,
11163 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST] = 1,
11164 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST_VLAN] = MLX5_MAX_VLAN_IDS,
11165 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST] = 1,
11166 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST_VLAN] = MLX5_MAX_VLAN_IDS,
11167 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC] = MLX5_MAX_UC_MAC_ADDRESSES,
11168 : : [MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN] =
11169 : : MLX5_MAX_UC_MAC_ADDRESSES * MLX5_MAX_VLAN_IDS,
11170 : : };
11171 : :
11172 : : static struct rte_flow_template_table_attr
11173 : : flow_hw_get_ctrl_rx_table_attr(enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type,
11174 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
11175 : : {
11176 : 0 : return (struct rte_flow_template_table_attr){
11177 : : .flow_attr = {
11178 : : .group = 0,
11179 : 0 : .priority = ctrl_rx_rss_priority_map[rss_type],
11180 : : .ingress = 1,
11181 : : },
11182 : 0 : .nb_flows = ctrl_rx_nb_flows_map[eth_pattern_type],
11183 : : };
11184 : : }
11185 : :
11186 : : static struct rte_flow_item
11187 : : flow_hw_get_ctrl_rx_eth_item(const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type)
11188 : : {
11189 : : struct rte_flow_item item = {
11190 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
11191 : : .mask = NULL,
11192 : : };
11193 : :
11194 : 0 : switch (eth_pattern_type) {
11195 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL:
11196 : : item.mask = &ctrl_rx_eth_promisc_mask;
11197 : : break;
11198 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL_MCAST:
11199 : : item.mask = &ctrl_rx_eth_mcast_mask;
11200 : 0 : break;
11201 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST:
11202 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST_VLAN:
11203 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC:
11204 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN:
11205 : : item.mask = &ctrl_rx_eth_dmac_mask;
11206 : 0 : break;
11207 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST:
11208 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST_VLAN:
11209 : : item.mask = &ctrl_rx_eth_ipv4_mcast_mask;
11210 : 0 : break;
11211 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST:
11212 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST_VLAN:
11213 : : item.mask = &ctrl_rx_eth_ipv6_mcast_mask;
11214 : 0 : break;
11215 : 0 : default:
11216 : : /* Should not reach here - ETH mask must be present. */
11217 : : item.type = RTE_FLOW_ITEM_TYPE_END;
11218 : : MLX5_ASSERT(false);
11219 : 0 : break;
11220 : : }
11221 : 0 : return item;
11222 : : }
11223 : :
11224 : : static struct rte_flow_item
11225 : : flow_hw_get_ctrl_rx_vlan_item(const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type)
11226 : : {
11227 : : struct rte_flow_item item = {
11228 : : .type = RTE_FLOW_ITEM_TYPE_VOID,
11229 : : .mask = NULL,
11230 : : };
11231 : :
11232 [ # # ]: 0 : switch (eth_pattern_type) {
11233 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST_VLAN:
11234 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST_VLAN:
11235 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST_VLAN:
11236 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN:
11237 : : item.type = RTE_FLOW_ITEM_TYPE_VLAN;
11238 : : item.mask = &rte_flow_item_vlan_mask;
11239 : 0 : break;
11240 : : default:
11241 : : /* Nothing to update. */
11242 : : break;
11243 : : }
11244 : 0 : return item;
11245 : : }
11246 : :
11247 : : static struct rte_flow_item
11248 : : flow_hw_get_ctrl_rx_l3_item(const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
11249 : : {
11250 : : struct rte_flow_item item = {
11251 : : .type = RTE_FLOW_ITEM_TYPE_VOID,
11252 : : .mask = NULL,
11253 : : };
11254 : :
11255 [ # # # ]: 0 : switch (rss_type) {
11256 : 0 : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4:
11257 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_UDP:
11258 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_TCP:
11259 : : item.type = RTE_FLOW_ITEM_TYPE_IPV4;
11260 : 0 : break;
11261 : 0 : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6:
11262 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_UDP:
11263 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_TCP:
11264 : : item.type = RTE_FLOW_ITEM_TYPE_IPV6;
11265 : 0 : break;
11266 : : default:
11267 : : /* Nothing to update. */
11268 : : break;
11269 : : }
11270 : 0 : return item;
11271 : : }
11272 : :
11273 : : static struct rte_flow_item
11274 : : flow_hw_get_ctrl_rx_l4_item(const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
11275 : : {
11276 : : struct rte_flow_item item = {
11277 : : .type = RTE_FLOW_ITEM_TYPE_VOID,
11278 : : .mask = NULL,
11279 : : };
11280 : :
11281 [ # # # ]: 0 : switch (rss_type) {
11282 : 0 : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_UDP:
11283 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_UDP:
11284 : : item.type = RTE_FLOW_ITEM_TYPE_UDP;
11285 : 0 : break;
11286 : 0 : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_TCP:
11287 : : case MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_TCP:
11288 : : item.type = RTE_FLOW_ITEM_TYPE_TCP;
11289 : 0 : break;
11290 : : default:
11291 : : /* Nothing to update. */
11292 : : break;
11293 : : }
11294 : 0 : return item;
11295 : : }
11296 : :
11297 : : static struct rte_flow_pattern_template *
11298 : 0 : flow_hw_create_ctrl_rx_pattern_template
11299 : : (struct rte_eth_dev *dev,
11300 : : const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type,
11301 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
11302 : : {
11303 : 0 : const struct rte_flow_pattern_template_attr attr = {
11304 : : .relaxed_matching = 0,
11305 : : .ingress = 1,
11306 : : };
11307 [ # # # # : 0 : struct rte_flow_item items[] = {
# # ]
11308 : : /* Matching patterns */
11309 : : flow_hw_get_ctrl_rx_eth_item(eth_pattern_type),
11310 : : flow_hw_get_ctrl_rx_vlan_item(eth_pattern_type),
11311 : : flow_hw_get_ctrl_rx_l3_item(rss_type),
11312 : : flow_hw_get_ctrl_rx_l4_item(rss_type),
11313 : : /* Terminate pattern */
11314 : : { .type = RTE_FLOW_ITEM_TYPE_END }
11315 : : };
11316 : :
11317 : 0 : return flow_hw_pattern_template_create(dev, &attr, items, NULL);
11318 : : }
11319 : :
11320 : : static int
11321 : 0 : flow_hw_create_ctrl_rx_tables(struct rte_eth_dev *dev)
11322 : : {
11323 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11324 : : unsigned int i;
11325 : : unsigned int j;
11326 : : int ret;
11327 : :
11328 : : MLX5_ASSERT(!priv->hw_ctrl_rx);
11329 : 0 : priv->hw_ctrl_rx = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*priv->hw_ctrl_rx),
11330 : 0 : RTE_CACHE_LINE_SIZE, rte_socket_id());
11331 [ # # ]: 0 : if (!priv->hw_ctrl_rx) {
11332 : 0 : DRV_LOG(ERR, "Failed to allocate memory for Rx control flow tables");
11333 : 0 : rte_errno = ENOMEM;
11334 : 0 : return -rte_errno;
11335 : : }
11336 : : /* Create all pattern template variants. */
11337 [ # # ]: 0 : for (i = 0; i < MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_MAX; ++i) {
11338 : : enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type = i;
11339 : :
11340 [ # # ]: 0 : for (j = 0; j < MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX; ++j) {
11341 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type = j;
11342 : : struct rte_flow_template_table_attr attr;
11343 : : struct rte_flow_pattern_template *pt;
11344 : :
11345 : : attr = flow_hw_get_ctrl_rx_table_attr(eth_pattern_type, rss_type);
11346 : 0 : pt = flow_hw_create_ctrl_rx_pattern_template(dev, eth_pattern_type,
11347 : : rss_type);
11348 [ # # ]: 0 : if (!pt)
11349 : 0 : goto err;
11350 : 0 : priv->hw_ctrl_rx->tables[i][j].attr = attr;
11351 : 0 : priv->hw_ctrl_rx->tables[i][j].pt = pt;
11352 : : }
11353 : : }
11354 : : return 0;
11355 : : err:
11356 : 0 : ret = rte_errno;
11357 : 0 : flow_hw_cleanup_ctrl_rx_tables(dev);
11358 : 0 : rte_errno = ret;
11359 : 0 : return -ret;
11360 : : }
11361 : :
11362 : : void
11363 : 0 : mlx5_flow_hw_cleanup_ctrl_rx_templates(struct rte_eth_dev *dev)
11364 : : {
11365 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11366 : : struct mlx5_flow_hw_ctrl_rx *hw_ctrl_rx;
11367 : : unsigned int i;
11368 : : unsigned int j;
11369 : :
11370 [ # # ]: 0 : if (!priv->dr_ctx)
11371 : : return;
11372 [ # # ]: 0 : if (!priv->hw_ctrl_rx)
11373 : : return;
11374 : : hw_ctrl_rx = priv->hw_ctrl_rx;
11375 [ # # ]: 0 : for (i = 0; i < MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_MAX; ++i) {
11376 [ # # ]: 0 : for (j = 0; j < MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX; ++j) {
11377 : : struct mlx5_flow_hw_ctrl_rx_table *tmpls = &hw_ctrl_rx->tables[i][j];
11378 : :
11379 [ # # ]: 0 : if (tmpls->tbl) {
11380 : 0 : claim_zero(flow_hw_table_destroy(dev, tmpls->tbl, NULL));
11381 : 0 : tmpls->tbl = NULL;
11382 : : }
11383 : : }
11384 : : }
11385 [ # # ]: 0 : for (j = 0; j < MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX; ++j) {
11386 [ # # ]: 0 : if (hw_ctrl_rx->rss[j]) {
11387 : 0 : claim_zero(flow_hw_actions_template_destroy(dev, hw_ctrl_rx->rss[j], NULL));
11388 : 0 : hw_ctrl_rx->rss[j] = NULL;
11389 : : }
11390 : : }
11391 : : }
11392 : :
11393 : : /**
11394 : : * Copy the provided HWS configuration to a newly allocated buffer.
11395 : : *
11396 : : * @param[in] port_attr
11397 : : * Port configuration attributes.
11398 : : * @param[in] nb_queue
11399 : : * Number of queue.
11400 : : * @param[in] queue_attr
11401 : : * Array that holds attributes for each flow queue.
11402 : : * @param[in] nt_mode
11403 : : * Non template mode.
11404 : : *
11405 : : * @return
11406 : : * Pointer to copied HWS configuration is returned on success.
11407 : : * Otherwise, NULL is returned and rte_errno is set.
11408 : : */
11409 : : static struct mlx5_flow_hw_attr *
11410 : 0 : flow_hw_alloc_copy_config(const struct rte_flow_port_attr *port_attr,
11411 : : const uint16_t nb_queue,
11412 : : const struct rte_flow_queue_attr *queue_attr[],
11413 : : bool nt_mode,
11414 : : struct rte_flow_error *error)
11415 : : {
11416 : : struct mlx5_flow_hw_attr *hw_attr;
11417 : : size_t hw_attr_size;
11418 : : unsigned int i;
11419 : :
11420 : 0 : hw_attr_size = sizeof(*hw_attr) + nb_queue * sizeof(*hw_attr->queue_attr);
11421 : 0 : hw_attr = mlx5_malloc(MLX5_MEM_ZERO, hw_attr_size, 0, SOCKET_ID_ANY);
11422 [ # # ]: 0 : if (!hw_attr) {
11423 : 0 : rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11424 : : "Not enough memory to store configuration");
11425 : 0 : return NULL;
11426 : : }
11427 : 0 : memcpy(&hw_attr->port_attr, port_attr, sizeof(*port_attr));
11428 : 0 : hw_attr->nb_queue = nb_queue;
11429 : : /* Queue attributes are placed after the mlx5_flow_hw_attr. */
11430 : 0 : hw_attr->queue_attr = (struct rte_flow_queue_attr *)(hw_attr + 1);
11431 [ # # ]: 0 : for (i = 0; i < nb_queue; ++i)
11432 : 0 : memcpy(&hw_attr->queue_attr[i], queue_attr[i], sizeof(hw_attr->queue_attr[i]));
11433 : 0 : hw_attr->nt_mode = nt_mode;
11434 : 0 : return hw_attr;
11435 : : }
11436 : :
11437 : : /**
11438 : : * Compares the preserved HWS configuration with the provided one.
11439 : : *
11440 : : * @param[in] hw_attr
11441 : : * Pointer to preserved HWS configuration.
11442 : : * @param[in] new_pa
11443 : : * Port configuration attributes to compare.
11444 : : * @param[in] new_nbq
11445 : : * Number of queues to compare.
11446 : : * @param[in] new_qa
11447 : : * Array that holds attributes for each flow queue.
11448 : : *
11449 : : * @return
11450 : : * True if configurations are the same, false otherwise.
11451 : : */
11452 : : static bool
11453 : 0 : flow_hw_compare_config(const struct mlx5_flow_hw_attr *hw_attr,
11454 : : const struct rte_flow_port_attr *new_pa,
11455 : : const uint16_t new_nbq,
11456 : : const struct rte_flow_queue_attr *new_qa[])
11457 : : {
11458 : : const struct rte_flow_port_attr *old_pa = &hw_attr->port_attr;
11459 : 0 : const uint16_t old_nbq = hw_attr->nb_queue;
11460 : 0 : const struct rte_flow_queue_attr *old_qa = hw_attr->queue_attr;
11461 : : unsigned int i;
11462 : :
11463 [ # # ]: 0 : if (old_pa->nb_counters != new_pa->nb_counters ||
11464 [ # # ]: 0 : old_pa->nb_aging_objects != new_pa->nb_aging_objects ||
11465 [ # # ]: 0 : old_pa->nb_meters != new_pa->nb_meters ||
11466 [ # # ]: 0 : old_pa->nb_conn_tracks != new_pa->nb_conn_tracks ||
11467 [ # # ]: 0 : old_pa->flags != new_pa->flags)
11468 : : return false;
11469 [ # # ]: 0 : if (old_nbq != new_nbq)
11470 : : return false;
11471 [ # # ]: 0 : for (i = 0; i < old_nbq; ++i)
11472 [ # # ]: 0 : if (old_qa[i].size != new_qa[i]->size)
11473 : : return false;
11474 : : return true;
11475 : : }
11476 : :
11477 : : /*
11478 : : * No need to explicitly release drop action templates on port stop.
11479 : : * Drop action templates release with other action templates during
11480 : : * mlx5_dev_close -> flow_hw_resource_release -> flow_hw_actions_template_destroy
11481 : : */
11482 : : static void
11483 : 0 : flow_hw_action_template_drop_release(struct rte_eth_dev *dev)
11484 : : {
11485 : : int i;
11486 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11487 : :
11488 [ # # ]: 0 : for (i = 0; i < MLX5DR_TABLE_TYPE_MAX; i++) {
11489 [ # # ]: 0 : if (!priv->action_template_drop[i])
11490 : 0 : continue;
11491 : 0 : flow_hw_actions_template_destroy(dev,
11492 : : priv->action_template_drop[i],
11493 : : NULL);
11494 : 0 : priv->action_template_drop[i] = NULL;
11495 : : }
11496 : 0 : }
11497 : :
11498 : : static int
11499 : 0 : flow_hw_action_template_drop_init(struct rte_eth_dev *dev,
11500 : : struct rte_flow_error *error)
11501 : : {
11502 : 0 : const struct rte_flow_action drop[2] = {
11503 : : [0] = { .type = RTE_FLOW_ACTION_TYPE_DROP },
11504 : : [1] = { .type = RTE_FLOW_ACTION_TYPE_END },
11505 : : };
11506 : : const struct rte_flow_action *actions = drop;
11507 : : const struct rte_flow_action *masks = drop;
11508 : 0 : const struct rte_flow_actions_template_attr attr[MLX5DR_TABLE_TYPE_MAX] = {
11509 : : [MLX5DR_TABLE_TYPE_NIC_RX] = { .ingress = 1 },
11510 : : [MLX5DR_TABLE_TYPE_NIC_TX] = { .egress = 1 },
11511 : : [MLX5DR_TABLE_TYPE_FDB] = { .transfer = 1 }
11512 : : };
11513 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11514 : :
11515 : 0 : priv->action_template_drop[MLX5DR_TABLE_TYPE_NIC_RX] =
11516 : : flow_hw_actions_template_create(dev,
11517 : : &attr[MLX5DR_TABLE_TYPE_NIC_RX],
11518 : : actions, masks, error);
11519 [ # # ]: 0 : if (!priv->action_template_drop[MLX5DR_TABLE_TYPE_NIC_RX])
11520 : : return -1;
11521 : 0 : priv->action_template_drop[MLX5DR_TABLE_TYPE_NIC_TX] =
11522 : : flow_hw_actions_template_create(dev,
11523 : : &attr[MLX5DR_TABLE_TYPE_NIC_TX],
11524 : : actions, masks, error);
11525 [ # # ]: 0 : if (!priv->action_template_drop[MLX5DR_TABLE_TYPE_NIC_TX])
11526 : : return -1;
11527 [ # # # # ]: 0 : if (priv->sh->config.dv_esw_en && priv->master) {
11528 : 0 : priv->action_template_drop[MLX5DR_TABLE_TYPE_FDB] =
11529 : : flow_hw_actions_template_create(dev,
11530 : : &attr[MLX5DR_TABLE_TYPE_FDB],
11531 : : actions, masks, error);
11532 [ # # ]: 0 : if (!priv->action_template_drop[MLX5DR_TABLE_TYPE_FDB])
11533 : 0 : return -1;
11534 : : }
11535 : : return 0;
11536 : : }
11537 : :
11538 : : static void
11539 : 0 : __flow_hw_resource_release(struct rte_eth_dev *dev, bool ctx_close)
11540 : : {
11541 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11542 : : struct rte_flow_template_table *tbl, *temp_tbl;
11543 : : struct rte_flow_pattern_template *it, *temp_it;
11544 : : struct rte_flow_actions_template *at, *temp_at;
11545 : : struct mlx5_flow_group *grp, *temp_grp;
11546 : : uint32_t i;
11547 : :
11548 : 0 : flow_hw_rxq_flag_set(dev, false);
11549 : 0 : flow_hw_flush_all_ctrl_flows(dev);
11550 : 0 : flow_hw_cleanup_ctrl_fdb_tables(dev);
11551 : 0 : flow_hw_cleanup_tx_repr_tagging(dev);
11552 : 0 : flow_hw_cleanup_ctrl_rx_tables(dev);
11553 : 0 : flow_hw_action_template_drop_release(dev);
11554 : 0 : grp = LIST_FIRST(&priv->flow_hw_grp);
11555 [ # # ]: 0 : while (grp) {
11556 : 0 : temp_grp = LIST_NEXT(grp, next);
11557 : 0 : claim_zero(flow_hw_group_unset_miss_group(dev, grp, NULL));
11558 : : grp = temp_grp;
11559 : : }
11560 : 0 : tbl = LIST_FIRST(&priv->flow_hw_tbl_ongo);
11561 [ # # ]: 0 : while (tbl) {
11562 : 0 : temp_tbl = LIST_NEXT(tbl, next);
11563 : 0 : claim_zero(flow_hw_table_destroy(dev, tbl, NULL));
11564 : : tbl = temp_tbl;
11565 : : }
11566 : 0 : tbl = LIST_FIRST(&priv->flow_hw_tbl);
11567 [ # # ]: 0 : while (tbl) {
11568 : 0 : temp_tbl = LIST_NEXT(tbl, next);
11569 : 0 : claim_zero(flow_hw_table_destroy(dev, tbl, NULL));
11570 : : tbl = temp_tbl;
11571 : : }
11572 : 0 : it = LIST_FIRST(&priv->flow_hw_itt);
11573 [ # # ]: 0 : while (it) {
11574 : 0 : temp_it = LIST_NEXT(it, next);
11575 : 0 : claim_zero(flow_hw_pattern_template_destroy(dev, it, NULL));
11576 : : it = temp_it;
11577 : : }
11578 : 0 : at = LIST_FIRST(&priv->flow_hw_at);
11579 [ # # ]: 0 : while (at) {
11580 : 0 : temp_at = LIST_NEXT(at, next);
11581 : 0 : claim_zero(flow_hw_actions_template_destroy(dev, at, NULL));
11582 : : at = temp_at;
11583 : : }
11584 [ # # ]: 0 : for (i = 0; i < MLX5_HW_ACTION_FLAG_MAX; i++) {
11585 [ # # ]: 0 : if (priv->hw_drop[i])
11586 : 0 : mlx5dr_action_destroy(priv->hw_drop[i]);
11587 [ # # ]: 0 : if (priv->hw_tag[i])
11588 : 0 : mlx5dr_action_destroy(priv->hw_tag[i]);
11589 : : }
11590 [ # # ]: 0 : if (priv->hw_def_miss)
11591 : 0 : mlx5dr_action_destroy(priv->hw_def_miss);
11592 : 0 : flow_hw_destroy_nat64_actions(priv);
11593 : 0 : flow_hw_destroy_vlan(dev);
11594 : 0 : flow_hw_destroy_send_to_kernel_action(priv);
11595 : 0 : flow_hw_free_vport_actions(priv);
11596 [ # # ]: 0 : if (priv->acts_ipool) {
11597 : 0 : mlx5_ipool_destroy(priv->acts_ipool);
11598 : 0 : priv->acts_ipool = NULL;
11599 : : }
11600 [ # # ]: 0 : if (priv->hws_age_req)
11601 : 0 : mlx5_hws_age_pool_destroy(priv);
11602 [ # # # # ]: 0 : if (!priv->shared_host && priv->hws_cpool) {
11603 : 0 : mlx5_hws_cnt_pool_destroy(priv->sh, priv->hws_cpool);
11604 : 0 : priv->hws_cpool = NULL;
11605 : : }
11606 [ # # ]: 0 : if (priv->hws_ctpool) {
11607 : 0 : flow_hw_ct_pool_destroy(dev, priv->hws_ctpool);
11608 : 0 : priv->hws_ctpool = NULL;
11609 : : }
11610 [ # # ]: 0 : if (priv->ct_mng) {
11611 : 0 : flow_hw_ct_mng_destroy(dev, priv->ct_mng);
11612 : 0 : priv->ct_mng = NULL;
11613 : : }
11614 : 0 : mlx5_flow_quota_destroy(dev);
11615 [ # # ]: 0 : if (priv->hw_q) {
11616 [ # # ]: 0 : for (i = 0; i < priv->nb_queue; i++) {
11617 : 0 : struct mlx5_hw_q *hwq = &priv->hw_q[i];
11618 : 0 : rte_ring_free(hwq->indir_iq);
11619 : 0 : rte_ring_free(hwq->indir_cq);
11620 : 0 : rte_ring_free(hwq->flow_transfer_pending);
11621 : 0 : rte_ring_free(hwq->flow_transfer_completed);
11622 : : }
11623 : 0 : mlx5_free(priv->hw_q);
11624 : 0 : priv->hw_q = NULL;
11625 : : }
11626 [ # # ]: 0 : if (ctx_close) {
11627 [ # # ]: 0 : if (priv->dr_ctx) {
11628 : 0 : claim_zero(mlx5dr_context_close(priv->dr_ctx));
11629 : 0 : priv->dr_ctx = NULL;
11630 : : }
11631 : : }
11632 [ # # ]: 0 : if (priv->shared_host) {
11633 : 0 : struct mlx5_priv *host_priv = priv->shared_host->data->dev_private;
11634 : 0 : rte_atomic_fetch_sub_explicit(&host_priv->shared_refcnt, 1,
11635 : : rte_memory_order_relaxed);
11636 : 0 : priv->shared_host = NULL;
11637 : : }
11638 [ # # ]: 0 : if (priv->hw_attr) {
11639 : 0 : mlx5_free(priv->hw_attr);
11640 : 0 : priv->hw_attr = NULL;
11641 : : }
11642 : 0 : priv->nb_queue = 0;
11643 : 0 : }
11644 : :
11645 : : static __rte_always_inline struct rte_ring *
11646 : : mlx5_hwq_ring_create(uint16_t port_id, uint32_t queue, uint32_t size, const char *str)
11647 : : {
11648 : : char mz_name[RTE_MEMZONE_NAMESIZE];
11649 : :
11650 : : snprintf(mz_name, sizeof(mz_name), "port_%u_%s_%u", port_id, str, queue);
11651 : 0 : return rte_ring_create(mz_name, size, SOCKET_ID_ANY,
11652 : : RING_F_SP_ENQ | RING_F_SC_DEQ | RING_F_EXACT_SZ);
11653 : : }
11654 : :
11655 : : static int
11656 : 0 : flow_hw_validate_attributes(const struct rte_flow_port_attr *port_attr,
11657 : : uint16_t nb_queue,
11658 : : const struct rte_flow_queue_attr *queue_attr[],
11659 : : bool nt_mode, struct rte_flow_error *error)
11660 : : {
11661 : : uint32_t size;
11662 : : unsigned int i;
11663 : :
11664 [ # # ]: 0 : if (port_attr == NULL)
11665 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11666 : : "Port attributes must be non-NULL");
11667 : :
11668 [ # # ]: 0 : if (nb_queue == 0 && !nt_mode)
11669 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11670 : : "At least one flow queue is required");
11671 : :
11672 [ # # ]: 0 : if (queue_attr == NULL)
11673 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11674 : : "Queue attributes must be non-NULL");
11675 : :
11676 : 0 : size = queue_attr[0]->size;
11677 [ # # ]: 0 : for (i = 1; i < nb_queue; ++i) {
11678 [ # # ]: 0 : if (queue_attr[i]->size != size)
11679 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11680 : : NULL,
11681 : : "All flow queues must have the same size");
11682 : : }
11683 : :
11684 : : return 0;
11685 : : }
11686 : :
11687 : : /**
11688 : : * Configure port HWS resources.
11689 : : *
11690 : : * @param[in] dev
11691 : : * Pointer to the rte_eth_dev structure.
11692 : : * @param[in] port_attr
11693 : : * Port configuration attributes.
11694 : : * @param[in] nb_queue
11695 : : * Number of queue.
11696 : : * @param[in] queue_attr
11697 : : * Array that holds attributes for each flow queue.
11698 : : * @param[in] nt_mode
11699 : : * Non-template mode.
11700 : : * @param[out] error
11701 : : * Pointer to error structure.
11702 : : *
11703 : : * @return
11704 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
11705 : : */
11706 : : static int
11707 : 0 : __flow_hw_configure(struct rte_eth_dev *dev,
11708 : : const struct rte_flow_port_attr *port_attr,
11709 : : uint16_t nb_queue,
11710 : : const struct rte_flow_queue_attr *queue_attr[],
11711 : : bool nt_mode,
11712 : : struct rte_flow_error *error)
11713 : : {
11714 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
11715 : : struct mlx5_priv *host_priv = NULL;
11716 : 0 : struct mlx5dr_context_attr dr_ctx_attr = {0};
11717 : : struct mlx5_hw_q *hw_q;
11718 : : struct mlx5_hw_q_job *job = NULL;
11719 : : uint32_t mem_size, i, j;
11720 : 0 : struct mlx5_indexed_pool_config cfg = {
11721 : : .size = sizeof(struct mlx5_action_construct_data),
11722 : : .trunk_size = 4096,
11723 : : .need_lock = 1,
11724 : 0 : .release_mem_en = !!priv->sh->config.reclaim_mode,
11725 : : .malloc = mlx5_malloc,
11726 : : .free = mlx5_free,
11727 : : .type = "mlx5_hw_action_construct_data",
11728 : : };
11729 : : /*
11730 : : * Adds one queue to be used by PMD.
11731 : : * The last queue will be used by the PMD.
11732 : : */
11733 : : uint16_t nb_q_updated = 0;
11734 : : struct rte_flow_queue_attr **_queue_attr = NULL;
11735 : 0 : struct rte_flow_queue_attr ctrl_queue_attr = {0};
11736 [ # # # # ]: 0 : bool is_proxy = !!(priv->sh->config.dv_esw_en && priv->master);
11737 : : int ret = 0;
11738 : : uint32_t action_flags;
11739 : : bool strict_queue = false;
11740 : :
11741 : 0 : error->type = RTE_FLOW_ERROR_TYPE_NONE;
11742 [ # # ]: 0 : if (mlx5dr_rule_get_handle_size() != MLX5_DR_RULE_SIZE) {
11743 : 0 : rte_errno = EINVAL;
11744 : 0 : goto err;
11745 : : }
11746 [ # # ]: 0 : if (flow_hw_validate_attributes(port_attr, nb_queue, queue_attr, nt_mode, error))
11747 : 0 : return -rte_errno;
11748 : : /*
11749 : : * Calling rte_flow_configure() again is allowed if
11750 : : * provided configuration matches the initially provided one,
11751 : : * or previous configuration was default non template one.
11752 : : */
11753 [ # # ]: 0 : if (priv->dr_ctx) {
11754 : : MLX5_ASSERT(priv->hw_attr != NULL);
11755 [ # # ]: 0 : for (i = 0; i < priv->nb_queue; i++) {
11756 : 0 : hw_q = &priv->hw_q[i];
11757 : : /* Make sure all queues are empty. */
11758 [ # # ]: 0 : if (hw_q->size != hw_q->job_idx) {
11759 : 0 : rte_errno = EBUSY;
11760 : 0 : goto err;
11761 : : }
11762 : : }
11763 : : /* If previous configuration was not default non template mode config. */
11764 [ # # ]: 0 : if (!priv->hw_attr->nt_mode) {
11765 [ # # ]: 0 : if (flow_hw_compare_config(priv->hw_attr, port_attr, nb_queue, queue_attr))
11766 : : return 0;
11767 : : else
11768 : 0 : return rte_flow_error_set(error, ENOTSUP,
11769 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11770 : : "Changing HWS configuration attributes "
11771 : : "is not supported");
11772 : : }
11773 : : /* Reconfiguration, need to release all resources from previous allocation. */
11774 : 0 : __flow_hw_resource_release(dev, true);
11775 : : }
11776 : 0 : priv->hw_attr = flow_hw_alloc_copy_config(port_attr, nb_queue, queue_attr, nt_mode, error);
11777 [ # # ]: 0 : if (!priv->hw_attr) {
11778 : 0 : ret = -rte_errno;
11779 : 0 : goto err;
11780 : : }
11781 : 0 : ctrl_queue_attr.size = queue_attr[0]->size;
11782 : 0 : nb_q_updated = nb_queue + 1;
11783 : 0 : _queue_attr = mlx5_malloc(MLX5_MEM_ZERO,
11784 : : nb_q_updated *
11785 : : sizeof(struct rte_flow_queue_attr *),
11786 : : 64, SOCKET_ID_ANY);
11787 [ # # ]: 0 : if (!_queue_attr) {
11788 : 0 : rte_errno = ENOMEM;
11789 : 0 : goto err;
11790 : : }
11791 : :
11792 : 0 : memcpy(_queue_attr, queue_attr, sizeof(void *) * nb_queue);
11793 : 0 : _queue_attr[nb_queue] = &ctrl_queue_attr;
11794 : 0 : priv->acts_ipool = mlx5_ipool_create(&cfg);
11795 [ # # ]: 0 : if (!priv->acts_ipool)
11796 : 0 : goto err;
11797 : : /* Allocate the queue job descriptor LIFO. */
11798 : 0 : mem_size = sizeof(priv->hw_q[0]) * nb_q_updated;
11799 [ # # ]: 0 : for (i = 0; i < nb_q_updated; i++) {
11800 : 0 : mem_size += (sizeof(struct mlx5_hw_q_job *) +
11801 : 0 : sizeof(struct mlx5_hw_q_job)) * _queue_attr[i]->size;
11802 : : }
11803 : 0 : priv->hw_q = mlx5_malloc(MLX5_MEM_ZERO, mem_size,
11804 : : 64, SOCKET_ID_ANY);
11805 [ # # ]: 0 : if (!priv->hw_q) {
11806 : 0 : rte_errno = ENOMEM;
11807 : 0 : goto err;
11808 : : }
11809 [ # # ]: 0 : for (i = 0; i < nb_q_updated; i++) {
11810 : 0 : priv->hw_q[i].job_idx = _queue_attr[i]->size;
11811 : 0 : priv->hw_q[i].size = _queue_attr[i]->size;
11812 : 0 : priv->hw_q[i].ongoing_flow_ops = 0;
11813 [ # # ]: 0 : if (i == 0)
11814 : 0 : priv->hw_q[i].job = (struct mlx5_hw_q_job **)
11815 : 0 : &priv->hw_q[nb_q_updated];
11816 : : else
11817 : 0 : priv->hw_q[i].job = (struct mlx5_hw_q_job **)&job[_queue_attr[i - 1]->size];
11818 : 0 : job = (struct mlx5_hw_q_job *)
11819 : 0 : &priv->hw_q[i].job[_queue_attr[i]->size];
11820 [ # # ]: 0 : for (j = 0; j < _queue_attr[i]->size; j++)
11821 : 0 : priv->hw_q[i].job[j] = &job[j];
11822 : : /* Notice ring name length is limited. */
11823 : 0 : priv->hw_q[i].indir_cq = mlx5_hwq_ring_create
11824 : 0 : (dev->data->port_id, i, _queue_attr[i]->size, "indir_act_cq");
11825 [ # # ]: 0 : if (!priv->hw_q[i].indir_cq)
11826 : 0 : goto err;
11827 : 0 : priv->hw_q[i].indir_iq = mlx5_hwq_ring_create
11828 : 0 : (dev->data->port_id, i, _queue_attr[i]->size, "indir_act_iq");
11829 [ # # ]: 0 : if (!priv->hw_q[i].indir_iq)
11830 : 0 : goto err;
11831 : 0 : priv->hw_q[i].flow_transfer_pending = mlx5_hwq_ring_create
11832 : 0 : (dev->data->port_id, i, _queue_attr[i]->size, "tx_pending");
11833 [ # # ]: 0 : if (!priv->hw_q[i].flow_transfer_pending)
11834 : 0 : goto err;
11835 : 0 : priv->hw_q[i].flow_transfer_completed = mlx5_hwq_ring_create
11836 : 0 : (dev->data->port_id, i, _queue_attr[i]->size, "tx_done");
11837 [ # # ]: 0 : if (!priv->hw_q[i].flow_transfer_completed)
11838 : 0 : goto err;
11839 : : }
11840 : 0 : dr_ctx_attr.pd = priv->sh->cdev->pd;
11841 : 0 : dr_ctx_attr.queues = nb_q_updated;
11842 : : /* Assign initial value of STC numbers for representors. */
11843 [ # # ]: 0 : if (priv->representor)
11844 : 0 : dr_ctx_attr.initial_log_stc_memory = MLX5_REPR_STC_MEMORY_LOG;
11845 : : /* Queue size should all be the same. Take the first one. */
11846 : 0 : dr_ctx_attr.queue_size = _queue_attr[0]->size;
11847 [ # # ]: 0 : if (port_attr->flags & RTE_FLOW_PORT_FLAG_SHARE_INDIRECT) {
11848 : : struct rte_eth_dev *host_dev = NULL;
11849 : : uint16_t port_id;
11850 : :
11851 : : MLX5_ASSERT(rte_eth_dev_is_valid_port(port_attr->host_port_id));
11852 [ # # ]: 0 : if (is_proxy) {
11853 : 0 : DRV_LOG(ERR, "cross vHCA shared mode not supported "
11854 : : "for E-Switch confgiurations");
11855 : 0 : rte_errno = ENOTSUP;
11856 : 0 : goto err;
11857 : : }
11858 [ # # ]: 0 : MLX5_ETH_FOREACH_DEV(port_id, dev->device) {
11859 [ # # ]: 0 : if (port_id == port_attr->host_port_id) {
11860 : 0 : host_dev = &rte_eth_devices[port_id];
11861 : 0 : break;
11862 : : }
11863 : : }
11864 [ # # ]: 0 : if (!host_dev || host_dev == dev ||
11865 [ # # # # ]: 0 : !host_dev->data || !host_dev->data->dev_private) {
11866 : 0 : DRV_LOG(ERR, "Invalid cross vHCA host port %u",
11867 : : port_attr->host_port_id);
11868 : 0 : rte_errno = EINVAL;
11869 : 0 : goto err;
11870 : : }
11871 : : host_priv = host_dev->data->dev_private;
11872 [ # # ]: 0 : if (host_priv->sh->cdev->ctx == priv->sh->cdev->ctx) {
11873 : 0 : DRV_LOG(ERR, "Sibling ports %u and %u do not "
11874 : : "require cross vHCA sharing mode",
11875 : : dev->data->port_id, port_attr->host_port_id);
11876 : 0 : rte_errno = EINVAL;
11877 : 0 : goto err;
11878 : : }
11879 [ # # ]: 0 : if (host_priv->shared_host) {
11880 : 0 : DRV_LOG(ERR, "Host port %u is not the sharing base",
11881 : : port_attr->host_port_id);
11882 : 0 : rte_errno = EINVAL;
11883 : 0 : goto err;
11884 : : }
11885 [ # # ]: 0 : if (port_attr->nb_counters ||
11886 [ # # ]: 0 : port_attr->nb_aging_objects ||
11887 [ # # ]: 0 : port_attr->nb_meters ||
11888 [ # # ]: 0 : port_attr->nb_conn_tracks) {
11889 : 0 : DRV_LOG(ERR,
11890 : : "Object numbers on guest port must be zeros");
11891 : 0 : rte_errno = EINVAL;
11892 : 0 : goto err;
11893 : : }
11894 : 0 : dr_ctx_attr.shared_ibv_ctx = host_priv->sh->cdev->ctx;
11895 : 0 : priv->shared_host = host_dev;
11896 : 0 : rte_atomic_fetch_add_explicit(&host_priv->shared_refcnt, 1,
11897 : : rte_memory_order_relaxed);
11898 : : }
11899 : : /* Set backward compatibale mode to support non template RTE FLOW API.*/
11900 : 0 : dr_ctx_attr.bwc = true;
11901 : 0 : priv->dr_ctx = mlx5dr_context_open(priv->sh->cdev->ctx, &dr_ctx_attr);
11902 : : /* rte_errno has been updated by HWS layer. */
11903 [ # # ]: 0 : if (!priv->dr_ctx)
11904 : 0 : goto err;
11905 : 0 : priv->nb_queue = nb_q_updated;
11906 : 0 : ret = flow_hw_action_template_drop_init(dev, error);
11907 [ # # ]: 0 : if (ret)
11908 : 0 : goto err;
11909 : 0 : ret = flow_hw_create_ctrl_rx_tables(dev);
11910 [ # # ]: 0 : if (ret) {
11911 : 0 : rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11912 : : "Failed to set up Rx control flow templates");
11913 : 0 : goto err;
11914 : : }
11915 : : /* Initialize quotas */
11916 [ # # # # : 0 : if (port_attr->nb_quotas || (host_priv && host_priv->quota_ctx.devx_obj)) {
# # ]
11917 : 0 : ret = mlx5_flow_quota_init(dev, port_attr->nb_quotas);
11918 [ # # ]: 0 : if (ret) {
11919 : 0 : rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11920 : : "Failed to initialize quota.");
11921 : 0 : goto err;
11922 : : }
11923 : : }
11924 : : /* Initialize meter library*/
11925 [ # # # # : 0 : if (port_attr->nb_meters || (host_priv && host_priv->hws_mpool))
# # ]
11926 [ # # ]: 0 : if (mlx5_flow_meter_init(dev, port_attr->nb_meters, 0, 0, nb_q_updated))
11927 : 0 : goto err;
11928 : : /* Add global actions. */
11929 [ # # ]: 0 : for (i = 0; i < MLX5_HW_ACTION_FLAG_MAX; i++) {
11930 : : uint32_t act_flags = 0;
11931 : :
11932 : 0 : act_flags = mlx5_hw_act_flag[i][0] | mlx5_hw_act_flag[i][1];
11933 [ # # ]: 0 : if (is_proxy)
11934 : 0 : act_flags |= mlx5_hw_act_flag[i][2];
11935 : 0 : priv->hw_drop[i] = mlx5dr_action_create_dest_drop(priv->dr_ctx, act_flags);
11936 [ # # ]: 0 : if (!priv->hw_drop[i])
11937 : 0 : goto err;
11938 : 0 : priv->hw_tag[i] = mlx5dr_action_create_tag
11939 : : (priv->dr_ctx, mlx5_hw_act_flag[i][0]);
11940 [ # # ]: 0 : if (!priv->hw_tag[i])
11941 : 0 : goto err;
11942 : : }
11943 [ # # # # ]: 0 : if (priv->sh->config.dv_esw_en && priv->sh->config.repr_matching) {
11944 : 0 : ret = flow_hw_setup_tx_repr_tagging(dev, error);
11945 [ # # ]: 0 : if (ret)
11946 : 0 : goto err;
11947 : : }
11948 : : /*
11949 : : * DEFAULT_MISS action have different behaviors in different domains.
11950 : : * In FDB, it will steering the packets to the E-switch manager.
11951 : : * In NIC Rx root, it will steering the packet to the kernel driver stack.
11952 : : * An action with all bits set in the flag can be created and the HWS
11953 : : * layer will translate it properly when being used in different rules.
11954 : : */
11955 : : action_flags = MLX5DR_ACTION_FLAG_ROOT_RX | MLX5DR_ACTION_FLAG_HWS_RX |
11956 : : MLX5DR_ACTION_FLAG_ROOT_TX | MLX5DR_ACTION_FLAG_HWS_TX;
11957 [ # # ]: 0 : if (is_proxy)
11958 : : action_flags |= (MLX5DR_ACTION_FLAG_ROOT_FDB | MLX5DR_ACTION_FLAG_HWS_FDB);
11959 : 0 : priv->hw_def_miss = mlx5dr_action_create_default_miss(priv->dr_ctx, action_flags);
11960 [ # # ]: 0 : if (!priv->hw_def_miss)
11961 : 0 : goto err;
11962 [ # # ]: 0 : if (is_proxy) {
11963 : 0 : ret = flow_hw_create_vport_actions(priv);
11964 [ # # ]: 0 : if (ret) {
11965 : 0 : rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11966 : : NULL, "Failed to create vport actions.");
11967 : 0 : goto err;
11968 : : }
11969 : 0 : ret = flow_hw_create_ctrl_tables(dev, error);
11970 [ # # ]: 0 : if (ret) {
11971 : 0 : rte_errno = -ret;
11972 : 0 : goto err;
11973 : : }
11974 : : }
11975 : : if (!priv->shared_host)
11976 : : flow_hw_create_send_to_kernel_actions(priv);
11977 [ # # # # : 0 : if (port_attr->nb_conn_tracks || (host_priv && host_priv->hws_ctpool)) {
# # ]
11978 [ # # ]: 0 : if (mlx5_flow_ct_init(dev, port_attr->nb_conn_tracks, nb_q_updated))
11979 : 0 : goto err;
11980 : : }
11981 [ # # # # : 0 : if (port_attr->nb_counters || (host_priv && host_priv->hws_cpool)) {
# # ]
11982 [ # # ]: 0 : struct mlx5_hws_cnt_pool *hws_cpool = host_priv ? host_priv->hws_cpool : NULL;
11983 : :
11984 : 0 : ret = mlx5_hws_cnt_pool_create(dev, port_attr->nb_counters,
11985 : : nb_queue, hws_cpool, error);
11986 [ # # ]: 0 : if (ret)
11987 : 0 : goto err;
11988 : : }
11989 [ # # ]: 0 : if (port_attr->nb_aging_objects) {
11990 [ # # ]: 0 : if (port_attr->nb_counters == 0) {
11991 : : /*
11992 : : * Aging management uses counter. Number counters
11993 : : * requesting should take into account a counter for
11994 : : * each flow rules containing AGE without counter.
11995 : : */
11996 : 0 : DRV_LOG(ERR, "Port %u AGE objects are requested (%u) "
11997 : : "without counters requesting.",
11998 : : dev->data->port_id,
11999 : : port_attr->nb_aging_objects);
12000 : 0 : rte_errno = EINVAL;
12001 : 0 : goto err;
12002 : : }
12003 [ # # ]: 0 : if (port_attr->flags & RTE_FLOW_PORT_FLAG_SHARE_INDIRECT) {
12004 : 0 : DRV_LOG(ERR, "Aging is not supported "
12005 : : "in cross vHCA sharing mode");
12006 : : ret = -ENOTSUP;
12007 : 0 : goto err;
12008 : : }
12009 : 0 : strict_queue = !!(port_attr->flags & RTE_FLOW_PORT_FLAG_STRICT_QUEUE);
12010 : 0 : ret = mlx5_hws_age_pool_init(dev, port_attr->nb_aging_objects,
12011 : : nb_queue, strict_queue);
12012 [ # # ]: 0 : if (ret < 0)
12013 : 0 : goto err;
12014 : : }
12015 : 0 : ret = flow_hw_create_vlan(dev);
12016 [ # # ]: 0 : if (ret) {
12017 : 0 : rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12018 : : NULL, "Failed to VLAN actions.");
12019 : 0 : goto err;
12020 : : }
12021 [ # # ]: 0 : if (flow_hw_create_nat64_actions(priv, error))
12022 : 0 : DRV_LOG(WARNING, "Cannot create NAT64 action on port %u, "
12023 : : "please check the FW version", dev->data->port_id);
12024 : : if (_queue_attr)
12025 : 0 : mlx5_free(_queue_attr);
12026 [ # # ]: 0 : if (port_attr->flags & RTE_FLOW_PORT_FLAG_STRICT_QUEUE)
12027 : 0 : priv->hws_strict_queue = 1;
12028 : 0 : dev->flow_fp_ops = &mlx5_flow_hw_fp_ops;
12029 : 0 : return 0;
12030 : 0 : err:
12031 : 0 : __flow_hw_resource_release(dev, true);
12032 [ # # ]: 0 : if (_queue_attr)
12033 : 0 : mlx5_free(_queue_attr);
12034 : : /* Do not overwrite the internal errno information. */
12035 [ # # # # ]: 0 : if (ret && error->type != RTE_FLOW_ERROR_TYPE_NONE)
12036 : : return ret;
12037 : 0 : return rte_flow_error_set(error, rte_errno,
12038 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12039 : : "fail to configure port");
12040 : : }
12041 : :
12042 : : /**
12043 : : * Configure port HWS resources.
12044 : : *
12045 : : * @param[in] dev
12046 : : * Pointer to the rte_eth_dev structure.
12047 : : * @param[in] port_attr
12048 : : * Port configuration attributes.
12049 : : * @param[in] nb_queue
12050 : : * Number of queue.
12051 : : * @param[in] queue_attr
12052 : : * Array that holds attributes for each flow queue.
12053 : : * @param[out] error
12054 : : * Pointer to error structure.
12055 : : *
12056 : : * @return
12057 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
12058 : : */
12059 : : static int
12060 : 0 : flow_hw_configure(struct rte_eth_dev *dev,
12061 : : const struct rte_flow_port_attr *port_attr,
12062 : : uint16_t nb_queue,
12063 : : const struct rte_flow_queue_attr *queue_attr[],
12064 : : struct rte_flow_error *error)
12065 : : {
12066 : 0 : struct rte_flow_error shadow_error = {0, };
12067 : :
12068 [ # # ]: 0 : if (!error)
12069 : : error = &shadow_error;
12070 : 0 : return __flow_hw_configure(dev, port_attr, nb_queue, queue_attr, false, error);
12071 : : }
12072 : :
12073 : : /**
12074 : : * Release HWS resources.
12075 : : *
12076 : : * @param[in] dev
12077 : : * Pointer to the rte_eth_dev structure.
12078 : : */
12079 : : void
12080 : 0 : flow_hw_resource_release(struct rte_eth_dev *dev)
12081 : : {
12082 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12083 : :
12084 [ # # ]: 0 : if (!priv->dr_ctx)
12085 : : return;
12086 : 0 : __flow_hw_resource_release(dev, false);
12087 : : }
12088 : :
12089 : : /* Sets vport tag and mask, for given port, used in HWS rules. */
12090 : : void
12091 : 0 : flow_hw_set_port_info(struct rte_eth_dev *dev)
12092 : : {
12093 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12094 : 0 : uint16_t port_id = dev->data->port_id;
12095 : : struct flow_hw_port_info *info;
12096 : :
12097 : : MLX5_ASSERT(port_id < RTE_MAX_ETHPORTS);
12098 : 0 : info = &mlx5_flow_hw_port_infos[port_id];
12099 : 0 : info->regc_mask = priv->vport_meta_mask;
12100 [ # # ]: 0 : info->regc_value = priv->vport_meta_tag;
12101 [ # # ]: 0 : info->is_wire = mlx5_is_port_on_mpesw_device(priv) ? priv->mpesw_uplink : priv->master;
12102 : 0 : }
12103 : :
12104 : : /* Clears vport tag and mask used for HWS rules. */
12105 : : void
12106 : 0 : flow_hw_clear_port_info(struct rte_eth_dev *dev)
12107 : : {
12108 : 0 : uint16_t port_id = dev->data->port_id;
12109 : : struct flow_hw_port_info *info;
12110 : :
12111 : : MLX5_ASSERT(port_id < RTE_MAX_ETHPORTS);
12112 : 0 : info = &mlx5_flow_hw_port_infos[port_id];
12113 : 0 : info->regc_mask = 0;
12114 : 0 : info->regc_value = 0;
12115 : 0 : info->is_wire = 0;
12116 : 0 : }
12117 : :
12118 : : static int
12119 : 0 : flow_hw_conntrack_destroy(struct rte_eth_dev *dev,
12120 : : uint32_t idx,
12121 : : struct rte_flow_error *error)
12122 : : {
12123 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12124 : 0 : struct mlx5_aso_ct_pool *pool = priv->hws_ctpool;
12125 : : struct mlx5_aso_ct_action *ct;
12126 : :
12127 [ # # ]: 0 : if (priv->shared_host)
12128 : 0 : return rte_flow_error_set(error, ENOTSUP,
12129 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12130 : : NULL,
12131 : : "CT destruction is not allowed to guest port");
12132 : 0 : ct = mlx5_ipool_get(pool->cts, idx);
12133 [ # # ]: 0 : if (!ct) {
12134 : 0 : return rte_flow_error_set(error, EINVAL,
12135 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12136 : : NULL,
12137 : : "Invalid CT destruction index");
12138 : : }
12139 : 0 : rte_atomic_store_explicit(&ct->state, ASO_CONNTRACK_FREE,
12140 : : rte_memory_order_relaxed);
12141 : 0 : mlx5_ipool_free(pool->cts, idx);
12142 : 0 : return 0;
12143 : : }
12144 : :
12145 : : static int
12146 : 0 : flow_hw_conntrack_query(struct rte_eth_dev *dev, uint32_t queue, uint32_t idx,
12147 : : struct rte_flow_action_conntrack *profile,
12148 : : void *user_data, bool push,
12149 : : struct rte_flow_error *error)
12150 : : {
12151 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12152 : 0 : struct mlx5_aso_ct_pool *pool = priv->hws_ctpool;
12153 : : struct mlx5_aso_ct_action *ct;
12154 : :
12155 [ # # ]: 0 : if (priv->shared_host)
12156 : 0 : return rte_flow_error_set(error, ENOTSUP,
12157 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12158 : : NULL,
12159 : : "CT query is not allowed to guest port");
12160 : 0 : ct = mlx5_ipool_get(pool->cts, idx);
12161 [ # # ]: 0 : if (!ct) {
12162 : 0 : return rte_flow_error_set(error, EINVAL,
12163 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12164 : : NULL,
12165 : : "Invalid CT query index");
12166 : : }
12167 : 0 : profile->peer_port = ct->peer;
12168 : 0 : profile->is_original_dir = ct->is_original;
12169 [ # # ]: 0 : if (mlx5_aso_ct_query_by_wqe(priv->sh, queue, ct, profile, user_data, push))
12170 : 0 : return rte_flow_error_set(error, EIO,
12171 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12172 : : NULL,
12173 : : "Failed to query CT context");
12174 : : return 0;
12175 : : }
12176 : :
12177 : :
12178 : : static int
12179 : 0 : flow_hw_conntrack_update(struct rte_eth_dev *dev, uint32_t queue,
12180 : : const struct rte_flow_modify_conntrack *action_conf,
12181 : : uint32_t idx, void *user_data, bool push,
12182 : : struct rte_flow_error *error)
12183 : : {
12184 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12185 : 0 : struct mlx5_aso_ct_pool *pool = priv->hws_ctpool;
12186 : : struct mlx5_aso_ct_action *ct;
12187 : : const struct rte_flow_action_conntrack *new_prf;
12188 : : int ret = 0;
12189 : :
12190 [ # # ]: 0 : if (priv->shared_host)
12191 : 0 : return rte_flow_error_set(error, ENOTSUP,
12192 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12193 : : NULL,
12194 : : "CT update is not allowed to guest port");
12195 : 0 : ct = mlx5_ipool_get(pool->cts, idx);
12196 [ # # ]: 0 : if (!ct) {
12197 : 0 : return rte_flow_error_set(error, EINVAL,
12198 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12199 : : NULL,
12200 : : "Invalid CT update index");
12201 : : }
12202 : 0 : new_prf = &action_conf->new_ct;
12203 [ # # ]: 0 : if (action_conf->direction)
12204 : 0 : ct->is_original = !!new_prf->is_original_dir;
12205 [ # # ]: 0 : if (action_conf->state) {
12206 : : /* Only validate the profile when it needs to be updated. */
12207 : 0 : ret = mlx5_validate_action_ct(dev, new_prf, error);
12208 [ # # ]: 0 : if (ret)
12209 : : return ret;
12210 : 0 : ret = mlx5_aso_ct_update_by_wqe(priv->sh, queue, ct, new_prf,
12211 : : user_data, push);
12212 [ # # ]: 0 : if (ret)
12213 : 0 : return rte_flow_error_set(error, EIO,
12214 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12215 : : NULL,
12216 : : "Failed to send CT context update WQE");
12217 [ # # ]: 0 : if (queue != MLX5_HW_INV_QUEUE)
12218 : : return 0;
12219 : : /* Block until ready or a failure in synchronous mode. */
12220 : 0 : ret = mlx5_aso_ct_available(priv->sh, queue, ct);
12221 [ # # ]: 0 : if (ret)
12222 : 0 : rte_flow_error_set(error, rte_errno,
12223 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12224 : : NULL,
12225 : : "Timeout to get the CT update");
12226 : : }
12227 : : return ret;
12228 : : }
12229 : :
12230 : : static struct rte_flow_action_handle *
12231 : 0 : flow_hw_conntrack_create(struct rte_eth_dev *dev, uint32_t queue,
12232 : : const struct rte_flow_action_conntrack *pro,
12233 : : void *user_data, bool push,
12234 : : struct rte_flow_error *error)
12235 : : {
12236 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12237 : 0 : struct mlx5_aso_ct_pool *pool = priv->hws_ctpool;
12238 : : struct mlx5_aso_ct_action *ct;
12239 : 0 : uint32_t ct_idx = 0;
12240 : : int ret;
12241 : : bool async = !!(queue != MLX5_HW_INV_QUEUE);
12242 : :
12243 [ # # ]: 0 : if (priv->shared_host) {
12244 : 0 : rte_flow_error_set(error, ENOTSUP,
12245 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12246 : : NULL,
12247 : : "CT create is not allowed to guest port");
12248 : 0 : return NULL;
12249 : : }
12250 [ # # ]: 0 : if (!pool) {
12251 : 0 : rte_flow_error_set(error, EINVAL,
12252 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12253 : : "CT is not enabled");
12254 : 0 : return 0;
12255 : : }
12256 : 0 : ct = mlx5_ipool_zmalloc(pool->cts, &ct_idx);
12257 [ # # ]: 0 : if (!ct) {
12258 : 0 : rte_flow_error_set(error, rte_errno,
12259 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12260 : : "Failed to allocate CT object");
12261 : 0 : return 0;
12262 : : }
12263 : 0 : ct->offset = ct_idx - 1;
12264 : 0 : ct->is_original = !!pro->is_original_dir;
12265 : 0 : ct->peer = pro->peer_port;
12266 : 0 : ct->pool = pool;
12267 [ # # ]: 0 : if (mlx5_aso_ct_update_by_wqe(priv->sh, queue, ct, pro, user_data, push)) {
12268 : 0 : mlx5_ipool_free(pool->cts, ct_idx);
12269 : 0 : rte_flow_error_set(error, EBUSY,
12270 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12271 : : "Failed to update CT");
12272 : 0 : return 0;
12273 : : }
12274 [ # # ]: 0 : if (!async) {
12275 : 0 : ret = mlx5_aso_ct_available(priv->sh, queue, ct);
12276 [ # # ]: 0 : if (ret) {
12277 : 0 : mlx5_ipool_free(pool->cts, ct_idx);
12278 : 0 : rte_flow_error_set(error, rte_errno,
12279 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12280 : : NULL,
12281 : : "Timeout to get the CT update");
12282 : 0 : return 0;
12283 : : }
12284 : : }
12285 : 0 : return MLX5_INDIRECT_ACT_HWS_CT_GEN_IDX(ct_idx);
12286 : : }
12287 : :
12288 : : /**
12289 : : * Validate shared action.
12290 : : *
12291 : : * @param[in] dev
12292 : : * Pointer to the rte_eth_dev structure.
12293 : : * @param[in] queue
12294 : : * Which queue to be used.
12295 : : * @param[in] attr
12296 : : * Operation attribute.
12297 : : * @param[in] conf
12298 : : * Indirect action configuration.
12299 : : * @param[in] action
12300 : : * rte_flow action detail.
12301 : : * @param[in] user_data
12302 : : * Pointer to the user_data.
12303 : : * @param[out] error
12304 : : * Pointer to error structure.
12305 : : *
12306 : : * @return
12307 : : * 0 on success, otherwise negative errno value.
12308 : : */
12309 : : static int
12310 : 0 : flow_hw_action_handle_validate(struct rte_eth_dev *dev, uint32_t queue,
12311 : : const struct rte_flow_op_attr *attr,
12312 : : const struct rte_flow_indir_action_conf *conf,
12313 : : const struct rte_flow_action *action,
12314 : : void *user_data,
12315 : : struct rte_flow_error *error)
12316 : : {
12317 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12318 : :
12319 : : RTE_SET_USED(attr);
12320 : : RTE_SET_USED(queue);
12321 : : RTE_SET_USED(user_data);
12322 [ # # # # : 0 : switch (action->type) {
# # # ]
12323 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
12324 [ # # ]: 0 : if (!priv->hws_age_req) {
12325 [ # # ]: 0 : if (flow_hw_allocate_actions(dev, MLX5_FLOW_ACTION_AGE,
12326 : : error))
12327 : 0 : return rte_flow_error_set
12328 : : (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
12329 : : NULL, "aging pool not initialized");
12330 : : }
12331 : : break;
12332 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
12333 [ # # ]: 0 : if (!priv->hws_cpool) {
12334 [ # # ]: 0 : if (flow_hw_allocate_actions(dev, MLX5_FLOW_ACTION_COUNT,
12335 : : error))
12336 : 0 : return rte_flow_error_set
12337 : : (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
12338 : : NULL, "counters pool not initialized");
12339 : : }
12340 : : break;
12341 : 0 : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
12342 [ # # ]: 0 : if (priv->hws_ctpool == NULL) {
12343 [ # # ]: 0 : if (flow_hw_allocate_actions(dev, MLX5_FLOW_ACTION_CT,
12344 : : error))
12345 : 0 : return rte_flow_error_set
12346 : : (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
12347 : : NULL, "CT pool not initialized");
12348 : : }
12349 : 0 : return mlx5_validate_action_ct(dev, action->conf, error);
12350 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
12351 : 0 : return flow_hw_validate_action_meter_mark(dev, action, true, error);
12352 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
12353 : 0 : return flow_dv_action_validate(dev, conf, action, error);
12354 : : case RTE_FLOW_ACTION_TYPE_QUOTA:
12355 : : return 0;
12356 : 0 : default:
12357 : 0 : return rte_flow_error_set(error, ENOTSUP,
12358 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12359 : : "action type not supported");
12360 : : }
12361 : : return 0;
12362 : : }
12363 : :
12364 : : static __rte_always_inline bool
12365 : : flow_hw_action_push(const struct rte_flow_op_attr *attr)
12366 : : {
12367 [ # # # # : 0 : return attr ? !attr->postpone : true;
# # # # #
# # # #
# ]
12368 : : }
12369 : :
12370 : : static __rte_always_inline struct mlx5_hw_q_job *
12371 : : flow_hw_action_job_init(struct mlx5_priv *priv, uint32_t queue,
12372 : : const struct rte_flow_action_handle *handle,
12373 : : void *user_data, void *query_data,
12374 : : enum mlx5_hw_job_type type,
12375 : : enum mlx5_hw_indirect_type indirect_type,
12376 : : struct rte_flow_error *error)
12377 : : {
12378 : : struct mlx5_hw_q_job *job;
12379 : :
12380 [ # # # # : 0 : if (queue == MLX5_HW_INV_QUEUE)
# # # # #
# # # #
# ]
12381 [ # # # # : 0 : queue = CTRL_QUEUE_ID(priv);
# # # # #
# # # ]
12382 : : job = flow_hw_job_get(priv, queue);
12383 [ # # # # : 0 : if (!job) {
# # # # #
# # # # #
# # # # #
# # # # #
# # # # ]
12384 : 0 : rte_flow_error_set(error, ENOMEM,
12385 : : RTE_FLOW_ERROR_TYPE_ACTION_NUM, NULL,
12386 : : "Action destroy failed due to queue full.");
12387 : 0 : return NULL;
12388 : : }
12389 : 0 : job->type = type;
12390 : 0 : job->action = handle;
12391 : 0 : job->user_data = user_data;
12392 : 0 : job->query.user = query_data;
12393 [ # # # # : 0 : job->indirect_type = indirect_type;
# # # # #
# # # ]
12394 : 0 : return job;
12395 : : }
12396 : :
12397 : : struct mlx5_hw_q_job *
12398 [ # # ]: 0 : mlx5_flow_action_job_init(struct mlx5_priv *priv, uint32_t queue,
12399 : : const struct rte_flow_action_handle *handle,
12400 : : void *user_data, void *query_data,
12401 : : enum mlx5_hw_job_type type,
12402 : : struct rte_flow_error *error)
12403 : : {
12404 : 0 : return flow_hw_action_job_init(priv, queue, handle, user_data, query_data,
12405 : : type, MLX5_HW_INDIRECT_TYPE_LEGACY, error);
12406 : : }
12407 : :
12408 : : static __rte_always_inline void
12409 : : flow_hw_action_finalize(struct rte_eth_dev *dev, uint32_t queue,
12410 : : struct mlx5_hw_q_job *job,
12411 : : bool push, bool aso, bool status)
12412 : : {
12413 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12414 : :
12415 [ # # ]: 0 : if (queue == MLX5_HW_INV_QUEUE)
12416 : 0 : queue = CTRL_QUEUE_ID(priv);
12417 [ # # # # : 0 : if (likely(status)) {
# # # # #
# # # ]
12418 : : /* 1. add new job to a queue */
12419 [ # # # # : 0 : if (!aso)
# # # # #
# ]
12420 [ # # # # : 0 : rte_ring_enqueue(push ?
# # # # #
# # # #
# ]
12421 : 0 : priv->hw_q[queue].indir_cq :
12422 : 0 : priv->hw_q[queue].indir_iq,
12423 : : job);
12424 : : /* 2. send pending jobs */
12425 [ # # # # : 0 : if (push)
# # # # #
# # # #
# ]
12426 : 0 : __flow_hw_push_action(dev, queue);
12427 : : } else {
12428 : : flow_hw_job_put(priv, job, queue);
12429 : : }
12430 : : }
12431 : :
12432 : : /**
12433 : : * Create shared action.
12434 : : *
12435 : : * @param[in] dev
12436 : : * Pointer to the rte_eth_dev structure.
12437 : : * @param[in] queue
12438 : : * Which queue to be used.
12439 : : * @param[in] attr
12440 : : * Operation attribute.
12441 : : * @param[in] conf
12442 : : * Indirect action configuration.
12443 : : * @param[in] action
12444 : : * rte_flow action detail.
12445 : : * @param[in] user_data
12446 : : * Pointer to the user_data.
12447 : : * @param[out] error
12448 : : * Pointer to error structure.
12449 : : *
12450 : : * @return
12451 : : * Action handle on success, NULL otherwise and rte_errno is set.
12452 : : */
12453 : : static struct rte_flow_action_handle *
12454 : 0 : flow_hw_action_handle_create(struct rte_eth_dev *dev, uint32_t queue,
12455 : : const struct rte_flow_op_attr *attr,
12456 : : const struct rte_flow_indir_action_conf *conf,
12457 : : const struct rte_flow_action *action,
12458 : : void *user_data,
12459 : : struct rte_flow_error *error)
12460 : : {
12461 : : struct rte_flow_action_handle *handle = NULL;
12462 : : struct mlx5_hw_q_job *job = NULL;
12463 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
12464 : : const struct rte_flow_action_age *age;
12465 : : struct mlx5_aso_mtr *aso_mtr;
12466 : : cnt_id_t cnt_id;
12467 : : uint32_t age_idx;
12468 : : bool push = flow_hw_action_push(attr);
12469 : : bool aso = false;
12470 : 0 : bool force_job = action->type == RTE_FLOW_ACTION_TYPE_METER_MARK;
12471 : :
12472 [ # # ]: 0 : if (!mlx5_hw_ctx_validate(dev, error))
12473 : : return NULL;
12474 [ # # ]: 0 : if (attr || force_job) {
12475 : : job = flow_hw_action_job_init(priv, queue, NULL, user_data,
12476 : : NULL, MLX5_HW_Q_JOB_TYPE_CREATE,
12477 : : MLX5_HW_INDIRECT_TYPE_LEGACY, error);
12478 : : if (!job)
12479 : 0 : return NULL;
12480 : : }
12481 [ # # # # : 0 : switch (action->type) {
# # # ]
12482 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
12483 [ # # ]: 0 : if (priv->hws_strict_queue) {
12484 : 0 : struct mlx5_age_info *info = GET_PORT_AGE_INFO(priv);
12485 : :
12486 [ # # ]: 0 : if (queue >= info->hw_q_age->nb_rings) {
12487 : 0 : rte_flow_error_set(error, EINVAL,
12488 : : RTE_FLOW_ERROR_TYPE_ACTION,
12489 : : NULL,
12490 : : "Invalid queue ID for indirect AGE.");
12491 : 0 : rte_errno = EINVAL;
12492 : 0 : return NULL;
12493 : : }
12494 : : }
12495 : 0 : age = action->conf;
12496 : 0 : age_idx = mlx5_hws_age_action_create(priv, queue, true, age,
12497 : : 0, error);
12498 [ # # ]: 0 : if (age_idx == 0) {
12499 : 0 : rte_flow_error_set(error, ENODEV,
12500 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12501 : : "AGE are not configured!");
12502 : : } else {
12503 : 0 : age_idx = (MLX5_INDIRECT_ACTION_TYPE_AGE <<
12504 : : MLX5_INDIRECT_ACTION_TYPE_OFFSET) | age_idx;
12505 : 0 : handle =
12506 : 0 : (struct rte_flow_action_handle *)(uintptr_t)age_idx;
12507 : : }
12508 : : break;
12509 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
12510 [ # # ]: 0 : if (mlx5_hws_cnt_shared_get(priv->hws_cpool, &cnt_id, 0))
12511 : 0 : rte_flow_error_set(error, ENODEV,
12512 : : RTE_FLOW_ERROR_TYPE_ACTION,
12513 : : NULL,
12514 : : "counter are not configured!");
12515 : : else
12516 : 0 : handle = (struct rte_flow_action_handle *)
12517 : 0 : (uintptr_t)cnt_id;
12518 : : break;
12519 : 0 : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
12520 : : aso = true;
12521 : 0 : handle = flow_hw_conntrack_create(dev, queue, action->conf, job,
12522 : : push, error);
12523 : 0 : break;
12524 [ # # ]: 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
12525 : : aso = true;
12526 : : aso_mtr = flow_hw_meter_mark_alloc(dev, queue, action, job, push, error);
12527 : : if (!aso_mtr)
12528 : : break;
12529 : 0 : handle = (void *)(uintptr_t)job->action;
12530 : 0 : break;
12531 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
12532 : 0 : handle = flow_dv_action_create(dev, conf, action, error);
12533 : 0 : break;
12534 : 0 : case RTE_FLOW_ACTION_TYPE_QUOTA:
12535 : : aso = true;
12536 : 0 : handle = mlx5_quota_alloc(dev, queue, action->conf,
12537 : : job, push, error);
12538 : 0 : break;
12539 : 0 : default:
12540 : 0 : rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
12541 : : NULL, "action type not supported");
12542 : 0 : break;
12543 : : }
12544 [ # # ]: 0 : if (job && !force_job) {
12545 : 0 : job->action = handle;
12546 [ # # ]: 0 : flow_hw_action_finalize(dev, queue, job, push, aso,
12547 : : handle != NULL);
12548 : : }
12549 : : return handle;
12550 : : }
12551 : :
12552 : : static int
12553 : 0 : mlx5_flow_update_meter_mark(struct rte_eth_dev *dev, uint32_t queue,
12554 : : const struct rte_flow_update_meter_mark *upd_meter_mark,
12555 : : uint32_t idx, bool push,
12556 : : struct mlx5_hw_q_job *job, struct rte_flow_error *error)
12557 : : {
12558 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12559 : 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
12560 : : const struct rte_flow_action_meter_mark *meter_mark = &upd_meter_mark->meter_mark;
12561 : 0 : struct mlx5_aso_mtr *aso_mtr = mlx5_ipool_get(pool->idx_pool, idx);
12562 : : struct mlx5_flow_meter_info *fm;
12563 : :
12564 [ # # ]: 0 : if (!aso_mtr)
12565 : 0 : return rte_flow_error_set(error, EINVAL,
12566 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12567 : : NULL, "Invalid meter_mark update index");
12568 : : fm = &aso_mtr->fm;
12569 [ # # ]: 0 : if (upd_meter_mark->profile_valid)
12570 : 0 : fm->profile = (struct mlx5_flow_meter_profile *)
12571 : 0 : (meter_mark->profile);
12572 [ # # ]: 0 : if (upd_meter_mark->color_mode_valid)
12573 : 0 : fm->color_aware = meter_mark->color_mode;
12574 [ # # ]: 0 : if (upd_meter_mark->state_valid)
12575 : 0 : fm->is_enable = meter_mark->state;
12576 [ # # ]: 0 : aso_mtr->state = (queue == MLX5_HW_INV_QUEUE) ?
12577 : : ASO_METER_WAIT : ASO_METER_WAIT_ASYNC;
12578 : : /* Update ASO flow meter by wqe. */
12579 [ # # ]: 0 : if (mlx5_aso_meter_update_by_wqe(priv, queue,
12580 : : aso_mtr, &priv->mtr_bulk, job, push))
12581 : 0 : return rte_flow_error_set(error, EINVAL,
12582 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12583 : : NULL, "Unable to update ASO meter WQE");
12584 : : /* Wait for ASO object completion. */
12585 [ # # # # ]: 0 : if (queue == MLX5_HW_INV_QUEUE &&
12586 : 0 : mlx5_aso_mtr_wait(priv, aso_mtr, true))
12587 : 0 : return rte_flow_error_set(error, EINVAL,
12588 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12589 : : NULL, "Unable to wait for ASO meter CQE");
12590 : : return 0;
12591 : : }
12592 : :
12593 : : /**
12594 : : * Update shared action.
12595 : : *
12596 : : * @param[in] dev
12597 : : * Pointer to the rte_eth_dev structure.
12598 : : * @param[in] queue
12599 : : * Which queue to be used.
12600 : : * @param[in] attr
12601 : : * Operation attribute.
12602 : : * @param[in] handle
12603 : : * Action handle to be updated.
12604 : : * @param[in] update
12605 : : * Update value.
12606 : : * @param[in] user_data
12607 : : * Pointer to the user_data.
12608 : : * @param[out] error
12609 : : * Pointer to error structure.
12610 : : *
12611 : : * @return
12612 : : * 0 on success, negative value otherwise and rte_errno is set.
12613 : : */
12614 : : static int
12615 : 0 : flow_hw_action_handle_update(struct rte_eth_dev *dev, uint32_t queue,
12616 : : const struct rte_flow_op_attr *attr,
12617 : : struct rte_flow_action_handle *handle,
12618 : : const void *update,
12619 : : void *user_data,
12620 : : struct rte_flow_error *error)
12621 : : {
12622 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12623 : : const struct rte_flow_modify_conntrack *ct_conf =
12624 : : (const struct rte_flow_modify_conntrack *)update;
12625 : : struct mlx5_hw_q_job *job = NULL;
12626 : 0 : uint32_t act_idx = (uint32_t)(uintptr_t)handle;
12627 : 0 : uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
12628 [ # # ]: 0 : uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
12629 : : int ret = 0;
12630 : : bool push = flow_hw_action_push(attr);
12631 : : bool aso = false;
12632 : 0 : bool force_job = type == MLX5_INDIRECT_ACTION_TYPE_METER_MARK;
12633 : :
12634 [ # # ]: 0 : if (attr || force_job) {
12635 : : job = flow_hw_action_job_init(priv, queue, handle, user_data,
12636 : : NULL, MLX5_HW_Q_JOB_TYPE_UPDATE,
12637 : : MLX5_HW_INDIRECT_TYPE_LEGACY, error);
12638 : : if (!job)
12639 : 0 : return -rte_errno;
12640 : : }
12641 [ # # # # : 0 : switch (type) {
# # ]
12642 : 0 : case MLX5_INDIRECT_ACTION_TYPE_AGE:
12643 : 0 : ret = mlx5_hws_age_action_update(priv, idx, update, error);
12644 : 0 : break;
12645 : 0 : case MLX5_INDIRECT_ACTION_TYPE_CT:
12646 [ # # ]: 0 : if (ct_conf->state)
12647 : : aso = true;
12648 : 0 : ret = flow_hw_conntrack_update(dev, queue, update, idx,
12649 : : job, push, error);
12650 : 0 : break;
12651 : 0 : case MLX5_INDIRECT_ACTION_TYPE_METER_MARK:
12652 : : aso = true;
12653 : 0 : ret = mlx5_flow_update_meter_mark(dev, queue, update, idx, push,
12654 : : job, error);
12655 : 0 : break;
12656 : 0 : case MLX5_INDIRECT_ACTION_TYPE_RSS:
12657 : 0 : ret = flow_dv_action_update(dev, handle, update, error);
12658 : 0 : break;
12659 : 0 : case MLX5_INDIRECT_ACTION_TYPE_QUOTA:
12660 : : aso = true;
12661 : 0 : ret = mlx5_quota_query_update(dev, queue, handle, update, NULL,
12662 : : job, push, error);
12663 : 0 : break;
12664 : 0 : default:
12665 : : ret = -ENOTSUP;
12666 : 0 : rte_flow_error_set(error, ENOTSUP,
12667 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12668 : : "action type not supported");
12669 : 0 : break;
12670 : : }
12671 [ # # ]: 0 : if (job && !force_job)
12672 [ # # ]: 0 : flow_hw_action_finalize(dev, queue, job, push, aso, ret == 0);
12673 : : return ret;
12674 : : }
12675 : :
12676 : : /**
12677 : : * Destroy shared action.
12678 : : *
12679 : : * @param[in] dev
12680 : : * Pointer to the rte_eth_dev structure.
12681 : : * @param[in] queue
12682 : : * Which queue to be used.
12683 : : * @param[in] attr
12684 : : * Operation attribute.
12685 : : * @param[in] handle
12686 : : * Action handle to be destroyed.
12687 : : * @param[in] user_data
12688 : : * Pointer to the user_data.
12689 : : * @param[out] error
12690 : : * Pointer to error structure.
12691 : : *
12692 : : * @return
12693 : : * 0 on success, negative value otherwise and rte_errno is set.
12694 : : */
12695 : : static int
12696 : 0 : flow_hw_action_handle_destroy(struct rte_eth_dev *dev, uint32_t queue,
12697 : : const struct rte_flow_op_attr *attr,
12698 : : struct rte_flow_action_handle *handle,
12699 : : void *user_data,
12700 : : struct rte_flow_error *error)
12701 : : {
12702 : 0 : uint32_t act_idx = (uint32_t)(uintptr_t)handle;
12703 : 0 : uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
12704 : 0 : uint32_t age_idx = act_idx & MLX5_HWS_AGE_IDX_MASK;
12705 : : uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
12706 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12707 [ # # ]: 0 : struct mlx5_aso_mtr_pool *pool = priv->hws_mpool;
12708 : : struct mlx5_hw_q_job *job = NULL;
12709 : : struct mlx5_aso_mtr *aso_mtr;
12710 : : struct mlx5_flow_meter_info *fm;
12711 : : bool push = flow_hw_action_push(attr);
12712 : : bool aso = false;
12713 : : int ret = 0;
12714 : 0 : bool force_job = type == MLX5_INDIRECT_ACTION_TYPE_METER_MARK;
12715 : :
12716 [ # # ]: 0 : if (attr || force_job) {
12717 : : job = flow_hw_action_job_init(priv, queue, handle, user_data,
12718 : : NULL, MLX5_HW_Q_JOB_TYPE_DESTROY,
12719 : : MLX5_HW_INDIRECT_TYPE_LEGACY, error);
12720 : : if (!job)
12721 : 0 : return -rte_errno;
12722 : : }
12723 [ # # # # : 0 : switch (type) {
# # # ]
12724 : 0 : case MLX5_INDIRECT_ACTION_TYPE_AGE:
12725 : 0 : ret = mlx5_hws_age_action_destroy(priv, age_idx, error);
12726 : 0 : break;
12727 : 0 : case MLX5_INDIRECT_ACTION_TYPE_COUNT:
12728 [ # # ]: 0 : age_idx = mlx5_hws_cnt_age_get(priv->hws_cpool, act_idx);
12729 [ # # ]: 0 : if (age_idx != 0)
12730 : : /*
12731 : : * If this counter belongs to indirect AGE, here is the
12732 : : * time to update the AGE.
12733 : : */
12734 : : mlx5_hws_age_nb_cnt_decrease(priv, age_idx);
12735 [ # # ]: 0 : mlx5_hws_cnt_shared_put(priv->hws_cpool, &act_idx);
12736 : : break;
12737 : 0 : case MLX5_INDIRECT_ACTION_TYPE_CT:
12738 : 0 : ret = flow_hw_conntrack_destroy(dev, idx, error);
12739 : 0 : break;
12740 : 0 : case MLX5_INDIRECT_ACTION_TYPE_METER_MARK:
12741 : 0 : aso_mtr = mlx5_ipool_get(pool->idx_pool, idx);
12742 [ # # ]: 0 : if (!aso_mtr) {
12743 : : ret = -EINVAL;
12744 : 0 : rte_flow_error_set(error, EINVAL,
12745 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12746 : : NULL, "Invalid meter_mark destroy index");
12747 : 0 : break;
12748 : : }
12749 : : fm = &aso_mtr->fm;
12750 : 0 : fm->is_enable = 0;
12751 : : /* Update ASO flow meter by wqe. */
12752 [ # # ]: 0 : if (mlx5_aso_meter_update_by_wqe(priv, queue, aso_mtr,
12753 : : &priv->mtr_bulk, job, push)) {
12754 : : ret = -EINVAL;
12755 : 0 : rte_flow_error_set(error, EINVAL,
12756 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12757 : : NULL, "Unable to update ASO meter WQE");
12758 : 0 : break;
12759 : : }
12760 : : /* Wait for ASO object completion. */
12761 [ # # # # ]: 0 : if (queue == MLX5_HW_INV_QUEUE &&
12762 : 0 : mlx5_aso_mtr_wait(priv, aso_mtr, true)) {
12763 : : ret = -EINVAL;
12764 : 0 : rte_flow_error_set(error, EINVAL,
12765 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12766 : : NULL, "Unable to wait for ASO meter CQE");
12767 : 0 : break;
12768 : : }
12769 : : aso = true;
12770 : : break;
12771 : 0 : case MLX5_INDIRECT_ACTION_TYPE_RSS:
12772 : 0 : ret = flow_dv_action_destroy(dev, handle, error);
12773 : 0 : break;
12774 : : case MLX5_INDIRECT_ACTION_TYPE_QUOTA:
12775 : : break;
12776 : 0 : default:
12777 : : ret = -ENOTSUP;
12778 : 0 : rte_flow_error_set(error, ENOTSUP,
12779 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12780 : : "action type not supported");
12781 : 0 : break;
12782 : : }
12783 [ # # ]: 0 : if (job && !force_job)
12784 [ # # ]: 0 : flow_hw_action_finalize(dev, queue, job, push, aso, ret == 0);
12785 : : return ret;
12786 : : }
12787 : :
12788 : : static int
12789 : 0 : flow_hw_query_counter(const struct rte_eth_dev *dev, uint32_t counter,
12790 : : void *data, struct rte_flow_error *error)
12791 : : {
12792 : : struct mlx5_hws_cnt_pool *hpool;
12793 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
12794 : : struct mlx5_hws_cnt *cnt;
12795 : : struct rte_flow_query_count *qc = data;
12796 : : uint32_t iidx;
12797 : : uint64_t pkts, bytes;
12798 : :
12799 [ # # ]: 0 : if (!mlx5_hws_cnt_id_valid(counter))
12800 : 0 : return rte_flow_error_set(error, EINVAL,
12801 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12802 : : "counter are not available");
12803 [ # # ]: 0 : hpool = mlx5_hws_cnt_host_pool(priv->hws_cpool);
12804 : : iidx = mlx5_hws_cnt_iidx(hpool, counter);
12805 : 0 : cnt = &hpool->pool[iidx];
12806 : : __hws_cnt_query_raw(priv->hws_cpool, counter, &pkts, &bytes);
12807 : 0 : qc->hits_set = 1;
12808 : 0 : qc->bytes_set = 1;
12809 : 0 : qc->hits = pkts - cnt->reset.hits;
12810 : 0 : qc->bytes = bytes - cnt->reset.bytes;
12811 [ # # ]: 0 : if (qc->reset) {
12812 : 0 : cnt->reset.bytes = bytes;
12813 : 0 : cnt->reset.hits = pkts;
12814 : : }
12815 : : return 0;
12816 : : }
12817 : :
12818 : : /**
12819 : : * Query a flow rule AGE action for aging information.
12820 : : *
12821 : : * @param[in] dev
12822 : : * Pointer to Ethernet device.
12823 : : * @param[in] age_idx
12824 : : * Index of AGE action parameter.
12825 : : * @param[out] data
12826 : : * Data retrieved by the query.
12827 : : * @param[out] error
12828 : : * Perform verbose error reporting if not NULL.
12829 : : *
12830 : : * @return
12831 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
12832 : : */
12833 : : static int
12834 : 0 : flow_hw_query_age(const struct rte_eth_dev *dev, uint32_t age_idx, void *data,
12835 : : struct rte_flow_error *error)
12836 : : {
12837 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
12838 : 0 : struct mlx5_age_info *age_info = GET_PORT_AGE_INFO(priv);
12839 : 0 : struct mlx5_indexed_pool *ipool = age_info->ages_ipool;
12840 : 0 : struct mlx5_hws_age_param *param = mlx5_ipool_get(ipool, age_idx);
12841 : : struct rte_flow_query_age *resp = data;
12842 : :
12843 [ # # # # ]: 0 : if (!param || !param->timeout)
12844 : 0 : return rte_flow_error_set(error, EINVAL,
12845 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12846 : : NULL, "age data not available");
12847 [ # # # ]: 0 : switch (rte_atomic_load_explicit(¶m->state, rte_memory_order_relaxed)) {
12848 : 0 : case HWS_AGE_AGED_OUT_REPORTED:
12849 : : case HWS_AGE_AGED_OUT_NOT_REPORTED:
12850 : 0 : resp->aged = 1;
12851 : 0 : break;
12852 : 0 : case HWS_AGE_CANDIDATE:
12853 : : case HWS_AGE_CANDIDATE_INSIDE_RING:
12854 : 0 : resp->aged = 0;
12855 : 0 : break;
12856 : : case HWS_AGE_FREE:
12857 : : /*
12858 : : * When state is FREE the flow itself should be invalid.
12859 : : * Fall-through.
12860 : : */
12861 : : default:
12862 : : MLX5_ASSERT(0);
12863 : : break;
12864 : : }
12865 : 0 : resp->sec_since_last_hit_valid = !resp->aged;
12866 [ # # ]: 0 : if (resp->sec_since_last_hit_valid)
12867 : 0 : resp->sec_since_last_hit = rte_atomic_load_explicit
12868 : : (¶m->sec_since_last_hit, rte_memory_order_relaxed);
12869 : : return 0;
12870 : : }
12871 : :
12872 : : static int
12873 : 0 : flow_hw_query(struct rte_eth_dev *dev, struct rte_flow *flow,
12874 : : const struct rte_flow_action *actions, void *data,
12875 : : struct rte_flow_error *error)
12876 : : {
12877 : : int ret = -EINVAL;
12878 : : struct rte_flow_hw *hw_flow = (struct rte_flow_hw *)flow;
12879 : : struct rte_flow_hw_aux *aux;
12880 : :
12881 [ # # ]: 0 : for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
12882 [ # # # # ]: 0 : switch (actions->type) {
12883 : : case RTE_FLOW_ACTION_TYPE_VOID:
12884 : : break;
12885 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
12886 [ # # ]: 0 : if (!(hw_flow->flags & MLX5_FLOW_HW_FLOW_FLAG_CNT_ID))
12887 : 0 : return rte_flow_error_set(error, EINVAL,
12888 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12889 : : "counter not defined in the rule");
12890 : 0 : ret = flow_hw_query_counter(dev, hw_flow->cnt_id, data,
12891 : : error);
12892 : 0 : break;
12893 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
12894 [ # # ]: 0 : if (!(hw_flow->flags & MLX5_FLOW_HW_FLOW_FLAG_AGE_IDX))
12895 : 0 : return rte_flow_error_set(error, EINVAL,
12896 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12897 : : "age data not available");
12898 : 0 : aux = mlx5_flow_hw_aux(dev->data->port_id, hw_flow);
12899 : 0 : ret = flow_hw_query_age(dev, mlx5_flow_hw_aux_get_age_idx(hw_flow, aux),
12900 : : data, error);
12901 : 0 : break;
12902 : 0 : default:
12903 : 0 : return rte_flow_error_set(error, ENOTSUP,
12904 : : RTE_FLOW_ERROR_TYPE_ACTION,
12905 : : actions,
12906 : : "action not supported");
12907 : : }
12908 : : }
12909 : : return ret;
12910 : : }
12911 : :
12912 : : /**
12913 : : * Validate indirect action.
12914 : : *
12915 : : * @param[in] dev
12916 : : * Pointer to the Ethernet device structure.
12917 : : * @param[in] conf
12918 : : * Shared action configuration.
12919 : : * @param[in] action
12920 : : * Action specification used to create indirect action.
12921 : : * @param[out] error
12922 : : * Perform verbose error reporting if not NULL. Initialized in case of
12923 : : * error only.
12924 : : *
12925 : : * @return
12926 : : * 0 on success, otherwise negative errno value.
12927 : : */
12928 : : static int
12929 : 0 : flow_hw_action_validate(struct rte_eth_dev *dev,
12930 : : const struct rte_flow_indir_action_conf *conf,
12931 : : const struct rte_flow_action *action,
12932 : : struct rte_flow_error *err)
12933 : : {
12934 : 0 : struct rte_flow_error shadow_error = {0, };
12935 : :
12936 [ # # ]: 0 : if (!err)
12937 : : err = &shadow_error;
12938 : 0 : return flow_hw_action_handle_validate(dev, MLX5_HW_INV_QUEUE, NULL,
12939 : : conf, action, NULL, err);
12940 : : }
12941 : :
12942 : : /**
12943 : : * Create indirect action.
12944 : : *
12945 : : * @param[in] dev
12946 : : * Pointer to the Ethernet device structure.
12947 : : * @param[in] conf
12948 : : * Shared action configuration.
12949 : : * @param[in] action
12950 : : * Action specification used to create indirect action.
12951 : : * @param[out] error
12952 : : * Perform verbose error reporting if not NULL. Initialized in case of
12953 : : * error only.
12954 : : *
12955 : : * @return
12956 : : * A valid shared action handle in case of success, NULL otherwise and
12957 : : * rte_errno is set.
12958 : : */
12959 : : static struct rte_flow_action_handle *
12960 : 0 : flow_hw_action_create(struct rte_eth_dev *dev,
12961 : : const struct rte_flow_indir_action_conf *conf,
12962 : : const struct rte_flow_action *action,
12963 : : struct rte_flow_error *err)
12964 : : {
12965 : 0 : return flow_hw_action_handle_create(dev, MLX5_HW_INV_QUEUE,
12966 : : NULL, conf, action, NULL, err);
12967 : : }
12968 : :
12969 : : /**
12970 : : * Destroy the indirect action.
12971 : : * Release action related resources on the NIC and the memory.
12972 : : * Lock free, (mutex should be acquired by caller).
12973 : : * Dispatcher for action type specific call.
12974 : : *
12975 : : * @param[in] dev
12976 : : * Pointer to the Ethernet device structure.
12977 : : * @param[in] handle
12978 : : * The indirect action object handle to be removed.
12979 : : * @param[out] error
12980 : : * Perform verbose error reporting if not NULL. Initialized in case of
12981 : : * error only.
12982 : : *
12983 : : * @return
12984 : : * 0 on success, otherwise negative errno value.
12985 : : */
12986 : : static int
12987 : 0 : flow_hw_action_destroy(struct rte_eth_dev *dev,
12988 : : struct rte_flow_action_handle *handle,
12989 : : struct rte_flow_error *error)
12990 : : {
12991 : 0 : return flow_hw_action_handle_destroy(dev, MLX5_HW_INV_QUEUE,
12992 : : NULL, handle, NULL, error);
12993 : : }
12994 : :
12995 : : /**
12996 : : * Updates in place shared action configuration.
12997 : : *
12998 : : * @param[in] dev
12999 : : * Pointer to the Ethernet device structure.
13000 : : * @param[in] handle
13001 : : * The indirect action object handle to be updated.
13002 : : * @param[in] update
13003 : : * Action specification used to modify the action pointed by *handle*.
13004 : : * *update* could be of same type with the action pointed by the *handle*
13005 : : * handle argument, or some other structures like a wrapper, depending on
13006 : : * the indirect action type.
13007 : : * @param[out] error
13008 : : * Perform verbose error reporting if not NULL. Initialized in case of
13009 : : * error only.
13010 : : *
13011 : : * @return
13012 : : * 0 on success, otherwise negative errno value.
13013 : : */
13014 : : static int
13015 : 0 : flow_hw_action_update(struct rte_eth_dev *dev,
13016 : : struct rte_flow_action_handle *handle,
13017 : : const void *update,
13018 : : struct rte_flow_error *err)
13019 : : {
13020 : 0 : return flow_hw_action_handle_update(dev, MLX5_HW_INV_QUEUE,
13021 : : NULL, handle, update, NULL, err);
13022 : : }
13023 : :
13024 : : static int
13025 : 0 : flow_hw_action_handle_query(struct rte_eth_dev *dev, uint32_t queue,
13026 : : const struct rte_flow_op_attr *attr,
13027 : : const struct rte_flow_action_handle *handle,
13028 : : void *data, void *user_data,
13029 : : struct rte_flow_error *error)
13030 : : {
13031 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13032 : : struct mlx5_hw_q_job *job = NULL;
13033 : 0 : uint32_t act_idx = (uint32_t)(uintptr_t)handle;
13034 : 0 : uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
13035 [ # # ]: 0 : uint32_t idx = MLX5_INDIRECT_ACTION_IDX_GET(handle);
13036 : : uint32_t age_idx = act_idx & MLX5_HWS_AGE_IDX_MASK;
13037 : : int ret;
13038 : : bool push = flow_hw_action_push(attr);
13039 : : bool aso = false;
13040 : :
13041 [ # # ]: 0 : if (attr) {
13042 : : job = flow_hw_action_job_init(priv, queue, handle, user_data,
13043 : : data, MLX5_HW_Q_JOB_TYPE_QUERY,
13044 : : MLX5_HW_INDIRECT_TYPE_LEGACY, error);
13045 : : if (!job)
13046 : 0 : return -rte_errno;
13047 : : }
13048 [ # # # # : 0 : switch (type) {
# ]
13049 : 0 : case MLX5_INDIRECT_ACTION_TYPE_AGE:
13050 : 0 : ret = flow_hw_query_age(dev, age_idx, data, error);
13051 : 0 : break;
13052 : 0 : case MLX5_INDIRECT_ACTION_TYPE_COUNT:
13053 : 0 : ret = flow_hw_query_counter(dev, act_idx, data, error);
13054 : 0 : break;
13055 : 0 : case MLX5_INDIRECT_ACTION_TYPE_CT:
13056 : : aso = true;
13057 [ # # ]: 0 : if (job)
13058 : 0 : job->query.user = data;
13059 : 0 : ret = flow_hw_conntrack_query(dev, queue, idx, data,
13060 : : job, push, error);
13061 : 0 : break;
13062 : 0 : case MLX5_INDIRECT_ACTION_TYPE_QUOTA:
13063 : : aso = true;
13064 : 0 : ret = mlx5_quota_query(dev, queue, handle, data,
13065 : : job, push, error);
13066 : 0 : break;
13067 : 0 : default:
13068 : : ret = -ENOTSUP;
13069 : 0 : rte_flow_error_set(error, ENOTSUP,
13070 : : RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13071 : : "action type not supported");
13072 : 0 : break;
13073 : : }
13074 [ # # ]: 0 : if (job)
13075 [ # # ]: 0 : flow_hw_action_finalize(dev, queue, job, push, aso, ret == 0);
13076 : : return ret;
13077 : : }
13078 : :
13079 : : static int
13080 : 0 : flow_hw_async_action_handle_query_update
13081 : : (struct rte_eth_dev *dev, uint32_t queue,
13082 : : const struct rte_flow_op_attr *attr,
13083 : : struct rte_flow_action_handle *handle,
13084 : : const void *update, void *query,
13085 : : enum rte_flow_query_update_mode qu_mode,
13086 : : void *user_data, struct rte_flow_error *error)
13087 : : {
13088 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
13089 : : bool push = flow_hw_action_push(attr);
13090 : : bool aso = false;
13091 : : struct mlx5_hw_q_job *job = NULL;
13092 : : int ret = 0;
13093 : :
13094 [ # # ]: 0 : if (attr) {
13095 : : job = flow_hw_action_job_init(priv, queue, handle, user_data,
13096 : : query,
13097 : : MLX5_HW_Q_JOB_TYPE_UPDATE_QUERY,
13098 : : MLX5_HW_INDIRECT_TYPE_LEGACY, error);
13099 : : if (!job)
13100 : 0 : return -rte_errno;
13101 : : }
13102 [ # # ]: 0 : switch (MLX5_INDIRECT_ACTION_TYPE_GET(handle)) {
13103 : 0 : case MLX5_INDIRECT_ACTION_TYPE_QUOTA:
13104 [ # # ]: 0 : if (qu_mode != RTE_FLOW_QU_QUERY_FIRST) {
13105 : 0 : ret = rte_flow_error_set
13106 : : (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION_CONF,
13107 : : NULL, "quota action must query before update");
13108 : 0 : break;
13109 : : }
13110 : : aso = true;
13111 : 0 : ret = mlx5_quota_query_update(dev, queue, handle,
13112 : : update, query, job, push, error);
13113 : 0 : break;
13114 : 0 : default:
13115 : 0 : ret = rte_flow_error_set(error, ENOTSUP,
13116 : : RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, "update and query not supportred");
13117 : : }
13118 [ # # ]: 0 : if (job)
13119 [ # # ]: 0 : flow_hw_action_finalize(dev, queue, job, push, aso, ret == 0);
13120 : : return ret;
13121 : : }
13122 : :
13123 : : static int
13124 : 0 : flow_hw_action_query(struct rte_eth_dev *dev,
13125 : : const struct rte_flow_action_handle *handle, void *data,
13126 : : struct rte_flow_error *error)
13127 : : {
13128 : 0 : return flow_hw_action_handle_query(dev, MLX5_HW_INV_QUEUE, NULL,
13129 : : handle, data, NULL, error);
13130 : : }
13131 : :
13132 : : static int
13133 : 0 : flow_hw_action_query_update(struct rte_eth_dev *dev,
13134 : : struct rte_flow_action_handle *handle,
13135 : : const void *update, void *query,
13136 : : enum rte_flow_query_update_mode qu_mode,
13137 : : struct rte_flow_error *error)
13138 : : {
13139 : 0 : return flow_hw_async_action_handle_query_update(dev, MLX5_HW_INV_QUEUE,
13140 : : NULL, handle, update,
13141 : : query, qu_mode, NULL,
13142 : : error);
13143 : : }
13144 : :
13145 : : /**
13146 : : * Get aged-out flows of a given port on the given HWS flow queue.
13147 : : *
13148 : : * @param[in] dev
13149 : : * Pointer to the Ethernet device structure.
13150 : : * @param[in] queue_id
13151 : : * Flow queue to query. Ignored when RTE_FLOW_PORT_FLAG_STRICT_QUEUE not set.
13152 : : * @param[in, out] contexts
13153 : : * The address of an array of pointers to the aged-out flows contexts.
13154 : : * @param[in] nb_contexts
13155 : : * The length of context array pointers.
13156 : : * @param[out] error
13157 : : * Perform verbose error reporting if not NULL. Initialized in case of
13158 : : * error only.
13159 : : *
13160 : : * @return
13161 : : * if nb_contexts is 0, return the amount of all aged contexts.
13162 : : * if nb_contexts is not 0 , return the amount of aged flows reported
13163 : : * in the context array, otherwise negative errno value.
13164 : : */
13165 : : static int
13166 : 0 : flow_hw_get_q_aged_flows(struct rte_eth_dev *dev, uint32_t queue_id,
13167 : : void **contexts, uint32_t nb_contexts,
13168 : : struct rte_flow_error *error)
13169 : : {
13170 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13171 : 0 : struct mlx5_age_info *age_info = GET_PORT_AGE_INFO(priv);
13172 : : struct rte_ring *r;
13173 : : int nb_flows = 0;
13174 : :
13175 [ # # ]: 0 : if (nb_contexts && !contexts)
13176 : 0 : return rte_flow_error_set(error, EINVAL,
13177 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13178 : : NULL, "empty context");
13179 [ # # ]: 0 : if (!priv->hws_age_req)
13180 : 0 : return rte_flow_error_set(error, ENOENT,
13181 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13182 : : NULL, "No aging initialized");
13183 [ # # ]: 0 : if (priv->hws_strict_queue) {
13184 [ # # ]: 0 : if (queue_id >= age_info->hw_q_age->nb_rings)
13185 : 0 : return rte_flow_error_set(error, EINVAL,
13186 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13187 : : NULL, "invalid queue id");
13188 : 0 : r = age_info->hw_q_age->aged_lists[queue_id];
13189 : : } else {
13190 : 0 : r = age_info->hw_age.aged_list;
13191 : 0 : MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
13192 : : }
13193 [ # # ]: 0 : if (nb_contexts == 0)
13194 : 0 : return rte_ring_count(r);
13195 [ # # ]: 0 : while ((uint32_t)nb_flows < nb_contexts) {
13196 : : uint32_t age_idx;
13197 : :
13198 : : if (rte_ring_dequeue_elem(r, &age_idx, sizeof(uint32_t)) < 0)
13199 : : break;
13200 : : /* get the AGE context if the aged-out index is still valid. */
13201 : 0 : contexts[nb_flows] = mlx5_hws_age_context_get(priv, age_idx);
13202 [ # # ]: 0 : if (!contexts[nb_flows])
13203 : 0 : continue;
13204 : 0 : nb_flows++;
13205 : : }
13206 : : return nb_flows;
13207 : : }
13208 : :
13209 : : /**
13210 : : * Get aged-out flows.
13211 : : *
13212 : : * This function is relevant only if RTE_FLOW_PORT_FLAG_STRICT_QUEUE isn't set.
13213 : : *
13214 : : * @param[in] dev
13215 : : * Pointer to the Ethernet device structure.
13216 : : * @param[in] contexts
13217 : : * The address of an array of pointers to the aged-out flows contexts.
13218 : : * @param[in] nb_contexts
13219 : : * The length of context array pointers.
13220 : : * @param[out] error
13221 : : * Perform verbose error reporting if not NULL. Initialized in case of
13222 : : * error only.
13223 : : *
13224 : : * @return
13225 : : * how many contexts get in success, otherwise negative errno value.
13226 : : * if nb_contexts is 0, return the amount of all aged contexts.
13227 : : * if nb_contexts is not 0 , return the amount of aged flows reported
13228 : : * in the context array.
13229 : : */
13230 : : static int
13231 : 0 : flow_hw_get_aged_flows(struct rte_eth_dev *dev, void **contexts,
13232 : : uint32_t nb_contexts, struct rte_flow_error *error)
13233 : : {
13234 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13235 : :
13236 [ # # ]: 0 : if (priv->hws_strict_queue)
13237 : 0 : DRV_LOG(WARNING,
13238 : : "port %u get aged flows called in strict queue mode.",
13239 : : dev->data->port_id);
13240 : 0 : return flow_hw_get_q_aged_flows(dev, 0, contexts, nb_contexts, error);
13241 : : }
13242 : : /**
13243 : : * Initialization function for non template API which calls
13244 : : * flow_hw_configure with default values.
13245 : : * Configure non queues cause 1 queue is configured by default for inner usage.
13246 : : *
13247 : : * @param[in] dev
13248 : : * Pointer to the Ethernet device structure.
13249 : : * @param[out] error
13250 : : * Pointer to the error structure.
13251 : : *
13252 : : * @return
13253 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
13254 : : */
13255 : : int
13256 : 0 : flow_hw_init(struct rte_eth_dev *dev,
13257 : : struct rte_flow_error *error)
13258 : : {
13259 : 0 : const struct rte_flow_port_attr port_attr = {0};
13260 : 0 : const struct rte_flow_queue_attr queue_attr = {.size = MLX5_NT_DEFAULT_QUEUE_SIZE};
13261 : 0 : const struct rte_flow_queue_attr *attr_list = &queue_attr;
13262 : :
13263 : : /**
13264 : : * If user uses template and non template API:
13265 : : * User will call flow_hw_configure and non template
13266 : : * API will use the allocated actions.
13267 : : * Init function will not call flow_hw_configure.
13268 : : *
13269 : : * If user uses only non template API's:
13270 : : * Init function will call flow_hw_configure.
13271 : : * It will not allocate memory for actions.
13272 : : * When needed allocation, it will handle same as for SWS today,
13273 : : * meaning using bulk allocations and resize as needed.
13274 : : */
13275 : : /* Configure hws with default values. */
13276 : 0 : DRV_LOG(DEBUG, "Apply default configuration, zero number of queues, inner control queue size is %u",
13277 : : MLX5_NT_DEFAULT_QUEUE_SIZE);
13278 : 0 : return __flow_hw_configure(dev, &port_attr, 0, &attr_list, true, error);
13279 : : }
13280 : :
13281 : 0 : static int flow_hw_prepare(struct rte_eth_dev *dev,
13282 : : const struct rte_flow_action actions[] __rte_unused,
13283 : : enum mlx5_flow_type type,
13284 : : struct rte_flow_hw **flow,
13285 : : struct rte_flow_error *error)
13286 : : {
13287 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13288 : 0 : uint32_t idx = 0;
13289 : :
13290 : : /*
13291 : : * Notice pool idx size = (sizeof(struct rte_flow_hw)
13292 : : * + sizeof(struct rte_flow_nt2hws)) for HWS mode.
13293 : : */
13294 : 0 : *flow = mlx5_ipool_zmalloc(priv->flows[type], &idx);
13295 [ # # ]: 0 : if (!(*flow))
13296 : 0 : return rte_flow_error_set(error, ENOMEM,
13297 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13298 : : "cannot allocate flow memory");
13299 : : /* Allocating 2 structures in one pool slot, updating nt2hw pointer.*/
13300 : 0 : (*flow)->nt2hws = (struct rte_flow_nt2hws *)
13301 : 0 : ((uintptr_t)(*flow) + sizeof(struct rte_flow_hw));
13302 : 0 : (*flow)->idx = idx;
13303 : 0 : (*flow)->nt2hws->flow_aux = mlx5_malloc(MLX5_MEM_ZERO, sizeof(struct rte_flow_hw_aux),
13304 : 0 : RTE_CACHE_LINE_SIZE, rte_dev_numa_node(dev->device));
13305 [ # # ]: 0 : if (!(*flow)->nt2hws->flow_aux)
13306 : 0 : return rte_flow_error_set(error, ENOMEM,
13307 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13308 : : "cannot allocate flow aux memory");
13309 : : return 0;
13310 : : }
13311 : :
13312 : : #define FLOW_HW_SET_DV_FIELDS(flow_attr, root, dv_resource) { \
13313 : : typeof(flow_attr) _flow_attr = (flow_attr); \
13314 : : if (_flow_attr->transfer) \
13315 : : dv_resource.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB; \
13316 : : else \
13317 : : dv_resource.ft_type = _flow_attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX : \
13318 : : MLX5DV_FLOW_TABLE_TYPE_NIC_RX; \
13319 : : root = _flow_attr->group ? 0 : 1; \
13320 : : dv_resource.flags = \
13321 : : mlx5_hw_act_flag[!!_flow_attr->group][get_mlx5dr_table_type(_flow_attr)]; \
13322 : : }
13323 : :
13324 : : static int
13325 : 0 : flow_hw_modify_hdr_resource_register
13326 : : (struct rte_eth_dev *dev,
13327 : : struct rte_flow_template_table *table,
13328 : : struct mlx5_hw_actions *hw_acts,
13329 : : struct rte_flow_hw *dev_flow,
13330 : : struct rte_flow_error *error)
13331 : : {
13332 : : struct rte_flow_attr *attr = &table->cfg.attr.flow_attr;
13333 : 0 : struct mlx5_flow_dv_modify_hdr_resource *dv_resource_ptr = NULL;
13334 : : union {
13335 : : struct mlx5_flow_dv_modify_hdr_resource dv_resource;
13336 : : uint8_t data[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
13337 : : sizeof(struct mlx5_modification_cmd) * MLX5_MHDR_MAX_CMD];
13338 : : } dummy;
13339 : : int ret;
13340 : :
13341 [ # # ]: 0 : if (hw_acts->mhdr) {
13342 : 0 : dummy.dv_resource.actions_num = hw_acts->mhdr->mhdr_cmds_num;
13343 : 0 : memcpy(dummy.dv_resource.actions, hw_acts->mhdr->mhdr_cmds,
13344 [ # # ]: 0 : sizeof(struct mlx5_modification_cmd) * dummy.dv_resource.actions_num);
13345 : : } else {
13346 : : return 0;
13347 : : }
13348 [ # # # # ]: 0 : FLOW_HW_SET_DV_FIELDS(attr, dummy.dv_resource.root, dummy.dv_resource);
13349 : 0 : dummy.dv_resource.flags |= MLX5DR_ACTION_FLAG_SHARED;
13350 : 0 : ret = __flow_modify_hdr_resource_register(dev, &dummy.dv_resource,
13351 : : &dv_resource_ptr, error);
13352 [ # # ]: 0 : if (ret)
13353 : : return ret;
13354 : : MLX5_ASSERT(dv_resource_ptr);
13355 : 0 : dev_flow->nt2hws->modify_hdr = dv_resource_ptr;
13356 : : /* keep action for the rule construction. */
13357 : 0 : hw_acts->rule_acts[hw_acts->mhdr->pos].action = dv_resource_ptr->action;
13358 : : /* Bulk size is 1, so index is 1. */
13359 : 0 : dev_flow->res_idx = 1;
13360 : 0 : return 0;
13361 : : }
13362 : :
13363 : : static int
13364 : 0 : flow_hw_encap_decap_resource_register
13365 : : (struct rte_eth_dev *dev,
13366 : : struct rte_flow_template_table *table,
13367 : : struct mlx5_hw_actions *hw_acts,
13368 : : struct rte_flow_hw *dev_flow,
13369 : : struct rte_flow_error *error)
13370 : : {
13371 : : struct rte_flow_attr *attr = &table->cfg.attr.flow_attr;
13372 : 0 : struct mlx5_flow_dv_encap_decap_resource *dv_resource_ptr = NULL;
13373 : : struct mlx5_flow_dv_encap_decap_resource dv_resource;
13374 : : struct mlx5_tbl_multi_pattern_ctx *mpctx = &table->mpctx;
13375 : : int ret;
13376 : : bool is_root;
13377 : : int ix;
13378 : :
13379 [ # # ]: 0 : if (hw_acts->encap_decap)
13380 : 0 : dv_resource.reformat_type = hw_acts->encap_decap->action_type;
13381 : : else
13382 : : return 0;
13383 [ # # # # ]: 0 : FLOW_HW_SET_DV_FIELDS(attr, is_root, dv_resource);
13384 [ # # ]: 0 : ix = mlx5_bwc_multi_pattern_reformat_to_index((enum mlx5dr_action_type)
13385 : : dv_resource.reformat_type);
13386 : : if (ix < 0)
13387 : 0 : return ix;
13388 [ # # ]: 0 : if (hw_acts->encap_decap->shared) {
13389 : 0 : dv_resource.size = hw_acts->encap_decap->data_size;
13390 : : MLX5_ASSERT(dv_resource.size <= MLX5_ENCAP_MAX_LEN);
13391 : 0 : memcpy(&dv_resource.buf, hw_acts->encap_decap->data, dv_resource.size);
13392 : 0 : dv_resource.flags |= MLX5DR_ACTION_FLAG_SHARED;
13393 : : } else {
13394 : 0 : typeof(mpctx->reformat[0]) *reformat = mpctx->reformat + ix;
13395 [ # # ]: 0 : if (!reformat->elements_num)
13396 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
13397 : : NULL, "No reformat action exist in the table.");
13398 : 0 : dv_resource.size = reformat->reformat_hdr->sz;
13399 : : MLX5_ASSERT(dv_resource.size <= MLX5_ENCAP_MAX_LEN);
13400 : 0 : memcpy(&dv_resource.buf, reformat->reformat_hdr->data, dv_resource.size);
13401 : : }
13402 : 0 : ret = __flow_encap_decap_resource_register(dev, &dv_resource, is_root,
13403 : : &dv_resource_ptr, error);
13404 [ # # ]: 0 : if (ret)
13405 : : return ret;
13406 : : MLX5_ASSERT(dv_resource_ptr);
13407 : 0 : dev_flow->nt2hws->rix_encap_decap = dv_resource_ptr->idx;
13408 : : /* keep action for the rule construction. */
13409 [ # # ]: 0 : if (hw_acts->encap_decap->shared)
13410 : 0 : hw_acts->rule_acts[hw_acts->encap_decap_pos].action = dv_resource_ptr->action;
13411 : : else
13412 : 0 : mpctx->segments[0].reformat_action[ix] = dv_resource_ptr->action;
13413 : : /* Bulk size is 1, so index is 1. */
13414 : 0 : dev_flow->res_idx = 1;
13415 : 0 : return 0;
13416 : : }
13417 : :
13418 : : static enum rte_flow_action_type
13419 : : flow_nta_get_indirect_action_type(const struct rte_flow_action *action)
13420 : : {
13421 [ # # ]: 0 : switch (MLX5_INDIRECT_ACTION_TYPE_GET(action->conf)) {
13422 : : case MLX5_INDIRECT_ACTION_TYPE_RSS:
13423 : : return RTE_FLOW_ACTION_TYPE_RSS;
13424 : : case MLX5_INDIRECT_ACTION_TYPE_AGE:
13425 : : return RTE_FLOW_ACTION_TYPE_AGE;
13426 : : case MLX5_INDIRECT_ACTION_TYPE_COUNT:
13427 : : return RTE_FLOW_ACTION_TYPE_COUNT;
13428 : : case MLX5_INDIRECT_ACTION_TYPE_CT:
13429 : : return RTE_FLOW_ACTION_TYPE_CONNTRACK;
13430 : : default:
13431 : : break;
13432 : : }
13433 : : return RTE_FLOW_ACTION_TYPE_END;
13434 : : }
13435 : :
13436 : : static void
13437 : : flow_nta_set_mh_mask_conf(const struct rte_flow_action_modify_field *action_conf,
13438 : : struct rte_flow_action_modify_field *mask_conf)
13439 : : {
13440 : : memset(mask_conf, 0xff, sizeof(*mask_conf));
13441 : 0 : mask_conf->operation = action_conf->operation;
13442 : 0 : mask_conf->dst.field = action_conf->dst.field;
13443 : 0 : mask_conf->src.field = action_conf->src.field;
13444 : : }
13445 : :
13446 : : union actions_conf {
13447 : : struct rte_flow_action_modify_field modify_field;
13448 : : struct rte_flow_action_raw_encap raw_encap;
13449 : : struct rte_flow_action_vxlan_encap vxlan_encap;
13450 : : struct rte_flow_action_nvgre_encap nvgre_encap;
13451 : : };
13452 : :
13453 : : static int
13454 : 0 : flow_nta_build_template_mask(const struct rte_flow_action actions[],
13455 : : struct rte_flow_action masks[MLX5_HW_MAX_ACTS],
13456 : : union actions_conf mask_conf[MLX5_HW_MAX_ACTS])
13457 : : {
13458 : : int i;
13459 : :
13460 [ # # # # ]: 0 : for (i = 0; i == 0 || actions[i - 1].type != RTE_FLOW_ACTION_TYPE_END; i++) {
13461 : 0 : const struct rte_flow_action *action = &actions[i];
13462 : 0 : struct rte_flow_action *mask = &masks[i];
13463 : 0 : union actions_conf *conf = &mask_conf[i];
13464 : :
13465 : 0 : mask->type = action->type;
13466 [ # # # # : 0 : switch (action->type) {
# # ]
13467 : : case RTE_FLOW_ACTION_TYPE_INDIRECT:
13468 : 0 : mask->type = flow_nta_get_indirect_action_type(action);
13469 [ # # ]: 0 : if (!mask->type)
13470 : : return -EINVAL;
13471 : : break;
13472 : 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
13473 : 0 : flow_nta_set_mh_mask_conf(action->conf, (void *)conf);
13474 : 0 : mask->conf = conf;
13475 : 0 : break;
13476 : : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
13477 : : /* This mask will set this action as shared. */
13478 : : memset(conf, 0xff, sizeof(struct rte_flow_action_raw_encap));
13479 : 0 : mask->conf = conf;
13480 : 0 : break;
13481 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
13482 : : /* This mask will set this action as shared. */
13483 : 0 : conf->vxlan_encap.definition =
13484 : : ((const struct rte_flow_action_vxlan_encap *)
13485 : 0 : action->conf)->definition;
13486 : 0 : mask->conf = conf;
13487 : 0 : break;
13488 : 0 : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
13489 : : /* This mask will set this action as shared. */
13490 : 0 : conf->nvgre_encap.definition =
13491 : : ((const struct rte_flow_action_nvgre_encap *)
13492 : 0 : action->conf)->definition;
13493 : 0 : mask->conf = conf;
13494 : 0 : break;
13495 : : default:
13496 : : break;
13497 : : }
13498 : : }
13499 : : return 0;
13500 : : #undef NTA_CHECK_CONF_BUF_SIZE
13501 : : }
13502 : :
13503 : : static int
13504 : 0 : flow_hw_translate_flow_actions(struct rte_eth_dev *dev,
13505 : : const struct rte_flow_attr *attr,
13506 : : const struct rte_flow_action actions[],
13507 : : struct rte_flow_hw *flow,
13508 : : struct mlx5_flow_hw_action_params *ap,
13509 : : struct mlx5_hw_actions *hw_acts,
13510 : : uint64_t item_flags, uint64_t action_flags,
13511 : : bool external,
13512 : : struct rte_flow_error *error)
13513 : : {
13514 : : int ret = 0;
13515 : 0 : uint32_t src_group = 0;
13516 : : enum mlx5dr_table_type table_type;
13517 : : struct mlx5_flow_group grp;
13518 : : struct rte_flow_actions_template *at = NULL;
13519 : 0 : struct rte_flow_actions_template_attr template_attr = {
13520 : 0 : .egress = attr->egress,
13521 : 0 : .ingress = attr->ingress,
13522 : 0 : .transfer = attr->transfer,
13523 : : };
13524 : : struct rte_flow_action masks[MLX5_HW_MAX_ACTS];
13525 : : union actions_conf mask_conf[MLX5_HW_MAX_ACTS];
13526 : :
13527 : : RTE_SET_USED(action_flags);
13528 : : memset(masks, 0, sizeof(masks));
13529 : : memset(mask_conf, 0, sizeof(mask_conf));
13530 : : /* Only set the needed fields explicitly. */
13531 : 0 : struct mlx5_flow_workspace *wks = mlx5_flow_push_thread_workspace();
13532 : : struct rte_flow_template_table *table;
13533 : :
13534 : : /*
13535 : : * Notice All direct actions will be unmasked,
13536 : : * except for modify header and encap,
13537 : : * and therefore will be parsed as part of action construct.
13538 : : * Modify header is always shared in HWS,
13539 : : * encap is masked such that it will be treated as shared.
13540 : : * shared actions will be parsed as part of template translation
13541 : : * and not during action construct.
13542 : : */
13543 [ # # ]: 0 : if (!wks)
13544 : 0 : return rte_flow_error_set(error, ENOMEM,
13545 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13546 : : NULL,
13547 : : "failed to push flow workspace");
13548 : 0 : table = wks->table;
13549 : 0 : flow_nta_build_template_mask(actions, masks, mask_conf);
13550 : : /* The group in the attribute translation was done in advance. */
13551 : 0 : ret = __translate_group(dev, attr, external, attr->group, &src_group, error);
13552 [ # # ]: 0 : if (ret)
13553 : : return ret;
13554 [ # # ]: 0 : if (attr->transfer)
13555 : : table_type = MLX5DR_TABLE_TYPE_FDB;
13556 [ # # ]: 0 : else if (attr->egress)
13557 : : table_type = MLX5DR_TABLE_TYPE_NIC_TX;
13558 : : else
13559 : : table_type = MLX5DR_TABLE_TYPE_NIC_RX;
13560 : 0 : at = __flow_hw_actions_template_create(dev, &template_attr, actions, masks, true, error);
13561 [ # # ]: 0 : if (!at) {
13562 : 0 : ret = -rte_errno;
13563 : 0 : goto end;
13564 : : }
13565 : 0 : grp.group_id = src_group;
13566 : 0 : table->grp = &grp;
13567 : 0 : table->type = table_type;
13568 : 0 : table->cfg.external = external;
13569 : 0 : table->nb_action_templates = 1;
13570 : 0 : memcpy(&table->cfg.attr.flow_attr, attr, sizeof(*attr));
13571 : 0 : table->ats[0].action_template = at;
13572 : 0 : ret = __flow_hw_translate_actions_template(dev, &table->cfg, hw_acts, at,
13573 : : &table->mpctx, true, error);
13574 [ # # ]: 0 : if (ret)
13575 : 0 : goto end;
13576 : : /* handle bulk actions register. */
13577 : 0 : ret = flow_hw_encap_decap_resource_register(dev, table, hw_acts, flow, error);
13578 [ # # ]: 0 : if (ret)
13579 : 0 : goto end;
13580 : 0 : ret = flow_hw_modify_hdr_resource_register(dev, table, hw_acts, flow, error);
13581 [ # # ]: 0 : if (ret)
13582 : 0 : goto end;
13583 : 0 : table->ats[0].acts = *hw_acts;
13584 : 0 : ret = flow_hw_actions_construct(dev, flow, ap,
13585 : : &table->ats[0], item_flags, table,
13586 [ # # ]: 0 : actions, hw_acts->rule_acts, 0, error);
13587 : : if (ret)
13588 : 0 : goto end;
13589 : 0 : goto end;
13590 : 0 : end:
13591 [ # # ]: 0 : if (ret)
13592 : : /* Make sure that there is no garbage in the actions. */
13593 : 0 : __flow_hw_action_template_destroy(dev, hw_acts);
13594 : : else
13595 : 0 : __flow_hw_act_data_flush(dev, hw_acts);
13596 [ # # ]: 0 : if (at)
13597 : 0 : mlx5_free(at);
13598 : 0 : mlx5_flow_pop_thread_workspace();
13599 : 0 : return ret;
13600 : : }
13601 : :
13602 : : static int
13603 : 0 : flow_hw_unregister_matcher(struct rte_eth_dev *dev,
13604 : : struct mlx5_flow_dv_matcher *matcher)
13605 : : {
13606 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13607 : 0 : struct mlx5_flow_group *group = matcher->group;
13608 : : int ret = 0;
13609 : :
13610 [ # # ]: 0 : if (group) {
13611 [ # # ]: 0 : if (matcher->matcher_object)
13612 : 0 : ret |= mlx5_list_unregister(group->matchers, &matcher->entry);
13613 : 0 : ret |= mlx5_hlist_unregister(priv->sh->groups, &group->entry);
13614 : : }
13615 : 0 : return ret;
13616 : : }
13617 : :
13618 : 0 : static int flow_hw_register_matcher(struct rte_eth_dev *dev,
13619 : : const struct rte_flow_attr *attr,
13620 : : const struct rte_flow_item items[],
13621 : : bool external,
13622 : : struct rte_flow_hw *flow,
13623 : : struct mlx5_flow_dv_matcher *matcher,
13624 : : struct rte_flow_error *error)
13625 : : {
13626 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13627 : 0 : struct rte_flow_error sub_error = {
13628 : : .type = RTE_FLOW_ERROR_TYPE_NONE,
13629 : : .cause = NULL,
13630 : : .message = NULL,
13631 : : };
13632 : 0 : struct rte_flow_attr flow_attr = *attr;
13633 : 0 : uint32_t specialize = 0; /* No unified FDB. */
13634 : 0 : struct mlx5_flow_cb_ctx ctx = {
13635 : : .dev = dev,
13636 : : .error = &sub_error,
13637 : : .data = &flow_attr,
13638 : : .data2 = &specialize,
13639 : : };
13640 : : void *items_ptr = &items;
13641 : 0 : struct mlx5_flow_cb_ctx matcher_ctx = {
13642 : : .error = &sub_error,
13643 : : .data = matcher,
13644 : : .data2 = items_ptr,
13645 : : };
13646 : : struct mlx5_list_entry *group_entry = NULL;
13647 : : struct mlx5_list_entry *matcher_entry = NULL;
13648 : : struct mlx5_flow_dv_matcher *resource;
13649 : : struct mlx5_list *matchers_list;
13650 : : struct mlx5_flow_group *flow_group;
13651 : : int ret;
13652 : :
13653 : :
13654 : 0 : matcher->crc = rte_raw_cksum((const void *)matcher->mask.buf,
13655 : : matcher->mask.size);
13656 : 0 : matcher->priority = attr->priority;
13657 : 0 : ret = __translate_group(dev, attr, external, attr->group, &flow_attr.group, error);
13658 [ # # ]: 0 : if (ret)
13659 : : return ret;
13660 : :
13661 : : /* Register the flow group. */
13662 : 0 : group_entry = mlx5_hlist_register(priv->sh->groups, flow_attr.group, &ctx);
13663 [ # # ]: 0 : if (!group_entry)
13664 : 0 : goto error;
13665 : : flow_group = container_of(group_entry, struct mlx5_flow_group, entry);
13666 : :
13667 : 0 : matchers_list = flow_group->matchers;
13668 : 0 : matcher->group = flow_group;
13669 : 0 : matcher_entry = mlx5_list_register(matchers_list, &matcher_ctx);
13670 [ # # ]: 0 : if (!matcher_entry)
13671 : 0 : goto error;
13672 : : resource = container_of(matcher_entry, typeof(*resource), entry);
13673 : 0 : flow->nt2hws->matcher = resource;
13674 : 0 : return 0;
13675 : :
13676 : 0 : error:
13677 [ # # ]: 0 : if (group_entry)
13678 : 0 : mlx5_hlist_unregister(priv->sh->groups, group_entry);
13679 [ # # ]: 0 : if (error) {
13680 [ # # ]: 0 : if (sub_error.type != RTE_FLOW_ERROR_TYPE_NONE)
13681 : : rte_memcpy(error, &sub_error, sizeof(sub_error));
13682 : : }
13683 : 0 : return rte_flow_error_set(error, ENOMEM,
13684 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13685 : : NULL, "fail to register matcher");
13686 : : }
13687 : :
13688 : : static int
13689 : 0 : flow_hw_allocate_actions(struct rte_eth_dev *dev,
13690 : : uint64_t action_flags,
13691 : : struct rte_flow_error *error)
13692 : : {
13693 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13694 : : int ret;
13695 : : uint obj_num;
13696 : :
13697 : 0 : error->type = RTE_FLOW_ERROR_TYPE_NONE;
13698 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_AGE) {
13699 : : /* If no age objects were previously allocated. */
13700 [ # # ]: 0 : if (!priv->hws_age_req) {
13701 : : /* If no counters were previously allocated. */
13702 [ # # ]: 0 : if (!priv->hws_cpool) {
13703 : 0 : obj_num = MLX5_CNT_NT_MAX(priv);
13704 : 0 : ret = mlx5_hws_cnt_pool_create(dev, obj_num,
13705 : 0 : priv->nb_queue,
13706 : : NULL, error);
13707 [ # # ]: 0 : if (ret)
13708 : 0 : goto err;
13709 : : }
13710 : : /* Allocate same number of counters. */
13711 : 0 : ret = mlx5_hws_age_pool_init(dev, priv->hws_cpool->cfg.request_num,
13712 : 0 : priv->nb_queue, false);
13713 [ # # ]: 0 : if (ret)
13714 : 0 : goto err;
13715 : : }
13716 : : }
13717 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_COUNT) {
13718 : : /* If no counters were previously allocated. */
13719 [ # # ]: 0 : if (!priv->hws_cpool) {
13720 : 0 : obj_num = MLX5_CNT_NT_MAX(priv);
13721 : 0 : ret = mlx5_hws_cnt_pool_create(dev, obj_num,
13722 : 0 : priv->nb_queue, NULL,
13723 : : error);
13724 [ # # ]: 0 : if (ret)
13725 : 0 : goto err;
13726 : : }
13727 : : }
13728 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_CT) {
13729 : : /* If no CT were previously allocated. */
13730 [ # # ]: 0 : if (!priv->hws_ctpool) {
13731 : 0 : obj_num = MLX5_CT_NT_MAX(priv);
13732 : 0 : ret = mlx5_flow_ct_init(dev, obj_num, priv->nb_queue);
13733 [ # # ]: 0 : if (ret)
13734 : 0 : goto err;
13735 : : }
13736 : : }
13737 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_METER) {
13738 : : /* If no meters were previously allocated. */
13739 [ # # ]: 0 : if (!priv->hws_mpool) {
13740 : 0 : obj_num = MLX5_MTR_NT_MAX(priv);
13741 : 0 : ret = mlx5_flow_meter_init(dev, obj_num, 0, 0,
13742 : : priv->nb_queue);
13743 [ # # ]: 0 : if (ret)
13744 : 0 : goto err;
13745 : : }
13746 : : }
13747 : : return 0;
13748 : 0 : err:
13749 [ # # ]: 0 : if (ret && error->type != RTE_FLOW_ERROR_TYPE_NONE)
13750 : : return ret;
13751 : 0 : return rte_flow_error_set(error, ret,
13752 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13753 : : NULL, "fail to allocate actions");
13754 : : }
13755 : :
13756 : 0 : static int flow_hw_apply(const struct rte_flow_item items[],
13757 : : struct mlx5dr_rule_action rule_actions[],
13758 : : struct rte_flow_hw *flow,
13759 : : struct rte_flow_error *error)
13760 : : {
13761 : : struct mlx5dr_bwc_rule *rule = NULL;
13762 : :
13763 : 0 : rule = mlx5dr_bwc_rule_create((struct mlx5dr_bwc_matcher *)
13764 : 0 : flow->nt2hws->matcher->matcher_object,
13765 : : items, rule_actions);
13766 : 0 : flow->nt2hws->nt_rule = rule;
13767 [ # # ]: 0 : if (!rule) {
13768 : 0 : return rte_flow_error_set(error, EINVAL,
13769 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13770 : : NULL, "fail to create rte flow");
13771 : : }
13772 : : return 0;
13773 : : }
13774 : :
13775 : : #ifdef HAVE_MLX5_HWS_SUPPORT
13776 : : /**
13777 : : * Create a flow.
13778 : : *
13779 : : * @param[in] dev
13780 : : * Pointer to Ethernet device.
13781 : : * @param[in] type
13782 : : * Flow type.
13783 : : * @param[in] attr
13784 : : * Flow rule attributes.
13785 : : * @param[in] items
13786 : : * Pattern specification (list terminated by the END pattern item).
13787 : : * @param[in] actions
13788 : : * Associated actions (list terminated by the END action).
13789 : : * @param[in] external
13790 : : * This flow rule is created by request external to PMD.
13791 : : * @param[out] flow
13792 : : * Flow pointer
13793 : : * @param[out] error
13794 : : * Perform verbose error reporting if not NULL.
13795 : : *
13796 : : * @return
13797 : : * 0 on success, negative errno value otherwise and rte_errno set.
13798 : : */
13799 : : int
13800 : 0 : flow_hw_create_flow(struct rte_eth_dev *dev, enum mlx5_flow_type type,
13801 : : const struct rte_flow_attr *attr,
13802 : : const struct rte_flow_item items[],
13803 : : const struct rte_flow_action actions[],
13804 : : uint64_t item_flags, uint64_t action_flags, bool external,
13805 : : struct rte_flow_hw **flow, struct rte_flow_error *error)
13806 : : {
13807 : : int ret;
13808 : 0 : struct mlx5_hw_actions hw_act = { { NULL } };
13809 : : struct mlx5_flow_hw_action_params ap;
13810 : 0 : struct mlx5_flow_dv_matcher matcher = {
13811 : : .mask = {
13812 : : .size = sizeof(matcher.mask.buf),
13813 : : },
13814 : : };
13815 : : uint32_t tbl_type;
13816 : :
13817 : 0 : struct mlx5_flow_attr flow_attr = {
13818 : 0 : .port_id = dev->data->port_id,
13819 : 0 : .group = attr->group,
13820 : 0 : .priority = attr->priority,
13821 : : .rss_level = 0,
13822 : : .act_flags = action_flags,
13823 : : .tbl_type = 0,
13824 : : };
13825 : :
13826 [ # # ]: 0 : if (attr->transfer)
13827 : : tbl_type = MLX5DR_TABLE_TYPE_FDB;
13828 [ # # ]: 0 : else if (attr->egress)
13829 : : tbl_type = MLX5DR_TABLE_TYPE_NIC_TX;
13830 : : else
13831 : : tbl_type = MLX5DR_TABLE_TYPE_NIC_RX;
13832 : 0 : flow_attr.tbl_type = tbl_type;
13833 : :
13834 : : /* Allocate needed memory. */
13835 : 0 : ret = flow_hw_prepare(dev, actions, type, flow, error);
13836 [ # # ]: 0 : if (ret)
13837 : 0 : goto error;
13838 : :
13839 : : /* TODO TBD flow_hw_handle_tunnel_offload(). */
13840 : 0 : (*flow)->nt_rule = true;
13841 : 0 : (*flow)->nt2hws->matcher = &matcher;
13842 : 0 : ret = flow_dv_translate_items_hws(items, &flow_attr, &matcher.mask.buf,
13843 : : MLX5_SET_MATCHER_HS_M, NULL,
13844 : : NULL, error);
13845 : :
13846 [ # # ]: 0 : if (ret)
13847 : 0 : goto error;
13848 : :
13849 : 0 : ret = flow_hw_register_matcher(dev, attr, items, external, *flow, &matcher, error);
13850 [ # # ]: 0 : if (ret)
13851 : 0 : goto error;
13852 : :
13853 : : /*
13854 : : * ASO allocation – iterating on actions list to allocate missing resources.
13855 : : * In the future when validate function in hws will be added,
13856 : : * The output actions bit mask instead of
13857 : : * looping on the actions array twice.
13858 : : */
13859 : 0 : ret = flow_hw_allocate_actions(dev, action_flags, error);
13860 [ # # ]: 0 : if (ret)
13861 : 0 : goto error;
13862 : :
13863 : : /* Note: the actions should be saved in the sub-flow rule itself for reference. */
13864 : 0 : ret = flow_hw_translate_flow_actions(dev, attr, actions, *flow, &ap, &hw_act,
13865 : : item_flags, action_flags, external, error);
13866 [ # # ]: 0 : if (ret)
13867 : 0 : goto error;
13868 : :
13869 : : /*
13870 : : * If the flow is external (from application) OR device is started,
13871 : : * OR mreg discover, then apply immediately.
13872 : : */
13873 [ # # # # ]: 0 : if (external || dev->data->dev_started ||
13874 [ # # ]: 0 : (attr->group == MLX5_FLOW_MREG_CP_TABLE_GROUP &&
13875 [ # # ]: 0 : attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR)) {
13876 : 0 : ret = flow_hw_apply(items, hw_act.rule_acts, *flow, error);
13877 [ # # ]: 0 : if (ret)
13878 : 0 : goto error;
13879 : : }
13880 : : ret = 0;
13881 : 0 : error:
13882 : : /*
13883 : : * Release memory allocated.
13884 : : * Cannot use __flow_hw_actions_release(dev, &hw_act);
13885 : : * since it destroys the actions as well.
13886 : : */
13887 [ # # ]: 0 : if (hw_act.encap_decap)
13888 : 0 : mlx5_free(hw_act.encap_decap);
13889 [ # # ]: 0 : if (hw_act.push_remove)
13890 : 0 : mlx5_free(hw_act.push_remove);
13891 [ # # ]: 0 : if (hw_act.mhdr)
13892 : 0 : mlx5_free(hw_act.mhdr);
13893 [ # # ]: 0 : if (ret) {
13894 : : /* release after actual error */
13895 [ # # # # ]: 0 : if ((*flow)->nt2hws && (*flow)->nt2hws->matcher)
13896 : 0 : flow_hw_unregister_matcher(dev, (*flow)->nt2hws->matcher);
13897 : : }
13898 : 0 : return ret;
13899 : : }
13900 : : #endif
13901 : :
13902 : : void
13903 : 0 : flow_hw_destroy(struct rte_eth_dev *dev, struct rte_flow_hw *flow)
13904 : : {
13905 : : int ret;
13906 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13907 : :
13908 [ # # # # ]: 0 : if (!flow || !flow->nt2hws)
13909 : : return;
13910 : :
13911 [ # # ]: 0 : if (flow->nt2hws->nt_rule) {
13912 : 0 : ret = mlx5dr_bwc_rule_destroy(flow->nt2hws->nt_rule);
13913 [ # # ]: 0 : if (ret)
13914 : 0 : DRV_LOG(ERR, "bwc rule destroy failed");
13915 : : }
13916 [ # # ]: 0 : flow->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_DESTROY;
13917 : : /* Notice this function does not handle shared/static actions. */
13918 : : hw_cmpl_flow_update_or_destroy(dev, flow, 0, NULL);
13919 : :
13920 : : /**
13921 : : * TODO: TBD - Release tunnel related memory allocations(mlx5_flow_tunnel_free)
13922 : : * – needed only if supporting tunnel offloads, notice update RX queue flags in SWS.
13923 : : */
13924 : :
13925 : : /**
13926 : : * Notice matcher destroy will take place when matcher's list is destroyed
13927 : : * , same as for DV.
13928 : : */
13929 [ # # ]: 0 : if (flow->nt2hws->flow_aux)
13930 : 0 : mlx5_free(flow->nt2hws->flow_aux);
13931 : :
13932 [ # # ]: 0 : if (flow->nt2hws->rix_encap_decap)
13933 : 0 : flow_encap_decap_resource_release(dev, flow->nt2hws->rix_encap_decap);
13934 [ # # ]: 0 : if (flow->nt2hws->modify_hdr) {
13935 : : MLX5_ASSERT(flow->nt2hws->modify_hdr->action);
13936 : 0 : mlx5_hlist_unregister(priv->sh->modify_cmds,
13937 : : &flow->nt2hws->modify_hdr->entry);
13938 : : }
13939 [ # # ]: 0 : if (flow->nt2hws->matcher)
13940 : 0 : flow_hw_unregister_matcher(dev, flow->nt2hws->matcher);
13941 : : }
13942 : :
13943 : : #ifdef HAVE_MLX5_HWS_SUPPORT
13944 : : /**
13945 : : * Destroy a flow.
13946 : : *
13947 : : * @param[in] dev
13948 : : * Pointer to Ethernet device.
13949 : : * @param[in] type
13950 : : * Flow type.
13951 : : * @param[in] flow_addr
13952 : : * Address of flow to destroy.
13953 : : */
13954 : : void
13955 : 0 : flow_hw_list_destroy(struct rte_eth_dev *dev, enum mlx5_flow_type type,
13956 : : uintptr_t flow_addr)
13957 : : {
13958 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
13959 : 0 : struct rte_flow_hw *flow = (struct rte_flow_hw *)flow_addr;
13960 : : struct mlx5_nta_rss_flow_head head = { .slh_first = flow };
13961 : :
13962 [ # # # # : 0 : if (!flow || !flow->nt2hws || flow->nt2hws->chaned_flow)
# # ]
13963 : : return;
13964 : 0 : mlx5_flow_nta_del_copy_action(dev, flow->nt2hws->rix_mreg_copy);
13965 [ # # ]: 0 : while (!SLIST_EMPTY(&head)) {
13966 : : flow = SLIST_FIRST(&head);
13967 : 0 : SLIST_REMOVE_HEAD(&head, nt2hws->next);
13968 : 0 : flow_hw_destroy(dev, flow);
13969 : : /* Release flow memory by idx */
13970 : 0 : mlx5_ipool_free(priv->flows[type], flow->idx);
13971 : : }
13972 : : }
13973 : : #endif
13974 : :
13975 : : /**
13976 : : * Create a flow.
13977 : : *
13978 : : * @param[in] dev
13979 : : * Pointer to Ethernet device.
13980 : : * @param[in] type
13981 : : * Flow type.
13982 : : * @param[in] attr
13983 : : * Flow rule attributes.
13984 : : * @param[in] items
13985 : : * Pattern specification (list terminated by the END pattern item).
13986 : : * @param[in] actions
13987 : : * Associated actions (list terminated by the END action).
13988 : : * @param[in] external
13989 : : * This flow rule is created by request external to PMD.
13990 : : * @param[out] error
13991 : : * Perform verbose error reporting if not NULL.
13992 : : *
13993 : : * @return
13994 : : * A flow addr on success, 0 otherwise and rte_errno is set.
13995 : : */
13996 : 0 : static uintptr_t flow_hw_list_create(struct rte_eth_dev *dev,
13997 : : enum mlx5_flow_type type,
13998 : : const struct rte_flow_attr *attr,
13999 : : const struct rte_flow_item items[],
14000 : : const struct rte_flow_action actions[],
14001 : : bool external,
14002 : : struct rte_flow_error *error)
14003 : : {
14004 : : int ret;
14005 : : int split;
14006 : : int encap_idx;
14007 : 0 : uint32_t cpy_idx = 0;
14008 : 0 : int actions_n = 0;
14009 : 0 : struct rte_flow_hw *flow = NULL;
14010 : 0 : struct rte_flow_hw *prfx_flow = NULL;
14011 : 0 : const struct rte_flow_action *qrss = NULL;
14012 : 0 : const struct rte_flow_action *mark = NULL;
14013 : 0 : uint64_t item_flags = flow_hw_matching_item_flags_get(items);
14014 : 0 : uint64_t action_flags = flow_hw_action_flags_get(actions, &qrss, &mark,
14015 : : &encap_idx, &actions_n, error);
14016 : 0 : struct mlx5_flow_hw_split_resource resource = {
14017 : : .suffix = {
14018 : : .attr = attr,
14019 : : .items = items,
14020 : : .actions = actions,
14021 : : },
14022 : : };
14023 : 0 : struct rte_flow_error shadow_error = {0, };
14024 : :
14025 : : /*
14026 : : * TODO: add a call to flow_hw_validate function once it exist.
14027 : : * and update mlx5_flow_hw_drv_ops accordingly.
14028 : : */
14029 : :
14030 : : RTE_SET_USED(encap_idx);
14031 [ # # ]: 0 : if (!error)
14032 : : error = &shadow_error;
14033 : 0 : split = mlx5_flow_nta_split_metadata(dev, attr, actions, qrss, action_flags,
14034 : : actions_n, external, &resource, error);
14035 [ # # ]: 0 : if (split < 0)
14036 : 0 : return split;
14037 : :
14038 : : /* Update the metadata copy table - MLX5_FLOW_MREG_CP_TABLE_GROUP */
14039 [ # # # # : 0 : if (((attr->ingress && attr->group != MLX5_FLOW_MREG_CP_TABLE_GROUP) ||
# # ]
14040 [ # # ]: 0 : attr->transfer) && external) {
14041 : 0 : ret = mlx5_flow_nta_update_copy_table(dev, &cpy_idx, mark,
14042 : : action_flags, error);
14043 [ # # ]: 0 : if (ret)
14044 : 0 : goto free;
14045 : : }
14046 : :
14047 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_RSS) {
14048 : : const struct rte_flow_action_rss
14049 : 0 : *rss_conf = flow_nta_locate_rss(dev, actions, error);
14050 : 0 : flow = flow_nta_handle_rss(dev, attr, items, actions, rss_conf,
14051 : : item_flags, action_flags, external,
14052 : : type, error);
14053 [ # # ]: 0 : if (flow) {
14054 : 0 : flow->nt2hws->rix_mreg_copy = cpy_idx;
14055 : 0 : cpy_idx = 0;
14056 [ # # ]: 0 : if (!split)
14057 : 0 : return (uintptr_t)flow;
14058 : 0 : goto prefix_flow;
14059 : : }
14060 : 0 : goto free;
14061 : : }
14062 : : /* Create single flow. */
14063 : 0 : ret = flow_hw_create_flow(dev, type, resource.suffix.attr, resource.suffix.items,
14064 : : resource.suffix.actions, item_flags, action_flags,
14065 : : external, &flow, error);
14066 [ # # ]: 0 : if (ret)
14067 : 0 : goto free;
14068 [ # # ]: 0 : if (flow) {
14069 : 0 : flow->nt2hws->rix_mreg_copy = cpy_idx;
14070 : 0 : cpy_idx = 0;
14071 [ # # ]: 0 : if (!split)
14072 : 0 : return (uintptr_t)flow;
14073 : : /* Fall Through to prefix flow creation. */
14074 : : }
14075 : 0 : prefix_flow:
14076 : 0 : ret = flow_hw_create_flow(dev, type, attr, items, resource.prefix.actions,
14077 : : item_flags, action_flags, external, &prfx_flow, error);
14078 [ # # ]: 0 : if (ret)
14079 : 0 : goto free;
14080 [ # # ]: 0 : if (prfx_flow) {
14081 : 0 : prfx_flow->nt2hws->rix_mreg_copy = flow->nt2hws->rix_mreg_copy;
14082 : 0 : flow->nt2hws->chaned_flow = 1;
14083 : 0 : SLIST_INSERT_AFTER(prfx_flow, flow, nt2hws->next);
14084 : 0 : mlx5_flow_nta_split_resource_free(dev, &resource);
14085 : 0 : return (uintptr_t)prfx_flow;
14086 : : }
14087 : 0 : free:
14088 [ # # ]: 0 : if (prfx_flow)
14089 : 0 : flow_hw_list_destroy(dev, type, (uintptr_t)prfx_flow);
14090 [ # # ]: 0 : if (flow)
14091 : 0 : flow_hw_list_destroy(dev, type, (uintptr_t)flow);
14092 [ # # ]: 0 : if (cpy_idx)
14093 : 0 : mlx5_flow_nta_del_copy_action(dev, cpy_idx);
14094 [ # # ]: 0 : if (split > 0)
14095 : 0 : mlx5_flow_nta_split_resource_free(dev, &resource);
14096 : : return 0;
14097 : : }
14098 : :
14099 : : static void
14100 : 0 : mlx5_mirror_destroy_clone(struct rte_eth_dev *dev,
14101 : : struct mlx5_mirror_clone *clone)
14102 : : {
14103 [ # # # ]: 0 : switch (clone->type) {
14104 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
14105 : : case RTE_FLOW_ACTION_TYPE_QUEUE:
14106 : 0 : mlx5_hrxq_release(dev,
14107 : 0 : ((struct mlx5_hrxq *)(clone->action_ctx))->idx);
14108 : 0 : break;
14109 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP:
14110 : 0 : flow_hw_jump_release(dev, clone->action_ctx);
14111 : : break;
14112 : : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
14113 : : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
14114 : : case RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:
14115 : : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
14116 : : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
14117 : : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
14118 : : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
14119 : : default:
14120 : : break;
14121 : : }
14122 : 0 : }
14123 : :
14124 : : void
14125 [ # # ]: 0 : mlx5_hw_mirror_destroy(struct rte_eth_dev *dev, struct mlx5_mirror *mirror)
14126 : : {
14127 : : uint32_t i;
14128 : :
14129 : : mlx5_indirect_list_remove_entry(&mirror->indirect);
14130 [ # # ]: 0 : for (i = 0; i < mirror->clones_num; i++)
14131 : 0 : mlx5_mirror_destroy_clone(dev, &mirror->clone[i]);
14132 [ # # ]: 0 : if (mirror->mirror_action)
14133 : 0 : mlx5dr_action_destroy(mirror->mirror_action);
14134 : 0 : mlx5_free(mirror);
14135 : 0 : }
14136 : :
14137 : : static __rte_always_inline bool
14138 : : mlx5_mirror_terminal_action(const struct rte_flow_action *action)
14139 : : {
14140 : 0 : switch (action->type) {
14141 : : case RTE_FLOW_ACTION_TYPE_JUMP:
14142 : : case RTE_FLOW_ACTION_TYPE_RSS:
14143 : : case RTE_FLOW_ACTION_TYPE_QUEUE:
14144 : : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
14145 : : case RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:
14146 : : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
14147 : : return true;
14148 : : default:
14149 : : break;
14150 : : }
14151 : : return false;
14152 : : }
14153 : :
14154 : : static bool
14155 : 0 : mlx5_mirror_validate_sample_action(struct rte_eth_dev *dev,
14156 : : const struct rte_flow_attr *flow_attr,
14157 : : const struct rte_flow_action *action)
14158 : : {
14159 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14160 : : const struct rte_flow_action_ethdev *port = NULL;
14161 [ # # # # ]: 0 : bool is_proxy = MLX5_HW_PORT_IS_PROXY(priv);
14162 : :
14163 [ # # ]: 0 : if (!action)
14164 : : return false;
14165 [ # # # # : 0 : switch (action->type) {
# ]
14166 : 0 : case RTE_FLOW_ACTION_TYPE_QUEUE:
14167 : : case RTE_FLOW_ACTION_TYPE_RSS:
14168 [ # # ]: 0 : if (flow_attr->transfer)
14169 : : return false;
14170 : : break;
14171 : 0 : case RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:
14172 [ # # # # ]: 0 : if (!is_proxy || !flow_attr->transfer)
14173 : : return false;
14174 : 0 : port = action->conf;
14175 [ # # # # ]: 0 : if (!port || port->port_id != MLX5_REPRESENTED_PORT_ESW_MGR)
14176 : : return false;
14177 : : break;
14178 : 0 : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
14179 : : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
14180 : : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
14181 : : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
14182 : : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
14183 [ # # # # ]: 0 : if (!is_proxy || !flow_attr->transfer)
14184 : : return false;
14185 [ # # ]: 0 : if (action[0].type == RTE_FLOW_ACTION_TYPE_RAW_DECAP &&
14186 [ # # ]: 0 : action[1].type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP)
14187 : : return false;
14188 : : break;
14189 : : case RTE_FLOW_ACTION_TYPE_JUMP_TO_TABLE_INDEX:
14190 : : break;
14191 : : default:
14192 : : return false;
14193 : : }
14194 : 0 : return true;
14195 : : }
14196 : :
14197 : : /**
14198 : : * Valid mirror actions list includes one or two SAMPLE actions
14199 : : * followed by JUMP.
14200 : : *
14201 : : * @return
14202 : : * Number of mirrors *action* list was valid.
14203 : : * -EINVAL otherwise.
14204 : : */
14205 : : static int
14206 : 0 : mlx5_hw_mirror_actions_list_validate(struct rte_eth_dev *dev,
14207 : : const struct rte_flow_attr *flow_attr,
14208 : : const struct rte_flow_action *actions)
14209 : : {
14210 [ # # ]: 0 : if (actions[0].type == RTE_FLOW_ACTION_TYPE_SAMPLE) {
14211 : : int i = 1;
14212 : : bool valid;
14213 : 0 : const struct rte_flow_action_sample *sample = actions[0].conf;
14214 : 0 : valid = mlx5_mirror_validate_sample_action(dev, flow_attr,
14215 : 0 : sample->actions);
14216 [ # # ]: 0 : if (!valid)
14217 : : return -EINVAL;
14218 [ # # ]: 0 : if (actions[1].type == RTE_FLOW_ACTION_TYPE_SAMPLE) {
14219 : : i = 2;
14220 : 0 : sample = actions[1].conf;
14221 : 0 : valid = mlx5_mirror_validate_sample_action(dev, flow_attr,
14222 : 0 : sample->actions);
14223 [ # # ]: 0 : if (!valid)
14224 : : return -EINVAL;
14225 : : }
14226 [ # # ]: 0 : return mlx5_mirror_terminal_action(actions + i) ? i + 1 : -EINVAL;
14227 : : }
14228 : : return -EINVAL;
14229 : : }
14230 : :
14231 : : static int
14232 [ # # ]: 0 : mirror_format_tir(struct rte_eth_dev *dev,
14233 : : struct mlx5_mirror_clone *clone,
14234 : : const struct mlx5_flow_template_table_cfg *table_cfg,
14235 : : const struct rte_flow_action *action,
14236 : : struct mlx5dr_action_dest_attr *dest_attr,
14237 : : struct rte_flow_error *error)
14238 : : {
14239 : : uint32_t hws_flags;
14240 : : enum mlx5dr_table_type table_type;
14241 : : struct mlx5_hrxq *tir_ctx;
14242 : :
14243 : : table_type = get_mlx5dr_table_type(&table_cfg->attr.flow_attr);
14244 : 0 : hws_flags = mlx5_hw_act_flag[MLX5_HW_ACTION_FLAG_NONE_ROOT][table_type];
14245 : 0 : tir_ctx = flow_hw_tir_action_register(dev, hws_flags, action);
14246 [ # # ]: 0 : if (!tir_ctx)
14247 : 0 : return rte_flow_error_set(error, EINVAL,
14248 : : RTE_FLOW_ERROR_TYPE_ACTION,
14249 : : action, "failed to create QUEUE action for mirror clone");
14250 : 0 : dest_attr->dest = tir_ctx->action;
14251 : 0 : clone->action_ctx = tir_ctx;
14252 : 0 : return 0;
14253 : : }
14254 : :
14255 : : static int
14256 : 0 : mirror_format_jump(struct rte_eth_dev *dev,
14257 : : struct mlx5_mirror_clone *clone,
14258 : : const struct mlx5_flow_template_table_cfg *table_cfg,
14259 : : const struct rte_flow_action *action,
14260 : : struct mlx5dr_action_dest_attr *dest_attr,
14261 : : struct rte_flow_error *error)
14262 : : {
14263 : 0 : const struct rte_flow_action_jump *jump_conf = action->conf;
14264 : 0 : struct mlx5_hw_jump_action *jump = flow_hw_jump_action_register
14265 : : (dev, table_cfg,
14266 : 0 : jump_conf->group, error);
14267 : :
14268 [ # # ]: 0 : if (!jump)
14269 : 0 : return rte_flow_error_set(error, EINVAL,
14270 : : RTE_FLOW_ERROR_TYPE_ACTION,
14271 : : action, "failed to create JUMP action for mirror clone");
14272 : 0 : dest_attr->dest = jump->hws_action;
14273 : 0 : clone->action_ctx = jump;
14274 : 0 : return 0;
14275 : : }
14276 : :
14277 : : static int
14278 : : mirror_format_port(struct rte_eth_dev *dev,
14279 : : const struct rte_flow_action *action,
14280 : : struct mlx5dr_action_dest_attr *dest_attr,
14281 : : struct rte_flow_error __rte_unused *error)
14282 : : {
14283 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14284 : 0 : const struct rte_flow_action_ethdev *port_action = action->conf;
14285 : :
14286 : 0 : dest_attr->dest = priv->hw_vport[port_action->port_id];
14287 : : return 0;
14288 : : }
14289 : :
14290 : : static int
14291 : 0 : hw_mirror_clone_reformat(const struct rte_flow_action *actions,
14292 : : struct mlx5dr_action_dest_attr *dest_attr,
14293 : : enum mlx5dr_action_type *action_type,
14294 : : uint8_t *reformat_buf, bool decap)
14295 : : {
14296 : : int ret;
14297 : : const struct rte_flow_item *encap_item = NULL;
14298 : : const struct rte_flow_action_raw_encap *encap_conf = NULL;
14299 : : typeof(dest_attr->reformat) *reformat = &dest_attr->reformat;
14300 : :
14301 [ # # # # ]: 0 : switch (actions[0].type) {
14302 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
14303 : 0 : encap_conf = actions[0].conf;
14304 : 0 : break;
14305 : 0 : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
14306 : 0 : encap_item = MLX5_CONST_ENCAP_ITEM(rte_flow_action_vxlan_encap,
14307 : : actions);
14308 : 0 : break;
14309 : 0 : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
14310 : 0 : encap_item = MLX5_CONST_ENCAP_ITEM(rte_flow_action_nvgre_encap,
14311 : : actions);
14312 : 0 : break;
14313 : : default:
14314 : : return -EINVAL;
14315 : : }
14316 : 0 : *action_type = decap ?
14317 [ # # ]: 0 : MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3 :
14318 : : MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;
14319 [ # # ]: 0 : if (encap_item) {
14320 : 0 : ret = flow_dv_convert_encap_data(encap_item, reformat_buf,
14321 : : &reformat->reformat_data_sz, NULL);
14322 [ # # ]: 0 : if (ret)
14323 : : return -EINVAL;
14324 : 0 : reformat->reformat_data = reformat_buf;
14325 : : } else {
14326 : 0 : reformat->reformat_data = (void *)(uintptr_t)encap_conf->data;
14327 : 0 : reformat->reformat_data_sz = encap_conf->size;
14328 : : }
14329 : : return 0;
14330 : : }
14331 : :
14332 : : static int
14333 : 0 : hw_mirror_format_clone(struct rte_eth_dev *dev,
14334 : : struct mlx5_mirror_clone *clone,
14335 : : const struct mlx5_flow_template_table_cfg *table_cfg,
14336 : : const struct rte_flow_action *actions,
14337 : : struct mlx5dr_action_dest_attr *dest_attr,
14338 : : uint8_t *reformat_buf, struct rte_flow_error *error)
14339 : : {
14340 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14341 : : int ret;
14342 : : uint32_t i;
14343 : : bool decap_seen = false;
14344 : :
14345 [ # # ]: 0 : for (i = 0; actions[i].type != RTE_FLOW_ACTION_TYPE_END; i++) {
14346 : 0 : dest_attr->action_type[i] = mlx5_hw_dr_action_types[actions[i].type];
14347 [ # # # # : 0 : switch (actions[i].type) {
# # # ]
14348 : 0 : case RTE_FLOW_ACTION_TYPE_QUEUE:
14349 : : case RTE_FLOW_ACTION_TYPE_RSS:
14350 : 0 : ret = mirror_format_tir(dev, clone, table_cfg,
14351 : : &actions[i], dest_attr, error);
14352 [ # # ]: 0 : if (ret)
14353 : 0 : return ret;
14354 : : break;
14355 : 0 : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
14356 : : ret = mirror_format_port(dev, &actions[i],
14357 : : dest_attr, error);
14358 : : if (ret)
14359 : : return ret;
14360 : : break;
14361 : 0 : case RTE_FLOW_ACTION_TYPE_JUMP:
14362 : 0 : ret = mirror_format_jump(dev, clone, table_cfg,
14363 : : &actions[i], dest_attr, error);
14364 [ # # ]: 0 : if (ret)
14365 : 0 : return ret;
14366 : : break;
14367 : 0 : case RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:
14368 : 0 : dest_attr->dest = priv->hw_def_miss;
14369 : 0 : break;
14370 : : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
14371 : : decap_seen = true;
14372 : : break;
14373 : 0 : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
14374 : : case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
14375 : : case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
14376 : 0 : ret = hw_mirror_clone_reformat(&actions[i], dest_attr,
14377 : : &dest_attr->action_type[i],
14378 : : reformat_buf, decap_seen);
14379 [ # # ]: 0 : if (ret < 0)
14380 : 0 : return rte_flow_error_set(error, EINVAL,
14381 : : RTE_FLOW_ERROR_TYPE_ACTION,
14382 : : &actions[i],
14383 : : "failed to create reformat action");
14384 : : break;
14385 : 0 : default:
14386 : 0 : return rte_flow_error_set(error, EINVAL,
14387 : : RTE_FLOW_ERROR_TYPE_ACTION,
14388 : : &actions[i], "unsupported sample action");
14389 : : }
14390 : 0 : clone->type = actions->type;
14391 : : }
14392 : 0 : dest_attr->action_type[i] = MLX5DR_ACTION_TYP_LAST;
14393 : 0 : return 0;
14394 : : }
14395 : :
14396 : : static struct rte_flow_action_list_handle *
14397 : 0 : mlx5_hw_mirror_handle_create(struct rte_eth_dev *dev,
14398 : : const struct mlx5_flow_template_table_cfg *table_cfg,
14399 : : const struct rte_flow_action *actions,
14400 : : struct rte_flow_error *error)
14401 : : {
14402 : : uint32_t hws_flags;
14403 : : int ret = 0, i, clones_num;
14404 : : struct mlx5_mirror *mirror;
14405 : : enum mlx5dr_table_type table_type;
14406 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14407 [ # # ]: 0 : const struct rte_flow_attr *flow_attr = &table_cfg->attr.flow_attr;
14408 : : uint8_t reformat_buf[MLX5_MIRROR_MAX_CLONES_NUM][MLX5_ENCAP_MAX_LEN];
14409 : : struct mlx5dr_action_dest_attr mirror_attr[MLX5_MIRROR_MAX_CLONES_NUM + 1];
14410 : : enum mlx5dr_action_type array_action_types[MLX5_MIRROR_MAX_CLONES_NUM + 1]
14411 : : [MLX5_MIRROR_MAX_SAMPLE_ACTIONS_LEN + 1];
14412 : :
14413 : : memset(mirror_attr, 0, sizeof(mirror_attr));
14414 : : memset(array_action_types, 0, sizeof(array_action_types));
14415 : : table_type = get_mlx5dr_table_type(flow_attr);
14416 : 0 : hws_flags = mlx5_hw_act_flag[MLX5_HW_ACTION_FLAG_NONE_ROOT][table_type];
14417 : 0 : clones_num = mlx5_hw_mirror_actions_list_validate(dev, flow_attr,
14418 : : actions);
14419 [ # # ]: 0 : if (clones_num < 0) {
14420 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14421 : : actions, "Invalid mirror list format");
14422 : 0 : return NULL;
14423 : : }
14424 : 0 : mirror = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mirror),
14425 : : 0, SOCKET_ID_ANY);
14426 [ # # ]: 0 : if (!mirror) {
14427 : 0 : rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_ACTION,
14428 : : actions, "Failed to allocate mirror context");
14429 : 0 : return NULL;
14430 : : }
14431 : :
14432 : 0 : mirror->indirect.type = MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR;
14433 : 0 : mirror->clones_num = clones_num;
14434 [ # # ]: 0 : for (i = 0; i < clones_num; i++) {
14435 : : const struct rte_flow_action *clone_actions;
14436 : :
14437 : 0 : mirror_attr[i].action_type = array_action_types[i];
14438 [ # # ]: 0 : if (actions[i].type == RTE_FLOW_ACTION_TYPE_SAMPLE) {
14439 : 0 : const struct rte_flow_action_sample *sample = actions[i].conf;
14440 : :
14441 : 0 : clone_actions = sample->actions;
14442 : : } else {
14443 : : clone_actions = &actions[i];
14444 : : }
14445 : 0 : ret = hw_mirror_format_clone(dev, &mirror->clone[i], table_cfg,
14446 : : clone_actions, &mirror_attr[i],
14447 : 0 : reformat_buf[i], error);
14448 : :
14449 [ # # ]: 0 : if (ret)
14450 : 0 : goto error;
14451 : : }
14452 : 0 : hws_flags |= MLX5DR_ACTION_FLAG_SHARED;
14453 : 0 : mirror->mirror_action = mlx5dr_action_create_dest_array(priv->dr_ctx,
14454 : : clones_num,
14455 : : mirror_attr,
14456 : : hws_flags);
14457 [ # # ]: 0 : if (!mirror->mirror_action) {
14458 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14459 : : actions, "Failed to create HWS mirror action");
14460 : 0 : goto error;
14461 : : }
14462 : :
14463 [ # # ]: 0 : mlx5_indirect_list_add_entry(&priv->indirect_list_head, &mirror->indirect);
14464 : 0 : return (struct rte_flow_action_list_handle *)mirror;
14465 : :
14466 : 0 : error:
14467 : 0 : mlx5_hw_mirror_destroy(dev, mirror);
14468 : 0 : return NULL;
14469 : : }
14470 : :
14471 : : void
14472 : 0 : mlx5_destroy_legacy_indirect(__rte_unused struct rte_eth_dev *dev,
14473 : : struct mlx5_indirect_list *ptr)
14474 : : {
14475 : : struct mlx5_indlst_legacy *obj = (typeof(obj))ptr;
14476 : :
14477 : : switch (obj->legacy_type) {
14478 : : case RTE_FLOW_ACTION_TYPE_METER_MARK:
14479 : : break; /* ASO meters were released in mlx5_flow_meter_flush() */
14480 : : default:
14481 : : break;
14482 : : }
14483 : 0 : mlx5_free(obj);
14484 : 0 : }
14485 : :
14486 : : static struct rte_flow_action_list_handle *
14487 : 0 : mlx5_create_legacy_indlst(struct rte_eth_dev *dev, uint32_t queue,
14488 : : const struct rte_flow_op_attr *attr,
14489 : : const struct rte_flow_indir_action_conf *conf,
14490 : : const struct rte_flow_action *actions,
14491 : : void *user_data, struct rte_flow_error *error)
14492 : : {
14493 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14494 : 0 : struct mlx5_indlst_legacy *indlst_obj = mlx5_malloc(MLX5_MEM_ZERO,
14495 : : sizeof(*indlst_obj),
14496 : : 0, SOCKET_ID_ANY);
14497 : :
14498 [ # # ]: 0 : if (!indlst_obj)
14499 : : return NULL;
14500 : 0 : indlst_obj->handle = flow_hw_action_handle_create(dev, queue, attr, conf,
14501 : : actions, user_data,
14502 : : error);
14503 [ # # ]: 0 : if (!indlst_obj->handle) {
14504 : 0 : mlx5_free(indlst_obj);
14505 : 0 : return NULL;
14506 : : }
14507 : 0 : indlst_obj->legacy_type = actions[0].type;
14508 : 0 : indlst_obj->indirect.type = MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY;
14509 [ # # ]: 0 : mlx5_indirect_list_add_entry(&priv->indirect_list_head, &indlst_obj->indirect);
14510 : 0 : return (struct rte_flow_action_list_handle *)indlst_obj;
14511 : : }
14512 : :
14513 : : static __rte_always_inline enum mlx5_indirect_list_type
14514 : : flow_hw_inlist_type_get(const struct rte_flow_action *actions)
14515 : : {
14516 [ # # # # ]: 0 : switch (actions[0].type) {
14517 : : case RTE_FLOW_ACTION_TYPE_SAMPLE:
14518 : : return MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR;
14519 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
14520 : 0 : return actions[1].type == RTE_FLOW_ACTION_TYPE_END ?
14521 : 0 : MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY :
14522 : : MLX5_INDIRECT_ACTION_LIST_TYPE_ERR;
14523 : : case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
14524 : : case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
14525 : : return MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT;
14526 : : default:
14527 : : break;
14528 : : }
14529 : : return MLX5_INDIRECT_ACTION_LIST_TYPE_ERR;
14530 : : }
14531 : :
14532 : : static struct rte_flow_action_list_handle*
14533 : 0 : mlx5_hw_decap_encap_handle_create(struct rte_eth_dev *dev,
14534 : : const struct mlx5_flow_template_table_cfg *table_cfg,
14535 : : const struct rte_flow_action *actions,
14536 : : struct rte_flow_error *error)
14537 : : {
14538 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14539 : : const struct rte_flow_attr *flow_attr = &table_cfg->attr.flow_attr;
14540 : : const struct rte_flow_action *encap = NULL;
14541 : : const struct rte_flow_action *decap = NULL;
14542 : 0 : struct rte_flow_indir_action_conf indirect_conf = {
14543 : 0 : .ingress = flow_attr->ingress,
14544 : 0 : .egress = flow_attr->egress,
14545 : 0 : .transfer = flow_attr->transfer,
14546 : : };
14547 : : struct mlx5_hw_encap_decap_action *handle;
14548 : : uint64_t action_flags = 0;
14549 : :
14550 : : /*
14551 : : * Allow
14552 : : * 1. raw_decap / raw_encap / end
14553 : : * 2. raw_encap / end
14554 : : * 3. raw_decap / end
14555 : : */
14556 [ # # ]: 0 : while (actions->type != RTE_FLOW_ACTION_TYPE_END) {
14557 [ # # ]: 0 : if (actions->type == RTE_FLOW_ACTION_TYPE_RAW_DECAP) {
14558 [ # # ]: 0 : if (action_flags) {
14559 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14560 : : actions, "Invalid indirect action list sequence");
14561 : 0 : return NULL;
14562 : : }
14563 : : action_flags |= MLX5_FLOW_ACTION_DECAP;
14564 : : decap = actions;
14565 [ # # ]: 0 : } else if (actions->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
14566 [ # # ]: 0 : if (action_flags & MLX5_FLOW_ACTION_ENCAP) {
14567 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14568 : : actions, "Invalid indirect action list sequence");
14569 : 0 : return NULL;
14570 : : }
14571 : 0 : action_flags |= MLX5_FLOW_ACTION_ENCAP;
14572 : : encap = actions;
14573 : : } else {
14574 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14575 : : actions, "Invalid indirect action type in list");
14576 : 0 : return NULL;
14577 : : }
14578 : 0 : actions++;
14579 : : }
14580 [ # # ]: 0 : if (!decap && !encap) {
14581 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14582 : : actions, "Invalid indirect action combinations");
14583 : 0 : return NULL;
14584 : : }
14585 : 0 : handle = mlx5_reformat_action_create(dev, &indirect_conf, encap, decap, error);
14586 [ # # ]: 0 : if (!handle) {
14587 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14588 : : actions, "Failed to create HWS decap_encap action");
14589 : 0 : return NULL;
14590 : : }
14591 : 0 : handle->indirect.type = MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT;
14592 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->indirect_list_head, &handle->indirect, entry);
14593 : 0 : return (struct rte_flow_action_list_handle *)handle;
14594 : : }
14595 : :
14596 : : static struct rte_flow_action_list_handle *
14597 [ # # ]: 0 : flow_hw_async_action_list_handle_create(struct rte_eth_dev *dev, uint32_t queue,
14598 : : const struct rte_flow_op_attr *attr,
14599 : : const struct rte_flow_indir_action_conf *conf,
14600 : : const struct rte_flow_action *actions,
14601 : : void *user_data,
14602 : : struct rte_flow_error *error)
14603 : : {
14604 : : struct mlx5_hw_q_job *job = NULL;
14605 : : bool push = flow_hw_action_push(attr);
14606 : : enum mlx5_indirect_list_type list_type;
14607 : : struct rte_flow_action_list_handle *handle;
14608 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14609 : 0 : const struct mlx5_flow_template_table_cfg table_cfg = {
14610 : : .external = true,
14611 : : .attr = {
14612 : : .flow_attr = {
14613 : 0 : .ingress = conf->ingress,
14614 : 0 : .egress = conf->egress,
14615 : 0 : .transfer = conf->transfer
14616 : : }
14617 : : }
14618 : : };
14619 : :
14620 [ # # ]: 0 : if (!mlx5_hw_ctx_validate(dev, error))
14621 : : return NULL;
14622 [ # # ]: 0 : if (!actions) {
14623 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14624 : : NULL, "No action list");
14625 : 0 : return NULL;
14626 : : }
14627 : : list_type = flow_hw_inlist_type_get(actions);
14628 [ # # ]: 0 : if (list_type == MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY) {
14629 : : /*
14630 : : * Legacy indirect actions already have
14631 : : * async resources management. No need to do it twice.
14632 : : */
14633 : 0 : handle = mlx5_create_legacy_indlst(dev, queue, attr, conf,
14634 : : actions, user_data, error);
14635 : 0 : goto end;
14636 : : }
14637 [ # # ]: 0 : if (attr) {
14638 : : job = flow_hw_action_job_init(priv, queue, NULL, user_data,
14639 : : NULL, MLX5_HW_Q_JOB_TYPE_CREATE,
14640 : : MLX5_HW_INDIRECT_TYPE_LIST, error);
14641 : : if (!job)
14642 : 0 : return NULL;
14643 : : }
14644 [ # # # ]: 0 : switch (list_type) {
14645 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR:
14646 : 0 : handle = mlx5_hw_mirror_handle_create(dev, &table_cfg,
14647 : : actions, error);
14648 : 0 : break;
14649 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT:
14650 : 0 : handle = mlx5_hw_decap_encap_handle_create(dev, &table_cfg,
14651 : : actions, error);
14652 : 0 : break;
14653 : 0 : default:
14654 : : handle = NULL;
14655 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
14656 : : actions, "Invalid list");
14657 : : }
14658 [ # # ]: 0 : if (job) {
14659 : 0 : job->action = handle;
14660 [ # # ]: 0 : flow_hw_action_finalize(dev, queue, job, push, false,
14661 : : handle != NULL);
14662 : : }
14663 : 0 : end:
14664 : : return handle;
14665 : : }
14666 : :
14667 : : static struct rte_flow_action_list_handle *
14668 : 0 : flow_hw_action_list_handle_create(struct rte_eth_dev *dev,
14669 : : const struct rte_flow_indir_action_conf *conf,
14670 : : const struct rte_flow_action *actions,
14671 : : struct rte_flow_error *error)
14672 : : {
14673 : 0 : return flow_hw_async_action_list_handle_create(dev, MLX5_HW_INV_QUEUE,
14674 : : NULL, conf, actions,
14675 : : NULL, error);
14676 : : }
14677 : :
14678 : : static int
14679 [ # # ]: 0 : flow_hw_async_action_list_handle_destroy
14680 : : (struct rte_eth_dev *dev, uint32_t queue,
14681 : : const struct rte_flow_op_attr *attr,
14682 : : struct rte_flow_action_list_handle *handle,
14683 : : void *user_data, struct rte_flow_error *error)
14684 : : {
14685 : : int ret = 0;
14686 : : struct mlx5_hw_q_job *job = NULL;
14687 : : bool push = flow_hw_action_push(attr);
14688 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
14689 : : enum mlx5_indirect_list_type type =
14690 : : mlx5_get_indirect_list_type((void *)handle);
14691 : :
14692 [ # # ]: 0 : if (type == MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY) {
14693 : : struct mlx5_indlst_legacy *legacy = (typeof(legacy))handle;
14694 : :
14695 : 0 : ret = flow_hw_action_handle_destroy(dev, queue, attr,
14696 : : legacy->handle,
14697 : : user_data, error);
14698 : : mlx5_indirect_list_remove_entry(&legacy->indirect);
14699 : 0 : goto end;
14700 : : }
14701 [ # # ]: 0 : if (attr) {
14702 : : job = flow_hw_action_job_init(priv, queue, NULL, user_data,
14703 : : NULL, MLX5_HW_Q_JOB_TYPE_DESTROY,
14704 : : MLX5_HW_INDIRECT_TYPE_LIST, error);
14705 : : if (!job)
14706 : 0 : return rte_errno;
14707 : : }
14708 [ # # # ]: 0 : switch (type) {
14709 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR:
14710 : 0 : mlx5_hw_mirror_destroy(dev, (struct mlx5_mirror *)handle);
14711 : 0 : break;
14712 : 0 : case MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT:
14713 [ # # ]: 0 : LIST_REMOVE(&((struct mlx5_hw_encap_decap_action *)handle)->indirect,
14714 : : entry);
14715 : 0 : mlx5_reformat_action_destroy(dev, handle, error);
14716 : 0 : break;
14717 : 0 : default:
14718 : 0 : ret = rte_flow_error_set(error, EINVAL,
14719 : : RTE_FLOW_ERROR_TYPE_ACTION,
14720 : : NULL, "Invalid indirect list handle");
14721 : : }
14722 [ # # ]: 0 : if (job) {
14723 : : flow_hw_action_finalize(dev, queue, job, push, false, true);
14724 : : }
14725 : 0 : end:
14726 : : return ret;
14727 : : }
14728 : :
14729 : : static int
14730 : 0 : flow_hw_action_list_handle_destroy(struct rte_eth_dev *dev,
14731 : : struct rte_flow_action_list_handle *handle,
14732 : : struct rte_flow_error *error)
14733 : : {
14734 : 0 : return flow_hw_async_action_list_handle_destroy(dev, MLX5_HW_INV_QUEUE,
14735 : : NULL, handle, NULL,
14736 : : error);
14737 : : }
14738 : :
14739 : : static int
14740 [ # # ]: 0 : flow_hw_async_action_list_handle_query_update
14741 : : (struct rte_eth_dev *dev, uint32_t queue_id,
14742 : : const struct rte_flow_op_attr *attr,
14743 : : const struct rte_flow_action_list_handle *handle,
14744 : : const void **update, void **query,
14745 : : enum rte_flow_query_update_mode mode,
14746 : : void *user_data, struct rte_flow_error *error)
14747 : : {
14748 : : enum mlx5_indirect_list_type type =
14749 : : mlx5_get_indirect_list_type((const void *)handle);
14750 : :
14751 [ # # ]: 0 : if (type == MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY) {
14752 : : struct mlx5_indlst_legacy *legacy = (void *)(uintptr_t)handle;
14753 : :
14754 [ # # ]: 0 : if (update && query)
14755 : 0 : return flow_hw_async_action_handle_query_update
14756 : : (dev, queue_id, attr, legacy->handle,
14757 : : update, query, mode, user_data, error);
14758 [ # # # # ]: 0 : else if (update && update[0])
14759 : 0 : return flow_hw_action_handle_update(dev, queue_id, attr,
14760 : : legacy->handle, update[0],
14761 : : user_data, error);
14762 [ # # # # ]: 0 : else if (query && query[0])
14763 : 0 : return flow_hw_action_handle_query(dev, queue_id, attr,
14764 : 0 : legacy->handle, query[0],
14765 : : user_data, error);
14766 : : else
14767 : 0 : return rte_flow_error_set(error, EINVAL,
14768 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14769 : : NULL, "invalid legacy handle query_update parameters");
14770 : : }
14771 : : return -ENOTSUP;
14772 : : }
14773 : :
14774 : : static int
14775 : 0 : flow_hw_action_list_handle_query_update(struct rte_eth_dev *dev,
14776 : : const struct rte_flow_action_list_handle *handle,
14777 : : const void **update, void **query,
14778 : : enum rte_flow_query_update_mode mode,
14779 : : struct rte_flow_error *error)
14780 : : {
14781 : 0 : return flow_hw_async_action_list_handle_query_update
14782 : : (dev, MLX5_HW_INV_QUEUE, NULL, handle,
14783 : : update, query, mode, NULL, error);
14784 : : }
14785 : :
14786 : : static int
14787 : 0 : flow_hw_calc_table_hash(struct rte_eth_dev *dev,
14788 : : const struct rte_flow_template_table *table,
14789 : : const struct rte_flow_item pattern[],
14790 : : uint8_t pattern_template_index,
14791 : : uint32_t *hash, struct rte_flow_error *error)
14792 : : {
14793 : : const struct rte_flow_item *items;
14794 : : struct mlx5_flow_hw_pattern_params pp;
14795 : : int res;
14796 : :
14797 : 0 : items = flow_hw_get_rule_items(dev, table, pattern,
14798 : : pattern_template_index,
14799 : : &pp);
14800 : 0 : res = mlx5dr_rule_hash_calculate(mlx5_table_matcher(table), items,
14801 : : pattern_template_index,
14802 : : MLX5DR_RULE_HASH_CALC_MODE_RAW,
14803 : : hash);
14804 [ # # ]: 0 : if (res)
14805 : 0 : return rte_flow_error_set(error, res,
14806 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14807 : : NULL,
14808 : : "hash could not be calculated");
14809 : : return 0;
14810 : : }
14811 : :
14812 : : static int
14813 : 0 : flow_hw_calc_encap_hash(struct rte_eth_dev *dev,
14814 : : const struct rte_flow_item pattern[],
14815 : : enum rte_flow_encap_hash_field dest_field,
14816 : : uint8_t *hash,
14817 : : struct rte_flow_error *error)
14818 : : {
14819 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14820 : : struct mlx5dr_crc_encap_entropy_hash_fields data;
14821 : 0 : enum mlx5dr_crc_encap_entropy_hash_size res_size =
14822 : : dest_field == RTE_FLOW_ENCAP_HASH_FIELD_SRC_PORT ?
14823 : 0 : MLX5DR_CRC_ENCAP_ENTROPY_HASH_SIZE_16 :
14824 : : MLX5DR_CRC_ENCAP_ENTROPY_HASH_SIZE_8;
14825 : : int res;
14826 : :
14827 : : memset(&data, 0, sizeof(struct mlx5dr_crc_encap_entropy_hash_fields));
14828 : :
14829 [ # # ]: 0 : for (; pattern->type != RTE_FLOW_ITEM_TYPE_END; pattern++) {
14830 [ # # # # : 0 : switch (pattern->type) {
# # # ]
14831 : 0 : case RTE_FLOW_ITEM_TYPE_IPV4:
14832 : 0 : data.dst.ipv4_addr =
14833 : 0 : ((const struct rte_flow_item_ipv4 *)(pattern->spec))->hdr.dst_addr;
14834 : 0 : data.src.ipv4_addr =
14835 : 0 : ((const struct rte_flow_item_ipv4 *)(pattern->spec))->hdr.src_addr;
14836 : 0 : break;
14837 : 0 : case RTE_FLOW_ITEM_TYPE_IPV6:
14838 : : memcpy(data.dst.ipv6_addr,
14839 : 0 : &((const struct rte_flow_item_ipv6 *)(pattern->spec))->hdr.dst_addr,
14840 : : sizeof(data.dst.ipv6_addr));
14841 : : memcpy(data.src.ipv6_addr,
14842 : : &((const struct rte_flow_item_ipv6 *)(pattern->spec))->hdr.src_addr,
14843 : : sizeof(data.src.ipv6_addr));
14844 : : break;
14845 : 0 : case RTE_FLOW_ITEM_TYPE_UDP:
14846 : 0 : data.next_protocol = IPPROTO_UDP;
14847 : 0 : data.dst_port =
14848 : 0 : ((const struct rte_flow_item_udp *)(pattern->spec))->hdr.dst_port;
14849 : 0 : data.src_port =
14850 : 0 : ((const struct rte_flow_item_udp *)(pattern->spec))->hdr.src_port;
14851 : 0 : break;
14852 : 0 : case RTE_FLOW_ITEM_TYPE_TCP:
14853 : 0 : data.next_protocol = IPPROTO_TCP;
14854 : 0 : data.dst_port =
14855 : 0 : ((const struct rte_flow_item_tcp *)(pattern->spec))->hdr.dst_port;
14856 : 0 : data.src_port =
14857 : 0 : ((const struct rte_flow_item_tcp *)(pattern->spec))->hdr.src_port;
14858 : 0 : break;
14859 : 0 : case RTE_FLOW_ITEM_TYPE_ICMP:
14860 : 0 : data.next_protocol = IPPROTO_ICMP;
14861 : 0 : break;
14862 : 0 : case RTE_FLOW_ITEM_TYPE_ICMP6:
14863 : 0 : data.next_protocol = IPPROTO_ICMPV6;
14864 : 0 : break;
14865 : : default:
14866 : : break;
14867 : : }
14868 : : }
14869 : 0 : res = mlx5dr_crc_encap_entropy_hash_calc(priv->dr_ctx, &data, hash, res_size);
14870 [ # # ]: 0 : if (res)
14871 : 0 : return rte_flow_error_set(error, res,
14872 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14873 : : NULL, "error while calculating encap hash");
14874 : : return 0;
14875 : : }
14876 : :
14877 : : static int
14878 : 0 : flow_hw_table_resize_multi_pattern_actions(struct rte_eth_dev *dev,
14879 : : struct rte_flow_template_table *table,
14880 : : uint32_t nb_flows,
14881 : : struct rte_flow_error *error)
14882 : : {
14883 : 0 : struct mlx5_multi_pattern_segment *segment = table->mpctx.segments;
14884 : : uint32_t bulk_size;
14885 : : int i, ret;
14886 : :
14887 : : /**
14888 : : * Segment always allocates Modify Header Argument Objects number in
14889 : : * powers of 2.
14890 : : * On resize, PMD adds minimal required argument objects number.
14891 : : * For example, if table size was 10, it allocated 16 argument objects.
14892 : : * Resize to 15 will not add new objects.
14893 : : */
14894 : 0 : for (i = 1;
14895 [ # # # # ]: 0 : i < MLX5_MAX_TABLE_RESIZE_NUM && segment->capacity;
14896 : 0 : i++, segment++) {
14897 : : /* keep the devtools/checkpatches.sh happy */
14898 : : }
14899 [ # # ]: 0 : if (i == MLX5_MAX_TABLE_RESIZE_NUM)
14900 : 0 : return rte_flow_error_set(error, EINVAL,
14901 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14902 : : table, "too many resizes");
14903 [ # # ]: 0 : if (segment->head_index - 1 >= nb_flows)
14904 : : return 0;
14905 [ # # ]: 0 : bulk_size = rte_align32pow2(nb_flows - segment->head_index + 1);
14906 : 0 : ret = mlx5_tbl_multi_pattern_process(dev, table, segment,
14907 : : rte_log2_u32(bulk_size),
14908 : : error);
14909 [ # # ]: 0 : if (ret)
14910 : 0 : return rte_flow_error_set(error, EINVAL,
14911 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14912 : : table, "too many resizes");
14913 : : return i;
14914 : : }
14915 : :
14916 : : static int
14917 : 0 : flow_hw_table_resize(struct rte_eth_dev *dev,
14918 : : struct rte_flow_template_table *table,
14919 : : uint32_t nb_flows,
14920 : : struct rte_flow_error *error)
14921 : : {
14922 : : struct mlx5dr_action_template *at[MLX5_HW_TBL_MAX_ACTION_TEMPLATE];
14923 : : struct mlx5dr_match_template *mt[MLX5_HW_TBL_MAX_ITEM_TEMPLATE];
14924 : 0 : struct mlx5dr_matcher_attr matcher_attr = table->matcher_attr;
14925 : 0 : struct mlx5dr_action_jump_to_matcher_attr jump_attr = {
14926 : : .type = MLX5DR_ACTION_JUMP_TO_MATCHER_BY_INDEX,
14927 : : .matcher = NULL,
14928 : : };
14929 : : struct mlx5_multi_pattern_segment *segment = NULL;
14930 : : struct mlx5dr_matcher *matcher = NULL;
14931 : : struct mlx5dr_action *jump = NULL;
14932 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
14933 : 0 : uint32_t i, selector = table->matcher_selector;
14934 : 0 : uint32_t other_selector = (selector + 1) & 1;
14935 : : int ret;
14936 : :
14937 [ # # ]: 0 : if (!rte_flow_template_table_resizable(dev->data->port_id, &table->cfg.attr))
14938 : 0 : return rte_flow_error_set(error, EINVAL,
14939 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14940 : : table, "no resizable attribute");
14941 [ # # ]: 0 : if (table->matcher_info[other_selector].matcher)
14942 : 0 : return rte_flow_error_set(error, EINVAL,
14943 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14944 : : table, "last table resize was not completed");
14945 [ # # ]: 0 : if (nb_flows <= table->cfg.attr.nb_flows)
14946 : 0 : return rte_flow_error_set(error, EINVAL,
14947 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14948 : : table, "shrinking table is not supported");
14949 : 0 : ret = mlx5_ipool_resize(table->flow, nb_flows, error);
14950 [ # # ]: 0 : if (ret)
14951 : : return ret;
14952 : : /*
14953 : : * A resizable matcher doesn't support rule update. In this case, the ipool
14954 : : * for the resource is not created and there is no need to resize it.
14955 : : */
14956 : : MLX5_ASSERT(!table->resource);
14957 [ # # ]: 0 : if (mlx5_is_multi_pattern_active(&table->mpctx)) {
14958 : 0 : ret = flow_hw_table_resize_multi_pattern_actions(dev, table, nb_flows, error);
14959 [ # # ]: 0 : if (ret < 0)
14960 : : return ret;
14961 [ # # ]: 0 : if (ret > 0)
14962 : 0 : segment = table->mpctx.segments + ret;
14963 : : }
14964 [ # # ]: 0 : for (i = 0; i < table->nb_item_templates; i++)
14965 : 0 : mt[i] = table->its[i]->mt;
14966 [ # # ]: 0 : for (i = 0; i < table->nb_action_templates; i++)
14967 : 0 : at[i] = table->ats[i].action_template->tmpl;
14968 : : nb_flows = rte_align32pow2(nb_flows);
14969 : 0 : matcher_attr.rule.num_log = rte_log2_u32(nb_flows);
14970 : 0 : matcher = mlx5dr_matcher_create(table->grp->tbl, mt,
14971 : : table->nb_item_templates, at,
14972 : : table->nb_action_templates,
14973 : : &matcher_attr);
14974 [ # # ]: 0 : if (!matcher) {
14975 : 0 : ret = rte_flow_error_set(error, rte_errno,
14976 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14977 : : table, "failed to create new matcher");
14978 : 0 : goto error;
14979 : : }
14980 [ # # ]: 0 : if (matcher_attr.isolated) {
14981 : 0 : jump_attr.matcher = matcher;
14982 : 0 : jump = mlx5dr_action_create_jump_to_matcher(priv->dr_ctx, &jump_attr,
14983 : 0 : mlx5_hw_act_flag[!!table->cfg.attr.flow_attr.group][table->type]);
14984 [ # # ]: 0 : if (!jump) {
14985 : 0 : ret = rte_flow_error_set(error, rte_errno,
14986 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14987 : : table, "failed to create jump to matcher action");
14988 : 0 : goto error;
14989 : : }
14990 : : }
14991 : 0 : rte_rwlock_write_lock(&table->matcher_replace_rwlk);
14992 : 0 : ret = mlx5dr_matcher_resize_set_target
14993 : : (table->matcher_info[selector].matcher, matcher);
14994 [ # # ]: 0 : if (ret) {
14995 : : rte_rwlock_write_unlock(&table->matcher_replace_rwlk);
14996 : 0 : ret = rte_flow_error_set(error, rte_errno,
14997 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14998 : : table, "failed to initiate matcher swap");
14999 : 0 : goto error;
15000 : : }
15001 : 0 : table->cfg.attr.nb_flows = nb_flows;
15002 : 0 : table->matcher_info[other_selector].matcher = matcher;
15003 : 0 : table->matcher_info[other_selector].jump = jump;
15004 : 0 : table->matcher_selector = other_selector;
15005 : 0 : rte_atomic_store_explicit(&table->matcher_info[other_selector].refcnt,
15006 : : 0, rte_memory_order_relaxed);
15007 : : rte_rwlock_write_unlock(&table->matcher_replace_rwlk);
15008 : 0 : return 0;
15009 : 0 : error:
15010 [ # # ]: 0 : if (segment)
15011 : 0 : mlx5_destroy_multi_pattern_segment(segment);
15012 [ # # ]: 0 : if (jump)
15013 : 0 : mlx5dr_action_destroy(jump);
15014 [ # # ]: 0 : if (matcher) {
15015 : 0 : ret = mlx5dr_matcher_destroy(matcher);
15016 : 0 : return rte_flow_error_set(error, rte_errno,
15017 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15018 : : table, "failed to destroy new matcher");
15019 : : }
15020 : : return ret;
15021 : : }
15022 : :
15023 : : static int
15024 : 0 : flow_hw_table_resize_complete(__rte_unused struct rte_eth_dev *dev,
15025 : : struct rte_flow_template_table *table,
15026 : : struct rte_flow_error *error)
15027 : : {
15028 : : int ret;
15029 : 0 : uint32_t selector = table->matcher_selector;
15030 : 0 : uint32_t other_selector = (selector + 1) & 1;
15031 : : struct mlx5_matcher_info *matcher_info = &table->matcher_info[other_selector];
15032 : : uint32_t matcher_refcnt;
15033 : :
15034 [ # # ]: 0 : if (!rte_flow_template_table_resizable(dev->data->port_id, &table->cfg.attr))
15035 : 0 : return rte_flow_error_set(error, EINVAL,
15036 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15037 : : table, "no resizable attribute");
15038 : 0 : matcher_refcnt = rte_atomic_load_explicit(&matcher_info->refcnt,
15039 : : rte_memory_order_relaxed);
15040 [ # # # # ]: 0 : if (!matcher_info->matcher || matcher_refcnt)
15041 : 0 : return rte_flow_error_set(error, EBUSY,
15042 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15043 : : table, "cannot complete table resize");
15044 [ # # ]: 0 : if (matcher_info->jump)
15045 : 0 : mlx5dr_action_destroy(matcher_info->jump);
15046 : 0 : ret = mlx5dr_matcher_destroy(matcher_info->matcher);
15047 [ # # ]: 0 : if (ret)
15048 : 0 : return rte_flow_error_set(error, rte_errno,
15049 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15050 : : table, "failed to destroy retired matcher");
15051 : 0 : matcher_info->matcher = NULL;
15052 : 0 : return 0;
15053 : : }
15054 : :
15055 : : static int
15056 : 0 : flow_hw_update_resized(struct rte_eth_dev *dev, uint32_t queue,
15057 : : const struct rte_flow_op_attr *attr,
15058 : : struct rte_flow *flow, void *user_data,
15059 : : struct rte_flow_error *error)
15060 : : {
15061 : : int ret;
15062 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
15063 : : struct rte_flow_hw *hw_flow = (struct rte_flow_hw *)flow;
15064 : 0 : struct rte_flow_template_table *table = hw_flow->table;
15065 : 0 : struct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(dev->data->port_id, hw_flow);
15066 : 0 : uint32_t table_selector = table->matcher_selector;
15067 : 0 : uint32_t rule_selector = aux->matcher_selector;
15068 : : uint32_t other_selector;
15069 : : struct mlx5dr_matcher *other_matcher;
15070 : 0 : struct mlx5dr_rule_attr rule_attr = {
15071 : : .queue_id = queue,
15072 : 0 : .burst = attr->postpone,
15073 : : };
15074 : :
15075 : : MLX5_ASSERT(hw_flow->flags & MLX5_FLOW_HW_FLOW_FLAG_MATCHER_SELECTOR);
15076 : : /**
15077 : : * mlx5dr_matcher_resize_rule_move() accepts original table matcher -
15078 : : * the one that was used BEFORE table resize.
15079 : : * Since the function is called AFTER table resize,
15080 : : * `table->matcher_selector` always points to the new matcher and
15081 : : * `aux->matcher_selector` points to a matcher used to create the flow.
15082 : : */
15083 : : other_selector = rule_selector == table_selector ?
15084 [ # # ]: 0 : (rule_selector + 1) & 1 : rule_selector;
15085 : 0 : other_matcher = table->matcher_info[other_selector].matcher;
15086 [ # # ]: 0 : if (!other_matcher)
15087 : 0 : return rte_flow_error_set(error, EINVAL,
15088 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
15089 : : "no active table resize");
15090 : 0 : hw_flow->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_MOVE;
15091 : 0 : hw_flow->user_data = user_data;
15092 : 0 : rule_attr.user_data = hw_flow;
15093 [ # # ]: 0 : if (rule_selector == table_selector) {
15094 : 0 : struct rte_ring *ring = !attr->postpone ?
15095 [ # # ]: 0 : priv->hw_q[queue].flow_transfer_completed :
15096 : 0 : priv->hw_q[queue].flow_transfer_pending;
15097 : 0 : rte_ring_enqueue(ring, hw_flow);
15098 : : flow_hw_q_inc_flow_ops(priv, queue);
15099 : 0 : return 0;
15100 : : }
15101 : 0 : ret = mlx5dr_matcher_resize_rule_move(other_matcher,
15102 : 0 : (struct mlx5dr_rule *)hw_flow->rule,
15103 : : &rule_attr);
15104 [ # # ]: 0 : if (ret) {
15105 : 0 : return rte_flow_error_set(error, rte_errno,
15106 : : RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
15107 : : "flow transfer failed");
15108 : : }
15109 : : flow_hw_q_inc_flow_ops(priv, queue);
15110 : 0 : return 0;
15111 : : }
15112 : :
15113 : : const struct mlx5_flow_driver_ops mlx5_flow_hw_drv_ops = {
15114 : : .list_create = flow_hw_list_create,
15115 : : .list_destroy = flow_hw_list_destroy,
15116 : : .validate = flow_dv_validate,
15117 : : .info_get = flow_hw_info_get,
15118 : : .configure = flow_hw_configure,
15119 : : .pattern_validate = flow_hw_pattern_validate,
15120 : : .pattern_template_create = flow_hw_pattern_template_create,
15121 : : .pattern_template_destroy = flow_hw_pattern_template_destroy,
15122 : : .actions_validate = flow_hw_actions_validate,
15123 : : .actions_template_create = flow_hw_actions_template_create,
15124 : : .actions_template_destroy = flow_hw_actions_template_destroy,
15125 : : .template_table_create = flow_hw_template_table_create,
15126 : : .template_table_destroy = flow_hw_table_destroy,
15127 : : .table_resize = flow_hw_table_resize,
15128 : : .group_set_miss_actions = flow_hw_group_set_miss_actions,
15129 : : .async_flow_create = flow_hw_async_flow_create,
15130 : : .async_flow_create_by_index = flow_hw_async_flow_create_by_index,
15131 : : .async_flow_update = flow_hw_async_flow_update,
15132 : : .async_flow_destroy = flow_hw_async_flow_destroy,
15133 : : .flow_update_resized = flow_hw_update_resized,
15134 : : .table_resize_complete = flow_hw_table_resize_complete,
15135 : : .pull = flow_hw_pull,
15136 : : .push = flow_hw_push,
15137 : : .async_action_create = flow_hw_action_handle_create,
15138 : : .async_action_destroy = flow_hw_action_handle_destroy,
15139 : : .async_action_update = flow_hw_action_handle_update,
15140 : : .async_action_query_update = flow_hw_async_action_handle_query_update,
15141 : : .async_action_query = flow_hw_action_handle_query,
15142 : : .action_validate = flow_hw_action_validate,
15143 : : .action_create = flow_hw_action_create,
15144 : : .action_destroy = flow_hw_action_destroy,
15145 : : .action_update = flow_hw_action_update,
15146 : : .action_query = flow_hw_action_query,
15147 : : .action_query_update = flow_hw_action_query_update,
15148 : : .action_list_handle_create = flow_hw_action_list_handle_create,
15149 : : .action_list_handle_destroy = flow_hw_action_list_handle_destroy,
15150 : : .action_list_handle_query_update =
15151 : : flow_hw_action_list_handle_query_update,
15152 : : .async_action_list_handle_create =
15153 : : flow_hw_async_action_list_handle_create,
15154 : : .async_action_list_handle_destroy =
15155 : : flow_hw_async_action_list_handle_destroy,
15156 : : .async_action_list_handle_query_update =
15157 : : flow_hw_async_action_list_handle_query_update,
15158 : : .query = flow_hw_query,
15159 : : .get_aged_flows = flow_hw_get_aged_flows,
15160 : : .get_q_aged_flows = flow_hw_get_q_aged_flows,
15161 : : .item_create = flow_dv_item_create,
15162 : : .item_release = flow_dv_item_release,
15163 : : .flow_calc_table_hash = flow_hw_calc_table_hash,
15164 : : .flow_calc_encap_hash = flow_hw_calc_encap_hash,
15165 : : };
15166 : :
15167 : : /**
15168 : : * Creates a control flow using flow template API on @p proxy_dev device,
15169 : : * on behalf of @p owner_dev device.
15170 : : *
15171 : : * This function uses locks internally to synchronize access to the
15172 : : * flow queue.
15173 : : *
15174 : : * Created flow is stored in private list associated with @p proxy_dev device.
15175 : : *
15176 : : * @param owner_dev
15177 : : * Pointer to Ethernet device on behalf of which flow is created.
15178 : : * @param proxy_dev
15179 : : * Pointer to Ethernet device on which flow is created.
15180 : : * @param table
15181 : : * Pointer to flow table.
15182 : : * @param items
15183 : : * Pointer to flow rule items.
15184 : : * @param item_template_idx
15185 : : * Index of an item template associated with @p table.
15186 : : * @param actions
15187 : : * Pointer to flow rule actions.
15188 : : * @param action_template_idx
15189 : : * Index of an action template associated with @p table.
15190 : : * @param info
15191 : : * Additional info about control flow rule.
15192 : : * @param external
15193 : : * External ctrl flow.
15194 : : *
15195 : : * @return
15196 : : * 0 on success, negative errno value otherwise and rte_errno set.
15197 : : */
15198 : : static __rte_unused int
15199 : 0 : flow_hw_create_ctrl_flow(struct rte_eth_dev *owner_dev,
15200 : : struct rte_eth_dev *proxy_dev,
15201 : : struct rte_flow_template_table *table,
15202 : : struct rte_flow_item items[],
15203 : : uint8_t item_template_idx,
15204 : : struct rte_flow_action actions[],
15205 : : uint8_t action_template_idx,
15206 : : struct mlx5_ctrl_flow_info *info,
15207 : : bool external)
15208 : : {
15209 : 0 : struct mlx5_priv *priv = proxy_dev->data->dev_private;
15210 : 0 : uint32_t queue = CTRL_QUEUE_ID(priv);
15211 : 0 : struct rte_flow_op_attr op_attr = {
15212 : : .postpone = 0,
15213 : : };
15214 : : struct rte_flow *flow = NULL;
15215 : : struct mlx5_ctrl_flow_entry *entry = NULL;
15216 : : int ret;
15217 : :
15218 : 0 : rte_spinlock_lock(&priv->hw_ctrl_lock);
15219 : 0 : entry = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_SYS, sizeof(*entry),
15220 : : 0, SOCKET_ID_ANY);
15221 [ # # ]: 0 : if (!entry) {
15222 : 0 : DRV_LOG(ERR, "port %u not enough memory to create control flows",
15223 : : proxy_dev->data->port_id);
15224 : 0 : rte_errno = ENOMEM;
15225 : : ret = -rte_errno;
15226 : 0 : goto error;
15227 : : }
15228 : 0 : flow = flow_hw_async_flow_create(proxy_dev, queue, &op_attr, table,
15229 : : items, item_template_idx,
15230 : : actions, action_template_idx,
15231 : : NULL, NULL);
15232 [ # # ]: 0 : if (!flow) {
15233 : 0 : DRV_LOG(ERR, "port %u failed to enqueue create control"
15234 : : " flow operation", proxy_dev->data->port_id);
15235 : 0 : ret = -rte_errno;
15236 : 0 : goto error;
15237 : : }
15238 : 0 : ret = __flow_hw_pull_comp(proxy_dev, queue, NULL);
15239 [ # # ]: 0 : if (ret) {
15240 : 0 : DRV_LOG(ERR, "port %u failed to insert control flow",
15241 : : proxy_dev->data->port_id);
15242 : 0 : rte_errno = EINVAL;
15243 : : ret = -rte_errno;
15244 : 0 : goto error;
15245 : : }
15246 : 0 : entry->owner_dev = owner_dev;
15247 : 0 : entry->flow = flow;
15248 [ # # ]: 0 : if (info)
15249 : 0 : entry->info = *info;
15250 : : else
15251 : 0 : entry->info.type = MLX5_CTRL_FLOW_TYPE_GENERAL;
15252 [ # # ]: 0 : if (external)
15253 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->hw_ext_ctrl_flows, entry, next);
15254 : : else
15255 [ # # ]: 0 : LIST_INSERT_HEAD(&priv->hw_ctrl_flows, entry, next);
15256 : : rte_spinlock_unlock(&priv->hw_ctrl_lock);
15257 : 0 : return 0;
15258 : 0 : error:
15259 [ # # ]: 0 : if (entry)
15260 : 0 : mlx5_free(entry);
15261 : : rte_spinlock_unlock(&priv->hw_ctrl_lock);
15262 : 0 : return ret;
15263 : : }
15264 : :
15265 : : /**
15266 : : * Destroys a control flow @p flow using flow template API on @p dev device.
15267 : : *
15268 : : * This function uses locks internally to synchronize access to the
15269 : : * flow queue.
15270 : : *
15271 : : * If the @p flow is stored on any private list/pool, then caller must free up
15272 : : * the relevant resources.
15273 : : *
15274 : : * @param dev
15275 : : * Pointer to Ethernet device.
15276 : : * @param flow
15277 : : * Pointer to flow rule.
15278 : : *
15279 : : * @return
15280 : : * 0 on success, non-zero value otherwise.
15281 : : */
15282 : : static int
15283 : 0 : flow_hw_destroy_ctrl_flow(struct rte_eth_dev *dev, struct rte_flow *flow)
15284 : : {
15285 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
15286 : 0 : uint32_t queue = CTRL_QUEUE_ID(priv);
15287 : 0 : struct rte_flow_op_attr op_attr = {
15288 : : .postpone = 0,
15289 : : };
15290 : : int ret;
15291 : :
15292 : 0 : rte_spinlock_lock(&priv->hw_ctrl_lock);
15293 : 0 : ret = flow_hw_async_flow_destroy(dev, queue, &op_attr, flow, NULL, NULL);
15294 [ # # ]: 0 : if (ret) {
15295 : 0 : DRV_LOG(ERR, "port %u failed to enqueue destroy control"
15296 : : " flow operation", dev->data->port_id);
15297 : 0 : goto exit;
15298 : : }
15299 : 0 : ret = __flow_hw_pull_comp(dev, queue, NULL);
15300 [ # # ]: 0 : if (ret) {
15301 : 0 : DRV_LOG(ERR, "port %u failed to destroy control flow",
15302 : : dev->data->port_id);
15303 : 0 : rte_errno = EINVAL;
15304 : : ret = -rte_errno;
15305 : 0 : goto exit;
15306 : : }
15307 : 0 : exit:
15308 : : rte_spinlock_unlock(&priv->hw_ctrl_lock);
15309 : 0 : return ret;
15310 : : }
15311 : :
15312 : : /**
15313 : : * Destroys control flows created on behalf of @p owner device on @p dev device.
15314 : : *
15315 : : * @param dev
15316 : : * Pointer to Ethernet device on which control flows were created.
15317 : : * @param owner
15318 : : * Pointer to Ethernet device owning control flows.
15319 : : *
15320 : : * @return
15321 : : * 0 on success, otherwise negative error code is returned and
15322 : : * rte_errno is set.
15323 : : */
15324 : : static int
15325 : 0 : flow_hw_flush_ctrl_flows_owned_by(struct rte_eth_dev *dev, struct rte_eth_dev *owner)
15326 : : {
15327 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
15328 : : struct mlx5_ctrl_flow_entry *cf;
15329 : : struct mlx5_ctrl_flow_entry *cf_next;
15330 : : int ret;
15331 : :
15332 : 0 : cf = LIST_FIRST(&priv->hw_ctrl_flows);
15333 [ # # ]: 0 : while (cf != NULL) {
15334 : 0 : cf_next = LIST_NEXT(cf, next);
15335 [ # # ]: 0 : if (cf->owner_dev == owner) {
15336 : 0 : ret = flow_hw_destroy_ctrl_flow(dev, cf->flow);
15337 [ # # ]: 0 : if (ret) {
15338 : 0 : rte_errno = ret;
15339 : 0 : return -ret;
15340 : : }
15341 [ # # ]: 0 : LIST_REMOVE(cf, next);
15342 : 0 : mlx5_free(cf);
15343 : : }
15344 : : cf = cf_next;
15345 : : }
15346 : : return 0;
15347 : : }
15348 : :
15349 : : /**
15350 : : * Destroys control flows created for @p owner_dev device.
15351 : : *
15352 : : * @param owner_dev
15353 : : * Pointer to Ethernet device owning control flows.
15354 : : *
15355 : : * @return
15356 : : * 0 on success, otherwise negative error code is returned and
15357 : : * rte_errno is set.
15358 : : */
15359 : : int
15360 : 0 : mlx5_flow_hw_flush_ctrl_flows(struct rte_eth_dev *owner_dev)
15361 : : {
15362 : 0 : struct mlx5_priv *owner_priv = owner_dev->data->dev_private;
15363 : : struct rte_eth_dev *proxy_dev;
15364 : 0 : uint16_t owner_port_id = owner_dev->data->port_id;
15365 : 0 : uint16_t proxy_port_id = owner_dev->data->port_id;
15366 : : int ret;
15367 : :
15368 : : /* Flush all flows created by this port for itself. */
15369 : 0 : ret = flow_hw_flush_ctrl_flows_owned_by(owner_dev, owner_dev);
15370 [ # # ]: 0 : if (ret)
15371 : : return ret;
15372 : : /* Flush all flows created for this port on proxy port. */
15373 [ # # ]: 0 : if (owner_priv->sh->config.dv_esw_en) {
15374 : 0 : ret = rte_flow_pick_transfer_proxy(owner_port_id, &proxy_port_id, NULL);
15375 [ # # ]: 0 : if (ret == -ENODEV) {
15376 : 0 : DRV_LOG(DEBUG, "Unable to find transfer proxy port for port %u. It was "
15377 : : "probably closed. Control flows were cleared.",
15378 : : owner_port_id);
15379 : 0 : rte_errno = 0;
15380 : 0 : return 0;
15381 [ # # ]: 0 : } else if (ret) {
15382 : 0 : DRV_LOG(ERR, "Unable to find proxy port for port %u (ret = %d)",
15383 : : owner_port_id, ret);
15384 : 0 : return ret;
15385 : : }
15386 : 0 : proxy_dev = &rte_eth_devices[proxy_port_id];
15387 : : } else {
15388 : : proxy_dev = owner_dev;
15389 : : }
15390 : 0 : return flow_hw_flush_ctrl_flows_owned_by(proxy_dev, owner_dev);
15391 : : }
15392 : :
15393 : : /**
15394 : : * Destroys all control flows created on @p dev device.
15395 : : *
15396 : : * @param owner_dev
15397 : : * Pointer to Ethernet device.
15398 : : *
15399 : : * @return
15400 : : * 0 on success, otherwise negative error code is returned and
15401 : : * rte_errno is set.
15402 : : */
15403 : : static int
15404 : 0 : flow_hw_flush_all_ctrl_flows(struct rte_eth_dev *dev)
15405 : : {
15406 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
15407 : : struct mlx5_ctrl_flow_entry *cf;
15408 : : struct mlx5_ctrl_flow_entry *cf_next;
15409 : : int ret;
15410 : :
15411 : 0 : cf = LIST_FIRST(&priv->hw_ctrl_flows);
15412 [ # # ]: 0 : while (cf != NULL) {
15413 : 0 : cf_next = LIST_NEXT(cf, next);
15414 : 0 : ret = flow_hw_destroy_ctrl_flow(dev, cf->flow);
15415 [ # # ]: 0 : if (ret) {
15416 : 0 : rte_errno = ret;
15417 : 0 : return -ret;
15418 : : }
15419 [ # # ]: 0 : LIST_REMOVE(cf, next);
15420 : 0 : mlx5_free(cf);
15421 : : cf = cf_next;
15422 : : }
15423 : 0 : cf = LIST_FIRST(&priv->hw_ext_ctrl_flows);
15424 [ # # ]: 0 : while (cf != NULL) {
15425 : 0 : cf_next = LIST_NEXT(cf, next);
15426 : 0 : ret = flow_hw_destroy_ctrl_flow(dev, cf->flow);
15427 [ # # ]: 0 : if (ret) {
15428 : 0 : rte_errno = ret;
15429 : 0 : return -ret;
15430 : : }
15431 [ # # ]: 0 : LIST_REMOVE(cf, next);
15432 : 0 : mlx5_free(cf);
15433 : : cf = cf_next;
15434 : : }
15435 : : return 0;
15436 : : }
15437 : :
15438 : : int
15439 : 0 : mlx5_flow_hw_esw_create_sq_miss_flow(struct rte_eth_dev *dev, uint32_t sqn, bool external)
15440 : : {
15441 : 0 : uint16_t port_id = dev->data->port_id;
15442 : 0 : struct rte_flow_item_ethdev esw_mgr_spec = {
15443 : : .port_id = MLX5_REPRESENTED_PORT_ESW_MGR,
15444 : : };
15445 : 0 : struct rte_flow_item_ethdev esw_mgr_mask = {
15446 : : .port_id = MLX5_REPRESENTED_PORT_ESW_MGR,
15447 : : };
15448 : 0 : struct rte_flow_item_tag reg_c0_spec = {
15449 : : .index = (uint8_t)REG_C_0,
15450 : : .data = flow_hw_esw_mgr_regc_marker(dev),
15451 : : };
15452 : 0 : struct rte_flow_item_tag reg_c0_mask = {
15453 : : .index = 0xff,
15454 : : .data = flow_hw_esw_mgr_regc_marker_mask(dev),
15455 : : };
15456 : 0 : struct mlx5_rte_flow_item_sq sq_spec = {
15457 : : .queue = sqn,
15458 : : };
15459 : 0 : struct rte_flow_action_ethdev port = {
15460 : : .port_id = port_id,
15461 : : };
15462 : 0 : struct rte_flow_item items[3] = { { 0 } };
15463 : 0 : struct rte_flow_action actions[3] = { { 0 } };
15464 : 0 : struct mlx5_ctrl_flow_info flow_info = {
15465 : : .type = MLX5_CTRL_FLOW_TYPE_SQ_MISS_ROOT,
15466 : : .esw_mgr_sq = sqn,
15467 : : };
15468 : : struct rte_eth_dev *proxy_dev;
15469 : : struct mlx5_priv *proxy_priv;
15470 : 0 : uint16_t proxy_port_id = dev->data->port_id;
15471 : : int ret;
15472 : :
15473 : 0 : ret = rte_flow_pick_transfer_proxy(port_id, &proxy_port_id, NULL);
15474 [ # # ]: 0 : if (ret) {
15475 : 0 : DRV_LOG(ERR, "Unable to pick transfer proxy port for port %u. Transfer proxy "
15476 : : "port must be present to create default SQ miss flows.",
15477 : : port_id);
15478 : 0 : return ret;
15479 : : }
15480 : 0 : proxy_dev = &rte_eth_devices[proxy_port_id];
15481 : 0 : proxy_priv = proxy_dev->data->dev_private;
15482 [ # # ]: 0 : if (!proxy_priv->dr_ctx) {
15483 : 0 : DRV_LOG(DEBUG, "Transfer proxy port (port %u) of port %u must be configured "
15484 : : "for HWS to create default SQ miss flows. Default flows will "
15485 : : "not be created.",
15486 : : proxy_port_id, port_id);
15487 : 0 : return 0;
15488 : : }
15489 [ # # ]: 0 : if (!proxy_priv->hw_ctrl_fdb ||
15490 [ # # ]: 0 : !proxy_priv->hw_ctrl_fdb->hw_esw_sq_miss_root_tbl ||
15491 [ # # ]: 0 : !proxy_priv->hw_ctrl_fdb->hw_esw_sq_miss_tbl) {
15492 : 0 : DRV_LOG(ERR, "Transfer proxy port (port %u) of port %u was configured, but "
15493 : : "default flow tables were not created.",
15494 : : proxy_port_id, port_id);
15495 : 0 : rte_errno = ENOMEM;
15496 : 0 : return -rte_errno;
15497 : : }
15498 : : /*
15499 : : * Create a root SQ miss flow rule - match E-Switch Manager and SQ,
15500 : : * and jump to group 1.
15501 : : */
15502 : 0 : items[0] = (struct rte_flow_item){
15503 : : .type = RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT,
15504 : : .spec = &esw_mgr_spec,
15505 : : .mask = &esw_mgr_mask,
15506 : : };
15507 : 0 : items[1] = (struct rte_flow_item){
15508 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_SQ,
15509 : : .spec = &sq_spec,
15510 : : };
15511 : 0 : items[2] = (struct rte_flow_item){
15512 : : .type = RTE_FLOW_ITEM_TYPE_END,
15513 : : };
15514 : 0 : actions[0] = (struct rte_flow_action){
15515 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
15516 : : };
15517 : 0 : actions[1] = (struct rte_flow_action){
15518 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
15519 : : };
15520 : 0 : actions[2] = (struct rte_flow_action) {
15521 : : .type = RTE_FLOW_ACTION_TYPE_END,
15522 : : };
15523 : 0 : ret = flow_hw_create_ctrl_flow(dev, proxy_dev,
15524 : : proxy_priv->hw_ctrl_fdb->hw_esw_sq_miss_root_tbl,
15525 : : items, 0, actions, 0, &flow_info, external);
15526 [ # # ]: 0 : if (ret) {
15527 : 0 : DRV_LOG(ERR, "Port %u failed to create root SQ miss flow rule for SQ %u, ret %d",
15528 : : port_id, sqn, ret);
15529 : 0 : return ret;
15530 : : }
15531 : : /*
15532 : : * Create a non-root SQ miss flow rule - match REG_C_0 marker and SQ,
15533 : : * and forward to port.
15534 : : */
15535 : 0 : items[0] = (struct rte_flow_item){
15536 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_TAG,
15537 : : .spec = ®_c0_spec,
15538 : : .mask = ®_c0_mask,
15539 : : };
15540 : 0 : items[1] = (struct rte_flow_item){
15541 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_SQ,
15542 : : .spec = &sq_spec,
15543 : : };
15544 : 0 : items[2] = (struct rte_flow_item){
15545 : : .type = RTE_FLOW_ITEM_TYPE_END,
15546 : : };
15547 : 0 : actions[0] = (struct rte_flow_action){
15548 : : .type = RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT,
15549 : : .conf = &port,
15550 : : };
15551 : 0 : actions[1] = (struct rte_flow_action){
15552 : : .type = RTE_FLOW_ACTION_TYPE_END,
15553 : : };
15554 : 0 : flow_info.type = MLX5_CTRL_FLOW_TYPE_SQ_MISS;
15555 : 0 : ret = flow_hw_create_ctrl_flow(dev, proxy_dev,
15556 : 0 : proxy_priv->hw_ctrl_fdb->hw_esw_sq_miss_tbl,
15557 : : items, 0, actions, 0, &flow_info, external);
15558 [ # # ]: 0 : if (ret) {
15559 : 0 : DRV_LOG(ERR, "Port %u failed to create HWS SQ miss flow rule for SQ %u, ret %d",
15560 : : port_id, sqn, ret);
15561 : 0 : return ret;
15562 : : }
15563 : : return 0;
15564 : : }
15565 : :
15566 : : static bool
15567 : : flow_hw_is_matching_sq_miss_flow(struct mlx5_ctrl_flow_entry *cf,
15568 : : struct rte_eth_dev *dev,
15569 : : uint32_t sqn)
15570 : : {
15571 : 0 : if (cf->owner_dev != dev)
15572 : : return false;
15573 [ # # # # ]: 0 : if (cf->info.type == MLX5_CTRL_FLOW_TYPE_SQ_MISS_ROOT && cf->info.esw_mgr_sq == sqn)
15574 : : return true;
15575 [ # # # # ]: 0 : if (cf->info.type == MLX5_CTRL_FLOW_TYPE_SQ_MISS && cf->info.esw_mgr_sq == sqn)
15576 : : return true;
15577 : : return false;
15578 : : }
15579 : :
15580 : : int
15581 : 0 : mlx5_flow_hw_esw_destroy_sq_miss_flow(struct rte_eth_dev *dev, uint32_t sqn)
15582 : : {
15583 : 0 : uint16_t port_id = dev->data->port_id;
15584 : 0 : uint16_t proxy_port_id = dev->data->port_id;
15585 : : struct rte_eth_dev *proxy_dev;
15586 : : struct mlx5_priv *proxy_priv;
15587 : : struct mlx5_ctrl_flow_entry *cf;
15588 : : struct mlx5_ctrl_flow_entry *cf_next;
15589 : : int ret;
15590 : :
15591 : 0 : ret = rte_flow_pick_transfer_proxy(port_id, &proxy_port_id, NULL);
15592 [ # # ]: 0 : if (ret) {
15593 : 0 : DRV_LOG(ERR, "Unable to pick transfer proxy port for port %u. Transfer proxy "
15594 : : "port must be present for default SQ miss flow rules to exist.",
15595 : : port_id);
15596 : 0 : return ret;
15597 : : }
15598 : 0 : proxy_dev = &rte_eth_devices[proxy_port_id];
15599 : 0 : proxy_priv = proxy_dev->data->dev_private;
15600 : : /* FDB default flow rules must be enabled. */
15601 : : MLX5_ASSERT(proxy_priv->sh->config.fdb_def_rule);
15602 [ # # ]: 0 : if (!proxy_priv->dr_ctx)
15603 : : return 0;
15604 [ # # ]: 0 : if (!proxy_priv->hw_ctrl_fdb ||
15605 [ # # ]: 0 : !proxy_priv->hw_ctrl_fdb->hw_esw_sq_miss_root_tbl ||
15606 [ # # ]: 0 : !proxy_priv->hw_ctrl_fdb->hw_esw_sq_miss_tbl)
15607 : : return 0;
15608 : 0 : cf = LIST_FIRST(&proxy_priv->hw_ctrl_flows);
15609 [ # # ]: 0 : while (cf != NULL) {
15610 [ # # ]: 0 : cf_next = LIST_NEXT(cf, next);
15611 : : if (flow_hw_is_matching_sq_miss_flow(cf, dev, sqn)) {
15612 : 0 : claim_zero(flow_hw_destroy_ctrl_flow(proxy_dev, cf->flow));
15613 [ # # ]: 0 : LIST_REMOVE(cf, next);
15614 : 0 : mlx5_free(cf);
15615 : : }
15616 : : cf = cf_next;
15617 : : }
15618 : : return 0;
15619 : : }
15620 : :
15621 : : int
15622 : 0 : mlx5_flow_hw_esw_create_default_jump_flow(struct rte_eth_dev *dev)
15623 : : {
15624 : 0 : uint16_t port_id = dev->data->port_id;
15625 : 0 : struct rte_flow_item_ethdev port_spec = {
15626 : : .port_id = port_id,
15627 : : };
15628 : 0 : struct rte_flow_item items[] = {
15629 : : {
15630 : : .type = RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT,
15631 : : .spec = &port_spec,
15632 : : },
15633 : : {
15634 : : .type = RTE_FLOW_ITEM_TYPE_END,
15635 : : },
15636 : : };
15637 : 0 : struct rte_flow_action_jump jump = {
15638 : : .group = 1,
15639 : : };
15640 : 0 : struct rte_flow_action actions[] = {
15641 : : {
15642 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
15643 : : .conf = &jump,
15644 : : },
15645 : : {
15646 : : .type = RTE_FLOW_ACTION_TYPE_END,
15647 : : }
15648 : : };
15649 : 0 : struct mlx5_ctrl_flow_info flow_info = {
15650 : : .type = MLX5_CTRL_FLOW_TYPE_DEFAULT_JUMP,
15651 : : };
15652 : : struct rte_eth_dev *proxy_dev;
15653 : : struct mlx5_priv *proxy_priv;
15654 : 0 : uint16_t proxy_port_id = dev->data->port_id;
15655 : : int ret;
15656 : :
15657 : 0 : ret = rte_flow_pick_transfer_proxy(port_id, &proxy_port_id, NULL);
15658 [ # # ]: 0 : if (ret) {
15659 : 0 : DRV_LOG(ERR, "Unable to pick transfer proxy port for port %u. Transfer proxy "
15660 : : "port must be present to create default FDB jump rule.",
15661 : : port_id);
15662 : 0 : return ret;
15663 : : }
15664 : 0 : proxy_dev = &rte_eth_devices[proxy_port_id];
15665 : 0 : proxy_priv = proxy_dev->data->dev_private;
15666 : : /* FDB default flow rules must be enabled. */
15667 : : MLX5_ASSERT(proxy_priv->sh->config.fdb_def_rule);
15668 [ # # ]: 0 : if (!proxy_priv->dr_ctx) {
15669 : 0 : DRV_LOG(DEBUG, "Transfer proxy port (port %u) of port %u must be configured "
15670 : : "for HWS to create default FDB jump rule. Default rule will "
15671 : : "not be created.",
15672 : : proxy_port_id, port_id);
15673 : 0 : return 0;
15674 : : }
15675 [ # # # # ]: 0 : if (!proxy_priv->hw_ctrl_fdb || !proxy_priv->hw_ctrl_fdb->hw_esw_zero_tbl) {
15676 : 0 : DRV_LOG(ERR, "Transfer proxy port (port %u) of port %u was configured, but "
15677 : : "default flow tables were not created.",
15678 : : proxy_port_id, port_id);
15679 : 0 : rte_errno = EINVAL;
15680 : 0 : return -rte_errno;
15681 : : }
15682 : 0 : return flow_hw_create_ctrl_flow(dev, proxy_dev,
15683 : : proxy_priv->hw_ctrl_fdb->hw_esw_zero_tbl,
15684 : : items, 0, actions, 0, &flow_info, false);
15685 : : }
15686 : :
15687 : : int
15688 : 0 : mlx5_flow_hw_create_tx_default_mreg_copy_flow(struct rte_eth_dev *dev)
15689 : : {
15690 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
15691 : 0 : struct rte_flow_item_eth promisc = {
15692 : : .hdr.dst_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
15693 : : .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
15694 : : .hdr.ether_type = 0,
15695 : : };
15696 : 0 : struct rte_flow_item eth_all[] = {
15697 : : [0] = {
15698 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
15699 : : .spec = &promisc,
15700 : : .mask = &promisc,
15701 : : },
15702 : : [1] = {
15703 : : .type = RTE_FLOW_ITEM_TYPE_END,
15704 : : },
15705 : : };
15706 : 0 : struct rte_flow_action_modify_field mreg_action = {
15707 : : .operation = RTE_FLOW_MODIFY_SET,
15708 : : .dst = {
15709 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
15710 : : .tag_index = REG_C_1,
15711 : : },
15712 : : .src = {
15713 : : .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,
15714 : : .tag_index = REG_A,
15715 : : },
15716 : : .width = 32,
15717 : : };
15718 : 0 : struct rte_flow_action copy_reg_action[] = {
15719 : : [0] = {
15720 : : .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,
15721 : : .conf = &mreg_action,
15722 : : },
15723 : : [1] = {
15724 : : .type = RTE_FLOW_ACTION_TYPE_JUMP,
15725 : : },
15726 : : [2] = {
15727 : : .type = RTE_FLOW_ACTION_TYPE_END,
15728 : : },
15729 : : };
15730 : 0 : struct mlx5_ctrl_flow_info flow_info = {
15731 : : .type = MLX5_CTRL_FLOW_TYPE_TX_META_COPY,
15732 : : };
15733 : :
15734 : : MLX5_ASSERT(priv->master);
15735 [ # # ]: 0 : if (!priv->dr_ctx ||
15736 [ # # ]: 0 : !priv->hw_ctrl_fdb ||
15737 [ # # ]: 0 : !priv->hw_ctrl_fdb->hw_tx_meta_cpy_tbl)
15738 : : return 0;
15739 : 0 : return flow_hw_create_ctrl_flow(dev, dev,
15740 : : priv->hw_ctrl_fdb->hw_tx_meta_cpy_tbl,
15741 : : eth_all, 0, copy_reg_action, 0, &flow_info, false);
15742 : : }
15743 : :
15744 : : int
15745 : 0 : mlx5_flow_hw_tx_repr_matching_flow(struct rte_eth_dev *dev, uint32_t sqn, bool external)
15746 : : {
15747 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
15748 : 0 : struct mlx5_rte_flow_item_sq sq_spec = {
15749 : : .queue = sqn,
15750 : : };
15751 : 0 : struct rte_flow_item items[] = {
15752 : : {
15753 : : .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_SQ,
15754 : : .spec = &sq_spec,
15755 : : },
15756 : : {
15757 : : .type = RTE_FLOW_ITEM_TYPE_END,
15758 : : },
15759 : : };
15760 : : /*
15761 : : * Allocate actions array suitable for all cases - extended metadata enabled or not.
15762 : : * With extended metadata there will be an additional MODIFY_FIELD action before JUMP.
15763 : : */
15764 : 0 : struct rte_flow_action actions[] = {
15765 : : { .type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD },
15766 : : { .type = RTE_FLOW_ACTION_TYPE_JUMP },
15767 : : { .type = RTE_FLOW_ACTION_TYPE_END },
15768 : : { .type = RTE_FLOW_ACTION_TYPE_END },
15769 : : };
15770 : 0 : struct mlx5_ctrl_flow_info flow_info = {
15771 : : .type = MLX5_CTRL_FLOW_TYPE_TX_REPR_MATCH,
15772 : : .tx_repr_sq = sqn,
15773 : : };
15774 : :
15775 : : /* It is assumed that caller checked for representor matching. */
15776 : : MLX5_ASSERT(priv->sh->config.repr_matching);
15777 [ # # ]: 0 : if (!priv->dr_ctx) {
15778 : 0 : DRV_LOG(DEBUG, "Port %u must be configured for HWS, before creating "
15779 : : "default egress flow rules. Omitting creation.",
15780 : : dev->data->port_id);
15781 : 0 : return 0;
15782 : : }
15783 [ # # ]: 0 : if (!priv->hw_tx_repr_tagging_tbl) {
15784 : 0 : DRV_LOG(ERR, "Port %u is configured for HWS, but table for default "
15785 : : "egress flow rules does not exist.",
15786 : : dev->data->port_id);
15787 : 0 : rte_errno = EINVAL;
15788 : 0 : return -rte_errno;
15789 : : }
15790 : : /*
15791 : : * If extended metadata mode is enabled, then an additional MODIFY_FIELD action must be
15792 : : * placed before terminating JUMP action.
15793 : : */
15794 [ # # ]: 0 : if (priv->sh->config.dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS) {
15795 : 0 : actions[1].type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD;
15796 : 0 : actions[2].type = RTE_FLOW_ACTION_TYPE_JUMP;
15797 : : }
15798 : 0 : return flow_hw_create_ctrl_flow(dev, dev, priv->hw_tx_repr_tagging_tbl,
15799 : : items, 0, actions, 0, &flow_info, external);
15800 : : }
15801 : :
15802 : : int
15803 : 0 : mlx5_flow_hw_lacp_rx_flow(struct rte_eth_dev *dev)
15804 : : {
15805 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
15806 : 0 : struct rte_flow_item_eth lacp_item = {
15807 : : .type = RTE_BE16(RTE_ETHER_TYPE_SLOW),
15808 : : };
15809 : 0 : struct rte_flow_item eth_lacp[] = {
15810 : : [0] = {
15811 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
15812 : : .spec = &lacp_item,
15813 : : .mask = &lacp_item,
15814 : : },
15815 : : [1] = {
15816 : : .type = RTE_FLOW_ITEM_TYPE_END,
15817 : : },
15818 : : };
15819 : 0 : struct rte_flow_action miss_action[] = {
15820 : : [0] = {
15821 : : .type = (enum rte_flow_action_type)
15822 : : MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS,
15823 : : },
15824 : : [1] = {
15825 : : .type = RTE_FLOW_ACTION_TYPE_END,
15826 : : },
15827 : : };
15828 : 0 : struct mlx5_ctrl_flow_info flow_info = {
15829 : : .type = MLX5_CTRL_FLOW_TYPE_LACP_RX,
15830 : : };
15831 : :
15832 [ # # # # : 0 : if (!priv->dr_ctx || !priv->hw_ctrl_fdb || !priv->hw_ctrl_fdb->hw_lacp_rx_tbl)
# # ]
15833 : : return 0;
15834 : 0 : return flow_hw_create_ctrl_flow(dev, dev,
15835 : : priv->hw_ctrl_fdb->hw_lacp_rx_tbl,
15836 : : eth_lacp, 0, miss_action, 0, &flow_info, false);
15837 : : }
15838 : :
15839 : : static uint32_t
15840 : : __calc_pattern_flags(const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type)
15841 : : {
15842 : : switch (eth_pattern_type) {
15843 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL:
15844 : : return MLX5_CTRL_PROMISCUOUS;
15845 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL_MCAST:
15846 : : return MLX5_CTRL_ALL_MULTICAST;
15847 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST:
15848 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST_VLAN:
15849 : : return MLX5_CTRL_BROADCAST;
15850 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST:
15851 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST_VLAN:
15852 : : return MLX5_CTRL_IPV4_MULTICAST;
15853 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST:
15854 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST_VLAN:
15855 : : return MLX5_CTRL_IPV6_MULTICAST;
15856 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC:
15857 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN:
15858 : : return MLX5_CTRL_DMAC;
15859 : : default:
15860 : : /* Should not reach here. */
15861 : : MLX5_ASSERT(false);
15862 : : return 0;
15863 : : }
15864 : : }
15865 : :
15866 : : static uint32_t
15867 : : __calc_vlan_flags(const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type)
15868 : : {
15869 [ # # ]: 0 : switch (eth_pattern_type) {
15870 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST_VLAN:
15871 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST_VLAN:
15872 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST_VLAN:
15873 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN:
15874 : : return MLX5_CTRL_VLAN_FILTER;
15875 : 0 : default:
15876 : 0 : return 0;
15877 : : }
15878 : : }
15879 : :
15880 : : static bool
15881 [ # # ]: 0 : eth_pattern_type_is_requested(const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type,
15882 : : uint32_t flags)
15883 : : {
15884 : : uint32_t pattern_flags = __calc_pattern_flags(eth_pattern_type);
15885 : : uint32_t vlan_flags = __calc_vlan_flags(eth_pattern_type);
15886 : 0 : bool pattern_requested = !!(pattern_flags & flags);
15887 [ # # # # ]: 0 : bool consider_vlan = vlan_flags || (MLX5_CTRL_VLAN_FILTER & flags);
15888 : 0 : bool vlan_requested = !!(vlan_flags & flags);
15889 : :
15890 [ # # ]: 0 : if (consider_vlan)
15891 : 0 : return pattern_requested && vlan_requested;
15892 : : else
15893 : : return pattern_requested;
15894 : : }
15895 : :
15896 : : static bool
15897 : : rss_type_is_requested(struct mlx5_priv *priv,
15898 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
15899 : : {
15900 : 0 : struct rte_flow_actions_template *at = priv->hw_ctrl_rx->rss[rss_type];
15901 : : unsigned int i;
15902 : :
15903 [ # # # # ]: 0 : for (i = 0; at->actions[i].type != RTE_FLOW_ACTION_TYPE_END; ++i) {
15904 [ # # # # ]: 0 : if (at->actions[i].type == RTE_FLOW_ACTION_TYPE_RSS) {
15905 : 0 : const struct rte_flow_action_rss *rss = at->actions[i].conf;
15906 : 0 : uint64_t rss_types = rss->types;
15907 : :
15908 [ # # # # ]: 0 : if ((rss_types & priv->rss_conf.rss_hf) != rss_types)
15909 : : return false;
15910 : : }
15911 : : }
15912 : : return true;
15913 : : }
15914 : :
15915 : : static const struct rte_flow_item_eth *
15916 : : __get_eth_spec(const enum mlx5_flow_ctrl_rx_eth_pattern_type pattern)
15917 : : {
15918 : 0 : switch (pattern) {
15919 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL:
15920 : : return &ctrl_rx_eth_promisc_spec;
15921 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL_MCAST:
15922 : 0 : return &ctrl_rx_eth_mcast_spec;
15923 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST:
15924 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST_VLAN:
15925 : 0 : return &ctrl_rx_eth_bcast_spec;
15926 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST:
15927 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST_VLAN:
15928 : 0 : return &ctrl_rx_eth_ipv4_mcast_spec;
15929 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST:
15930 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST_VLAN:
15931 : 0 : return &ctrl_rx_eth_ipv6_mcast_spec;
15932 : 0 : default:
15933 : : /* This case should not be reached. */
15934 : : MLX5_ASSERT(false);
15935 : 0 : return NULL;
15936 : : }
15937 : : }
15938 : :
15939 : : static int
15940 [ # # # # : 0 : __flow_hw_ctrl_flows_single(struct rte_eth_dev *dev,
# # ]
15941 : : struct rte_flow_template_table *tbl,
15942 : : const enum mlx5_flow_ctrl_rx_eth_pattern_type pattern_type,
15943 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
15944 : : {
15945 : : const struct rte_flow_item_eth *eth_spec = __get_eth_spec(pattern_type);
15946 : : struct rte_flow_item items[5];
15947 : 0 : struct rte_flow_action actions[] = {
15948 : : { .type = RTE_FLOW_ACTION_TYPE_RSS },
15949 : : { .type = RTE_FLOW_ACTION_TYPE_END },
15950 : : };
15951 : 0 : struct mlx5_ctrl_flow_info flow_info = {
15952 : : .type = MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS,
15953 : : };
15954 : :
15955 [ # # ]: 0 : if (!eth_spec)
15956 : : return -EINVAL;
15957 : : memset(items, 0, sizeof(items));
15958 : 0 : items[0] = (struct rte_flow_item){
15959 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
15960 : : .spec = eth_spec,
15961 : : };
15962 [ # # # ]: 0 : items[1] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_VOID };
15963 [ # # # ]: 0 : items[2] = flow_hw_get_ctrl_rx_l3_item(rss_type);
15964 : 0 : items[3] = flow_hw_get_ctrl_rx_l4_item(rss_type);
15965 : 0 : items[4] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_END };
15966 : : /* Without VLAN filtering, only a single flow rule must be created. */
15967 : 0 : return flow_hw_create_ctrl_flow(dev, dev, tbl, items, 0, actions, 0, &flow_info, false);
15968 : : }
15969 : :
15970 : : static int
15971 : 0 : __flow_hw_ctrl_flows_single_vlan(struct rte_eth_dev *dev,
15972 : : struct rte_flow_template_table *tbl,
15973 : : const enum mlx5_flow_ctrl_rx_eth_pattern_type pattern_type,
15974 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
15975 : : {
15976 [ # # # # : 0 : struct mlx5_priv *priv = dev->data->dev_private;
# # ]
15977 : : const struct rte_flow_item_eth *eth_spec = __get_eth_spec(pattern_type);
15978 : : struct rte_flow_item items[5];
15979 : 0 : struct rte_flow_action actions[] = {
15980 : : { .type = RTE_FLOW_ACTION_TYPE_RSS },
15981 : : { .type = RTE_FLOW_ACTION_TYPE_END },
15982 : : };
15983 : 0 : struct mlx5_ctrl_flow_info flow_info = {
15984 : : .type = MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS,
15985 : : };
15986 : : unsigned int i;
15987 : :
15988 [ # # ]: 0 : if (!eth_spec)
15989 : : return -EINVAL;
15990 : : memset(items, 0, sizeof(items));
15991 : 0 : items[0] = (struct rte_flow_item){
15992 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
15993 : : .spec = eth_spec,
15994 : : };
15995 : : /* Optional VLAN for now will be VOID - will be filled later. */
15996 [ # # # ]: 0 : items[1] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_VLAN };
15997 [ # # # ]: 0 : items[2] = flow_hw_get_ctrl_rx_l3_item(rss_type);
15998 : 0 : items[3] = flow_hw_get_ctrl_rx_l4_item(rss_type);
15999 : 0 : items[4] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_END };
16000 : : /* Since VLAN filtering is done, create a single flow rule for each registered vid. */
16001 [ # # ]: 0 : for (i = 0; i < priv->vlan_filter_n; ++i) {
16002 : 0 : uint16_t vlan = priv->vlan_filter[i];
16003 : 0 : struct rte_flow_item_vlan vlan_spec = {
16004 [ # # ]: 0 : .hdr.vlan_tci = rte_cpu_to_be_16(vlan),
16005 : : };
16006 : :
16007 : 0 : items[1].spec = &vlan_spec;
16008 [ # # ]: 0 : if (flow_hw_create_ctrl_flow(dev, dev,
16009 : : tbl, items, 0, actions, 0, &flow_info, false))
16010 : 0 : return -rte_errno;
16011 : : }
16012 : : return 0;
16013 : : }
16014 : :
16015 : : static int
16016 : 0 : __flow_hw_ctrl_flows_unicast_create(struct rte_eth_dev *dev,
16017 : : struct rte_flow_template_table *tbl,
16018 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type,
16019 : : const struct rte_ether_addr *addr)
16020 : : {
16021 : 0 : struct rte_flow_item_eth eth_spec = {
16022 : : .hdr.dst_addr = *addr,
16023 : : };
16024 : : struct rte_flow_item items[5];
16025 : 0 : struct rte_flow_action actions[] = {
16026 : : { .type = RTE_FLOW_ACTION_TYPE_RSS },
16027 : : { .type = RTE_FLOW_ACTION_TYPE_END },
16028 : : };
16029 [ # # # ]: 0 : struct mlx5_ctrl_flow_info flow_info = {
16030 : : .type = MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC,
16031 : : .uc = {
16032 : : .dmac = *addr,
16033 : : },
16034 : : };
16035 : :
16036 : : memset(items, 0, sizeof(items));
16037 : 0 : items[0] = (struct rte_flow_item){
16038 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
16039 : : .spec = ð_spec,
16040 : : };
16041 [ # # # ]: 0 : items[1] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_VOID };
16042 [ # # # ]: 0 : items[2] = flow_hw_get_ctrl_rx_l3_item(rss_type);
16043 : 0 : items[3] = flow_hw_get_ctrl_rx_l4_item(rss_type);
16044 : 0 : items[4] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_END };
16045 : :
16046 [ # # ]: 0 : if (flow_hw_create_ctrl_flow(dev, dev, tbl, items, 0, actions, 0, &flow_info, false))
16047 : 0 : return -rte_errno;
16048 : :
16049 : : return 0;
16050 : : }
16051 : :
16052 : : static int
16053 : 0 : __flow_hw_ctrl_flows_unicast(struct rte_eth_dev *dev,
16054 : : struct rte_flow_template_table *tbl,
16055 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
16056 : : {
16057 : : unsigned int i;
16058 : : int ret;
16059 : :
16060 [ # # ]: 0 : for (i = 0; i < MLX5_MAX_MAC_ADDRESSES; ++i) {
16061 [ # # ]: 0 : struct rte_ether_addr *mac = &dev->data->mac_addrs[i];
16062 : :
16063 [ # # ]: 0 : if (rte_is_zero_ether_addr(mac))
16064 : 0 : continue;
16065 : :
16066 : 0 : ret = __flow_hw_ctrl_flows_unicast_create(dev, tbl, rss_type, mac);
16067 [ # # ]: 0 : if (ret < 0)
16068 : 0 : return ret;
16069 : : }
16070 : : return 0;
16071 : : }
16072 : :
16073 : : static int
16074 : 0 : __flow_hw_ctrl_flows_unicast_vlan_create(struct rte_eth_dev *dev,
16075 : : struct rte_flow_template_table *tbl,
16076 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type,
16077 : : const struct rte_ether_addr *addr,
16078 : : const uint16_t vid)
16079 : : {
16080 : 0 : struct rte_flow_item_eth eth_spec = {
16081 : : .hdr.dst_addr = *addr,
16082 : : };
16083 : 0 : struct rte_flow_item_vlan vlan_spec = {
16084 [ # # ]: 0 : .tci = rte_cpu_to_be_16(vid),
16085 : : };
16086 : : struct rte_flow_item items[5];
16087 : 0 : struct rte_flow_action actions[] = {
16088 : : { .type = RTE_FLOW_ACTION_TYPE_RSS },
16089 : : { .type = RTE_FLOW_ACTION_TYPE_END },
16090 : : };
16091 [ # # # ]: 0 : struct mlx5_ctrl_flow_info flow_info = {
16092 : : .type = MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC_VLAN,
16093 : : .uc = {
16094 : : .dmac = *addr,
16095 : : .vlan = vid,
16096 : : },
16097 : : };
16098 : :
16099 : : memset(items, 0, sizeof(items));
16100 : 0 : items[0] = (struct rte_flow_item){
16101 : : .type = RTE_FLOW_ITEM_TYPE_ETH,
16102 : : .spec = ð_spec,
16103 : : };
16104 [ # # # ]: 0 : items[1] = (struct rte_flow_item){
16105 : : .type = RTE_FLOW_ITEM_TYPE_VLAN,
16106 : : .spec = &vlan_spec,
16107 : : };
16108 [ # # # ]: 0 : items[2] = flow_hw_get_ctrl_rx_l3_item(rss_type);
16109 : 0 : items[3] = flow_hw_get_ctrl_rx_l4_item(rss_type);
16110 : 0 : items[4] = (struct rte_flow_item){ .type = RTE_FLOW_ITEM_TYPE_END };
16111 : :
16112 [ # # ]: 0 : if (flow_hw_create_ctrl_flow(dev, dev, tbl, items, 0, actions, 0, &flow_info, false))
16113 : 0 : return -rte_errno;
16114 : :
16115 : : return 0;
16116 : : }
16117 : :
16118 : : static int
16119 : 0 : __flow_hw_ctrl_flows_unicast_vlan(struct rte_eth_dev *dev,
16120 : : struct rte_flow_template_table *tbl,
16121 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
16122 : : {
16123 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16124 : : unsigned int i;
16125 : : unsigned int j;
16126 : :
16127 [ # # ]: 0 : for (i = 0; i < MLX5_MAX_MAC_ADDRESSES; ++i) {
16128 [ # # ]: 0 : struct rte_ether_addr *mac = &dev->data->mac_addrs[i];
16129 : :
16130 [ # # ]: 0 : if (rte_is_zero_ether_addr(mac))
16131 : 0 : continue;
16132 : :
16133 [ # # ]: 0 : for (j = 0; j < priv->vlan_filter_n; ++j) {
16134 : 0 : uint16_t vlan = priv->vlan_filter[j];
16135 : : int ret;
16136 : :
16137 : 0 : ret = __flow_hw_ctrl_flows_unicast_vlan_create(dev, tbl, rss_type,
16138 : : mac, vlan);
16139 [ # # ]: 0 : if (ret < 0)
16140 : 0 : return ret;
16141 : : }
16142 : : }
16143 : : return 0;
16144 : : }
16145 : :
16146 : : static int
16147 : 0 : __flow_hw_ctrl_flows(struct rte_eth_dev *dev,
16148 : : struct rte_flow_template_table *tbl,
16149 : : const enum mlx5_flow_ctrl_rx_eth_pattern_type pattern_type,
16150 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type)
16151 : : {
16152 [ # # # # : 0 : switch (pattern_type) {
# ]
16153 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL:
16154 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_ALL_MCAST:
16155 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST:
16156 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST:
16157 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST:
16158 : 0 : return __flow_hw_ctrl_flows_single(dev, tbl, pattern_type, rss_type);
16159 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_BCAST_VLAN:
16160 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV4_MCAST_VLAN:
16161 : : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_IPV6_MCAST_VLAN:
16162 : 0 : return __flow_hw_ctrl_flows_single_vlan(dev, tbl, pattern_type, rss_type);
16163 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC:
16164 : 0 : return __flow_hw_ctrl_flows_unicast(dev, tbl, rss_type);
16165 : 0 : case MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN:
16166 : 0 : return __flow_hw_ctrl_flows_unicast_vlan(dev, tbl, rss_type);
16167 : 0 : default:
16168 : : /* Should not reach here. */
16169 : : MLX5_ASSERT(false);
16170 : 0 : rte_errno = EINVAL;
16171 : 0 : return -EINVAL;
16172 : : }
16173 : : }
16174 : :
16175 : :
16176 : : int
16177 : 0 : mlx5_flow_hw_ctrl_flows(struct rte_eth_dev *dev, uint32_t flags)
16178 : : {
16179 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16180 : : struct mlx5_flow_hw_ctrl_rx *hw_ctrl_rx;
16181 : : unsigned int i;
16182 : : int j;
16183 : : int ret = 0;
16184 : :
16185 : : RTE_SET_USED(priv);
16186 : : RTE_SET_USED(flags);
16187 [ # # ]: 0 : if (!priv->dr_ctx) {
16188 : 0 : DRV_LOG(DEBUG, "port %u Control flow rules will not be created. "
16189 : : "HWS needs to be configured beforehand.",
16190 : : dev->data->port_id);
16191 : 0 : return 0;
16192 : : }
16193 [ # # ]: 0 : if (!priv->hw_ctrl_rx) {
16194 : 0 : DRV_LOG(ERR, "port %u Control flow rules templates were not created.",
16195 : : dev->data->port_id);
16196 : 0 : rte_errno = EINVAL;
16197 : 0 : return -rte_errno;
16198 : : }
16199 : : hw_ctrl_rx = priv->hw_ctrl_rx;
16200 [ # # ]: 0 : for (i = 0; i < MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_MAX; ++i) {
16201 : : const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type = i;
16202 : :
16203 [ # # ]: 0 : if (!eth_pattern_type_is_requested(eth_pattern_type, flags))
16204 : 0 : continue;
16205 [ # # ]: 0 : for (j = 0; j < MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX; ++j) {
16206 : 0 : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type = j;
16207 : : struct rte_flow_actions_template *at;
16208 : : struct mlx5_flow_hw_ctrl_rx_table *tmpls = &hw_ctrl_rx->tables[i][j];
16209 : 0 : const struct mlx5_flow_template_table_cfg cfg = {
16210 : : .attr = tmpls->attr,
16211 : : .external = 0,
16212 : : };
16213 : :
16214 [ # # ]: 0 : if (!hw_ctrl_rx->rss[rss_type]) {
16215 : 0 : at = flow_hw_create_ctrl_rx_rss_template(dev, rss_type);
16216 [ # # ]: 0 : if (!at)
16217 : 0 : return -rte_errno;
16218 : 0 : hw_ctrl_rx->rss[rss_type] = at;
16219 : : } else {
16220 : 0 : at = hw_ctrl_rx->rss[rss_type];
16221 : : }
16222 [ # # ]: 0 : if (!rss_type_is_requested(priv, rss_type))
16223 : 0 : continue;
16224 [ # # ]: 0 : if (!tmpls->tbl) {
16225 : 0 : tmpls->tbl = flow_hw_table_create(dev, &cfg,
16226 : : &tmpls->pt, 1, &at, 1, NULL);
16227 [ # # ]: 0 : if (!tmpls->tbl) {
16228 : 0 : DRV_LOG(ERR, "port %u Failed to create template table "
16229 : : "for control flow rules. Unable to create "
16230 : : "control flow rules.",
16231 : : dev->data->port_id);
16232 : 0 : return -rte_errno;
16233 : : }
16234 : : }
16235 : :
16236 : 0 : ret = __flow_hw_ctrl_flows(dev, tmpls->tbl, eth_pattern_type, rss_type);
16237 [ # # ]: 0 : if (ret) {
16238 : 0 : DRV_LOG(ERR, "port %u Failed to create control flow rule.",
16239 : : dev->data->port_id);
16240 : 0 : return ret;
16241 : : }
16242 : : }
16243 : : }
16244 : : return 0;
16245 : : }
16246 : :
16247 : : static int
16248 : 0 : mlx5_flow_hw_ctrl_flow_single(struct rte_eth_dev *dev,
16249 : : const enum mlx5_flow_ctrl_rx_eth_pattern_type eth_pattern_type,
16250 : : const struct rte_ether_addr *addr,
16251 : : const uint16_t vlan)
16252 : : {
16253 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16254 : : struct mlx5_flow_hw_ctrl_rx *hw_ctrl_rx;
16255 : : unsigned int j;
16256 : : int ret = 0;
16257 : :
16258 [ # # ]: 0 : if (!priv->dr_ctx) {
16259 : 0 : DRV_LOG(DEBUG, "port %u Control flow rules will not be created. "
16260 : : "HWS needs to be configured beforehand.",
16261 : : dev->data->port_id);
16262 : 0 : return 0;
16263 : : }
16264 [ # # ]: 0 : if (!priv->hw_ctrl_rx) {
16265 : 0 : DRV_LOG(ERR, "port %u Control flow rules templates were not created.",
16266 : : dev->data->port_id);
16267 : 0 : rte_errno = EINVAL;
16268 : 0 : return -rte_errno;
16269 : : }
16270 : : hw_ctrl_rx = priv->hw_ctrl_rx;
16271 : :
16272 : : /* TODO: this part should be somehow refactored. It's common with common flow creation. */
16273 [ # # ]: 0 : for (j = 0; j < MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX; ++j) {
16274 : : const enum mlx5_flow_ctrl_rx_expanded_rss_type rss_type = j;
16275 : : const unsigned int pti = eth_pattern_type;
16276 : : struct rte_flow_actions_template *at;
16277 : : struct mlx5_flow_hw_ctrl_rx_table *tmpls = &hw_ctrl_rx->tables[pti][j];
16278 : 0 : const struct mlx5_flow_template_table_cfg cfg = {
16279 : : .attr = tmpls->attr,
16280 : : .external = 0,
16281 : : };
16282 : :
16283 [ # # ]: 0 : if (!hw_ctrl_rx->rss[rss_type]) {
16284 : 0 : at = flow_hw_create_ctrl_rx_rss_template(dev, rss_type);
16285 [ # # ]: 0 : if (!at)
16286 : 0 : return -rte_errno;
16287 : 0 : hw_ctrl_rx->rss[rss_type] = at;
16288 : : } else {
16289 : 0 : at = hw_ctrl_rx->rss[rss_type];
16290 : : }
16291 [ # # ]: 0 : if (!rss_type_is_requested(priv, rss_type))
16292 : 0 : continue;
16293 [ # # ]: 0 : if (!tmpls->tbl) {
16294 : 0 : tmpls->tbl = flow_hw_table_create(dev, &cfg,
16295 : : &tmpls->pt, 1, &at, 1, NULL);
16296 [ # # ]: 0 : if (!tmpls->tbl) {
16297 : 0 : DRV_LOG(ERR, "port %u Failed to create template table "
16298 : : "for control flow rules. Unable to create "
16299 : : "control flow rules.",
16300 : : dev->data->port_id);
16301 : 0 : return -rte_errno;
16302 : : }
16303 : : }
16304 : :
16305 : : MLX5_ASSERT(eth_pattern_type == MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC ||
16306 : : eth_pattern_type == MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN);
16307 : :
16308 [ # # ]: 0 : if (eth_pattern_type == MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC)
16309 : 0 : ret = __flow_hw_ctrl_flows_unicast_create(dev, tmpls->tbl, rss_type, addr);
16310 : : else
16311 : 0 : ret = __flow_hw_ctrl_flows_unicast_vlan_create(dev, tmpls->tbl, rss_type,
16312 : : addr, vlan);
16313 [ # # ]: 0 : if (ret) {
16314 : 0 : DRV_LOG(ERR, "port %u Failed to create unicast control flow rule.",
16315 : : dev->data->port_id);
16316 : 0 : return ret;
16317 : : }
16318 : : }
16319 : :
16320 : : return 0;
16321 : : }
16322 : :
16323 : : int
16324 : 0 : mlx5_flow_hw_ctrl_flow_dmac(struct rte_eth_dev *dev,
16325 : : const struct rte_ether_addr *addr)
16326 : : {
16327 : 0 : return mlx5_flow_hw_ctrl_flow_single(dev, MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC,
16328 : : addr, 0);
16329 : : }
16330 : :
16331 : : int
16332 : 0 : mlx5_flow_hw_ctrl_flow_dmac_destroy(struct rte_eth_dev *dev,
16333 : : const struct rte_ether_addr *addr)
16334 : : {
16335 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16336 : : struct mlx5_ctrl_flow_entry *entry;
16337 : : struct mlx5_ctrl_flow_entry *tmp;
16338 : : int ret;
16339 : :
16340 : : /*
16341 : : * HWS does not have automatic RSS flow expansion,
16342 : : * so each variant of the control flow rule is a separate entry in the list.
16343 : : * In that case, the whole list must be traversed.
16344 : : */
16345 : 0 : entry = LIST_FIRST(&priv->hw_ctrl_flows);
16346 [ # # ]: 0 : while (entry != NULL) {
16347 : 0 : tmp = LIST_NEXT(entry, next);
16348 : :
16349 [ # # # # ]: 0 : if (entry->info.type != MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC ||
16350 : : !rte_is_same_ether_addr(addr, &entry->info.uc.dmac)) {
16351 : : entry = tmp;
16352 : 0 : continue;
16353 : : }
16354 : :
16355 : 0 : ret = flow_hw_destroy_ctrl_flow(dev, entry->flow);
16356 [ # # ]: 0 : LIST_REMOVE(entry, next);
16357 : 0 : mlx5_free(entry);
16358 [ # # ]: 0 : if (ret)
16359 : 0 : return ret;
16360 : :
16361 : : entry = tmp;
16362 : : }
16363 : : return 0;
16364 : : }
16365 : :
16366 : : int
16367 : 0 : mlx5_flow_hw_ctrl_flow_dmac_vlan(struct rte_eth_dev *dev,
16368 : : const struct rte_ether_addr *addr,
16369 : : const uint16_t vlan)
16370 : : {
16371 : 0 : return mlx5_flow_hw_ctrl_flow_single(dev, MLX5_FLOW_HW_CTRL_RX_ETH_PATTERN_DMAC_VLAN,
16372 : : addr, vlan);
16373 : : }
16374 : :
16375 : : int
16376 : 0 : mlx5_flow_hw_ctrl_flow_dmac_vlan_destroy(struct rte_eth_dev *dev,
16377 : : const struct rte_ether_addr *addr,
16378 : : const uint16_t vlan)
16379 : : {
16380 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16381 : : struct mlx5_ctrl_flow_entry *entry;
16382 : : struct mlx5_ctrl_flow_entry *tmp;
16383 : : int ret;
16384 : :
16385 : : /*
16386 : : * HWS does not have automatic RSS flow expansion,
16387 : : * so each variant of the control flow rule is a separate entry in the list.
16388 : : * In that case, the whole list must be traversed.
16389 : : */
16390 : 0 : entry = LIST_FIRST(&priv->hw_ctrl_flows);
16391 [ # # ]: 0 : while (entry != NULL) {
16392 : 0 : tmp = LIST_NEXT(entry, next);
16393 : :
16394 [ # # # # ]: 0 : if (entry->info.type != MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC_VLAN ||
16395 : 0 : !rte_is_same_ether_addr(addr, &entry->info.uc.dmac) ||
16396 [ # # ]: 0 : vlan != entry->info.uc.vlan) {
16397 : : entry = tmp;
16398 : 0 : continue;
16399 : : }
16400 : :
16401 : 0 : ret = flow_hw_destroy_ctrl_flow(dev, entry->flow);
16402 [ # # ]: 0 : LIST_REMOVE(entry, next);
16403 : 0 : mlx5_free(entry);
16404 [ # # ]: 0 : if (ret)
16405 : 0 : return ret;
16406 : :
16407 : : entry = tmp;
16408 : : }
16409 : : return 0;
16410 : : }
16411 : :
16412 : : static __rte_always_inline uint32_t
16413 : : mlx5_reformat_domain_to_tbl_type(const struct rte_flow_indir_action_conf *domain)
16414 : : {
16415 : : uint32_t tbl_type;
16416 : :
16417 : 0 : if (domain->transfer)
16418 : : tbl_type = MLX5DR_ACTION_FLAG_HWS_FDB;
16419 [ # # ]: 0 : else if (domain->egress)
16420 : : tbl_type = MLX5DR_ACTION_FLAG_HWS_TX;
16421 [ # # ]: 0 : else if (domain->ingress)
16422 : : tbl_type = MLX5DR_ACTION_FLAG_HWS_RX;
16423 : : else
16424 : : tbl_type = UINT32_MAX;
16425 : : return tbl_type;
16426 : : }
16427 : :
16428 : : static struct mlx5_hw_encap_decap_action *
16429 : 0 : __mlx5_reformat_create(struct rte_eth_dev *dev,
16430 : : const struct rte_flow_action_raw_encap *encap_conf,
16431 : : const struct rte_flow_indir_action_conf *domain,
16432 : : enum mlx5dr_action_type type)
16433 : : {
16434 [ # # ]: 0 : struct mlx5_priv *priv = dev->data->dev_private;
16435 : : struct mlx5_hw_encap_decap_action *handle;
16436 : : struct mlx5dr_action_reformat_header hdr;
16437 : : uint32_t flags;
16438 : :
16439 : : flags = mlx5_reformat_domain_to_tbl_type(domain);
16440 : 0 : flags |= (uint32_t)MLX5DR_ACTION_FLAG_SHARED;
16441 [ # # ]: 0 : if (flags == UINT32_MAX) {
16442 : 0 : DRV_LOG(ERR, "Reformat: invalid indirect action configuration");
16443 : 0 : return NULL;
16444 : : }
16445 : : /* Allocate new list entry. */
16446 : 0 : handle = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*handle), 0, SOCKET_ID_ANY);
16447 [ # # ]: 0 : if (!handle) {
16448 : 0 : DRV_LOG(ERR, "Reformat: failed to allocate reformat entry");
16449 : 0 : return NULL;
16450 : : }
16451 : 0 : handle->action_type = type;
16452 [ # # ]: 0 : hdr.sz = encap_conf ? encap_conf->size : 0;
16453 [ # # ]: 0 : hdr.data = encap_conf ? encap_conf->data : NULL;
16454 : 0 : handle->action = mlx5dr_action_create_reformat(priv->dr_ctx,
16455 : : type, 1, &hdr, 0, flags);
16456 [ # # ]: 0 : if (!handle->action) {
16457 : 0 : DRV_LOG(ERR, "Reformat: failed to create reformat action");
16458 : 0 : mlx5_free(handle);
16459 : 0 : return NULL;
16460 : : }
16461 : : return handle;
16462 : : }
16463 : :
16464 : : /**
16465 : : * Create mlx5 reformat action.
16466 : : *
16467 : : * @param[in] dev
16468 : : * Pointer to rte_eth_dev structure.
16469 : : * @param[in] conf
16470 : : * Pointer to the indirect action parameters.
16471 : : * @param[in] encap_action
16472 : : * Pointer to the raw_encap action configuration.
16473 : : * @param[in] decap_action
16474 : : * Pointer to the raw_decap action configuration.
16475 : : * @param[out] error
16476 : : * Pointer to error structure.
16477 : : *
16478 : : * @return
16479 : : * A valid shared action handle in case of success, NULL otherwise and
16480 : : * rte_errno is set.
16481 : : */
16482 : : struct mlx5_hw_encap_decap_action*
16483 : 0 : mlx5_reformat_action_create(struct rte_eth_dev *dev,
16484 : : const struct rte_flow_indir_action_conf *conf,
16485 : : const struct rte_flow_action *encap_action,
16486 : : const struct rte_flow_action *decap_action,
16487 : : struct rte_flow_error *error)
16488 : : {
16489 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16490 : : struct mlx5_hw_encap_decap_action *handle;
16491 : : const struct rte_flow_action_raw_encap *encap = NULL;
16492 : : const struct rte_flow_action_raw_decap *decap = NULL;
16493 : : enum mlx5dr_action_type type = MLX5DR_ACTION_TYP_LAST;
16494 : :
16495 : : MLX5_ASSERT(!encap_action || encap_action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP);
16496 : : MLX5_ASSERT(!decap_action || decap_action->type == RTE_FLOW_ACTION_TYPE_RAW_DECAP);
16497 [ # # ]: 0 : if (priv->sh->config.dv_flow_en != 2) {
16498 : 0 : rte_flow_error_set(error, ENOTSUP,
16499 : : RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
16500 : : "Reformat: hardware does not support");
16501 : 0 : return NULL;
16502 : : }
16503 [ # # # # ]: 0 : if (!conf || (conf->transfer + conf->egress + conf->ingress != 1)) {
16504 : 0 : rte_flow_error_set(error, EINVAL,
16505 : : RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
16506 : : "Reformat: domain should be specified");
16507 : 0 : return NULL;
16508 : : }
16509 [ # # # # : 0 : if ((encap_action && !encap_action->conf) || (decap_action && !decap_action->conf)) {
# # # # ]
16510 : 0 : rte_flow_error_set(error, EINVAL,
16511 : : RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
16512 : : "Reformat: missed action configuration");
16513 : 0 : return NULL;
16514 : : }
16515 [ # # ]: 0 : if (encap_action && !decap_action) {
16516 : 0 : encap = (const struct rte_flow_action_raw_encap *)encap_action->conf;
16517 [ # # ]: 0 : if (!encap->size || encap->size > MLX5_ENCAP_MAX_LEN ||
16518 : : encap->size < MLX5_ENCAPSULATION_DECISION_SIZE) {
16519 : 0 : rte_flow_error_set(error, EINVAL,
16520 : : RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
16521 : : "Reformat: Invalid encap length");
16522 : 0 : return NULL;
16523 : : }
16524 : : type = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2;
16525 [ # # ]: 0 : } else if (decap_action && !encap_action) {
16526 : 0 : decap = (const struct rte_flow_action_raw_decap *)decap_action->conf;
16527 [ # # ]: 0 : if (!decap->size || decap->size < MLX5_ENCAPSULATION_DECISION_SIZE) {
16528 : 0 : rte_flow_error_set(error, EINVAL,
16529 : : RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
16530 : : "Reformat: Invalid decap length");
16531 : 0 : return NULL;
16532 : : }
16533 : : type = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2;
16534 [ # # ]: 0 : } else if (encap_action && decap_action) {
16535 : 0 : decap = (const struct rte_flow_action_raw_decap *)decap_action->conf;
16536 : 0 : encap = (const struct rte_flow_action_raw_encap *)encap_action->conf;
16537 [ # # ]: 0 : if (decap->size < MLX5_ENCAPSULATION_DECISION_SIZE &&
16538 [ # # # # ]: 0 : encap->size >= MLX5_ENCAPSULATION_DECISION_SIZE &&
16539 : : encap->size <= MLX5_ENCAP_MAX_LEN) {
16540 : : type = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3;
16541 [ # # ]: 0 : } else if (decap->size >= MLX5_ENCAPSULATION_DECISION_SIZE &&
16542 [ # # ]: 0 : encap->size < MLX5_ENCAPSULATION_DECISION_SIZE) {
16543 : : type = MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2;
16544 : : } else {
16545 : 0 : rte_flow_error_set(error, EINVAL,
16546 : : RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
16547 : : "Reformat: Invalid decap & encap length");
16548 : 0 : return NULL;
16549 : : }
16550 [ # # ]: 0 : } else if (!encap_action && !decap_action) {
16551 : 0 : rte_flow_error_set(error, EINVAL,
16552 : : RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
16553 : : "Reformat: Invalid decap & encap configurations");
16554 : 0 : return NULL;
16555 : : }
16556 [ # # ]: 0 : if (!priv->dr_ctx) {
16557 : 0 : rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
16558 : : encap_action, "Reformat: HWS not supported");
16559 : 0 : return NULL;
16560 : : }
16561 : 0 : handle = __mlx5_reformat_create(dev, encap, conf, type);
16562 [ # # ]: 0 : if (!handle) {
16563 : 0 : rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, encap_action,
16564 : : "Reformat: failed to create indirect action");
16565 : 0 : return NULL;
16566 : : }
16567 : : return handle;
16568 : : }
16569 : :
16570 : : /**
16571 : : * Destroy the indirect reformat action.
16572 : : * Release action related resources on the NIC and the memory.
16573 : : * Lock free, (mutex should be acquired by caller).
16574 : : *
16575 : : * @param[in] dev
16576 : : * Pointer to the Ethernet device structure.
16577 : : * @param[in] handle
16578 : : * The indirect action list handle to be removed.
16579 : : * @param[out] error
16580 : : * Perform verbose error reporting if not NULL. Initialized in case of
16581 : : * error only.
16582 : : *
16583 : : * @return
16584 : : * 0 on success, otherwise negative errno value.
16585 : : */
16586 : : int
16587 : 0 : mlx5_reformat_action_destroy(struct rte_eth_dev *dev,
16588 : : struct rte_flow_action_list_handle *handle,
16589 : : struct rte_flow_error *error)
16590 : : {
16591 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16592 : : struct mlx5_hw_encap_decap_action *action;
16593 : :
16594 : : action = (struct mlx5_hw_encap_decap_action *)handle;
16595 [ # # # # ]: 0 : if (!priv->dr_ctx || !action)
16596 : 0 : return rte_flow_error_set(error, ENOTSUP,
16597 : : RTE_FLOW_ERROR_TYPE_ACTION, handle,
16598 : : "Reformat: invalid action handle");
16599 : 0 : mlx5dr_action_destroy(action->action);
16600 : 0 : mlx5_free(handle);
16601 : 0 : return 0;
16602 : : }
16603 : :
16604 : : static bool
16605 : 0 : flow_hw_is_item_masked(const struct rte_flow_item *item)
16606 : : {
16607 : : const uint8_t *byte;
16608 : : int size;
16609 : : int i;
16610 : :
16611 [ # # ]: 0 : if (item->mask == NULL)
16612 : : return false;
16613 : :
16614 [ # # ]: 0 : switch ((int)item->type) {
16615 : : case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
16616 : : size = sizeof(struct rte_flow_item_tag);
16617 : : break;
16618 : : case MLX5_RTE_FLOW_ITEM_TYPE_SQ:
16619 : : size = sizeof(struct mlx5_rte_flow_item_sq);
16620 : : break;
16621 : 0 : default:
16622 : 0 : size = rte_flow_conv(RTE_FLOW_CONV_OP_ITEM_MASK, NULL, 0, item, NULL);
16623 : : /*
16624 : : * Pattern template items are passed to this function.
16625 : : * These items were already validated, so error is not expected.
16626 : : * Also, if mask is NULL, then spec size is bigger than 0 always.
16627 : : */
16628 : : MLX5_ASSERT(size > 0);
16629 : : }
16630 : :
16631 : 0 : byte = (const uint8_t *)item->mask;
16632 [ # # ]: 0 : for (i = 0; i < size; ++i)
16633 [ # # ]: 0 : if (byte[i])
16634 : : return true;
16635 : :
16636 : : return false;
16637 : : }
16638 : :
16639 : : static int
16640 : 0 : flow_hw_validate_rule_pattern(struct rte_eth_dev *dev,
16641 : : const struct rte_flow_template_table *table,
16642 : : const uint8_t pattern_template_idx,
16643 : : const struct rte_flow_item items[],
16644 : : struct rte_flow_error *error)
16645 : : {
16646 : : const struct rte_flow_pattern_template *pt;
16647 : : const struct rte_flow_item *pt_item;
16648 : :
16649 [ # # ]: 0 : if (pattern_template_idx >= table->nb_item_templates)
16650 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
16651 : : "Pattern template index out of range");
16652 : :
16653 : 0 : pt = table->its[pattern_template_idx];
16654 : 0 : pt_item = pt->items;
16655 : :
16656 : : /* If any item was prepended, skip it. */
16657 [ # # ]: 0 : if (pt->implicit_port || pt->implicit_tag)
16658 : 0 : pt_item++;
16659 : :
16660 [ # # ]: 0 : for (; pt_item->type != RTE_FLOW_ITEM_TYPE_END; pt_item++, items++) {
16661 [ # # ]: 0 : if (pt_item->type != items->type)
16662 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM,
16663 : : items, "Item type does not match the template");
16664 : :
16665 : : /*
16666 : : * Assumptions:
16667 : : * - Currently mlx5dr layer contains info on which fields in masks are supported.
16668 : : * - This info is not exposed to PMD directly.
16669 : : * - Because of that, it is assumed that since pattern template is correct,
16670 : : * then, items' masks in pattern template have nonzero values only in
16671 : : * supported fields.
16672 : : * This is known, because a temporary mlx5dr matcher is created during pattern
16673 : : * template creation to validate the template.
16674 : : * - As a result, it is safe to look for nonzero bytes in mask to determine if
16675 : : * item spec is needed in a flow rule.
16676 : : */
16677 [ # # ]: 0 : if (!flow_hw_is_item_masked(pt_item))
16678 : 0 : continue;
16679 : :
16680 [ # # ]: 0 : if (items->spec == NULL)
16681 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
16682 : : items, "Item spec is required");
16683 : :
16684 [ # # # ]: 0 : switch (items->type) {
16685 : : const struct rte_flow_item_ethdev *ethdev;
16686 : : const struct rte_flow_item_tx_queue *tx_queue;
16687 : : struct mlx5_txq_ctrl *txq;
16688 : :
16689 : 0 : case RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT:
16690 : : ethdev = items->spec;
16691 [ # # ]: 0 : if (flow_hw_validate_target_port_id(dev, ethdev->port_id)) {
16692 : 0 : return rte_flow_error_set(error, EINVAL,
16693 : : RTE_FLOW_ERROR_TYPE_ITEM_SPEC, items,
16694 : : "Invalid port");
16695 : : }
16696 : : break;
16697 : 0 : case RTE_FLOW_ITEM_TYPE_TX_QUEUE:
16698 : : tx_queue = items->spec;
16699 [ # # # # ]: 0 : if (mlx5_is_external_txq(dev, tx_queue->tx_queue))
16700 : 0 : continue;
16701 : 0 : txq = mlx5_txq_get(dev, tx_queue->tx_queue);
16702 [ # # ]: 0 : if (!txq)
16703 : 0 : return rte_flow_error_set(error, EINVAL,
16704 : : RTE_FLOW_ERROR_TYPE_ITEM_SPEC, items,
16705 : : "Invalid Tx queue");
16706 : 0 : mlx5_txq_release(dev, tx_queue->tx_queue);
16707 : : default:
16708 : : break;
16709 : : }
16710 : : }
16711 : :
16712 : : return 0;
16713 : : }
16714 : :
16715 : : static bool
16716 : 0 : flow_hw_valid_indirect_action_type(const struct rte_flow_action *user_action,
16717 : : const enum rte_flow_action_type expected_type)
16718 : : {
16719 : 0 : uint32_t user_indirect_type = MLX5_INDIRECT_ACTION_TYPE_GET(user_action->conf);
16720 : : uint32_t expected_indirect_type;
16721 : :
16722 [ # # # # : 0 : switch ((int)expected_type) {
# # # ]
16723 : : case RTE_FLOW_ACTION_TYPE_RSS:
16724 : : case MLX5_RTE_FLOW_ACTION_TYPE_RSS:
16725 : : expected_indirect_type = MLX5_INDIRECT_ACTION_TYPE_RSS;
16726 : : break;
16727 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
16728 : : case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
16729 : : expected_indirect_type = MLX5_INDIRECT_ACTION_TYPE_COUNT;
16730 : 0 : break;
16731 : 0 : case RTE_FLOW_ACTION_TYPE_AGE:
16732 : : expected_indirect_type = MLX5_INDIRECT_ACTION_TYPE_AGE;
16733 : 0 : break;
16734 : 0 : case RTE_FLOW_ACTION_TYPE_CONNTRACK:
16735 : : expected_indirect_type = MLX5_INDIRECT_ACTION_TYPE_CT;
16736 : 0 : break;
16737 : 0 : case RTE_FLOW_ACTION_TYPE_METER_MARK:
16738 : : case MLX5_RTE_FLOW_ACTION_TYPE_METER_MARK:
16739 : : expected_indirect_type = MLX5_INDIRECT_ACTION_TYPE_METER_MARK;
16740 : 0 : break;
16741 : 0 : case RTE_FLOW_ACTION_TYPE_QUOTA:
16742 : : expected_indirect_type = MLX5_INDIRECT_ACTION_TYPE_QUOTA;
16743 : 0 : break;
16744 : : default:
16745 : : return false;
16746 : : }
16747 : :
16748 : 0 : return user_indirect_type == expected_indirect_type;
16749 : : }
16750 : :
16751 : : static int
16752 : 0 : flow_hw_validate_rule_actions(struct rte_eth_dev *dev,
16753 : : const struct rte_flow_template_table *table,
16754 : : const uint8_t actions_template_idx,
16755 : : const struct rte_flow_action actions[],
16756 : : struct rte_flow_error *error)
16757 : : {
16758 : : const struct rte_flow_actions_template *at;
16759 : : const struct mlx5_hw_actions *hw_acts;
16760 : : const struct mlx5_action_construct_data *act_data;
16761 : : unsigned int idx;
16762 : :
16763 [ # # ]: 0 : if (actions_template_idx >= table->nb_action_templates)
16764 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
16765 : : "Actions template index out of range");
16766 : :
16767 : 0 : at = table->ats[actions_template_idx].action_template;
16768 : : hw_acts = &table->ats[actions_template_idx].acts;
16769 : :
16770 [ # # ]: 0 : for (idx = 0; actions[idx].type != RTE_FLOW_ACTION_TYPE_END; ++idx) {
16771 : : const struct rte_flow_action *user_action = &actions[idx];
16772 : 0 : const struct rte_flow_action *tmpl_action = &at->orig_actions[idx];
16773 : :
16774 [ # # ]: 0 : if (user_action->type != tmpl_action->type)
16775 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
16776 : : user_action,
16777 : : "Action type does not match type specified in "
16778 : : "actions template");
16779 : : }
16780 : :
16781 : : /*
16782 : : * Only go through unmasked actions and check if configuration is provided.
16783 : : * Configuration of masked actions is ignored.
16784 : : */
16785 [ # # ]: 0 : LIST_FOREACH(act_data, &hw_acts->act_list, next) {
16786 : : const struct rte_flow_action *user_action;
16787 : :
16788 : 0 : user_action = &actions[act_data->action_src];
16789 : :
16790 : : /* Skip actions which do not require conf. */
16791 [ # # ]: 0 : switch ((int)act_data->type) {
16792 : 0 : case RTE_FLOW_ACTION_TYPE_COUNT:
16793 : : case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
16794 : : case MLX5_RTE_FLOW_ACTION_TYPE_METER_MARK:
16795 : : case MLX5_RTE_FLOW_ACTION_TYPE_RSS:
16796 : 0 : continue;
16797 : : default:
16798 : : break;
16799 : : }
16800 : :
16801 [ # # ]: 0 : if (user_action->conf == NULL)
16802 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
16803 : : user_action,
16804 : : "Action requires configuration");
16805 : :
16806 [ # # # # : 0 : switch ((int)user_action->type) {
# # ]
16807 : : enum rte_flow_action_type expected_type;
16808 : : const struct rte_flow_action_ethdev *ethdev;
16809 : : const struct rte_flow_action_modify_field *mf;
16810 : :
16811 : 0 : case RTE_FLOW_ACTION_TYPE_INDIRECT:
16812 : 0 : expected_type = act_data->indirect.expected_type;
16813 [ # # ]: 0 : if (!flow_hw_valid_indirect_action_type(user_action, expected_type))
16814 : 0 : return rte_flow_error_set(error, EINVAL,
16815 : : RTE_FLOW_ERROR_TYPE_ACTION_CONF,
16816 : : user_action,
16817 : : "Indirect action type does not match "
16818 : : "the type specified in the mask");
16819 : : break;
16820 : 0 : case RTE_FLOW_ACTION_TYPE_QUEUE:
16821 [ # # ]: 0 : if (mlx5_flow_validate_target_queue(dev, user_action, error))
16822 : 0 : return -rte_errno;
16823 : : break;
16824 : 0 : case RTE_FLOW_ACTION_TYPE_RSS:
16825 [ # # ]: 0 : if (mlx5_validate_action_rss(dev, user_action, error))
16826 : 0 : return -rte_errno;
16827 : : break;
16828 : 0 : case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
16829 : : /* TODO: Compare other fields if needed. */
16830 : : mf = user_action->conf;
16831 [ # # ]: 0 : if (mf->operation != act_data->modify_header.action.operation ||
16832 [ # # ]: 0 : mf->src.field != act_data->modify_header.action.src.field ||
16833 [ # # ]: 0 : mf->dst.field != act_data->modify_header.action.dst.field ||
16834 [ # # ]: 0 : mf->width != act_data->modify_header.action.width)
16835 : 0 : return rte_flow_error_set(error, EINVAL,
16836 : : RTE_FLOW_ERROR_TYPE_ACTION_CONF,
16837 : : user_action,
16838 : : "Modify field configuration does not "
16839 : : "match configuration from actions "
16840 : : "template");
16841 : : break;
16842 : 0 : case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
16843 : : ethdev = user_action->conf;
16844 [ # # ]: 0 : if (flow_hw_validate_target_port_id(dev, ethdev->port_id)) {
16845 : 0 : return rte_flow_error_set(error, EINVAL,
16846 : : RTE_FLOW_ERROR_TYPE_ACTION_CONF,
16847 : : user_action, "Invalid port");
16848 : : }
16849 : : break;
16850 : : default:
16851 : : break;
16852 : : }
16853 : : }
16854 : :
16855 : : return 0;
16856 : : }
16857 : :
16858 : : static int
16859 : 0 : flow_hw_async_op_validate(struct rte_eth_dev *dev,
16860 : : const uint32_t queue,
16861 : : const struct rte_flow_template_table *table,
16862 : : struct rte_flow_error *error)
16863 : : {
16864 : 0 : struct mlx5_priv *priv = dev->data->dev_private;
16865 : :
16866 : : MLX5_ASSERT(table != NULL);
16867 : :
16868 [ # # # # ]: 0 : if (table->cfg.external && queue >= priv->hw_attr->nb_queue)
16869 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
16870 : : "Incorrect queue");
16871 : :
16872 : : return 0;
16873 : : }
16874 : :
16875 : : /**
16876 : : * Validate user input for rte_flow_async_create() implementation.
16877 : : *
16878 : : * If RTE_LIBRTE_MLX5_DEBUG macro is not defined, this function is a no-op.
16879 : : *
16880 : : * @param[in] dev
16881 : : * Pointer to the rte_eth_dev structure.
16882 : : * @param[in] queue
16883 : : * The queue to create the flow.
16884 : : * @param[in] table
16885 : : * Pointer to template table.
16886 : : * @param[in] rule_index
16887 : : * The item pattern flow follows from the table.
16888 : : * @param[in] items
16889 : : * Items with flow spec value.
16890 : : * @param[in] pattern_template_index
16891 : : * The item pattern flow follows from the table.
16892 : : * @param[in] actions
16893 : : * Action with flow spec value.
16894 : : * @param[in] action_template_index
16895 : : * The action pattern flow follows from the table.
16896 : : * @param[out] error
16897 : : * Pointer to error structure.
16898 : : *
16899 : : * @return
16900 : : * 0 if user input is valid.
16901 : : * Negative errno otherwise, rte_errno and error struct is populated.
16902 : : */
16903 : : static int
16904 : 0 : flow_hw_async_create_validate(struct rte_eth_dev *dev,
16905 : : const uint32_t queue,
16906 : : const struct rte_flow_template_table *table,
16907 : : enum rte_flow_table_insertion_type insertion_type,
16908 : : uint32_t rule_index,
16909 : : const struct rte_flow_item items[],
16910 : : const uint8_t pattern_template_index,
16911 : : const struct rte_flow_action actions[],
16912 : : const uint8_t action_template_index,
16913 : : struct rte_flow_error *error)
16914 : : {
16915 [ # # ]: 0 : if (flow_hw_async_op_validate(dev, queue, table, error))
16916 : 0 : return -rte_errno;
16917 : :
16918 [ # # ]: 0 : if (insertion_type != table->cfg.attr.insertion_type)
16919 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
16920 : : NULL, "Flow rule insertion type mismatch with table configuration");
16921 : :
16922 [ # # ]: 0 : if (table->cfg.attr.insertion_type != RTE_FLOW_TABLE_INSERTION_TYPE_PATTERN)
16923 [ # # ]: 0 : if (rule_index >= table->cfg.attr.nb_flows)
16924 : 0 : return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
16925 : : NULL, "Flow rule index exceeds table size");
16926 : :
16927 [ # # ]: 0 : if (table->cfg.attr.insertion_type != RTE_FLOW_TABLE_INSERTION_TYPE_INDEX)
16928 [ # # ]: 0 : if (flow_hw_validate_rule_pattern(dev, table, pattern_template_index, items, error))
16929 : 0 : return -rte_errno;
16930 : :
16931 [ # # ]: 0 : if (flow_hw_validate_rule_actions(dev, table, action_template_index, actions, error))
16932 : 0 : return -rte_errno;
16933 : :
16934 : : return 0;
16935 : : }
16936 : :
16937 : : /**
16938 : : * Validate user input for rte_flow_async_update() implementation.
16939 : : *
16940 : : * If RTE_LIBRTE_MLX5_DEBUG macro is not defined, this function is a no-op.
16941 : : *
16942 : : * @param[in] dev
16943 : : * Pointer to the rte_eth_dev structure.
16944 : : * @param[in] queue
16945 : : * The queue to create the flow.
16946 : : * @param[in] flow
16947 : : * Flow rule to be updated.
16948 : : * @param[in] actions
16949 : : * Action with flow spec value.
16950 : : * @param[in] action_template_index
16951 : : * The action pattern flow follows from the table.
16952 : : * @param[out] error
16953 : : * Pointer to error structure.
16954 : : *
16955 : : * @return
16956 : : * 0 if user input is valid.
16957 : : * Negative errno otherwise, rte_errno and error struct is set.
16958 : : */
16959 : : static int
16960 : 0 : flow_hw_async_update_validate(struct rte_eth_dev *dev,
16961 : : const uint32_t queue,
16962 : : const struct rte_flow_hw *flow,
16963 : : const struct rte_flow_action actions[],
16964 : : const uint8_t action_template_index,
16965 : : struct rte_flow_error *error)
16966 : : {
16967 [ # # ]: 0 : if (flow_hw_async_op_validate(dev, queue, flow->table, error))
16968 : 0 : return -rte_errno;
16969 : :
16970 [ # # ]: 0 : if (flow_hw_validate_rule_actions(dev, flow->table, action_template_index, actions, error))
16971 : 0 : return -rte_errno;
16972 : :
16973 : : return 0;
16974 : : }
16975 : :
16976 : : /**
16977 : : * Validate user input for rte_flow_async_destroy() implementation.
16978 : : *
16979 : : * If RTE_LIBRTE_MLX5_DEBUG macro is not defined, this function is a no-op.
16980 : : *
16981 : : * @param[in] dev
16982 : : * Pointer to the rte_eth_dev structure.
16983 : : * @param[in] queue
16984 : : * The queue to create the flow.
16985 : : * @param[in] flow
16986 : : * Flow rule to be destroyed.
16987 : : * @param[out] error
16988 : : * Pointer to error structure.
16989 : : *
16990 : : * @return
16991 : : * 0 if user input is valid.
16992 : : * Negative errno otherwise, rte_errno and error struct is set.
16993 : : */
16994 : : static int
16995 : : flow_hw_async_destroy_validate(struct rte_eth_dev *dev,
16996 : : const uint32_t queue,
16997 : : const struct rte_flow_hw *flow,
16998 : : struct rte_flow_error *error)
16999 : : {
17000 : : if (flow_hw_async_op_validate(dev, queue, flow->table, error))
17001 : : return -rte_errno;
17002 : :
17003 : : return 0;
17004 : : }
17005 : :
17006 : : static struct rte_flow_fp_ops mlx5_flow_hw_fp_ops = {
17007 : : .async_create = flow_hw_async_flow_create,
17008 : : .async_create_by_index = flow_hw_async_flow_create_by_index,
17009 : : .async_create_by_index_with_pattern = flow_hw_async_flow_create_by_index_with_pattern,
17010 : : .async_actions_update = flow_hw_async_flow_update,
17011 : : .async_destroy = flow_hw_async_flow_destroy,
17012 : : .push = flow_hw_push,
17013 : : .pull = flow_hw_pull,
17014 : : .async_action_handle_create = flow_hw_action_handle_create,
17015 : : .async_action_handle_destroy = flow_hw_action_handle_destroy,
17016 : : .async_action_handle_update = flow_hw_action_handle_update,
17017 : : .async_action_handle_query = flow_hw_action_handle_query,
17018 : : .async_action_handle_query_update = flow_hw_async_action_handle_query_update,
17019 : : .async_action_list_handle_create = flow_hw_async_action_list_handle_create,
17020 : : .async_action_list_handle_destroy = flow_hw_async_action_list_handle_destroy,
17021 : : .async_action_list_handle_query_update =
17022 : : flow_hw_async_action_list_handle_query_update,
17023 : : };
17024 : :
17025 : : #endif
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