Branch data Line data Source code
1 : : /* SPDX-License-Identifier: BSD-3-Clause
2 : : * Copyright 2018 Mellanox Technologies, Ltd
3 : : */
4 : :
5 : : #include <unistd.h>
6 : :
7 : : #include <rte_errno.h>
8 : : #include <rte_malloc.h>
9 : : #include <rte_eal_paging.h>
10 : :
11 : : #include "mlx5_prm.h"
12 : : #include "mlx5_devx_cmds.h"
13 : : #include "mlx5_common_log.h"
14 : : #include "mlx5_malloc.h"
15 : :
16 : : /* FW writes status value to the OUT buffer at offset 00H */
17 : : #define MLX5_FW_STATUS(o) MLX5_GET(general_obj_out_cmd_hdr, (o), status)
18 : : /* FW writes syndrome value to the OUT buffer at offset 04H */
19 : : #define MLX5_FW_SYNDROME(o) MLX5_GET(general_obj_out_cmd_hdr, (o), syndrome)
20 : :
21 : : #define MLX5_DEVX_ERR_RC(x) ((x) > 0 ? -(x) : ((x) < 0 ? (x) : -1))
22 : :
23 : : #define DEVX_DRV_LOG(level, out, reason, param, value) \
24 : : do { \
25 : : /* \
26 : : * Some (old) GCC compilers like 7.5.0 and aarch64 GCC 7.1-2017.08 \
27 : : * do not expand correctly when the macro invoked when the `param` \
28 : : * is `NULL`. \
29 : : * Use `local_param` to avoid direct `NULL` expansion. \
30 : : */ \
31 : : const char *local_param = (const char *)param; \
32 : : \
33 : : rte_errno = errno; \
34 : : if (!local_param) { \
35 : : DRV_LOG(level, \
36 : : "DevX %s failed errno=%d status=%#x syndrome=%#x", \
37 : : (reason), errno, MLX5_FW_STATUS((out)), \
38 : : MLX5_FW_SYNDROME((out))); \
39 : : } else { \
40 : : DRV_LOG(level, \
41 : : "DevX %s %s=%#X failed errno=%d status=%#x syndrome=%#x",\
42 : : (reason), local_param, (value), errno, \
43 : : MLX5_FW_STATUS((out)), MLX5_FW_SYNDROME((out))); \
44 : : } \
45 : : } while (0)
46 : :
47 : : static void *
48 [ # # ]: 0 : mlx5_devx_get_hca_cap(void *ctx, uint32_t *in, uint32_t *out,
49 : : int *err, uint32_t flags)
50 : : {
51 : : const size_t size_in = MLX5_ST_SZ_DW(query_hca_cap_in) * sizeof(int);
52 : : const size_t size_out = MLX5_ST_SZ_DW(query_hca_cap_out) * sizeof(int);
53 : : int rc;
54 : :
55 : : memset(in, 0, size_in);
56 : : memset(out, 0, size_out);
57 [ # # ]: 0 : MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
58 [ # # ]: 0 : MLX5_SET(query_hca_cap_in, in, op_mod, flags);
59 : 0 : rc = mlx5_glue->devx_general_cmd(ctx, in, size_in, out, size_out);
60 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
61 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "HCA capabilities", "func", flags >> 1);
62 [ # # ]: 0 : if (err)
63 [ # # ]: 0 : *err = MLX5_DEVX_ERR_RC(rc);
64 : 0 : return NULL;
65 : : }
66 [ # # ]: 0 : if (err)
67 : 0 : *err = 0;
68 : 0 : return MLX5_ADDR_OF(query_hca_cap_out, out, capability);
69 : : }
70 : :
71 : : /**
72 : : * Perform read access to the registers. Reads data from register
73 : : * and writes ones to the specified buffer.
74 : : *
75 : : * @param[in] ctx
76 : : * Context returned from mlx5 open_device() glue function.
77 : : * @param[in] reg_id
78 : : * Register identifier according to the PRM.
79 : : * @param[in] arg
80 : : * Register access auxiliary parameter according to the PRM.
81 : : * @param[out] data
82 : : * Pointer to the buffer to store read data.
83 : : * @param[in] dw_cnt
84 : : * Buffer size in double words.
85 : : *
86 : : * @return
87 : : * 0 on success, a negative value otherwise.
88 : : */
89 : : int
90 : 0 : mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg,
91 : : uint32_t *data, uint32_t dw_cnt)
92 : : {
93 : 0 : uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0};
94 : 0 : uint32_t out[MLX5_ST_SZ_DW(access_register_out) +
95 : : MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0};
96 : : int rc;
97 : :
98 : : MLX5_ASSERT(data && dw_cnt);
99 : : MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX);
100 [ # # ]: 0 : if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) {
101 : 0 : DRV_LOG(ERR, "Not enough buffer for register read data");
102 : 0 : return -1;
103 : : }
104 : 0 : MLX5_SET(access_register_in, in, opcode,
105 : : MLX5_CMD_OP_ACCESS_REGISTER_USER);
106 : 0 : MLX5_SET(access_register_in, in, op_mod,
107 : : MLX5_ACCESS_REGISTER_IN_OP_MOD_READ);
108 : 0 : MLX5_SET(access_register_in, in, register_id, reg_id);
109 : 0 : MLX5_SET(access_register_in, in, argument, arg);
110 : 0 : rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,
111 : 0 : MLX5_ST_SZ_BYTES(access_register_out) +
112 : : sizeof(uint32_t) * dw_cnt);
113 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
114 [ # # # # ]: 0 : DEVX_DRV_LOG(DEBUG, out, "read access", "NIC register", reg_id);
115 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
116 : : }
117 : 0 : memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)],
118 : : dw_cnt * sizeof(uint32_t));
119 : 0 : return 0;
120 : : }
121 : :
122 : : /**
123 : : * Perform write access to the registers.
124 : : *
125 : : * @param[in] ctx
126 : : * Context returned from mlx5 open_device() glue function.
127 : : * @param[in] reg_id
128 : : * Register identifier according to the PRM.
129 : : * @param[in] arg
130 : : * Register access auxiliary parameter according to the PRM.
131 : : * @param[out] data
132 : : * Pointer to the buffer containing data to write.
133 : : * @param[in] dw_cnt
134 : : * Buffer size in double words (32bit units).
135 : : *
136 : : * @return
137 : : * 0 on success, a negative value otherwise.
138 : : */
139 : : int
140 : 0 : mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, uint32_t arg,
141 : : uint32_t *data, uint32_t dw_cnt)
142 : : {
143 : 0 : uint32_t in[MLX5_ST_SZ_DW(access_register_in) +
144 : : MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0};
145 : 0 : uint32_t out[MLX5_ST_SZ_DW(access_register_out)] = {0};
146 : : int rc;
147 : : void *ptr;
148 : :
149 : : MLX5_ASSERT(data && dw_cnt);
150 : : MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX);
151 [ # # ]: 0 : if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) {
152 : 0 : DRV_LOG(ERR, "Data to write exceeds max size");
153 : 0 : return -1;
154 : : }
155 : 0 : MLX5_SET(access_register_in, in, opcode,
156 : : MLX5_CMD_OP_ACCESS_REGISTER_USER);
157 : 0 : MLX5_SET(access_register_in, in, op_mod,
158 : : MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE);
159 : 0 : MLX5_SET(access_register_in, in, register_id, reg_id);
160 : 0 : MLX5_SET(access_register_in, in, argument, arg);
161 : : ptr = MLX5_ADDR_OF(access_register_in, in, register_data);
162 : 0 : memcpy(ptr, data, dw_cnt * sizeof(uint32_t));
163 : 0 : rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
164 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
165 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "write access", "NIC register", reg_id);
166 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
167 : : }
168 : 0 : rc = mlx5_glue->devx_general_cmd(ctx, in,
169 : 0 : MLX5_ST_SZ_BYTES(access_register_in) +
170 : : dw_cnt * sizeof(uint32_t),
171 : : out, sizeof(out));
172 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
173 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "write access", "NIC register", reg_id);
174 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
175 : : }
176 : : return 0;
177 : : }
178 : :
179 : : struct mlx5_devx_obj *
180 : 0 : mlx5_devx_cmd_flow_counter_alloc_general(void *ctx,
181 : : struct mlx5_devx_counter_attr *attr)
182 : : {
183 : 0 : struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs),
184 : : 0, SOCKET_ID_ANY);
185 : 0 : uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0};
186 : 0 : uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0};
187 : :
188 [ # # ]: 0 : if (!dcs) {
189 : 0 : rte_errno = ENOMEM;
190 : 0 : return NULL;
191 : : }
192 : 0 : MLX5_SET(alloc_flow_counter_in, in, opcode,
193 : : MLX5_CMD_OP_ALLOC_FLOW_COUNTER);
194 [ # # ]: 0 : if (attr->bulk_log_max_alloc)
195 : 0 : MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk_log_size,
196 : : attr->flow_counter_bulk_log_size);
197 : : else
198 : 0 : MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk,
199 : : attr->bulk_n_128);
200 [ # # ]: 0 : if (attr->pd_valid)
201 : 0 : MLX5_SET(alloc_flow_counter_in, in, pd, attr->pd);
202 : 0 : dcs->obj = mlx5_glue->devx_obj_create(ctx, in,
203 : : sizeof(in), out, sizeof(out));
204 [ # # ]: 0 : if (!dcs->obj) {
205 : 0 : DRV_LOG(ERR, "Can't allocate counters - error %d", errno);
206 : 0 : rte_errno = errno;
207 : 0 : mlx5_free(dcs);
208 : 0 : return NULL;
209 : : }
210 [ # # ]: 0 : dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id);
211 : 0 : return dcs;
212 : : }
213 : :
214 : : /**
215 : : * Allocate flow counters via devx interface.
216 : : *
217 : : * @param[in] ctx
218 : : * Context returned from mlx5 open_device() glue function.
219 : : * @param dcs
220 : : * Pointer to counters properties structure to be filled by the routine.
221 : : * @param bulk_n_128
222 : : * Bulk counter numbers in 128 counters units.
223 : : *
224 : : * @return
225 : : * Pointer to counter object on success, a negative value otherwise and
226 : : * rte_errno is set.
227 : : */
228 : : struct mlx5_devx_obj *
229 : 0 : mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128)
230 : : {
231 : 0 : struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs),
232 : : 0, SOCKET_ID_ANY);
233 : 0 : uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0};
234 : 0 : uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0};
235 : :
236 [ # # ]: 0 : if (!dcs) {
237 : 0 : rte_errno = ENOMEM;
238 : 0 : return NULL;
239 : : }
240 : 0 : MLX5_SET(alloc_flow_counter_in, in, opcode,
241 : : MLX5_CMD_OP_ALLOC_FLOW_COUNTER);
242 : 0 : MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128);
243 : 0 : dcs->obj = mlx5_glue->devx_obj_create(ctx, in,
244 : : sizeof(in), out, sizeof(out));
245 [ # # ]: 0 : if (!dcs->obj) {
246 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "allocate counters", NULL, 0);
247 : 0 : mlx5_free(dcs);
248 : 0 : return NULL;
249 : : }
250 [ # # ]: 0 : dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id);
251 : 0 : return dcs;
252 : : }
253 : :
254 : : /**
255 : : * Query flow counters values.
256 : : *
257 : : * @param[in] dcs
258 : : * devx object that was obtained from mlx5_devx_cmd_fc_alloc.
259 : : * @param[in] clear
260 : : * Whether hardware should clear the counters after the query or not.
261 : : * @param[in] n_counters
262 : : * 0 in case of 1 counter to read, otherwise the counter number to read.
263 : : * @param pkts
264 : : * The number of packets that matched the flow.
265 : : * @param bytes
266 : : * The number of bytes that matched the flow.
267 : : * @param mkey
268 : : * The mkey key for batch query.
269 : : * @param addr
270 : : * The address in the mkey range for batch query.
271 : : * @param cmd_comp
272 : : * The completion object for asynchronous batch query.
273 : : * @param async_id
274 : : * The ID to be returned in the asynchronous batch query response.
275 : : *
276 : : * @return
277 : : * 0 on success, a negative value otherwise.
278 : : */
279 : : int
280 : 0 : mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
281 : : int clear, uint32_t n_counters,
282 : : uint64_t *pkts, uint64_t *bytes,
283 : : uint32_t mkey, void *addr,
284 : : void *cmd_comp,
285 : : uint64_t async_id)
286 : : {
287 : : uint32_t out[MLX5_ST_SZ_BYTES(query_flow_counter_out) + MLX5_ST_SZ_BYTES(traffic_counter)];
288 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0};
289 : : const int out_len = RTE_DIM(out);
290 : : void *stats;
291 : : int rc;
292 : :
293 : 0 : MLX5_SET(query_flow_counter_in, in, opcode,
294 : : MLX5_CMD_OP_QUERY_FLOW_COUNTER);
295 : 0 : MLX5_SET(query_flow_counter_in, in, op_mod, 0);
296 : 0 : MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id);
297 : 0 : MLX5_SET(query_flow_counter_in, in, clear, !!clear);
298 : :
299 [ # # ]: 0 : if (n_counters) {
300 [ # # ]: 0 : MLX5_SET(query_flow_counter_in, in, num_of_counters,
301 : : n_counters);
302 [ # # ]: 0 : MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1);
303 : 0 : MLX5_SET(query_flow_counter_in, in, mkey, mkey);
304 : 0 : MLX5_SET64(query_flow_counter_in, in, address,
305 : : (uint64_t)(uintptr_t)addr);
306 : : }
307 [ # # ]: 0 : if (!cmd_comp)
308 : 0 : rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
309 : : out_len);
310 : : else
311 : 0 : rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in),
312 : : out_len, async_id,
313 : : cmd_comp);
314 [ # # ]: 0 : if (rc) {
315 : 0 : DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc);
316 : 0 : rte_errno = rc;
317 : 0 : return -rc;
318 : : }
319 [ # # ]: 0 : if (!n_counters) {
320 : : stats = MLX5_ADDR_OF(query_flow_counter_out,
321 : : out, flow_statistics);
322 [ # # ]: 0 : *pkts = MLX5_GET64(traffic_counter, stats, packets);
323 [ # # ]: 0 : *bytes = MLX5_GET64(traffic_counter, stats, octets);
324 : : }
325 : : return 0;
326 : : }
327 : :
328 : : /**
329 : : * Create a new mkey.
330 : : *
331 : : * @param[in] ctx
332 : : * Context returned from mlx5 open_device() glue function.
333 : : * @param[in] attr
334 : : * Attributes of the requested mkey.
335 : : *
336 : : * @return
337 : : * Pointer to Devx mkey on success, a negative value otherwise and rte_errno
338 : : * is set.
339 : : */
340 : : struct mlx5_devx_obj *
341 : 0 : mlx5_devx_cmd_mkey_create(void *ctx,
342 : : struct mlx5_devx_mkey_attr *attr)
343 : : {
344 : 0 : struct mlx5_klm *klm_array = attr->klm_array;
345 : 0 : int klm_num = attr->klm_num;
346 [ # # ]: 0 : int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) +
347 : 0 : (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm);
348 : 0 : uint32_t *in = alloca(sizeof(uint32_t) * in_size_dw);
349 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0};
350 : : void *mkc;
351 : 0 : struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey),
352 : : 0, SOCKET_ID_ANY);
353 : : size_t pgsize;
354 : : uint32_t translation_size;
355 : :
356 [ # # ]: 0 : if (!mkey) {
357 : 0 : rte_errno = ENOMEM;
358 : 0 : return NULL;
359 : : }
360 : : memset(in, 0, in_size_dw * 4);
361 : 0 : pgsize = rte_mem_page_size();
362 [ # # ]: 0 : if (pgsize == (size_t)-1) {
363 : 0 : mlx5_free(mkey);
364 : 0 : DRV_LOG(ERR, "Failed to get page size");
365 : 0 : rte_errno = ENOMEM;
366 : 0 : return NULL;
367 : : }
368 [ # # ]: 0 : MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY);
369 : : mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
370 [ # # ]: 0 : if (klm_num > 0) {
371 : : int i;
372 : 0 : uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in,
373 : : klm_pas_mtt);
374 : 0 : translation_size = RTE_ALIGN(klm_num, 4);
375 [ # # ]: 0 : for (i = 0; i < klm_num; i++) {
376 [ # # ]: 0 : MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count);
377 [ # # ]: 0 : MLX5_SET(klm, klm, mkey, klm_array[i].mkey);
378 [ # # ]: 0 : MLX5_SET64(klm, klm, address, klm_array[i].address);
379 : 0 : klm += MLX5_ST_SZ_BYTES(klm);
380 : : }
381 [ # # ]: 0 : for (; i < (int)translation_size; i++) {
382 [ # # ]: 0 : MLX5_SET(klm, klm, mkey, 0x0);
383 : 0 : MLX5_SET64(klm, klm, address, 0x0);
384 : 0 : klm += MLX5_ST_SZ_BYTES(klm);
385 : : }
386 [ # # # # ]: 0 : MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ?
387 : : MLX5_MKC_ACCESS_MODE_KLM_FBS :
388 : : MLX5_MKC_ACCESS_MODE_KLM);
389 [ # # ]: 0 : MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size);
390 : : } else {
391 : 0 : translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16;
392 [ # # ]: 0 : MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
393 [ # # # # ]: 0 : MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize));
394 : : }
395 [ # # ]: 0 : MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
396 : : translation_size);
397 [ # # ]: 0 : MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id);
398 [ # # ]: 0 : MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access);
399 [ # # ]: 0 : MLX5_SET(mkc, mkc, lw, 0x1);
400 [ # # ]: 0 : MLX5_SET(mkc, mkc, lr, 0x1);
401 [ # # ]: 0 : if (attr->set_remote_rw) {
402 [ # # ]: 0 : MLX5_SET(mkc, mkc, rw, 0x1);
403 [ # # ]: 0 : MLX5_SET(mkc, mkc, rr, 0x1);
404 : : }
405 [ # # ]: 0 : MLX5_SET(mkc, mkc, qpn, 0xffffff);
406 [ # # ]: 0 : MLX5_SET(mkc, mkc, pd, attr->pd);
407 [ # # ]: 0 : MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF);
408 [ # # ]: 0 : MLX5_SET(mkc, mkc, umr_en, attr->umr_en);
409 [ # # ]: 0 : MLX5_SET(mkc, mkc, translations_octword_size, translation_size);
410 [ # # ]: 0 : MLX5_SET(mkc, mkc, relaxed_ordering_write,
411 : : attr->relaxed_ordering_write);
412 [ # # ]: 0 : MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read);
413 [ # # ]: 0 : MLX5_SET64(mkc, mkc, start_addr, attr->addr);
414 [ # # ]: 0 : MLX5_SET64(mkc, mkc, len, attr->size);
415 [ # # ]: 0 : MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en);
416 [ # # ]: 0 : if (attr->crypto_en) {
417 [ # # ]: 0 : MLX5_SET(mkc, mkc, bsf_en, attr->crypto_en);
418 [ # # ]: 0 : MLX5_SET(mkc, mkc, bsf_octword_size, 4);
419 : : }
420 : 0 : mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out,
421 : : sizeof(out));
422 [ # # ]: 0 : if (!mkey->obj) {
423 [ # # # # : 0 : DEVX_DRV_LOG(ERR, out, klm_num ? "create indirect mkey"
# # ]
424 : : : "create direct key", NULL, 0);
425 : 0 : mlx5_free(mkey);
426 : 0 : return NULL;
427 : : }
428 [ # # ]: 0 : mkey->id = MLX5_GET(create_mkey_out, out, mkey_index);
429 : 0 : mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF);
430 : 0 : return mkey;
431 : : }
432 : :
433 : : /**
434 : : * Get status of devx command response.
435 : : * Mainly used for asynchronous commands.
436 : : *
437 : : * @param[in] out
438 : : * The out response buffer.
439 : : *
440 : : * @return
441 : : * 0 on success, non-zero value otherwise.
442 : : */
443 : : int
444 : 0 : mlx5_devx_get_out_command_status(void *out)
445 : : {
446 : : int status;
447 : :
448 [ # # ]: 0 : if (!out)
449 : : return -EINVAL;
450 [ # # ]: 0 : status = MLX5_GET(query_flow_counter_out, out, status);
451 [ # # ]: 0 : if (status) {
452 [ # # ]: 0 : int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome);
453 : :
454 : 0 : DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status,
455 : : syndrome);
456 : : }
457 : : return status;
458 : : }
459 : :
460 : : /**
461 : : * Destroy any object allocated by a Devx API.
462 : : *
463 : : * @param[in] obj
464 : : * Pointer to a general object.
465 : : *
466 : : * @return
467 : : * 0 on success, a negative value otherwise.
468 : : */
469 : : int
470 : 0 : mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj)
471 : : {
472 : : int ret;
473 : :
474 [ # # ]: 0 : if (!obj)
475 : : return 0;
476 : 0 : ret = mlx5_glue->devx_obj_destroy(obj->obj);
477 : 0 : mlx5_free(obj);
478 : 0 : return ret;
479 : : }
480 : :
481 : : /**
482 : : * Query NIC vport context.
483 : : * Fills minimal inline attribute.
484 : : *
485 : : * @param[in] ctx
486 : : * ibv contexts returned from mlx5dv_open_device.
487 : : * @param[in] vport
488 : : * vport index
489 : : * @param[out] attr
490 : : * Attributes device values.
491 : : *
492 : : * @return
493 : : * 0 on success, a negative value otherwise.
494 : : */
495 : : static int
496 : 0 : mlx5_devx_cmd_query_nic_vport_context(void *ctx,
497 : : unsigned int vport,
498 : : struct mlx5_hca_attr *attr)
499 : : {
500 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0};
501 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0};
502 : : void *vctx;
503 : : int rc;
504 : :
505 : : /* Query NIC vport context to determine inline mode. */
506 : 0 : MLX5_SET(query_nic_vport_context_in, in, opcode,
507 : : MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT);
508 : 0 : MLX5_SET(query_nic_vport_context_in, in, vport_number, vport);
509 [ # # ]: 0 : if (vport)
510 [ # # ]: 0 : MLX5_SET(query_nic_vport_context_in, in, other_vport, 1);
511 : 0 : rc = mlx5_glue->devx_general_cmd(ctx,
512 : : in, sizeof(in),
513 : : out, sizeof(out));
514 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
515 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "query NIC vport context", NULL, 0);
516 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
517 : : }
518 : : vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out,
519 : : nic_vport_context);
520 [ # # ]: 0 : if (attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
521 [ # # ]: 0 : attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx,
522 : : min_wqe_inline_mode);
523 [ # # ]: 0 : attr->system_image_guid = MLX5_GET64(nic_vport_context, vctx,
524 : : system_image_guid);
525 : 0 : return 0;
526 : : }
527 : :
528 : : /**
529 : : * Query NIC vDPA attributes.
530 : : *
531 : : * @param[in] ctx
532 : : * Context returned from mlx5 open_device() glue function.
533 : : * @param[out] vdpa_attr
534 : : * vDPA Attributes structure to fill.
535 : : */
536 : : static void
537 : 0 : mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx,
538 : : struct mlx5_hca_vdpa_attr *vdpa_attr)
539 : : {
540 : : uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)];
541 : : uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)];
542 : : void *hcattr;
543 : :
544 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, NULL,
545 : : MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION |
546 : : MLX5_HCA_CAP_OPMOD_GET_CUR);
547 [ # # ]: 0 : if (!hcattr) {
548 : 0 : DRV_LOG(DEBUG, "Failed to query devx VDPA capabilities");
549 : 0 : vdpa_attr->valid = 0;
550 : : } else {
551 : 0 : vdpa_attr->valid = 1;
552 : 0 : vdpa_attr->desc_tunnel_offload_type =
553 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
554 : : desc_tunnel_offload_type);
555 : 0 : vdpa_attr->eth_frame_offload_type =
556 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
557 : : eth_frame_offload_type);
558 : 0 : vdpa_attr->virtio_version_1_0 =
559 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
560 : : virtio_version_1_0);
561 [ # # ]: 0 : vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr,
562 : : tso_ipv4);
563 [ # # ]: 0 : vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr,
564 : : tso_ipv6);
565 [ # # ]: 0 : vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
566 : : tx_csum);
567 [ # # ]: 0 : vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
568 : : rx_csum);
569 [ # # ]: 0 : vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr,
570 : : event_mode);
571 : 0 : vdpa_attr->virtio_queue_type =
572 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
573 : : virtio_queue_type);
574 : 0 : vdpa_attr->log_doorbell_stride =
575 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
576 : : log_doorbell_stride);
577 : 0 : vdpa_attr->vnet_modify_ext =
578 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
579 : : vnet_modify_ext);
580 : 0 : vdpa_attr->virtio_net_q_addr_modify =
581 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
582 : : virtio_net_q_addr_modify);
583 : 0 : vdpa_attr->virtio_q_index_modify =
584 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
585 : : virtio_q_index_modify);
586 : 0 : vdpa_attr->log_doorbell_bar_size =
587 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
588 : : log_doorbell_bar_size);
589 : 0 : vdpa_attr->doorbell_bar_offset =
590 [ # # ]: 0 : MLX5_GET64(virtio_emulation_cap, hcattr,
591 : : doorbell_bar_offset);
592 : 0 : vdpa_attr->max_num_virtio_queues =
593 [ # # ]: 0 : MLX5_GET(virtio_emulation_cap, hcattr,
594 : : max_num_virtio_queues);
595 [ # # ]: 0 : vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr,
596 : : umem_1_buffer_param_a);
597 [ # # ]: 0 : vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr,
598 : : umem_1_buffer_param_b);
599 [ # # ]: 0 : vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr,
600 : : umem_2_buffer_param_a);
601 [ # # ]: 0 : vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr,
602 : : umem_2_buffer_param_b);
603 [ # # ]: 0 : vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr,
604 : : umem_3_buffer_param_a);
605 [ # # ]: 0 : vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr,
606 : : umem_3_buffer_param_b);
607 : : }
608 : 0 : }
609 : :
610 : : /**
611 : : * Query match sample handle parameters.
612 : : *
613 : : * This command allows translating a field sample handle returned by either
614 : : * PARSE_GRAPH_FLOW_MATCH_SAMPLE or by GENEVE TLV OPTION object into values
615 : : * used for header modification or header matching/hashing.
616 : : *
617 : : * @param[in] ctx
618 : : * Context used to create either GENEVE TLV option or FLEX PARSE GRAPH object.
619 : : * @param[in] sample_field_id
620 : : * Field sample handle returned by either PARSE_GRAPH_FLOW_MATCH_SAMPLE
621 : : * or by GENEVE TLV OPTION object.
622 : : * @param[out] attr
623 : : * Pointer to match sample info attributes structure.
624 : : *
625 : : * @return
626 : : * 0 on success, a negative errno otherwise and rte_errno is set.
627 : : */
628 : : int
629 : 0 : mlx5_devx_cmd_match_sample_info_query(void *ctx, uint32_t sample_field_id,
630 : : struct mlx5_devx_match_sample_info_query_attr *attr)
631 : : {
632 : : #ifdef HAVE_IBV_FLOW_DV_SUPPORT
633 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_match_sample_info_out)] = {0};
634 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_match_sample_info_in)] = {0};
635 : : int rc;
636 : :
637 : 0 : MLX5_SET(query_match_sample_info_in, in, opcode,
638 : : MLX5_CMD_OP_QUERY_MATCH_SAMPLE_INFO);
639 : 0 : MLX5_SET(query_match_sample_info_in, in, op_mod, 0);
640 : 0 : MLX5_SET(query_match_sample_info_in, in, sample_field_id,
641 : : sample_field_id);
642 : 0 : rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
643 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
644 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "query match sample info",
645 : : "sample_field_id", sample_field_id);
646 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
647 : : }
648 [ # # ]: 0 : attr->modify_field_id = MLX5_GET(query_match_sample_info_out, out,
649 : : modify_field_id);
650 [ # # ]: 0 : attr->sample_dw_data = MLX5_GET(query_match_sample_info_out, out,
651 : : field_format_select_dw);
652 [ # # ]: 0 : attr->sample_dw_ok_bit = MLX5_GET(query_match_sample_info_out, out,
653 : : ok_bit_format_select_dw);
654 [ # # ]: 0 : attr->sample_dw_ok_bit_offset = MLX5_GET(query_match_sample_info_out,
655 : : out, ok_bit_offset);
656 : 0 : return 0;
657 : : #else
658 : : (void)ctx;
659 : : (void)sample_field_id;
660 : : (void)attr;
661 : : return -ENOTSUP;
662 : : #endif
663 : : }
664 : :
665 : : int
666 : 0 : mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,
667 : : uint32_t *ids,
668 : : uint32_t num, uint8_t *anchor)
669 : : {
670 : 0 : uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
671 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0};
672 : : void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr);
673 : : void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex);
674 : : void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
675 : : int ret;
676 : : uint32_t idx = 0;
677 : : uint32_t i;
678 : :
679 [ # # ]: 0 : if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) {
680 : 0 : rte_errno = EINVAL;
681 : 0 : DRV_LOG(ERR, "Too many sample IDs to be fetched.");
682 : 0 : return -rte_errno;
683 : : }
684 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
685 : : MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
686 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
687 : : MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
688 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id);
689 : 0 : ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in),
690 : : out, sizeof(out));
691 [ # # ]: 0 : if (ret) {
692 : 0 : rte_errno = ret;
693 : 0 : DRV_LOG(ERR, "Failed to query sample IDs with object %p.",
694 : : (void *)flex_obj);
695 : 0 : return -rte_errno;
696 : : }
697 [ # # ]: 0 : if (anchor)
698 [ # # ]: 0 : *anchor = MLX5_GET(parse_graph_flex, flex, head_anchor_id);
699 [ # # ]: 0 : for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM && idx < num; i++) {
700 : 0 : void *s_off = (void *)((char *)sample + i *
701 : : MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
702 : : uint32_t en;
703 : :
704 [ # # ]: 0 : en = MLX5_GET(parse_graph_flow_match_sample, s_off,
705 : : flow_match_sample_en);
706 [ # # ]: 0 : if (!en)
707 : 0 : continue;
708 [ # # ]: 0 : ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off,
709 : : flow_match_sample_field_id);
710 : : }
711 [ # # ]: 0 : if (num != idx) {
712 : 0 : rte_errno = EINVAL;
713 : 0 : DRV_LOG(ERR, "Number of sample IDs are not as expected.");
714 : 0 : return -rte_errno;
715 : : }
716 : : return ret;
717 : : }
718 : :
719 : : struct mlx5_devx_obj *
720 : 0 : mlx5_devx_cmd_create_flex_parser(void *ctx,
721 : : struct mlx5_devx_graph_node_attr *data)
722 : : {
723 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0};
724 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
725 : : void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr);
726 : : void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex);
727 : : void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
728 : : void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc);
729 : : void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc);
730 : 0 : struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc
731 : : (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY);
732 : : uint32_t i;
733 : :
734 [ # # ]: 0 : if (!parse_flex_obj) {
735 : 0 : DRV_LOG(ERR, "Failed to allocate flex parser data.");
736 : 0 : rte_errno = ENOMEM;
737 : 0 : return NULL;
738 : : }
739 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
740 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
741 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
742 : : MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
743 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, header_length_mode,
744 : : data->header_length_mode);
745 [ # # ]: 0 : MLX5_SET64(parse_graph_flex, flex, modify_field_select,
746 : : data->modify_field_select);
747 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, header_length_base_value,
748 : : data->header_length_base_value);
749 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, header_length_field_offset,
750 : : data->header_length_field_offset);
751 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, header_length_field_shift,
752 : : data->header_length_field_shift);
753 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, next_header_field_offset,
754 : : data->next_header_field_offset);
755 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, next_header_field_size,
756 : : data->next_header_field_size);
757 [ # # ]: 0 : MLX5_SET(parse_graph_flex, flex, header_length_field_mask,
758 : : data->header_length_field_mask);
759 [ # # ]: 0 : for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {
760 : : struct mlx5_devx_match_sample_attr *s = &data->sample[i];
761 : 0 : void *s_off = (void *)((char *)sample + i *
762 : : MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
763 : :
764 [ # # ]: 0 : if (!s->flow_match_sample_en)
765 : 0 : continue;
766 [ # # ]: 0 : MLX5_SET(parse_graph_flow_match_sample, s_off,
767 : : flow_match_sample_en, !!s->flow_match_sample_en);
768 [ # # ]: 0 : MLX5_SET(parse_graph_flow_match_sample, s_off,
769 : : flow_match_sample_field_offset,
770 : : s->flow_match_sample_field_offset);
771 [ # # ]: 0 : MLX5_SET(parse_graph_flow_match_sample, s_off,
772 : : flow_match_sample_offset_mode,
773 : : s->flow_match_sample_offset_mode);
774 [ # # ]: 0 : MLX5_SET(parse_graph_flow_match_sample, s_off,
775 : : flow_match_sample_field_offset_mask,
776 : : s->flow_match_sample_field_offset_mask);
777 [ # # ]: 0 : MLX5_SET(parse_graph_flow_match_sample, s_off,
778 : : flow_match_sample_field_offset_shift,
779 : : s->flow_match_sample_field_offset_shift);
780 [ # # ]: 0 : MLX5_SET(parse_graph_flow_match_sample, s_off,
781 : : flow_match_sample_field_base_offset,
782 : : s->flow_match_sample_field_base_offset);
783 [ # # ]: 0 : MLX5_SET(parse_graph_flow_match_sample, s_off,
784 : : flow_match_sample_tunnel_mode,
785 : : s->flow_match_sample_tunnel_mode);
786 : : }
787 [ # # ]: 0 : for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) {
788 : : struct mlx5_devx_graph_arc_attr *ia = &data->in[i];
789 : : struct mlx5_devx_graph_arc_attr *oa = &data->out[i];
790 : 0 : void *in_off = (void *)((char *)in_arc + i *
791 : : MLX5_ST_SZ_BYTES(parse_graph_arc));
792 : 0 : void *out_off = (void *)((char *)out_arc + i *
793 : : MLX5_ST_SZ_BYTES(parse_graph_arc));
794 : :
795 [ # # ]: 0 : if (ia->arc_parse_graph_node != 0) {
796 [ # # ]: 0 : MLX5_SET(parse_graph_arc, in_off,
797 : : compare_condition_value,
798 : : ia->compare_condition_value);
799 [ # # ]: 0 : MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel,
800 : : ia->start_inner_tunnel);
801 [ # # ]: 0 : MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node,
802 : : ia->arc_parse_graph_node);
803 [ # # ]: 0 : MLX5_SET(parse_graph_arc, in_off,
804 : : parse_graph_node_handle,
805 : : ia->parse_graph_node_handle);
806 : : }
807 [ # # ]: 0 : if (oa->arc_parse_graph_node != 0) {
808 [ # # ]: 0 : MLX5_SET(parse_graph_arc, out_off,
809 : : compare_condition_value,
810 : : oa->compare_condition_value);
811 [ # # ]: 0 : MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel,
812 : : oa->start_inner_tunnel);
813 [ # # ]: 0 : MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node,
814 : : oa->arc_parse_graph_node);
815 [ # # ]: 0 : MLX5_SET(parse_graph_arc, out_off,
816 : : parse_graph_node_handle,
817 : : oa->parse_graph_node_handle);
818 : : }
819 : : }
820 : 0 : parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
821 : : out, sizeof(out));
822 [ # # ]: 0 : if (!parse_flex_obj->obj) {
823 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create FLEX PARSE GRAPH", NULL, 0);
824 : 0 : mlx5_free(parse_flex_obj);
825 : 0 : return NULL;
826 : : }
827 [ # # ]: 0 : parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
828 : 0 : return parse_flex_obj;
829 : : }
830 : :
831 : : static int
832 : 0 : mlx5_devx_cmd_query_hca_parse_graph_node_cap
833 : : (void *ctx, struct mlx5_hca_flex_attr *attr)
834 : : {
835 : : uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)];
836 : : uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)];
837 : : void *hcattr;
838 : : int rc;
839 : :
840 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
841 : : MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP |
842 : : MLX5_HCA_CAP_OPMOD_GET_CUR);
843 [ # # ]: 0 : if (!hcattr)
844 : 0 : return rc;
845 [ # # ]: 0 : attr->node_in = MLX5_GET(parse_graph_node_cap, hcattr, node_in);
846 [ # # ]: 0 : attr->node_out = MLX5_GET(parse_graph_node_cap, hcattr, node_out);
847 [ # # ]: 0 : attr->header_length_mode = MLX5_GET(parse_graph_node_cap, hcattr,
848 : : header_length_mode);
849 [ # # ]: 0 : attr->sample_offset_mode = MLX5_GET(parse_graph_node_cap, hcattr,
850 : : sample_offset_mode);
851 [ # # ]: 0 : attr->max_num_arc_in = MLX5_GET(parse_graph_node_cap, hcattr,
852 : : max_num_arc_in);
853 [ # # ]: 0 : attr->max_num_arc_out = MLX5_GET(parse_graph_node_cap, hcattr,
854 : : max_num_arc_out);
855 [ # # ]: 0 : attr->max_num_sample = MLX5_GET(parse_graph_node_cap, hcattr,
856 : : max_num_sample);
857 [ # # ]: 0 : attr->parse_graph_anchor = MLX5_GET(parse_graph_node_cap, hcattr, parse_graph_anchor);
858 [ # # ]: 0 : attr->sample_tunnel_inner2 = MLX5_GET(parse_graph_node_cap, hcattr,
859 : : sample_tunnel_inner2);
860 [ # # ]: 0 : attr->zero_size_supported = MLX5_GET(parse_graph_node_cap, hcattr,
861 : : zero_size_supported);
862 [ # # ]: 0 : attr->sample_id_in_out = MLX5_GET(parse_graph_node_cap, hcattr,
863 : : sample_id_in_out);
864 [ # # ]: 0 : attr->max_base_header_length = MLX5_GET(parse_graph_node_cap, hcattr,
865 : : max_base_header_length);
866 [ # # ]: 0 : attr->max_sample_base_offset = MLX5_GET(parse_graph_node_cap, hcattr,
867 : : max_sample_base_offset);
868 [ # # ]: 0 : attr->max_next_header_offset = MLX5_GET(parse_graph_node_cap, hcattr,
869 : : max_next_header_offset);
870 [ # # ]: 0 : attr->header_length_mask_width = MLX5_GET(parse_graph_node_cap, hcattr,
871 : : header_length_mask_width);
872 : : /* Get the max supported samples from HCA CAP 2 */
873 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
874 : : MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 |
875 : : MLX5_HCA_CAP_OPMOD_GET_CUR);
876 [ # # ]: 0 : if (!hcattr)
877 : 0 : return rc;
878 : 0 : attr->max_num_prog_sample =
879 [ # # ]: 0 : MLX5_GET(cmd_hca_cap_2, hcattr, max_num_prog_sample_field);
880 : 0 : return 0;
881 : : }
882 : :
883 : : static int
884 : 0 : mlx5_devx_query_pkt_integrity_match(void *hcattr)
885 : : {
886 [ # # ]: 0 : return MLX5_GET(flow_table_nic_cap, hcattr,
887 [ # # # # ]: 0 : ft_field_support_2_nic_receive.inner_l3_ok) &&
888 : : MLX5_GET(flow_table_nic_cap, hcattr,
889 [ # # # # ]: 0 : ft_field_support_2_nic_receive.inner_l4_ok) &&
890 : : MLX5_GET(flow_table_nic_cap, hcattr,
891 [ # # # # ]: 0 : ft_field_support_2_nic_receive.outer_l3_ok) &&
892 : : MLX5_GET(flow_table_nic_cap, hcattr,
893 [ # # # # ]: 0 : ft_field_support_2_nic_receive.outer_l4_ok) &&
894 : : MLX5_GET(flow_table_nic_cap, hcattr,
895 : : ft_field_support_2_nic_receive
896 [ # # # # ]: 0 : .inner_ipv4_checksum_ok) &&
897 : : MLX5_GET(flow_table_nic_cap, hcattr,
898 [ # # # # ]: 0 : ft_field_support_2_nic_receive.inner_l4_checksum_ok) &&
899 : : MLX5_GET(flow_table_nic_cap, hcattr,
900 : : ft_field_support_2_nic_receive
901 [ # # # # : 0 : .outer_ipv4_checksum_ok) &&
# # # # #
# # # # #
# # # # ]
902 [ # # # # ]: 0 : MLX5_GET(flow_table_nic_cap, hcattr,
903 : : ft_field_support_2_nic_receive.outer_l4_checksum_ok);
904 : : }
905 : :
906 : : /**
907 : : * Query HCA attributes.
908 : : * Using those attributes we can check on run time if the device
909 : : * is having the required capabilities.
910 : : *
911 : : * @param[in] ctx
912 : : * Context returned from mlx5 open_device() glue function.
913 : : * @param[out] attr
914 : : * Attributes device values.
915 : : *
916 : : * @return
917 : : * 0 on success, a negative value otherwise.
918 : : */
919 : : int
920 : 0 : mlx5_devx_cmd_query_hca_attr(void *ctx,
921 : : struct mlx5_hca_attr *attr)
922 : : {
923 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
924 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
925 : : bool hca_cap_2_sup;
926 : : uint64_t general_obj_types_supported = 0;
927 : : void *hcattr;
928 : : int rc, i;
929 : :
930 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
931 : : MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE |
932 : : MLX5_HCA_CAP_OPMOD_GET_CUR);
933 [ # # ]: 0 : if (!hcattr)
934 : 0 : return rc;
935 [ # # ]: 0 : hca_cap_2_sup = MLX5_GET(cmd_hca_cap, hcattr, hca_cap_2);
936 [ # # ]: 0 : attr->max_wqe_sz_sq = MLX5_GET(cmd_hca_cap, hcattr, max_wqe_sz_sq);
937 : 0 : attr->flow_counter_bulk_alloc_bitmap =
938 [ # # ]: 0 : MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc);
939 [ # # ]: 0 : attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr,
940 : : flow_counters_dump);
941 [ # # ]: 0 : attr->log_max_rmp = MLX5_GET(cmd_hca_cap, hcattr, log_max_rmp);
942 [ # # ]: 0 : attr->mem_rq_rmp = MLX5_GET(cmd_hca_cap, hcattr, mem_rq_rmp);
943 [ # # ]: 0 : attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr,
944 : : log_max_rqt_size);
945 [ # # ]: 0 : attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager);
946 [ # # ]: 0 : attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin);
947 [ # # ]: 0 : attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr,
948 : : log_max_hairpin_queues);
949 [ # # ]: 0 : attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr,
950 : : log_max_hairpin_wq_data_sz);
951 [ # # ]: 0 : attr->log_max_hairpin_num_packets = MLX5_GET
952 : : (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz);
953 [ # # ]: 0 : attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id);
954 [ # # ]: 0 : attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr,
955 : : relaxed_ordering_write);
956 [ # # ]: 0 : attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr,
957 : : relaxed_ordering_read);
958 [ # # ]: 0 : attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr,
959 : : access_register_user);
960 [ # # ]: 0 : attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr,
961 : : eth_net_offloads);
962 [ # # ]: 0 : attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);
963 [ # # ]: 0 : attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr,
964 : : flex_parser_protocols);
965 [ # # ]: 0 : attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr,
966 : : max_geneve_tlv_options);
967 [ # # ]: 0 : attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr,
968 : : max_geneve_tlv_option_data_len);
969 [ # # ]: 0 : attr->geneve_tlv_option_offset = MLX5_GET(cmd_hca_cap, hcattr,
970 : : geneve_tlv_option_offset);
971 [ # # ]: 0 : attr->geneve_tlv_sample = MLX5_GET(cmd_hca_cap, hcattr,
972 : : geneve_tlv_sample);
973 [ # # ]: 0 : attr->query_match_sample_info = MLX5_GET(cmd_hca_cap, hcattr,
974 : : query_match_sample_info);
975 [ # # ]: 0 : attr->geneve_tlv_option_sample_id = MLX5_GET(cmd_hca_cap, hcattr,
976 : : flex_parser_id_geneve_opt_0);
977 [ # # ]: 0 : attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos);
978 [ # # ]: 0 : attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr,
979 : : wqe_index_ignore_cap);
980 [ # # ]: 0 : attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd);
981 [ # # ]: 0 : attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq);
982 [ # # ]: 0 : attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr,
983 : : log_max_static_sq_wq);
984 [ # # ]: 0 : attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports);
985 [ # # ]: 0 : attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr,
986 : : device_frequency_khz);
987 : 0 : attr->scatter_fcs_w_decap_disable =
988 [ # # ]: 0 : MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable);
989 [ # # ]: 0 : attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce);
990 [ # # ]: 0 : attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format);
991 [ # # ]: 0 : attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format);
992 : 0 : attr->steering_format_version =
993 [ # # ]: 0 : MLX5_GET(cmd_hca_cap, hcattr, steering_format_version);
994 [ # # ]: 0 : attr->regexp_params = MLX5_GET(cmd_hca_cap, hcattr, regexp_params);
995 [ # # ]: 0 : attr->regexp_version = MLX5_GET(cmd_hca_cap, hcattr, regexp_version);
996 [ # # ]: 0 : attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr,
997 : : regexp_num_of_engines);
998 : : /* Read the general_obj_types bitmap and extract the relevant bits. */
999 [ # # ]: 0 : general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr,
1000 : : general_obj_types);
1001 : 0 : attr->qos.flow_meter_aso_sup =
1002 : 0 : !!(general_obj_types_supported &
1003 : : MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO);
1004 : 0 : attr->vdpa.valid = !!(general_obj_types_supported &
1005 : : MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q);
1006 : 0 : attr->vdpa.queue_counters_valid =
1007 : 0 : !!(general_obj_types_supported &
1008 : : MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS);
1009 : 0 : attr->parse_graph_flex_node =
1010 : 0 : !!(general_obj_types_supported &
1011 : : MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE);
1012 : 0 : attr->flow_hit_aso = !!(general_obj_types_supported &
1013 : : MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO);
1014 : 0 : attr->geneve_tlv_opt = !!(general_obj_types_supported &
1015 : : MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT);
1016 : 0 : attr->dek = !!(general_obj_types_supported &
1017 : : MLX5_GENERAL_OBJ_TYPES_CAP_DEK);
1018 : 0 : attr->import_kek = !!(general_obj_types_supported &
1019 : : MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK);
1020 : 0 : attr->credential = !!(general_obj_types_supported &
1021 : : MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL);
1022 : 0 : attr->crypto_login = !!(general_obj_types_supported &
1023 : : MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN);
1024 : : /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */
1025 [ # # ]: 0 : attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq);
1026 [ # # ]: 0 : attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp);
1027 [ # # ]: 0 : attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz);
1028 [ # # ]: 0 : attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz);
1029 [ # # ]: 0 : attr->log_max_wq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_wq_sz);
1030 [ # # ]: 0 : attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz);
1031 [ # # ]: 0 : attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd);
1032 [ # # ]: 0 : attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq);
1033 [ # # ]: 0 : attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz);
1034 : 0 : attr->reg_c_preserve =
1035 [ # # ]: 0 : MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve);
1036 [ # # ]: 0 : attr->mmo_regex_qp_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_qp);
1037 [ # # ]: 0 : attr->mmo_regex_sq_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_sq);
1038 [ # # ]: 0 : attr->mmo_dma_sq_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_sq);
1039 [ # # ]: 0 : attr->mmo_compress_sq_en = MLX5_GET(cmd_hca_cap, hcattr,
1040 : : compress_mmo_sq);
1041 [ # # ]: 0 : attr->mmo_decompress_sq_en = MLX5_GET(cmd_hca_cap, hcattr,
1042 : : decompress_mmo_sq);
1043 [ # # ]: 0 : attr->mmo_dma_qp_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_qp);
1044 [ # # ]: 0 : attr->mmo_compress_qp_en = MLX5_GET(cmd_hca_cap, hcattr,
1045 : : compress_mmo_qp);
1046 [ # # ]: 0 : attr->decomp_deflate_v1_en = MLX5_GET(cmd_hca_cap, hcattr,
1047 : : decompress_deflate_v1);
1048 [ # # ]: 0 : attr->decomp_deflate_v2_en = MLX5_GET(cmd_hca_cap, hcattr,
1049 : : decompress_deflate_v2);
1050 [ # # ]: 0 : attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr,
1051 : : compress_min_block_size);
1052 [ # # ]: 0 : attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size);
1053 [ # # ]: 0 : attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr,
1054 : : log_compress_mmo_size);
1055 [ # # ]: 0 : attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr,
1056 : : log_decompress_mmo_size);
1057 [ # # ]: 0 : attr->decomp_lz4_data_only_en = MLX5_GET(cmd_hca_cap, hcattr,
1058 : : decompress_lz4_data_only_v2);
1059 [ # # ]: 0 : attr->decomp_lz4_no_checksum_en = MLX5_GET(cmd_hca_cap, hcattr,
1060 : : decompress_lz4_no_checksum_v2);
1061 [ # # ]: 0 : attr->decomp_lz4_checksum_en = MLX5_GET(cmd_hca_cap, hcattr,
1062 : : decompress_lz4_checksum_v2);
1063 [ # # ]: 0 : attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression);
1064 [ # # ]: 0 : attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr,
1065 : : mini_cqe_resp_flow_tag);
1066 [ # # ]: 0 : attr->cqe_compression_128 = MLX5_GET(cmd_hca_cap, hcattr,
1067 : : cqe_compression_128);
1068 [ # # ]: 0 : attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr,
1069 : : mini_cqe_resp_l3_l4_tag);
1070 [ # # ]: 0 : attr->enhanced_cqe_compression = MLX5_GET(cmd_hca_cap, hcattr,
1071 : : enhanced_cqe_compression);
1072 : 0 : attr->umr_indirect_mkey_disabled =
1073 [ # # ]: 0 : MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled);
1074 : 0 : attr->umr_modify_entity_size_disabled =
1075 [ # # ]: 0 : MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled);
1076 [ # # ]: 0 : attr->wait_on_time = MLX5_GET(cmd_hca_cap, hcattr, wait_on_time);
1077 [ # # ]: 0 : attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto);
1078 : 0 : attr->ct_offload = !!(general_obj_types_supported &
1079 : : MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD);
1080 [ # # ]: 0 : attr->rq_delay_drop = MLX5_GET(cmd_hca_cap, hcattr, rq_delay_drop);
1081 [ # # ]: 0 : attr->nic_flow_table = MLX5_GET(cmd_hca_cap, hcattr, nic_flow_table);
1082 [ # # ]: 0 : attr->striding_rq = MLX5_GET(cmd_hca_cap, hcattr, striding_rq);
1083 : 0 : attr->ext_stride_num_range =
1084 [ # # ]: 0 : MLX5_GET(cmd_hca_cap, hcattr, ext_stride_num_range);
1085 [ # # ]: 0 : attr->nic_flow_table = MLX5_GET(cmd_hca_cap, hcattr, nic_flow_table);
1086 [ # # ]: 0 : attr->max_flow_counter_15_0 = MLX5_GET(cmd_hca_cap, hcattr,
1087 : : max_flow_counter_15_0);
1088 [ # # ]: 0 : attr->max_flow_counter_31_16 = MLX5_GET(cmd_hca_cap, hcattr,
1089 : : max_flow_counter_31_16);
1090 [ # # ]: 0 : attr->alloc_flow_counter_pd = MLX5_GET(cmd_hca_cap, hcattr,
1091 : : alloc_flow_counter_pd);
1092 [ # # ]: 0 : attr->flow_counter_access_aso = MLX5_GET(cmd_hca_cap, hcattr,
1093 : : flow_counter_access_aso);
1094 [ # # ]: 0 : attr->flow_access_aso_opc_mod = MLX5_GET(cmd_hca_cap, hcattr,
1095 : : flow_access_aso_opc_mod);
1096 [ # # ]: 0 : attr->wqe_based_flow_table_sup = MLX5_GET(cmd_hca_cap, hcattr,
1097 : : wqe_based_flow_table_update_cap);
1098 : : /*
1099 : : * Flex item support needs max_num_prog_sample_field
1100 : : * from the Capabilities 2 table for PARSE_GRAPH_NODE
1101 : : */
1102 [ # # ]: 0 : if (attr->parse_graph_flex_node) {
1103 : 0 : rc = mlx5_devx_cmd_query_hca_parse_graph_node_cap
1104 : : (ctx, &attr->flex);
1105 [ # # ]: 0 : if (rc)
1106 : : return -1;
1107 : 0 : attr->flex.query_match_sample_info =
1108 : 0 : attr->query_match_sample_info;
1109 : : }
1110 [ # # ]: 0 : if (attr->crypto) {
1111 [ # # # # : 0 : attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts) ||
# # ]
1112 [ # # # # : 0 : MLX5_GET(cmd_hca_cap, hcattr, aes_xts_multi_block_be_tweak) ||
# # # # #
# # # ]
1113 : : MLX5_GET(cmd_hca_cap, hcattr, aes_xts_single_block_le_tweak);
1114 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1115 : : MLX5_GET_HCA_CAP_OP_MOD_CRYPTO |
1116 : : MLX5_HCA_CAP_OPMOD_GET_CUR);
1117 [ # # ]: 0 : if (!hcattr)
1118 : : return -1;
1119 [ # # ]: 0 : attr->crypto_wrapped_import_method = !!(MLX5_GET(crypto_caps,
1120 : : hcattr, wrapped_import_method)
1121 : 0 : & 1 << 2);
1122 [ # # ]: 0 : attr->crypto_mmo.crypto_mmo_qp = MLX5_GET(crypto_caps, hcattr, crypto_mmo_qp);
1123 : 0 : attr->crypto_mmo.gcm_256_encrypt =
1124 [ # # ]: 0 : MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_256_encrypt);
1125 : 0 : attr->crypto_mmo.gcm_128_encrypt =
1126 [ # # ]: 0 : MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_128_encrypt);
1127 : 0 : attr->crypto_mmo.gcm_256_decrypt =
1128 [ # # ]: 0 : MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_256_decrypt);
1129 : 0 : attr->crypto_mmo.gcm_128_decrypt =
1130 [ # # ]: 0 : MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_128_decrypt);
1131 : 0 : attr->crypto_mmo.gcm_auth_tag_128 =
1132 [ # # ]: 0 : MLX5_GET(crypto_caps, hcattr, gcm_auth_tag_128);
1133 : 0 : attr->crypto_mmo.gcm_auth_tag_96 =
1134 [ # # ]: 0 : MLX5_GET(crypto_caps, hcattr, gcm_auth_tag_96);
1135 : 0 : attr->crypto_mmo.log_crypto_mmo_max_size =
1136 [ # # ]: 0 : MLX5_GET(crypto_caps, hcattr, log_crypto_mmo_max_size);
1137 : : }
1138 [ # # ]: 0 : if (hca_cap_2_sup) {
1139 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1140 : : MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 |
1141 : : MLX5_HCA_CAP_OPMOD_GET_CUR);
1142 [ # # ]: 0 : if (!hcattr) {
1143 : 0 : DRV_LOG(DEBUG,
1144 : : "Failed to query DevX HCA capabilities 2.");
1145 : 0 : return rc;
1146 : : }
1147 [ # # ]: 0 : attr->log_min_stride_wqe_sz = MLX5_GET(cmd_hca_cap_2, hcattr,
1148 : : log_min_stride_wqe_sz);
1149 [ # # ]: 0 : attr->hairpin_sq_wqe_bb_size = MLX5_GET(cmd_hca_cap_2, hcattr,
1150 : : hairpin_sq_wqe_bb_size);
1151 [ # # ]: 0 : attr->hairpin_sq_wq_in_host_mem = MLX5_GET(cmd_hca_cap_2, hcattr,
1152 : : hairpin_sq_wq_in_host_mem);
1153 [ # # ]: 0 : attr->hairpin_data_buffer_locked = MLX5_GET(cmd_hca_cap_2, hcattr,
1154 : : hairpin_data_buffer_locked);
1155 [ # # ]: 0 : attr->flow_counter_bulk_log_max_alloc = MLX5_GET(cmd_hca_cap_2,
1156 : : hcattr, flow_counter_bulk_log_max_alloc);
1157 : 0 : attr->flow_counter_bulk_log_granularity =
1158 [ # # ]: 0 : MLX5_GET(cmd_hca_cap_2, hcattr,
1159 : : flow_counter_bulk_log_granularity);
1160 [ # # ]: 0 : rc = MLX5_GET(cmd_hca_cap_2, hcattr,
1161 : : cross_vhca_object_to_object_supported);
1162 : 0 : attr->cross_vhca =
1163 : : (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_STC_TO_TIR) &&
1164 : : (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_STC_TO_FT) &&
1165 : 0 : (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_FT_TO_FT) &&
1166 : : (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_FT_TO_RTC);
1167 [ # # ]: 0 : rc = MLX5_GET(cmd_hca_cap_2, hcattr,
1168 : : allowed_object_for_other_vhca_access);
1169 : 0 : attr->cross_vhca = attr->cross_vhca &&
1170 : : (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_TIR) &&
1171 [ # # # # ]: 0 : (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_FT) &&
1172 : : (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_RTC);
1173 [ # # ]: 0 : if (attr->ct_offload)
1174 [ # # ]: 0 : attr->log_max_conn_track_offload = MLX5_GET(cmd_hca_cap_2, hcattr,
1175 : : log_max_conn_track_offload);
1176 : : }
1177 [ # # ]: 0 : if (attr->log_min_stride_wqe_sz == 0)
1178 : 0 : attr->log_min_stride_wqe_sz = MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE;
1179 [ # # ]: 0 : if (attr->qos.sup) {
1180 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1181 : : MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |
1182 : : MLX5_HCA_CAP_OPMOD_GET_CUR);
1183 [ # # ]: 0 : if (!hcattr) {
1184 : 0 : DRV_LOG(DEBUG, "Failed to query devx QOS capabilities");
1185 : 0 : return rc;
1186 : : }
1187 : 0 : attr->qos.flow_meter_old =
1188 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr, flow_meter_old);
1189 [ # # ]: 0 : attr->qos.log_max_flow_meter =
1190 : 0 : MLX5_GET(qos_cap, hcattr, log_max_flow_meter);
1191 [ # # ]: 0 : attr->qos.flow_meter_reg_c_ids =
1192 : : MLX5_GET(qos_cap, hcattr, flow_meter_reg_id);
1193 : 0 : attr->qos.flow_meter =
1194 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr, flow_meter);
1195 : 0 : attr->qos.packet_pacing =
1196 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr, packet_pacing);
1197 : 0 : attr->qos.wqe_rate_pp =
1198 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr, wqe_rate_pp);
1199 [ # # ]: 0 : if (attr->qos.flow_meter_aso_sup) {
1200 : 0 : attr->qos.log_meter_aso_granularity =
1201 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr,
1202 : : log_meter_aso_granularity);
1203 : 0 : attr->qos.log_meter_aso_max_alloc =
1204 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr,
1205 : : log_meter_aso_max_alloc);
1206 : 0 : attr->qos.log_max_num_meter_aso =
1207 [ # # ]: 0 : MLX5_GET(qos_cap, hcattr,
1208 : : log_max_num_meter_aso);
1209 : : }
1210 : : }
1211 [ # # ]: 0 : if (attr->vdpa.valid)
1212 : 0 : mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa);
1213 [ # # ]: 0 : if (!attr->eth_net_offloads)
1214 : : return 0;
1215 : : /* Query Flow Sampler Capability From FLow Table Properties Layout. */
1216 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1217 : : MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE |
1218 : : MLX5_HCA_CAP_OPMOD_GET_CUR);
1219 [ # # ]: 0 : if (!hcattr) {
1220 : 0 : attr->log_max_ft_sampler_num = 0;
1221 : 0 : return rc;
1222 : : }
1223 [ # # ]: 0 : attr->log_max_ft_sampler_num = MLX5_GET
1224 : : (flow_table_nic_cap, hcattr,
1225 : : flow_table_properties_nic_receive.log_max_ft_sampler_num);
1226 [ # # ]: 0 : attr->flow.tunnel_header_0_1 = MLX5_GET
1227 : : (flow_table_nic_cap, hcattr,
1228 : : ft_field_support_2_nic_receive.tunnel_header_0_1);
1229 [ # # ]: 0 : attr->flow.tunnel_header_2_3 = MLX5_GET
1230 : : (flow_table_nic_cap, hcattr,
1231 : : ft_field_support_2_nic_receive.tunnel_header_2_3);
1232 [ # # ]: 0 : attr->modify_outer_ip_ecn = MLX5_GET
1233 : : (flow_table_nic_cap, hcattr,
1234 : : ft_header_modify_nic_receive.outer_ip_ecn);
1235 [ # # ]: 0 : attr->modify_outer_ipv6_traffic_class = MLX5_GET
1236 : : (flow_table_nic_cap, hcattr,
1237 : : ft_header_modify_nic_receive.outer_ipv6_traffic_class);
1238 : 0 : attr->set_reg_c = 0xffff;
1239 [ # # ]: 0 : if (attr->nic_flow_table) {
1240 : : #define GET_RX_REG_X_BITS \
1241 : : MLX5_GET(flow_table_nic_cap, hcattr, \
1242 : : ft_header_modify_nic_receive.metadata_reg_c_x)
1243 : : #define GET_TX_REG_X_BITS \
1244 : : MLX5_GET(flow_table_nic_cap, hcattr, \
1245 : : ft_header_modify_nic_transmit.metadata_reg_c_x)
1246 : :
1247 : : uint32_t tx_reg, rx_reg, reg_c_8_15;
1248 : :
1249 [ # # ]: 0 : tx_reg = GET_TX_REG_X_BITS;
1250 [ # # ]: 0 : reg_c_8_15 = MLX5_GET(flow_table_nic_cap, hcattr,
1251 : : ft_field_support_2_nic_transmit.metadata_reg_c_8_15);
1252 : 0 : tx_reg |= ((0xff & reg_c_8_15) << 8);
1253 [ # # ]: 0 : rx_reg = GET_RX_REG_X_BITS;
1254 [ # # ]: 0 : reg_c_8_15 = MLX5_GET(flow_table_nic_cap, hcattr,
1255 : : ft_field_support_2_nic_receive.metadata_reg_c_8_15);
1256 : 0 : rx_reg |= ((0xff & reg_c_8_15) << 8);
1257 : 0 : attr->set_reg_c &= (rx_reg & tx_reg);
1258 : :
1259 : : #undef GET_RX_REG_X_BITS
1260 : : #undef GET_TX_REG_X_BITS
1261 : : }
1262 : 0 : attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr);
1263 [ # # ]: 0 : attr->inner_ipv4_ihl = MLX5_GET
1264 : : (flow_table_nic_cap, hcattr,
1265 : : ft_field_support_2_nic_receive.inner_ipv4_ihl);
1266 [ # # ]: 0 : attr->outer_ipv4_ihl = MLX5_GET
1267 : : (flow_table_nic_cap, hcattr,
1268 : : ft_field_support_2_nic_receive.outer_ipv4_ihl);
1269 [ # # ]: 0 : attr->lag_rx_port_affinity = MLX5_GET
1270 : : (flow_table_nic_cap, hcattr,
1271 : : ft_field_support_2_nic_receive.lag_rx_port_affinity);
1272 : : /* Query HCA offloads for Ethernet protocol. */
1273 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1274 : : MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS |
1275 : : MLX5_HCA_CAP_OPMOD_GET_CUR);
1276 [ # # ]: 0 : if (!hcattr) {
1277 : 0 : attr->eth_net_offloads = 0;
1278 : 0 : return rc;
1279 : : }
1280 [ # # ]: 0 : attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps,
1281 : : hcattr, wqe_vlan_insert);
1282 [ # # ]: 0 : attr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps,
1283 : : hcattr, csum_cap);
1284 [ # # ]: 0 : attr->vlan_cap = MLX5_GET(per_protocol_networking_offload_caps,
1285 : : hcattr, vlan_cap);
1286 [ # # ]: 0 : attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr,
1287 : : lro_cap);
1288 [ # # ]: 0 : attr->max_lso_cap = MLX5_GET(per_protocol_networking_offload_caps,
1289 : : hcattr, max_lso_cap);
1290 [ # # ]: 0 : attr->scatter_fcs = MLX5_GET(per_protocol_networking_offload_caps,
1291 : : hcattr, scatter_fcs);
1292 [ # # ]: 0 : attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps,
1293 : : hcattr, tunnel_lro_gre);
1294 [ # # ]: 0 : attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps,
1295 : : hcattr, tunnel_lro_vxlan);
1296 [ # # ]: 0 : attr->swp = MLX5_GET(per_protocol_networking_offload_caps,
1297 : : hcattr, swp);
1298 : 0 : attr->tunnel_stateless_gre =
1299 [ # # ]: 0 : MLX5_GET(per_protocol_networking_offload_caps,
1300 : : hcattr, tunnel_stateless_gre);
1301 : 0 : attr->tunnel_stateless_vxlan =
1302 [ # # ]: 0 : MLX5_GET(per_protocol_networking_offload_caps,
1303 : : hcattr, tunnel_stateless_vxlan);
1304 [ # # ]: 0 : attr->swp_csum = MLX5_GET(per_protocol_networking_offload_caps,
1305 : : hcattr, swp_csum);
1306 [ # # ]: 0 : attr->swp_lso = MLX5_GET(per_protocol_networking_offload_caps,
1307 : : hcattr, swp_lso);
1308 [ # # ]: 0 : attr->lro_max_msg_sz_mode = MLX5_GET
1309 : : (per_protocol_networking_offload_caps,
1310 : : hcattr, lro_max_msg_sz_mode);
1311 [ # # ]: 0 : for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) {
1312 : 0 : attr->lro_timer_supported_periods[i] =
1313 [ # # ]: 0 : MLX5_GET(per_protocol_networking_offload_caps, hcattr,
1314 : : lro_timer_supported_periods[i]);
1315 : : }
1316 [ # # ]: 0 : attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps,
1317 : : hcattr, lro_min_mss_size);
1318 : 0 : attr->tunnel_stateless_geneve_rx =
1319 [ # # ]: 0 : MLX5_GET(per_protocol_networking_offload_caps,
1320 : : hcattr, tunnel_stateless_geneve_rx);
1321 : 0 : attr->geneve_max_opt_len =
1322 [ # # ]: 0 : MLX5_GET(per_protocol_networking_offload_caps,
1323 : : hcattr, max_geneve_opt_len);
1324 [ # # ]: 0 : attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps,
1325 : : hcattr, wqe_inline_mode);
1326 [ # # ]: 0 : attr->tunnel_stateless_gtp = MLX5_GET
1327 : : (per_protocol_networking_offload_caps,
1328 : : hcattr, tunnel_stateless_gtp);
1329 [ # # ]: 0 : attr->tunnel_stateless_vxlan_gpe_nsh = MLX5_GET
1330 : : (per_protocol_networking_offload_caps,
1331 : : hcattr, tunnel_stateless_vxlan_gpe_nsh);
1332 [ # # ]: 0 : attr->rss_ind_tbl_cap = MLX5_GET
1333 : : (per_protocol_networking_offload_caps,
1334 : : hcattr, rss_ind_tbl_cap);
1335 [ # # ]: 0 : attr->multi_pkt_send_wqe = MLX5_GET
1336 : : (per_protocol_networking_offload_caps,
1337 : : hcattr, multi_pkt_send_wqe);
1338 [ # # ]: 0 : attr->enhanced_multi_pkt_send_wqe = MLX5_GET
1339 : : (per_protocol_networking_offload_caps,
1340 : : hcattr, enhanced_multi_pkt_send_wqe);
1341 [ # # ]: 0 : if (attr->wqe_based_flow_table_sup) {
1342 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1343 : : MLX5_GET_HCA_CAP_OP_MOD_WQE_BASED_FLOW_TABLE |
1344 : : MLX5_HCA_CAP_OPMOD_GET_CUR);
1345 [ # # ]: 0 : if (!hcattr) {
1346 : 0 : DRV_LOG(DEBUG, "Failed to query WQE Based Flow table capabilities");
1347 : 0 : return rc;
1348 : : }
1349 [ # # ]: 0 : attr->max_header_modify_pattern_length = MLX5_GET(wqe_based_flow_table_cap,
1350 : : hcattr,
1351 : : max_header_modify_pattern_length);
1352 : : }
1353 : : /* Query HCA attribute for ROCE. */
1354 [ # # ]: 0 : if (attr->roce) {
1355 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1356 : : MLX5_GET_HCA_CAP_OP_MOD_ROCE |
1357 : : MLX5_HCA_CAP_OPMOD_GET_CUR);
1358 [ # # ]: 0 : if (!hcattr) {
1359 : 0 : DRV_LOG(DEBUG,
1360 : : "Failed to query devx HCA ROCE capabilities");
1361 : 0 : return rc;
1362 : : }
1363 [ # # ]: 0 : attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format);
1364 : : }
1365 [ # # ]: 0 : if (attr->eth_virt) {
1366 : 0 : rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr);
1367 [ # # ]: 0 : if (rc) {
1368 : 0 : attr->eth_virt = 0;
1369 : 0 : goto error;
1370 : : }
1371 : : }
1372 [ # # ]: 0 : if (attr->eswitch_manager) {
1373 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1374 : : MLX5_SET_HCA_CAP_OP_MOD_ESW |
1375 : : MLX5_HCA_CAP_OPMOD_GET_CUR);
1376 [ # # ]: 0 : if (!hcattr)
1377 : 0 : return rc;
1378 : 0 : attr->esw_mgr_vport_id_valid =
1379 [ # # ]: 0 : MLX5_GET(esw_cap, hcattr,
1380 : : esw_manager_vport_number_valid);
1381 : 0 : attr->esw_mgr_vport_id =
1382 [ # # ]: 0 : MLX5_GET(esw_cap, hcattr, esw_manager_vport_number);
1383 : : }
1384 [ # # ]: 0 : if (attr->eswitch_manager) {
1385 : : uint32_t esw_reg, reg_c_8_15;
1386 : :
1387 : 0 : hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1388 : : MLX5_GET_HCA_CAP_OP_MOD_ESW_FLOW_TABLE |
1389 : : MLX5_HCA_CAP_OPMOD_GET_CUR);
1390 [ # # ]: 0 : if (!hcattr)
1391 : 0 : return rc;
1392 [ # # ]: 0 : esw_reg = MLX5_GET(flow_table_esw_cap, hcattr,
1393 : : ft_header_modify_esw_fdb.metadata_reg_c_x);
1394 [ # # ]: 0 : reg_c_8_15 = MLX5_GET(flow_table_esw_cap, hcattr,
1395 : : ft_field_support_2_esw_fdb.metadata_reg_c_8_15);
1396 : 0 : attr->set_reg_c &= ((0xff & reg_c_8_15) << 8) | esw_reg;
1397 : : }
1398 : : return 0;
1399 : : error:
1400 : 0 : rc = (rc > 0) ? -rc : rc;
1401 : 0 : return rc;
1402 : : }
1403 : :
1404 : : /**
1405 : : * Query TIS transport domain from QP verbs object using DevX API.
1406 : : *
1407 : : * @param[in] qp
1408 : : * Pointer to verbs QP returned by ibv_create_qp .
1409 : : * @param[in] tis_num
1410 : : * TIS number of TIS to query.
1411 : : * @param[out] tis_td
1412 : : * Pointer to TIS transport domain variable, to be set by the routine.
1413 : : *
1414 : : * @return
1415 : : * 0 on success, a negative value otherwise.
1416 : : */
1417 : : int
1418 : 0 : mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num,
1419 : : uint32_t *tis_td)
1420 : : {
1421 : : #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1422 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0};
1423 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0};
1424 : : int rc;
1425 : : void *tis_ctx;
1426 : :
1427 : 0 : MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS);
1428 : 0 : MLX5_SET(query_tis_in, in, tisn, tis_num);
1429 : 0 : rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out));
1430 [ # # ]: 0 : if (rc) {
1431 : 0 : DRV_LOG(ERR, "Failed to query QP using DevX");
1432 : 0 : return -rc;
1433 : : };
1434 : : tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context);
1435 [ # # ]: 0 : *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain);
1436 : 0 : return 0;
1437 : : #else
1438 : : (void)qp;
1439 : : (void)tis_num;
1440 : : (void)tis_td;
1441 : : return -ENOTSUP;
1442 : : #endif
1443 : : }
1444 : :
1445 : : /**
1446 : : * Fill WQ data for DevX API command.
1447 : : * Utility function for use when creating DevX objects containing a WQ.
1448 : : *
1449 : : * @param[in] wq_ctx
1450 : : * Pointer to WQ context to fill with data.
1451 : : * @param [in] wq_attr
1452 : : * Pointer to WQ attributes structure to fill in WQ context.
1453 : : */
1454 : : static void
1455 : 0 : devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr)
1456 : : {
1457 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type);
1458 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature);
1459 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode);
1460 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave);
1461 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge);
1462 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size);
1463 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset);
1464 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm);
1465 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, pd, wq_attr->pd);
1466 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page);
1467 [ # # ]: 0 : MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr);
1468 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter);
1469 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter);
1470 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride);
1471 [ # # ]: 0 : if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT)
1472 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, log_wq_pg_sz,
1473 : : wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT);
1474 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz);
1475 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid);
1476 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid);
1477 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, log_hairpin_num_packets,
1478 : : wq_attr->log_hairpin_num_packets);
1479 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz);
1480 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides,
1481 : : wq_attr->single_wqe_log_num_of_strides);
1482 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en);
1483 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes,
1484 : : wq_attr->single_stride_log_num_of_bytes);
1485 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id);
1486 [ # # ]: 0 : MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id);
1487 [ # # ]: 0 : MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset);
1488 : 0 : }
1489 : :
1490 : : /**
1491 : : * Create RQ using DevX API.
1492 : : *
1493 : : * @param[in] ctx
1494 : : * Context returned from mlx5 open_device() glue function.
1495 : : * @param [in] rq_attr
1496 : : * Pointer to create RQ attributes structure.
1497 : : * @param [in] socket
1498 : : * CPU socket ID for allocations.
1499 : : *
1500 : : * @return
1501 : : * The DevX object created, NULL otherwise and rte_errno is set.
1502 : : */
1503 : : struct mlx5_devx_obj *
1504 : 0 : mlx5_devx_cmd_create_rq(void *ctx,
1505 : : struct mlx5_devx_create_rq_attr *rq_attr,
1506 : : int socket)
1507 : : {
1508 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0};
1509 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0};
1510 : : void *rq_ctx, *wq_ctx;
1511 : : struct mlx5_devx_wq_attr *wq_attr;
1512 : : struct mlx5_devx_obj *rq = NULL;
1513 : :
1514 : 0 : rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket);
1515 [ # # ]: 0 : if (!rq) {
1516 : 0 : DRV_LOG(ERR, "Failed to allocate RQ data");
1517 : 0 : rte_errno = ENOMEM;
1518 : 0 : return NULL;
1519 : : }
1520 [ # # ]: 0 : MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ);
1521 : : rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx);
1522 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky);
1523 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en);
1524 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
1525 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
1526 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type);
1527 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
1528 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en);
1529 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin);
1530 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, hairpin_data_buffer_type, rq_attr->hairpin_data_buffer_type);
1531 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index);
1532 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn);
1533 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
1534 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn);
1535 [ # # ]: 0 : MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format);
1536 : : wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
1537 : 0 : wq_attr = &rq_attr->wq_attr;
1538 : 0 : devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1539 : 0 : rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1540 : : out, sizeof(out));
1541 [ # # ]: 0 : if (!rq->obj) {
1542 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create RQ", NULL, 0);
1543 : 0 : mlx5_free(rq);
1544 : 0 : return NULL;
1545 : : }
1546 [ # # ]: 0 : rq->id = MLX5_GET(create_rq_out, out, rqn);
1547 : 0 : return rq;
1548 : : }
1549 : :
1550 : : /**
1551 : : * Modify RQ using DevX API.
1552 : : *
1553 : : * @param[in] rq
1554 : : * Pointer to RQ object structure.
1555 : : * @param [in] rq_attr
1556 : : * Pointer to modify RQ attributes structure.
1557 : : *
1558 : : * @return
1559 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
1560 : : */
1561 : : int
1562 : 0 : mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
1563 : : struct mlx5_devx_modify_rq_attr *rq_attr)
1564 : : {
1565 : 0 : uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0};
1566 : 0 : uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0};
1567 : : void *rq_ctx, *wq_ctx;
1568 : : int ret;
1569 : :
1570 : 0 : MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ);
1571 : 0 : MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state);
1572 [ # # ]: 0 : MLX5_SET(modify_rq_in, in, rqn, rq->id);
1573 [ # # ]: 0 : MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask);
1574 : : rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1575 : 0 : MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
1576 [ # # ]: 0 : if (rq_attr->modify_bitmask &
1577 : : MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS)
1578 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
1579 [ # # ]: 0 : if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD)
1580 [ # # ]: 0 : MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
1581 [ # # ]: 0 : if (rq_attr->modify_bitmask &
1582 : : MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID)
1583 : 0 : MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
1584 : 0 : MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq);
1585 : 0 : MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca);
1586 [ # # ]: 0 : if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) {
1587 : : wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
1588 : 0 : MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm);
1589 : : }
1590 : 0 : ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in),
1591 : : out, sizeof(out));
1592 : :
1593 [ # # ]: 0 : if (ret) {
1594 : 0 : DRV_LOG(ERR, "Failed to modify RQ using DevX");
1595 : 0 : rte_errno = errno;
1596 : 0 : return -errno;
1597 : : }
1598 : : return ret;
1599 : : }
1600 : :
1601 : : /*
1602 : : * Query RQ using DevX API.
1603 : : *
1604 : : * @param[in] rq_obj
1605 : : * RQ Devx Object
1606 : : * @param[out] out
1607 : : * RQ Query Output
1608 : : * @param[in] outlen
1609 : : * RQ Query Output Length
1610 : : *
1611 : : * @return
1612 : : * 0 if Query successful, else non-zero return value from devx_obj_query API
1613 : : */
1614 : : int
1615 : 0 : mlx5_devx_cmd_query_rq(struct mlx5_devx_obj *rq_obj, void *out, size_t outlen)
1616 : : {
1617 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0};
1618 : : int rc;
1619 : :
1620 : 0 : MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ);
1621 : 0 : MLX5_SET(query_rq_in, in, rqn, rq_obj->id);
1622 : 0 : rc = mlx5_glue->devx_obj_query(rq_obj->obj, in, sizeof(in), out, outlen);
1623 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
1624 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "RQ query", "rq_id", rq_obj->id);
1625 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
1626 : : }
1627 : : return 0;
1628 : : }
1629 : :
1630 : : /**
1631 : : * Create RMP using DevX API.
1632 : : *
1633 : : * @param[in] ctx
1634 : : * Context returned from mlx5 open_device() glue function.
1635 : : * @param [in] rmp_attr
1636 : : * Pointer to create RMP attributes structure.
1637 : : * @param [in] socket
1638 : : * CPU socket ID for allocations.
1639 : : *
1640 : : * @return
1641 : : * The DevX object created, NULL otherwise and rte_errno is set.
1642 : : */
1643 : : struct mlx5_devx_obj *
1644 : 0 : mlx5_devx_cmd_create_rmp(void *ctx,
1645 : : struct mlx5_devx_create_rmp_attr *rmp_attr,
1646 : : int socket)
1647 : : {
1648 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_rmp_in)] = {0};
1649 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_rmp_out)] = {0};
1650 : : void *rmp_ctx, *wq_ctx;
1651 : : struct mlx5_devx_wq_attr *wq_attr;
1652 : : struct mlx5_devx_obj *rmp = NULL;
1653 : :
1654 : 0 : rmp = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rmp), 0, socket);
1655 [ # # ]: 0 : if (!rmp) {
1656 : 0 : DRV_LOG(ERR, "Failed to allocate RMP data");
1657 : 0 : rte_errno = ENOMEM;
1658 : 0 : return NULL;
1659 : : }
1660 [ # # ]: 0 : MLX5_SET(create_rmp_in, in, opcode, MLX5_CMD_OP_CREATE_RMP);
1661 : : rmp_ctx = MLX5_ADDR_OF(create_rmp_in, in, ctx);
1662 [ # # ]: 0 : MLX5_SET(rmpc, rmp_ctx, state, rmp_attr->state);
1663 [ # # ]: 0 : MLX5_SET(rmpc, rmp_ctx, basic_cyclic_rcv_wqe,
1664 : : rmp_attr->basic_cyclic_rcv_wqe);
1665 : : wq_ctx = MLX5_ADDR_OF(rmpc, rmp_ctx, wq);
1666 : 0 : wq_attr = &rmp_attr->wq_attr;
1667 : 0 : devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1668 : 0 : rmp->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1669 : : sizeof(out));
1670 [ # # ]: 0 : if (!rmp->obj) {
1671 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create RMP", NULL, 0);
1672 : 0 : mlx5_free(rmp);
1673 : 0 : return NULL;
1674 : : }
1675 [ # # ]: 0 : rmp->id = MLX5_GET(create_rmp_out, out, rmpn);
1676 : 0 : return rmp;
1677 : : }
1678 : :
1679 : : /*
1680 : : * Create TIR using DevX API.
1681 : : *
1682 : : * @param[in] ctx
1683 : : * Context returned from mlx5 open_device() glue function.
1684 : : * @param [in] tir_attr
1685 : : * Pointer to TIR attributes structure.
1686 : : *
1687 : : * @return
1688 : : * The DevX object created, NULL otherwise and rte_errno is set.
1689 : : */
1690 : : struct mlx5_devx_obj *
1691 : 0 : mlx5_devx_cmd_create_tir(void *ctx,
1692 : : struct mlx5_devx_tir_attr *tir_attr)
1693 : : {
1694 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
1695 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0};
1696 : : void *tir_ctx, *outer, *inner, *rss_key;
1697 : : struct mlx5_devx_obj *tir = NULL;
1698 : :
1699 : 0 : tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY);
1700 [ # # ]: 0 : if (!tir) {
1701 : 0 : DRV_LOG(ERR, "Failed to allocate TIR data");
1702 : 0 : rte_errno = ENOMEM;
1703 : 0 : return NULL;
1704 : : }
1705 [ # # ]: 0 : MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1706 : : tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx);
1707 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type);
1708 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1709 : : tir_attr->lro_timeout_period_usecs);
1710 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask);
1711 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz);
1712 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn);
1713 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric);
1714 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, tunneled_offload_en,
1715 : : tir_attr->tunneled_offload_en);
1716 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table);
1717 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1718 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1719 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain);
1720 : : rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key);
1721 [ # # ]: 0 : memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN);
1722 : : outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer);
1723 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1724 : : tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1725 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1726 : : tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1727 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, outer, selected_fields,
1728 : : tir_attr->rx_hash_field_selector_outer.selected_fields);
1729 : : inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner);
1730 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1731 : : tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1732 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1733 : : tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1734 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, inner, selected_fields,
1735 : : tir_attr->rx_hash_field_selector_inner.selected_fields);
1736 : 0 : tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1737 : : out, sizeof(out));
1738 [ # # ]: 0 : if (!tir->obj) {
1739 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create TIR", NULL, 0);
1740 : 0 : mlx5_free(tir);
1741 : 0 : return NULL;
1742 : : }
1743 [ # # ]: 0 : tir->id = MLX5_GET(create_tir_out, out, tirn);
1744 : 0 : return tir;
1745 : : }
1746 : :
1747 : : /**
1748 : : * Modify TIR using DevX API.
1749 : : *
1750 : : * @param[in] tir
1751 : : * Pointer to TIR DevX object structure.
1752 : : * @param [in] modify_tir_attr
1753 : : * Pointer to TIR modification attributes structure.
1754 : : *
1755 : : * @return
1756 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
1757 : : */
1758 : : int
1759 : 0 : mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir,
1760 : : struct mlx5_devx_modify_tir_attr *modify_tir_attr)
1761 : : {
1762 : : struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir;
1763 : 0 : uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0};
1764 : 0 : uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0};
1765 : : void *tir_ctx;
1766 : : int ret;
1767 : :
1768 : 0 : MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR);
1769 : 0 : MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn);
1770 [ # # ]: 0 : MLX5_SET64(modify_tir_in, in, modify_bitmask,
1771 : : modify_tir_attr->modify_bitmask);
1772 : : tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1773 [ # # ]: 0 : if (modify_tir_attr->modify_bitmask &
1774 : : MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) {
1775 : 0 : MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1776 : : tir_attr->lro_timeout_period_usecs);
1777 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, lro_enable_mask,
1778 : : tir_attr->lro_enable_mask);
1779 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, lro_max_msg_sz,
1780 : : tir_attr->lro_max_msg_sz);
1781 : : }
1782 [ # # ]: 0 : if (modify_tir_attr->modify_bitmask &
1783 : : MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE)
1784 : 0 : MLX5_SET(tirc, tir_ctx, indirect_table,
1785 : : tir_attr->indirect_table);
1786 [ # # ]: 0 : if (modify_tir_attr->modify_bitmask &
1787 : : MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) {
1788 : : int i;
1789 : : void *outer, *inner;
1790 : :
1791 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, rx_hash_symmetric,
1792 : : tir_attr->rx_hash_symmetric);
1793 : 0 : MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1794 [ # # ]: 0 : for (i = 0; i < 10; i++) {
1795 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i],
1796 : : tir_attr->rx_hash_toeplitz_key[i]);
1797 : : }
1798 : : outer = MLX5_ADDR_OF(tirc, tir_ctx,
1799 : : rx_hash_field_selector_outer);
1800 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1801 : : tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1802 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1803 : : tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1804 [ # # ]: 0 : MLX5_SET
1805 : : (rx_hash_field_select, outer, selected_fields,
1806 : : tir_attr->rx_hash_field_selector_outer.selected_fields);
1807 : : inner = MLX5_ADDR_OF(tirc, tir_ctx,
1808 : : rx_hash_field_selector_inner);
1809 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1810 : : tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1811 [ # # ]: 0 : MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1812 : : tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1813 [ # # ]: 0 : MLX5_SET
1814 : : (rx_hash_field_select, inner, selected_fields,
1815 : : tir_attr->rx_hash_field_selector_inner.selected_fields);
1816 : : }
1817 [ # # ]: 0 : if (modify_tir_attr->modify_bitmask &
1818 : : MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) {
1819 [ # # ]: 0 : MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1820 : : }
1821 : 0 : ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in),
1822 : : out, sizeof(out));
1823 [ # # ]: 0 : if (ret) {
1824 : 0 : DRV_LOG(ERR, "Failed to modify TIR using DevX");
1825 : 0 : rte_errno = errno;
1826 : 0 : return -errno;
1827 : : }
1828 : : return ret;
1829 : : }
1830 : :
1831 : : /**
1832 : : * Create RQT using DevX API.
1833 : : *
1834 : : * @param[in] ctx
1835 : : * Context returned from mlx5 open_device() glue function.
1836 : : * @param [in] rqt_attr
1837 : : * Pointer to RQT attributes structure.
1838 : : *
1839 : : * @return
1840 : : * The DevX object created, NULL otherwise and rte_errno is set.
1841 : : */
1842 : : struct mlx5_devx_obj *
1843 : 0 : mlx5_devx_cmd_create_rqt(void *ctx,
1844 : : struct mlx5_devx_rqt_attr *rqt_attr)
1845 : : {
1846 : : uint32_t *in = NULL;
1847 : 0 : uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) +
1848 : 0 : rqt_attr->rqt_actual_size * sizeof(uint32_t);
1849 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
1850 : : void *rqt_ctx;
1851 : : struct mlx5_devx_obj *rqt = NULL;
1852 : : unsigned int i;
1853 : :
1854 : 0 : in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1855 [ # # ]: 0 : if (!in) {
1856 : 0 : DRV_LOG(ERR, "Failed to allocate RQT IN data");
1857 : 0 : rte_errno = ENOMEM;
1858 : 0 : return NULL;
1859 : : }
1860 : 0 : rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY);
1861 [ # # ]: 0 : if (!rqt) {
1862 : 0 : DRV_LOG(ERR, "Failed to allocate RQT data");
1863 : 0 : rte_errno = ENOMEM;
1864 : 0 : mlx5_free(in);
1865 : 0 : return NULL;
1866 : : }
1867 [ # # ]: 0 : MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
1868 : 0 : rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1869 [ # # ]: 0 : MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1870 [ # # ]: 0 : MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
1871 [ # # ]: 0 : MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1872 [ # # ]: 0 : for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1873 [ # # ]: 0 : MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1874 : 0 : rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out));
1875 : 0 : mlx5_free(in);
1876 [ # # ]: 0 : if (!rqt->obj) {
1877 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create RQT", NULL, 0);
1878 : 0 : mlx5_free(rqt);
1879 : 0 : return NULL;
1880 : : }
1881 [ # # ]: 0 : rqt->id = MLX5_GET(create_rqt_out, out, rqtn);
1882 : 0 : return rqt;
1883 : : }
1884 : :
1885 : : /**
1886 : : * Modify RQT using DevX API.
1887 : : *
1888 : : * @param[in] rqt
1889 : : * Pointer to RQT DevX object structure.
1890 : : * @param [in] rqt_attr
1891 : : * Pointer to RQT attributes structure.
1892 : : *
1893 : : * @return
1894 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
1895 : : */
1896 : : int
1897 : 0 : mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
1898 : : struct mlx5_devx_rqt_attr *rqt_attr)
1899 : : {
1900 : 0 : uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) +
1901 : 0 : rqt_attr->rqt_actual_size * sizeof(uint32_t);
1902 : 0 : uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0};
1903 : 0 : uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1904 : : void *rqt_ctx;
1905 : : unsigned int i;
1906 : : int ret;
1907 : :
1908 [ # # ]: 0 : if (!in) {
1909 : 0 : DRV_LOG(ERR, "Failed to allocate RQT modify IN data.");
1910 : 0 : rte_errno = ENOMEM;
1911 : 0 : return -ENOMEM;
1912 : : }
1913 [ # # ]: 0 : MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT);
1914 [ # # ]: 0 : MLX5_SET(modify_rqt_in, in, rqtn, rqt->id);
1915 : 0 : MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1);
1916 : 0 : rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context);
1917 [ # # ]: 0 : MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1918 [ # # ]: 0 : MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1919 [ # # ]: 0 : for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1920 [ # # ]: 0 : MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1921 : 0 : ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out));
1922 : 0 : mlx5_free(in);
1923 [ # # ]: 0 : if (ret) {
1924 : 0 : DRV_LOG(ERR, "Failed to modify RQT using DevX.");
1925 : 0 : rte_errno = errno;
1926 : 0 : return -rte_errno;
1927 : : }
1928 : : return ret;
1929 : : }
1930 : :
1931 : : /**
1932 : : * Create SQ using DevX API.
1933 : : *
1934 : : * @param[in] ctx
1935 : : * Context returned from mlx5 open_device() glue function.
1936 : : * @param [in] sq_attr
1937 : : * Pointer to SQ attributes structure.
1938 : : * @param [in] socket
1939 : : * CPU socket ID for allocations.
1940 : : *
1941 : : * @return
1942 : : * The DevX object created, NULL otherwise and rte_errno is set.
1943 : : **/
1944 : : struct mlx5_devx_obj *
1945 : 0 : mlx5_devx_cmd_create_sq(void *ctx,
1946 : : struct mlx5_devx_create_sq_attr *sq_attr)
1947 : : {
1948 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0};
1949 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0};
1950 : : void *sq_ctx;
1951 : : void *wq_ctx;
1952 : : struct mlx5_devx_wq_attr *wq_attr;
1953 : : struct mlx5_devx_obj *sq = NULL;
1954 : :
1955 : 0 : sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY);
1956 [ # # ]: 0 : if (!sq) {
1957 : 0 : DRV_LOG(ERR, "Failed to allocate SQ data");
1958 : 0 : rte_errno = ENOMEM;
1959 : 0 : return NULL;
1960 : : }
1961 [ # # ]: 0 : MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ);
1962 : : sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx);
1963 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky);
1964 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master);
1965 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre);
1966 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en);
1967 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe,
1968 : : sq_attr->allow_multi_pkt_send_wqe);
1969 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode,
1970 : : sq_attr->min_wqe_inline_mode);
1971 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
1972 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr);
1973 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp);
1974 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin);
1975 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire);
1976 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq);
1977 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, hairpin_wq_buffer_type, sq_attr->hairpin_wq_buffer_type);
1978 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index);
1979 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn);
1980 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index,
1981 : : sq_attr->packet_pacing_rate_limit_index);
1982 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz);
1983 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num);
1984 [ # # ]: 0 : MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format);
1985 : : wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq);
1986 : 0 : wq_attr = &sq_attr->wq_attr;
1987 : 0 : devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1988 : 0 : sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1989 : : out, sizeof(out));
1990 [ # # ]: 0 : if (!sq->obj) {
1991 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create SQ", NULL, 0);
1992 : 0 : mlx5_free(sq);
1993 : 0 : return NULL;
1994 : : }
1995 [ # # ]: 0 : sq->id = MLX5_GET(create_sq_out, out, sqn);
1996 : 0 : return sq;
1997 : : }
1998 : :
1999 : : /**
2000 : : * Modify SQ using DevX API.
2001 : : *
2002 : : * @param[in] sq
2003 : : * Pointer to SQ object structure.
2004 : : * @param [in] sq_attr
2005 : : * Pointer to SQ attributes structure.
2006 : : *
2007 : : * @return
2008 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
2009 : : */
2010 : : int
2011 : 0 : mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
2012 : : struct mlx5_devx_modify_sq_attr *sq_attr)
2013 : : {
2014 : 0 : uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0};
2015 : 0 : uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0};
2016 : : void *sq_ctx;
2017 : : int ret;
2018 : :
2019 : 0 : MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ);
2020 : 0 : MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state);
2021 [ # # ]: 0 : MLX5_SET(modify_sq_in, in, sqn, sq->id);
2022 : : sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2023 : 0 : MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
2024 : 0 : MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq);
2025 : 0 : MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca);
2026 : 0 : ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in),
2027 : : out, sizeof(out));
2028 [ # # ]: 0 : if (ret) {
2029 : 0 : DRV_LOG(ERR, "Failed to modify SQ using DevX");
2030 : 0 : rte_errno = errno;
2031 : 0 : return -rte_errno;
2032 : : }
2033 : : return ret;
2034 : : }
2035 : :
2036 : : /*
2037 : : * Query SQ using DevX API.
2038 : : *
2039 : : * @param[in] sq_obj
2040 : : * SQ Devx Object
2041 : : * @param[out] out
2042 : : * SQ Query Output
2043 : : * @param[in] outlen
2044 : : * SQ Query Output Length
2045 : : *
2046 : : * @return
2047 : : * 0 if Query successful, else non-zero return value from devx_obj_query API
2048 : : */
2049 : : int
2050 : 0 : mlx5_devx_cmd_query_sq(struct mlx5_devx_obj *sq_obj, void *out, size_t outlen)
2051 : : {
2052 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_sq_in)] = {0};
2053 : : int rc;
2054 : :
2055 : 0 : MLX5_SET(query_sq_in, in, opcode, MLX5_CMD_OP_QUERY_SQ);
2056 : 0 : MLX5_SET(query_sq_in, in, sqn, sq_obj->id);
2057 : 0 : rc = mlx5_glue->devx_obj_query(sq_obj->obj, in, sizeof(in), out, outlen);
2058 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
2059 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "SQ query", "sq_id", sq_obj->id);
2060 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
2061 : : }
2062 : : return 0;
2063 : : }
2064 : :
2065 : : /**
2066 : : * Create TIS using DevX API.
2067 : : *
2068 : : * @param[in] ctx
2069 : : * Context returned from mlx5 open_device() glue function.
2070 : : * @param [in] tis_attr
2071 : : * Pointer to TIS attributes structure.
2072 : : *
2073 : : * @return
2074 : : * The DevX object created, NULL otherwise and rte_errno is set.
2075 : : */
2076 : : struct mlx5_devx_obj *
2077 : 0 : mlx5_devx_cmd_create_tis(void *ctx,
2078 : : struct mlx5_devx_tis_attr *tis_attr)
2079 : : {
2080 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2081 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0};
2082 : : struct mlx5_devx_obj *tis = NULL;
2083 : : void *tis_ctx;
2084 : :
2085 : 0 : tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY);
2086 [ # # ]: 0 : if (!tis) {
2087 : 0 : DRV_LOG(ERR, "Failed to allocate TIS object");
2088 : 0 : rte_errno = ENOMEM;
2089 : 0 : return NULL;
2090 : : }
2091 [ # # ]: 0 : MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS);
2092 : : tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx);
2093 [ # # ]: 0 : MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,
2094 : : tis_attr->strict_lag_tx_port_affinity);
2095 [ # # ]: 0 : MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity,
2096 : : tis_attr->lag_tx_port_affinity);
2097 [ # # ]: 0 : MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio);
2098 [ # # ]: 0 : MLX5_SET(tisc, tis_ctx, transport_domain,
2099 : : tis_attr->transport_domain);
2100 : 0 : tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2101 : : out, sizeof(out));
2102 [ # # ]: 0 : if (!tis->obj) {
2103 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create TIS", NULL, 0);
2104 : 0 : mlx5_free(tis);
2105 : 0 : return NULL;
2106 : : }
2107 [ # # ]: 0 : tis->id = MLX5_GET(create_tis_out, out, tisn);
2108 : 0 : return tis;
2109 : : }
2110 : :
2111 : : /**
2112 : : * Create transport domain using DevX API.
2113 : : *
2114 : : * @param[in] ctx
2115 : : * Context returned from mlx5 open_device() glue function.
2116 : : * @return
2117 : : * The DevX object created, NULL otherwise and rte_errno is set.
2118 : : */
2119 : : struct mlx5_devx_obj *
2120 : 0 : mlx5_devx_cmd_create_td(void *ctx)
2121 : : {
2122 : 0 : uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0};
2123 : 0 : uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0};
2124 : : struct mlx5_devx_obj *td = NULL;
2125 : :
2126 : 0 : td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY);
2127 [ # # ]: 0 : if (!td) {
2128 : 0 : DRV_LOG(ERR, "Failed to allocate TD object");
2129 : 0 : rte_errno = ENOMEM;
2130 : 0 : return NULL;
2131 : : }
2132 [ # # ]: 0 : MLX5_SET(alloc_transport_domain_in, in, opcode,
2133 : : MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN);
2134 : 0 : td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2135 : : out, sizeof(out));
2136 [ # # ]: 0 : if (!td->obj) {
2137 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create TIS", NULL, 0);
2138 : 0 : mlx5_free(td);
2139 : 0 : return NULL;
2140 : : }
2141 [ # # ]: 0 : td->id = MLX5_GET(alloc_transport_domain_out, out,
2142 : : transport_domain);
2143 : 0 : return td;
2144 : : }
2145 : :
2146 : : /**
2147 : : * Dump all flows to file.
2148 : : *
2149 : : * @param[in] fdb_domain
2150 : : * FDB domain.
2151 : : * @param[in] rx_domain
2152 : : * RX domain.
2153 : : * @param[in] tx_domain
2154 : : * TX domain.
2155 : : * @param[out] file
2156 : : * Pointer to file stream.
2157 : : *
2158 : : * @return
2159 : : * 0 on success, a negative value otherwise.
2160 : : */
2161 : : int
2162 : 0 : mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused,
2163 : : void *rx_domain __rte_unused,
2164 : : void *tx_domain __rte_unused, FILE *file __rte_unused)
2165 : : {
2166 : : int ret = 0;
2167 : :
2168 : : #ifdef HAVE_MLX5_DR_FLOW_DUMP
2169 [ # # ]: 0 : if (fdb_domain) {
2170 : 0 : ret = mlx5_glue->dr_dump_domain(file, fdb_domain);
2171 [ # # ]: 0 : if (ret)
2172 : : return ret;
2173 : : }
2174 : : MLX5_ASSERT(rx_domain);
2175 : 0 : ret = mlx5_glue->dr_dump_domain(file, rx_domain);
2176 [ # # ]: 0 : if (ret)
2177 : : return ret;
2178 : : MLX5_ASSERT(tx_domain);
2179 : 0 : ret = mlx5_glue->dr_dump_domain(file, tx_domain);
2180 : : #else
2181 : : ret = ENOTSUP;
2182 : : #endif
2183 : 0 : return -ret;
2184 : : }
2185 : :
2186 : : int
2187 : 0 : mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused,
2188 : : FILE *file __rte_unused)
2189 : : {
2190 : : int ret = 0;
2191 : : #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE
2192 [ # # ]: 0 : if (rule_info)
2193 : 0 : ret = mlx5_glue->dr_dump_rule(file, rule_info);
2194 : : #else
2195 : : ret = ENOTSUP;
2196 : : #endif
2197 : 0 : return -ret;
2198 : : }
2199 : :
2200 : : /*
2201 : : * Create CQ using DevX API.
2202 : : *
2203 : : * @param[in] ctx
2204 : : * Context returned from mlx5 open_device() glue function.
2205 : : * @param [in] attr
2206 : : * Pointer to CQ attributes structure.
2207 : : *
2208 : : * @return
2209 : : * The DevX object created, NULL otherwise and rte_errno is set.
2210 : : */
2211 : : struct mlx5_devx_obj *
2212 : 0 : mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr)
2213 : : {
2214 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0};
2215 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0};
2216 : 0 : struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO,
2217 : : sizeof(*cq_obj),
2218 : : 0, SOCKET_ID_ANY);
2219 : : void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context);
2220 : :
2221 [ # # ]: 0 : if (!cq_obj) {
2222 : 0 : DRV_LOG(ERR, "Failed to allocate CQ object memory.");
2223 : 0 : rte_errno = ENOMEM;
2224 : 0 : return NULL;
2225 : : }
2226 [ # # ]: 0 : MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ);
2227 [ # # ]: 0 : if (attr->db_umem_valid) {
2228 [ # # ]: 0 : MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid);
2229 [ # # ]: 0 : MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id);
2230 [ # # ]: 0 : MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset);
2231 : : } else {
2232 [ # # ]: 0 : MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr);
2233 : : }
2234 [ # # ]: 0 : MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ?
2235 : : MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B);
2236 [ # # ]: 0 : MLX5_SET(cqc, cqctx, cc, attr->use_first_only);
2237 [ # # ]: 0 : MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore);
2238 [ # # ]: 0 : MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size);
2239 [ # # ]: 0 : if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)
2240 [ # # ]: 0 : MLX5_SET(cqc, cqctx, log_page_size,
2241 : : attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT);
2242 [ # # ]: 0 : MLX5_SET(cqc, cqctx, c_eqn, attr->eqn);
2243 [ # # ]: 0 : MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id);
2244 [ # # ]: 0 : MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en);
2245 [ # # ]: 0 : MLX5_SET(cqc, cqctx, cqe_comp_layout, !!attr->cqe_comp_layout);
2246 [ # # ]: 0 : MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format);
2247 [ # # ]: 0 : MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext,
2248 : : attr->mini_cqe_res_format_ext);
2249 [ # # ]: 0 : if (attr->q_umem_valid) {
2250 [ # # ]: 0 : MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid);
2251 [ # # ]: 0 : MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id);
2252 [ # # ]: 0 : MLX5_SET64(create_cq_in, in, cq_umem_offset,
2253 : : attr->q_umem_offset);
2254 : : }
2255 : 0 : cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2256 : : sizeof(out));
2257 [ # # ]: 0 : if (!cq_obj->obj) {
2258 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create CQ", NULL, 0);
2259 : 0 : mlx5_free(cq_obj);
2260 : 0 : return NULL;
2261 : : }
2262 [ # # ]: 0 : cq_obj->id = MLX5_GET(create_cq_out, out, cqn);
2263 : 0 : return cq_obj;
2264 : : }
2265 : :
2266 : : /*
2267 : : * Query CQ using DevX API.
2268 : : *
2269 : : * @param[in] cq_obj
2270 : : * CQ Devx Object
2271 : : * @param[out] out
2272 : : * CQ Query Output
2273 : : * @param[in] outlen
2274 : : * CQ Query Output Length
2275 : : *
2276 : : * @return
2277 : : * 0 if Query successful, else non-zero return value from devx_obj_query API
2278 : : */
2279 : : int
2280 : 0 : mlx5_devx_cmd_query_cq(struct mlx5_devx_obj *cq_obj, void *out, size_t outlen)
2281 : : {
2282 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_cq_in)] = {0};
2283 : : int rc;
2284 : :
2285 : 0 : MLX5_SET(query_cq_in, in, opcode, MLX5_CMD_OP_QUERY_CQ);
2286 : 0 : MLX5_SET(query_cq_in, in, cqn, cq_obj->id);
2287 : 0 : rc = mlx5_glue->devx_obj_query(cq_obj->obj, in, sizeof(in), out, outlen);
2288 [ # # # # : 0 : if (rc || MLX5_FW_STATUS(out)) {
# # # # ]
2289 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "CQ query", "cq_id", cq_obj->id);
2290 [ # # ]: 0 : return MLX5_DEVX_ERR_RC(rc);
2291 : : }
2292 : : return 0;
2293 : : }
2294 : :
2295 : : /**
2296 : : * Create VIRTQ using DevX API.
2297 : : *
2298 : : * @param[in] ctx
2299 : : * Context returned from mlx5 open_device() glue function.
2300 : : * @param [in] attr
2301 : : * Pointer to VIRTQ attributes structure.
2302 : : *
2303 : : * @return
2304 : : * The DevX object created, NULL otherwise and rte_errno is set.
2305 : : */
2306 : : struct mlx5_devx_obj *
2307 : 0 : mlx5_devx_cmd_create_virtq(void *ctx,
2308 : : struct mlx5_devx_virtq_attr *attr)
2309 : : {
2310 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
2311 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2312 : 0 : struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO,
2313 : : sizeof(*virtq_obj),
2314 : : 0, SOCKET_ID_ANY);
2315 : : void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
2316 : : void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
2317 : : void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
2318 : :
2319 [ # # ]: 0 : if (!virtq_obj) {
2320 : 0 : DRV_LOG(ERR, "Failed to allocate virtq data.");
2321 : 0 : rte_errno = ENOMEM;
2322 : 0 : return NULL;
2323 : : }
2324 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2325 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2326 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2327 : : MLX5_GENERAL_OBJ_TYPE_VIRTQ);
2328 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, hw_available_index,
2329 : : attr->hw_available_index);
2330 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index);
2331 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4);
2332 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6);
2333 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum);
2334 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum);
2335 [ # # ]: 0 : MLX5_SET16(virtio_q, virtctx, virtio_version_1_0,
2336 : : attr->virtio_version_1_0);
2337 [ # # ]: 0 : MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode);
2338 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id);
2339 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr);
2340 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr);
2341 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr);
2342 [ # # ]: 0 : MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
2343 [ # # ]: 0 : MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size);
2344 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey);
2345 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id);
2346 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size);
2347 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset);
2348 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id);
2349 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size);
2350 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset);
2351 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id);
2352 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size);
2353 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset);
2354 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id);
2355 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, pd, attr->pd);
2356 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode);
2357 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us);
2358 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp);
2359 [ # # ]: 0 : MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id);
2360 : 0 : virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2361 : : sizeof(out));
2362 [ # # ]: 0 : if (!virtq_obj->obj) {
2363 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create VIRTQ", NULL, 0);
2364 : 0 : mlx5_free(virtq_obj);
2365 : 0 : return NULL;
2366 : : }
2367 [ # # ]: 0 : virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2368 : 0 : return virtq_obj;
2369 : : }
2370 : :
2371 : : /**
2372 : : * Modify VIRTQ using DevX API.
2373 : : *
2374 : : * @param[in] virtq_obj
2375 : : * Pointer to virtq object structure.
2376 : : * @param [in] attr
2377 : : * Pointer to modify virtq attributes structure.
2378 : : *
2379 : : * @return
2380 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
2381 : : */
2382 : : int
2383 : 0 : mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,
2384 : : struct mlx5_devx_virtq_attr *attr)
2385 : : {
2386 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
2387 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2388 : : void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
2389 : : void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
2390 : : void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
2391 : : int ret;
2392 : :
2393 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2394 : : MLX5_CMD_OP_MODIFY_GENERAL_OBJECT);
2395 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2396 : : MLX5_GENERAL_OBJ_TYPE_VIRTQ);
2397 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
2398 [ # # ]: 0 : MLX5_SET64(virtio_net_q, virtq, modify_field_select,
2399 : : attr->mod_fields_bitmap);
2400 : 0 : MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
2401 [ # # ]: 0 : if (!attr->mod_fields_bitmap) {
2402 : 0 : DRV_LOG(ERR, "Failed to modify VIRTQ for no type set.");
2403 : 0 : rte_errno = EINVAL;
2404 : 0 : return -rte_errno;
2405 : : }
2406 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_STATE)
2407 : 0 : MLX5_SET16(virtio_net_q, virtq, state, attr->state);
2408 [ # # ]: 0 : if (attr->mod_fields_bitmap &
2409 : : MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS) {
2410 : 0 : MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey,
2411 : : attr->dirty_bitmap_mkey);
2412 [ # # ]: 0 : MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr,
2413 : : attr->dirty_bitmap_addr);
2414 : 0 : MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size,
2415 : : attr->dirty_bitmap_size);
2416 : : }
2417 [ # # ]: 0 : if (attr->mod_fields_bitmap &
2418 : : MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE)
2419 [ # # ]: 0 : MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable,
2420 : : attr->dirty_bitmap_dump_enable);
2421 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_QUEUE_PERIOD) {
2422 : 0 : MLX5_SET(virtio_q, virtctx, queue_period_mode,
2423 : : attr->hw_latency_mode);
2424 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, queue_period_us,
2425 : : attr->hw_max_latency_us);
2426 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, queue_max_count,
2427 : : attr->hw_max_pending_comp);
2428 : : }
2429 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_ADDR) {
2430 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr);
2431 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr);
2432 [ # # ]: 0 : MLX5_SET64(virtio_q, virtctx, available_addr,
2433 : : attr->available_addr);
2434 : : }
2435 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_AVAILABLE_INDEX)
2436 : 0 : MLX5_SET16(virtio_net_q, virtq, hw_available_index,
2437 : : attr->hw_available_index);
2438 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_USED_INDEX)
2439 : 0 : MLX5_SET16(virtio_net_q, virtq, hw_used_index,
2440 : : attr->hw_used_index);
2441 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_TYPE)
2442 : 0 : MLX5_SET16(virtio_q, virtctx, virtio_q_type, attr->q_type);
2443 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_VERSION_1_0)
2444 : 0 : MLX5_SET16(virtio_q, virtctx, virtio_version_1_0,
2445 : : attr->virtio_version_1_0);
2446 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_MKEY)
2447 : 0 : MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey);
2448 [ # # ]: 0 : if (attr->mod_fields_bitmap &
2449 : : MLX5_VIRTQ_MODIFY_TYPE_QUEUE_FEATURE_BIT_MASK) {
2450 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4);
2451 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6);
2452 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum);
2453 [ # # ]: 0 : MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum);
2454 : : }
2455 [ # # ]: 0 : if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_EVENT_MODE) {
2456 [ # # ]: 0 : MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode);
2457 [ # # ]: 0 : MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id);
2458 : : }
2459 : 0 : ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in),
2460 : : out, sizeof(out));
2461 [ # # ]: 0 : if (ret) {
2462 : 0 : DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
2463 : 0 : rte_errno = errno;
2464 : 0 : return -rte_errno;
2465 : : }
2466 : : return ret;
2467 : : }
2468 : :
2469 : : /**
2470 : : * Query VIRTQ using DevX API.
2471 : : *
2472 : : * @param[in] virtq_obj
2473 : : * Pointer to virtq object structure.
2474 : : * @param [in/out] attr
2475 : : * Pointer to virtq attributes structure.
2476 : : *
2477 : : * @return
2478 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
2479 : : */
2480 : : int
2481 : 0 : mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,
2482 : : struct mlx5_devx_virtq_attr *attr)
2483 : : {
2484 : 0 : uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
2485 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0};
2486 : : void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr);
2487 : : void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq);
2488 : : int ret;
2489 : :
2490 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2491 : : MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
2492 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2493 : : MLX5_GENERAL_OBJ_TYPE_VIRTQ);
2494 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
2495 : 0 : ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in),
2496 : : out, sizeof(out));
2497 [ # # ]: 0 : if (ret) {
2498 : 0 : DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
2499 : 0 : rte_errno = errno;
2500 : 0 : return -errno;
2501 : : }
2502 [ # # ]: 0 : attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq,
2503 : : hw_available_index);
2504 [ # # ]: 0 : attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index);
2505 [ # # ]: 0 : attr->state = MLX5_GET16(virtio_net_q, virtq, state);
2506 [ # # ]: 0 : attr->error_type = MLX5_GET16(virtio_net_q, virtq,
2507 : : virtio_q_context.error_type);
2508 : 0 : return ret;
2509 : : }
2510 : :
2511 : : /**
2512 : : * Create QP using DevX API.
2513 : : *
2514 : : * @param[in] ctx
2515 : : * Context returned from mlx5 open_device() glue function.
2516 : : * @param [in] attr
2517 : : * Pointer to QP attributes structure.
2518 : : *
2519 : : * @return
2520 : : * The DevX object created, NULL otherwise and rte_errno is set.
2521 : : */
2522 : : struct mlx5_devx_obj *
2523 : 0 : mlx5_devx_cmd_create_qp(void *ctx,
2524 : : struct mlx5_devx_qp_attr *attr)
2525 : : {
2526 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0};
2527 : 0 : uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0};
2528 : 0 : struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO,
2529 : : sizeof(*qp_obj),
2530 : : 0, SOCKET_ID_ANY);
2531 : : void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
2532 : :
2533 [ # # ]: 0 : if (!qp_obj) {
2534 : 0 : DRV_LOG(ERR, "Failed to allocate QP data.");
2535 : 0 : rte_errno = ENOMEM;
2536 : 0 : return NULL;
2537 : : }
2538 [ # # ]: 0 : MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP);
2539 [ # # ]: 0 : MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC);
2540 [ # # ]: 0 : MLX5_SET(qpc, qpc, pd, attr->pd);
2541 [ # # ]: 0 : MLX5_SET(qpc, qpc, ts_format, attr->ts_format);
2542 [ # # ]: 0 : MLX5_SET(qpc, qpc, user_index, attr->user_index);
2543 [ # # ]: 0 : if (attr->uar_index) {
2544 [ # # ]: 0 : if (attr->mmo) {
2545 : : void *qpc_ext_and_pas_list = MLX5_ADDR_OF(create_qp_in,
2546 : : in, qpc_extension_and_pas_list);
2547 : : void *qpc_ext = MLX5_ADDR_OF(qpc_extension_and_pas_list,
2548 : : qpc_ext_and_pas_list, qpc_data_extension);
2549 : :
2550 [ # # ]: 0 : MLX5_SET(create_qp_in, in, qpc_ext, 1);
2551 [ # # ]: 0 : MLX5_SET(qpc_extension, qpc_ext, mmo, 1);
2552 : : }
2553 [ # # ]: 0 : MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2554 [ # # ]: 0 : MLX5_SET(qpc, qpc, uar_page, attr->uar_index);
2555 [ # # ]: 0 : if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)
2556 [ # # ]: 0 : MLX5_SET(qpc, qpc, log_page_size,
2557 : : attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT);
2558 [ # # ]: 0 : if (attr->num_of_send_wqbbs) {
2559 : : MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->num_of_send_wqbbs));
2560 [ # # ]: 0 : MLX5_SET(qpc, qpc, cqn_snd, attr->cqn);
2561 [ # # ]: 0 : MLX5_SET(qpc, qpc, log_sq_size,
2562 : : rte_log2_u32(attr->num_of_send_wqbbs));
2563 : : } else {
2564 [ # # ]: 0 : MLX5_SET(qpc, qpc, no_sq, 1);
2565 : : }
2566 [ # # ]: 0 : if (attr->num_of_receive_wqes) {
2567 : : MLX5_ASSERT(RTE_IS_POWER_OF_2(
2568 : : attr->num_of_receive_wqes));
2569 [ # # ]: 0 : MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn);
2570 [ # # ]: 0 : MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride -
2571 : : MLX5_LOG_RQ_STRIDE_SHIFT);
2572 [ # # # # ]: 0 : MLX5_SET(qpc, qpc, log_rq_size,
2573 : : rte_log2_u32(attr->num_of_receive_wqes));
2574 [ # # ]: 0 : MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ);
2575 : : } else {
2576 [ # # ]: 0 : MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
2577 : : }
2578 [ # # ]: 0 : if (attr->dbr_umem_valid) {
2579 [ # # ]: 0 : MLX5_SET(qpc, qpc, dbr_umem_valid,
2580 : : attr->dbr_umem_valid);
2581 [ # # ]: 0 : MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id);
2582 : : }
2583 [ # # ]: 0 : if (attr->cd_master)
2584 [ # # ]: 0 : MLX5_SET(qpc, qpc, cd_master, attr->cd_master);
2585 [ # # ]: 0 : if (attr->cd_slave_send)
2586 [ # # ]: 0 : MLX5_SET(qpc, qpc, cd_slave_send, attr->cd_slave_send);
2587 [ # # ]: 0 : if (attr->cd_slave_recv)
2588 [ # # ]: 0 : MLX5_SET(qpc, qpc, cd_slave_receive, attr->cd_slave_recv);
2589 [ # # ]: 0 : MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address);
2590 [ # # ]: 0 : MLX5_SET64(create_qp_in, in, wq_umem_offset,
2591 : : attr->wq_umem_offset);
2592 [ # # ]: 0 : MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id);
2593 [ # # ]: 0 : MLX5_SET(create_qp_in, in, wq_umem_valid, 1);
2594 : : } else {
2595 : : /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */
2596 [ # # ]: 0 : MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
2597 [ # # ]: 0 : MLX5_SET(qpc, qpc, no_sq, 1);
2598 : : }
2599 : 0 : qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2600 : : sizeof(out));
2601 [ # # ]: 0 : if (!qp_obj->obj) {
2602 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create QP", NULL, 0);
2603 : 0 : mlx5_free(qp_obj);
2604 : 0 : return NULL;
2605 : : }
2606 [ # # ]: 0 : qp_obj->id = MLX5_GET(create_qp_out, out, qpn);
2607 : 0 : return qp_obj;
2608 : : }
2609 : :
2610 : : /**
2611 : : * Modify QP using DevX API.
2612 : : * Currently supports only force loop-back QP.
2613 : : *
2614 : : * @param[in] qp
2615 : : * Pointer to QP object structure.
2616 : : * @param [in] qp_st_mod_op
2617 : : * The QP state modification operation.
2618 : : * @param [in] remote_qp_id
2619 : : * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation.
2620 : : *
2621 : : * @return
2622 : : * 0 on success, a negative errno value otherwise and rte_errno is set.
2623 : : */
2624 : : int
2625 : 0 : mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op,
2626 : : uint32_t remote_qp_id)
2627 : : {
2628 : : union {
2629 : : uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)];
2630 : : uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)];
2631 : : uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)];
2632 : : uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_in)];
2633 : : } in;
2634 : : union {
2635 : : uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)];
2636 : : uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)];
2637 : : uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)];
2638 : : uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_out)];
2639 : : } out;
2640 : : void *qpc;
2641 : : int ret;
2642 : : unsigned int inlen;
2643 : : unsigned int outlen;
2644 : :
2645 : : memset(&in, 0, sizeof(in));
2646 : : memset(&out, 0, sizeof(out));
2647 : 0 : MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op);
2648 [ # # # # : 0 : switch (qp_st_mod_op) {
# ]
2649 : 0 : case MLX5_CMD_OP_RST2INIT_QP:
2650 : 0 : MLX5_SET(rst2init_qp_in, &in, qpn, qp->id);
2651 : : qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc);
2652 : 0 : MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
2653 : : MLX5_SET(qpc, qpc, rre, 1);
2654 [ # # ]: 0 : MLX5_SET(qpc, qpc, rwe, 1);
2655 : 0 : MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2656 : : inlen = sizeof(in.rst2init);
2657 : : outlen = sizeof(out.rst2init);
2658 : 0 : break;
2659 : 0 : case MLX5_CMD_OP_INIT2RTR_QP:
2660 : 0 : MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id);
2661 : : qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc);
2662 : 0 : MLX5_SET(qpc, qpc, primary_address_path.fl, 1);
2663 : 0 : MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
2664 : : MLX5_SET(qpc, qpc, mtu, 1);
2665 [ # # ]: 0 : MLX5_SET(qpc, qpc, log_msg_max, 30);
2666 : 0 : MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id);
2667 : 0 : MLX5_SET(qpc, qpc, min_rnr_nak, 0);
2668 : : inlen = sizeof(in.init2rtr);
2669 : : outlen = sizeof(out.init2rtr);
2670 : 0 : break;
2671 : 0 : case MLX5_CMD_OP_RTR2RTS_QP:
2672 : : qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc);
2673 : 0 : MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id);
2674 : 0 : MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 16);
2675 : : MLX5_SET(qpc, qpc, log_ack_req_freq, 0);
2676 [ # # ]: 0 : MLX5_SET(qpc, qpc, retry_count, 7);
2677 [ # # ]: 0 : MLX5_SET(qpc, qpc, rnr_retry, 7);
2678 : : inlen = sizeof(in.rtr2rts);
2679 : : outlen = sizeof(out.rtr2rts);
2680 : 0 : break;
2681 : 0 : case MLX5_CMD_OP_QP_2RST:
2682 : 0 : MLX5_SET(2rst_qp_in, &in, qpn, qp->id);
2683 : : inlen = sizeof(in.qp2rst);
2684 : : outlen = sizeof(out.qp2rst);
2685 : 0 : break;
2686 : 0 : default:
2687 : 0 : DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.",
2688 : : qp_st_mod_op);
2689 : 0 : rte_errno = EINVAL;
2690 : 0 : return -rte_errno;
2691 : : }
2692 : 0 : ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen);
2693 [ # # ]: 0 : if (ret) {
2694 : 0 : DRV_LOG(ERR, "Failed to modify QP using DevX.");
2695 : 0 : rte_errno = errno;
2696 : 0 : return -rte_errno;
2697 : : }
2698 : : return ret;
2699 : : }
2700 : :
2701 : : struct mlx5_devx_obj *
2702 : 0 : mlx5_devx_cmd_create_virtio_q_counters(void *ctx)
2703 : : {
2704 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0};
2705 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2706 : 0 : struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO,
2707 : : sizeof(*couners_obj), 0,
2708 : : SOCKET_ID_ANY);
2709 : : void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr);
2710 : :
2711 [ # # ]: 0 : if (!couners_obj) {
2712 : 0 : DRV_LOG(ERR, "Failed to allocate virtio queue counters data.");
2713 : 0 : rte_errno = ENOMEM;
2714 : 0 : return NULL;
2715 : : }
2716 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2717 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2718 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2719 : : MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
2720 : 0 : couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2721 : : sizeof(out));
2722 [ # # ]: 0 : if (!couners_obj->obj) {
2723 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create virtio queue counters Obj", NULL,
2724 : : 0);
2725 : 0 : mlx5_free(couners_obj);
2726 : 0 : return NULL;
2727 : : }
2728 [ # # ]: 0 : couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2729 : 0 : return couners_obj;
2730 : : }
2731 : :
2732 : : int
2733 : 0 : mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,
2734 : : struct mlx5_devx_virtio_q_couners_attr *attr)
2735 : : {
2736 : 0 : uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
2737 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0};
2738 : : void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr);
2739 : : void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out,
2740 : : virtio_q_counters);
2741 : : int ret;
2742 : :
2743 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2744 : : MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
2745 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2746 : : MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
2747 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id);
2748 : 0 : ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out,
2749 : : sizeof(out));
2750 [ # # ]: 0 : if (ret) {
2751 : 0 : DRV_LOG(ERR, "Failed to query virtio q counters using DevX.");
2752 : 0 : rte_errno = errno;
2753 : 0 : return -errno;
2754 : : }
2755 [ # # ]: 0 : attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
2756 : : received_desc);
2757 [ # # ]: 0 : attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
2758 : : completed_desc);
2759 [ # # ]: 0 : attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters,
2760 : : error_cqes);
2761 [ # # ]: 0 : attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters,
2762 : : bad_desc_errors);
2763 [ # # ]: 0 : attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters,
2764 : : exceed_max_chain);
2765 [ # # ]: 0 : attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters,
2766 : : invalid_buffer);
2767 : 0 : return ret;
2768 : : }
2769 : :
2770 : : /**
2771 : : * Create general object of type FLOW_HIT_ASO using DevX API.
2772 : : *
2773 : : * @param[in] ctx
2774 : : * Context returned from mlx5 open_device() glue function.
2775 : : * @param [in] pd
2776 : : * PD value to associate the FLOW_HIT_ASO object with.
2777 : : *
2778 : : * @return
2779 : : * The DevX object created, NULL otherwise and rte_errno is set.
2780 : : */
2781 : : struct mlx5_devx_obj *
2782 : 0 : mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd)
2783 : : {
2784 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0};
2785 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2786 : : struct mlx5_devx_obj *flow_hit_aso_obj = NULL;
2787 : : void *ptr = NULL;
2788 : :
2789 : 0 : flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj),
2790 : : 0, SOCKET_ID_ANY);
2791 [ # # ]: 0 : if (!flow_hit_aso_obj) {
2792 : 0 : DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data");
2793 : 0 : rte_errno = ENOMEM;
2794 : 0 : return NULL;
2795 : : }
2796 : : ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr);
2797 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2798 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2799 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2800 : : MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO);
2801 : : ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso);
2802 [ # # ]: 0 : MLX5_SET(flow_hit_aso, ptr, access_pd, pd);
2803 : 0 : flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2804 : : out, sizeof(out));
2805 [ # # ]: 0 : if (!flow_hit_aso_obj->obj) {
2806 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create FLOW_HIT_ASO", NULL, 0);
2807 : 0 : mlx5_free(flow_hit_aso_obj);
2808 : 0 : return NULL;
2809 : : }
2810 [ # # ]: 0 : flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2811 : 0 : return flow_hit_aso_obj;
2812 : : }
2813 : :
2814 : : /*
2815 : : * Create PD using DevX API.
2816 : : *
2817 : : * @param[in] ctx
2818 : : * Context returned from mlx5 open_device() glue function.
2819 : : *
2820 : : * @return
2821 : : * The DevX object created, NULL otherwise and rte_errno is set.
2822 : : */
2823 : : struct mlx5_devx_obj *
2824 : 0 : mlx5_devx_cmd_alloc_pd(void *ctx)
2825 : : {
2826 : : struct mlx5_devx_obj *ppd =
2827 : 0 : mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY);
2828 : 0 : u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0};
2829 : 0 : u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0};
2830 : :
2831 [ # # ]: 0 : if (!ppd) {
2832 : 0 : DRV_LOG(ERR, "Failed to allocate PD data.");
2833 : 0 : rte_errno = ENOMEM;
2834 : 0 : return NULL;
2835 : : }
2836 : 0 : MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2837 : 0 : ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2838 : : out, sizeof(out));
2839 [ # # ]: 0 : if (!ppd->obj) {
2840 : 0 : mlx5_free(ppd);
2841 : 0 : DRV_LOG(ERR, "Failed to allocate PD Obj using DevX.");
2842 : 0 : rte_errno = errno;
2843 : 0 : return NULL;
2844 : : }
2845 [ # # ]: 0 : ppd->id = MLX5_GET(alloc_pd_out, out, pd);
2846 : 0 : return ppd;
2847 : : }
2848 : :
2849 : : /**
2850 : : * Create general object of type FLOW_METER_ASO using DevX API.
2851 : : *
2852 : : * @param[in] ctx
2853 : : * Context returned from mlx5 open_device() glue function.
2854 : : * @param [in] pd
2855 : : * PD value to associate the FLOW_METER_ASO object with.
2856 : : * @param [in] log_obj_size
2857 : : * log_obj_size define to allocate number of 2 * meters
2858 : : * in one FLOW_METER_ASO object.
2859 : : *
2860 : : * @return
2861 : : * The DevX object created, NULL otherwise and rte_errno is set.
2862 : : */
2863 : : struct mlx5_devx_obj *
2864 : 0 : mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd,
2865 : : uint32_t log_obj_size)
2866 : : {
2867 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0};
2868 : : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
2869 : : struct mlx5_devx_obj *flow_meter_aso_obj;
2870 : : void *ptr;
2871 : :
2872 : 0 : flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO,
2873 : : sizeof(*flow_meter_aso_obj),
2874 : : 0, SOCKET_ID_ANY);
2875 [ # # ]: 0 : if (!flow_meter_aso_obj) {
2876 : 0 : DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data");
2877 : 0 : rte_errno = ENOMEM;
2878 : 0 : return NULL;
2879 : : }
2880 : : ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr);
2881 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2882 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2883 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2884 : : MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO);
2885 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range,
2886 : : log_obj_size);
2887 : : ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso);
2888 [ # # ]: 0 : MLX5_SET(flow_meter_aso, ptr, access_pd, pd);
2889 : 0 : flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create(
2890 : : ctx, in, sizeof(in),
2891 : : out, sizeof(out));
2892 [ # # ]: 0 : if (!flow_meter_aso_obj->obj) {
2893 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create FLOW_METTER_ASO", NULL, 0);
2894 : 0 : mlx5_free(flow_meter_aso_obj);
2895 : 0 : return NULL;
2896 : : }
2897 [ # # ]: 0 : flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr,
2898 : : out, obj_id);
2899 : 0 : return flow_meter_aso_obj;
2900 : : }
2901 : :
2902 : : /*
2903 : : * Create general object of type CONN_TRACK_OFFLOAD using DevX API.
2904 : : *
2905 : : * @param[in] ctx
2906 : : * Context returned from mlx5 open_device() glue function.
2907 : : * @param [in] pd
2908 : : * PD value to associate the CONN_TRACK_OFFLOAD ASO object with.
2909 : : * @param [in] log_obj_size
2910 : : * log_obj_size to allocate its power of 2 * objects
2911 : : * in one CONN_TRACK_OFFLOAD bulk allocation.
2912 : : *
2913 : : * @return
2914 : : * The DevX object created, NULL otherwise and rte_errno is set.
2915 : : */
2916 : : struct mlx5_devx_obj *
2917 : 0 : mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, uint32_t pd,
2918 : : uint32_t log_obj_size)
2919 : : {
2920 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_conn_track_aso_in)] = {0};
2921 : : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
2922 : : struct mlx5_devx_obj *ct_aso_obj;
2923 : : void *ptr;
2924 : :
2925 : 0 : ct_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ct_aso_obj),
2926 : : 0, SOCKET_ID_ANY);
2927 [ # # ]: 0 : if (!ct_aso_obj) {
2928 : 0 : DRV_LOG(ERR, "Failed to allocate CONN_TRACK_OFFLOAD object.");
2929 : 0 : rte_errno = ENOMEM;
2930 : 0 : return NULL;
2931 : : }
2932 : : ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, hdr);
2933 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2934 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2935 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2936 : : MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD);
2937 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, log_obj_size);
2938 : : ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, conn_track_offload);
2939 [ # # ]: 0 : MLX5_SET(conn_track_offload, ptr, conn_track_aso_access_pd, pd);
2940 : 0 : ct_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2941 : : out, sizeof(out));
2942 [ # # ]: 0 : if (!ct_aso_obj->obj) {
2943 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create CONN_TRACK_OFFLOAD", NULL, 0);
2944 : 0 : mlx5_free(ct_aso_obj);
2945 : 0 : return NULL;
2946 : : }
2947 [ # # ]: 0 : ct_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2948 : 0 : return ct_aso_obj;
2949 : : }
2950 : :
2951 : : /**
2952 : : * Create general object of type GENEVE TLV option using DevX API.
2953 : : *
2954 : : * @param[in] ctx
2955 : : * Context returned from mlx5 open_device() glue function.
2956 : : * @param[in] attr
2957 : : * Pointer to GENEVE TLV option attributes structure.
2958 : : *
2959 : : * @return
2960 : : * The DevX object created, NULL otherwise and rte_errno is set.
2961 : : */
2962 : : struct mlx5_devx_obj *
2963 : 0 : mlx5_devx_cmd_create_geneve_tlv_option(void *ctx,
2964 : : struct mlx5_devx_geneve_tlv_option_attr *attr)
2965 : : {
2966 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0};
2967 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2968 : 0 : struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO,
2969 : : sizeof(*geneve_tlv_opt_obj),
2970 : : 0, SOCKET_ID_ANY);
2971 : :
2972 [ # # ]: 0 : if (!geneve_tlv_opt_obj) {
2973 : 0 : DRV_LOG(ERR, "Failed to allocate GENEVE TLV option object.");
2974 : 0 : rte_errno = ENOMEM;
2975 : 0 : return NULL;
2976 : : }
2977 : : void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr);
2978 : : void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in,
2979 : : geneve_tlv_opt);
2980 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2981 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2982 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2983 : : MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT);
2984 [ # # ]: 0 : MLX5_SET(geneve_tlv_option, opt, option_type, attr->option_type);
2985 [ # # ]: 0 : MLX5_SET(geneve_tlv_option, opt, option_data_length,
2986 : : attr->option_data_len);
2987 [ # # ]: 0 : if (attr->option_class_ignore)
2988 [ # # ]: 0 : MLX5_SET(geneve_tlv_option, opt, option_class_ignore,
2989 : : attr->option_class_ignore);
2990 : : else
2991 [ # # # # ]: 0 : MLX5_SET(geneve_tlv_option, opt, option_class,
2992 : : rte_be_to_cpu_16(attr->option_class));
2993 [ # # ]: 0 : if (attr->offset_valid) {
2994 [ # # ]: 0 : MLX5_SET(geneve_tlv_option, opt, sample_offset_valid,
2995 : : attr->offset_valid);
2996 [ # # ]: 0 : MLX5_SET(geneve_tlv_option, opt, sample_offset,
2997 : : attr->sample_offset);
2998 : : }
2999 : 0 : geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in,
3000 : : sizeof(in), out,
3001 : : sizeof(out));
3002 [ # # ]: 0 : if (!geneve_tlv_opt_obj->obj) {
3003 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create GENEVE TLV option", NULL, 0);
3004 : 0 : mlx5_free(geneve_tlv_opt_obj);
3005 : 0 : return NULL;
3006 : : }
3007 [ # # ]: 0 : geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
3008 : 0 : return geneve_tlv_opt_obj;
3009 : : }
3010 : :
3011 : : /**
3012 : : * Query GENEVE TLV option using DevX API.
3013 : : *
3014 : : * @param[in] ctx
3015 : : * Context used to create GENEVE TLV option object.
3016 : : * @param[in] geneve_tlv_opt_obj
3017 : : * DevX object of the GENEVE TLV option.
3018 : : * @param[out] attr
3019 : : * Pointer to match sample info attributes structure.
3020 : : *
3021 : : * @return
3022 : : * 0 on success, a negative errno otherwise and rte_errno is set.
3023 : : */
3024 : : int
3025 : 0 : mlx5_devx_cmd_query_geneve_tlv_option(void *ctx,
3026 : : struct mlx5_devx_obj *geneve_tlv_opt_obj,
3027 : : struct mlx5_devx_match_sample_info_query_attr *attr)
3028 : : {
3029 : 0 : uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
3030 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_geneve_tlv_option_out)] = {0};
3031 : : void *hdr = MLX5_ADDR_OF(query_geneve_tlv_option_out, in, hdr);
3032 : : void *opt = MLX5_ADDR_OF(query_geneve_tlv_option_out, out,
3033 : : geneve_tlv_opt);
3034 : : int ret;
3035 : :
3036 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
3037 : : MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
3038 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
3039 : : MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT);
3040 : 0 : MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, geneve_tlv_opt_obj->id);
3041 : : /* Call first query to get sample handle. */
3042 : 0 : ret = mlx5_glue->devx_obj_query(geneve_tlv_opt_obj->obj, in, sizeof(in),
3043 : : out, sizeof(out));
3044 [ # # ]: 0 : if (ret) {
3045 : 0 : DRV_LOG(ERR, "Failed to query GENEVE TLV option using DevX.");
3046 : 0 : rte_errno = errno;
3047 : 0 : return -errno;
3048 : : }
3049 : : /* Call second query to get sample information. */
3050 [ # # # # ]: 0 : if (MLX5_GET(geneve_tlv_option, opt, sample_id_valid)) {
3051 [ # # ]: 0 : uint32_t sample_id = MLX5_GET(geneve_tlv_option, opt,
3052 : : geneve_sample_field_id);
3053 : :
3054 : 0 : return mlx5_devx_cmd_match_sample_info_query(ctx, sample_id,
3055 : : attr);
3056 : : }
3057 : 0 : DRV_LOG(DEBUG, "GENEVE TLV option sample isn't valid.");
3058 : 0 : return 0;
3059 : : }
3060 : :
3061 : : int
3062 : 0 : mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id)
3063 : : {
3064 : : #ifdef HAVE_IBV_FLOW_DV_SUPPORT
3065 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0};
3066 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0};
3067 : : int rc;
3068 : : void *rq_ctx;
3069 : :
3070 : 0 : MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ);
3071 : 0 : MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num);
3072 : 0 : rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out));
3073 [ # # ]: 0 : if (rc) {
3074 : 0 : rte_errno = errno;
3075 : 0 : DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - "
3076 : : "rc = %d, errno = %d.", rc, errno);
3077 : 0 : return -rc;
3078 : : };
3079 : : rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context);
3080 [ # # ]: 0 : *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id);
3081 : 0 : return 0;
3082 : : #else
3083 : : (void)wq;
3084 : : (void)counter_set_id;
3085 : : return -ENOTSUP;
3086 : : #endif
3087 : : }
3088 : :
3089 : : /*
3090 : : * Allocate queue counters via devx interface.
3091 : : *
3092 : : * @param[in] ctx
3093 : : * Context returned from mlx5 open_device() glue function.
3094 : : * @param[out] syndrome
3095 : : * Get syndrome of devx command response.
3096 : : *
3097 : : * @return
3098 : : * Pointer to counter object on success, a NULL value otherwise and
3099 : : * rte_errno is set.
3100 : : */
3101 : : struct mlx5_devx_obj *
3102 : 0 : mlx5_devx_cmd_queue_counter_alloc(void *ctx, int *syndrome)
3103 : : {
3104 : : int status;
3105 : 0 : struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0,
3106 : : SOCKET_ID_ANY);
3107 : 0 : uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {0};
3108 : 0 : uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0};
3109 : :
3110 [ # # ]: 0 : if (!dcs) {
3111 : 0 : rte_errno = ENOMEM;
3112 : 0 : return NULL;
3113 : : }
3114 : 0 : MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
3115 : 0 : dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
3116 : : sizeof(out));
3117 [ # # ]: 0 : if (!dcs->obj) {
3118 [ # # # # ]: 0 : DEVX_DRV_LOG(DEBUG, out, "create q counter set", NULL, 0);
3119 [ # # ]: 0 : status = MLX5_GET(alloc_q_counter_out, out, status);
3120 [ # # ]: 0 : if (status && syndrome)
3121 [ # # ]: 0 : *syndrome = MLX5_GET(alloc_q_counter_out, out, syndrome);
3122 : 0 : mlx5_free(dcs);
3123 : 0 : return NULL;
3124 : : }
3125 [ # # ]: 0 : dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id);
3126 : 0 : return dcs;
3127 : : }
3128 : :
3129 : : /**
3130 : : * Query queue counters values.
3131 : : *
3132 : : * @param[in] dcs
3133 : : * devx object of the queue counter set.
3134 : : * @param[in] clear
3135 : : * Whether hardware should clear the counters after the query or not.
3136 : : * @param[out] out_of_buffers
3137 : : * Number of dropped occurred due to lack of WQE for the associated QPs/RQs.
3138 : : *
3139 : : * @return
3140 : : * 0 on success, a negative value otherwise.
3141 : : */
3142 : : int
3143 : 0 : mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear,
3144 : : uint32_t *out_of_buffers)
3145 : : {
3146 : 0 : uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0};
3147 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0};
3148 : : int rc;
3149 : :
3150 : 0 : MLX5_SET(query_q_counter_in, in, opcode,
3151 : : MLX5_CMD_OP_QUERY_Q_COUNTER);
3152 : 0 : MLX5_SET(query_q_counter_in, in, op_mod, 0);
3153 : 0 : MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id);
3154 : 0 : MLX5_SET(query_q_counter_in, in, clear, !!clear);
3155 : 0 : rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
3156 : : sizeof(out));
3157 [ # # ]: 0 : if (rc) {
3158 : 0 : DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc);
3159 : 0 : rte_errno = rc;
3160 : 0 : return -rc;
3161 : : }
3162 [ # # ]: 0 : *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer);
3163 : 0 : return 0;
3164 : : }
3165 : :
3166 : : /**
3167 : : * Create general object of type DEK using DevX API.
3168 : : *
3169 : : * @param[in] ctx
3170 : : * Context returned from mlx5 open_device() glue function.
3171 : : * @param [in] attr
3172 : : * Pointer to DEK attributes structure.
3173 : : *
3174 : : * @return
3175 : : * The DevX object created, NULL otherwise and rte_errno is set.
3176 : : */
3177 : : struct mlx5_devx_obj *
3178 : 0 : mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr)
3179 : : {
3180 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0};
3181 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
3182 : : struct mlx5_devx_obj *dek_obj = NULL;
3183 : : void *ptr = NULL, *key_addr = NULL;
3184 : :
3185 : 0 : dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj),
3186 : : 0, SOCKET_ID_ANY);
3187 [ # # ]: 0 : if (dek_obj == NULL) {
3188 : 0 : DRV_LOG(ERR, "Failed to allocate DEK object data");
3189 : 0 : rte_errno = ENOMEM;
3190 : 0 : return NULL;
3191 : : }
3192 : : ptr = MLX5_ADDR_OF(create_dek_in, in, hdr);
3193 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
3194 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
3195 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
3196 : : MLX5_GENERAL_OBJ_TYPE_DEK);
3197 : : ptr = MLX5_ADDR_OF(create_dek_in, in, dek);
3198 [ # # ]: 0 : MLX5_SET(dek, ptr, key_size, attr->key_size);
3199 [ # # ]: 0 : MLX5_SET(dek, ptr, has_keytag, attr->has_keytag);
3200 [ # # ]: 0 : MLX5_SET(dek, ptr, key_purpose, attr->key_purpose);
3201 [ # # ]: 0 : MLX5_SET(dek, ptr, pd, attr->pd);
3202 [ # # ]: 0 : MLX5_SET64(dek, ptr, opaque, attr->opaque);
3203 : : key_addr = MLX5_ADDR_OF(dek, ptr, key);
3204 : 0 : memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE);
3205 : 0 : dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
3206 : : out, sizeof(out));
3207 [ # # ]: 0 : if (dek_obj->obj == NULL) {
3208 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create DEK", NULL, 0);
3209 : 0 : mlx5_free(dek_obj);
3210 : 0 : return NULL;
3211 : : }
3212 [ # # ]: 0 : dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
3213 : 0 : return dek_obj;
3214 : : }
3215 : :
3216 : : /**
3217 : : * Create general object of type IMPORT_KEK using DevX API.
3218 : : *
3219 : : * @param[in] ctx
3220 : : * Context returned from mlx5 open_device() glue function.
3221 : : * @param [in] attr
3222 : : * Pointer to IMPORT_KEK attributes structure.
3223 : : *
3224 : : * @return
3225 : : * The DevX object created, NULL otherwise and rte_errno is set.
3226 : : */
3227 : : struct mlx5_devx_obj *
3228 : 0 : mlx5_devx_cmd_create_import_kek_obj(void *ctx,
3229 : : struct mlx5_devx_import_kek_attr *attr)
3230 : : {
3231 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_import_kek_in)] = {0};
3232 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
3233 : : struct mlx5_devx_obj *import_kek_obj = NULL;
3234 : : void *ptr = NULL, *key_addr = NULL;
3235 : :
3236 : 0 : import_kek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*import_kek_obj),
3237 : : 0, SOCKET_ID_ANY);
3238 [ # # ]: 0 : if (import_kek_obj == NULL) {
3239 : 0 : DRV_LOG(ERR, "Failed to allocate IMPORT_KEK object data");
3240 : 0 : rte_errno = ENOMEM;
3241 : 0 : return NULL;
3242 : : }
3243 : : ptr = MLX5_ADDR_OF(create_import_kek_in, in, hdr);
3244 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
3245 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
3246 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
3247 : : MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK);
3248 : : ptr = MLX5_ADDR_OF(create_import_kek_in, in, import_kek);
3249 [ # # ]: 0 : MLX5_SET(import_kek, ptr, key_size, attr->key_size);
3250 : : key_addr = MLX5_ADDR_OF(import_kek, ptr, key);
3251 : 0 : memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE);
3252 : 0 : import_kek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
3253 : : out, sizeof(out));
3254 [ # # ]: 0 : if (import_kek_obj->obj == NULL) {
3255 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create IMPORT_KEK", NULL, 0);
3256 : 0 : mlx5_free(import_kek_obj);
3257 : 0 : return NULL;
3258 : : }
3259 [ # # ]: 0 : import_kek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
3260 : 0 : return import_kek_obj;
3261 : : }
3262 : :
3263 : : /**
3264 : : * Create general object of type CREDENTIAL using DevX API.
3265 : : *
3266 : : * @param[in] ctx
3267 : : * Context returned from mlx5 open_device() glue function.
3268 : : * @param [in] attr
3269 : : * Pointer to CREDENTIAL attributes structure.
3270 : : *
3271 : : * @return
3272 : : * The DevX object created, NULL otherwise and rte_errno is set.
3273 : : */
3274 : : struct mlx5_devx_obj *
3275 : 0 : mlx5_devx_cmd_create_credential_obj(void *ctx,
3276 : : struct mlx5_devx_credential_attr *attr)
3277 : : {
3278 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_credential_in)] = {0};
3279 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
3280 : : struct mlx5_devx_obj *credential_obj = NULL;
3281 : : void *ptr = NULL, *credential_addr = NULL;
3282 : :
3283 : 0 : credential_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*credential_obj),
3284 : : 0, SOCKET_ID_ANY);
3285 [ # # ]: 0 : if (credential_obj == NULL) {
3286 : 0 : DRV_LOG(ERR, "Failed to allocate CREDENTIAL object data");
3287 : 0 : rte_errno = ENOMEM;
3288 : 0 : return NULL;
3289 : : }
3290 : : ptr = MLX5_ADDR_OF(create_credential_in, in, hdr);
3291 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
3292 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
3293 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
3294 : : MLX5_GENERAL_OBJ_TYPE_CREDENTIAL);
3295 : : ptr = MLX5_ADDR_OF(create_credential_in, in, credential);
3296 [ # # ]: 0 : MLX5_SET(credential, ptr, credential_role, attr->credential_role);
3297 : : credential_addr = MLX5_ADDR_OF(credential, ptr, credential);
3298 : 0 : memcpy(credential_addr, (void *)(attr->credential),
3299 : : MLX5_CRYPTO_CREDENTIAL_SIZE);
3300 : 0 : credential_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
3301 : : out, sizeof(out));
3302 [ # # ]: 0 : if (credential_obj->obj == NULL) {
3303 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create CREDENTIAL", NULL, 0);
3304 : 0 : mlx5_free(credential_obj);
3305 : 0 : return NULL;
3306 : : }
3307 [ # # ]: 0 : credential_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
3308 : 0 : return credential_obj;
3309 : : }
3310 : :
3311 : : /**
3312 : : * Create general object of type CRYPTO_LOGIN using DevX API.
3313 : : *
3314 : : * @param[in] ctx
3315 : : * Context returned from mlx5 open_device() glue function.
3316 : : * @param [in] attr
3317 : : * Pointer to CRYPTO_LOGIN attributes structure.
3318 : : *
3319 : : * @return
3320 : : * The DevX object created, NULL otherwise and rte_errno is set.
3321 : : */
3322 : : struct mlx5_devx_obj *
3323 : 0 : mlx5_devx_cmd_create_crypto_login_obj(void *ctx,
3324 : : struct mlx5_devx_crypto_login_attr *attr)
3325 : : {
3326 : 0 : uint32_t in[MLX5_ST_SZ_DW(create_crypto_login_in)] = {0};
3327 : 0 : uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
3328 : : struct mlx5_devx_obj *crypto_login_obj = NULL;
3329 : : void *ptr = NULL, *credential_addr = NULL;
3330 : :
3331 : 0 : crypto_login_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*crypto_login_obj),
3332 : : 0, SOCKET_ID_ANY);
3333 [ # # ]: 0 : if (crypto_login_obj == NULL) {
3334 : 0 : DRV_LOG(ERR, "Failed to allocate CRYPTO_LOGIN object data");
3335 : 0 : rte_errno = ENOMEM;
3336 : 0 : return NULL;
3337 : : }
3338 : : ptr = MLX5_ADDR_OF(create_crypto_login_in, in, hdr);
3339 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
3340 : : MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
3341 [ # # ]: 0 : MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
3342 : : MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN);
3343 : : ptr = MLX5_ADDR_OF(create_crypto_login_in, in, crypto_login);
3344 [ # # ]: 0 : MLX5_SET(crypto_login, ptr, credential_pointer,
3345 : : attr->credential_pointer);
3346 [ # # ]: 0 : MLX5_SET(crypto_login, ptr, session_import_kek_ptr,
3347 : : attr->session_import_kek_ptr);
3348 : : credential_addr = MLX5_ADDR_OF(crypto_login, ptr, credential);
3349 : 0 : memcpy(credential_addr, (void *)(attr->credential),
3350 : : MLX5_CRYPTO_CREDENTIAL_SIZE);
3351 : 0 : crypto_login_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
3352 : : out, sizeof(out));
3353 [ # # ]: 0 : if (crypto_login_obj->obj == NULL) {
3354 [ # # # # ]: 0 : DEVX_DRV_LOG(ERR, out, "create CRYPTO_LOGIN", NULL, 0);
3355 : 0 : mlx5_free(crypto_login_obj);
3356 : 0 : return NULL;
3357 : : }
3358 [ # # ]: 0 : crypto_login_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
3359 : 0 : return crypto_login_obj;
3360 : : }
3361 : :
3362 : : /**
3363 : : * Query LAG context.
3364 : : *
3365 : : * @param[in] ctx
3366 : : * Pointer to ibv_context, returned from mlx5dv_open_device.
3367 : : * @param[out] lag_ctx
3368 : : * Pointer to struct mlx5_devx_lag_context, to be set by the routine.
3369 : : *
3370 : : * @return
3371 : : * 0 on success, a negative value otherwise.
3372 : : */
3373 : : int
3374 : 0 : mlx5_devx_cmd_query_lag(void *ctx,
3375 : : struct mlx5_devx_lag_context *lag_ctx)
3376 : : {
3377 : 0 : uint32_t in[MLX5_ST_SZ_DW(query_lag_in)] = {0};
3378 : 0 : uint32_t out[MLX5_ST_SZ_DW(query_lag_out)] = {0};
3379 : : void *lctx;
3380 : : int rc;
3381 : :
3382 : 0 : MLX5_SET(query_lag_in, in, opcode, MLX5_CMD_OP_QUERY_LAG);
3383 : 0 : rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
3384 [ # # ]: 0 : if (rc)
3385 : 0 : goto error;
3386 : : lctx = MLX5_ADDR_OF(query_lag_out, out, context);
3387 [ # # ]: 0 : lag_ctx->fdb_selection_mode = MLX5_GET(lag_context, lctx,
3388 : : fdb_selection_mode);
3389 [ # # ]: 0 : lag_ctx->port_select_mode = MLX5_GET(lag_context, lctx,
3390 : : port_select_mode);
3391 [ # # ]: 0 : lag_ctx->lag_state = MLX5_GET(lag_context, lctx, lag_state);
3392 [ # # ]: 0 : lag_ctx->tx_remap_affinity_2 = MLX5_GET(lag_context, lctx,
3393 : : tx_remap_affinity_2);
3394 [ # # ]: 0 : lag_ctx->tx_remap_affinity_1 = MLX5_GET(lag_context, lctx,
3395 : : tx_remap_affinity_1);
3396 : 0 : return 0;
3397 : : error:
3398 : 0 : rc = (rc > 0) ? -rc : rc;
3399 : 0 : return rc;
3400 : : }
|
