Branch data Line data Source code
1 : : /* SPDX-License-Identifier: BSD-3-Clause
2 : : * Copyright(c) 2024 Realtek Corporation. All rights reserved
3 : : */
4 : :
5 : : #include "../r8169_ethdev.h"
6 : : #include "../r8169_hw.h"
7 : : #include "../r8169_phy.h"
8 : : #include "rtl8126a_mcu.h"
9 : :
10 : : /* For RTL8126A, CFG_METHOD_69,70,71 */
11 : :
12 : : static void
13 : 0 : hw_init_rxcfg_8126a(struct rtl_hw *hw)
14 : : {
15 [ # # # ]: 0 : switch (hw->mcfg) {
16 : 0 : case CFG_METHOD_69:
17 : 0 : RTL_W32(hw, RxConfig, Rx_Fetch_Number_8 | RxCfg_pause_slot_en |
18 : : (RX_DMA_BURST_512 << RxCfgDMAShift));
19 : : break;
20 : 0 : case CFG_METHOD_70:
21 : : case CFG_METHOD_71:
22 : 0 : RTL_W32(hw, RxConfig, Rx_Fetch_Number_8 | Rx_Close_Multiple |
23 : : RxCfg_pause_slot_en | (RX_DMA_BURST_512 << RxCfgDMAShift));
24 : : break;
25 : : }
26 : 0 : }
27 : :
28 : : static void
29 : 0 : hw_ephy_config_8126a(struct rtl_hw *hw)
30 : : {
31 : : switch (hw->mcfg) {
32 : : case CFG_METHOD_69 ... CFG_METHOD_71:
33 : : /* nothing to do */
34 : : break;
35 : : }
36 : 0 : }
37 : :
38 : : static void
39 : : rtl_hw_phy_config_8126a_1(struct rtl_hw *hw)
40 : : {
41 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA442, BIT_11);
42 : :
43 : 0 : RTL_W16(hw, EEE_TXIDLE_TIMER_8125, hw->mtu + RTE_ETHER_HDR_LEN + 0x20);
44 : 0 : }
45 : :
46 : : static void
47 : 0 : rtl_hw_phy_config_8126a_2(struct rtl_hw *hw)
48 : : {
49 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA442, BIT_11);
50 : :
51 : 0 : RTL_W16(hw, EEE_TXIDLE_TIMER_8125, hw->mtu + RTE_ETHER_HDR_LEN + 0x20);
52 : :
53 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80BF);
54 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xED00);
55 : :
56 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80CD);
57 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x1000);
58 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80D1);
59 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xC800);
60 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80D4);
61 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0xC800);
62 : :
63 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80E1);
64 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x10CC);
65 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80E5);
66 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x4F0C);
67 : :
68 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8387);
69 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x4700);
70 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA80C, (BIT_7 | BIT_6), BIT_7);
71 : :
72 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xAC90, BIT_4);
73 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xAD2C, BIT_15);
74 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8321);
75 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x1100);
76 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xACF8, (BIT_3 | BIT_2));
77 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8183);
78 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x5900);
79 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xAD94, BIT_5);
80 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xA654, BIT_11);
81 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xB648, BIT_14);
82 : :
83 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x839E);
84 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x2F00);
85 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x83F2);
86 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0800);
87 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xADA0, BIT_1);
88 : :
89 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x80F3);
90 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x9900);
91 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8126);
92 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0xC100);
93 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x893A);
94 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x8080);
95 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8647);
96 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0xE600);
97 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x862C);
98 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x1200);
99 : :
100 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x864A);
101 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0xE600);
102 : :
103 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x80A0);
104 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0xBCBC);
105 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x805E);
106 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0xBCBC);
107 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8056);
108 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x3077);
109 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8058);
110 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x5A00);
111 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8098);
112 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x3077);
113 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x809A);
114 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x5A00);
115 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8052);
116 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x3733);
117 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8094);
118 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x3733);
119 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x807F);
120 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x7C75);
121 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x803D);
122 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x7C75);
123 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8036);
124 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x3000);
125 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8078);
126 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x3000);
127 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8031);
128 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x3300);
129 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8073);
130 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x3300);
131 : :
132 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAE06, 0xFC00, 0x7C00);
133 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x89D1);
134 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0004);
135 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8FBD);
136 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x0A00);
137 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8FBE);
138 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0D09);
139 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x89CD);
140 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0F0F);
141 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x89CF);
142 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0F0F);
143 : :
144 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x83A4);
145 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x6600);
146 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x83A6);
147 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x6601);
148 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x83C0);
149 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x6600);
150 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x83C2);
151 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x6601);
152 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8414);
153 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x6600);
154 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8416);
155 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x6601);
156 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x83F8);
157 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x6600);
158 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x83FA);
159 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x6601);
160 : :
161 : 0 : rtl_set_phy_mcu_patch_request(hw);
162 : :
163 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBD96, 0x1F00, 0x1000);
164 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBF1C, 0x0007, 0x0007);
165 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xBFBE, BIT_15);
166 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBF40, 0x0380, 0x0280);
167 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBF90, BIT_7, (BIT_6 | BIT_5));
168 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xBF90, BIT_4, (BIT_3 | BIT_2));
169 : 0 : rtl_clear_phy_mcu_patch_request(hw);
170 : :
171 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x843B);
172 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x2000);
173 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x843D);
174 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x2000);
175 : :
176 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xB516, 0x7F);
177 : :
178 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xBF80, (BIT_5 | BIT_4));
179 : :
180 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8188);
181 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0044);
182 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00A8);
183 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00D6);
184 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00EC);
185 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00F6);
186 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00FC);
187 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00FE);
188 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00FE);
189 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00BC);
190 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0058);
191 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x002A);
192 : :
193 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8015);
194 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0800);
195 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FFD);
196 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0000);
197 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FFF);
198 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x7F00);
199 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FFB);
200 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
201 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FE9);
202 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0002);
203 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FEF);
204 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x00A5);
205 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FF1);
206 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0106);
207 : :
208 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FE1);
209 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0102);
210 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FE3);
211 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0400);
212 : :
213 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA654, BIT_11);
214 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0XA65A, (BIT_1 | BIT_0));
215 : :
216 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xAC3A, 0x5851);
217 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0XAC3C, (BIT_15 | BIT_14 | BIT_12),
218 : : BIT_13);
219 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAC42, BIT_9, (BIT_8 | BIT_7 | BIT_6));
220 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xAC3E, (BIT_15 | BIT_14 | BIT_13));
221 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xAC42, (BIT_5 | BIT_4 | BIT_3));
222 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAC42, BIT_1, (BIT_2 | BIT_0));
223 : :
224 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xAC1A, 0x00DB);
225 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xADE4, 0x01B5);
226 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xAD9C, (BIT_11 | BIT_10));
227 : :
228 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x814B);
229 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x1100);
230 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x814D);
231 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x1100);
232 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x814F);
233 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0B00);
234 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8142);
235 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
236 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8144);
237 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
238 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8150);
239 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
240 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8118);
241 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0700);
242 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x811A);
243 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0700);
244 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x811C);
245 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0500);
246 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x810F);
247 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
248 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8111);
249 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
250 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x811D);
251 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
252 : :
253 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xAC36, BIT_12);
254 : 0 : rtl_clear_eth_phy_ocp_bit(hw, 0xAD1C, BIT_8);
255 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xADE8, 0xFFC0, 0x1400);
256 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x864B);
257 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x9D00);
258 : :
259 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8F97);
260 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x003F);
261 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x3F02);
262 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x023C);
263 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x3B0A);
264 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1C00);
265 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
266 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
267 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
268 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
269 : :
270 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xAD9C, BIT_5);
271 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8122);
272 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0C00);
273 : :
274 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x82C8);
275 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03ED);
276 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03FF);
277 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0009);
278 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03FE);
279 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x000B);
280 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0021);
281 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03F7);
282 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03B8);
283 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03E0);
284 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0049);
285 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0049);
286 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03E0);
287 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03B8);
288 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03F7);
289 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0021);
290 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x000B);
291 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03FE);
292 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0009);
293 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03FF);
294 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03ED);
295 : :
296 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x80EF);
297 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0C00);
298 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x82A0);
299 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x000E);
300 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03FE);
301 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03ED);
302 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0006);
303 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x001A);
304 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03F1);
305 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03D8);
306 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0023);
307 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0054);
308 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0322);
309 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x00DD);
310 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03AB);
311 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03DC);
312 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0027);
313 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x000E);
314 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03E5);
315 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03F9);
316 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0012);
317 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0001);
318 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03F1);
319 : :
320 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8018);
321 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA438, BIT_13);
322 : :
323 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FE4);
324 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0000);
325 : :
326 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB54C, 0xFFC0, 0x3700);
327 : 0 : }
328 : :
329 : : static void
330 : 0 : rtl_hw_phy_config_8126a_3(struct rtl_hw *hw)
331 : : {
332 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA442, BIT_11);
333 : :
334 : 0 : RTL_W16(hw, EEE_TXIDLE_TIMER_8125, hw->mtu + RTE_ETHER_HDR_LEN + 0x20);
335 : :
336 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8183);
337 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x5900);
338 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA654, BIT_11);
339 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xB648, BIT_14);
340 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xAD2C, BIT_15);
341 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xAD94, BIT_5);
342 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xADA0, BIT_1);
343 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xAE06, (BIT_15 | BIT_14 |
344 : : BIT_13 | BIT_12 | BIT_11 | BIT_10),
345 : : (BIT_14 | BIT_13 | BIT_12 | BIT_11 | BIT_10));
346 : :
347 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8647);
348 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0xE600);
349 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8036);
350 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x3000);
351 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8078);
352 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x3000);
353 : :
354 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x89E9);
355 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00);
356 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FFD);
357 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
358 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FFE);
359 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0200);
360 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8FFF);
361 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0400);
362 : :
363 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8018);
364 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x7700);
365 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8F9C);
366 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0005);
367 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
368 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x00ED);
369 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0502);
370 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0B00);
371 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xD401);
372 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8FA8);
373 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xA438, 0xFF00, 0x2900);
374 : :
375 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x814B);
376 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x1100);
377 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x814D);
378 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x1100);
379 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x814F);
380 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0B00);
381 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8142);
382 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
383 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8144);
384 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
385 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8150);
386 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
387 : :
388 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8118);
389 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0700);
390 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x811A);
391 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0700);
392 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x811C);
393 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0500);
394 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x810F);
395 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
396 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8111);
397 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
398 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x811D);
399 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0100);
400 : :
401 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xAD1C, BIT_8);
402 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xADE8, (BIT_15 | BIT_14 |
403 : : BIT_13 | BIT_12 | BIT_11 | BIT_10 |
404 : : BIT_9 | BIT_8 | BIT_7 | BIT_6),
405 : : (BIT_12 | BIT_10));
406 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x864B);
407 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x9D00);
408 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x862C);
409 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x1200);
410 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x8566);
411 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x003F);
412 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x3F02);
413 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x023C);
414 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x3B0A);
415 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x1C00);
416 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
417 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
418 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
419 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0x0000);
420 : :
421 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xAD9C, BIT_5);
422 : :
423 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x8122);
424 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0C00);
425 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x82C8);
426 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03ED);
427 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03FF);
428 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0009);
429 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03FE);
430 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x000B);
431 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0021);
432 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03F7);
433 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03B8);
434 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03E0);
435 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0049);
436 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0049);
437 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03E0);
438 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03B8);
439 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03F7);
440 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0021);
441 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x000B);
442 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03FE);
443 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0009);
444 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03FF);
445 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03ED);
446 : :
447 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x80EF);
448 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB87E, 0xFF00, 0x0C00);
449 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87C, 0x82A0);
450 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x000E);
451 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03FE);
452 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03ED);
453 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0006);
454 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x001A);
455 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03F1);
456 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03D8);
457 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0023);
458 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0054);
459 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0322);
460 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x00DD);
461 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03AB);
462 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03DC);
463 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0027);
464 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x000E);
465 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03E5);
466 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03F9);
467 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0012);
468 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x0001);
469 : 0 : rtl_mdio_direct_write_phy_ocp(hw, 0xB87E, 0x03F1);
470 : :
471 : 0 : rtl_set_eth_phy_ocp_bit(hw, 0xA430, (BIT_1 | BIT_0));
472 : :
473 : 0 : rtl_clear_and_set_eth_phy_ocp_bit(hw, 0xB54C, 0xFFC0, 0x3700);
474 : 0 : }
475 : :
476 : : static void
477 : 0 : hw_phy_config_8126a(struct rtl_hw *hw)
478 : : {
479 [ # # # # ]: 0 : switch (hw->mcfg) {
480 : : case CFG_METHOD_69:
481 : : rtl_hw_phy_config_8126a_1(hw);
482 : : break;
483 : 0 : case CFG_METHOD_70:
484 : 0 : rtl_hw_phy_config_8126a_2(hw);
485 : 0 : break;
486 : 0 : case CFG_METHOD_71:
487 : 0 : rtl_hw_phy_config_8126a_3(hw);
488 : 0 : break;
489 : : }
490 : 0 : }
491 : :
492 : : static void
493 : 0 : hw_mac_mcu_config_8126a(struct rtl_hw *hw)
494 : : {
495 [ # # ]: 0 : if (hw->NotWrMcuPatchCode)
496 : : return;
497 : :
498 [ # # # # ]: 0 : switch (hw->mcfg) {
499 : 0 : case CFG_METHOD_69:
500 : 0 : rtl_set_mac_mcu_8126a_1(hw);
501 : 0 : break;
502 : 0 : case CFG_METHOD_70:
503 : 0 : rtl_set_mac_mcu_8126a_2(hw);
504 : 0 : break;
505 : 0 : case CFG_METHOD_71:
506 : 0 : rtl_set_mac_mcu_8126a_3(hw);
507 : 0 : break;
508 : : }
509 : : }
510 : :
511 : : static void
512 : 0 : hw_phy_mcu_config_8126a(struct rtl_hw *hw)
513 : : {
514 [ # # # # ]: 0 : switch (hw->mcfg) {
515 : 0 : case CFG_METHOD_69:
516 : 0 : rtl_set_phy_mcu_8126a_1(hw);
517 : 0 : break;
518 : 0 : case CFG_METHOD_70:
519 : 0 : rtl_set_phy_mcu_8126a_2(hw);
520 : 0 : break;
521 : 0 : case CFG_METHOD_71:
522 : 0 : rtl_set_phy_mcu_8126a_3(hw);
523 : 0 : break;
524 : : }
525 : 0 : }
526 : :
527 : : const struct rtl_hw_ops rtl8126a_ops = {
528 : : .hw_init_rxcfg = hw_init_rxcfg_8126a,
529 : : .hw_ephy_config = hw_ephy_config_8126a,
530 : : .hw_phy_config = hw_phy_config_8126a,
531 : : .hw_mac_mcu_config = hw_mac_mcu_config_8126a,
532 : : .hw_phy_mcu_config = hw_phy_mcu_config_8126a,
533 : : };
|
